char *tmp, *end;
char mac[16];
const char *path;
- unsigned char mac_addr[6];
+ unsigned char mac_addr[ARP_HLEN];
int offset;
if (fdt_path_offset(fdt, "/aliases") < 0)
{
struct node_info *ni = node_info;
struct mtd_device *dev;
- char *parts;
int i, idx;
int noff;
- parts = getenv("mtdparts");
- if (!parts)
- return;
-
if (mtdparts_init() != 0)
return;
pdata->iobase = dev_get_addr(dev);
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
}
pdata->max_speed = 0;
- cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL);
+ cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
if (cell)
pdata->max_speed = fdt32_to_cpu(*cell);
#ifdef CONFIG_DM_GPIO
- if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"snps,reset-active-low"))
reset_flags |= GPIOD_ACTIVE_LOW;
ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
&priv->reset_gpio, reset_flags);
if (ret == 0) {
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"snps,reset-delays-us", dw_pdata->reset_delays, 3);
} else if (ret == -ENOENT) {
ret = 0;
{ .compatible = "allwinner,sun7i-a20-gmac" },
{ .compatible = "altr,socfpga-stmmac" },
{ .compatible = "amlogic,meson6-dwmac" },
+ { .compatible = "amlogic,meson-gx-dwmac" },
{ .compatible = "st,stm32-dwmac" },
{ }
};
}
fec_reg_setup(priv);
- fec_set_dev_name((char *)dev->name, dev_id);
priv->dev_id = (dev_id == -1) ? 0 : dev_id;
return 0;
priv->eth = (struct ethernet_regs *)pdata->iobase;
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+ #include <clk.h>
#include <dm.h>
/*
struct mii_dev *bus;
#ifdef CONFIG_DM_ETH
+ unsigned long pclk_rate;
phy_interface_t phy_interface;
#endif
};
static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
{
u32 config;
+ #ifdef CONFIG_DM_ETH
+ unsigned long macb_hz = macb->pclk_rate;
+ #else
unsigned long macb_hz = get_macb_pclk_rate(id);
+ #endif
if (macb_hz < 20000000)
config = MACB_BF(CLK, MACB_CLK_DIV8);
static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
{
u32 config;
+
+ #ifdef CONFIG_DM_ETH
+ unsigned long macb_hz = macb->pclk_rate;
+ #else
unsigned long macb_hz = get_macb_pclk_rate(id);
+ #endif
if (macb_hz < 20000000)
config = GEM_BF(CLK, GEM_CLK_DIV8);
.write_hwaddr = macb_write_hwaddr,
};
+ static int macb_enable_clk(struct udevice *dev)
+ {
+ struct macb_device *macb = dev_get_priv(dev);
+ struct clk clk;
+ ulong clk_rate;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return -EINVAL;
+
+ ret = clk_enable(&clk);
+ if (ret)
+ return ret;
+
+ clk_rate = clk_get_rate(&clk);
+ if (!clk_rate)
+ return -EINVAL;
+
+ macb->pclk_rate = clk_rate;
+
+ return 0;
+ }
+
static int macb_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct macb_device *macb = dev_get_priv(dev);
-
- #ifdef CONFIG_DM_ETH
const char *phy_mode;
+ int ret;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
macb->phy_interface = phy_get_interface_by_name(phy_mode);
if (macb->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
- #endif
macb->regs = (void *)pdata->iobase;
+ ret = macb_enable_clk(dev);
+ if (ret)
+ return ret;
+
_macb_eth_initialize(macb);
+
#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
int retval;
struct mii_dev *mdiodev = mdio_alloc();
/* Extended Registers */
#define DP83867_RGMIICTL 0x0032
#define DP83867_RGMIIDCTL 0x0086
+ #define DP83867_IO_MUX_CFG 0x0170
#define DP83867_SW_RESET BIT(15)
#define DP83867_SW_RESTART BIT(14)
#define DEFAULT_TX_ID_DELAY DP83867_RGMIIDCTL_2_75_NS
#define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
+ /* IO_MUX_CFG bits */
+ #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
+
+ #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
+ #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
+
struct dp83867_private {
int rx_id_delay;
int tx_id_delay;
int fifo_depth;
+ int io_impedance;
};
/**
{
struct dp83867_private *dp83867 = phydev->priv;
struct udevice *dev = phydev->dev;
+ int node = dev->of_offset;
+ const void *fdt = gd->fdt_blob;
+
+ if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
+ dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
+ else if (fdtdec_get_bool(fdt, node, "ti,min-output-impedance"))
+ dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
+ else
+ dp83867->io_impedance = -EINVAL;
- dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,rx-internal-delay", -1);
- dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,tx-internal-delay", -1);
- dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,fifo-depth", -1);
return 0;
dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
+ dp83867->io_impedance = -EINVAL;
return 0;
}
phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
}
- if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
- (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
+ if (phy_interface_is_rgmii(phydev)) {
val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
DP83867_DEVADDR, phydev->addr);
phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
DP83867_DEVADDR, phydev->addr, delay);
+
+ if (dp83867->io_impedance >= 0) {
+ val = phy_read_mmd_indirect(phydev,
+ DP83867_IO_MUX_CFG,
+ DP83867_DEVADDR,
+ phydev->addr);
+ val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
+ val |= dp83867->io_impedance &
+ DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
+ phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
+ DP83867_DEVADDR, phydev->addr,
+ val);
+ }
}
genphy_config_aneg(phydev);
hostprogs-$(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER) += atmel_pmecc_params
-hostprogs-$(CONFIG_CMD_LICENSE) += bin2header
hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo
hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo
HOSTCFLAGS_bmp_logo.o := -pedantic
hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr
HOSTCFLAGS_gen_eth_addr.o := -pedantic
+ hostprogs-$(CONFIG_CMD_NET) += gen_ethaddr_crc
+ gen_ethaddr_crc-objs := gen_ethaddr_crc.o lib/crc8.o
+ HOSTCFLAGS_gen_ethaddr_crc.o := -pedantic
+
hostprogs-$(CONFIG_CMD_LOADS) += img2srec
HOSTCFLAGS_img2srec.o := -pedantic
# that won't build on some weird host compiler -- though there are lots of
# exceptions for files that aren't complaint.
HOSTCFLAGS_crc32.o := -pedantic
+ HOSTCFLAGS_crc8.o := -pedantic
HOSTCFLAGS_md5.o := -pedantic
HOSTCFLAGS_sha1.o := -pedantic
HOSTCFLAGS_sha256.o := -pedantic
endif # !LOGO_BMP
-# Generated gziped GPL-2.0 license text
-LICENSE_H = $(objtree)/include/license.h
-LICENSE-$(CONFIG_CMD_LICENSE) += $(LICENSE_H)
-
#
# Use native tools and options
# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
-D__KERNEL_STRICT_NAMES \
-D_GNU_SOURCE
-__build: $(LOGO-y) $(LICENSE-y)
+__build: $(LOGO-y)
$(LOGO_H): $(obj)/bmp_logo $(LOGO_BMP)
$(obj)/bmp_logo --gen-info $(LOGO_BMP) > $@
$(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP)
$(obj)/bmp_logo --gen-data $(LOGO_BMP) > $@
-$(LICENSE_H): $(obj)/bin2header $(srctree)/Licenses/gpl-2.0.txt
- cat $(srctree)/Licenses/gpl-2.0.txt | gzip -9 -c | \
- $(obj)/bin2header license_gzip > $(LICENSE_H)
-
# Let clean descend into subdirs
subdir- += env
projects / u-boot / commitdiff