]> git.sur5r.net Git - u-boot/commitdiff
* Temporarily disabled John Kerl's extended MII command code because
authorwdenk <wdenk>
Sun, 18 Apr 2004 23:32:11 +0000 (23:32 +0000)
committerwdenk <wdenk>
Sun, 18 Apr 2004 23:32:11 +0000 (23:32 +0000)
  "miivals.h" is missing

* Patches by Mark Jonas, 13 Apr 2004:
  - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S
  - Add sync instructions to IceCube SDRAM init code
  - Move SDRAM chip constants into seperate include files
  - Unify DDR and SDR initialization code
  - Unify all IceCube (Lite5xxx) target names

CHANGELOG
MAKEALL
Makefile
board/icecube/icecube.c
board/icecube/mt46v16m16-75.h [new file with mode: 0644]
board/icecube/mt48lc16m16a2-75.h [new file with mode: 0644]
board/utx8245/utx8245.c
common/cmd_mii.c
cpu/mpc5xxx/start.S
doc/README.IceCube
drivers/serial_xuartlite.c

index 1420fd138e9fbc10ca98e9afefe2df6c6d0e25d1..f4112df90092857ba39e541b4cb1998ae2bc8f55 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,16 @@
 Changes for U-Boot 1.1.1:
 ======================================================================
 
+* Temporarily disabled John Kerl's extended MII command code because
+  "miivals.h" is missing
+
+* Patches by Mark Jonas, 13 Apr 2004:
+  - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S
+  - Add sync instructions to IceCube SDRAM init code
+  - Move SDRAM chip constants into seperate include files
+  - Unify DDR and SDR initialization code
+  - Unify all IceCube (Lite5xxx) target names
+
 * Patch by John Kerl, 16 Apr 2004:
   Enable ranges in mii command, e.g. mii read 0-1f 0 or
   mii read 4-7 18-1a.  Also add mii dump subcommand for
diff --git a/MAKEALL b/MAKEALL
index b241057c9cbdcdccaaf07aaf36a3b831f69a3860..d0dd2235c354de3fa4194e3018ceec09d8f97381 100644 (file)
--- a/MAKEALL
+++ b/MAKEALL
@@ -25,7 +25,7 @@ LIST_5xx="    \
 #########################################################################
 
 LIST_5xxx="    \
-       IceCube_5100    IceCube_5200    EVAL5200        PM520           \
+       icecube_5100    icecube_5200    EVAL5200        PM520           \
 "
 
 #########################################################################
index 0287765c79f74830222368696d87022678b3f228..3eb1758a979e47fd327ffc88d8f6b6dc176fa0aa 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -212,16 +212,16 @@ PATI_config:              unconfig
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
-MPC5200LITE_config             \
-MPC5200LITE_LOWBOOT_config     \
-MPC5200LITE_LOWBOOT08_config   \
-icecube_5200_DDR_config                \
-IceCube_5200_DDR_config                \
-icecube_5200_DDR_LOWBOOT_config \
-icecube_5200_DDR_LOWBOOT08_config \
-icecube_5200_config            \
-IceCube_5200_config            \
-IceCube_5100_config:           unconfig
+Lite5200_config                                \
+Lite5200_LOWBOOT_config                        \
+Lite5200_LOWBOOT08_config              \
+icecube_5200_config                    \
+icecube_5200_LOWBOOT_config            \
+icecube_5200_LOWBOOT08_config          \
+icecube_5200_DDR_config                \
+icecube_5200_DDR_LOWBOOT_config        \
+icecube_5200_DDR_LOWBOOT08_config      \
+icecube_5100_config:                   unconfig
        @ >include/config.h
        @[ -z "$(findstring LOWBOOT_,$@)" ] || \
                { if [ "$(findstring DDR,$@)" ] ; \
index e40bcdf4bccc3e6ca5fcc73595960babbaf11a64..5a206c0f4853251386a0b01a2e0fc2f6fb5990ab 100644 (file)
@@ -2,6 +2,9 @@
  * (C) Copyright 2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
 #include <mpc5xxx.h>
 #include <pci.h>
 
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
 #ifndef CFG_RAMBOOT
 static void sdram_start (int hi_addr)
 {
        long hi_addr_bit = hi_addr ? 0x01000000 : 0;
 
-#ifdef CONFIG_MPC5200_DDR
        /* unlock mode register */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f00 | hi_addr_bit;
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+       __asm__ volatile ("sync");
+       
        /* precharge all banks */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+       __asm__ volatile ("sync");
+
+#if SDRAM_DDR
        /* set mode register: extended mode */
-       *(vu_long *)MPC5XXX_SDRAM_MODE = 0x40090000;
+       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+       __asm__ volatile ("sync");
+
        /* set mode register: reset DLL */
-       *(vu_long *)MPC5XXX_SDRAM_MODE = 0x058d0000;
-       /* precharge all banks */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
-       /* auto refresh */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f04 | hi_addr_bit;
-       /* set mode register */
-       *(vu_long *)MPC5XXX_SDRAM_MODE = 0x018d0000;
-       /* normal operation */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x705f0f00 | hi_addr_bit;
-#else
-       /* unlock mode register */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
-       /* precharge all banks */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
-       /* set mode register */
-#if defined(CONFIG_MPC5200)
-       *(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000;
-#elif defined(CONFIG_MGT5100)
-       *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
+       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+       __asm__ volatile ("sync");
 #endif
+
+       /* precharge all banks */
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+       __asm__ volatile ("sync");
+
        /* auto refresh */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
-       /* auto refresh */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+       __asm__ volatile ("sync");
+
        /* set mode register */
-       *(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000;
+       *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+       __asm__ volatile ("sync");
+       
        /* normal operation */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
-#endif
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+       __asm__ volatile ("sync");
 }
 #endif
 
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
 long int initdram (int board_type)
 {
        ulong dramsize = 0;
-#ifdef CONFIG_MPC5200_DDR
        ulong dramsize2 = 0;
-#endif
 #ifndef CFG_RAMBOOT
        ulong test1, test2;
-
-       /* configure SDRAM start/end */
-#if defined(CONFIG_MPC5200)
+       
+       /* setup SDRAM chip selects */
        *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
        *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+       __asm__ volatile ("sync");
 
-#ifdef CONFIG_MPC5200_DDR
        /* setup config registers */
-       *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0x73722930;
-       *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x47770000;
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+       __asm__ volatile ("sync");
 
-       /* set tap delay to 0x10 */
-       *(vu_long *)MPC5XXX_CDM_PORCFG = 0x10000000;
-#else
-       /* setup config registers */
-       *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xd2322800;
-       *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x8ad70000;
+#if SDRAM_DDR
+       /* set tap delay */
+       *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+       __asm__ volatile ("sync");
 #endif
 
-#elif defined(CONFIG_MGT5100)
-       *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-       *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-       *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-
-       /* setup config registers */
-       *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
-       *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
-
-       /* address select register */
-       *(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
-#endif
+       /* find RAM size using SDRAM CS0 only */
        sdram_start(0);
        test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
        sdram_start(1);
@@ -119,11 +116,24 @@ long int initdram (int board_type)
        } else {
                dramsize = test2;
        }
-#if defined(CONFIG_MPC5200)
-       *(vu_long *)MPC5XXX_SDRAM_CS0CFG =
-               (0x13 + __builtin_ffs(dramsize >> 20) - 1);
-#ifdef CONFIG_MPC5200_DDR
+
+       /* memory smaller than 1MB is impossible */
+       if (dramsize < (1 << 20)) {
+               dramsize = 0;
+       }
+       
+       /* set SDRAM CS0 size according to the amount of RAM found */
+       if (dramsize > 0) {
+               *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+       } else {
+               *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+       }
+
+       
+       /* let SDRAM CS1 start right after CS0 */
        *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+       /* find RAM size using SDRAM CS1 only */
        sdram_start(0);
        test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
        sdram_start(1);
@@ -134,34 +144,94 @@ long int initdram (int board_type)
        } else {
                dramsize2 = test2;
        }
-       *(vu_long *)MPC5XXX_SDRAM_CS1CFG =
-               dramsize + (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-#else
-       *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-#endif
+       
+       /* memory smaller than 1MB is impossible */
+       if (dramsize2 < (1 << 20)) {
+               dramsize2 = 0;
+       }
+       
+       /* set SDRAM CS1 size according to the amount of RAM found */
+       if (dramsize2 > 0) {
+               *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+                       | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+       } else {
+               *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+       }
+
+#else /* CFG_RAMBOOT */
+
+       /* retrieve size of memory connected to SDRAM CS0 */
+       dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+       if (dramsize >= 0x13) {
+               dramsize = (1 << (dramsize - 0x13)) << 20;
+       } else {
+               dramsize = 0;
+       }
+
+       /* retrieve size of memory connected to SDRAM CS1 */
+       dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+       if (dramsize2 >= 0x13) {
+               dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+       } else {
+               dramsize2 = 0;
+       }
+
+#endif /* CFG_RAMBOOT */
+
+       return dramsize + dramsize2;
+}
+
 #elif defined(CONFIG_MGT5100)
-       *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-#endif
 
-#else  /* CFG_RAMBOOT */
-#ifdef CONFIG_MGT5100
+long int initdram (int board_type)
+{
+       ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+       ulong test1, test2;
+       
+       /* setup and enable SDRAM chip selects */
+       *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+       *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
        *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+       __asm__ volatile ("sync");
+
+       /* setup config registers */
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+       /* address select register */
+       *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+       __asm__ volatile ("sync");
+
+       /* find RAM size */
+       sdram_start(0);
+       test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+       sdram_start(1);
+       test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+       if (test1 > test2) {
+               sdram_start(0);
+               dramsize = test1;
+       } else {
+               dramsize = test2;
+       }
+
+       /* set SDRAM end address according to size */
+       *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+       
+#else /* CFG_RAMBOOT */
+
+       /* Retrieve amount of SDRAM available */
        dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-#else
-       dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
-#ifdef CONFIG_MPC5200_DDR
-       dramsize2 = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20);
-#endif
-#endif
+
 #endif /* CFG_RAMBOOT */
 
-#ifdef CONFIG_MPC5200_DDR
-       dramsize += dramsize2;
-#endif
-       /* return total ram size */
        return dramsize;
 }
 
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
 int checkboard (void)
 {
 #if defined(CONFIG_MPC5200)
diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h
new file mode 100644 (file)
index 0000000..4c0f9a7
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR      1               /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE     0x018D0000
+#define SDRAM_EMODE    0x40090000
+#define SDRAM_CONTROL  0x705f0f00
+#define SDRAM_CONFIG1  0x73722930
+#define SDRAM_CONFIG2  0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h
new file mode 100644 (file)
index 0000000..ffdf039
--- /dev/null
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR      0               /* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE     0x00CD0000
+#define SDRAM_CONTROL  0x504F0000
+#define SDRAM_CONFIG1  0xD2322800
+#define SDRAM_CONFIG2  0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE     0x008D0000
+#define SDRAM_CONTROL  0x504F0000
+#define SDRAM_CONFIG1  0xC2222600
+#define SDRAM_CONFIG2  0x88B70004
+#define SDRAM_ADDRSEL  0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
index d870c9fcd84951315bedbbc90b665a9b9f1e8a7c..834fd84079b2eb05313c987adf3774d421bf8b72 100644 (file)
@@ -67,7 +67,7 @@ long int initdram(int board_type)
        emear1 = (emear1 & 0xFFFF0000) |
                ((new_bank0_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
                ((new_bank1_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT << 8);
-               
+
        mpc824x_mpc107_setreg(MEAR1, mear1);
        mpc824x_mpc107_setreg(EMEAR1, emear1);
 
index 4a848297723bc8f0a6c5c1a33e10fc441046cd40..4539dc54cad63ba215e65ba1d0dff97c9bc3fe70 100644 (file)
 
 #include <common.h>
 #include <command.h>
-#include <miiphy.h>
-#include <miivals.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <miiphy.h>
+
+#define        CONFIG_TERSE_MII        /* XXX necessary here because "miivals.h" is missing */
 
 #ifdef CONFIG_TERSE_MII
 /*
@@ -145,7 +146,10 @@ U_BOOT_CMD(
        "mii read  <addr> <reg>        - read  MII PHY <addr> register <reg>\n"
        "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
 );
-#else /* CONFIG_TERSE_MII */
+
+#else /* ! CONFIG_TERSE_MII ================================================= */
+
+#include <miivals.h>
 
 typedef struct _MII_reg_desc_t {
        ushort regno;
index 559c7f415aab092a21b3404040c1f076abdb99ec..e12eee9d1d913808a29a2bdc5109c43748e3cbca 100644 (file)
@@ -103,6 +103,9 @@ boot_cold:
 boot_warm:
        mfmsr   r5                      /* save msr contents            */
 
+       /* Move CSBoot and adjust instruction pointer                   */
+       /*--------------------------------------------------------------*/
+
 #if defined(CFG_LOWBOOT)
 #if defined(CFG_RAMBOOT)
 #error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
@@ -113,19 +116,15 @@ boot_warm:
        stw     r3, 0x4(r4)             /* CS0 start */
        lis     r3,     STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
        ori     r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
-
        stw     r3, 0x8(r4)             /* CS0 stop */
-       lis     r3,     0x00047800@h
-       ori     r3, r3, 0x00047800@l
-       stw     r3, 0x300(r4)           /* set timing, CS0/boot conf reg */
        lis     r3,     0x02010000@h
        ori     r3, r3, 0x02010000@l
-       stw     r3, 0x54(r4)            /* CS0 and Boot enable, IPBI ctrl reg */
+       stw     r3, 0x54(r4)            /* CS0 and Boot enable */
 
-       lis     r3,     lowboot_reentry@h
-       ori     r3, r3, lowboot_reentry@l
+       lis     r3,     lowboot_reentry@h       /* jump from bootlow address space (0x0000xxxx) */
+       ori     r3, r3, lowboot_reentry@l       /* to the address space the linker used */
        mtlr    r3
-       blr                             /* jump to flash based address */
+       blr
 
 lowboot_reentry:
        lis     r3,     START_REG(CFG_BOOTCS_START)@h
@@ -134,12 +133,9 @@ lowboot_reentry:
        lis     r3,     STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
        ori     r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
        stw     r3, 0x50(r4)            /* Boot stop */
-       lis     r3,     0x00047800@h
-       ori     r3, r3, 0x00047800@l
-       stw     r3, 0x300(r4)           /* set timing, CS0/boot conf reg */
        lis     r3,     0x02000001@h
        ori     r3, r3, 0x02000001@l
-       stw     r3, 0x54(r4)            /* Boot enable, CS0 disable, wait state enable */
+       stw     r3, 0x54(r4)            /* Boot enable, CS0 disable */
 #endif /* CFG_LOWBOOT */
 
 #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
index 52ad158f0d4c87b21e0db58210a8a95da89dc0ce..5252bc97678aff2a24742e5a51abc1556c416801 100644 (file)
@@ -1,9 +1,12 @@
 ---------------------------------------------------------------------------
 Build target                Flash address | BDI "go" command | Reset Vector
 ---------------------------------------------------------------------------
-MPC5200LITE                  0xFFF00000   |    0xFFF00100    |   0xFFF00100
-MPC5200LITE_LOWBOOT          0xFF000000   |    0xFF000100    |   0x00000100
-MPC5200LITE_LOWBOOT08        0xFF800000   |    0xFF800100    |   0x00000100
+Lite5200                     0xFFF00000   |    0xFFF00100    |   0xFFF00100
+Lite5200_LOWBOOT             0xFF000000   |    0xFF000100    |   0x00000100
+Lite5200_LOWBOOT08           0xFF800000   |    0xFF800100    |   0x00000100
+icecube_5200                 0xFFF00000   |    0xFFF00100    |   0xFFF00100
+icecube_5200_LOWBOOT         0xFF000000   |    0xFF000100    |   0x00000100
+icecube_5200_LOWBOOT08       0xFF800000   |    0xFF800100    |   0x00000100
 icecube_5200_DDR             0xFFF00000   |    0xFFF00100    |   0xFFF00100
 icecube_5200_DDR_LOWBOOT     0xFF800000   |    0xFF800100    |   0x00000100
 icecube_5200_DDR_LOWBOOT08   0xFF800000   |    0xFF800100    |   0x00000100
index 3af150d4237c27dc992227525005042d60dc828e..fcd1593cb8663b0f4a3da1bb53d15a1d04c331e4 100644 (file)
@@ -23,6 +23,9 @@
  */
 
 #include <config.h>
+
+#ifdef CONFIG_MICROBLZE
+
 #include <asm/serial_xuartlite.h>
 
 /* FIXME: we should convert these to in32 and out32 */
@@ -70,3 +73,5 @@ int serial_tstc(void)
 {
        return (IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA);
 }
+
+#endif /* CONFIG_MICROBLZE */