]> git.sur5r.net Git - u-boot/commitdiff
powerpc: mpc8xx: Change CONFIG_8xx to CONFIG_MPC8xx
authorChristophe Leroy <christophe.leroy@c-s.fr>
Fri, 16 Mar 2018 16:20:41 +0000 (17:20 +0100)
committerTom Rini <trini@konsulko.com>
Fri, 6 Apr 2018 20:30:37 +0000 (16:30 -0400)
CONFIG_8xx doesn't mean much outside of arch/powerpc/
This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ...
It also renames 8xx_immap.h to immap_8xx.h to be consistent with
other file names.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
20 files changed:
api/api_platform-powerpc.c
arch/powerpc/Kconfig
arch/powerpc/cpu/mpc8xx/Kconfig
arch/powerpc/cpu/mpc8xx/immap.c
arch/powerpc/include/asm/8xx_immap.h [deleted file]
arch/powerpc/include/asm/cache.h
arch/powerpc/include/asm/global_data.h
arch/powerpc/include/asm/immap_8xx.h [new file with mode: 0644]
arch/powerpc/include/asm/iopin_8xx.h
arch/powerpc/include/asm/ppc.h
cmd/bdinfo.c
configs/MCR3000_defconfig
drivers/net/Kconfig
drivers/serial/Kconfig
drivers/spi/Kconfig
include/asm-generic/u-boot.h
include/commproc.h
include/mpc8xx.h
include/ppc_asm.tmpl
include/watchdog.h

index 9e9bc63b2f568aeeb83389530b40b86134294cbc..aae7ddee959e99d219af4153e5efa051c3e7eb96 100644 (file)
@@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si)
        si->clk_bus = gd->bus_clk;
        si->clk_cpu = gd->cpu_clk;
 
-#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define bi_bar bi_immr_base
 #elif defined(CONFIG_MPC83xx)
 #define bi_bar bi_immrbar
index e4b3043fa2263c05e8c5ec711d3c7988e989d055..f29465f2c02aca9d4b7df009bd50a3753e56b186 100644 (file)
@@ -30,7 +30,7 @@ config MPC86xx
        select SYS_FSL_DDR_BE
        imply CMD_REGINFO
 
-config 8xx
+config MPC8xx
        bool "MPC8xx"
        imply CMD_REGINFO
 
index 5a7db335ed2f846aee77d5462508bad7c7a413f2..f112317376567b6fbc24c4783b4b6a019a338fc5 100644 (file)
@@ -1,5 +1,5 @@
 menu "mpc8xx CPU"
-       depends on 8xx
+       depends on MPC8xx
 
 config SYS_CPU
        default "mpc8xx"
index 2284979dd6539335f719861946824b23219dbad9..dfe5dc21251bcebb4edbb4b5cb97dce4a6399194 100644 (file)
@@ -12,7 +12,7 @@
 #include <common.h>
 #include <command.h>
 
-#include <asm/8xx_immap.h>
+#include <asm/immap_8xx.h>
 #include <commproc.h>
 #include <asm/iopin_8xx.h>
 #include <asm/io.h>
diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h
deleted file mode 100644 (file)
index 3999a02..0000000
+++ /dev/null
@@ -1,468 +0,0 @@
-/*
- * MPC8xx Internal Memory Map
- * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
- *
- * The I/O on the MPC860 is comprised of blocks of special registers
- * and the dual port ram for the Communication Processor Module.
- * Within this space are functional units such as the SIU, memory
- * controller, system timers, and other control functions.  It is
- * a combination that I found difficult to separate into logical
- * functional files.....but anyone else is welcome to try.  -- Dan
- */
-#ifndef __IMMAP_8XX__
-#define __IMMAP_8XX__
-
-/* System configuration registers.
-*/
-typedef        struct sys_conf {
-       uint    sc_siumcr;
-       uint    sc_sypcr;
-       uint    sc_swt;
-       char    res1[2];
-       ushort  sc_swsr;
-       uint    sc_sipend;
-       uint    sc_simask;
-       uint    sc_siel;
-       uint    sc_sivec;
-       uint    sc_tesr;
-       char    res2[0xc];
-       uint    sc_sdcr;
-       char    res3[0x4c];
-} sysconf8xx_t;
-
-/* PCMCIA configuration registers.
-*/
-typedef struct pcmcia_conf {
-       uint    pcmc_pbr0;
-       uint    pcmc_por0;
-       uint    pcmc_pbr1;
-       uint    pcmc_por1;
-       uint    pcmc_pbr2;
-       uint    pcmc_por2;
-       uint    pcmc_pbr3;
-       uint    pcmc_por3;
-       uint    pcmc_pbr4;
-       uint    pcmc_por4;
-       uint    pcmc_pbr5;
-       uint    pcmc_por5;
-       uint    pcmc_pbr6;
-       uint    pcmc_por6;
-       uint    pcmc_pbr7;
-       uint    pcmc_por7;
-       char    res1[0x20];
-       uint    pcmc_pgcra;
-       uint    pcmc_pgcrb;
-       uint    pcmc_pscr;
-       char    res2[4];
-       uint    pcmc_pipr;
-       char    res3[4];
-       uint    pcmc_per;
-       char    res4[4];
-} pcmconf8xx_t;
-
-/* Memory controller registers.
-*/
-typedef struct mem_ctlr {
-       uint    memc_br0;
-       uint    memc_or0;
-       uint    memc_br1;
-       uint    memc_or1;
-       uint    memc_br2;
-       uint    memc_or2;
-       uint    memc_br3;
-       uint    memc_or3;
-       uint    memc_br4;
-       uint    memc_or4;
-       uint    memc_br5;
-       uint    memc_or5;
-       uint    memc_br6;
-       uint    memc_or6;
-       uint    memc_br7;
-       uint    memc_or7;
-       char    res1[0x24];
-       uint    memc_mar;
-       uint    memc_mcr;
-       char    res2[4];
-       uint    memc_mamr;
-       uint    memc_mbmr;
-       ushort  memc_mstat;
-       ushort  memc_mptpr;
-       uint    memc_mdr;
-       char    res3[0x80];
-} memctl8xx_t;
-
-/* System Integration Timers.
-*/
-typedef struct sys_int_timers {
-       ushort  sit_tbscr;
-       char    res0[0x02];
-       uint    sit_tbreff0;
-       uint    sit_tbreff1;
-       char    res1[0x14];
-       ushort  sit_rtcsc;
-       char    res2[0x02];
-       uint    sit_rtc;
-       uint    sit_rtsec;
-       uint    sit_rtcal;
-       char    res3[0x10];
-       ushort  sit_piscr;
-       char    res4[2];
-       uint    sit_pitc;
-       uint    sit_pitr;
-       char    res5[0x34];
-} sit8xx_t;
-
-#define TBSCR_TBIRQ_MASK       ((ushort)0xff00)
-#define TBSCR_REFA             ((ushort)0x0080)
-#define TBSCR_REFB             ((ushort)0x0040)
-#define TBSCR_REFAE            ((ushort)0x0008)
-#define TBSCR_REFBE            ((ushort)0x0004)
-#define TBSCR_TBF              ((ushort)0x0002)
-#define TBSCR_TBE              ((ushort)0x0001)
-
-#define RTCSC_RTCIRQ_MASK      ((ushort)0xff00)
-#define RTCSC_SEC              ((ushort)0x0080)
-#define RTCSC_ALR              ((ushort)0x0040)
-#define RTCSC_38K              ((ushort)0x0010)
-#define RTCSC_SIE              ((ushort)0x0008)
-#define RTCSC_ALE              ((ushort)0x0004)
-#define RTCSC_RTF              ((ushort)0x0002)
-#define RTCSC_RTE              ((ushort)0x0001)
-
-#define PISCR_PIRQ_MASK                ((ushort)0xff00)
-#define PISCR_PS               ((ushort)0x0080)
-#define PISCR_PIE              ((ushort)0x0004)
-#define PISCR_PTF              ((ushort)0x0002)
-#define PISCR_PTE              ((ushort)0x0001)
-
-/* Clocks and Reset.
-*/
-typedef struct clk_and_reset {
-       uint    car_sccr;
-       uint    car_plprcr;
-       uint    car_rsr;
-       char    res[0x74];        /* Reserved area                  */
-} car8xx_t;
-
-/* System Integration Timers keys.
-*/
-typedef struct sitk {
-       uint    sitk_tbscrk;
-       uint    sitk_tbreff0k;
-       uint    sitk_tbreff1k;
-       uint    sitk_tbk;
-       char    res1[0x10];
-       uint    sitk_rtcsck;
-       uint    sitk_rtck;
-       uint    sitk_rtseck;
-       uint    sitk_rtcalk;
-       char    res2[0x10];
-       uint    sitk_piscrk;
-       uint    sitk_pitck;
-       char    res3[0x38];
-} sitk8xx_t;
-
-/* Clocks and reset keys.
-*/
-typedef struct cark {
-       uint    cark_sccrk;
-       uint    cark_plprcrk;
-       uint    cark_rsrk;
-       char    res[0x474];
-} cark8xx_t;
-
-/* The key to unlock registers maintained by keep-alive power.
-*/
-#define KAPWR_KEY      ((unsigned int)0x55ccaa33)
-
-/* I2C
-*/
-typedef struct i2c {
-       u_char  i2c_i2mod;
-       char    res1[3];
-       u_char  i2c_i2add;
-       char    res2[3];
-       u_char  i2c_i2brg;
-       char    res3[3];
-       u_char  i2c_i2com;
-       char    res4[3];
-       u_char  i2c_i2cer;
-       char    res5[3];
-       u_char  i2c_i2cmr;
-       char    res6[0x8b];
-} i2c8xx_t;
-
-/* DMA control/status registers.
-*/
-typedef struct sdma_csr {
-       char    res1[4];
-       uint    sdma_sdar;
-       u_char  sdma_sdsr;
-       char    res3[3];
-       u_char  sdma_sdmr;
-       char    res4[3];
-       u_char  sdma_idsr1;
-       char    res5[3];
-       u_char  sdma_idmr1;
-       char    res6[3];
-       u_char  sdma_idsr2;
-       char    res7[3];
-       u_char  sdma_idmr2;
-       char    res8[0x13];
-} sdma8xx_t;
-
-/* Communication Processor Module Interrupt Controller.
-*/
-typedef struct cpm_ic {
-       ushort  cpic_civr;
-       char    res[0xe];
-       uint    cpic_cicr;
-       uint    cpic_cipr;
-       uint    cpic_cimr;
-       uint    cpic_cisr;
-} cpic8xx_t;
-
-/* Input/Output Port control/status registers.
-*/
-typedef struct io_port {
-       ushort  iop_padir;
-       ushort  iop_papar;
-       ushort  iop_paodr;
-       ushort  iop_padat;
-       char    res1[8];
-       ushort  iop_pcdir;
-       ushort  iop_pcpar;
-       ushort  iop_pcso;
-       ushort  iop_pcdat;
-       ushort  iop_pcint;
-       char    res2[6];
-       ushort  iop_pddir;
-       ushort  iop_pdpar;
-       char    res3[2];
-       ushort  iop_pddat;
-       uint    utmode;
-       char    res4[4];
-} iop8xx_t;
-
-/* Communication Processor Module Timers
-*/
-typedef struct cpm_timers {
-       ushort  cpmt_tgcr;
-       char    res1[0xe];
-       ushort  cpmt_tmr1;
-       ushort  cpmt_tmr2;
-       ushort  cpmt_trr1;
-       ushort  cpmt_trr2;
-       ushort  cpmt_tcr1;
-       ushort  cpmt_tcr2;
-       ushort  cpmt_tcn1;
-       ushort  cpmt_tcn2;
-       ushort  cpmt_tmr3;
-       ushort  cpmt_tmr4;
-       ushort  cpmt_trr3;
-       ushort  cpmt_trr4;
-       ushort  cpmt_tcr3;
-       ushort  cpmt_tcr4;
-       ushort  cpmt_tcn3;
-       ushort  cpmt_tcn4;
-       ushort  cpmt_ter1;
-       ushort  cpmt_ter2;
-       ushort  cpmt_ter3;
-       ushort  cpmt_ter4;
-       char    res2[8];
-} cpmtimer8xx_t;
-
-/* Finally, the Communication Processor stuff.....
-*/
-typedef struct scc {           /* Serial communication channels */
-       uint    scc_gsmrl;
-       uint    scc_gsmrh;
-       ushort  scc_psmr;
-       char    res1[2];
-       ushort  scc_todr;
-       ushort  scc_dsr;
-       ushort  scc_scce;
-       char    res2[2];
-       ushort  scc_sccm;
-       char    res3;
-       u_char  scc_sccs;
-       char    res4[8];
-} scc_t;
-
-typedef struct smc {           /* Serial management channels */
-       char    res1[2];
-       ushort  smc_smcmr;
-       char    res2[2];
-       u_char  smc_smce;
-       char    res3[3];
-       u_char  smc_smcm;
-       char    res4[5];
-} smc_t;
-
-/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
- * it fits within the address space.
- */
-
-typedef struct fec {
-       uint    fec_addr_low;           /* lower 32 bits of station address     */
-       ushort  fec_addr_high;          /* upper 16 bits of station address     */
-       ushort  res1;                   /* reserved                             */
-       uint    fec_hash_table_high;    /* upper 32-bits of hash table          */
-       uint    fec_hash_table_low;     /* lower 32-bits of hash table          */
-       uint    fec_r_des_start;        /* beginning of Rx descriptor ring      */
-       uint    fec_x_des_start;        /* beginning of Tx descriptor ring      */
-       uint    fec_r_buff_size;        /* Rx buffer size                       */
-       uint    res2[9];                /* reserved                             */
-       uint    fec_ecntrl;             /* ethernet control register            */
-       uint    fec_ievent;             /* interrupt event register             */
-       uint    fec_imask;              /* interrupt mask register              */
-       uint    fec_ivec;               /* interrupt level and vector status    */
-       uint    fec_r_des_active;       /* Rx ring updated flag                 */
-       uint    fec_x_des_active;       /* Tx ring updated flag                 */
-       uint    res3[10];               /* reserved                             */
-       uint    fec_mii_data;           /* MII data register                    */
-       uint    fec_mii_speed;          /* MII speed control register           */
-       uint    res4[17];               /* reserved                             */
-       uint    fec_r_bound;            /* end of RAM (read-only)               */
-       uint    fec_r_fstart;           /* Rx FIFO start address                */
-       uint    res5[6];                /* reserved                             */
-       uint    fec_x_fstart;           /* Tx FIFO start address                */
-       uint    res6[17];               /* reserved                             */
-       uint    fec_fun_code;           /* fec SDMA function code               */
-       uint    res7[3];                /* reserved                             */
-       uint    fec_r_cntrl;            /* Rx control register                  */
-       uint    fec_r_hash;             /* Rx hash register                     */
-       uint    res8[14];               /* reserved                             */
-       uint    fec_x_cntrl;            /* Tx control register                  */
-       uint    res9[0x1e];             /* reserved                             */
-} fec_t;
-
-typedef struct comm_proc {
-       /* General control and status registers.
-       */
-       ushort  cp_cpcr;
-       u_char  res1[2];
-       ushort  cp_rccr;
-       u_char  res2;
-       u_char  cp_rmds;
-       u_char  res3[4];
-       ushort  cp_cpmcr1;
-       ushort  cp_cpmcr2;
-       ushort  cp_cpmcr3;
-       ushort  cp_cpmcr4;
-       u_char  res4[2];
-       ushort  cp_rter;
-       u_char  res5[2];
-       ushort  cp_rtmr;
-       u_char  res6[0x14];
-
-       /* Baud rate generators.
-       */
-       uint    cp_brgc1;
-       uint    cp_brgc2;
-       uint    cp_brgc3;
-       uint    cp_brgc4;
-
-       /* Serial Communication Channels.
-       */
-       scc_t   cp_scc[4];
-
-       /* Serial Management Channels.
-       */
-       smc_t   cp_smc[2];
-
-       /* Serial Peripheral Interface.
-       */
-       ushort  cp_spmode;
-       u_char  res7[4];
-       u_char  cp_spie;
-       u_char  res8[3];
-       u_char  cp_spim;
-       u_char  res9[2];
-       u_char  cp_spcom;
-       u_char  res10[2];
-
-       /* Parallel Interface Port.
-       */
-       u_char  res11[2];
-       ushort  cp_pipc;
-       u_char  res12[2];
-       ushort  cp_ptpr;
-       uint    cp_pbdir;
-       uint    cp_pbpar;
-       u_char  res13[2];
-       ushort  cp_pbodr;
-       uint    cp_pbdat;
-
-       /* Port E - MPC87x/88x only.
-        */
-       uint    cp_pedir;
-       uint    cp_pepar;
-       uint    cp_peso;
-       uint    cp_peodr;
-       uint    cp_pedat;
-
-       /* Communications Processor Timing Register -
-          Contains RMII Timing for the FECs on MPC87x/88x only.
-       */
-       uint    cp_cptr;
-
-       /* Serial Interface and Time Slot Assignment.
-       */
-       uint    cp_simode;
-       u_char  cp_sigmr;
-       u_char  res15;
-       u_char  cp_sistr;
-       u_char  cp_sicmr;
-       u_char  res16[4];
-       uint    cp_sicr;
-       uint    cp_sirp;
-       u_char  res17[0xc];
-
-       u_char  res19[0x100];
-       u_char  cp_siram[0x200];
-
-       /* The fast ethernet controller is not really part of the CPM,
-        * but it resides in the address space.
-        */
-       fec_t   cp_fec;
-       char    res18[0xE00];
-
-       /* The MPC885 family has a second FEC here */
-       fec_t   cp_fec2;
-#define cp_fec1        cp_fec  /* consistency macro */
-
-       /* Dual Ported RAM follows.
-        * There are many different formats for this memory area
-        * depending upon the devices used and options chosen.
-        * Some processors don't have all of it populated.
-        */
-       u_char  cp_dpmem[0x1C00];       /* BD / Data / ucode */
-
-       /* Parameter RAM */
-       union {
-               u_char  cp_dparam[0x400];
-               u16     cp_dparam16[0x200];
-       };
-} cpm8xx_t;
-
-/* Internal memory map.
-*/
-typedef struct immap {
-       sysconf8xx_t    im_siu_conf;    /* SIU Configuration */
-       pcmconf8xx_t    im_pcmcia;      /* PCMCIA Configuration */
-       memctl8xx_t     im_memctl;      /* Memory Controller */
-       sit8xx_t        im_sit;         /* System integration timers */
-       car8xx_t        im_clkrst;      /* Clocks and reset */
-       sitk8xx_t       im_sitk;        /* Sys int timer keys */
-       cark8xx_t       im_clkrstk;     /* Clocks and reset keys */
-       char            res[96];
-       i2c8xx_t        im_i2c;         /* I2C control/status */
-       sdma8xx_t       im_sdma;        /* SDMA control/status */
-       cpic8xx_t       im_cpic;        /* CPM Interrupt Controller */
-       iop8xx_t        im_ioport;      /* IO Port control/status */
-       cpmtimer8xx_t   im_cpmtimer;    /* CPM timers */
-       cpm8xx_t        im_cpm;         /* Communication processor */
-} immap_t;
-
-#endif /* __IMMAP_8XX__ */
index 0801d2c367765e3162fd86226eec4661d17c5890..445a366807db9d6b061d37907fdcc54fae035b73 100644 (file)
@@ -7,7 +7,7 @@
 #include <asm/processor.h>
 
 /* bytes per L1 cache line */
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
 #define        L1_CACHE_SHIFT  4
 #elif defined(CONFIG_PPC64BRIDGE)
 #define L1_CACHE_SHIFT 7
@@ -72,7 +72,7 @@ void disable_cpc_sram(void);
 #define L2CACHE_NONE   0x03    /* NONE */
 #define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
 
-#ifdef CONFIG_8xx
+#ifdef CONFIG_MPC8xx
 /* Cache control on the MPC8xx is provided through some additional
  * special purpose registers.
  */
@@ -139,6 +139,6 @@ static inline void wr_dc_adr(uint val)
        mtspr(DC_ADR, val);
 }
 #endif
-#endif /* CONFIG_8xx */
+#endif /* CONFIG_MPC8xx */
 
 #endif
index 35a02b61a44b3409640b85fbbce719f2e95e67dd..016dc19cb4c914ab03ba86bbf736874f1b271dd7 100644 (file)
@@ -19,7 +19,7 @@ struct arch_global_data {
        u8 sdhc_adapter;
 #endif
 #endif
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
        unsigned long brg_clk;
 #endif
 #if defined(CONFIG_CPM2)
diff --git a/arch/powerpc/include/asm/immap_8xx.h b/arch/powerpc/include/asm/immap_8xx.h
new file mode 100644 (file)
index 0000000..3999a02
--- /dev/null
@@ -0,0 +1,468 @@
+/*
+ * MPC8xx Internal Memory Map
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * The I/O on the MPC860 is comprised of blocks of special registers
+ * and the dual port ram for the Communication Processor Module.
+ * Within this space are functional units such as the SIU, memory
+ * controller, system timers, and other control functions.  It is
+ * a combination that I found difficult to separate into logical
+ * functional files.....but anyone else is welcome to try.  -- Dan
+ */
+#ifndef __IMMAP_8XX__
+#define __IMMAP_8XX__
+
+/* System configuration registers.
+*/
+typedef        struct sys_conf {
+       uint    sc_siumcr;
+       uint    sc_sypcr;
+       uint    sc_swt;
+       char    res1[2];
+       ushort  sc_swsr;
+       uint    sc_sipend;
+       uint    sc_simask;
+       uint    sc_siel;
+       uint    sc_sivec;
+       uint    sc_tesr;
+       char    res2[0xc];
+       uint    sc_sdcr;
+       char    res3[0x4c];
+} sysconf8xx_t;
+
+/* PCMCIA configuration registers.
+*/
+typedef struct pcmcia_conf {
+       uint    pcmc_pbr0;
+       uint    pcmc_por0;
+       uint    pcmc_pbr1;
+       uint    pcmc_por1;
+       uint    pcmc_pbr2;
+       uint    pcmc_por2;
+       uint    pcmc_pbr3;
+       uint    pcmc_por3;
+       uint    pcmc_pbr4;
+       uint    pcmc_por4;
+       uint    pcmc_pbr5;
+       uint    pcmc_por5;
+       uint    pcmc_pbr6;
+       uint    pcmc_por6;
+       uint    pcmc_pbr7;
+       uint    pcmc_por7;
+       char    res1[0x20];
+       uint    pcmc_pgcra;
+       uint    pcmc_pgcrb;
+       uint    pcmc_pscr;
+       char    res2[4];
+       uint    pcmc_pipr;
+       char    res3[4];
+       uint    pcmc_per;
+       char    res4[4];
+} pcmconf8xx_t;
+
+/* Memory controller registers.
+*/
+typedef struct mem_ctlr {
+       uint    memc_br0;
+       uint    memc_or0;
+       uint    memc_br1;
+       uint    memc_or1;
+       uint    memc_br2;
+       uint    memc_or2;
+       uint    memc_br3;
+       uint    memc_or3;
+       uint    memc_br4;
+       uint    memc_or4;
+       uint    memc_br5;
+       uint    memc_or5;
+       uint    memc_br6;
+       uint    memc_or6;
+       uint    memc_br7;
+       uint    memc_or7;
+       char    res1[0x24];
+       uint    memc_mar;
+       uint    memc_mcr;
+       char    res2[4];
+       uint    memc_mamr;
+       uint    memc_mbmr;
+       ushort  memc_mstat;
+       ushort  memc_mptpr;
+       uint    memc_mdr;
+       char    res3[0x80];
+} memctl8xx_t;
+
+/* System Integration Timers.
+*/
+typedef struct sys_int_timers {
+       ushort  sit_tbscr;
+       char    res0[0x02];
+       uint    sit_tbreff0;
+       uint    sit_tbreff1;
+       char    res1[0x14];
+       ushort  sit_rtcsc;
+       char    res2[0x02];
+       uint    sit_rtc;
+       uint    sit_rtsec;
+       uint    sit_rtcal;
+       char    res3[0x10];
+       ushort  sit_piscr;
+       char    res4[2];
+       uint    sit_pitc;
+       uint    sit_pitr;
+       char    res5[0x34];
+} sit8xx_t;
+
+#define TBSCR_TBIRQ_MASK       ((ushort)0xff00)
+#define TBSCR_REFA             ((ushort)0x0080)
+#define TBSCR_REFB             ((ushort)0x0040)
+#define TBSCR_REFAE            ((ushort)0x0008)
+#define TBSCR_REFBE            ((ushort)0x0004)
+#define TBSCR_TBF              ((ushort)0x0002)
+#define TBSCR_TBE              ((ushort)0x0001)
+
+#define RTCSC_RTCIRQ_MASK      ((ushort)0xff00)
+#define RTCSC_SEC              ((ushort)0x0080)
+#define RTCSC_ALR              ((ushort)0x0040)
+#define RTCSC_38K              ((ushort)0x0010)
+#define RTCSC_SIE              ((ushort)0x0008)
+#define RTCSC_ALE              ((ushort)0x0004)
+#define RTCSC_RTF              ((ushort)0x0002)
+#define RTCSC_RTE              ((ushort)0x0001)
+
+#define PISCR_PIRQ_MASK                ((ushort)0xff00)
+#define PISCR_PS               ((ushort)0x0080)
+#define PISCR_PIE              ((ushort)0x0004)
+#define PISCR_PTF              ((ushort)0x0002)
+#define PISCR_PTE              ((ushort)0x0001)
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+       uint    car_sccr;
+       uint    car_plprcr;
+       uint    car_rsr;
+       char    res[0x74];        /* Reserved area                  */
+} car8xx_t;
+
+/* System Integration Timers keys.
+*/
+typedef struct sitk {
+       uint    sitk_tbscrk;
+       uint    sitk_tbreff0k;
+       uint    sitk_tbreff1k;
+       uint    sitk_tbk;
+       char    res1[0x10];
+       uint    sitk_rtcsck;
+       uint    sitk_rtck;
+       uint    sitk_rtseck;
+       uint    sitk_rtcalk;
+       char    res2[0x10];
+       uint    sitk_piscrk;
+       uint    sitk_pitck;
+       char    res3[0x38];
+} sitk8xx_t;
+
+/* Clocks and reset keys.
+*/
+typedef struct cark {
+       uint    cark_sccrk;
+       uint    cark_plprcrk;
+       uint    cark_rsrk;
+       char    res[0x474];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY      ((unsigned int)0x55ccaa33)
+
+/* I2C
+*/
+typedef struct i2c {
+       u_char  i2c_i2mod;
+       char    res1[3];
+       u_char  i2c_i2add;
+       char    res2[3];
+       u_char  i2c_i2brg;
+       char    res3[3];
+       u_char  i2c_i2com;
+       char    res4[3];
+       u_char  i2c_i2cer;
+       char    res5[3];
+       u_char  i2c_i2cmr;
+       char    res6[0x8b];
+} i2c8xx_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+       char    res1[4];
+       uint    sdma_sdar;
+       u_char  sdma_sdsr;
+       char    res3[3];
+       u_char  sdma_sdmr;
+       char    res4[3];
+       u_char  sdma_idsr1;
+       char    res5[3];
+       u_char  sdma_idmr1;
+       char    res6[3];
+       u_char  sdma_idsr2;
+       char    res7[3];
+       u_char  sdma_idmr2;
+       char    res8[0x13];
+} sdma8xx_t;
+
+/* Communication Processor Module Interrupt Controller.
+*/
+typedef struct cpm_ic {
+       ushort  cpic_civr;
+       char    res[0xe];
+       uint    cpic_cicr;
+       uint    cpic_cipr;
+       uint    cpic_cimr;
+       uint    cpic_cisr;
+} cpic8xx_t;
+
+/* Input/Output Port control/status registers.
+*/
+typedef struct io_port {
+       ushort  iop_padir;
+       ushort  iop_papar;
+       ushort  iop_paodr;
+       ushort  iop_padat;
+       char    res1[8];
+       ushort  iop_pcdir;
+       ushort  iop_pcpar;
+       ushort  iop_pcso;
+       ushort  iop_pcdat;
+       ushort  iop_pcint;
+       char    res2[6];
+       ushort  iop_pddir;
+       ushort  iop_pdpar;
+       char    res3[2];
+       ushort  iop_pddat;
+       uint    utmode;
+       char    res4[4];
+} iop8xx_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+       ushort  cpmt_tgcr;
+       char    res1[0xe];
+       ushort  cpmt_tmr1;
+       ushort  cpmt_tmr2;
+       ushort  cpmt_trr1;
+       ushort  cpmt_trr2;
+       ushort  cpmt_tcr1;
+       ushort  cpmt_tcr2;
+       ushort  cpmt_tcn1;
+       ushort  cpmt_tcn2;
+       ushort  cpmt_tmr3;
+       ushort  cpmt_tmr4;
+       ushort  cpmt_trr3;
+       ushort  cpmt_trr4;
+       ushort  cpmt_tcr3;
+       ushort  cpmt_tcr4;
+       ushort  cpmt_tcn3;
+       ushort  cpmt_tcn4;
+       ushort  cpmt_ter1;
+       ushort  cpmt_ter2;
+       ushort  cpmt_ter3;
+       ushort  cpmt_ter4;
+       char    res2[8];
+} cpmtimer8xx_t;
+
+/* Finally, the Communication Processor stuff.....
+*/
+typedef struct scc {           /* Serial communication channels */
+       uint    scc_gsmrl;
+       uint    scc_gsmrh;
+       ushort  scc_psmr;
+       char    res1[2];
+       ushort  scc_todr;
+       ushort  scc_dsr;
+       ushort  scc_scce;
+       char    res2[2];
+       ushort  scc_sccm;
+       char    res3;
+       u_char  scc_sccs;
+       char    res4[8];
+} scc_t;
+
+typedef struct smc {           /* Serial management channels */
+       char    res1[2];
+       ushort  smc_smcmr;
+       char    res2[2];
+       u_char  smc_smce;
+       char    res3[3];
+       u_char  smc_smcm;
+       char    res4[5];
+} smc_t;
+
+/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
+ * it fits within the address space.
+ */
+
+typedef struct fec {
+       uint    fec_addr_low;           /* lower 32 bits of station address     */
+       ushort  fec_addr_high;          /* upper 16 bits of station address     */
+       ushort  res1;                   /* reserved                             */
+       uint    fec_hash_table_high;    /* upper 32-bits of hash table          */
+       uint    fec_hash_table_low;     /* lower 32-bits of hash table          */
+       uint    fec_r_des_start;        /* beginning of Rx descriptor ring      */
+       uint    fec_x_des_start;        /* beginning of Tx descriptor ring      */
+       uint    fec_r_buff_size;        /* Rx buffer size                       */
+       uint    res2[9];                /* reserved                             */
+       uint    fec_ecntrl;             /* ethernet control register            */
+       uint    fec_ievent;             /* interrupt event register             */
+       uint    fec_imask;              /* interrupt mask register              */
+       uint    fec_ivec;               /* interrupt level and vector status    */
+       uint    fec_r_des_active;       /* Rx ring updated flag                 */
+       uint    fec_x_des_active;       /* Tx ring updated flag                 */
+       uint    res3[10];               /* reserved                             */
+       uint    fec_mii_data;           /* MII data register                    */
+       uint    fec_mii_speed;          /* MII speed control register           */
+       uint    res4[17];               /* reserved                             */
+       uint    fec_r_bound;            /* end of RAM (read-only)               */
+       uint    fec_r_fstart;           /* Rx FIFO start address                */
+       uint    res5[6];                /* reserved                             */
+       uint    fec_x_fstart;           /* Tx FIFO start address                */
+       uint    res6[17];               /* reserved                             */
+       uint    fec_fun_code;           /* fec SDMA function code               */
+       uint    res7[3];                /* reserved                             */
+       uint    fec_r_cntrl;            /* Rx control register                  */
+       uint    fec_r_hash;             /* Rx hash register                     */
+       uint    res8[14];               /* reserved                             */
+       uint    fec_x_cntrl;            /* Tx control register                  */
+       uint    res9[0x1e];             /* reserved                             */
+} fec_t;
+
+typedef struct comm_proc {
+       /* General control and status registers.
+       */
+       ushort  cp_cpcr;
+       u_char  res1[2];
+       ushort  cp_rccr;
+       u_char  res2;
+       u_char  cp_rmds;
+       u_char  res3[4];
+       ushort  cp_cpmcr1;
+       ushort  cp_cpmcr2;
+       ushort  cp_cpmcr3;
+       ushort  cp_cpmcr4;
+       u_char  res4[2];
+       ushort  cp_rter;
+       u_char  res5[2];
+       ushort  cp_rtmr;
+       u_char  res6[0x14];
+
+       /* Baud rate generators.
+       */
+       uint    cp_brgc1;
+       uint    cp_brgc2;
+       uint    cp_brgc3;
+       uint    cp_brgc4;
+
+       /* Serial Communication Channels.
+       */
+       scc_t   cp_scc[4];
+
+       /* Serial Management Channels.
+       */
+       smc_t   cp_smc[2];
+
+       /* Serial Peripheral Interface.
+       */
+       ushort  cp_spmode;
+       u_char  res7[4];
+       u_char  cp_spie;
+       u_char  res8[3];
+       u_char  cp_spim;
+       u_char  res9[2];
+       u_char  cp_spcom;
+       u_char  res10[2];
+
+       /* Parallel Interface Port.
+       */
+       u_char  res11[2];
+       ushort  cp_pipc;
+       u_char  res12[2];
+       ushort  cp_ptpr;
+       uint    cp_pbdir;
+       uint    cp_pbpar;
+       u_char  res13[2];
+       ushort  cp_pbodr;
+       uint    cp_pbdat;
+
+       /* Port E - MPC87x/88x only.
+        */
+       uint    cp_pedir;
+       uint    cp_pepar;
+       uint    cp_peso;
+       uint    cp_peodr;
+       uint    cp_pedat;
+
+       /* Communications Processor Timing Register -
+          Contains RMII Timing for the FECs on MPC87x/88x only.
+       */
+       uint    cp_cptr;
+
+       /* Serial Interface and Time Slot Assignment.
+       */
+       uint    cp_simode;
+       u_char  cp_sigmr;
+       u_char  res15;
+       u_char  cp_sistr;
+       u_char  cp_sicmr;
+       u_char  res16[4];
+       uint    cp_sicr;
+       uint    cp_sirp;
+       u_char  res17[0xc];
+
+       u_char  res19[0x100];
+       u_char  cp_siram[0x200];
+
+       /* The fast ethernet controller is not really part of the CPM,
+        * but it resides in the address space.
+        */
+       fec_t   cp_fec;
+       char    res18[0xE00];
+
+       /* The MPC885 family has a second FEC here */
+       fec_t   cp_fec2;
+#define cp_fec1        cp_fec  /* consistency macro */
+
+       /* Dual Ported RAM follows.
+        * There are many different formats for this memory area
+        * depending upon the devices used and options chosen.
+        * Some processors don't have all of it populated.
+        */
+       u_char  cp_dpmem[0x1C00];       /* BD / Data / ucode */
+
+       /* Parameter RAM */
+       union {
+               u_char  cp_dparam[0x400];
+               u16     cp_dparam16[0x200];
+       };
+} cpm8xx_t;
+
+/* Internal memory map.
+*/
+typedef struct immap {
+       sysconf8xx_t    im_siu_conf;    /* SIU Configuration */
+       pcmconf8xx_t    im_pcmcia;      /* PCMCIA Configuration */
+       memctl8xx_t     im_memctl;      /* Memory Controller */
+       sit8xx_t        im_sit;         /* System integration timers */
+       car8xx_t        im_clkrst;      /* Clocks and reset */
+       sitk8xx_t       im_sitk;        /* Sys int timer keys */
+       cark8xx_t       im_clkrstk;     /* Clocks and reset keys */
+       char            res[96];
+       i2c8xx_t        im_i2c;         /* I2C control/status */
+       sdma8xx_t       im_sdma;        /* SDMA control/status */
+       cpic8xx_t       im_cpic;        /* CPM Interrupt Controller */
+       iop8xx_t        im_ioport;      /* IO Port control/status */
+       cpmtimer8xx_t   im_cpmtimer;    /* CPM timers */
+       cpm8xx_t        im_cpm;         /* Communication processor */
+} immap_t;
+
+#endif /* __IMMAP_8XX__ */
index 15679a2db55b6c0a265b4a6b8f45d2163cca49d4..3b4e1b64a41c27c56597190b84b35a83b6f090fd 100644 (file)
@@ -11,7 +11,7 @@
 #define _ASM_IOPIN_8XX_H_
 
 #include <linux/types.h>
-#include <asm/8xx_immap.h>
+#include <asm/immap_8xx.h>
 #include <asm/io.h>
 
 #ifdef __KERNEL__
index c3f73ef8858991ae4b360d012321759ec181ed7c..8e76c38ea39fd7af69a79c4ca5e218e6ae4ab49e 100644 (file)
@@ -13,8 +13,8 @@
 
 #ifndef __ASSEMBLY__
 
-#if defined(CONFIG_8xx)
-#include <asm/8xx_immap.h>
+#if defined(CONFIG_MPC8xx)
+#include <asm/immap_8xx.h>
 #endif
 #ifdef CONFIG_MPC86xx
 #include <mpc86xx.h>
index de6fc48987793b4ffe6a93541f36095d861e99bc..7bea9b7a2d12984fd122449d571694d5efc97df0 100644 (file)
@@ -180,7 +180,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        print_bi_flash(bd);
        print_num("sramstart",          bd->bi_sramstart);
        print_num("sramsize",           bd->bi_sramsize);
-#if    defined(CONFIG_8xx) || defined(CONFIG_E500)
+#if    defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
        print_num("immr_base",          bd->bi_immr_base);
 #endif
        print_num("bootflags",          bd->bi_bootflags);
index 108cf00154a2cf677803db9fb960fc443031b7f2..bce4d0e74c2e4fecb4aaadafaae1958b7814d3c2 100644 (file)
@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x4000000
-CONFIG_8xx=y
+CONFIG_MPC8xx=y
 CONFIG_TARGET_MCR3000=y
 CONFIG_8xx_GCLK_FREQ=132000000
 CONFIG_CMD_IMMAP=y
index f589978b43584335708b93c2a1a2e5098d4a5f52..608ed71cf7f6c00049082d5e6fc139f9a4fe6f54 100644 (file)
@@ -331,7 +331,7 @@ config RENESAS_RAVB
 
 config MPC8XX_FEC
        bool "Fast Ethernet Controller on MPC8XX"
-       depends on 8xx
+       depends on MPC8xx
        select MII
        help
          This driver implements support for the Fast Ethernet Controller
index eb718a650faae04915a9796594020e92e3014b22..3d5b2bf15f089b753f9722c0623d17cbafd143d5 100644 (file)
@@ -624,7 +624,7 @@ config ZYNQ_SERIAL
 
 config MPC8XX_CONS
        bool "Console driver for MPC8XX"
-       depends on 8xx
+       depends on MPC8xx
        default y
 
 choice
index 12dde8fb953821c1c14a140b3a9455a08900c25d..d3e407ec1101732a4f71b88a70998abce61f90b7 100644 (file)
@@ -276,7 +276,7 @@ config LPC32XX_SSP
 
 config MPC8XX_SPI
        bool "MPC8XX SPI Driver"
-       depends on 8xx
+       depends on MPC8xx
        help
          Enable support for SPI on MPC8XX
 
index d3049d81f581f93272f5b27947de8d90ba77d56f..f734d53eec26cb7306968553bb4eeee29793ebd9 100644 (file)
@@ -37,7 +37,7 @@ typedef struct bd_info {
        unsigned long   bi_dsp_freq; /* dsp core frequency */
        unsigned long   bi_ddr_freq; /* ddr frequency */
 #endif
-#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
        unsigned long   bi_immr_base;   /* base of IMMR register */
 #endif
 #if defined(CONFIG_M68K)
index 9536b135dcf6620eb9624e6f12992a84f93eab18..bd8adec6b070fa44bed1733446a57c7679b0db82 100644 (file)
@@ -16,7 +16,7 @@
 #ifndef __CPM_8XX__
 #define __CPM_8XX__
 
-#include <asm/8xx_immap.h>
+#include <asm/immap_8xx.h>
 
 /* CPM Command register.
 */
index fc081ab7568e76ae0c09508b11d0434eb9c704d8..daa874ccf58961a071fbb3c14d4feee6929b9757 100644 (file)
@@ -81,7 +81,7 @@
 #define TBSCR_TBIRQ2   0x0400          /* Time Base Interrupt Request 2        */
 #define TBSCR_TBIRQ1   0x0200          /* Time Base Interrupt Request 1        */
 #define TBSCR_TBIRQ0   0x0100          /* Time Base Interrupt Request 0        */
-#if 0  /* already in asm/8xx_immap.h */
+#if 0  /* already in asm/immap_8xx.h */
 #define TBSCR_REFA     0x0080          /* Reference Interrupt Status A         */
 #define TBSCR_REFB     0x0040          /* Reference Interrupt Status B         */
 #define TBSCR_REFAE    0x0008          /* Second Interrupt Enable A            */
@@ -95,7 +95,7 @@
  */
 #undef PISCR_PIRQ                      /* TBD                                  */
 #define PISCR_PITF     0x0002          /* Periodic Interrupt Timer Freeze      */
-#if 0  /* already in asm/8xx_immap.h */
+#if 0  /* already in asm/immap_8xx.h */
 #define PISCR_PS       0x0080          /* Periodic interrupt Status            */
 #define PISCR_PIE      0x0004          /* Periodic Interrupt Enable            */
 #define PISCR_PTE      0x0001          /* Periodic Timer Enable                */
index 18783340d969ac3ef39a2adf2823671816e72538..4947c77b8d446d2e08766413682cac85d05a1f4b 100644 (file)
@@ -81,7 +81,7 @@
 #define        r30     30
 #define        r31     31
 
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
 
 /* Some special registers */
 
 #define LCTRL2 157     /* Load/Store Support       (37-41) */
 #define ICTRL  158
 
-#endif /* CONFIG_8xx */
+#endif /* CONFIG_MPC8xx */
 
 
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
 
 /* Registers in the processor's internal memory map that we use.
 */
index 64b59f107ade3261741cfb72e71d7b3604c4bea4..d420ab127b3b50e3e1848a340ffabe42944f4411 100644 (file)
@@ -73,7 +73,7 @@ int init_func_watchdog_reset(void);
  */
 
 /* MPC 8xx */
-#if defined(CONFIG_8xx) && !defined(__ASSEMBLY__)
+#if defined(CONFIG_MPC8xx) && !defined(__ASSEMBLY__)
        void reset_8xx_watchdog(immap_t __iomem *immr);
 #endif