Describe U_BOOT_CMD_COMPLETE.
Describe the arguments of U_BOOT_CMD and U_BOOT_CMD_COMPLETE.
Describe the arguments of the command function.
Describe the arguments of the completion function.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Eugen Hristev [Wed, 9 May 2018 13:28:38 +0000 (16:28 +0300)]
test: fs: fs-test: Modified test 1 to do a ls to a nonexistent dir
Added a simple ls to a nonexistent directory for test 1.
In case the driver is broken for a nonexistent directory, U-boot
might crash.
Here is an example failed output:
=> # Test Case 1 - ls
=> ext4ls host 0:0
<DIR> 4096 .
<DIR> 4096 ..
<DIR> 16384 lost+found
<DIR> 4096 SUBDIR 2621440000 2.5GB.file 1048576 1MB.file
=> # In addition, test with a nonexistent directory to see if we crash.
=> ext4ls host 0:0 invalid_d
** Can not find directory. **
./test/fs/fs-test.sh: line 161: 25786 Segmentation fault (core dumped) $UBOOT <<EOF
Subsequent tests will fail if U-boot crashes.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Tested on SAMA5D2_Xplained board (sama5d2_xplained_mmc_defconfig)
Looks like crash is introduced by commit:
"fa9ca8a" fs/ext4/ext4fs.c: Free dirnode in error path of ext4fs_ls
Issue is that dirnode is not initialized, and then freed if the call
to ext4_ls fails. ext4_ls will not change the value of dirnode in this case
thus we have a crash with data abort.
I added initialization and a check for dirname being NULL.
Fixes: "fa9ca8a" fs/ext4/ext4fs.c: Free dirnode in error path of ext4fs_ls Cc: Stefan Brüns <stefan.bruens@rwth-aachen.de> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Eugen Hristev [Wed, 9 May 2018 07:30:26 +0000 (10:30 +0300)]
configs: at91sam9x5ek: updated mtdparts variable in bootargs
We have a new demo layout of our sama5 boards for the NAND Flash
memory.
According to this new layout, adjust the mtdparts variable in bootargs
to align with this, which is available at :
http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d3XplainedMainPage#NAND_Flash_demo_Memory_map,
Based on original work by Wenyou Yang
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Nicolas Ferre [Wed, 9 May 2018 07:30:25 +0000 (10:30 +0300)]
configs: at91: Adjust CONFIG_ENV_OFFSET to match sama5 address
In order to have a single ENV_OFFSET to manage, use the same as the sama5 one.
This address matches our NAND flash map available at:
http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d3XplainedMainPage#NAND_Flash_demo_Memory_map
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[eugen.hristev@microchip.com: rework on latest version of u-boot] Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Nicolas Ferre [Wed, 9 May 2018 07:30:24 +0000 (10:30 +0300)]
configs: at91: sama5_common: Adjust CONFIG_ENV_OFFSET to match block alignment
Fix the unaligned environment address.
This address matches our NAND flash map available at:
http://www.at91.com/linux4sam/bin/view/Linux4SAM/Sama5d3XplainedMainPage#NAND_Flash_demo_Memory_map
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[eugen.hristev@microchip.com: rework on latest version of u-boot] Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Tom Rini [Tue, 8 May 2018 18:34:05 +0000 (14:34 -0400)]
FIT: Make fit_conf_print() be a static function
We only call fit_conf_print from one place in the code, so mark it as
static and move it up to where we call it. This in turn has us move a
few other already static functions up further as well.
Tom Rini [Tue, 8 May 2018 15:34:36 +0000 (11:34 -0400)]
Licenses/README: Update some style and add explicit license to the document
- Add an SPDX license tag to the file, saying it's GPL-2.0.
- From the Linux Kernel v4.17-rc4, import the "License identifier
syntax" section as-is from Documentation/process/license-rules.rst
and then change it to be clearer about examples from the Linux Kernel
vs examples found in U-Boot, and when we're talking about U-Boot.
Tom Rini [Tue, 8 May 2018 00:46:52 +0000 (20:46 -0400)]
arm: armv7m: Clean up some thumb / compiler flag options
- The correct way to build with thumb mode is to select SYS_THUMB_BUILD
- We should be setting -march=armv7-m in arch/arm/Makefile not the
sub-config.mk file.
Tom Rini [Thu, 10 May 2018 11:15:54 +0000 (07:15 -0400)]
.travis.yml: Further optimizations
- Xilinx aarch64 is caught in the general xilinx arm job, exclude from
the general aarch64 job.
- Give the generic aarch64 job a better name
- Re-sort the PowerPC jobs so that we can complete them a bit quicker.
Tom Rini [Thu, 10 May 2018 11:15:52 +0000 (07:15 -0400)]
at91: Minor tweaks to SPL logic for space savings on smartweb
- spl_board_init is empty on smartweb so drop that function
- When CONFIG_AT91SAM9_WATCHDOG is set we do not disable the watchdog in
SPL and instead let full U-Boot handle it. Instead of an empty
function just do not call a function.
Marek Vasut [Wed, 2 May 2018 10:09:23 +0000 (12:09 +0200)]
ARM: rmobile: Unify Gen2 Makefile entry
Drop per-SoC Makefile entries and replace them with one unified entry
now that the PFC tables are gone. Shuffle the Makefile around a bit
to make it more organized.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Mon, 30 Apr 2018 12:10:36 +0000 (14:10 +0200)]
ARM: rmobile: Update V2H Blanche
The V2H Blanche port was broken since some time. This patch updates
the V2H Blanche port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Michal Simek [Fri, 18 May 2018 11:15:08 +0000 (13:15 +0200)]
arm64: zynqmp: Use DWC3 generic driver and DM_USB
Remove harcoded XHCI lists and detect mode, speed based on DT.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Serial-changes: 2
- Remove also XHCI macros from hardware.h
- Remove additional new line in zcu106
Michal Simek [Fri, 18 May 2018 11:15:06 +0000 (13:15 +0200)]
usb: dwc3: Add generic DWC3 glue logic driver
By enabling BLK by default this is the next driver which needs to get
support for DM_USB. Adding generic DWC3 glue logic which only
parse nodes and read device mode. Based on it probe proper
host/peripheral DWC3 drivers for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mugunthan V N [Fri, 18 May 2018 11:15:05 +0000 (13:15 +0200)]
usb: common: add support to get maximum speed from dt
Add support to get maximum speed from dt so that usb drivers
makes use of it for DT parsing.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
(rebase and fix errors) Reviewed-by: Simon Glass <sjg@chromium.org>
Mugunthan V N [Fri, 18 May 2018 11:15:04 +0000 (13:15 +0200)]
usb: dwc3: Add dwc3_init/remove with DM_USB
The patch is preparing dwc3 core for enabling DM_USB with peripheral
driver with using driver model support.
The driver will be bound by the DWC3 wrapper driver based on the
dr_mode device tree entry.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
(Remove dwc3-omap changes) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds phy tranceiver driver for STM32 USB PHY
Controller (usbphyc) that provides dual port High-Speed
phy for OTG (single port) and EHCI/OHCI host controller
(two ports).
One port of the phy is shared between the two USB controllers
through a UTMI+ switch.
Seung-Woo Kim [Thu, 10 May 2018 01:52:15 +0000 (10:52 +0900)]
gadget: f_thor: update to support more than 4GB file as thor 5.0
During file download, it only uses 32bit variable for file size and
it limits maximum file size less than 4GB. Update to support more
than 4GB file with using two 32bit variables for file size as thor
protocol 5.0.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Seung-Woo Kim [Thu, 10 May 2018 01:52:14 +0000 (10:52 +0900)]
gadget: f_thor: fix filename overflow
The thor sender can send filename without null character and it is
used without consideration of overflow. Actually, character array
for filename is assigned with DEFINE_CACHE_ALIGN_BUFFER() and it
is bigger than size of memcpy, so there was no real overflow.
Fix filename overflow for code level integrity.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is
accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch
conditional build in order this file can by shared across other SOCFPGAs.
Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Tien Fong Chee [Tue, 5 Dec 2017 07:58:01 +0000 (15:58 +0800)]
ARM: socfpga: Add DRAM bank size initialization function
Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every single
SOCFPGA board.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Tested-by: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 23 Apr 2018 20:49:31 +0000 (22:49 +0200)]
ARM: socfpga: Repair A10 EMAC reset handling
The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
The A10 clock manager parsed DT bindings generated by Quartus the
bsp-editor to configure the A10 clocks. Sadly, those DT bindings
changed at some point. The clock manager patch used the old ones,
this patch replaces the bindings parser with one for the new set.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
Marek Vasut [Sat, 12 May 2018 09:56:10 +0000 (11:56 +0200)]
fdt: Add another Altera Arria10 clock init compatible
The DT bindings for the Arria10 clock init have changed, add another
compatible to make them work with U-Boot until a proper clock driver
gets written.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:43 +0000 (16:26 +0200)]
sandbox: tests: Add tests for mc34708 PMIC device
Following tests has been added for mc34708 device:
- get_test for mc34708 PMIC
- Check if proper number of registers is read
- Check if default (emulated via i2c device) value is properly read
- Check if value write/read operation is correct
- Perform tests to check if pmic_clrsetbits() is working correctly
Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:38 +0000 (16:26 +0200)]
pmic: Rewrite the pmic command to not only work with single byte transmission
Up till now it was only possible to use 'pmic' command with a single byte
transmission.
The pmic_read|write functions has been replaced with ones, which don't need
the transmission length as a parameter.
Due to that it is possible now to read data from PMICs transmitting more
data than 1 byte at once (e.g. mc34708)
Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
projects / u-boot / log