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--- /dev/null
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--- /dev/null
+TOOL_CHAIN=KPIT GNURX-ELF Toolchain
+VERSION=v15.01
+TC_INSTALL=C:\Program Files (x86)\KPIT\GNURXv15.01-ELF\rx-elf\rx-elf\
+GCC_STRING=4.8-GNURX_v15.01
+VERSION_IDE=
+E2STUDIO_VERSION=4.0.2.008
+ACTIVE_CONFIGURATION=HardwareDebug
\ No newline at end of file
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>RTOSDemo</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>com.renesas.cdt.core.genmakebuilder</name>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
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+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <triggers>full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
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+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ </natures>\r
+ <linkedResources>\r
+ <link>\r
+ <name>src/FreeRTOS_Source</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Source</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>src/Full_Demo/Standard_Demo_Tasks</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>src/Full_Demo/Standard_Demo_Tasks/include</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_ROOT/FreeRTOS/Demo/Common/include</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+ <filteredResources>\r
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+ </matcher>\r
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+ </matcher>\r
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+ <arguments>1.0-name-matches-false-false-RX100</arguments>\r
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+ <arguments>1.0-name-matches-false-false-heap_4.c</arguments>\r
+ </matcher>\r
+ </filter>\r
+ </filteredResources>\r
+ <variableList>\r
+ <variable>\r
+ <name>FREERTOS_ROOT</name>\r
+ <value>$%7BPARENT-3-PROJECT_LOC%7D</value>\r
+ </variable>\r
+ </variableList>\r
+</projectDescription>\r
--- /dev/null
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+Use\ existing\ dependencies\ during\ project\ build=false\r
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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+\r
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+ <name>Debug</name>\r
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+ <name>DDFFile</name>\r
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+ <state>0</state>\r
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+ <archiveVersion>4</archiveVersion>\r
+ <data>\r
+ <version>4</version>\r
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+ <debug>1</debug>\r
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+ <name>EmuMandatory</name>\r
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+ <name>OCEmuUseUSBSerialNo</name>\r
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+ <state>0</state>\r
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+ <option>\r
+ <name>E20LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
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+ <state>0</state>\r
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+ <data>\r
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+ <wantNonLocal>1</wantNonLocal>\r
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+ <name>E2LiteDoLogfile</name>\r
+ <state>0</state>\r
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+ <archiveVersion>4</archiveVersion>\r
+ <data>\r
+ <version>5</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
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+ <state>0</state>\r
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+ <state>0</state>\r
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+ <state>0</state>\r
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+ <state></state>\r
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+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
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+ <state>1</state>\r
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+ <name>SimEnablePSP</name>\r
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+ <option>\r
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+ <state>$TOOLKIT_DIR$\CONFIG\iocf.psp.config</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
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+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
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+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
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+ <loadFlag>0</loadFlag>\r
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+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
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+ </plugin>\r
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+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
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+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
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+ </debuggerPlugins>\r
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+ <configuration>\r
+ <name>Release</name>\r
+ <toolchain>\r
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+ <state>0</state>\r
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+ <name>ODebuggerFpu</name>\r
+ <state>0</state>\r
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+ <name>RXEMUE20</name>\r
+ <archiveVersion>4</archiveVersion>\r
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+ <version>4</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
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+ <option>\r
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+ <name>OCEmuUseUSBSerialNo</name>\r
+ <state>0</state>\r
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+ <name>OCDownloadOnlyChangedBlocks</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>E20LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>E20DoLogfile</name>\r
+ <state>0</state>\r
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+ </data>\r
+ </settings>\r
+ <settings>\r
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+ <archiveVersion>1</archiveVersion>\r
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+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
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+ <option>\r
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+ <state>1</state>\r
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+ <name>E2LiteUseUSBSerialNo</name>\r
+ <state>0</state>\r
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+ <name>E2LiteUSBSerialNo</name>\r
+ <state></state>\r
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+ <name>E2LiteDownloadSuppressDownload</name>\r
+ <state>0</state>\r
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+ <name>E2LiteDownloadVerifyAll</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>E2LiteDownloadAttach</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>E2LiteDebuggingMode</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>E2LiteDownloadExcecuteAfterFlash</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>E2LiteDownloadOnlyChangedBlocks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>E2LiteLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>E2LiteDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RXJLINK</name>\r
+ <archiveVersion>4</archiveVersion>\r
+ <data>\r
+ <version>5</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>JlinkMandatory</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>OCJlinkDownloadSuppressDownload</name>\r
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+ <option>\r
+ <name>OCJlinkDownloadVerifyAll</name>\r
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+ <name>OCDownloadAttach</name>\r
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+ <option>\r
+ <name>OCDebuggingMode</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>OCJlinkExcecuteAfterFlash</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkScanChainEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkDevicePosition</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkOtherDeviceTypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkPreceedingIRBits</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkUseUSBSerialNo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJlinkUSBSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>SIMRX</name>\r
+ <archiveVersion>1</archiveVersion>\r
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+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
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+ <name>SimMandatory</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>SimEnablePSP</name>\r
+ <state>0</state>\r
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+ <option>\r
+ <name>SimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>SimPspConfigFile</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
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+ <name>Debug</name>\r
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+ <name>RX</name>\r
+ </toolchain>\r
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+ <name>OGChipSelectMenu</name>\r
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+ <name>GenCodeModel</name>\r
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+ <state>Use the normal configuration of the C/EC++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+ </option>\r
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+ <name>GenRTConfigPath</name>\r
+ <state>$TOOLKIT_DIR$\LIB\dlrxdllsn.h</state>\r
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+ <name>HeapSize</name>\r
+ <state>0x4</state>\r
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+ <name>GenIntSize</name>\r
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+ <name>GenRwpi</name>\r
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+ <name>ICCRX</name>\r
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+ <name>IccGenerateDebugInfo</name>\r
+ <state>1</state>\r
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+ <name>IccOutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
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+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
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+ <name>PreInclude</name>\r
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+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$\src\cg_src</state>\r
+ <state>$PROJ_DIR$\src</state>\r
+ <state>$PROJ_DIR$\..\..\Source\include</state>\r
+ <state>$PROJ_DIR$\..\..\Source\portable\IAR\RX100</state>\r
+ <state>$PROJ_DIR$\..\Common\include</state>\r
+ <state>$PROJ_DIR$\src\Full_Demo</state>\r
+ </option>\r
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+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
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+ <state>0</state>\r
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+ <state></state>\r
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+ <state>100</state>\r
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+ <name>AsmListIncludeHeaderSource</name>\r
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+ <option>\r
+ <name>OOCObjCopyEnable</name>\r
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+ </data>\r
+ </settings>\r
+ <settings>\r
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+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ <hasPrio>0</hasPrio>\r
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+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
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+ </settings>\r
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+ <prebuild></prebuild>\r
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+ <state>1</state>\r
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+ </option>\r
+ <option>\r
+ <name>AsmIncludePath</name>\r
+ <state>$TOOLKIT_DIR$\INC\</state>\r
+ </option>\r
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+ </option>\r
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+ <name>AsmPreprocLine</name>\r
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+ <state></state>\r
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+ <option>\r
+ <name>AsmDiagnosticsWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDiagnosticsError</name>\r
+ <state></state>\r
+ </option>\r
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+ <state>0</state>\r
+ </option>\r
+ <option>\r
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+ <state>0</state>\r
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+ <option>\r
+ <name>AsmMaxNumberOfErrors</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmProcessor</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmObjPrefix</name>\r
+ <state>1</state>\r
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+ <option>\r
+ <name>AsmOutputFile</name>\r
+ <state>$FILE_BNAME$.r54</state>\r
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+ <option>\r
+ <name>AsmByteOrder</name>\r
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+ <name>AsmUseExtraOptions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDataModel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmDoubleSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmStdIncludeIgnore2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmIntSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmPosIndRopi</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmCpuCore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AsmCpuPatch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AsmListIncludeHeaderSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>OBJCOPY</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>OOCOutputFormat</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCOutputOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCOutputFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OOCCommandLineProducer</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCObjCopyEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ <hasPrio>0</hasPrio>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ILINK</name>\r
+ <archiveVersion>4</archiveVersion>\r
+ <data>\r
+ <version>6</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>IlinkLibIOConfig</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>XLinkMisraHandler</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkInputFileSlave</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOutputFile</name>\r
+ <state>$PROJ_FNAME$.out</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkDebugInfoEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkKeepSymbols</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinaryFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinarySymbol</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinarySegment</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkRawBinaryAlign</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkConfigDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkMapFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogInitialization</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogModule</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogSection</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogVeneer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfFile</name>\r
+ <state>lnk0t.icf</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIcfFileSlave</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkSuppressDiags</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsRem</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsWarn</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkTreatAsErr</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkWarningsAreErrors</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkUStackSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkIStackSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkHeapSize</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkUseExtraOptions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAutoLibEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkAdditionalLibs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOverrideProgramEntryLabel</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabelSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkProgramEntryLabel</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoFill</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerByte</name>\r
+ <state>0xFF</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerStart</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>FillerEnd</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcSize</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlign</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcPoly</name>\r
+ <state>0x11021</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcCompl</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcBitOrder</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcInitialValue</name>\r
+ <state>0x0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoCrc</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcFullSize</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCspyDebugSupportEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCspyBufferedWrite</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogAutoLibSelect</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogRedirSymbols</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkLogUnusedFragments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkSubnormal</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcReverseByteOrder</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkCrcUseAsInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptInline</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptMergeDuplSections</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptUseVfe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkOptForceVfe</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcAlgorithm</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CrcUnitSize</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkThreadsSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackAnalysisEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackControlFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IlinkStackCallGraphFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARCHIVE</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>0</debug>\r
+ <option>\r
+ <name>IarchiveInputs</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IarchiveOutput</name>\r
+ <state>###Unitialized###</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BILINK</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ </configuration>\r
+ <group>\r
+ <name>Blinky_Demo</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\Blinky_Demo\main_blinky.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>cg_src</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\cg_src\r_cg_cgc.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\cg_src\r_cg_hardware_setup.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\cg_src\r_cg_port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\cg_src\r_cg_sci.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>FreeRTOS_Source</name>\r
+ <group>\r
+ <name>portable</name>\r
+ <group>\r
+ <name>MemMang</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\RX100\port.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\portable\IAR\RX100\port_asm.s</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\event_groups.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Full_Demo</name>\r
+ <group>\r
+ <name>Standard_Demo_Tasks</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\countsem.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\death.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\dynamic.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\flop.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\IntQueue.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\IntSemTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\TaskNotify.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\Common\Minimal\TimerDemo.c</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\Full_Demo\IntQueueTimer.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\Full_Demo\main_full.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\Full_Demo\RegTest_IAR.s</name>\r
+ </file>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\FreeRTOSConfig.h</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\src\rskrx113def.h</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
--- /dev/null
+################################################################################\r
+# Automatically-generated file. Do not edit!\r
+################################################################################\r
+\r
+PATH := $(PATH):C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\bin;C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\libexec\gcc\rx-elf\4.8-GNURX_v15.01
\ No newline at end of file
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM\r
+@REM Read about available command line parameters in the C-SPY Debugging\r
+@REM Guide. Hints about additional command line parameters that may be\r
+@REM useful in specific cases:\r
+@REM --download_only Downloads a code image without starting a debug\r
+@REM session afterwards.\r
+@REM --silent Omits the sign-on message.\r
+@REM --timeout Limits the maximum allowed execution time.\r
+@REM \r
+\r
+\r
+@echo off \r
+\r
+if not "%1" == "" goto debugFile \r
+\r
+@echo on \r
+\r
+"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.driver.xcl" \r
+\r
+@echo off \r
+goto end \r
+\r
+:debugFile \r
+\r
+@echo on \r
+\r
+"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.driver.xcl" \r
+\r
+@echo off \r
+:end
\ No newline at end of file
--- /dev/null
+ -B \r
+\r
+"-p" \r
+\r
+"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\config\debugger\ior5f51138.ddf" \r
+\r
+"--endian" \r
+\r
+"l" \r
+\r
+"--double" \r
+\r
+"64" \r
+\r
+"--core" \r
+\r
+"rxv1" \r
+\r
+"--int" \r
+\r
+"32" \r
+\r
+"--no_fpu" \r
+\r
+"-d" \r
+\r
+"emue20" \r
+\r
+"--drv_mode" \r
+\r
+"debugging" \r
+\r
+"--drv_communication" \r
+\r
+"USB" \r
+\r
+\r
+\r
+\r
--- /dev/null
+"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxproc.dll" \r
+\r
+"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxe1e20.dll" \r
+\r
+"C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\Debug\Exe\RTOSDemo.out" \r
+\r
+--plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxbat.dll" \r
+\r
+\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+ <Desktop>\r
+ <Static>\r
+ <Debug-Log>\r
+ <ColumnWidth0>20</ColumnWidth0>\r
+ <ColumnWidth1>1622</ColumnWidth1>\r
+ </Debug-Log>\r
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--- /dev/null
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+\r
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+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Blinky_Demo</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS_Source/portable</ExpandedNode><ExpandedNode>RTOSDemo/Full_Demo</ExpandedNode><ExpandedNode>RTOSDemo/Full_Demo/Standard_Demo_Tasks</ExpandedNode><ExpandedNode>RTOSDemo/cg_src</ExpandedNode></NodeDict></Session>\r
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+ <Top><Row0><Sizes><Toolbar-012083D8><key>iaridepm.enu1</key></Toolbar-012083D8></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>627</Bottom><Right>400</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>239286</sizeVertCX><sizeVertCY>639228</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>313</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>315</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>320122</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
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--- /dev/null
+[MainWindow]\r
+WindowPlacement=_ 519 0 1619 872 3\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds...and so on.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles an LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Renesas includes. */\r
+#include <rskrx113def.h>\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_userdefine.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in\r
+ * main.c.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static QueueHandle_t xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ NULL, /* The parameter passed to the task - not used in this case. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+const unsigned long ulExpectedValue = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == ulExpectedValue )\r
+ {\r
+ LED0 = !LED0;\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#ifdef __ICCRX__\r
+ #include <iorx113.h>\r
+ #include <machine.h>\r
+#endif\r
+\r
+#ifdef __GNUC__\r
+ #include "iodefine.h"\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ ( 32000000 ) /* Set in mcu_info.h. */\r
+#define configPERIPHERAL_CLOCK_HZ ( 32000000 ) /* Set in muc_info.h. */\r
+#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 125 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+\r
+#define configMAX_PRIORITIES ( 7 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+\r
+/* The interrupt priority used by the kernel itself for the tick interrupt and\r
+the pended interrupt. This would normally be the lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+\r
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
+Interrupts that use a priority above this will not be effected by anything the\r
+kernel is doing. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros\r
+allow the application writer to add additional code before and after the MCU is\r
+placed into the low power state respectively. The implementations provided in\r
+this demo can be extended to save even more power - for example the analog\r
+input used by the low power demo could be switched off in the pre-sleep macro\r
+and back on again in the post sleep macro. */\r
+void vPreSleepProcessing( unsigned long xExpectedIdleTime );\r
+void vPostSleepProcessing( unsigned long xExpectedIdleTime );\r
+#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime );\r
+#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime );\r
+\r
+/* configTICK_VECTOR must be set to the interrupt vector used by the peripheral\r
+that generates the tick interrupt. */\r
+#define configTICK_VECTOR VECT_CMT0_CMI0\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * This file contains the non-portable and therefore RX62N specific parts of\r
+ * the IntQueue standard demo task - namely the configuration of the timers\r
+ * that generate the interrupts and the interrupt entry points.\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+#define tmrTIMER_0_1_FREQUENCY ( 2000UL )\r
+#define tmrTIMER_2_3_FREQUENCY ( 2111UL )\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+ /* Ensure interrupts do not start until full configuration is complete. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ /* Give write access. */\r
+ SYSTEM.PRCR.WORD = 0xa502;\r
+\r
+ /* Cascade two 8bit timer channels to generate the interrupts.\r
+ 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are\r
+ utilised for this test. */\r
+\r
+ /* Enable the timers. */\r
+ SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;\r
+ SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;\r
+\r
+ /* Enable compare match A interrupt request. */\r
+ TMR0.TCR.BIT.CMIEA = 1;\r
+ TMR2.TCR.BIT.CMIEA = 1;\r
+\r
+ /* Clear the timer on compare match A. */\r
+ TMR0.TCR.BIT.CCLR = 1;\r
+ TMR2.TCR.BIT.CCLR = 1;\r
+\r
+ /* Set the compare match value. */\r
+ TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
+ TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
+\r
+ /* 16 bit operation ( count from timer 1,2 ). */\r
+ TMR0.TCCR.BIT.CSS = 3;\r
+ TMR2.TCCR.BIT.CSS = 3;\r
+\r
+ /* Use PCLK as the input. */\r
+ TMR1.TCCR.BIT.CSS = 1;\r
+ TMR3.TCCR.BIT.CSS = 1;\r
+\r
+ /* Divide PCLK by 8. */\r
+ TMR1.TCCR.BIT.CKS = 2;\r
+ TMR3.TCCR.BIT.CKS = 2;\r
+\r
+ /* Enable TMR 0, 2 interrupts. */\r
+ TMR0.TCR.BIT.CMIEA = 1;\r
+ TMR2.TCR.BIT.CMIEA = 1;\r
+\r
+ /* Set interrupt priority and enable. */\r
+ IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
+ IR( TMR0, CMIA0 ) = 0U;\r
+ IEN( TMR0, CMIA0 ) = 1U;\r
+\r
+ /* Do the same for TMR2, but to vector 129. */\r
+ IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;\r
+ IR( TMR2, CMIA2 ) = 0U;\r
+ IEN( TMR2, CMIA2 ) = 1U;\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __GNUC__\r
+\r
+ void vIntQTimerISR0( void ) __attribute__ ((interrupt));\r
+ void vIntQTimerISR1( void ) __attribute__ ((interrupt));\r
+\r
+ void vIntQTimerISR0( void )\r
+ {\r
+ /* Enable interrupts to allow interrupt nesting. */\r
+ __asm volatile( "setpsw i" );\r
+\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+\r
+ void vIntQTimerISR1( void )\r
+ {\r
+ /* Enable interrupts to allow interrupt nesting. */\r
+ __asm volatile( "setpsw i" );\r
+\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+ }\r
+\r
+#endif /* __GNUC__ */\r
+\r
+#ifdef __ICCRX__\r
+\r
+#pragma vector = VECT_TMR0_CMIA0\r
+__interrupt void vT0_1InterruptHandler( void )\r
+{\r
+ __enable_interrupt();\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma vector = VECT_TMR2_CMIA2\r
+__interrupt void vT2_3InterruptHandler( void )\r
+{\r
+ __enable_interrupt();\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+}\r
+\r
+#endif /* __ICCRX__ */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+portBASE_TYPE xTimer0Handler( void );\r
+portBASE_TYPE xTimer1Handler( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+;/*\r
+; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+; All rights reserved\r
+;\r
+; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * FreeRTOS provides completely free yet professionally developed, *\r
+; * robust, strictly quality controlled, supported, and cross *\r
+; * platform software that has become a de facto standard. *\r
+; * *\r
+; * Help yourself get started quickly and support the FreeRTOS *\r
+; * project by purchasing a FreeRTOS tutorial book, reference *\r
+; * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+; * *\r
+; * Thank you! *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+; This file is part of the FreeRTOS distribution.\r
+;\r
+; FreeRTOS is free software; you can redistribute it and/or modify it under\r
+; the terms of the GNU General Public License (version 2) as published by the\r
+; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+;\r
+; >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+; >>! a combined work that includes FreeRTOS without being obliged to provide\r
+; >>! the source code for proprietary components outside of the FreeRTOS\r
+; >>! kernel.\r
+;\r
+; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+; FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+; link: http://www.freertos.org/a00114.html\r
+;\r
+; 1 tab == 4 spaces!\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * Having a problem? Start by reading the FAQ "My application does *\r
+; * not run, what could be wrong?" *\r
+; * *\r
+; * http://www.FreeRTOS.org/FAQHelp.html *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+; http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+; license and Real Time Engineers Ltd. contact details.;\r
+;\r
+; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+; including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+; compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+;\r
+; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+; licenses offer ticketed support, indemnification and middleware.\r
+;\r
+; http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+; engineered and independently SIL3 certified version for use in safety and\r
+; mission critical applications that require provable dependability.\r
+;\r
+; 1 tab == 4 spaces!\r
+;*/\r
+\r
+ .global _vRegTest1Implementation\r
+ .global _vRegTest2Implementation\r
+\r
+ .extern _ulRegTest1LoopCounter\r
+ .extern _ulRegTest2LoopCounter\r
+\r
+ .text\r
+\r
+\r
+;/* This function is explained in the comments at the top of main.c. */\r
+_vRegTest1Implementation:\r
+\r
+ ; Put a known value in each register.\r
+ MOV.L #1, R1\r
+ MOV.L #2, R2\r
+ MOV.L #3, R3\r
+ MOV.L #4, R4\r
+ MOV.L #5, R5\r
+ MOV.L #6, R6\r
+ MOV.L #7, R7\r
+ MOV.L #8, R8\r
+ MOV.L #9, R9\r
+ MOV.L #10, R10\r
+ MOV.L #11, R11\r
+ MOV.L #12, R12\r
+ MOV.L #13, R13\r
+ MOV.L #14, R14\r
+ MOV.L #15, R15\r
+\r
+ ; Loop, checking each itteration that each register still contains the\r
+ ; expected value.\r
+TestLoop1:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest1LoopCounter, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register.\r
+ MOV.L #1, R14\r
+ MOV.L #0872E0H, R15\r
+ MOV.B R14, [R15]\r
+ NOP\r
+ NOP\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ ; Now compare each register to ensure it still contains the value that was\r
+ ; set before this loop was entered.\r
+ CMP #1, R1\r
+ BNE RegTest1Error\r
+ CMP #2, R2\r
+ BNE RegTest1Error\r
+ CMP #3, R3\r
+ BNE RegTest1Error\r
+ CMP #4, R4\r
+ BNE RegTest1Error\r
+ CMP #5, R5\r
+ BNE RegTest1Error\r
+ CMP #6, R6\r
+ BNE RegTest1Error\r
+ CMP #7, R7\r
+ BNE RegTest1Error\r
+ CMP #8, R8\r
+ BNE RegTest1Error\r
+ CMP #9, R9\r
+ BNE RegTest1Error\r
+ CMP #10, R10\r
+ BNE RegTest1Error\r
+ CMP #11, R11\r
+ BNE RegTest1Error\r
+ CMP #12, R12\r
+ BNE RegTest1Error\r
+ CMP #13, R13\r
+ BNE RegTest1Error\r
+ CMP #14, R14\r
+ BNE RegTest1Error\r
+ CMP #15, R15\r
+ BNE RegTest1Error\r
+\r
+ ; All comparisons passed, start a new itteratio of this loop.\r
+ BRA TestLoop1\r
+\r
+RegTest1Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; causing the check task to indicate the error.\r
+ BRA RegTest1Error\r
+;/*-----------------------------------------------------------*/\r
+\r
+;/* This function is explained in the comments at the top of main.c. */\r
+_vRegTest2Implementation:\r
+\r
+ ; Put a known value in each register.\r
+ MOV.L #10, R1\r
+ MOV.L #20, R2\r
+ MOV.L #30, R3\r
+ MOV.L #40, R4\r
+ MOV.L #50, R5\r
+ MOV.L #60, R6\r
+ MOV.L #70, R7\r
+ MOV.L #80, R8\r
+ MOV.L #90, R9\r
+ MOV.L #100, R10\r
+ MOV.L #110, R11\r
+ MOV.L #120, R12\r
+ MOV.L #130, R13\r
+ MOV.L #140, R14\r
+ MOV.L #150, R15\r
+\r
+ ; Loop, checking on each itteration that each register still contains the\r
+ ; expected value.\r
+TestLoop2:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest2LoopCounter, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ CMP #10, R1\r
+ BNE RegTest2Error\r
+ CMP #20, R2\r
+ BNE RegTest2Error\r
+ CMP #30, R3\r
+ BNE RegTest2Error\r
+ CMP #40, R4\r
+ BNE RegTest2Error\r
+ CMP #50, R5\r
+ BNE RegTest2Error\r
+ CMP #60, R6\r
+ BNE RegTest2Error\r
+ CMP #70, R7\r
+ BNE RegTest2Error\r
+ CMP #80, R8\r
+ BNE RegTest2Error\r
+ CMP #90, R9\r
+ BNE RegTest2Error\r
+ CMP #100, R10\r
+ BNE RegTest2Error\r
+ CMP #110, R11\r
+ BNE RegTest2Error\r
+ CMP #120, R12\r
+ BNE RegTest2Error\r
+ CMP #130, R13\r
+ BNE RegTest2Error\r
+ CMP #140, R14\r
+ BNE RegTest2Error\r
+ CMP #150, R15\r
+ BNE RegTest2Error\r
+\r
+ ; All comparisons passed, start a new itteratio of this loop.\r
+ BRA TestLoop2\r
+\r
+RegTest2Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; - causing the check task to indicate the error.\r
+ BRA RegTest2Error\r
+ \r
+ .END\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+ PUBLIC _vRegTest1Implementation\r
+ PUBLIC _vRegTest2Implementation\r
+\r
+ EXTERN _ulRegTest1CycleCount\r
+ EXTERN _ulRegTest2CycleCount\r
+\r
+ RSEG CODE:CODE(4)\r
+\r
+_vRegTest1Implementation:\r
+\r
+ /* Set each register to a known value. */\r
+ MOV.L #0x33333333, R15\r
+ MVTACHI R15\r
+ MOV.L #0x44444444, R15\r
+ MVTACLO R15\r
+ MOV.L #1, R1\r
+ MOV.L #2, R2\r
+ MOV.L #3, R3\r
+ MOV.L #4, R4\r
+ MOV.L #5, R5\r
+ MOV.L #6, R6\r
+ MOV.L #7, R7\r
+ MOV.L #8, R8\r
+ MOV.L #9, R9\r
+ MOV.L #10, R10\r
+ MOV.L #11, R11\r
+ MOV.L #12, R12\r
+ MOV.L #13, R13\r
+ MOV.L #14, R14\r
+ MOV.L #15, R15\r
+\r
+ /* Loop, checking each iteration that each register still contains the\r
+ expected value. */\r
+ TestLoop1:\r
+\r
+ /* Push the registers that are going to get clobbered. */\r
+ PUSHM R14-R15\r
+\r
+ /* Increment the loop counter to show this task is still getting CPU\r
+ time. */\r
+ MOV.L #_ulRegTest1CycleCount, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ /* Yield to extend the text coverage. Set the bit in the ITU SWINTR\r
+ register. */\r
+ MOV.L #1, R14\r
+ MOV.L #0872E0H, R15\r
+ MOV.B R14, [R15]\r
+ NOP\r
+ NOP\r
+\r
+ /* Check the accumulator value. */\r
+ MVFACHI R15\r
+ CMP #0x33333333, R15\r
+ BNE RegTest2Error\r
+ MVFACMI R15\r
+ CMP #0x33334444, R15\r
+ BNE RegTest2Error\r
+\r
+ /* Restore the clobbered registers. */\r
+ POPM R14-R15\r
+\r
+ /* Now compare each register to ensure it still contains the value that\r
+ was set before this loop was entered. */\r
+ CMP #1, R1\r
+ BNE RegTest1Error\r
+ CMP #2, R2\r
+ BNE RegTest1Error\r
+ CMP #3, R3\r
+ BNE RegTest1Error\r
+ CMP #4, R4\r
+ BNE RegTest1Error\r
+ CMP #5, R5\r
+ BNE RegTest1Error\r
+ CMP #6, R6\r
+ BNE RegTest1Error\r
+ CMP #7, R7\r
+ BNE RegTest1Error\r
+ CMP #8, R8\r
+ BNE RegTest1Error\r
+ CMP #9, R9\r
+ BNE RegTest1Error\r
+ CMP #10, R10\r
+ BNE RegTest1Error\r
+ CMP #11, R11\r
+ BNE RegTest1Error\r
+ CMP #12, R12\r
+ BNE RegTest1Error\r
+ CMP #13, R13\r
+ BNE RegTest1Error\r
+ CMP #14, R14\r
+ BNE RegTest1Error\r
+ CMP #15, R15\r
+ BNE RegTest1Error\r
+\r
+ /* All comparisons passed, start a new iteration of this loop. */\r
+ BRA TestLoop1\r
+\r
+ /* A compare failed, just loop here so the loop counter stops\r
+ incrementing causing the check timer to indicate the error. */\r
+ RegTest1Error:\r
+ BRA RegTest1Error\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+_vRegTest2Implementation:\r
+\r
+ /* Set each register to a known value. */\r
+ MOV.L #0x11111111, R15\r
+ MVTACHI R15\r
+ MOV.L #0x22222222, R15\r
+ MVTACLO R15\r
+ MOV.L #100, R1\r
+ MOV.L #200, R2\r
+ MOV.L #300, R3\r
+ MOV.L #400, R4\r
+ MOV.L #500, R5\r
+ MOV.L #600, R6\r
+ MOV.L #700, R7\r
+ MOV.L #800, R8\r
+ MOV.L #900, R9\r
+ MOV.L #1000, R10\r
+ MOV.L #1001, R11\r
+ MOV.L #1002, R12\r
+ MOV.L #1003, R13\r
+ MOV.L #1004, R14\r
+ MOV.L #1005, R15\r
+\r
+ /* Loop, checking each iteration that each register still contains the\r
+ expected value. */\r
+ TestLoop2:\r
+\r
+ /* Push the registers that are going to get clobbered. */\r
+ PUSHM R14-R15\r
+\r
+ /* Increment the loop counter to show this task is still getting CPU\r
+ time. */\r
+ MOV.L #_ulRegTest2CycleCount, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ /* Check the accumulator value. */\r
+ MVFACHI R15\r
+ CMP #0x11111111, R15\r
+ BNE RegTest2Error\r
+ MVFACMI R15\r
+ CMP #0x11112222, R15\r
+ BNE RegTest2Error\r
+\r
+ /* Restore the clobbered registers. */\r
+ POPM R14-R15\r
+\r
+ /* Now compare each register to ensure it still contains the value that\r
+ was set before this loop was entered. */\r
+ CMP #100, R1\r
+ BNE RegTest2Error\r
+ CMP #200, R2\r
+ BNE RegTest2Error\r
+ CMP #300, R3\r
+ BNE RegTest2Error\r
+ CMP #400, R4\r
+ BNE RegTest2Error\r
+ CMP #500, R5\r
+ BNE RegTest2Error\r
+ CMP #600, R6\r
+ BNE RegTest2Error\r
+ CMP #700, R7\r
+ BNE RegTest2Error\r
+ CMP #800, R8\r
+ BNE RegTest2Error\r
+ CMP #900, R9\r
+ BNE RegTest2Error\r
+ CMP #1000, R10\r
+ BNE RegTest2Error\r
+ CMP #1001, R11\r
+ BNE RegTest2Error\r
+ CMP #1002, R12\r
+ BNE RegTest2Error\r
+ CMP #1003, R13\r
+ BNE RegTest2Error\r
+ CMP #1004, R14\r
+ BNE RegTest2Error\r
+ CMP #1005, R15\r
+ BNE RegTest2Error\r
+\r
+ /* All comparisons passed, start a new iteration of this loop. */\r
+ BRA TestLoop2\r
+\r
+ /* A compare failed, just loop here so the loop counter stops\r
+ incrementing causing the check timer to indicate the error. */\r
+ RegTest2Error:\r
+ BRA RegTest2Error\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+ END\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky\r
+ * style project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to\r
+ * select between the two. See the notes on using\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the\r
+ * comprehensive version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ *\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and software timers, then\r
+ * starts the scheduler. The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" task - The check task period is initially set to three seconds. The\r
+ * task checks that all the standard demo tasks, and the register check tasks,\r
+ * are not only still executing, but are executing without reporting any errors.\r
+ * If the check task discovers that a task has either stalled, or reported an\r
+ * error, then it changes its own execution period from the initial three\r
+ * seconds, to just 200ms. The check task also toggles an LED each time it is\r
+ * called. This provides a visual indication of the system status: If the LED\r
+ * toggles every three seconds, then no issues have been discovered. If the LED\r
+ * toggles every 200ms, then an issue has been discovered with at least one\r
+ * task.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "flop.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+#include "serial.h"\r
+#include "TimerDemo.h"\r
+#include "QueueOverwrite.h"\r
+#include "IntQueue.h"\r
+#include "EventGroupsDemo.h"\r
+#include "TaskNotify.h"\r
+#include "IntSemTest.h"\r
+\r
+/* Renesas includes. */\r
+#include <rskrx113def.h>\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_userdefine.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )\r
+#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The priority used by the UART command console task. */\r
+#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )\r
+\r
+/* Parameters that are passed into the register check tasks solely for the\r
+purpose of ensuring parameters are passed into tasks correctly. */\r
+#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL )\r
+#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL )\r
+\r
+/* The base period used by the timer test tasks. */\r
+#define mainTIMER_TEST_PERIOD ( 50 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Entry point for the comprehensive demo (as opposed to the simple blinky\r
+ * demo).\r
+ */\r
+void main_full( void );\r
+\r
+/*\r
+ * The full demo includes some functionality called from the tick hook.\r
+ */\r
+void vFullDemoTickHook( void );\r
+\r
+ /*\r
+ * The check task, as described at the top of this file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the registers, as described at the top of this file. The nature of these\r
+ * files necessitates that they are written in assembly, but the entry points\r
+ * are kept in the C file for the convenience of checking the task parameter.\r
+ */\r
+static void prvRegTest1Task( void *pvParameters );\r
+static void prvRegTest2Task( void *pvParameters );\r
+void vRegTest1Implementation( void );\r
+void vRegTest2Implementation( void );\r
+\r
+/*\r
+ * A high priority task that does nothing other than execute at a pseudo random\r
+ * time to ensure the other test tasks don't just execute in a repeating\r
+ * pattern.\r
+ */\r
+static void prvPseudoRandomiser( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check task. If the variables keep incrementing,\r
+then the register check tasks have not discovered any errors. If a variable\r
+stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/* String for display in the web server. It is set to an error message if the\r
+check task detects an error. */\r
+const char *pcStatusMessage = "All tasks running without error";\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+ /* Start all the other standard demo/test tasks. They have no particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartInterruptQueueTasks();\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+//_RB_ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+ vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );\r
+ vStartEventGroupTasks();\r
+ vStartTaskNotifyTask();\r
+ vStartInterruptSemaphoreTasks();\r
+\r
+ /* Create the register check tasks, as described at the top of this file */\r
+ xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the task that just adds a little random behaviour. */\r
+ xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );\r
+\r
+ /* Create the task that performs the 'check' functionality, as described at\r
+ the top of this file. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* The set of tasks created by the following function call have to be\r
+ created last as they keep account of the number of tasks they expect to see\r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
+TickType_t xLastExecutionTime;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
+ works correctly. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. The onboard LED is toggled on each iteration.\r
+ If an error is detected then the delay period is decreased from\r
+ mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
+ effect of increasing the rate at which the onboard LED toggles, and in so\r
+ doing gives visual feedback of the system status. */\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+ if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 0UL;\r
+ }\r
+\r
+#ifdef _RB_\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 1UL;\r
+ }\r
+#endif\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 2UL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 3UL;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 4UL;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 5UL;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 6UL;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 7UL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 8UL;\r
+ }\r
+\r
+ if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )\r
+ {\r
+ ulErrorFound |= 1UL << 9UL;\r
+ }\r
+\r
+ if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 10UL;\r
+ }\r
+\r
+ if( xIsQueueOverwriteTaskStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= 1UL << 11UL;\r
+ }\r
+\r
+ if( xAreEventGroupTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= 1UL << 12UL;\r
+ }\r
+\r
+ if( xAreTaskNotificationTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 13UL;\r
+ }\r
+\r
+ if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 14UL;\r
+ }\r
+\r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound |= 1UL << 15UL;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound |= 1UL << 16UL;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ LED0 = !LED0;\r
+\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash the LED\r
+ at a higher frequency to give visible feedback that something has\r
+ gone wrong (it might just be that the loop back connector required\r
+ by the comtest tasks has not been fitted). */\r
+ xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
+ pcStatusMessage = "Error found in at least one task.";\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPseudoRandomiser( void *pvParameters )\r
+{\r
+const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS );\r
+volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;\r
+\r
+ /* This task does nothing other than ensure there is a little bit of\r
+ disruption in the scheduling pattern of the other tasks. Normally this is\r
+ done by generating interrupts at pseudo random times. */\r
+ for( ;; )\r
+ {\r
+ ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;\r
+ ulValue = ( ulNextRand >> 16UL ) & 0xffUL;\r
+\r
+ if( ulValue < ulMinDelay )\r
+ {\r
+ ulValue = ulMinDelay;\r
+ }\r
+\r
+ vTaskDelay( ulValue );\r
+\r
+ while( ulValue > 0 )\r
+ {\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+ __asm volatile( "NOP" );\r
+\r
+ ulValue--;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vFullDemoTickHook( void )\r
+{\r
+ /* The full demo includes a software timer demo/test that requires\r
+ prodding periodically from the tick interrupt. */\r
+ vTimerPeriodicISRTests();\r
+\r
+ /* Call the periodic queue overwrite from ISR demo. */\r
+ vQueueOverwritePeriodicISRDemo();\r
+\r
+ /* Call the periodic event group from ISR demo. */\r
+ vPeriodicEventGroupsProcessing();\r
+\r
+ /* Use task notifications from an interrupt. */\r
+ xNotifyTaskFromISR();\r
+\r
+ /* Use mutexes from interrupts. */\r
+ vInterruptSemaphorePeriodicTest();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest1Task( void *pvParameters )\r
+{\r
+ if( pvParameters != mainREG_TEST_1_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ vRegTest1Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest2Task( void *pvParameters )\r
+{\r
+ if( pvParameters != mainREG_TEST_2_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ vRegTest2Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef PRIORITY_DEFINITIONS_H\r
+#define PRIORITY_DEFINITIONS_H\r
+\r
+#ifndef __IASMRX__\r
+ #error This file is only intended to be included from the FreeRTOS IAR port layer assembly file.\r
+#endif\r
+\r
+/* The interrupt priority used by the kernel itself for the tick interrupt and\r
+the pended interrupt. This would normally be the lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+\r
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
+Interrupts that use a priority above this will not be effected by anything the\r
+kernel is doing. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+#endif /* PRIORITY_DEFINITIONS_H */\r
--- /dev/null
+/***************************************************************/\r
+/* */\r
+/* PROJECT NAME : RTOSDemo */\r
+/* FILE : interrupt_handlers.c */\r
+/* DESCRIPTION : Interrupt Handler */\r
+/* CPU SERIES : RX100 */\r
+/* CPU TYPE : RX113 */\r
+/* */\r
+/* This file is generated by e2 studio. */\r
+/* */\r
+/***************************************************************/ \r
+ \r
+ \r
+ \r
+ \r
+/************************************************************************/\r
+/* File Version: V1.1A */\r
+/* History : 1.00 (2013-11-18) [Hardware Manual Revision : 0.40] */\r
+/* : 1.10 (2014-02-26) [Hardware Manual Revision : 0.50] */\r
+/* : 1.1A (2015-04-20) [Hardware Manual Revision : 1.02] */\r
+/* Date Generated: 25/05/2015 */\r
+/************************************************************************/\r
+\r
+#include "interrupt_handlers.h"\r
+\r
+// INT_Exception(Supervisor Instruction)\r
+void INT_Excep_SuperVisorInst(void){/* brk(){ } */}\r
+\r
+// INT_Exception(Undefined Instruction)\r
+void INT_Excep_UndefinedInst(void){/* brk(){ } */}\r
+\r
+// NMI\r
+void INT_NonMaskableInterrupt(void){/* brk(){ } */}\r
+\r
+// Dummy\r
+void INT_Dummy(void){/* brk(){ } */}\r
+\r
+// BRK\r
+void INT_Excep_BRK(void){/* wait();*/ }\r
+\r
+// BSC BUSERR\r
+void INT_Excep_BSC_BUSERR(void){ }\r
+\r
+// FCU FRDYI\r
+void INT_Excep_FCU_FRDYI(void){ }\r
+\r
+// ICU SWINT\r
+void INT_Excep_ICU_SWINT(void){ }\r
+\r
+// CMT0 CMI0\r
+void INT_Excep_CMT0_CMI0(void){ }\r
+\r
+// CMT1 CMI1\r
+void INT_Excep_CMT1_CMI1(void){ }\r
+\r
+// CMT2 CMI2\r
+void INT_Excep_CMT2_CMI2(void){ }\r
+\r
+// CMT3 CMI3\r
+void INT_Excep_CMT3_CMI3(void){ }\r
+\r
+// CAC FERRF\r
+void INT_Excep_CAC_FERRF(void){ }\r
+\r
+// CAC MENDF\r
+void INT_Excep_CAC_MENDF(void){ }\r
+\r
+// CAC OVFF\r
+void INT_Excep_CAC_OVFF(void){ }\r
+\r
+// USB0 D0FIFO0\r
+void INT_Excep_USB0_D0FIFO0(void){ }\r
+\r
+// USB0 D1FIFO0\r
+void INT_Excep_USB0_D1FIFO0(void){ }\r
+\r
+// USB0 USBI0\r
+void INT_Excep_USB0_USBI0(void){ }\r
+\r
+// RSPI0 SPEI0\r
+void INT_Excep_RSPI0_SPEI0(void){ }\r
+\r
+// RSPI0 SPRI0\r
+void INT_Excep_RSPI0_SPRI0(void){ }\r
+\r
+// RSPI0 SPTI0\r
+void INT_Excep_RSPI0_SPTI0(void){ }\r
+\r
+// RSPI0 SPII0\r
+void INT_Excep_RSPI0_SPII0(void){ }\r
+\r
+// DOC DOPCF\r
+void INT_Excep_DOC_DOPCF(void){ }\r
+\r
+// CMPB CMPB0\r
+void INT_Excep_CMPB_CMPB0(void){ }\r
+\r
+// CMPB CMPB1\r
+void INT_Excep_CMPB_CMPB1(void){ }\r
+\r
+// CTSU CTSUWR\r
+void INT_Excep_CTSU_CTSUWR(void){ }\r
+\r
+// CTSU CTSURD\r
+void INT_Excep_CTSU_CTSURD(void){ }\r
+\r
+// CTSU CTSUFN\r
+void INT_Excep_CTSU_CTSUFN(void){ }\r
+\r
+// RTC CUP\r
+void INT_Excep_RTC_CUP(void){ }\r
+\r
+// ICU IRQ0\r
+void INT_Excep_ICU_IRQ0(void){ }\r
+\r
+// ICU IRQ1\r
+void INT_Excep_ICU_IRQ1(void){ }\r
+\r
+// ICU IRQ2\r
+void INT_Excep_ICU_IRQ2(void){ }\r
+\r
+// ICU IRQ3\r
+void INT_Excep_ICU_IRQ3(void){ }\r
+\r
+// ICU IRQ4\r
+void INT_Excep_ICU_IRQ4(void){ }\r
+\r
+// ICU IRQ5\r
+void INT_Excep_ICU_IRQ5(void){ }\r
+\r
+// ICU IRQ6\r
+void INT_Excep_ICU_IRQ6(void){ }\r
+\r
+// ICU IRQ7\r
+void INT_Excep_ICU_IRQ7(void){ }\r
+\r
+// ELC ELSR8I\r
+void INT_Excep_ELC_ELSR8I(void){ }\r
+\r
+// LVD LVD1\r
+void INT_Excep_LVD_LVD1(void){ }\r
+\r
+// LVD LVD2\r
+void INT_Excep_LVD_LVD2(void){ }\r
+\r
+// USB0 USBR0\r
+void INT_Excep_USB0_USBR0(void){ }\r
+\r
+// RTC ALM\r
+void INT_Excep_RTC_ALM(void){ }\r
+\r
+// RTC PRD\r
+void INT_Excep_RTC_PRD(void){ }\r
+\r
+// S12AD S12ADI0\r
+void INT_Excep_S12AD_S12ADI0(void){ }\r
+\r
+// S12AD GBADI\r
+void INT_Excep_S12AD_GBADI(void){ }\r
+\r
+// ELC ELSR18I\r
+void INT_Excep_ELC_ELSR18I(void){ }\r
+\r
+// SSI0 SSIF0\r
+void INT_Excep_SSI0_SSIF0(void){ }\r
+\r
+// SSI0 SSIRXI0\r
+void INT_Excep_SSI0_SSIRXI0(void){ }\r
+\r
+// SSI0 SSITXI0\r
+void INT_Excep_SSI0_SSITXI0(void){ }\r
+\r
+// MTU0 TGIA0\r
+void INT_Excep_MTU0_TGIA0(void){ }\r
+\r
+// MTU0 TGIB0\r
+void INT_Excep_MTU0_TGIB0(void){ }\r
+\r
+// MTU0 TGIC0\r
+void INT_Excep_MTU0_TGIC0(void){ }\r
+\r
+// MTU0 TGID0\r
+void INT_Excep_MTU0_TGID0(void){ }\r
+\r
+// MTU0 TCIV0\r
+void INT_Excep_MTU0_TCIV0(void){ }\r
+\r
+// MTU0 TGIE0\r
+void INT_Excep_MTU0_TGIE0(void){ }\r
+\r
+// MTU0 TGIF0\r
+void INT_Excep_MTU0_TGIF0(void){ }\r
+\r
+// MTU1 TGIA1\r
+void INT_Excep_MTU1_TGIA1(void){ }\r
+\r
+// MTU1 TGIB1\r
+void INT_Excep_MTU1_TGIB1(void){ }\r
+\r
+// MTU1 TCIV1\r
+void INT_Excep_MTU1_TCIV1(void){ }\r
+\r
+// MTU1 TCIU1\r
+void INT_Excep_MTU1_TCIU1(void){ }\r
+\r
+// MTU2 TGIA2\r
+void INT_Excep_MTU2_TGIA2(void){ }\r
+\r
+// MTU2 TGIB2\r
+void INT_Excep_MTU2_TGIB2(void){ }\r
+\r
+// MTU2 TCIV2\r
+void INT_Excep_MTU2_TCIV2(void){ }\r
+\r
+// MTU2 TCIU2\r
+void INT_Excep_MTU2_TCIU2(void){ }\r
+\r
+// MTU3 TGIA3\r
+void INT_Excep_MTU3_TGIA3(void){ }\r
+\r
+// MTU3 TGIB3\r
+void INT_Excep_MTU3_TGIB3(void){ }\r
+\r
+// MTU3 TGIC3\r
+void INT_Excep_MTU3_TGIC3(void){ }\r
+\r
+// MTU3 TGID3\r
+void INT_Excep_MTU3_TGID3(void){ }\r
+\r
+// MTU3 TCIV3\r
+void INT_Excep_MTU3_TCIV3(void){ }\r
+\r
+// MTU4 TGIA4\r
+void INT_Excep_MTU4_TGIA4(void){ }\r
+\r
+// MTU4 TGIB4\r
+void INT_Excep_MTU4_TGIB4(void){ }\r
+\r
+// MTU4 TGIC4\r
+void INT_Excep_MTU4_TGIC4(void){ }\r
+\r
+// MTU4 TGID4\r
+void INT_Excep_MTU4_TGID4(void){ }\r
+\r
+// MTU4 TCIV4\r
+void INT_Excep_MTU4_TCIV4(void){ }\r
+\r
+// MTU5 TGIU5\r
+void INT_Excep_MTU5_TGIU5(void){ }\r
+\r
+// MTU5 TGIV5\r
+void INT_Excep_MTU5_TGIV5(void){ }\r
+\r
+// MTU5 TGIW5\r
+void INT_Excep_MTU5_TGIW5(void){ }\r
+\r
+// POE OEI1\r
+void INT_Excep_POE_OEI1(void){ }\r
+\r
+// POE OEI2\r
+void INT_Excep_POE_OEI2(void){ }\r
+\r
+// TMR0 CMIA0\r
+void INT_Excep_TMR0_CMIA0(void){ }\r
+\r
+// TMR0 CMIB0\r
+void INT_Excep_TMR0_CMIB0(void){ }\r
+\r
+// TMR0 OVI0\r
+void INT_Excep_TMR0_OVI0(void){ }\r
+\r
+// TMR1 CMIA1\r
+void INT_Excep_TMR1_CMIA1(void){ }\r
+\r
+// TMR1 CMIB1\r
+void INT_Excep_TMR1_CMIB1(void){ }\r
+\r
+// TMR1 OVI1\r
+void INT_Excep_TMR1_OVI1(void){ }\r
+\r
+// TMR2 CMIA2\r
+void INT_Excep_TMR2_CMIA2(void){ }\r
+\r
+// TMR2 CMIB2\r
+void INT_Excep_TMR2_CMIB2(void){ }\r
+\r
+// TMR2 OVI2\r
+void INT_Excep_TMR2_OVI2(void){ }\r
+\r
+// TMR3 CMIA3\r
+void INT_Excep_TMR3_CMIA3(void){ }\r
+\r
+// TMR3 CMIB3\r
+void INT_Excep_TMR3_CMIB3(void){ }\r
+\r
+// TMR3 OVI3\r
+void INT_Excep_TMR3_OVI3(void){ }\r
+\r
+// SCI2 ERI2\r
+void INT_Excep_SCI2_ERI2(void){ }\r
+\r
+// SCI2 RXI2\r
+void INT_Excep_SCI2_RXI2(void){ }\r
+\r
+// SCI2 TXI2\r
+void INT_Excep_SCI2_TXI2(void){ }\r
+\r
+// SCI2 TEI2\r
+void INT_Excep_SCI2_TEI2(void){ }\r
+\r
+// SCI0 ERI0\r
+void INT_Excep_SCI0_ERI0(void){ }\r
+\r
+// SCI0 RXI0\r
+void INT_Excep_SCI0_RXI0(void){ }\r
+\r
+// SCI0 TXI0\r
+void INT_Excep_SCI0_TXI0(void){ }\r
+\r
+// SCI0 TEI0\r
+void INT_Excep_SCI0_TEI0(void){ }\r
+\r
+// SCI1 ERI1\r
+void INT_Excep_SCI1_ERI1(void){ }\r
+\r
+// SCI1 RXI1\r
+void INT_Excep_SCI1_RXI1(void){ }\r
+\r
+// SCI1 TXI1\r
+void INT_Excep_SCI1_TXI1(void){ }\r
+\r
+// SCI1 TEI1\r
+void INT_Excep_SCI1_TEI1(void){ }\r
+\r
+// SCI5 ERI5\r
+void INT_Excep_SCI5_ERI5(void){ }\r
+\r
+// SCI5 RXI5\r
+void INT_Excep_SCI5_RXI5(void){ }\r
+\r
+// SCI5 TXI5\r
+void INT_Excep_SCI5_TXI5(void){ }\r
+\r
+// SCI5 TEI5\r
+void INT_Excep_SCI5_TEI5(void){ }\r
+\r
+// SCI6 ERI6\r
+void INT_Excep_SCI6_ERI6(void){ }\r
+\r
+// SCI6 RXI6\r
+void INT_Excep_SCI6_RXI6(void){ }\r
+\r
+// SCI6 TXI6\r
+void INT_Excep_SCI6_TXI6(void){ }\r
+\r
+// SCI6 TEI6\r
+void INT_Excep_SCI6_TEI6(void){ }\r
+\r
+// SCI8 ERI8\r
+void INT_Excep_SCI8_ERI8(void){ }\r
+\r
+// SCI8 RXI8\r
+void INT_Excep_SCI8_RXI8(void){ }\r
+\r
+// SCI8 TXI8\r
+void INT_Excep_SCI8_TXI8(void){ }\r
+\r
+// SCI8 TEI8\r
+void INT_Excep_SCI8_TEI8(void){ }\r
+\r
+// SCI9 ERI9\r
+void INT_Excep_SCI9_ERI9(void){ }\r
+\r
+// SCI9 RXI9\r
+void INT_Excep_SCI9_RXI9(void){ }\r
+\r
+// SCI9 TXI9\r
+void INT_Excep_SCI9_TXI9(void){ }\r
+\r
+// SCI9 TEI9\r
+void INT_Excep_SCI9_TEI9(void){ }\r
+\r
+// SCI12 ERI12\r
+void INT_Excep_SCI12_ERI12(void){ }\r
+\r
+// SCI12 RXI12\r
+void INT_Excep_SCI12_RXI12(void){ }\r
+\r
+// SCI12 TXI12\r
+void INT_Excep_SCI12_TXI12(void){ }\r
+\r
+// SCI12 TEI12\r
+void INT_Excep_SCI12_TEI12(void){ }\r
+\r
+// SCI12 SCIX0\r
+void INT_Excep_SCI12_SCIX0(void){ }\r
+\r
+// SCI12 SCIX1\r
+void INT_Excep_SCI12_SCIX1(void){ }\r
+\r
+// SCI12 SCIX2\r
+void INT_Excep_SCI12_SCIX2(void){ }\r
+\r
+// SCI12 SCIX3\r
+void INT_Excep_SCI12_SCIX3(void){ }\r
+\r
+// RIIC0 EEI0\r
+void INT_Excep_RIIC0_EEI0(void){ }\r
+\r
+// RIIC0 RXI0\r
+void INT_Excep_RIIC0_RXI0(void){ }\r
+\r
+// RIIC0 TXI0\r
+void INT_Excep_RIIC0_TXI0(void){ }\r
+\r
+// RIIC0 TEI0\r
+void INT_Excep_RIIC0_TEI0(void){ }\r
+\r
--- /dev/null
+/***************************************************************/\r
+/* */\r
+/* PROJECT NAME : RTOSDemo */\r
+/* FILE : interrupt_handlers.h */\r
+/* DESCRIPTION : Interrupt Handler Declarations */\r
+/* CPU SERIES : RX100 */\r
+/* CPU TYPE : RX113 */\r
+/* */\r
+/* This file is generated by e2 studio. */\r
+/* */\r
+/***************************************************************/ \r
+ \r
+ \r
+ \r
+ \r
+/************************************************************************\r
+*\r
+* Device : RX/RX100/RX113\r
+*\r
+* File Name : vect.h\r
+*\r
+* Abstract : Definition of Vector.\r
+*\r
+* History : 1.00 (2013-11-18) [Hardware Manual Revision : 0.40]\r
+* : 1.10 (2014-02-26) [Hardware Manual Revision : 0.50]\r
+* : 1.1A (2015-04-20) [Hardware Manual Revision : 1.02]\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright (C) 2015 (2013 - 2014) Renesas Electronics Corporation.\r
+*\r
+********************************************************************+++*/\r
+/************************************************************************/\r
+/* File Version: V1.1A */\r
+/* History : 1.00 (2013-11-18) [Hardware Manual Revision : 0.40] */\r
+/* : 1.10 (2014-02-26) [Hardware Manual Revision : 0.50] */\r
+/* : 1.1A (2015-04-20) [Hardware Manual Revision : 1.02] */\r
+/* Date Generated: 25/05/2015 */\r
+/************************************************************************/\r
+\r
+#ifndef INTERRUPT_HANDLERS_H\r
+#define INTERRUPT_HANDLERS_H\r
+\r
+// INT_Exception(Supervisor Instruction)\r
+void INT_Excep_SuperVisorInst(void) __attribute__ ((interrupt));\r
+\r
+// INT_Exception(Undefined Instruction)\r
+void INT_Excep_UndefinedInst(void) __attribute__ ((interrupt));\r
+\r
+// NMI\r
+void INT_NonMaskableInterrupt(void) __attribute__ ((interrupt));\r
+\r
+// Dummy\r
+void INT_Dummy(void) __attribute__ ((interrupt));\r
+\r
+// BRK\r
+void INT_Excep_BRK(void) __attribute__ ((interrupt));\r
+\r
+// BSC BUSERR\r
+void INT_Excep_BSC_BUSERR(void) __attribute__ ((interrupt));\r
+\r
+// FCU FRDYI\r
+void INT_Excep_FCU_FRDYI(void) __attribute__ ((interrupt));\r
+\r
+// ICU SWINT\r
+void INT_Excep_ICU_SWINT(void) __attribute__ ((interrupt));\r
+\r
+// CMT0 CMI0\r
+void INT_Excep_CMT0_CMI0(void) __attribute__ ((interrupt));\r
+\r
+// CMT1 CMI1\r
+void INT_Excep_CMT1_CMI1(void) __attribute__ ((interrupt));\r
+\r
+// CMT2 CMI2\r
+void INT_Excep_CMT2_CMI2(void) __attribute__ ((interrupt));\r
+\r
+// CMT3 CMI3\r
+void INT_Excep_CMT3_CMI3(void) __attribute__ ((interrupt));\r
+\r
+// CAC FERRF\r
+void INT_Excep_CAC_FERRF(void) __attribute__ ((interrupt));\r
+\r
+// CAC MENDF\r
+void INT_Excep_CAC_MENDF(void) __attribute__ ((interrupt));\r
+\r
+// CAC OVFF\r
+void INT_Excep_CAC_OVFF(void) __attribute__ ((interrupt));\r
+\r
+// USB0 D0FIFO0\r
+void INT_Excep_USB0_D0FIFO0(void) __attribute__ ((interrupt));\r
+\r
+// USB0 D1FIFO0\r
+void INT_Excep_USB0_D1FIFO0(void) __attribute__ ((interrupt));\r
+\r
+// USB0 USBI0\r
+void INT_Excep_USB0_USBI0(void) __attribute__ ((interrupt));\r
+\r
+// RSPI0 SPEI0\r
+void INT_Excep_RSPI0_SPEI0(void) __attribute__ ((interrupt));\r
+\r
+// RSPI0 SPRI0\r
+void INT_Excep_RSPI0_SPRI0(void) __attribute__ ((interrupt));\r
+\r
+// RSPI0 SPTI0\r
+void INT_Excep_RSPI0_SPTI0(void) __attribute__ ((interrupt));\r
+\r
+// RSPI0 SPII0\r
+void INT_Excep_RSPI0_SPII0(void) __attribute__ ((interrupt));\r
+\r
+// DOC DOPCF\r
+void INT_Excep_DOC_DOPCF(void) __attribute__ ((interrupt));\r
+\r
+// CMPB CMPB0\r
+void INT_Excep_CMPB_CMPB0(void) __attribute__ ((interrupt));\r
+\r
+// CMPB CMPB1\r
+void INT_Excep_CMPB_CMPB1(void) __attribute__ ((interrupt));\r
+\r
+// CTSU CTSUWR\r
+void INT_Excep_CTSU_CTSUWR(void) __attribute__ ((interrupt));\r
+\r
+// CTSU CTSURD\r
+void INT_Excep_CTSU_CTSURD(void) __attribute__ ((interrupt));\r
+\r
+// CTSU CTSUFN\r
+void INT_Excep_CTSU_CTSUFN(void) __attribute__ ((interrupt));\r
+\r
+// RTC CUP\r
+void INT_Excep_RTC_CUP(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ0\r
+void INT_Excep_ICU_IRQ0(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ1\r
+void INT_Excep_ICU_IRQ1(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ2\r
+void INT_Excep_ICU_IRQ2(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ3\r
+void INT_Excep_ICU_IRQ3(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ4\r
+void INT_Excep_ICU_IRQ4(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ5\r
+void INT_Excep_ICU_IRQ5(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ6\r
+void INT_Excep_ICU_IRQ6(void) __attribute__ ((interrupt));\r
+\r
+// ICU IRQ7\r
+void INT_Excep_ICU_IRQ7(void) __attribute__ ((interrupt));\r
+\r
+// ELC ELSR8I\r
+void INT_Excep_ELC_ELSR8I(void) __attribute__ ((interrupt));\r
+\r
+// LVD LVD1\r
+void INT_Excep_LVD_LVD1(void) __attribute__ ((interrupt));\r
+\r
+// LVD LVD2\r
+void INT_Excep_LVD_LVD2(void) __attribute__ ((interrupt));\r
+\r
+// USB0 USBR0\r
+void INT_Excep_USB0_USBR0(void) __attribute__ ((interrupt));\r
+\r
+// RTC ALM\r
+void INT_Excep_RTC_ALM(void) __attribute__ ((interrupt));\r
+\r
+// RTC PRD\r
+void INT_Excep_RTC_PRD(void) __attribute__ ((interrupt));\r
+\r
+// S12AD S12ADI0\r
+void INT_Excep_S12AD_S12ADI0(void) __attribute__ ((interrupt));\r
+\r
+// S12AD GBADI\r
+void INT_Excep_S12AD_GBADI(void) __attribute__ ((interrupt));\r
+\r
+// ELC ELSR18I\r
+void INT_Excep_ELC_ELSR18I(void) __attribute__ ((interrupt));\r
+\r
+// SSI0 SSIF0\r
+void INT_Excep_SSI0_SSIF0(void) __attribute__ ((interrupt));\r
+\r
+// SSI0 SSIRXI0\r
+void INT_Excep_SSI0_SSIRXI0(void) __attribute__ ((interrupt));\r
+\r
+// SSI0 SSITXI0\r
+void INT_Excep_SSI0_SSITXI0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGIA0\r
+void INT_Excep_MTU0_TGIA0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGIB0\r
+void INT_Excep_MTU0_TGIB0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGIC0\r
+void INT_Excep_MTU0_TGIC0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGID0\r
+void INT_Excep_MTU0_TGID0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TCIV0\r
+void INT_Excep_MTU0_TCIV0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGIE0\r
+void INT_Excep_MTU0_TGIE0(void) __attribute__ ((interrupt));\r
+\r
+// MTU0 TGIF0\r
+void INT_Excep_MTU0_TGIF0(void) __attribute__ ((interrupt));\r
+\r
+// MTU1 TGIA1\r
+void INT_Excep_MTU1_TGIA1(void) __attribute__ ((interrupt));\r
+\r
+// MTU1 TGIB1\r
+void INT_Excep_MTU1_TGIB1(void) __attribute__ ((interrupt));\r
+\r
+// MTU1 TCIV1\r
+void INT_Excep_MTU1_TCIV1(void) __attribute__ ((interrupt));\r
+\r
+// MTU1 TCIU1\r
+void INT_Excep_MTU1_TCIU1(void) __attribute__ ((interrupt));\r
+\r
+// MTU2 TGIA2\r
+void INT_Excep_MTU2_TGIA2(void) __attribute__ ((interrupt));\r
+\r
+// MTU2 TGIB2\r
+void INT_Excep_MTU2_TGIB2(void) __attribute__ ((interrupt));\r
+\r
+// MTU2 TCIV2\r
+void INT_Excep_MTU2_TCIV2(void) __attribute__ ((interrupt));\r
+\r
+// MTU2 TCIU2\r
+void INT_Excep_MTU2_TCIU2(void) __attribute__ ((interrupt));\r
+\r
+// MTU3 TGIA3\r
+void INT_Excep_MTU3_TGIA3(void) __attribute__ ((interrupt));\r
+\r
+// MTU3 TGIB3\r
+void INT_Excep_MTU3_TGIB3(void) __attribute__ ((interrupt));\r
+\r
+// MTU3 TGIC3\r
+void INT_Excep_MTU3_TGIC3(void) __attribute__ ((interrupt));\r
+\r
+// MTU3 TGID3\r
+void INT_Excep_MTU3_TGID3(void) __attribute__ ((interrupt));\r
+\r
+// MTU3 TCIV3\r
+void INT_Excep_MTU3_TCIV3(void) __attribute__ ((interrupt));\r
+\r
+// MTU4 TGIA4\r
+void INT_Excep_MTU4_TGIA4(void) __attribute__ ((interrupt));\r
+\r
+// MTU4 TGIB4\r
+void INT_Excep_MTU4_TGIB4(void) __attribute__ ((interrupt));\r
+\r
+// MTU4 TGIC4\r
+void INT_Excep_MTU4_TGIC4(void) __attribute__ ((interrupt));\r
+\r
+// MTU4 TGID4\r
+void INT_Excep_MTU4_TGID4(void) __attribute__ ((interrupt));\r
+\r
+// MTU4 TCIV4\r
+void INT_Excep_MTU4_TCIV4(void) __attribute__ ((interrupt));\r
+\r
+// MTU5 TGIU5\r
+void INT_Excep_MTU5_TGIU5(void) __attribute__ ((interrupt));\r
+\r
+// MTU5 TGIV5\r
+void INT_Excep_MTU5_TGIV5(void) __attribute__ ((interrupt));\r
+\r
+// MTU5 TGIW5\r
+void INT_Excep_MTU5_TGIW5(void) __attribute__ ((interrupt));\r
+\r
+// POE OEI1\r
+void INT_Excep_POE_OEI1(void) __attribute__ ((interrupt));\r
+\r
+// POE OEI2\r
+void INT_Excep_POE_OEI2(void) __attribute__ ((interrupt));\r
+\r
+// TMR0 CMIA0\r
+void INT_Excep_TMR0_CMIA0(void) __attribute__ ((interrupt));\r
+\r
+// TMR0 CMIB0\r
+void INT_Excep_TMR0_CMIB0(void) __attribute__ ((interrupt));\r
+\r
+// TMR0 OVI0\r
+void INT_Excep_TMR0_OVI0(void) __attribute__ ((interrupt));\r
+\r
+// TMR1 CMIA1\r
+void INT_Excep_TMR1_CMIA1(void) __attribute__ ((interrupt));\r
+\r
+// TMR1 CMIB1\r
+void INT_Excep_TMR1_CMIB1(void) __attribute__ ((interrupt));\r
+\r
+// TMR1 OVI1\r
+void INT_Excep_TMR1_OVI1(void) __attribute__ ((interrupt));\r
+\r
+// TMR2 CMIA2\r
+void INT_Excep_TMR2_CMIA2(void) __attribute__ ((interrupt));\r
+\r
+// TMR2 CMIB2\r
+void INT_Excep_TMR2_CMIB2(void) __attribute__ ((interrupt));\r
+\r
+// TMR2 OVI2\r
+void INT_Excep_TMR2_OVI2(void) __attribute__ ((interrupt));\r
+\r
+// TMR3 CMIA3\r
+void INT_Excep_TMR3_CMIA3(void) __attribute__ ((interrupt));\r
+\r
+// TMR3 CMIB3\r
+void INT_Excep_TMR3_CMIB3(void) __attribute__ ((interrupt));\r
+\r
+// TMR3 OVI3\r
+void INT_Excep_TMR3_OVI3(void) __attribute__ ((interrupt));\r
+\r
+// SCI2 ERI2\r
+void INT_Excep_SCI2_ERI2(void) __attribute__ ((interrupt));\r
+\r
+// SCI2 RXI2\r
+void INT_Excep_SCI2_RXI2(void) __attribute__ ((interrupt));\r
+\r
+// SCI2 TXI2\r
+void INT_Excep_SCI2_TXI2(void) __attribute__ ((interrupt));\r
+\r
+// SCI2 TEI2\r
+void INT_Excep_SCI2_TEI2(void) __attribute__ ((interrupt));\r
+\r
+// SCI0 ERI0\r
+void INT_Excep_SCI0_ERI0(void) __attribute__ ((interrupt));\r
+\r
+// SCI0 RXI0\r
+void INT_Excep_SCI0_RXI0(void) __attribute__ ((interrupt));\r
+\r
+// SCI0 TXI0\r
+void INT_Excep_SCI0_TXI0(void) __attribute__ ((interrupt));\r
+\r
+// SCI0 TEI0\r
+void INT_Excep_SCI0_TEI0(void) __attribute__ ((interrupt));\r
+\r
+// SCI1 ERI1\r
+void INT_Excep_SCI1_ERI1(void) __attribute__ ((interrupt));\r
+\r
+// SCI1 RXI1\r
+void INT_Excep_SCI1_RXI1(void) __attribute__ ((interrupt));\r
+\r
+// SCI1 TXI1\r
+void INT_Excep_SCI1_TXI1(void) __attribute__ ((interrupt));\r
+\r
+// SCI1 TEI1\r
+void INT_Excep_SCI1_TEI1(void) __attribute__ ((interrupt));\r
+\r
+// SCI5 ERI5\r
+void INT_Excep_SCI5_ERI5(void) __attribute__ ((interrupt));\r
+\r
+// SCI5 RXI5\r
+void INT_Excep_SCI5_RXI5(void) __attribute__ ((interrupt));\r
+\r
+// SCI5 TXI5\r
+void INT_Excep_SCI5_TXI5(void) __attribute__ ((interrupt));\r
+\r
+// SCI5 TEI5\r
+void INT_Excep_SCI5_TEI5(void) __attribute__ ((interrupt));\r
+\r
+// SCI6 ERI6\r
+void INT_Excep_SCI6_ERI6(void) __attribute__ ((interrupt));\r
+\r
+// SCI6 RXI6\r
+void INT_Excep_SCI6_RXI6(void) __attribute__ ((interrupt));\r
+\r
+// SCI6 TXI6\r
+void INT_Excep_SCI6_TXI6(void) __attribute__ ((interrupt));\r
+\r
+// SCI6 TEI6\r
+void INT_Excep_SCI6_TEI6(void) __attribute__ ((interrupt));\r
+\r
+// SCI8 ERI8\r
+void INT_Excep_SCI8_ERI8(void) __attribute__ ((interrupt));\r
+\r
+// SCI8 RXI8\r
+void INT_Excep_SCI8_RXI8(void) __attribute__ ((interrupt));\r
+\r
+// SCI8 TXI8\r
+void INT_Excep_SCI8_TXI8(void) __attribute__ ((interrupt));\r
+\r
+// SCI8 TEI8\r
+void INT_Excep_SCI8_TEI8(void) __attribute__ ((interrupt));\r
+\r
+// SCI9 ERI9\r
+void INT_Excep_SCI9_ERI9(void) __attribute__ ((interrupt));\r
+\r
+// SCI9 RXI9\r
+void INT_Excep_SCI9_RXI9(void) __attribute__ ((interrupt));\r
+\r
+// SCI9 TXI9\r
+void INT_Excep_SCI9_TXI9(void) __attribute__ ((interrupt));\r
+\r
+// SCI9 TEI9\r
+void INT_Excep_SCI9_TEI9(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 ERI12\r
+void INT_Excep_SCI12_ERI12(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 RXI12\r
+void INT_Excep_SCI12_RXI12(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 TXI12\r
+void INT_Excep_SCI12_TXI12(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 TEI12\r
+void INT_Excep_SCI12_TEI12(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 SCIX0\r
+void INT_Excep_SCI12_SCIX0(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 SCIX1\r
+void INT_Excep_SCI12_SCIX1(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 SCIX2\r
+void INT_Excep_SCI12_SCIX2(void) __attribute__ ((interrupt));\r
+\r
+// SCI12 SCIX3\r
+void INT_Excep_SCI12_SCIX3(void) __attribute__ ((interrupt));\r
+\r
+// RIIC0 EEI0\r
+void INT_Excep_RIIC0_EEI0(void) __attribute__ ((interrupt));\r
+\r
+// RIIC0 RXI0\r
+void INT_Excep_RIIC0_RXI0(void) __attribute__ ((interrupt));\r
+\r
+// RIIC0 TXI0\r
+void INT_Excep_RIIC0_TXI0(void) __attribute__ ((interrupt));\r
+\r
+// RIIC0 TEI0\r
+void INT_Excep_RIIC0_TEI0(void) __attribute__ ((interrupt));\r
+\r
+// ;<<VECTOR DATA START (POWER ON RESET)>>\r
+// ;Power On Reset PC\r
+extern void PowerON_Reset_PC(void) __attribute__ ((interrupt)); \r
+// ;<<VECTOR DATA END (POWER ON RESET)>>\r
+\r
+#endif\r
--- /dev/null
+/*******************************************************************************\r
+ * DISCLAIMER\r
+ * This software is supplied by Renesas Electronics Corporation and is only\r
+ * intended for use with Renesas products. No other uses are authorized. This\r
+ * software is owned by Renesas Electronics Corporation and is protected under\r
+ * all applicable laws, including copyright laws.\r
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+ * Renesas reserves the right, without notice, to make changes to this software\r
+ * and to discontinue the availability of this software. By using this software,\r
+ * you agree to the additional terms and conditions found by accessing the\r
+ * following link:\r
+ * http://www.renesas.com/disclaimer\r
+ *******************************************************************************/\r
+/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */\r
+/*******************************************************************************\r
+ * File Name : r_rsk_async.c\r
+ * Version : 1.00\r
+ * Device(s) : R5F51138AxFP\r
+ * Tool-Chain : CCRX\r
+ * H/W Platform : RSKRX113\r
+ * Description : Functions used to send data via the SCI in asynchronous mode\r
+ *******************************************************************************/\r
+/*******************************************************************************\r
+ * History : 26.08.2014 Ver. 1.00 First Release\r
+ *******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ System Includes\r
+ *******************************************************************************/\r
+/* Following header file provides string type definitions. */\r
+#include <string.h>\r
+\r
+/*******************************************************************************\r
+ User Includes (Project Level Includes)\r
+ *******************************************************************************/\r
+/* Defines port registers */\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_sci.h"\r
+#include "r_rsk_async.h"\r
+\r
+/*******************************************************************************\r
+ User Defines\r
+ *******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Global Variables\r
+ *******************************************************************************/\r
+\r
+/* Declaration of the command string to clear the terminal screen */\r
+static const char cmd_clr_scr[] =\r
+{ 27, 91, 50, 74, 0, 27, 91, 72, 0 };\r
+\r
+/*******************************************************************************\r
+ * Function Prototypes\r
+ *******************************************************************************/\r
+\r
+/* text_write function prototype */\r
+static void text_write (const char * const msg_string);\r
+\r
+/*******************************************************************************\r
+ * Function Name: R_ASYNC_Init\r
+ * Description : This function initialises the SCI channel connected to the\r
+ * RS232 connector on the RSK. The channel is configured for\r
+ * transmission and reception, and instructions are sent to the\r
+ * terminal.\r
+ * Argument : none\r
+ * Return value : none\r
+ *******************************************************************************/\r
+void R_ASYNC_Init (void)\r
+{\r
+\r
+ /* Set up SCI1 receive buffer */\r
+ R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
+\r
+ /* Enable SCI1 operations */\r
+ R_SCI1_Start();\r
+\r
+ /* Clear the text on terminal window */\r
+ text_write(cmd_clr_scr);\r
+\r
+ /* Display splash screen on terminal window */\r
+ text_write("Renesas RSKRX113 Async Serial \r\n");\r
+\r
+ /* Inform user on how to stop transmission */\r
+ text_write("Press 'z' to stop and any key to resume\r\n\n");\r
+}\r
+/*******************************************************************************\r
+ * End of function R_ASYNC_Init\r
+ *******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Function Name : text_write\r
+ * Description : Transmits null-terminated string.\r
+ * Argument : (char*) msg_string - null terminated string\r
+ * Return value : None\r
+ *******************************************************************************/\r
+static void text_write (const char * const msg_string)\r
+{\r
+ R_SCI1_AsyncTransmit((uint8_t *) msg_string, (uint16_t) strlen(msg_string));\r
+}\r
+/*******************************************************************************\r
+ * End of function text_write\r
+ *******************************************************************************/\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * DISCLAIMER\r
+ * This software is supplied by Renesas Electronics Corporation and is only\r
+ * intended for use with Renesas products. No other uses are authorized. This\r
+ * software is owned by Renesas Electronics Corporation and is protected under\r
+ * all applicable laws, including copyright laws.\r
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+ * Renesas reserves the right, without notice, to make changes to this software\r
+ * and to discontinue the availability of this software. By using this software,\r
+ * you agree to the additional terms and conditions found by accessing the\r
+ * following link:\r
+ * http://www.renesas.com/disclaimer\r
+ *******************************************************************************/\r
+/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */\r
+/*******************************************************************************\r
+ * File Name : r_rsk_async.h\r
+ * Version : 1.00\r
+ * Device(s) : R5F51138AxFP\r
+ * Tool-Chain : CCRX\r
+ * H/W Platform : RSKRX113\r
+ * Description : Functions used to send data via the SCI in asynchronous mode\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * History : 26.08.2014 Ver. 1.00 First Release\r
+ *******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Macro Definitions\r
+ *******************************************************************************/\r
+/* Multiple inclusion prevention macro */\r
+#ifndef R_RSK_ASYNC_H\r
+#define R_RSK_ASYNC_H\r
+\r
+/*******************************************************************************\r
+ * Global Function Prototypes\r
+ *******************************************************************************/\r
+/* initialise asynchronous transmission*/\r
+void R_ASYNC_Init (void);\r
+\r
+/* End of multiple inclusion prevention macro */\r
+#endif\r
+\r
--- /dev/null
+/***************************************************************/\r
+/* */\r
+/* PROJECT NAME : RTOSDemo */\r
+/* FILE : reset_program.asm */\r
+/* DESCRIPTION : Reset Program */\r
+/* CPU SERIES : RX100 */\r
+/* CPU TYPE : RX113 */\r
+/* */\r
+/* This file is generated by e2 studio. */\r
+/* */\r
+/***************************************************************/ \r
+ \r
+ \r
+/************************************************************************/\r
+/* File Version: V1.01 */\r
+/* Date Generated: 04/03/2015 */\r
+/************************************************************************/\r
+\r
+ /*reset_program.asm*/\r
+\r
+ .list\r
+ .section .text\r
+ .global _PowerON_Reset /*global Start routine */\r
+ \r
+ .extern _HardwareSetup /*external Sub-routine to initialise Hardware*/\r
+ .extern _data\r
+ .extern _mdata\r
+ .extern _ebss\r
+ .extern _bss\r
+ .extern _edata\r
+ .extern _main \r
+ .extern _ustack\r
+ .extern _istack\r
+ .extern _rvectors\r
+ .extern _exit\r
+\r
+_PowerON_Reset :\r
+/* initialise user stack pointer */\r
+ mvtc #_ustack,USP\r
+\r
+/* initialise interrupt stack pointer */\r
+ mvtc #_istack,ISP\r
+\r
+#ifdef __RXv2__\r
+/* setup exception vector */\r
+ mvtc #_ExceptVectors, extb /* EXCEPTION VECTOR ADDRESS */\r
+#endif\r
+\r
+/* setup intb */\r
+ mvtc #_rvectors_start, intb /* INTERRUPT VECTOR ADDRESS definition */\r
+\r
+/* setup FPSW */\r
+ mvtc #100h, fpsw \r
+\r
+/* load data section from ROM to RAM */\r
+\r
+ mov #_mdata,r2 /* src ROM address of data section in R2 */\r
+ mov #_data,r1 /* dest start RAM address of data section in R1 */\r
+ mov #_edata,r3 /* end RAM address of data section in R3 */\r
+ sub r1,r3 /* size of data section in R3 (R3=R3-R1) */\r
+#ifdef __RX_ALLOW_STRING_INSNS__\r
+ smovf /* block copy R3 bytes from R2 to R1 */\r
+#else\r
+ cmp #0, r3\r
+ beq 2f\r
+\r
+1: mov.b [r2+], r5\r
+ mov.b r5, [r1+]\r
+ sub #1, r3\r
+ bne 1b\r
+2:\r
+#endif\r
+\r
+\r
+/* bss initialisation : zero out bss */\r
+\r
+ mov #00h,r2 /* load R2 reg with zero */\r
+ mov #_ebss, r3 /* store the end address of bss in R3 */\r
+ mov #_bss, r1 /* store the start address of bss in R1 */\r
+ sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */\r
+ sstr.b\r
+/* call the hardware initialiser */\r
+ mov #_HardwareSetup,r7\r
+ jsr r7\r
+ nop\r
+\r
+/* setup PSW */\r
+ mvtc #10000h, psw /* Set Ubit & Ibit for PSW */\r
+\r
+/* change PSW PM to user-mode */\r
+ MVFC PSW,R1\r
+//DO NOT SWITCH TO USER MODE OR #00100000h,R1\r
+ PUSH.L R1\r
+ MVFC PC,R1\r
+ ADD #10,R1\r
+ PUSH.L R1\r
+ RTE\r
+ NOP\r
+ NOP\r
+#ifdef CPPAPP\r
+ mov #__rx_init,r7\r
+ jsr r7\r
+#endif \r
+/* start user program */\r
+ mov #_main,r7\r
+ jsr r7\r
+ mov #_exit,r7\r
+ jsr r7\r
+\r
+#ifdef CPPAPP\r
+ .global _rx_run_preinit_array\r
+ .type _rx_run_preinit_array,@function\r
+_rx_run_preinit_array:\r
+ mov #__preinit_array_start,r1\r
+ mov #__preinit_array_end,r2\r
+ mov #_rx_run_inilist,r7\r
+ jsr r7\r
+\r
+ .global _rx_run_init_array\r
+ .type _rx_run_init_array,@function\r
+_rx_run_init_array:\r
+ mov #__init_array_start,r1\r
+ mov #__init_array_end,r2\r
+ mov #4, r3\r
+ mov #_rx_run_inilist,r7\r
+ jsr r7\r
+\r
+ .global _rx_run_fini_array\r
+ .type _rx_run_fini_array,@function\r
+_rx_run_fini_array:\r
+ mov #__fini_array_start,r2\r
+ mov #__fini_array_end,r1\r
+ mov #-4, r3\r
+ /* fall through */\r
+\r
+_rx_run_inilist:\r
+next_inilist:\r
+ cmp r1,r2\r
+ beq.b done_inilist\r
+ mov.l [r1],r4\r
+ cmp #-1, r4\r
+ beq.b skip_inilist\r
+ cmp #0, r4\r
+ beq.b skip_inilist\r
+ pushm r1-r3\r
+ jsr r4\r
+ popm r1-r3\r
+skip_inilist:\r
+ add r3,r1\r
+ mov #next_inilist,r7\r
+ jsr r7\r
+done_inilist:\r
+ rts\r
+\r
+ .section .init,"ax"\r
+ .balign 4\r
+\r
+ .global __rx_init\r
+__rx_init:\r
+\r
+ .section .fini,"ax"\r
+ .balign 4\r
+\r
+ .global __rx_fini\r
+__rx_fini:\r
+ mov #_rx_run_fini_array,r7\r
+ jsr r7\r
+\r
+ .section .sdata\r
+ .balign 4\r
+ .global __gp\r
+ .weak __gp\r
+__gp: \r
+\r
+ .section .data\r
+ .global ___dso_handle\r
+ .weak ___dso_handle\r
+___dso_handle:\r
+ .long 0\r
+\r
+ .section .init,"ax"\r
+ mov #_rx_run_preinit_array,r7\r
+ jsr r7\r
+ mov #_rx_run_init_array,r7\r
+ jsr r7\r
+ rts\r
+ \r
+ .global __rx_init_end\r
+__rx_init_end:\r
+\r
+ .section .fini,"ax"\r
+\r
+ rts\r
+ .global __rx_fini_end\r
+__rx_fini_end:\r
+\r
+#endif\r
+\r
+/* call to exit*/\r
+_exit:\r
+ bra _loop_here\r
+_loop_here:\r
+ bra _loop_here\r
+ \r
+ .text \r
+ .end\r
--- /dev/null
+/***************************************************************/\r
+/* */\r
+/* PROJECT NAME : RTOSDemo */\r
+/* FILE : typedefine.h */\r
+/* DESCRIPTION : Aliases of Integer Type */\r
+/* CPU SERIES : RX100 */\r
+/* CPU TYPE : RX113 */\r
+/* */\r
+/* This file is generated by e2 studio. */\r
+/* */\r
+/***************************************************************/ \r
+ \r
+ \r
+/************************************************************************/\r
+/* File Version: V1.00 */\r
+/* Date Generated: 08/07/2013 */\r
+/************************************************************************/\r
+\r
+typedef signed char _SBYTE;\r
+typedef unsigned char _UBYTE;\r
+typedef signed short _SWORD;\r
+typedef unsigned short _UWORD;\r
+typedef signed int _SINT;\r
+typedef unsigned int _UINT;\r
+typedef signed long _SDWORD;\r
+typedef unsigned long _UDWORD;\r
+typedef signed long long _SQWORD;\r
+typedef unsigned long long _UQWORD;\r
--- /dev/null
+/***************************************************************/\r
+/* */\r
+/* PROJECT NAME : RTOSDemo */\r
+/* FILE : vector_table.c */\r
+/* DESCRIPTION : Vector Table */\r
+/* CPU SERIES : RX100 */\r
+/* CPU TYPE : RX113 */\r
+/* */\r
+/* This file is generated by e2 studio. */\r
+/* */\r
+/***************************************************************/ \r
+ \r
+ \r
+/************************************************************************/\r
+/* File Version: V1.00 */\r
+/* Date Generated: 20/08/2014 */\r
+/************************************************************************/\r
+\r
+#include "interrupt_handlers.h"\r
+\r
+typedef void (*fp) (void);\r
+extern void PowerON_Reset (void);\r
+extern void stack (void);\r
+extern void vPortSoftwareInterruptISR( void );\r
+extern void vPortTickISR( void );\r
+extern void vIntQTimerISR0( void );\r
+extern void vIntQTimerISR1( void );\r
+\r
+#define FVECT_SECT __attribute__ ((section (".fvectors")))\r
+\r
+const void *HardwareVectors[] FVECT_SECT = {\r
+//;0xffffff80 MDES Endian Select Register\r
+#ifdef __RX_LITTLE_ENDIAN__ \r
+(fp)0xffffffff,\r
+#endif\r
+#ifdef __RX_BIG_ENDIAN__ \r
+(fp)0xfffffff8,\r
+#endif\r
+//;0xffffff84 Reserved\r
+ (fp)0, \r
+//;0xffffff88 OFS1\r
+ (fp)0xFFFFFFFF,\r
+//;0xffffff8C OFS0\r
+ (fp)0xFFFFFFFF,\r
+//;0xffffff90 Reserved\r
+ (fp)0, \r
+//;0xffffff94 Reserved\r
+ (fp)0, \r
+//;0xffffff98 Reserved\r
+ (fp)0, \r
+//;0xffffff9C Reserved\r
+ (fp)0, \r
+//;0xffffffA0 Reserved\r
+ (fp)0,\r
+ //;0xffffffA4 Reserved\r
+ (fp)0,\r
+//;0xffffffA8 Reserved\r
+ (fp)0,\r
+//;0xffffffAC Reserved\r
+ (fp)0,\r
+//;0xffffffB0 Reserved\r
+ (fp)0,\r
+//;0xffffffB4 Reserved\r
+ (fp)0,\r
+//;0xffffffB8 Reserved\r
+ (fp)0,\r
+//;0xffffffBC Reserved\r
+ (fp)0,\r
+//;0xffffffC0 Reserved\r
+ (fp)0,\r
+//;0xffffffC4 Reserved\r
+ (fp)0,\r
+//;0xffffffC8 Reserved\r
+ (fp)0,\r
+//;0xffffffCC Reserved\r
+ (fp)0,\r
+//;0xffffffd0 Exception(Supervisor Instruction)\r
+ INT_Excep_SuperVisorInst,\r
+//;0xffffffd4 Reserved\r
+ (fp)0,\r
+//;0xffffffd8 Reserved\r
+ (fp)0,\r
+//;0xffffffdc Exception(Undefined Instruction)\r
+ INT_Excep_UndefinedInst,\r
+//;0xffffffe0 Reserved\r
+ (fp)0,\r
+//;0xffffffe4 Reserved\r
+ (fp)0,\r
+//;0xffffffe8 Reserved\r
+ (fp)0,\r
+//;0xffffffec Reserved\r
+ (fp)0,\r
+//;0xfffffff0 Reserved\r
+ (fp)0,\r
+//;0xfffffff4 Reserved\r
+ (fp)0,\r
+//;0xfffffff8 NMI\r
+ INT_NonMaskableInterrupt,\r
+//;0xfffffffc RESET\r
+//;<<VECTOR DATA START (POWER ON RESET)>>\r
+//;Power On Reset PC\r
+ PowerON_Reset \r
+//;<<VECTOR DATA END (POWER ON RESET)>>\r
+};\r
+#define RVECT_SECT __attribute__ ((section (".rvectors")))\r
+\r
+const fp RelocatableVectors[] RVECT_SECT = {\r
+//;0x0000 BRK\r
+ (fp)INT_Excep_BRK,\r
+//;0x0004 Reserved\r
+ (fp)0,\r
+//;0x0008 Reserved\r
+ (fp)0,\r
+//;0x000C Reserved\r
+ (fp)0,\r
+//;0x0010 Reserved\r
+ (fp)0,\r
+//;0x0014 Reserved\r
+ (fp)0,\r
+//;0x0018 Reserved\r
+ (fp)0,\r
+//;0x001C Reserved\r
+ (fp)0,\r
+//;0x0020 Reserved\r
+ (fp)0,\r
+//;0x0024 Reserved\r
+ (fp)0,\r
+//;0x0028 Reserved\r
+ (fp)0,\r
+//;0x002C Reserved\r
+ (fp)0,\r
+//;0x0030 Reserved\r
+ (fp)0,\r
+//;0x0034 Reserved\r
+ (fp)0,\r
+//;0x0038 Reserved\r
+ (fp)0,\r
+//;0x003C Reserved\r
+ (fp)0,\r
+//;0x0040 BSC_BUSERR\r
+ (fp)INT_Excep_BSC_BUSERR,\r
+//;0x0044 Reserved\r
+ (fp)0,\r
+//;0x0048 Reserved\r
+ (fp)0,\r
+//;0x004C Reserved\r
+ (fp)0,\r
+//;0x0050 Reserved\r
+ (fp)0,\r
+//;0x0054 FCUERR\r
+ (fp)0,\r
+//;0x0058 Reserved\r
+ (fp)0,\r
+//;0x005C FRDYI\r
+ (fp)INT_Excep_FCU_FRDYI,\r
+//;0x0060 Reserved\r
+ (fp)0,\r
+//;0x0064 Reserved\r
+ (fp)0,\r
+//;0x0068 Reserved\r
+ (fp)0,\r
+//;0x006C ICU_SWINT\r
+ (fp)vPortSoftwareInterruptISR,\r
+//;0x0070 CMT0_CMI0\r
+ (fp)vPortTickISR,\r
+//;0x0074 CMT1_CMI1\r
+ (fp)INT_Excep_CMT1_CMI1,\r
+//;0x0078 CMT2_CMI2\r
+ (fp)INT_Excep_CMT2_CMI2,\r
+//;0x007C CMT3_CMI3\r
+ (fp)INT_Excep_CMT3_CMI3,\r
+//;0x0080 CAC_FERRF\r
+ (fp)INT_Excep_CAC_FERRF,\r
+//;0x0084 CAC_MENDF\r
+ (fp)INT_Excep_CAC_MENDF,\r
+//;0x0088 CAC_OVFF\r
+ (fp)INT_Excep_CAC_OVFF,\r
+//;0x008C Reserved\r
+ (fp)0,\r
+//;0x0090 USB0_D0FIFO0\r
+ (fp)INT_Excep_USB0_D0FIFO0,\r
+//;0x0094 USB0_D1FIFO0\r
+ (fp)INT_Excep_USB0_D1FIFO0,\r
+//;0x0098 USB0_USBI0\r
+ (fp)INT_Excep_USB0_USBI0,\r
+//;0x009C Reserved\r
+ (fp)0,\r
+//;0x00A0 Reserved\r
+ (fp)0,\r
+//;0x00A4 Reserved\r
+ (fp)0,\r
+//;0x00A8 Reserved\r
+ (fp)0,\r
+//;0x00AC Reserved\r
+ (fp)0,\r
+//;0x00B0 RSPI0_SPEI0\r
+ (fp)INT_Excep_RSPI0_SPEI0,\r
+//;0x00B4 RSPI0_SPRI0\r
+ (fp)INT_Excep_RSPI0_SPRI0,\r
+//;0x00B8 RSPI0_SPTI0\r
+ (fp)INT_Excep_RSPI0_SPTI0,\r
+//;0x00BC RSPI0_SPII0\r
+ (fp)INT_Excep_RSPI0_SPII0,\r
+//;0x00C0 Reserved\r
+ (fp)0,\r
+//;0x00C4 Reserved\r
+ (fp)0,\r
+//;0x00C8 Reserved\r
+ (fp)0,\r
+//;0x00CC Reserved\r
+ (fp)0,\r
+//;0x00D0 Reserved\r
+ (fp)0,\r
+//;0x00D4 Reserved\r
+ (fp)0,\r
+//;0x00D8 Reserved\r
+ (fp)0,\r
+//;0x00DC Reserved\r
+ (fp)0,\r
+//;0x00E0 Reserved\r
+ (fp)0,\r
+//;0x00E4 DOC_DOPCF\r
+ (fp)INT_Excep_DOC_DOPCF,\r
+//;0x00E8 CMPB_CMPB0\r
+ (fp)INT_Excep_CMPB_CMPB0,\r
+//;0x00EC CMPB_CMPB1\r
+ (fp)INT_Excep_CMPB_CMPB1,\r
+//;0x00F0 CTSU_CTSUWR\r
+ (fp)INT_Excep_CTSU_CTSUWR,\r
+//;0x00F4 CTSU_CTSURD\r
+ (fp)INT_Excep_CTSU_CTSURD,\r
+//;0x00F8 CTSU_CTSUFN\r
+ (fp)INT_Excep_CTSU_CTSUFN,\r
+//;0x00FC Excep_RTC_CUP\r
+ (fp)INT_Excep_RTC_CUP,\r
+//;0x0100 IRQ0\r
+ (fp)INT_Excep_ICU_IRQ0,\r
+//;0x0104 IRQ1\r
+ (fp)INT_Excep_ICU_IRQ1,\r
+//;0x0108 IRQ2\r
+ (fp)INT_Excep_ICU_IRQ2,\r
+//;0x010C IRQ3\r
+ (fp)INT_Excep_ICU_IRQ3,\r
+//;0x0110 IRQ4\r
+ (fp)INT_Excep_ICU_IRQ4,\r
+//;0x0114 IRQ5\r
+ (fp)INT_Excep_ICU_IRQ5,\r
+//;0x0118 IRQ6\r
+ (fp)INT_Excep_ICU_IRQ6,\r
+//;0x011C IRQ7\r
+ (fp)INT_Excep_ICU_IRQ7,\r
+//;0x0120 Reserved\r
+ (fp)0,\r
+//;0x0124 Reserved\r
+ (fp)0,\r
+//;0x0128 Reserved\r
+ (fp)0,\r
+//;0x012C Reserved\r
+ (fp)0,\r
+//;0x0130 Reserved\r
+ (fp)0,\r
+//;0x0134 Reserved\r
+ (fp)0,\r
+//;0x0138 Reserved\r
+ (fp)0,\r
+//;0x013C Reserved\r
+ (fp)0,\r
+//;0x0140 ELC ELSR8I\r
+ (fp)INT_Excep_ELC_ELSR8I,\r
+//;0x0144 Reserved\r
+ (fp)0,\r
+//;0x0148 Reserved\r
+ (fp)0,\r
+//;0x014C Reserved\r
+ (fp)0,\r
+//;0x0150 Reserved\r
+ (fp)0,\r
+//;0x0154 Reserved\r
+ (fp)0,\r
+//;0x0158 Reserved\r
+ (fp)0,\r
+//;0x015C Reserved\r
+ (fp)0,\r
+//;0x0160 LVD_LVD1\r
+ (fp)INT_Excep_LVD_LVD1,\r
+//;0x0164 LVD_LVD2\r
+ (fp)INT_Excep_LVD_LVD2,\r
+//;0x0168 USB0_USBR0\r
+ (fp)INT_Excep_USB0_USBR0,\r
+//;0x016C Reserved\r
+ (fp)0,\r
+//;0x0170 RTC_ALM\r
+ (fp)INT_Excep_RTC_ALM,\r
+//;0x0174 RTC_PRD\r
+ (fp)INT_Excep_RTC_PRD,\r
+//;0x0178 Reserved\r
+ (fp)0,\r
+//;0x017C Reserved\r
+ (fp)0,\r
+//;0x0180 Reserved\r
+ (fp)0,\r
+//;0x0184 Reserved\r
+ (fp)0,\r
+//;0x0188 Reserved\r
+ (fp)0,\r
+//;0x018C Reserved\r
+ (fp)0,\r
+//;0x0190 Reserved\r
+ (fp)0,\r
+//;0x0194 Reserved\r
+ (fp)0,\r
+//;0x0198 S12AD_S12ADI0 \r
+ (fp)INT_Excep_S12AD_S12ADI0,\r
+//;0x019C S12AD_GBADI \r
+ (fp)INT_Excep_S12AD_GBADI,\r
+//104;0x01A0 Reserved \r
+ (fp)0,\r
+//105;0x01A4 Reserved \r
+ (fp)0,\r
+//;0x01A8 ELC_ELSR18I\r
+ (fp)INT_Excep_ELC_ELSR18I,\r
+//;0x01AC Reserved\r
+ (fp)0,\r
+//;0x01B0 SSI0_SSIF0\r
+ (fp)INT_Excep_SSI0_SSIF0,\r
+//;0x01B4 SSI0_SSIRXI0\r
+ (fp)INT_Excep_SSI0_SSIRXI0,\r
+//;0x01B8 SSI0_SSITXI0\r
+ (fp)INT_Excep_SSI0_SSITXI0,\r
+//;0x01BC Reserved\r
+ (fp)0,\r
+//;0x01C0 Reserved\r
+ (fp)0,\r
+//;0x01C4 Reserved\r
+ (fp)0,\r
+//;0x01C8 MTU0_TGIA0 \r
+ (fp)INT_Excep_MTU0_TGIA0,\r
+//;0x01CC MTU0_TGIB0 \r
+ (fp)INT_Excep_MTU0_TGIB0,\r
+//;0x01D0 MTU0_TGIC0 \r
+ (fp)INT_Excep_MTU0_TGIC0,\r
+//;0x01D4 MTU0_TGID0 \r
+ (fp)INT_Excep_MTU0_TGID0,\r
+//;0x01D8 MTU0_TCIV0 \r
+ (fp)INT_Excep_MTU0_TCIV0,\r
+//;0x01DC MTU0_TGIE0 \r
+ (fp)INT_Excep_MTU0_TGIE0,\r
+//;0x01E0 MTU0_TGIF0 \r
+ (fp)INT_Excep_MTU0_TGIF0, \r
+//;0x01E4 MTU1_TGIA1 \r
+ (fp)INT_Excep_MTU1_TGIA1,\r
+//;0x01E8 MTU1_TGIB1 \r
+ (fp)INT_Excep_MTU1_TGIB1,\r
+//;0x01EC MTU1_TCIV1 \r
+ (fp)INT_Excep_MTU1_TCIV1,\r
+//;0x01F0 MTU1_TCIU1 \r
+ (fp)INT_Excep_MTU1_TCIU1, \r
+//;0x01F4 MTU2_TGIA2 \r
+ (fp)INT_Excep_MTU2_TGIA2,\r
+//;0x01F8 MTU2_TGIB2 \r
+ (fp)INT_Excep_MTU2_TGIB2,\r
+//;0x01FC MTU2_TCIV2 \r
+ (fp)INT_Excep_MTU2_TCIV2,\r
+//;0x0200 MTU2_TCIU2 \r
+ (fp)INT_Excep_MTU2_TCIU2, \r
+//;0x0204 MTU3_TGIA3 \r
+ (fp)INT_Excep_MTU3_TGIA3,\r
+//;0x0208 MTU3_TGIB3 \r
+ (fp)INT_Excep_MTU3_TGIB3,\r
+//;0x020C MTU3_TGIC3 \r
+ (fp)INT_Excep_MTU3_TGIC3,\r
+//;0x0210 MTU3_TGID3 \r
+ (fp)INT_Excep_MTU3_TGID3,\r
+//;0x0214 MTU3_TCIV3 \r
+ (fp)INT_Excep_MTU3_TCIV3, \r
+//;0x0218 MTU4_TGIA4 \r
+ (fp)INT_Excep_MTU4_TGIA4,\r
+//;0x021C MTU4_TGIB4 \r
+ (fp)INT_Excep_MTU4_TGIB4,\r
+//;0x0220 MTU4_TGIC4 \r
+ (fp)INT_Excep_MTU4_TGIC4,\r
+//;0x0224 MTU4_TGID4 \r
+ (fp)INT_Excep_MTU4_TGID4,\r
+//;0x0228 MTU4_TCIV4 \r
+ (fp)INT_Excep_MTU4_TCIV4, \r
+//;0x022C MTU5_TGIU5 \r
+ (fp)INT_Excep_MTU5_TGIU5,\r
+//;0x0230 MTU5_TGIV5 \r
+ (fp)INT_Excep_MTU5_TGIV5,\r
+//;0x0234 MTU5_TGIW5 \r
+ (fp)INT_Excep_MTU5_TGIW5,\r
+//;0x0238 Reserved\r
+ (fp)0,\r
+//;0x023C Reserved\r
+ (fp)0,\r
+//;0x0240 Reserved\r
+ (fp)0,\r
+//;0x0244 Reserved\r
+ (fp)0,\r
+//;0x0248 Reserved\r
+ (fp)0,\r
+//;0x024C Reserved\r
+ (fp)0,\r
+//;0x0250 Reserved\r
+ (fp)0,\r
+//;0x0254 Reserved\r
+ (fp)0,\r
+//;0x0258 Reserved\r
+ (fp)0,\r
+//;0x025C Reserved\r
+ (fp)0,\r
+//;0x0260 Reserved\r
+ (fp)0,\r
+//;0x0264 Reserved\r
+ (fp)0,\r
+//;0x0268 Reserved\r
+ (fp)0,\r
+//;0x026C Reserved\r
+ (fp)0,\r
+//;0x0270 Reserved\r
+ (fp)0,\r
+//;0x0274 Reserved\r
+ (fp)0,\r
+//;0x0278 Reserved\r
+ (fp)0,\r
+//;0x027C Reserved\r
+ (fp)0,\r
+//;0x0280 Reserved\r
+ (fp)0,\r
+//;0x0284 Reserved\r
+ (fp)0,\r
+//;0x0288 Reserved\r
+ (fp)0,\r
+//;0x028C Reserved\r
+ (fp)0,\r
+//;0x0290 Reserved\r
+ (fp)0,\r
+//;0x0294 Reserved\r
+ (fp)0,\r
+//;0x0298 Reserved\r
+ (fp)0,\r
+//;0x029C Reserved\r
+ (fp)0,\r
+//;0x02A0 Reserved\r
+ (fp)0,\r
+//;0x02A4 Reserved\r
+ (fp)0,\r
+//;0x02A8 POE_OEI1\r
+ (fp)INT_Excep_POE_OEI1,\r
+//;0x02AC POE_OEI2\r
+ (fp)INT_Excep_POE_OEI2,\r
+//;0x02B0 Reserved\r
+ (fp)0,\r
+//;0x02B4 Reserved\r
+ (fp)0,\r
+//;0x02B8 TMR0_CMIA0\r
+ (fp)vIntQTimerISR0,\r
+//;0x02BC TMR0_CMIB0\r
+ (fp)INT_Excep_TMR0_CMIB0,\r
+//;0x02C0 TMR0_OVI0\r
+ (fp)INT_Excep_TMR0_OVI0,\r
+//;0x02C4 TMR1_CMIA1\r
+ (fp)INT_Excep_TMR1_CMIA1,\r
+//;0x02C8 TMR1_CMIB1\r
+ (fp)INT_Excep_TMR1_CMIB1,\r
+//;0x02CC TMR1_OVI1\r
+ (fp)INT_Excep_TMR1_OVI1,\r
+//;0x02D0 TMR2_CMIA2\r
+ (fp)vIntQTimerISR1,\r
+//;0x02D4 TMR2_CMIB2\r
+ (fp)INT_Excep_TMR2_CMIB2,\r
+//;0x02D8 TMR2_OVI2\r
+ (fp)INT_Excep_TMR2_OVI2,\r
+//;0x02DC TMR3_CMIA3\r
+ (fp)INT_Excep_TMR3_CMIA3,\r
+//;0x02E0 TMR3_CMIB3\r
+ (fp)INT_Excep_TMR3_CMIB3,\r
+//;0x02E4 TMR3_OVI3\r
+ (fp)INT_Excep_TMR3_OVI3,\r
+//;0x02E8 SCI2_ERI2\r
+ (fp)INT_Excep_SCI2_ERI2,\r
+//;0x02EC SCI2_RXI2\r
+ (fp)INT_Excep_SCI2_RXI2,\r
+//;0x02F0 SCI2_TXI2\r
+ (fp)INT_Excep_SCI2_TXI2,\r
+//;0x02F4 SCI2_TEI2\r
+ (fp)INT_Excep_SCI2_TEI2,\r
+//;0x02F8 Reserved\r
+ (fp)0,\r
+//;0x02FC Reserved\r
+ (fp)0,\r
+//;0x0300 Reserved\r
+ (fp)0,\r
+//;0x0304 Reserved\r
+ (fp)0,\r
+//;0x0308 Reserved\r
+ (fp)0,\r
+//;0x030C Reserved\r
+ (fp)0,\r
+//;0x0310 Reserved\r
+ (fp)0,\r
+//;0x0314 Reserved\r
+ (fp)0,\r
+//;0x0318 Reserved\r
+ (fp)0,\r
+//;0x031C Reserved\r
+ (fp)0,\r
+//;0x0320 Reserved\r
+ (fp)0,\r
+//;0x0324 Reserved\r
+ (fp)0,\r
+//;0x0328 Reserved\r
+ (fp)0,\r
+//;0x032C Reserved\r
+ (fp)0,\r
+//;0x0330 Reserved\r
+ (fp)0,\r
+//;0x0334 Reserved\r
+ (fp)0,\r
+//;0x0338 Reserved\r
+ (fp)0,\r
+//;0x033C Reserved\r
+ (fp)0,\r
+//;0x0340 Reserved\r
+ (fp)0,\r
+//;0x0344 Reserved\r
+ (fp)0,\r
+//;0x0348 Reserved\r
+ (fp)0,\r
+//;0x034C Reserved\r
+ (fp)0,\r
+//;0x0350 Reserved\r
+ (fp)0,\r
+//;0x0354 Reserved\r
+ (fp)0,\r
+//;0x0358 SCI0_ERI0\r
+ (fp)INT_Excep_SCI0_ERI0,\r
+//;0x035C SCI0_RXI0\r
+ (fp)INT_Excep_SCI0_RXI0,\r
+//;0x0360 SCI0_TXI0\r
+ (fp)INT_Excep_SCI0_TXI0,\r
+//;0x0364 SCI0_TEI0\r
+ (fp)INT_Excep_SCI0_TEI0,\r
+//;0x0368 SCI1_ERI1\r
+ (fp)INT_Excep_SCI1_ERI1,\r
+//;0x036C SCI1_RXI1\r
+ (fp)INT_Excep_SCI1_RXI1,\r
+//;0x0370 SCI1_TXI1\r
+ (fp)INT_Excep_SCI1_TXI1,\r
+//;0x0374 SCI1_TEI1\r
+ (fp)INT_Excep_SCI1_TEI1,\r
+//;0x0378 SCI5_ERI5\r
+ (fp)INT_Excep_SCI5_ERI5,\r
+//;0x037C SCI5_RXI5\r
+ (fp)INT_Excep_SCI5_RXI5,\r
+//;0x0380 SCI5_TXI5\r
+ (fp)INT_Excep_SCI5_TXI5,\r
+//;0x0384 SCI5_TEI5\r
+ (fp)INT_Excep_SCI5_TEI5,\r
+//;0x0388 SCI6_ERI6\r
+ (fp)INT_Excep_SCI6_ERI6,\r
+//;0x038C SCI6_RXI6\r
+ (fp)INT_Excep_SCI6_RXI6,\r
+//;0x0390 SCI6_TXI6\r
+ (fp)INT_Excep_SCI6_TXI6,\r
+//;0x0394 SCI6_TEI6\r
+ (fp)INT_Excep_SCI6_TEI6,\r
+//;0x0398 SCI8_ERI8\r
+ (fp)INT_Excep_SCI8_ERI8,\r
+//;0x039C SCI8_RXI8\r
+ (fp)INT_Excep_SCI8_RXI8,\r
+//;0x03A0 SCI8_TXI8\r
+ (fp)INT_Excep_SCI8_TXI8,\r
+//;0x03A4 SCI8_TEI8\r
+ (fp)INT_Excep_SCI8_TEI8,\r
+//;0x03A8 SCI9_ERI9\r
+ (fp)INT_Excep_SCI9_ERI9,\r
+//;0x03AC SCI9_RXI9\r
+ (fp)INT_Excep_SCI9_RXI9,\r
+//;0x03B0 SCI9_TXI9\r
+ (fp)INT_Excep_SCI9_TXI9,\r
+//;0x03B4 SCI9_TEI9\r
+ (fp)INT_Excep_SCI9_TEI9,\r
+//;0x03B8 SCI12_ERI12\r
+ (fp)INT_Excep_SCI12_ERI12,\r
+//;0x03BC SCI12_RXI12\r
+ (fp)INT_Excep_SCI12_RXI12,\r
+//;0x03C0 SCI12_TXI12\r
+ (fp)INT_Excep_SCI12_TXI12,\r
+//;0x03C4 SCI12_TEI12\r
+ (fp)INT_Excep_SCI12_TEI12,\r
+//;0x03C8 SCI12_SCIX0\r
+ (fp)INT_Excep_SCI12_SCIX0,\r
+//;0x03CC SCI12_SCIX1\r
+ (fp)INT_Excep_SCI12_SCIX1,\r
+//;0x03D0 SCI12_SCIX2\r
+ (fp)INT_Excep_SCI12_SCIX2,\r
+//;0x03D4 SCI12_SCIX3\r
+ (fp)INT_Excep_SCI12_SCIX3,\r
+//;0x03D8 RIIC0_EEI0\r
+ (fp)INT_Excep_RIIC0_EEI0,\r
+//;0x03DC RIIC0_RXI0\r
+ (fp)INT_Excep_RIIC0_RXI0,\r
+//;0x03E0 RIIC0_TXI0\r
+ (fp)INT_Excep_RIIC0_TXI0,\r
+//;0x03E4 RIIC0_TEI0\r
+ (fp)INT_Excep_RIIC0_TEI0,\r
+//;0x03E8 Reserved\r
+ (fp)0,\r
+//;0x03EC Reserved\r
+ (fp)0,\r
+//;0x03F0 Reserved\r
+ (fp)0,\r
+//;0x03F4 Reserved\r
+ (fp)0,\r
+//;0x03F8 Reserved\r
+ (fp)0,\r
+//;0x03FC Reserved\r
+ (fp)0,\r
+};\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_cgc.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for CGC module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_cgc.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_CGC_Create\r
+* Description : This function initializes the clock generator.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_CGC_Create(void)\r
+{\r
+ uint32_t sckcr_dummy;\r
+ uint32_t w_count;\r
+\r
+ /* Set main clock control registers */\r
+ SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _20_CGC_MAINOSC_OVER10M;\r
+ SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768;\r
+\r
+ /* Set main clock operation */\r
+ SYSTEM.MOSCCR.BIT.MOSTP = 0U;\r
+\r
+ /* Wait for main clock oscillator wait counter overflow */\r
+ while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF);\r
+\r
+ /* Set system clock */\r
+ sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000000_CGC_PCLKB_DIV_1 | _00000000_CGC_ICLK_DIV_1 | \r
+ _00000000_CGC_FCLK_DIV_1;\r
+ SYSTEM.SCKCR.LONG = sckcr_dummy;\r
+\r
+ while (SYSTEM.SCKCR.LONG != sckcr_dummy);\r
+\r
+ /* Set PLL circuit */\r
+ SYSTEM.PLLCR.WORD = _0002_CGC_PLL_FREQ_DIV_4 | _0F00_CGC_PLL_FREQ_MUL_8;\r
+ SYSTEM.PLLCR2.BIT.PLLEN = 0U;\r
+\r
+ /* Wait for PLL wait counter overflow */\r
+ while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF);\r
+\r
+ /* Stop sub-clock */\r
+ SYSTEM.SOSCCR.BIT.SOSTP = 1U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (1U != SYSTEM.SOSCCR.BIT.SOSTP);\r
+\r
+ /* Stop sub-clock */\r
+ RTC.RCR3.BIT.RTCEN = 0U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (0U != RTC.RCR3.BIT.RTCEN);\r
+\r
+ /* Wait for 5 sub-clock cycles */\r
+ for (w_count = 0U; w_count < _007B_CGC_SUBSTPWT_WAIT; w_count++)\r
+ {\r
+ __asm volatile( "NOP" );\r
+ }\r
+\r
+ /* Set sub-clock drive capacity */\r
+ RTC.RCR3.BIT.RTCDV = 1U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (1U != RTC.RCR3.BIT.RTCDV);\r
+\r
+ /* Set sub-clock */\r
+ SYSTEM.SOSCCR.BIT.SOSTP = 0U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (0U != SYSTEM.SOSCCR.BIT.SOSTP);\r
+\r
+ /* Wait for sub-clock to be stable */\r
+ for (w_count = 0U; w_count < _00061A81_CGC_SUBOSCWT_WAIT; w_count++)\r
+ {\r
+ __asm volatile( "NOP" );\r
+ }\r
+\r
+ /* Set clock source */\r
+ SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL;\r
+\r
+ while (SYSTEM.SCKCR3.WORD != _0400_CGC_CLOCKSOURCE_PLL);\r
+\r
+ /* Set LOCO */\r
+ SYSTEM.LOCOCR.BIT.LCSTP = 1U;\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_cgc.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for CGC module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef CGC_H\r
+#define CGC_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+/*\r
+ System Clock Control Register (SCKCR)\r
+*/\r
+/* Peripheral Module Clock D (PCLKD) */\r
+#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */\r
+#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */\r
+#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */\r
+#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */\r
+#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */\r
+#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */\r
+#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */\r
+/* Peripheral Module Clock B (PCLKB) */\r
+#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */\r
+#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */\r
+#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */\r
+#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */\r
+#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */\r
+#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */\r
+#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */\r
+/* System Clock (ICLK) */\r
+#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */\r
+#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */\r
+#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */\r
+#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */\r
+#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */\r
+#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */\r
+#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */\r
+/* System Clock (FCLK) */\r
+#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */\r
+#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */\r
+#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */\r
+#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */\r
+#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */\r
+#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */\r
+#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */\r
+\r
+/*\r
+ System Clock Control Register 3 (SCKCR3)\r
+*/\r
+#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */\r
+#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */\r
+#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */\r
+#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */\r
+#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */\r
+\r
+/*\r
+ PLL Control Register (PLLCR)\r
+*/\r
+/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */\r
+#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */\r
+#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */\r
+#define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */\r
+/* Frequency Multiplication Factor Select (STC[5:0]) */\r
+#define _0B00_CGC_PLL_FREQ_MUL_6 (0x0B00U) /* x6 */\r
+#define _0F00_CGC_PLL_FREQ_MUL_8 (0x0F00U) /* x8 */\r
+\r
+/*\r
+ USB-dedicated PLL Control Register (UPLLCR)\r
+*/\r
+/* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */\r
+#define _0000_CGC_PLL_UPLIDIV_1 (0x0000U) /* x1 */\r
+#define _0001_CGC_PLL_UPLIDIV_2 (0x0001U) /* x1/2 */\r
+#define _0002_CGC_PLL_UPLIDIV_4 (0x0002U) /* x1/4 */\r
+/* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */\r
+#define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */\r
+#define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */\r
+/* Frequency Multiplication Factor Select (USTC[5:0]) */\r
+#define _0B00_CGC_PLL_USTC_6 (0x0B00U) /* x6 */\r
+#define _0F00_CGC_PLL_USTC_8 (0x0F00U) /* x8 */\r
+\r
+/*\r
+ Oscillation Stop Detection Control Register (OSTDCR)\r
+*/\r
+/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */\r
+#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */\r
+#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */\r
+/* Oscillation Stop Detection Function Enable (OSTDE) */\r
+#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */\r
+#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */\r
+\r
+/*\r
+ Main Clock Oscillator Wait Control Register (MOSCWTCR)\r
+*/\r
+/* Main Clock Oscillator Wait Time (MSTS[4:0]) */\r
+#define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */\r
+#define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */\r
+#define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */\r
+#define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */\r
+#define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */\r
+#define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */\r
+#define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */\r
+#define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */\r
+\r
+/*\r
+ HOCO Wait Control Register (HOCOWTCR)\r
+*/\r
+/* HOCO Wait Time (HOCOWTCR) */\r
+#define _05_CGC_HOCO_WAIT_CYCLE_138 (0x05U) /* Wait time = 138 cycles (34.5us) */\r
+#define _06_CGC_HOCO_WAIT_CYCLE_266 (0x06U) /* Wait time = 266 cycles (66.5us) */\r
+\r
+/*\r
+ Clock Output Control Register (CKOCR)\r
+*/\r
+/* Clock Output Source Select (CKOSEL[2:0]) */\r
+#define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */\r
+#define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */\r
+#define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */\r
+#define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */\r
+/* Clock Output Division Ratio Select (CKODIV[2:0]) */\r
+#define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */\r
+#define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */\r
+#define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */\r
+#define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */\r
+#define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */\r
+/* Clock Output Control (CKOSTP) */\r
+#define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */\r
+#define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */\r
+\r
+/*\r
+ Main Clock Oscillator Forced Oscillation Control Register (MOFCR)\r
+*/\r
+/* Main Oscillator Drive Capability Switch (MODRV21) */\r
+#define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */\r
+#define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */\r
+/* Main Clock Oscillator Switch (MOSEL) */\r
+#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */\r
+#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */\r
+\r
+/*\r
+ LCD Source Clock Control Register (LCDSCLKCR)\r
+*/\r
+/* LCD Source Clock Select (LCDSCLKSEL[2:0]) */\r
+#define _00_CGC_LCDSCLKSEL_LOCO (0x00U) /* LOCO */\r
+#define _01_CGC_LCDSCLKSEL_HOCO (0x01U) /* HOCO */\r
+#define _02_CGC_LCDSCLKSEL_MAINCLK (0x02U) /* Main clock oscillator */\r
+#define _03_CGC_LCDSCLKSEL_SUBCLK (0x03U) /* Sub-clock oscillator */\r
+#define _04_CGC_LCDSCLKSEL_IWDT (0x04U) /* IWDT-dedicated on-chip oscillator */\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+#define _007B_CGC_SUBSTPWT_WAIT (0x007BU) /* Wait time for 5 sub clock cycles */\r
+#define _00061A81_CGC_SUBOSCWT_WAIT (0x00061A81U) /* Wait time for sub clock stable */\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void R_CGC_Create(void);\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_cgc_user.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for CGC module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_cgc.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_hardware_setup.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements system initializing function.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_cgc.h"\r
+#include "r_cg_port.h"\r
+#include "r_cg_sci.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_Systeminit\r
+* Description : This function initializes every macro.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_Systeminit(void)\r
+{\r
+ /* Enable writing to registers related to operating modes, LPC, CGC and software reset */\r
+ SYSTEM.PRCR.WORD = 0xA50FU; \r
+\r
+ /* Enable writing to MPC pin function control registers */\r
+ MPC.PWPR.BIT.B0WI = 0U; \r
+ MPC.PWPR.BIT.PFSWE = 1U;\r
+\r
+ /* Initialize non-existent pins */\r
+ PORT0.PDR.BYTE = 0x6BU;\r
+ PORT3.PDR.BYTE = 0xD8U;\r
+ PORT4.PDR.BYTE = 0xA0U;\r
+ PORT5.PDR.BYTE = 0x80U;\r
+ PORT9.PDR.BYTE = 0xF8U;\r
+ PORTD.PDR.BYTE = 0xE0U;\r
+ PORTF.PDR.BYTE = 0x3FU;\r
+ PORTJ.PDR.BYTE = 0x32U;\r
+\r
+ /* Set peripheral settings */\r
+ R_CGC_Create();\r
+ R_PORT_Create();\r
+ R_SCI1_Create();\r
+\r
+ /* Disable writing to MPC pin function control registers */\r
+ MPC.PWPR.BIT.PFSWE = 0U; \r
+ MPC.PWPR.BIT.B0WI = 1U; \r
+\r
+ /* Enable protection */\r
+ SYSTEM.PRCR.WORD = 0xA500U; \r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: HardwareSetup\r
+* Description : This function initializes hardware setting.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void HardwareSetup(void)\r
+{\r
+ R_Systeminit();\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability\r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_macrodriver.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements general head file.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef MODULEID_H\r
+#define MODULEID_H\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "../iodefine.h"\r
+//_RB_#include <machine.h>\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+#ifndef __TYPEDEF__\r
+\r
+/* Status list definition */\r
+#define MD_STATUSBASE (0x00U)\r
+#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */\r
+#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */\r
+#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */\r
+#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */\r
+#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */\r
+\r
+/* Error list definition */\r
+#define MD_ERRORBASE (0x80U)\r
+#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */\r
+#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */\r
+#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */\r
+#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */\r
+#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */\r
+#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */\r
+#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */\r
+\r
+/* BRK handler command options */\r
+typedef enum {\r
+ BRK_NO_COMMAND,\r
+ BRK_ALL_MODULE_CLOCK_STOP,\r
+ BRK_SLEEP,\r
+ BRK_DEEP_SLEEP,\r
+ BRK_STANDBY,\r
+ BRK_LOAD_FINTV_REGISTER\r
+} brk_commands;\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+#ifndef __TYPEDEF__\r
+ #if !defined( _STD_USING_INT_TYPES ) && !defined( _STDINT )\r
+ #define _SYS_INT_TYPES_H\r
+ #ifndef _STD_USING_BIT_TYPES\r
+ #ifndef __int8_t_defined\r
+ #define __int8_t_defined\r
+ #endif\r
+ typedef signed char int8_t;\r
+ typedef signed short int16_t;\r
+ #endif\r
+\r
+ typedef unsigned char uint8_t;\r
+ typedef unsigned short uint16_t;\r
+ typedef signed long int32_t;\r
+ typedef unsigned long uint32_t;\r
+\r
+ typedef signed char int_least8_t;\r
+ typedef signed short int_least16_t;\r
+ typedef signed long int_least32_t;\r
+ typedef unsigned char uint_least8_t;\r
+ typedef unsigned short uint_least16_t;\r
+ typedef unsigned long uint_least32_t;\r
+ #endif\r
+\r
+ typedef unsigned short MD_STATUS;\r
+ #define __TYPEDEF__\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void HardwareSetup(void);\r
+void R_Systeminit(void);\r
+\r
+#endif\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_port.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for Port module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_port.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_PORT_Create\r
+* Description : This function initializes the Port I/O.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_PORT_Create(void)\r
+{\r
+ PORT2.PDR.BYTE = _04_Pm2_MODE_OUTPUT | _08_Pm3_MODE_OUTPUT | _10_Pm4_MODE_OUTPUT | _20_Pm5_MODE_OUTPUT | \r
+ _00_Pm7_MODE_INPUT;\r
+ PORT3.PDR.BYTE = _00_Pm2_MODE_INPUT | _D8_PDR3_DEFAULT;\r
+ PORTJ.PDR.BYTE = _00_Pm0_MODE_INPUT | _32_PDRJ_DEFAULT;\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_port.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for Port module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef PORT_H\r
+#define PORT_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+/*\r
+ Port Direction Register (PDR)\r
+*/\r
+/* Pmn Direction Control (B7 - B0) */\r
+#define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */\r
+#define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */\r
+#define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */\r
+#define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */\r
+#define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */\r
+#define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */\r
+#define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */\r
+#define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */\r
+#define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */\r
+#define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */\r
+#define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */\r
+#define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */\r
+#define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */\r
+#define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */\r
+#define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */\r
+#define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */\r
+#define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */\r
+#define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */\r
+#define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */\r
+#define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */\r
+#define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */\r
+#define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */\r
+#define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */\r
+#define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */\r
+\r
+/*\r
+ Port Output Data Register (PODR)\r
+*/\r
+/* Pmn Output Data Store (B7 - B0) */\r
+#define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */\r
+#define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */\r
+#define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */\r
+#define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */\r
+#define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */\r
+#define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */\r
+#define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */\r
+#define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */\r
+#define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */\r
+#define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */\r
+#define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */\r
+#define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */\r
+#define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */\r
+#define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */\r
+#define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */\r
+#define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */\r
+\r
+/*\r
+ Open Drain Control Register 0 (ODR0)\r
+*/\r
+/* Pmn Output Type Select (Pm0 to Pm3) */\r
+#define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
+#define _02_Pm0_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */\r
+#define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
+#define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */\r
+#define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
+#define _20_Pm2_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */\r
+#define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
+#define _80_Pm3_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */\r
+\r
+/*\r
+ Open Drain Control Register 1 (ODR1)\r
+*/\r
+/* Pmn Output Type Select (Pm4 to Pm7) */\r
+#define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
+#define _02_Pm4_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */\r
+#define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
+#define _08_Pm5_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */\r
+#define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
+#define _20_Pm6_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */\r
+#define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
+#define _80_Pm7_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */\r
+\r
+/*\r
+ Pull-Up Control Register (PCR)\r
+*/\r
+/* Pm0 Input Pull-Up Resistor Control ((B7 - B0)) */\r
+#define _00_Pm0_PULLUP_OFF (0x00U) /* Pn0 pull-up resistor not connected */\r
+#define _01_Pm0_PULLUP_ON (0x01U) /* Pn0 pull-up resistor connected */\r
+#define _00_Pm1_PULLUP_OFF (0x00U) /* Pn1 pull-up resistor not connected */\r
+#define _02_Pm1_PULLUP_ON (0x02U) /* Pn1 pull-up resistor connected */\r
+#define _00_Pm2_PULLUP_OFF (0x00U) /* Pn2 Pull-up resistor not connected */\r
+#define _04_Pm2_PULLUP_ON (0x04U) /* Pn2 pull-up resistor connected */\r
+#define _00_Pm3_PULLUP_OFF (0x00U) /* Pn3 pull-up resistor not connected */\r
+#define _08_Pm3_PULLUP_ON (0x08U) /* Pn3 pull-up resistor connected */\r
+#define _00_Pm4_PULLUP_OFF (0x00U) /* Pn4 pull-up resistor not connected */\r
+#define _10_Pm4_PULLUP_ON (0x10U) /* Pn4 pull-up resistor connected */\r
+#define _00_Pm5_PULLUP_OFF (0x00U) /* Pn5 pull-up resistor not connected */\r
+#define _20_Pm5_PULLUP_ON (0x20U) /* Pn5 pull-up resistor connected */\r
+#define _00_Pm6_PULLUP_OFF (0x00U) /* Pn6 pull-up resistor not connected */\r
+#define _40_Pm6_PULLUP_ON (0x40U) /* Pn6 pull-up resistor connected */\r
+#define _00_Pm7_PULLUP_OFF (0x00U) /* Pn7 pull-up resistor not connected */\r
+#define _80_Pm7_PULLUP_ON (0x80U) /* Pn7 pull-up resistor connected */\r
+\r
+/*\r
+ Port Switching Register A (PSRA)\r
+*/\r
+/* PB6/PC0 Switching (PSEL6) */\r
+#define _00_PORT_PSEL6_PB6 (0x00U) /* PB6 general I/O port function is selected */\r
+#define _40_PORT_PSEL6_PC0 (0x40U) /* PC0 general I/O port function is selected */\r
+/* PB7/PC1 Switching (PSEL7) */\r
+#define _00_PORT_PSEL7_PB7 (0x00U) /* PB7 general I/O port function is selected */\r
+#define _80_PORT_PSEL7_PC1 (0x80U) /* PC1 general I/O port function is selected */\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+#define _6B_PDR0_DEFAULT (0x6BU) /* PDR0 default value */\r
+#define _D8_PDR3_DEFAULT (0xD8U) /* PDR3 default value */\r
+#define _A0_PDR4_DEFAULT (0xA0U) /* PDR4 default value */\r
+#define _80_PDR5_DEFAULT (0x80U) /* PDR5 default value */\r
+#define _F8_PDR9_DEFAULT (0xF8U) /* PDR9 default value */\r
+#define _E0_PDRD_DEFAULT (0xE0U) /* PDRD default value */\r
+#define _3F_PDRF_DEFAULT (0x3FU) /* PDRF default value */\r
+#define _32_PDRJ_DEFAULT (0x32U) /* PDRJ default value */\r
+\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void R_PORT_Create(void);\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_port_user.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for Port module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_port.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_sbrk.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : Program of sbrk.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include <stddef.h>\r
+#include <stdio.h>\r
+#include "r_cg_sbrk.h"\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+\r
+int8_t *sbrk(size_t size);\r
+\r
+extern int8_t *_s1ptr;\r
+\r
+union HEAP_TYPE\r
+{\r
+ int16_t dummy ; /* Dummy for 4-byte boundary */\r
+ int8_t heap[HEAPSIZE]; /* Declaration of the area managed by sbrk */\r
+};\r
+\r
+static union HEAP_TYPE heap_area ;\r
+\r
+/* End address allocated by sbrk */\r
+static int8_t *brk = (int8_t *) &heap_area;\r
+\r
+/**************************************************************************/\r
+/* sbrk:Memory area allocation */\r
+/* Return value:Start address of allocated area (Pass) */\r
+/* -1 (Failure) */\r
+/**************************************************************************/\r
+int8_t *sbrk(size_t size) /* Assigned area size */\r
+{\r
+ int8_t *p;\r
+\r
+ if (brk+size > heap_area.heap + HEAPSIZE) /* Empty area size */\r
+ {\r
+ p = (int8_t *)-1;\r
+ }\r
+ else\r
+ {\r
+ p = brk; /* Area assignment */\r
+ brk += size; /* End address update */\r
+ }\r
+\r
+ return p;\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_sbrk.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : Header file of sbrk file.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef _SBRK_H\r
+#define _SBRK_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+#define HEAPSIZE (0x400U) /* Size of area managed by sbrk */\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_sci.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for SCI module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_sci.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+uint8_t * gp_sci1_tx_address; /* SCI1 transmit buffer address */\r
+uint16_t g_sci1_tx_count; /* SCI1 transmit data number */\r
+uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */\r
+uint16_t g_sci1_rx_count; /* SCI1 receive data number */\r
+uint16_t g_sci1_rx_length; /* SCI1 receive data length */\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCI1_Create\r
+* Description : This function initializes the SCI1.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_SCI1_Create(void)\r
+{\r
+ /* Cancel SCI1 module stop state */\r
+ MSTP(SCI1) = 0U;\r
+\r
+ /* Set interrupt priority */\r
+ IPR(SCI1, ERI1) = _0F_SCI_PRIORITY_LEVEL15;\r
+\r
+ /* Clear the SCR.TIE, RIE, TE, RE and TEIE bits */\r
+ SCI1.SCR.BIT.TIE = 0U;\r
+ SCI1.SCR.BIT.RIE = 0U;\r
+ SCI1.SCR.BIT.TE = 0U;\r
+ SCI1.SCR.BIT.RE = 0U;\r
+ SCI1.SCR.BIT.TEIE = 0U;\r
+\r
+ /* Set RXD1 pin */\r
+ MPC.P15PFS.BYTE = 0x0AU;\r
+ PORT1.PMR.BYTE |= 0x20U;\r
+ /* Set TXD1 pin */\r
+ MPC.P16PFS.BYTE = 0x0AU;\r
+ PORT1.PODR.BYTE |= 0x40U;\r
+ PORT1.PDR.BYTE |= 0x40U;\r
+ PORT1.PMR.BYTE |= 0x40U;\r
+\r
+ /* Set clock enable */\r
+ SCI1.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED;\r
+\r
+ /* Clear the SIMR1.IICM, SPMR.CKPH, and CKPOL bit */\r
+ SCI1.SIMR1.BIT.IICM = 0U;\r
+ SCI1.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED;\r
+\r
+ /* Set control registers */\r
+ SCI1.SMR.BYTE = _01_SCI_CLOCK_PCLK_4 | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | \r
+ _00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE;\r
+ SCI1.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | _72_SCI_SCMR_DEFAULT;\r
+\r
+ /* Set SEMR, SNFR */\r
+ SCI1.SEMR.BYTE = _00_SCI_LOW_LEVEL_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK;\r
+\r
+ /* Set bitrate */\r
+ SCI1.BRR = 0x19U;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCI1_Start\r
+* Description : This function starts the SCI1.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_SCI1_Start(void)\r
+{\r
+ IR(SCI1,TXI1) = 0U;\r
+ IR(SCI1,TEI1) = 0U;\r
+ IR(SCI1,RXI1) = 0U;\r
+ IR(SCI1,ERI1) = 0U;\r
+ IEN(SCI1,TXI1) = 1U;\r
+ IEN(SCI1,TEI1) = 1U;\r
+ IEN(SCI1,RXI1) = 1U;\r
+ IEN(SCI1,ERI1) = 1U;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCI1_Stop\r
+* Description : This function stops the SCI1.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_SCI1_Stop(void)\r
+{\r
+ /* Set TXD1 pin */\r
+ PORT1.PMR.BYTE &= 0xBFU;\r
+\r
+ SCI1.SCR.BYTE &= 0xCF; /* Disable serial transmit and receive */\r
+ SCI1.SCR.BIT.TIE = 0U; /* Disable TXI interrupt */\r
+ SCI1.SCR.BIT.RIE = 0U; /* Disable RXI and ERI interrupt */\r
+ IR(SCI1,TXI1) = 0U;\r
+ IEN(SCI1,TXI1) = 0U;\r
+ IR(SCI1,TEI1) = 0U;\r
+ IEN(SCI1,TEI1) = 0U;\r
+ IR(SCI1,RXI1) = 0U;\r
+ IEN(SCI1,RXI1) = 0U;\r
+ IR(SCI1,ERI1) = 0U;\r
+ IEN(SCI1,ERI1) = 0U;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCI1_Serial_Receive\r
+* Description : This function receives SCI1 data.\r
+* Arguments : rx_buf -\r
+* receive buffer pointer (Not used when receive data handled by DTC)\r
+* rx_num -\r
+* buffer size\r
+* Return Value : status -\r
+* MD_OK or MD_ARGERROR\r
+***********************************************************************************************************************/\r
+MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num)\r
+{\r
+ MD_STATUS status = MD_OK;\r
+\r
+ if (rx_num < 1U)\r
+ {\r
+ status = MD_ARGERROR;\r
+ }\r
+ else\r
+ {\r
+ g_sci1_rx_count = 0U;\r
+ g_sci1_rx_length = rx_num;\r
+ gp_sci1_rx_address = rx_buf;\r
+ SCI1.SCR.BIT.RIE = 1U;\r
+ SCI1.SCR.BIT.RE = 1U;\r
+ }\r
+\r
+ return (status);\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCI1_Serial_Send\r
+* Description : This function transmits SCI1 data.\r
+* Arguments : tx_buf -\r
+* transfer buffer pointer (Not used when transmit data handled by DTC)\r
+* tx_num -\r
+* buffer size\r
+* Return Value : status -\r
+* MD_OK or MD_ARGERROR\r
+***********************************************************************************************************************/\r
+MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num)\r
+{\r
+ MD_STATUS status = MD_OK;\r
+\r
+ if (tx_num < 1U)\r
+ {\r
+ status = MD_ARGERROR;\r
+ }\r
+ else\r
+ {\r
+ gp_sci1_tx_address = tx_buf;\r
+ g_sci1_tx_count = tx_num;\r
+ /* Set TXD1 pin */\r
+ PORT1.PMR.BYTE |= 0x40U;\r
+ SCI1.SCR.BIT.TIE = 1U;\r
+ SCI1.SCR.BIT.TE = 1U;\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_sci.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for SCI module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef SCI_H\r
+#define SCI_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+\r
+/*\r
+ Serial mode register (SMR)\r
+*/\r
+/* Clock select (CKS) */\r
+#define _00_SCI_CLOCK_PCLK (0x00U) /* PCLK */\r
+#define _01_SCI_CLOCK_PCLK_4 (0x01U) /* PCLK/4 */\r
+#define _02_SCI_CLOCK_PCLK_16 (0x02U) /* PCLK/16 */\r
+#define _03_SCI_CLOCK_PCLK_64 (0x03U) /* PCLK/64 */\r
+/* Multi-processor Mode (MP) */\r
+#define _00_SCI_MULTI_PROCESSOR_DISABLE (0x00U) /* Disable multiprocessor mode */\r
+#define _04_SCI_MULTI_PROCESSOR_ENABLE (0x04U) /* Enable multiprocessor mode */\r
+/* Stop bit length (STOP) */\r
+#define _00_SCI_STOP_1 (0x00U) /* 1 stop bit length */\r
+#define _08_SCI_STOP_2 (0x08U) /* 2 stop bits length */\r
+/* Parity mode (PM) */\r
+#define _00_SCI_PARITY_EVEN (0x00U) /* Parity even */\r
+#define _10_SCI_PARITY_ODD (0x10U) /* Parity odd */\r
+/* Parity enable (PE) */\r
+#define _00_SCI_PARITY_DISABLE (0x00U) /* Parity disable */\r
+#define _20_SCI_PARITY_ENABLE (0x20U) /* Parity enable */\r
+/* Character length (CHR) */\r
+#define _00_SCI_DATA_LENGTH_8 (0x00U) /* Data length 8 bits */\r
+#define _40_SCI_DATA_LENGTH_7 (0x40U) /* Data length 7 bits */\r
+/* Communications mode (CM) */\r
+#define _00_SCI_ASYNCHRONOUS_MODE (0x00U) /* Asynchronous mode */\r
+#define _80_SCI_CLOCK_SYNCHRONOUS_MODE (0x80U) /* Clock synchronous mode */\r
+/* Base clock pulse (BCP) */\r
+#define _00_SCI_32_93_CLOCK_CYCLES (0x00U) /* 32 or 93 clock cycles */\r
+#define _04_SCI_64_128_CLOCK_CYCLES (0x04U) /* 64 or 128 clock cycles */\r
+#define _08_SCI_186_372_CLOCK_CYCLES (0x08U) /* 186 or 372 clock cycles */\r
+#define _0C_SCI_256_512_CLOCK_CYCLES (0x0CU) /* 256 or 512 clock cycles */\r
+/* Block transfer mode (BLK) */\r
+#define _00_SCI_BLK_TRANSFER_DISABLE (0x00U) /* Block transfer disable */\r
+#define _40_SCI_BLK_TRANSFER_ENABLE (0x40U) /* Block transfer enable */\r
+/* GSM mode (GSM) */\r
+#define _00_SCI_GSM_DISABLE (0x00U) /* Normal mode operation */\r
+#define _80_SCI_GSM_ENABLE (0x80U) /* GSM mode operation */\r
+\r
+/*\r
+ Serial control register (SCR)\r
+*/\r
+/* Clock enable (CKE) */\r
+#define _00_SCI_INTERNAL_SCK_UNUSED (0x00U) /* Internal clock selected, SCK pin unused */\r
+#define _01_SCI_INTERNAL_SCK_OUTPUT (0x01U) /* Internal clock selected, SCK pin as clock output */\r
+#define _02_SCI_EXTERNAL (0x02U) /* External clock selected */\r
+#define _03_SCI_EXTERNAL (0x03U) /* External clock selected */\r
+/* Transmit end interrupt enable (TEIE) */\r
+#define _00_SCI_TEI_INTERRUPT_DISABLE (0x00U) /* TEI interrupt request disable */\r
+#define _04_SCI_TEI_INTERRUPT_ENABLE (0x04U) /* TEI interrupt request enable */\r
+/* Multi-processor interrupt enable (MPIE) */\r
+#define _00_SCI_MP_INTERRUPT_NORMAL (0x00U) /* Normal reception */\r
+#define _08_SCI_MP_INTERRUPT_SPECIAL (0x08U) /* Multi-processor ID reception */\r
+/* Receive enable (RE) */\r
+#define _00_SCI_RECEIVE_DISABLE (0x00U) /* Disable receive mode */\r
+#define _10_SCI_RECEIVE_ENABLE (0x10U) /* Enable receive mode */\r
+/* Transmit enable (TE) */\r
+#define _00_SCI_TRANSMIT_DISABLE (0x00U) /* Disable transmit mode */\r
+#define _20_SCI_TRANSMIT_ENABLE (0x20U) /* Enable transmit mode */\r
+/* Receive interrupt enable (RIE) */\r
+#define _00_SCI_RXI_ERI_DISABLE (0x00U) /* Disable RXI and ERI interrupt requests */\r
+#define _40_SCI_RXI_ERI_ENABLE (0x40U) /* Enable RXI and ERI interrupt requests */\r
+/* Transmit interrupt enable (TIE) */\r
+#define _00_SCI_TXI_DISABLE (0x00U) /* Disable TXI interrupt requests */\r
+#define _80_SCI_TXI_ENABLE (0x80U) /* Enable TXI interrupt requests */\r
+\r
+/*\r
+ Serial status register (SSR)\r
+*/\r
+/* Multi-Processor bit transfer (MPBT) */\r
+#define _00_SCI_SET_DATA_TRANSFER (0x00U) /* Set data transmission cycles */\r
+#define _01_SCI_SET_ID_TRANSFER (0x01U) /* Set ID transmission cycles */\r
+/* Multi-Processor (MPB) */\r
+#define _00_SCI_DATA_TRANSFER (0x00U) /* In data transmission cycles */\r
+#define _02_SCI_ID_TRANSFER (0x02U) /* In ID transmission cycles */\r
+/* Transmit end flag (TEND) */\r
+#define _00_SCI_TRANSMITTING (0x00U) /* A character is being transmitted */\r
+#define _04_SCI_TRANSMIT_COMPLETE (0x04U) /* Character transfer has been completed */\r
+/* Parity error flag (PER) */\r
+#define _08_SCI_PARITY_ERROR (0x08U) /* A parity error has occurred */\r
+/* Framing error flag (FER) */\r
+#define _10_SCI_FRAME_ERROR (0x10U) /* A framing error has occurred */\r
+/* Overrun error flag (ORER) */\r
+#define _20_SCI_OVERRUN_ERROR (0x20U) /* An overrun error has occurred */\r
+\r
+/*\r
+ Smart card mode register (SCMR)\r
+*/\r
+/* Smart card interface mode select (SMIF) */\r
+#define _00_SCI_SERIAL_MODE (0x00U) /* Serial communications interface mode */\r
+#define _01_SCI_SMART_CARD_MODE (0x01U) /* Smart card interface mode */\r
+/* Transmitted / received data invert (SINV) */\r
+#define _00_SCI_DATA_INVERT_NONE (0x00U) /* Data is not inverted */\r
+#define _04_SCI_DATA_INVERTED (0x04U) /* Data is inverted */\r
+/* Transmitted / received data transfer direction (SDIR) */\r
+#define _00_SCI_DATA_LSB_FIRST (0x00U) /* Transfer data LSB first */\r
+#define _08_SCI_DATA_MSB_FIRST (0x08U) /* Transfer data MSB first */\r
+/* Base clock pulse 2 (BCP2) */\r
+#define _00_SCI_93_128_186_512_CLK (0x00U) /* 93, 128, 186, or 512 clock cycles */\r
+#define _80_SCI_32_64_256_372_CLK (0x80U) /* 32, 64, 256, or 372 clock cycles */\r
+#define _72_SCI_SCMR_DEFAULT (0x72U) /* Write default value of SCMR */\r
+\r
+/* \r
+ Serial extended mode register (SEMR)\r
+*/\r
+/* Asynchronous Mode Clock Source Select (ACS0) */\r
+#define _00_SCI_ASYNC_SOURCE_EXTERNAL (0x00U) /* External clock input */\r
+#define _01_SCI_ASYNC_SOURCE_TMR (0x01U) /* Logical AND of two clock cycles output from TMR */\r
+/* Asynchronous mode base clock select (ABCS) */\r
+#define _00_SCI_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */\r
+#define _10_SCI_8_BASE_CLOCK (0x10U) /* Selects 8 base clock cycles for 1 bit period */ \r
+/* Digital noise filter function enable (NFEN) */\r
+#define _00_SCI_NOISE_FILTER_DISABLE (0x00U) /* Noise filter is disabled */\r
+#define _20_SCI_NOISE_FILTER_ENABLE (0x20U) /* Noise filter is enabled */\r
+/* Asynchronous start bit edge detections select (RXDESEL) */\r
+#define _00_SCI_LOW_LEVEL_START_BIT (0x00U) /* Low level on RXDn pin selected as start bit */\r
+#define _80_SCI_FALLING_EDGE_START_BIT (0x80U) /* Falling edge on RXDn pin selected as start bit */\r
+\r
+/*\r
+ Noise filter setting register (SNFR)\r
+*/\r
+/* Noise filter clock select (NFCS) */\r
+#define _00_SCI_ASYNC_DIV_1 (0x00U) /* Clock signal divided by 1 is used with the noise filter */\r
+#define _01_SCI_IIC_DIV_1 (0x01U) /* Clock signal divided by 1 is used with the noise filter */\r
+#define _02_SCI_IIC_DIV_2 (0x02U) /* Clock signal divided by 2 is used with the noise filter */\r
+#define _03_SCI_IIC_DIV_4 (0x03U) /* Clock signal divided by 4 is used with the noise filter */\r
+#define _04_SCI_IIC_DIV_8 (0x04U) /* Clock signal divided by 8 is used with the noise filter */\r
+\r
+/*\r
+ I2C mode register 1 (SIMR1)\r
+*/\r
+/* Simple IIC mode select (IICM) */\r
+#define _00_SCI_SERIAL_SMART_CARD_MODE (0x00U) /* Serial or smart card mode */\r
+#define _01_SCI_IIC_MODE (0x01U) /* Simple IIC mode */\r
+\r
+/*\r
+ I2C mode register 2 (SIMR2)\r
+*/\r
+/* IIC interrupt mode select (IICINTM) */\r
+#define _00_SCI_ACK_NACK_INTERRUPTS (0x00U) /* Use ACK/NACK interrupts */\r
+#define _01_SCI_RX_TX_INTERRUPTS (0x01U) /* Use reception/transmission interrupts */\r
+/* Clock synchronization (IICCSC) */\r
+#define _00_SCI_NO_SYNCHRONIZATION (0x00U) /* No synchronization with the clock signal */\r
+#define _02_SCI_SYNCHRONIZATION (0x02U) /* Synchronization with the clock signal */\r
+/* ACK transmission data (IICACKT) */\r
+#define _00_SCI_ACK_TRANSMISSION (0x00U) /* ACK transmission */\r
+#define _20_SCI_NACK_TRANSMISSION (0x20U) /* NACK transmission and reception of ACK/NACK */\r
+\r
+/*\r
+ I2C mode register 3 (SIMR3)\r
+*/\r
+/* Start condition generation (IICSTAREQ) */\r
+#define _00_SCI_START_CONDITION_OFF (0x00U) /* Start condition is not generated */\r
+#define _01_SCI_START_CONDITION_ON (0x01U) /* Start condition is generated */\r
+/* Restart condition generation (IICRSTAREQ) */\r
+#define _00_SCI_RESTART_CONDITION_OFF (0x00U) /* Restart condition is not generated */\r
+#define _02_SCI_RESTART_CONDITION_ON (0x02U) /* Restart condition is generated */\r
+/* Stop condition generation (IICSTPREQ) */\r
+#define _00_SCI_STOP_CONDITION_OFF (0x00U) /* Stop condition is not generated */\r
+#define _04_SCI_STOP_CONDITION_ON (0x04U) /* Stop condition is generated */\r
+/* Issuing of start, restart, or sstop condition completed flag (IICSTIF) */\r
+#define _00_SCI_CONDITION_GENERATED (0x00U) /* No requests to generate conditions/conditions generated */\r
+#define _08_SCI_GENERATION_COMPLETED (0x08U) /* All request generation has been completed */\r
+/* SSDA output select (IICSDAS) */\r
+#define _00_SCI_SSDA_DATA_OUTPUT (0x00U) /* SSDA output is serial data output */\r
+#define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10U) /* SSDA output generates start, restart or stop condition */\r
+#define _20_SCI_SSDA_LOW_LEVEL (0x20U) /* SSDA output low level */\r
+#define _30_SCI_SSDA_HIGH_IMPEDANCE (0x30U) /* SSDA output high impedance */\r
+/* SSCL output select (IICSCLS) */\r
+#define _00_SCI_SSCL_CLOCK_OUTPUT (0x00U) /* SSCL output is serial clock output */\r
+#define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40U) /* SSCL output generates start, restart or stop condition */\r
+#define _80_SCI_SSCL_LOW_LEVEL (0x80U) /* SSCL output low level */\r
+#define _C0_SCI_SSCL_HIGH_IMPEDANCE (0xC0U) /* SSCL output high impedance */\r
+\r
+/*\r
+ I2C status register (SISR)\r
+*/\r
+/* ACK reception data flag (IICACKR) */\r
+#define _00_SCI_ACK_RECEIVED (0x00U) /* ACK received */\r
+#define _01_SCI_NACK_RECEIVED (0x01U) /* NACK received */\r
+\r
+/*\r
+ SPI mode register (SPMR)\r
+*/\r
+/* SS pin function enable (SSE) */\r
+#define _00_SCI_SS_PIN_DISABLE (0x00U) /* SS pin function disabled */\r
+#define _01_SCI_SS_PIN_ENABLE (0x01U) /* SS pin function enabled */\r
+/* CTS enable (CTSE) */\r
+#define _00_SCI_RTS (0x00U) /* RTS function is enabled */\r
+#define _02_SCI_CTS (0x02U) /* CTS function is disabled */\r
+/* Master slave select (MSS) */\r
+#define _00_SCI_SPI_MASTER (0x00U) /* Master mode */\r
+#define _04_SCI_SPI_SLAVE (0x04U) /* Slave mode */\r
+/* Mode fault flag (MFF) */\r
+#define _00_SCI_NO_MODE_FAULT (0x00U) /* No mode fault */\r
+#define _10_SCI_MODE_FAULT (0x10U) /* Mode fault */\r
+/* Clock polarity select (CKPOL) */\r
+#define _00_SCI_CLOCK_NOT_INVERTED (0x00U) /* Clock polarity is not inverted */\r
+#define _40_SCI_CLOCK_INVERTED (0x40U) /* Clock polarity is inverted */\r
+/* Clock phase select (CKPH) */\r
+#define _00_SCI_CLOCK_NOT_DELAYED (0x00U) /* Clock is not delayed */\r
+#define _80_SCI_CLOCK_DELAYED (0x80U) /* Clock is delayed */\r
+\r
+/*\r
+ Interrupt Source Priority Register n (IPRn)\r
+*/\r
+/* Interrupt Priority Level Select (IPR[3:0]) */\r
+#define _00_SCI_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */\r
+#define _01_SCI_PRIORITY_LEVEL1 (0x01U) /* Level 1 */\r
+#define _02_SCI_PRIORITY_LEVEL2 (0x02U) /* Level 2 */\r
+#define _03_SCI_PRIORITY_LEVEL3 (0x03U) /* Level 3 */\r
+#define _04_SCI_PRIORITY_LEVEL4 (0x04U) /* Level 4 */\r
+#define _05_SCI_PRIORITY_LEVEL5 (0x05U) /* Level 5 */\r
+#define _06_SCI_PRIORITY_LEVEL6 (0x06U) /* Level 6 */\r
+#define _07_SCI_PRIORITY_LEVEL7 (0x07U) /* Level 7 */\r
+#define _08_SCI_PRIORITY_LEVEL8 (0x08U) /* Level 8 */\r
+#define _09_SCI_PRIORITY_LEVEL9 (0x09U) /* Level 9 */\r
+#define _0A_SCI_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */\r
+#define _0B_SCI_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */\r
+#define _0C_SCI_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */\r
+#define _0D_SCI_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */\r
+#define _0E_SCI_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */\r
+#define _0F_SCI_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */\r
+\r
+/*\r
+ Transfer status control value\r
+*/\r
+/* Simple IIC Transmit Receive Flag */\r
+#define _80_SCI_IIC_TRANSMISSION (0x80U)\r
+#define _00_SCI_IIC_RECEPTION (0x00U)\r
+/* Simple IIC Start Stop Flag */\r
+#define _80_SCI_IIC_START_CYCLE (0x80U)\r
+#define _00_SCI_IIC_STOP_CYCLE (0x00U)\r
+/* Multiprocessor Asynchronous Communication Flag */\r
+#define _80_SCI_ID_TRANSMISSION_CYCLE (0x80U)\r
+#define _00_SCI_DATA_TRANSMISSION_CYCLE (0x00U)\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void R_SCI1_Create(void);\r
+void R_SCI1_Start(void);\r
+void R_SCI1_Stop(void);\r
+MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num);\r
+MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num);\r
+static void r_sci1_callback_transmitend(void);\r
+static void r_sci1_callback_receiveend(void);\r
+static void r_sci1_callback_receiveerror(void);\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+\r
+/* Some of the code in this file is generated using "Code Generator" for e2 studio.\r
+ * Warnings exist in this module. */\r
+\r
+/* Exported functions used to transmit a number of bytes and wait for completion */\r
+MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num);\r
+\r
+/* Character is used to receive key presses from PC terminal */\r
+extern uint8_t g_rx_char;\r
+\r
+/* Flag used to control transmission to PC terminal */\r
+extern volatile uint8_t g_tx_flag;\r
+\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_sci_user.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for SCI module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_sci.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+#include "rskrx113def.h"\r
+//_RB_#include "r_cg_cmt.h"\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+extern uint8_t * gp_sci1_tx_address; /* SCI1 send buffer address */\r
+extern uint16_t g_sci1_tx_count; /* SCI1 send data number */\r
+extern uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */\r
+extern uint16_t g_sci1_rx_count; /* SCI1 receive data number */\r
+extern uint16_t g_sci1_rx_length; /* SCI1 receive data length */\r
+/* Start user code for global. Do not edit comment generated here */\r
+\r
+/* Global used to receive a character from the PC terminal */\r
+uint8_t g_rx_char;\r
+\r
+/* Flag used to control transmission to PC terminal */\r
+volatile uint8_t g_tx_flag = FALSE;\r
+\r
+/* Flag used locally to detect transmission complete */\r
+static volatile uint8_t sci1_txdone;\r
+\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_transmit_interrupt\r
+* Description : None\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TXI1\r
+#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1),fint)\r
+#else\r
+#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1))\r
+#endif\r
+static void r_sci1_transmit_interrupt(void)\r
+{\r
+ if (g_sci1_tx_count > 0U)\r
+ {\r
+ SCI1.TDR = *gp_sci1_tx_address;\r
+ gp_sci1_tx_address++;\r
+ g_sci1_tx_count--;\r
+ }\r
+ else \r
+ {\r
+ SCI1.SCR.BIT.TIE = 0U;\r
+ SCI1.SCR.BIT.TEIE = 1U;\r
+ }\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_transmitend_interrupt\r
+* Description : None\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TEI1\r
+#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1),fint)\r
+#else\r
+#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1))\r
+#endif\r
+static void r_sci1_transmitend_interrupt(void)\r
+{\r
+ /* Set TXD1 pin */\r
+ PORT1.PMR.BYTE &= 0xBFU;\r
+ SCI1.SCR.BIT.TIE = 0U;\r
+ SCI1.SCR.BIT.TE = 0U;\r
+ SCI1.SCR.BIT.TEIE = 0U;\r
+\r
+ r_sci1_callback_transmitend();\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_receive_interrupt\r
+* Description : None\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+#if FAST_INTERRUPT_VECTOR == VECT_SCI1_RXI1\r
+#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1),fint)\r
+#else\r
+#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1))\r
+#endif\r
+static void r_sci1_receive_interrupt(void)\r
+{\r
+ if (g_sci1_rx_length > g_sci1_rx_count)\r
+ {\r
+ *gp_sci1_rx_address = SCI1.RDR;\r
+ gp_sci1_rx_address++;\r
+ g_sci1_rx_count++;\r
+\r
+ if (g_sci1_rx_length == g_sci1_rx_count)\r
+ {\r
+ r_sci1_callback_receiveend();\r
+ }\r
+ }\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_receiveerror_interrupt\r
+* Description : None\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+#if FAST_INTERRUPT_VECTOR == VECT_SCI1_ERI1\r
+#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1),fint)\r
+#else\r
+#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1))\r
+#endif\r
+static void r_sci1_receiveerror_interrupt(void)\r
+{\r
+ uint8_t err_type;\r
+\r
+ r_sci1_callback_receiveerror();\r
+\r
+ /* Clear overrun, framing and parity error flags */\r
+ err_type = SCI1.SSR.BYTE;\r
+ SCI1.SSR.BYTE = err_type & 0xC7U;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_callback_transmitend\r
+* Description : This function is a callback function when SCI1 finishes transmission.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+static void r_sci1_callback_transmitend(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ sci1_txdone = TRUE;\r
+\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_callback_receiveend\r
+* Description : This function is a callback function when SCI1 finishes reception.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+static void r_sci1_callback_receiveend(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ /* Check the contents of g_rx_char */\r
+ if ('z' == g_rx_char)\r
+ {\r
+ /* Stop the timer used to control transmission to PC terminal*/\r
+//_RB_ R_CMT0_Stop();\r
+\r
+ /* Turn off LED0 and turn on LED1 to indicate serial transmission\r
+ inactive */\r
+ LED0 = LED_OFF;\r
+ LED1 = LED_ON;\r
+ }\r
+ else\r
+ {\r
+ /* Start the timer used to control transmission to PC terminal*/\r
+//_RB_ R_CMT0_Start();\r
+\r
+ /* Turn on LED0 and turn off LED1 to indicate serial transmission\r
+ active */\r
+ LED0 = LED_ON;\r
+ LED1 = LED_OFF;\r
+ }\r
+\r
+ /* Set up SCI1 receive buffer again */\r
+ R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
+\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_callback_receiveerror\r
+* Description : This function is a callback function when SCI1 reception encounters error.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+static void r_sci1_callback_receiveerror(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/***********************************************************************************************************************\r
+ * Function Name: R_SCI1_AsyncTransmit\r
+ * Description : This function sends SCI1 data and waits for the transmit end flag.\r
+ * Arguments : tx_buf -\r
+ * transfer buffer pointer\r
+ * tx_num -\r
+ * buffer size\r
+ * Return Value : status -\r
+ * MD_OK or MD_ARGERROR\r
+ ***********************************************************************************************************************/\r
+MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num)\r
+{\r
+ MD_STATUS status = MD_OK;\r
+\r
+ /* clear the flag before initiating a new transmission */\r
+ sci1_txdone = FALSE;\r
+\r
+ /* Send the data using the API */\r
+ status = R_SCI1_Serial_Send(tx_buf, tx_num);\r
+\r
+ /* Wait for the transmit end flag */\r
+ while (FALSE == sci1_txdone)\r
+ {\r
+ /* Wait */\r
+ }\r
+ return (status);\r
+}\r
+/***********************************************************************************************************************\r
+ * End of function R_SCI1_AsyncTransmit\r
+ ***********************************************************************************************************************/\r
+\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_userdefine.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file includes user definition.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef _USER_DEF_H\r
+#define _USER_DEF_H\r
+\r
+/***********************************************************************************************************************\r
+User definitions\r
+***********************************************************************************************************************/\r
+#define FAST_INTERRUPT_VECTOR 0\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+#define TRUE (1)\r
+#define FALSE (0)\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
--- /dev/null
+/***************************************************************/\r
+/* */\r
+/* PROJECT NAME : RTOSDemo */\r
+/* FILE : iodefine.h */\r
+/* DESCRIPTION : Definition of I/O Registers */\r
+/* CPU SERIES : RX100 */\r
+/* CPU TYPE : RX113 */\r
+/* */\r
+/* This file is generated by e2 studio. */\r
+/* */\r
+/***************************************************************/ \r
+ \r
+ \r
+ \r
+ \r
+/*********************************************************************************\r
+*\r
+* Device : RX/RX100/RX113\r
+*\r
+* File Name : iodefine.h\r
+*\r
+* Abstract : Definition of I/O Register.\r
+*\r
+* History : 0.4 (2013-11-18) [Hardware Manual Revision : 0.40]\r
+* : 0.5 (2014-01-05) [Hardware Manual Revision : 0.50]\r
+* : 1.0 (2014-07-22) [Hardware Manual Revision : 1.00]\r
+* : 1.0A (2015-04-20) [Hardware Manual Revision : 1.02 + TU]\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright (C) 2015 (2013 - 2014) Renesas Electronics Corporation.\r
+*\r
+*********************************************************************************/\r
+/********************************************************************************/\r
+/* */\r
+/* DESCRIPTION : Definition of ICU Register */\r
+/* CPU TYPE : RX113 */\r
+/* */\r
+/* Usage : IR,DTCER,IER,IPR of ICU Register */\r
+/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */\r
+/* The bit access operation is "Bit_Name(interrupt source,name)". */\r
+/* A part of the name can be omitted. */\r
+/* for example : */\r
+/* IR(MTU0,TGIA0) = 0; expands to : */\r
+/* ICU.IR[114].BIT.IR = 0; */\r
+/* */\r
+/* DTCE(ICU,IRQ0) = 1; expands to : */\r
+/* ICU.DTCER[64].BIT.DTCE = 1; */\r
+/* */\r
+/* IEN(CMT0,CMI0) = 1; expands to : */\r
+/* ICU.IER[0x03].BIT.IEN4 = 1; */\r
+/* */\r
+/* Usage : #pragma interrupt Function_Identifier(vect=**) */\r
+/* The number of vector is "(interrupt source, name)". */\r
+/* for example : */\r
+/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */\r
+/* #pragma interrupt INT_IRQ0(vect=64) */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=28) */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */\r
+/* */\r
+/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */\r
+/* The bit access operation is "MSTP(name)". */\r
+/* The name that can be used is a macro name defined with "iodefine.h". */\r
+/* for example : */\r
+/* MSTP(TMR2) = 0; // TMR23,TMR2,TMR3 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */\r
+/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */\r
+/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */\r
+/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */\r
+/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */\r
+/* */\r
+/* */\r
+/********************************************************************************/\r
+#ifndef __RX113IODEFINE_HEADER__\r
+#define __RX113IODEFINE_HEADER__\r
+\r
+#pragma pack(4)\r
+\r
+struct st_bsc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char STSCLR : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char STSCLR : 1;\r
+#endif\r
+ } BIT;\r
+ } BERCLR;\r
+ char wk0[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IGAEN : 1;\r
+ unsigned char TOEN : 1;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char TOEN : 1;\r
+ unsigned char IGAEN : 1;\r
+#endif\r
+ } BIT;\r
+ } BEREN;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IA : 1;\r
+ unsigned char TO : 1;\r
+ unsigned char : 2;\r
+ unsigned char MST : 3;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char MST : 3;\r
+ unsigned char : 2;\r
+ unsigned char TO : 1;\r
+ unsigned char IA : 1;\r
+#endif\r
+ } BIT;\r
+ } BERSR1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 3;\r
+ unsigned short ADDR : 13;\r
+#else\r
+ unsigned short ADDR : 13;\r
+ unsigned short : 3;\r
+#endif\r
+ } BIT;\r
+ } BERSR2;\r
+ char wk3[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short BPRA : 2;\r
+ unsigned short BPRO : 2;\r
+ unsigned short BPIB : 2;\r
+ unsigned short BPGB : 2;\r
+ unsigned short : 2;\r
+ unsigned short BPFB : 2;\r
+ unsigned short : 4;\r
+#else\r
+ unsigned short : 4;\r
+ unsigned short BPFB : 2;\r
+ unsigned short : 2;\r
+ unsigned short BPGB : 2;\r
+ unsigned short BPIB : 2;\r
+ unsigned short BPRO : 2;\r
+ unsigned short BPRA : 2;\r
+#endif\r
+ } BIT;\r
+ } BUSPRI;\r
+};\r
+\r
+struct st_cac {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CFME : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char CFME : 1;\r
+#endif\r
+ } BIT;\r
+ } CACR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CACREFE : 1;\r
+ unsigned char FMCS : 3;\r
+ unsigned char TCSS : 2;\r
+ unsigned char EDGES : 2;\r
+#else\r
+ unsigned char EDGES : 2;\r
+ unsigned char TCSS : 2;\r
+ unsigned char FMCS : 3;\r
+ unsigned char CACREFE : 1;\r
+#endif\r
+ } BIT;\r
+ } CACR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char RPS : 1;\r
+ unsigned char RSCS : 3;\r
+ unsigned char RCDS : 2;\r
+ unsigned char DFS : 2;\r
+#else\r
+ unsigned char DFS : 2;\r
+ unsigned char RCDS : 2;\r
+ unsigned char RSCS : 3;\r
+ unsigned char RPS : 1;\r
+#endif\r
+ } BIT;\r
+ } CACR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char FERRIE : 1;\r
+ unsigned char MENDIE : 1;\r
+ unsigned char OVFIE : 1;\r
+ unsigned char : 1;\r
+ unsigned char FERRFCL : 1;\r
+ unsigned char MENDFCL : 1;\r
+ unsigned char OVFFCL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char OVFFCL : 1;\r
+ unsigned char MENDFCL : 1;\r
+ unsigned char FERRFCL : 1;\r
+ unsigned char : 1;\r
+ unsigned char OVFIE : 1;\r
+ unsigned char MENDIE : 1;\r
+ unsigned char FERRIE : 1;\r
+#endif\r
+ } BIT;\r
+ } CAICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char FERRF : 1;\r
+ unsigned char MENDF : 1;\r
+ unsigned char OVFF : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char OVFF : 1;\r
+ unsigned char MENDF : 1;\r
+ unsigned char FERRF : 1;\r
+#endif\r
+ } BIT;\r
+ } CASTR;\r
+ char wk0[1];\r
+ unsigned short CAULVR;\r
+ unsigned short CALLVR;\r
+ unsigned short CACNTBR;\r
+};\r
+\r
+struct st_cmpb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CPB0INI : 1;\r
+ unsigned char : 3;\r
+ unsigned char CPB1INI : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char CPB1INI : 1;\r
+ unsigned char : 3;\r
+ unsigned char CPB0INI : 1;\r
+#endif\r
+ } BIT;\r
+ } CPBCNT1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CPB0WCP : 1;\r
+ unsigned char : 3;\r
+ unsigned char CPB1WCP : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char CPB1WCP : 1;\r
+ unsigned char : 3;\r
+ unsigned char CPB0WCP : 1;\r
+#endif\r
+ } BIT;\r
+ } CPBCNT2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 3;\r
+ unsigned char CPB0OUT : 1;\r
+ unsigned char : 3;\r
+ unsigned char CPB1OUT : 1;\r
+#else\r
+ unsigned char CPB1OUT : 1;\r
+ unsigned char : 3;\r
+ unsigned char CPB0OUT : 1;\r
+ unsigned char : 3;\r
+#endif\r
+ } BIT;\r
+ } CPBFLG;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CPB0INTEN : 1;\r
+ unsigned char CPB0INTEG : 1;\r
+ unsigned char CPB0INTPL : 1;\r
+ unsigned char : 1;\r
+ unsigned char CPB1INTEN : 1;\r
+ unsigned char CPB1INTEG : 1;\r
+ unsigned char CPB1INTPL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char CPB1INTPL : 1;\r
+ unsigned char CPB1INTEG : 1;\r
+ unsigned char CPB1INTEN : 1;\r
+ unsigned char : 1;\r
+ unsigned char CPB0INTPL : 1;\r
+ unsigned char CPB0INTEG : 1;\r
+ unsigned char CPB0INTEN : 1;\r
+#endif\r
+ } BIT;\r
+ } CPBINT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CPB0FEN : 1;\r
+ unsigned char : 1;\r
+ unsigned char CPB0F : 2;\r
+ unsigned char CPB1FEN : 1;\r
+ unsigned char : 1;\r
+ unsigned char CPB1F : 2;\r
+#else\r
+ unsigned char CPB1F : 2;\r
+ unsigned char : 1;\r
+ unsigned char CPB1FEN : 1;\r
+ unsigned char CPB0F : 2;\r
+ unsigned char : 1;\r
+ unsigned char CPB0FEN : 1;\r
+#endif\r
+ } BIT;\r
+ } CPBF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CPBSPDMD : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char CPBSPDMD : 1;\r
+#endif\r
+ } BIT;\r
+ } CPBMD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CPB0VRF : 1;\r
+ unsigned char : 3;\r
+ unsigned char CPB1VRF : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char CPB1VRF : 1;\r
+ unsigned char : 3;\r
+ unsigned char CPB0VRF : 1;\r
+#endif\r
+ } BIT;\r
+ } CPBREF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CPB0OE : 1;\r
+ unsigned char CPB0OP : 1;\r
+ unsigned char : 2;\r
+ unsigned char CPB1OE : 1;\r
+ unsigned char CPB1OP : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char CPB1OP : 1;\r
+ unsigned char CPB1OE : 1;\r
+ unsigned char : 2;\r
+ unsigned char CPB0OP : 1;\r
+ unsigned char CPB0OE : 1;\r
+#endif\r
+ } BIT;\r
+ } CPBOCR;\r
+};\r
+\r
+struct st_cmt {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short STR0 : 1;\r
+ unsigned short STR1 : 1;\r
+ unsigned short : 14;\r
+#else\r
+ unsigned short : 14;\r
+ unsigned short STR1 : 1;\r
+ unsigned short STR0 : 1;\r
+#endif\r
+ } BIT;\r
+ } CMSTR0;\r
+ char wk0[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short STR2 : 1;\r
+ unsigned short STR3 : 1;\r
+ unsigned short : 14;\r
+#else\r
+ unsigned short : 14;\r
+ unsigned short STR3 : 1;\r
+ unsigned short STR2 : 1;\r
+#endif\r
+ } BIT;\r
+ } CMSTR1;\r
+};\r
+\r
+struct st_cmt0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CKS : 2;\r
+ unsigned short : 4;\r
+ unsigned short CMIE : 1;\r
+ unsigned short : 9;\r
+#else\r
+ unsigned short : 9;\r
+ unsigned short CMIE : 1;\r
+ unsigned short : 4;\r
+ unsigned short CKS : 2;\r
+#endif\r
+ } BIT;\r
+ } CMCR;\r
+ unsigned short CMCNT;\r
+ unsigned short CMCOR;\r
+};\r
+\r
+struct st_crc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char GPS : 2;\r
+ unsigned char LMS : 1;\r
+ unsigned char : 4;\r
+ unsigned char DORCLR : 1;\r
+#else\r
+ unsigned char DORCLR : 1;\r
+ unsigned char : 4;\r
+ unsigned char LMS : 1;\r
+ unsigned char GPS : 2;\r
+#endif\r
+ } BIT;\r
+ } CRCCR;\r
+ unsigned char CRCDIR;\r
+ unsigned short CRCDOR;\r
+};\r
+\r
+struct st_ctsu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUSTRT : 1;\r
+ unsigned char CTSUCAP : 1;\r
+ unsigned char CTSUSNZ : 1;\r
+ unsigned char : 1;\r
+ unsigned char CTSUINIT : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char CTSUINIT : 1;\r
+ unsigned char : 1;\r
+ unsigned char CTSUSNZ : 1;\r
+ unsigned char CTSUCAP : 1;\r
+ unsigned char CTSUSTRT : 1;\r
+#endif\r
+ } BIT;\r
+ } CTSUCR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUPON : 1;\r
+ unsigned char CTSUCSW : 1;\r
+ unsigned char CTSUATUNE0 : 1;\r
+ unsigned char CTSUATUNE1 : 1;\r
+ unsigned char CTSUCLK : 2;\r
+ unsigned char CTSUMD : 2;\r
+#else\r
+ unsigned char CTSUMD : 2;\r
+ unsigned char CTSUCLK : 2;\r
+ unsigned char CTSUATUNE1 : 1;\r
+ unsigned char CTSUATUNE0 : 1;\r
+ unsigned char CTSUCSW : 1;\r
+ unsigned char CTSUPON : 1;\r
+#endif\r
+ } BIT;\r
+ } CTSUCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUPRRATIO : 4;\r
+ unsigned char CTSUPRMODE : 2;\r
+ unsigned char CTSUSOFF : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char CTSUSOFF : 1;\r
+ unsigned char CTSUPRMODE : 2;\r
+ unsigned char CTSUPRRATIO : 4;\r
+#endif\r
+ } BIT;\r
+ } CTSUSDPRS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUSST : 8;\r
+#else\r
+ unsigned char CTSUSST : 8;\r
+#endif\r
+ } BIT;\r
+ } CTSUSST;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUMCH0 : 4;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char CTSUMCH0 : 4;\r
+#endif\r
+ } BIT;\r
+ } CTSUMCH0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUMCH1 : 4;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char CTSUMCH1 : 4;\r
+#endif\r
+ } BIT;\r
+ } CTSUMCH1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUCHAC00 : 1;\r
+ unsigned char CTSUCHAC01 : 1;\r
+ unsigned char CTSUCHAC02 : 1;\r
+ unsigned char CTSUCHAC03 : 1;\r
+ unsigned char CTSUCHAC04 : 1;\r
+ unsigned char CTSUCHAC05 : 1;\r
+ unsigned char CTSUCHAC06 : 1;\r
+ unsigned char CTSUCHAC07 : 1;\r
+#else\r
+ unsigned char CTSUCHAC07 : 1;\r
+ unsigned char CTSUCHAC06 : 1;\r
+ unsigned char CTSUCHAC05 : 1;\r
+ unsigned char CTSUCHAC04 : 1;\r
+ unsigned char CTSUCHAC03 : 1;\r
+ unsigned char CTSUCHAC02 : 1;\r
+ unsigned char CTSUCHAC01 : 1;\r
+ unsigned char CTSUCHAC00 : 1;\r
+#endif\r
+ } BIT;\r
+ } CTSUCHAC0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUCHAC10 : 1;\r
+ unsigned char CTSUCHAC11 : 1;\r
+ unsigned char CTSUCHAC12 : 1;\r
+ unsigned char CTSUCHAC13 : 1;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char CTSUCHAC13 : 1;\r
+ unsigned char CTSUCHAC12 : 1;\r
+ unsigned char CTSUCHAC11 : 1;\r
+ unsigned char CTSUCHAC10 : 1;\r
+#endif\r
+ } BIT;\r
+ } CTSUCHAC1;\r
+ char wk0[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUCHTRC00 : 1;\r
+ unsigned char CTSUCHTRC01 : 1;\r
+ unsigned char CTSUCHTRC02 : 1;\r
+ unsigned char CTSUCHTRC03 : 1;\r
+ unsigned char CTSUCHTRC04 : 1;\r
+ unsigned char CTSUCHTRC05 : 1;\r
+ unsigned char CTSUCHTRC06 : 1;\r
+ unsigned char CTSUCHTRC07 : 1;\r
+#else\r
+ unsigned char CTSUCHTRC07 : 1;\r
+ unsigned char CTSUCHTRC06 : 1;\r
+ unsigned char CTSUCHTRC05 : 1;\r
+ unsigned char CTSUCHTRC04 : 1;\r
+ unsigned char CTSUCHTRC03 : 1;\r
+ unsigned char CTSUCHTRC02 : 1;\r
+ unsigned char CTSUCHTRC01 : 1;\r
+ unsigned char CTSUCHTRC00 : 1;\r
+#endif\r
+ } BIT;\r
+ } CTSUCHTRC0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUCHTRC10 : 1;\r
+ unsigned char CTSUCHTRC11 : 1;\r
+ unsigned char CTSUCHTRC12 : 1;\r
+ unsigned char CTSUCHTRC13 : 1;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char CTSUCHTRC13 : 1;\r
+ unsigned char CTSUCHTRC12 : 1;\r
+ unsigned char CTSUCHTRC11 : 1;\r
+ unsigned char CTSUCHTRC10 : 1;\r
+#endif\r
+ } BIT;\r
+ } CTSUCHTRC1;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUSSMOD : 2;\r
+ unsigned char : 2;\r
+ unsigned char CTSUSSCNT : 2;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char CTSUSSCNT : 2;\r
+ unsigned char : 2;\r
+ unsigned char CTSUSSMOD : 2;\r
+#endif\r
+ } BIT;\r
+ } CTSUDCLKC;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CTSUSTC : 3;\r
+ unsigned char : 1;\r
+ unsigned char CTSUDTSR : 1;\r
+ unsigned char CTSUSOVF : 1;\r
+ unsigned char CTSUROVF : 1;\r
+ unsigned char CTSUPS : 1;\r
+#else\r
+ unsigned char CTSUPS : 1;\r
+ unsigned char CTSUROVF : 1;\r
+ unsigned char CTSUSOVF : 1;\r
+ unsigned char CTSUDTSR : 1;\r
+ unsigned char : 1;\r
+ unsigned char CTSUSTC : 3;\r
+#endif\r
+ } BIT;\r
+ } CTSUST;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 8;\r
+ unsigned short CTSUSSDIV : 4;\r
+ unsigned short : 4;\r
+#else\r
+ unsigned short : 4;\r
+ unsigned short CTSUSSDIV : 4;\r
+ unsigned short : 8;\r
+#endif\r
+ } BIT;\r
+ } CTSUSSC;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CTSUSO : 10;\r
+ unsigned short CTSUSNUM : 6;\r
+#else\r
+ unsigned short CTSUSNUM : 6;\r
+ unsigned short CTSUSO : 10;\r
+#endif\r
+ } BIT;\r
+ } CTSUSO0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CTSURICOA : 8;\r
+ unsigned short CTSUSDPA : 5;\r
+ unsigned short CTSUICOG : 2;\r
+ unsigned short : 1;\r
+#else\r
+ unsigned short : 1;\r
+ unsigned short CTSUICOG : 2;\r
+ unsigned short CTSUSDPA : 5;\r
+ unsigned short CTSURICOA : 8;\r
+#endif\r
+ } BIT;\r
+ } CTSUSO1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CTSUSC : 16;\r
+#else\r
+ unsigned short CTSUSC : 16;\r
+#endif\r
+ } BIT;\r
+ } CTSUSC;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CTSURC : 16;\r
+#else\r
+ unsigned short CTSURC : 16;\r
+#endif\r
+ } BIT;\r
+ } CTSURC;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 15;\r
+ unsigned short CTSUICOMP : 1;\r
+#else\r
+ unsigned short CTSUICOMP : 1;\r
+ unsigned short : 15;\r
+#endif\r
+ } BIT;\r
+ } CTSUERRS;\r
+};\r
+\r
+struct st_da {\r
+ unsigned short DADR0;\r
+ unsigned short DADR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 6;\r
+ unsigned char DAOE0 : 1;\r
+ unsigned char DAOE1 : 1;\r
+#else\r
+ unsigned char DAOE1 : 1;\r
+ unsigned char DAOE0 : 1;\r
+ unsigned char : 6;\r
+#endif\r
+ } BIT;\r
+ } DACR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char DPSEL : 1;\r
+#else\r
+ unsigned char DPSEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } DADPR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char DAADST : 1;\r
+#else\r
+ unsigned char DAADST : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } DAADSCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char REF : 3;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char REF : 3;\r
+#endif\r
+ } BIT;\r
+ } DAVREFCR;\r
+};\r
+\r
+struct st_doc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char OMS : 2;\r
+ unsigned char DCSEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char DOPCIE : 1;\r
+ unsigned char DOPCF : 1;\r
+ unsigned char DOPCFCL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char DOPCFCL : 1;\r
+ unsigned char DOPCF : 1;\r
+ unsigned char DOPCIE : 1;\r
+ unsigned char : 1;\r
+ unsigned char DCSEL : 1;\r
+ unsigned char OMS : 2;\r
+#endif\r
+ } BIT;\r
+ } DOCR;\r
+ char wk0[1];\r
+ unsigned short DODIR;\r
+ unsigned short DODSR;\r
+};\r
+\r
+struct st_dtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 4;\r
+ unsigned char RRS : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char RRS : 1;\r
+ unsigned char : 4;\r
+#endif\r
+ } BIT;\r
+ } DTCCR;\r
+ char wk0[3];\r
+ void *DTCVBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SHORT : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char SHORT : 1;\r
+#endif\r
+ } BIT;\r
+ } DTCADMOD;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char DTCST : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char DTCST : 1;\r
+#endif\r
+ } BIT;\r
+ } DTCST;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short VECN : 8;\r
+ unsigned short : 7;\r
+ unsigned short ACT : 1;\r
+#else\r
+ unsigned short ACT : 1;\r
+ unsigned short : 7;\r
+ unsigned short VECN : 8;\r
+#endif\r
+ } BIT;\r
+ } DTCSTS;\r
+};\r
+\r
+struct st_elc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ELCON : 1;\r
+#else\r
+ unsigned char ELCON : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } ELCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char ELS : 8;\r
+#else\r
+ unsigned char ELS : 8;\r
+#endif\r
+ } BIT;\r
+ } ELSR[26];\r
+ char wk0[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 2;\r
+ unsigned char MTU1MD : 2;\r
+ unsigned char MTU2MD : 2;\r
+ unsigned char MTU3MD : 2;\r
+#else\r
+ unsigned char MTU3MD : 2;\r
+ unsigned char MTU2MD : 2;\r
+ unsigned char MTU1MD : 2;\r
+ unsigned char : 2;\r
+#endif\r
+ } BIT;\r
+ } ELOPA;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MTU4MD : 2;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char MTU4MD : 2;\r
+#endif\r
+ } BIT;\r
+ } ELOPB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 2;\r
+ unsigned char CMT1MD : 2;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char CMT1MD : 2;\r
+ unsigned char : 2;\r
+#endif\r
+ } BIT;\r
+ } ELOPC;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TMR0MD : 2;\r
+ unsigned char : 2;\r
+ unsigned char TMR2MD : 2;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char TMR2MD : 2;\r
+ unsigned char : 2;\r
+ unsigned char TMR0MD : 2;\r
+#endif\r
+ } BIT;\r
+ } ELOPD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PGR0 : 1;\r
+ unsigned char PGR1 : 1;\r
+ unsigned char PGR2 : 1;\r
+ unsigned char PGR3 : 1;\r
+ unsigned char PGR4 : 1;\r
+ unsigned char PGR5 : 1;\r
+ unsigned char PGR6 : 1;\r
+ unsigned char PGR7 : 1;\r
+#else\r
+ unsigned char PGR7 : 1;\r
+ unsigned char PGR6 : 1;\r
+ unsigned char PGR5 : 1;\r
+ unsigned char PGR4 : 1;\r
+ unsigned char PGR3 : 1;\r
+ unsigned char PGR2 : 1;\r
+ unsigned char PGR1 : 1;\r
+ unsigned char PGR0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PGR1;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PGCI : 2;\r
+ unsigned char PGCOVE : 1;\r
+ unsigned char : 1;\r
+ unsigned char PGCO : 3;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char PGCO : 3;\r
+ unsigned char : 1;\r
+ unsigned char PGCOVE : 1;\r
+ unsigned char PGCI : 2;\r
+#endif\r
+ } BIT;\r
+ } PGC1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PDBF0 : 1;\r
+ unsigned char PDBF1 : 1;\r
+ unsigned char PDBF2 : 1;\r
+ unsigned char PDBF3 : 1;\r
+ unsigned char PDBF4 : 1;\r
+ unsigned char PDBF5 : 1;\r
+ unsigned char PDBF6 : 1;\r
+ unsigned char PDBF7 : 1;\r
+#else\r
+ unsigned char PDBF7 : 1;\r
+ unsigned char PDBF6 : 1;\r
+ unsigned char PDBF5 : 1;\r
+ unsigned char PDBF4 : 1;\r
+ unsigned char PDBF3 : 1;\r
+ unsigned char PDBF2 : 1;\r
+ unsigned char PDBF1 : 1;\r
+ unsigned char PDBF0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDBF1;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSB : 3;\r
+ unsigned char PSP : 2;\r
+ unsigned char PSM : 2;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char PSM : 2;\r
+ unsigned char PSP : 2;\r
+ unsigned char PSB : 3;\r
+#endif\r
+ } BIT;\r
+ } PEL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSB : 3;\r
+ unsigned char PSP : 2;\r
+ unsigned char PSM : 2;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char PSM : 2;\r
+ unsigned char PSP : 2;\r
+ unsigned char PSB : 3;\r
+#endif\r
+ } BIT;\r
+ } PEL1;\r
+ char wk4[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SEG : 1;\r
+ unsigned char : 5;\r
+ unsigned char WE : 1;\r
+ unsigned char WI : 1;\r
+#else\r
+ unsigned char WI : 1;\r
+ unsigned char WE : 1;\r
+ unsigned char : 5;\r
+ unsigned char SEG : 1;\r
+#endif\r
+ } BIT;\r
+ } ELSEGR;\r
+};\r
+\r
+struct st_flash {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char DFLEN : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char DFLEN : 1;\r
+#endif\r
+ } BIT;\r
+ } DFLCTL;\r
+ char wk0[31];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 8;\r
+ unsigned short SASMF : 1;\r
+ unsigned short : 7;\r
+#else\r
+ unsigned short : 7;\r
+ unsigned short SASMF : 1;\r
+ unsigned short : 8;\r
+#endif\r
+ } BIT;\r
+ } FSCMR;\r
+ unsigned short FAWSMR;\r
+ unsigned short FAWEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PCKA : 5;\r
+ unsigned char : 1;\r
+ unsigned char SAS : 2;\r
+#else\r
+ unsigned char SAS : 2;\r
+ unsigned char : 1;\r
+ unsigned char PCKA : 5;\r
+#endif\r
+ } BIT;\r
+ } FISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CMD : 3;\r
+ unsigned char : 4;\r
+ unsigned char OPST : 1;\r
+#else\r
+ unsigned char OPST : 1;\r
+ unsigned char : 4;\r
+ unsigned char CMD : 3;\r
+#endif\r
+ } BIT;\r
+ } FEXCR;\r
+ unsigned short FEAML;\r
+// char wk1[1];\r
+ unsigned char FEAMH;\r
+ char wk2[5];\r
+ unsigned char FPR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PERR : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char PERR : 1;\r
+#endif\r
+ } BIT;\r
+ } FPSR;\r
+ unsigned short FRBL;\r
+ unsigned short FRBH;\r
+ char wk3[16058];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 1;\r
+ unsigned char FMS0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char RPDIS : 1;\r
+ unsigned char FMS1 : 1;\r
+ unsigned char : 1;\r
+ unsigned char LVPE : 1;\r
+ unsigned char FMS2 : 1;\r
+#else\r
+ unsigned char FMS2 : 1;\r
+ unsigned char LVPE : 1;\r
+ unsigned char : 1;\r
+ unsigned char FMS1 : 1;\r
+ unsigned char RPDIS : 1;\r
+ unsigned char : 1;\r
+ unsigned char FMS0 : 1;\r
+ unsigned char : 1;\r
+#endif\r
+ } BIT;\r
+ } FPMCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char EXS : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char EXS : 1;\r
+#endif\r
+ } BIT;\r
+ } FASR;\r
+ unsigned short FSARL;\r
+// char wk4[1];\r
+ unsigned char FSARH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CMD : 4;\r
+ unsigned char DRC : 1;\r
+ unsigned char : 1;\r
+ unsigned char STOP : 1;\r
+ unsigned char OPST : 1;\r
+#else\r
+ unsigned char OPST : 1;\r
+ unsigned char STOP : 1;\r
+ unsigned char : 1;\r
+ unsigned char DRC : 1;\r
+ unsigned char CMD : 4;\r
+#endif\r
+ } BIT;\r
+ } FCR;\r
+ unsigned short FEARL;\r
+ unsigned char FEARH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char FRESET : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char FRESET : 1;\r
+#endif\r
+ } BIT;\r
+ } FRESETR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char ERERR : 1;\r
+ unsigned char PRGERR : 1;\r
+ unsigned char : 1;\r
+ unsigned char BCERR : 1;\r
+ unsigned char ILGLERR : 1;\r
+ unsigned char EILGLERR : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char EILGLERR : 1;\r
+ unsigned char ILGLERR : 1;\r
+ unsigned char BCERR : 1;\r
+ unsigned char : 1;\r
+ unsigned char PRGERR : 1;\r
+ unsigned char ERERR : 1;\r
+#endif\r
+ } BIT;\r
+ } FSTATR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 1;\r
+ unsigned char DRRDY : 1;\r
+ unsigned char : 4;\r
+ unsigned char FRDY : 1;\r
+ unsigned char EXRDY : 1;\r
+#else\r
+ unsigned char EXRDY : 1;\r
+ unsigned char FRDY : 1;\r
+ unsigned char : 4;\r
+ unsigned char DRRDY : 1;\r
+ unsigned char : 1;\r
+#endif\r
+ } BIT;\r
+ } FSTATR1;\r
+ unsigned short FWBL;\r
+ unsigned short FWBH;\r
+ char wk5[34];\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short FEKEY:8;\r
+// unsigned short FENTRYD:1;\r
+// unsigned short :6;\r
+// unsigned short FENTRY0:1;\r
+// } BIT;\r
+ } FENTRYR;\r
+};\r
+\r
+struct st_icu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IR : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char IR : 1;\r
+#endif\r
+ } BIT;\r
+ } IR[250];\r
+ char wk0[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char DTCE : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char DTCE : 1;\r
+#endif\r
+ } BIT;\r
+ } DTCER[249];\r
+ char wk1[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IEN0 : 1;\r
+ unsigned char IEN1 : 1;\r
+ unsigned char IEN2 : 1;\r
+ unsigned char IEN3 : 1;\r
+ unsigned char IEN4 : 1;\r
+ unsigned char IEN5 : 1;\r
+ unsigned char IEN6 : 1;\r
+ unsigned char IEN7 : 1;\r
+#else\r
+ unsigned char IEN7 : 1;\r
+ unsigned char IEN6 : 1;\r
+ unsigned char IEN5 : 1;\r
+ unsigned char IEN4 : 1;\r
+ unsigned char IEN3 : 1;\r
+ unsigned char IEN2 : 1;\r
+ unsigned char IEN1 : 1;\r
+ unsigned char IEN0 : 1;\r
+#endif\r
+ } BIT;\r
+ } IER[32];\r
+ char wk2[192];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SWINT : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char SWINT : 1;\r
+#endif\r
+ } BIT;\r
+ } SWINTR;\r
+ char wk3[15];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short FVCT : 8;\r
+ unsigned short : 7;\r
+ unsigned short FIEN : 1;\r
+#else\r
+ unsigned short FIEN : 1;\r
+ unsigned short : 7;\r
+ unsigned short FVCT : 8;\r
+#endif\r
+ } BIT;\r
+ } FIR;\r
+ char wk4[14];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IPR : 4;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char IPR : 4;\r
+#endif\r
+ } BIT;\r
+ } IPR[250];\r
+ char wk5[262];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 2;\r
+ unsigned char IRQMD : 2;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char IRQMD : 2;\r
+ unsigned char : 2;\r
+#endif\r
+ } BIT;\r
+ } IRQCR[8];\r
+ char wk6[8];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char FLTEN0 : 1;\r
+ unsigned char FLTEN1 : 1;\r
+ unsigned char FLTEN2 : 1;\r
+ unsigned char FLTEN3 : 1;\r
+ unsigned char FLTEN4 : 1;\r
+ unsigned char FLTEN5 : 1;\r
+ unsigned char FLTEN6 : 1;\r
+ unsigned char FLTEN7 : 1;\r
+#else\r
+ unsigned char FLTEN7 : 1;\r
+ unsigned char FLTEN6 : 1;\r
+ unsigned char FLTEN5 : 1;\r
+ unsigned char FLTEN4 : 1;\r
+ unsigned char FLTEN3 : 1;\r
+ unsigned char FLTEN2 : 1;\r
+ unsigned char FLTEN1 : 1;\r
+ unsigned char FLTEN0 : 1;\r
+#endif\r
+ } BIT;\r
+ } IRQFLTE0;\r
+ char wk7[3];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short FCLKSEL0 : 2;\r
+ unsigned short FCLKSEL1 : 2;\r
+ unsigned short FCLKSEL2 : 2;\r
+ unsigned short FCLKSEL3 : 2;\r
+ unsigned short FCLKSEL4 : 2;\r
+ unsigned short FCLKSEL5 : 2;\r
+ unsigned short FCLKSEL6 : 2;\r
+ unsigned short FCLKSEL7 : 2;\r
+#else\r
+ unsigned short FCLKSEL7 : 2;\r
+ unsigned short FCLKSEL6 : 2;\r
+ unsigned short FCLKSEL5 : 2;\r
+ unsigned short FCLKSEL4 : 2;\r
+ unsigned short FCLKSEL3 : 2;\r
+ unsigned short FCLKSEL2 : 2;\r
+ unsigned short FCLKSEL1 : 2;\r
+ unsigned short FCLKSEL0 : 2;\r
+#endif\r
+ } BIT;\r
+ } IRQFLTC0;\r
+ char wk8[106];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NMIST : 1;\r
+ unsigned char OSTST : 1;\r
+ unsigned char : 1;\r
+ unsigned char IWDTST : 1;\r
+ unsigned char LVD1ST : 1;\r
+ unsigned char LVD2ST : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char LVD2ST : 1;\r
+ unsigned char LVD1ST : 1;\r
+ unsigned char IWDTST : 1;\r
+ unsigned char : 1;\r
+ unsigned char OSTST : 1;\r
+ unsigned char NMIST : 1;\r
+#endif\r
+ } BIT;\r
+ } NMISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NMIEN : 1;\r
+ unsigned char OSTEN : 1;\r
+ unsigned char : 1;\r
+ unsigned char IWDTEN : 1;\r
+ unsigned char LVD1EN : 1;\r
+ unsigned char LVD2EN : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char LVD2EN : 1;\r
+ unsigned char LVD1EN : 1;\r
+ unsigned char IWDTEN : 1;\r
+ unsigned char : 1;\r
+ unsigned char OSTEN : 1;\r
+ unsigned char NMIEN : 1;\r
+#endif\r
+ } BIT;\r
+ } NMIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NMICLR : 1;\r
+ unsigned char OSTCLR : 1;\r
+ unsigned char : 1;\r
+ unsigned char IWDTCLR : 1;\r
+ unsigned char LVD1CLR : 1;\r
+ unsigned char LVD2CLR : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char LVD2CLR : 1;\r
+ unsigned char LVD1CLR : 1;\r
+ unsigned char IWDTCLR : 1;\r
+ unsigned char : 1;\r
+ unsigned char OSTCLR : 1;\r
+ unsigned char NMICLR : 1;\r
+#endif\r
+ } BIT;\r
+ } NMICLR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 3;\r
+ unsigned char NMIMD : 1;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char NMIMD : 1;\r
+ unsigned char : 3;\r
+#endif\r
+ } BIT;\r
+ } NMICR;\r
+ char wk9[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NFLTEN : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char NFLTEN : 1;\r
+#endif\r
+ } BIT;\r
+ } NMIFLTE;\r
+ char wk10[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NFCLKSEL : 2;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char NFCLKSEL : 2;\r
+#endif\r
+ } BIT;\r
+ } NMIFLTC;\r
+};\r
+\r
+struct st_irda {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 2;\r
+ unsigned char IRRXINV : 1;\r
+ unsigned char IRTXINV : 1;\r
+ unsigned char IRCKS : 3;\r
+ unsigned char IRE : 1;\r
+#else\r
+ unsigned char IRE : 1;\r
+ unsigned char IRCKS : 3;\r
+ unsigned char IRTXINV : 1;\r
+ unsigned char IRRXINV : 1;\r
+ unsigned char : 2;\r
+#endif\r
+ } BIT;\r
+ } IRCR;\r
+};\r
+\r
+struct st_iwdt {\r
+ unsigned char IWDTRR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short TOPS : 2;\r
+ unsigned short : 2;\r
+ unsigned short CKS : 4;\r
+ unsigned short RPES : 2;\r
+ unsigned short : 2;\r
+ unsigned short RPSS : 2;\r
+ unsigned short : 2;\r
+#else\r
+ unsigned short : 2;\r
+ unsigned short RPSS : 2;\r
+ unsigned short : 2;\r
+ unsigned short RPES : 2;\r
+ unsigned short CKS : 4;\r
+ unsigned short : 2;\r
+ unsigned short TOPS : 2;\r
+#endif\r
+ } BIT;\r
+ } IWDTCR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CNTVAL : 14;\r
+ unsigned short UNDFF : 1;\r
+ unsigned short REFEF : 1;\r
+#else\r
+ unsigned short REFEF : 1;\r
+ unsigned short UNDFF : 1;\r
+ unsigned short CNTVAL : 14;\r
+#endif\r
+ } BIT;\r
+ } IWDTSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char RSTIRQS : 1;\r
+#else\r
+ unsigned char RSTIRQS : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } IWDTRCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char SLCSTP : 1;\r
+#else\r
+ unsigned char SLCSTP : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } IWDTCSTPR;\r
+};\r
+\r
+struct st_lcdc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LBAS : 2;\r
+ unsigned char LDTY : 3;\r
+ unsigned char LWAVE : 1;\r
+ unsigned char MDSET : 2;\r
+#else\r
+ unsigned char MDSET : 2;\r
+ unsigned char LWAVE : 1;\r
+ unsigned char LDTY : 3;\r
+ unsigned char LBAS : 2;\r
+#endif\r
+ } BIT;\r
+ } LCDM0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LCDVLM : 1;\r
+ unsigned char : 2;\r
+ unsigned char LCDSEL : 1;\r
+ unsigned char BLON : 1;\r
+ unsigned char VLCON : 1;\r
+ unsigned char SCOC : 1;\r
+ unsigned char LCDON : 1;\r
+#else\r
+ unsigned char LCDON : 1;\r
+ unsigned char SCOC : 1;\r
+ unsigned char VLCON : 1;\r
+ unsigned char BLON : 1;\r
+ unsigned char LCDSEL : 1;\r
+ unsigned char : 2;\r
+ unsigned char LCDVLM : 1;\r
+#endif\r
+ } BIT;\r
+ } LCDM1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LCDC0 : 6;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char LCDC0 : 6;\r
+#endif\r
+ } BIT;\r
+ } LCDC0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char VLCD : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char VLCD : 5;\r
+#endif\r
+ } BIT;\r
+ } VLCD;\r
+ char wk0[60];\r
+ unsigned char SEG00;\r
+ unsigned char SEG01;\r
+ unsigned char SEG02;\r
+ unsigned char SEG03;\r
+ unsigned char SEG04;\r
+ unsigned char SEG05;\r
+ unsigned char SEG06;\r
+ unsigned char SEG07;\r
+ unsigned char SEG08;\r
+ unsigned char SEG09;\r
+ unsigned char SEG10;\r
+ unsigned char SEG11;\r
+ unsigned char SEG12;\r
+ unsigned char SEG13;\r
+ unsigned char SEG14;\r
+ unsigned char SEG15;\r
+ unsigned char SEG16;\r
+ unsigned char SEG17;\r
+ unsigned char SEG18;\r
+ unsigned char SEG19;\r
+ unsigned char SEG20;\r
+ unsigned char SEG21;\r
+ unsigned char SEG22;\r
+ unsigned char SEG23;\r
+ unsigned char SEG24;\r
+ unsigned char SEG25;\r
+ unsigned char SEG26;\r
+ unsigned char SEG27;\r
+ unsigned char SEG28;\r
+ unsigned char SEG29;\r
+ unsigned char SEG30;\r
+ unsigned char SEG31;\r
+ unsigned char SEG32;\r
+ unsigned char SEG33;\r
+ unsigned char SEG34;\r
+ unsigned char SEG35;\r
+ unsigned char SEG36;\r
+ unsigned char SEG37;\r
+ unsigned char SEG38;\r
+ unsigned char SEG39;\r
+};\r
+\r
+struct st_lpt {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LPCNTPSSEL : 3;\r
+ unsigned char : 1;\r
+ unsigned char LPCNTCKSEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char LPCMRE0 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char LPCMRE0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char LPCNTCKSEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char LPCNTPSSEL : 3;\r
+#endif\r
+ } BIT;\r
+ } LPTCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LPCNTSTP : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char LPCNTSTP : 1;\r
+#endif\r
+ } BIT;\r
+ } LPTCR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LPCNTEN : 1;\r
+ unsigned char LPCNTRST : 1;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char LPCNTRST : 1;\r
+ unsigned char LPCNTEN : 1;\r
+#endif\r
+ } BIT;\r
+ } LPTCR3;\r
+ char wk0[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short LPCNTPRD : 16;\r
+#else\r
+ unsigned short LPCNTPRD : 16;\r
+#endif\r
+ } BIT;\r
+ } LPTPRD;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short LPCMR0 : 16;\r
+#else\r
+ unsigned short LPCMR0 : 16;\r
+#endif\r
+ } BIT;\r
+ } LPCMR0;\r
+ char wk2[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 15;\r
+ unsigned short LPWKUPEN : 1;\r
+#else\r
+ unsigned short LPWKUPEN : 1;\r
+ unsigned short : 15;\r
+#endif\r
+ } BIT;\r
+ } LPWUCR;\r
+};\r
+\r
+struct st_mpc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 6;\r
+ unsigned char PFSWE : 1;\r
+ unsigned char B0WI : 1;\r
+#else\r
+ unsigned char B0WI : 1;\r
+ unsigned char PFSWE : 1;\r
+ unsigned char : 6;\r
+#endif\r
+ } BIT;\r
+ } PWPR;\r
+ char wk0[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P02PFS;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P04PFS;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P07PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P10PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P11PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P12PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P13PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P14PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P15PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P16PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P17PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P20PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P21PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P22PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P23PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P24PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P25PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P26PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P27PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P30PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P31PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P32PFS;\r
+ char wk3[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 6;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 6;\r
+#endif\r
+ } BIT;\r
+ } P35PFS;\r
+ char wk4[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } P40PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } P41PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } P42PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } P43PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } P44PFS;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } P46PFS;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P50PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P51PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P52PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P53PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P54PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P55PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } P56PFS;\r
+ char wk7[25];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } P90PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } P91PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } P92PFS;\r
+ char wk8[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PA0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PA1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PA2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PA3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PA4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PA5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PA6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PA7PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PB0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PB1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PB2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PB3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PB4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PB5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PB6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PB7PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PC0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PC1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PC2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PC3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PC4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PC5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PC6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PC7PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PD0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PD1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PD2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PD3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PD4PFS;\r
+ char wk9[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PE0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PE1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PE2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PE3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PE4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PE5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PE6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char ISEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PE7PFS;\r
+ char wk10[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PF6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PF7PFS;\r
+ char wk11[16];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } PJ0PFS;\r
+ char wk12[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } PJ2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PSEL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char PSEL : 5;\r
+#endif\r
+ } BIT;\r
+ } PJ3PFS;\r
+ char wk13[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } PJ6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ASEL : 1;\r
+#else\r
+ unsigned char ASEL : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } PJ7PFS;\r
+};\r
+\r
+struct st_mtu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char OE3B : 1;\r
+ unsigned char OE4A : 1;\r
+ unsigned char OE4B : 1;\r
+ unsigned char OE3D : 1;\r
+ unsigned char OE4C : 1;\r
+ unsigned char OE4D : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char OE4D : 1;\r
+ unsigned char OE4C : 1;\r
+ unsigned char OE3D : 1;\r
+ unsigned char OE4B : 1;\r
+ unsigned char OE4A : 1;\r
+ unsigned char OE3B : 1;\r
+#endif\r
+ } BIT;\r
+ } TOER;\r
+ char wk0[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char UF : 1;\r
+ unsigned char VF : 1;\r
+ unsigned char WF : 1;\r
+ unsigned char FB : 1;\r
+ unsigned char P : 1;\r
+ unsigned char N : 1;\r
+ unsigned char BDC : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char BDC : 1;\r
+ unsigned char N : 1;\r
+ unsigned char P : 1;\r
+ unsigned char FB : 1;\r
+ unsigned char WF : 1;\r
+ unsigned char VF : 1;\r
+ unsigned char UF : 1;\r
+#endif\r
+ } BIT;\r
+ } TGCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char OLSP : 1;\r
+ unsigned char OLSN : 1;\r
+ unsigned char TOCS : 1;\r
+ unsigned char TOCL : 1;\r
+ unsigned char : 2;\r
+ unsigned char PSYE : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char PSYE : 1;\r
+ unsigned char : 2;\r
+ unsigned char TOCL : 1;\r
+ unsigned char TOCS : 1;\r
+ unsigned char OLSN : 1;\r
+ unsigned char OLSP : 1;\r
+#endif\r
+ } BIT;\r
+ } TOCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char OLS1P : 1;\r
+ unsigned char OLS1N : 1;\r
+ unsigned char OLS2P : 1;\r
+ unsigned char OLS2N : 1;\r
+ unsigned char OLS3P : 1;\r
+ unsigned char OLS3N : 1;\r
+ unsigned char BF : 2;\r
+#else\r
+ unsigned char BF : 2;\r
+ unsigned char OLS3N : 1;\r
+ unsigned char OLS3P : 1;\r
+ unsigned char OLS2N : 1;\r
+ unsigned char OLS2P : 1;\r
+ unsigned char OLS1N : 1;\r
+ unsigned char OLS1P : 1;\r
+#endif\r
+ } BIT;\r
+ } TOCR2;\r
+ char wk1[4];\r
+ unsigned short TCDR;\r
+ unsigned short TDDR;\r
+ char wk2[8];\r
+ unsigned short TCNTS;\r
+ unsigned short TCBR;\r
+ char wk3[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char T4VCOR : 3;\r
+ unsigned char T4VEN : 1;\r
+ unsigned char T3ACOR : 3;\r
+ unsigned char T3AEN : 1;\r
+#else\r
+ unsigned char T3AEN : 1;\r
+ unsigned char T3ACOR : 3;\r
+ unsigned char T4VEN : 1;\r
+ unsigned char T4VCOR : 3;\r
+#endif\r
+ } BIT;\r
+ } TITCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char T4VCNT : 3;\r
+ unsigned char : 1;\r
+ unsigned char T3ACNT : 3;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char T3ACNT : 3;\r
+ unsigned char : 1;\r
+ unsigned char T4VCNT : 3;\r
+#endif\r
+ } BIT;\r
+ } TITCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BTE : 2;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char BTE : 2;\r
+#endif\r
+ } BIT;\r
+ } TBTER;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TDER : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char TDER : 1;\r
+#endif\r
+ } BIT;\r
+ } TDER;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char OLS1P : 1;\r
+ unsigned char OLS1N : 1;\r
+ unsigned char OLS2P : 1;\r
+ unsigned char OLS2N : 1;\r
+ unsigned char OLS3P : 1;\r
+ unsigned char OLS3N : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char OLS3N : 1;\r
+ unsigned char OLS3P : 1;\r
+ unsigned char OLS2N : 1;\r
+ unsigned char OLS2P : 1;\r
+ unsigned char OLS1N : 1;\r
+ unsigned char OLS1P : 1;\r
+#endif\r
+ } BIT;\r
+ } TOLBR;\r
+ char wk6[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char WRE : 1;\r
+ unsigned char : 6;\r
+ unsigned char CCE : 1;\r
+#else\r
+ unsigned char CCE : 1;\r
+ unsigned char : 6;\r
+ unsigned char WRE : 1;\r
+#endif\r
+ } BIT;\r
+ } TWCR;\r
+ char wk7[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CST0 : 1;\r
+ unsigned char CST1 : 1;\r
+ unsigned char CST2 : 1;\r
+ unsigned char : 3;\r
+ unsigned char CST3 : 1;\r
+ unsigned char CST4 : 1;\r
+#else\r
+ unsigned char CST4 : 1;\r
+ unsigned char CST3 : 1;\r
+ unsigned char : 3;\r
+ unsigned char CST2 : 1;\r
+ unsigned char CST1 : 1;\r
+ unsigned char CST0 : 1;\r
+#endif\r
+ } BIT;\r
+ } TSTR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SYNC0 : 1;\r
+ unsigned char SYNC1 : 1;\r
+ unsigned char SYNC2 : 1;\r
+ unsigned char : 3;\r
+ unsigned char SYNC3 : 1;\r
+ unsigned char SYNC4 : 1;\r
+#else\r
+ unsigned char SYNC4 : 1;\r
+ unsigned char SYNC3 : 1;\r
+ unsigned char : 3;\r
+ unsigned char SYNC2 : 1;\r
+ unsigned char SYNC1 : 1;\r
+ unsigned char SYNC0 : 1;\r
+#endif\r
+ } BIT;\r
+ } TSYR;\r
+ char wk8[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char RWE : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char RWE : 1;\r
+#endif\r
+ } BIT;\r
+ } TRWER;\r
+};\r
+\r
+struct st_mtu0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NFAEN : 1;\r
+ unsigned char NFBEN : 1;\r
+ unsigned char NFCEN : 1;\r
+ unsigned char NFDEN : 1;\r
+ unsigned char NFCS : 2;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char NFCS : 2;\r
+ unsigned char NFDEN : 1;\r
+ unsigned char NFCEN : 1;\r
+ unsigned char NFBEN : 1;\r
+ unsigned char NFAEN : 1;\r
+#endif\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[111];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TPSC : 3;\r
+ unsigned char CKEG : 2;\r
+ unsigned char CCLR : 3;\r
+#else\r
+ unsigned char CCLR : 3;\r
+ unsigned char CKEG : 2;\r
+ unsigned char TPSC : 3;\r
+#endif\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MD : 4;\r
+ unsigned char BFA : 1;\r
+ unsigned char BFB : 1;\r
+ unsigned char BFE : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char BFE : 1;\r
+ unsigned char BFB : 1;\r
+ unsigned char BFA : 1;\r
+ unsigned char MD : 4;\r
+#endif\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IOA : 4;\r
+ unsigned char IOB : 4;\r
+#else\r
+ unsigned char IOB : 4;\r
+ unsigned char IOA : 4;\r
+#endif\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IOC : 4;\r
+ unsigned char IOD : 4;\r
+#else\r
+ unsigned char IOD : 4;\r
+ unsigned char IOC : 4;\r
+#endif\r
+ } BIT;\r
+ } TIORL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TGIEA : 1;\r
+ unsigned char TGIEB : 1;\r
+ unsigned char TGIEC : 1;\r
+ unsigned char TGIED : 1;\r
+ unsigned char TCIEV : 1;\r
+ unsigned char : 2;\r
+ unsigned char TTGE : 1;\r
+#else\r
+ unsigned char TTGE : 1;\r
+ unsigned char : 2;\r
+ unsigned char TCIEV : 1;\r
+ unsigned char TGIED : 1;\r
+ unsigned char TGIEC : 1;\r
+ unsigned char TGIEB : 1;\r
+ unsigned char TGIEA : 1;\r
+#endif\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char TCFD : 1;\r
+#else\r
+ unsigned char TCFD : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk1[16];\r
+ unsigned short TGRE;\r
+ unsigned short TGRF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TGIEE : 1;\r
+ unsigned char TGIEF : 1;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char TGIEF : 1;\r
+ unsigned char TGIEE : 1;\r
+#endif\r
+ } BIT;\r
+ } TIER2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TTSA : 1;\r
+ unsigned char TTSB : 1;\r
+ unsigned char TTSE : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char TTSE : 1;\r
+ unsigned char TTSB : 1;\r
+ unsigned char TTSA : 1;\r
+#endif\r
+ } BIT;\r
+ } TBTM;\r
+};\r
+\r
+struct st_mtu1 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NFAEN : 1;\r
+ unsigned char NFBEN : 1;\r
+ unsigned char NFCEN : 1;\r
+ unsigned char NFDEN : 1;\r
+ unsigned char NFCS : 2;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char NFCS : 2;\r
+ unsigned char NFDEN : 1;\r
+ unsigned char NFCEN : 1;\r
+ unsigned char NFBEN : 1;\r
+ unsigned char NFAEN : 1;\r
+#endif\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[238];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TPSC : 3;\r
+ unsigned char CKEG : 2;\r
+ unsigned char CCLR : 2;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char CCLR : 2;\r
+ unsigned char CKEG : 2;\r
+ unsigned char TPSC : 3;\r
+#endif\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MD : 4;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char MD : 4;\r
+#endif\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IOA : 4;\r
+ unsigned char IOB : 4;\r
+#else\r
+ unsigned char IOB : 4;\r
+ unsigned char IOA : 4;\r
+#endif\r
+ } BIT;\r
+ } TIOR;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TGIEA : 1;\r
+ unsigned char TGIEB : 1;\r
+ unsigned char : 2;\r
+ unsigned char TCIEV : 1;\r
+ unsigned char TCIEU : 1;\r
+ unsigned char : 1;\r
+ unsigned char TTGE : 1;\r
+#else\r
+ unsigned char TTGE : 1;\r
+ unsigned char : 1;\r
+ unsigned char TCIEU : 1;\r
+ unsigned char TCIEV : 1;\r
+ unsigned char : 2;\r
+ unsigned char TGIEB : 1;\r
+ unsigned char TGIEA : 1;\r
+#endif\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char TCFD : 1;\r
+#else\r
+ unsigned char TCFD : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk3[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char I1AE : 1;\r
+ unsigned char I1BE : 1;\r
+ unsigned char I2AE : 1;\r
+ unsigned char I2BE : 1;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char I2BE : 1;\r
+ unsigned char I2AE : 1;\r
+ unsigned char I1BE : 1;\r
+ unsigned char I1AE : 1;\r
+#endif\r
+ } BIT;\r
+ } TICCR;\r
+};\r
+\r
+struct st_mtu2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NFAEN : 1;\r
+ unsigned char NFBEN : 1;\r
+ unsigned char NFCEN : 1;\r
+ unsigned char NFDEN : 1;\r
+ unsigned char NFCS : 2;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char NFCS : 2;\r
+ unsigned char NFDEN : 1;\r
+ unsigned char NFCEN : 1;\r
+ unsigned char NFBEN : 1;\r
+ unsigned char NFAEN : 1;\r
+#endif\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[365];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TPSC : 3;\r
+ unsigned char CKEG : 2;\r
+ unsigned char CCLR : 2;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char CCLR : 2;\r
+ unsigned char CKEG : 2;\r
+ unsigned char TPSC : 3;\r
+#endif\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MD : 4;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char MD : 4;\r
+#endif\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IOA : 4;\r
+ unsigned char IOB : 4;\r
+#else\r
+ unsigned char IOB : 4;\r
+ unsigned char IOA : 4;\r
+#endif\r
+ } BIT;\r
+ } TIOR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TGIEA : 1;\r
+ unsigned char TGIEB : 1;\r
+ unsigned char : 2;\r
+ unsigned char TCIEV : 1;\r
+ unsigned char TCIEU : 1;\r
+ unsigned char : 1;\r
+ unsigned char TTGE : 1;\r
+#else\r
+ unsigned char TTGE : 1;\r
+ unsigned char : 1;\r
+ unsigned char TCIEU : 1;\r
+ unsigned char TCIEV : 1;\r
+ unsigned char : 2;\r
+ unsigned char TGIEB : 1;\r
+ unsigned char TGIEA : 1;\r
+#endif\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char TCFD : 1;\r
+#else\r
+ unsigned char TCFD : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_mtu3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TPSC : 3;\r
+ unsigned char CKEG : 2;\r
+ unsigned char CCLR : 3;\r
+#else\r
+ unsigned char CCLR : 3;\r
+ unsigned char CKEG : 2;\r
+ unsigned char TPSC : 3;\r
+#endif\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MD : 4;\r
+ unsigned char BFA : 1;\r
+ unsigned char BFB : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char BFB : 1;\r
+ unsigned char BFA : 1;\r
+ unsigned char MD : 4;\r
+#endif\r
+ } BIT;\r
+ } TMDR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IOA : 4;\r
+ unsigned char IOB : 4;\r
+#else\r
+ unsigned char IOB : 4;\r
+ unsigned char IOA : 4;\r
+#endif\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IOC : 4;\r
+ unsigned char IOD : 4;\r
+#else\r
+ unsigned char IOD : 4;\r
+ unsigned char IOC : 4;\r
+#endif\r
+ } BIT;\r
+ } TIORL;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TGIEA : 1;\r
+ unsigned char TGIEB : 1;\r
+ unsigned char TGIEC : 1;\r
+ unsigned char TGIED : 1;\r
+ unsigned char TCIEV : 1;\r
+ unsigned char : 2;\r
+ unsigned char TTGE : 1;\r
+#else\r
+ unsigned char TTGE : 1;\r
+ unsigned char : 2;\r
+ unsigned char TCIEV : 1;\r
+ unsigned char TGIED : 1;\r
+ unsigned char TGIEC : 1;\r
+ unsigned char TGIEB : 1;\r
+ unsigned char TGIEA : 1;\r
+#endif\r
+ } BIT;\r
+ } TIER;\r
+ char wk3[7];\r
+ unsigned short TCNT;\r
+ char wk4[6];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk5[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk6[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char TCFD : 1;\r
+#else\r
+ unsigned char TCFD : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } TSR;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TTSA : 1;\r
+ unsigned char TTSB : 1;\r
+ unsigned char TTSE : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char TTSE : 1;\r
+ unsigned char TTSB : 1;\r
+ unsigned char TTSA : 1;\r
+#endif\r
+ } BIT;\r
+ } TBTM;\r
+ char wk8[90];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NFAEN : 1;\r
+ unsigned char NFBEN : 1;\r
+ unsigned char NFCEN : 1;\r
+ unsigned char NFDEN : 1;\r
+ unsigned char NFCS : 2;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char NFCS : 2;\r
+ unsigned char NFDEN : 1;\r
+ unsigned char NFCEN : 1;\r
+ unsigned char NFBEN : 1;\r
+ unsigned char NFAEN : 1;\r
+#endif\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu4 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TPSC : 3;\r
+ unsigned char CKEG : 2;\r
+ unsigned char CCLR : 3;\r
+#else\r
+ unsigned char CCLR : 3;\r
+ unsigned char CKEG : 2;\r
+ unsigned char TPSC : 3;\r
+#endif\r
+ } BIT;\r
+ } TCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MD : 4;\r
+ unsigned char BFA : 1;\r
+ unsigned char BFB : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char BFB : 1;\r
+ unsigned char BFA : 1;\r
+ unsigned char MD : 4;\r
+#endif\r
+ } BIT;\r
+ } TMDR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IOA : 4;\r
+ unsigned char IOB : 4;\r
+#else\r
+ unsigned char IOB : 4;\r
+ unsigned char IOA : 4;\r
+#endif\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IOC : 4;\r
+ unsigned char IOD : 4;\r
+#else\r
+ unsigned char IOD : 4;\r
+ unsigned char IOC : 4;\r
+#endif\r
+ } BIT;\r
+ } TIORL;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TGIEA : 1;\r
+ unsigned char TGIEB : 1;\r
+ unsigned char TGIEC : 1;\r
+ unsigned char TGIED : 1;\r
+ unsigned char TCIEV : 1;\r
+ unsigned char : 1;\r
+ unsigned char TTGE2 : 1;\r
+ unsigned char TTGE : 1;\r
+#else\r
+ unsigned char TTGE : 1;\r
+ unsigned char TTGE2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char TCIEV : 1;\r
+ unsigned char TGIED : 1;\r
+ unsigned char TGIEC : 1;\r
+ unsigned char TGIEB : 1;\r
+ unsigned char TGIEA : 1;\r
+#endif\r
+ } BIT;\r
+ } TIER;\r
+ char wk4[8];\r
+ unsigned short TCNT;\r
+ char wk5[8];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk6[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char TCFD : 1;\r
+#else\r
+ unsigned char TCFD : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } TSR;\r
+ char wk8[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TTSA : 1;\r
+ unsigned char TTSB : 1;\r
+ unsigned char TTSE : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char TTSE : 1;\r
+ unsigned char TTSB : 1;\r
+ unsigned char TTSA : 1;\r
+#endif\r
+ } BIT;\r
+ } TBTM;\r
+ char wk9[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short ITB4VE : 1;\r
+ unsigned short ITB3AE : 1;\r
+ unsigned short ITA4VE : 1;\r
+ unsigned short ITA3AE : 1;\r
+ unsigned short DT4BE : 1;\r
+ unsigned short UT4BE : 1;\r
+ unsigned short DT4AE : 1;\r
+ unsigned short UT4AE : 1;\r
+ unsigned short : 6;\r
+ unsigned short BF : 2;\r
+#else\r
+ unsigned short BF : 2;\r
+ unsigned short : 6;\r
+ unsigned short UT4AE : 1;\r
+ unsigned short DT4AE : 1;\r
+ unsigned short UT4BE : 1;\r
+ unsigned short DT4BE : 1;\r
+ unsigned short ITA3AE : 1;\r
+ unsigned short ITA4VE : 1;\r
+ unsigned short ITB3AE : 1;\r
+ unsigned short ITB4VE : 1;\r
+#endif\r
+ } BIT;\r
+ } TADCR;\r
+ char wk10[2];\r
+ unsigned short TADCORA;\r
+ unsigned short TADCORB;\r
+ unsigned short TADCOBRA;\r
+ unsigned short TADCOBRB;\r
+ char wk11[72];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NFAEN : 1;\r
+ unsigned char NFBEN : 1;\r
+ unsigned char NFCEN : 1;\r
+ unsigned char NFDEN : 1;\r
+ unsigned char NFCS : 2;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char NFCS : 2;\r
+ unsigned char NFDEN : 1;\r
+ unsigned char NFCEN : 1;\r
+ unsigned char NFBEN : 1;\r
+ unsigned char NFAEN : 1;\r
+#endif\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu5 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NFUEN : 1;\r
+ unsigned char NFVEN : 1;\r
+ unsigned char NFWEN : 1;\r
+ unsigned char : 1;\r
+ unsigned char NFCS : 2;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char NFCS : 2;\r
+ unsigned char : 1;\r
+ unsigned char NFWEN : 1;\r
+ unsigned char NFVEN : 1;\r
+ unsigned char NFUEN : 1;\r
+#endif\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[490];\r
+ unsigned short TCNTU;\r
+ unsigned short TGRU;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TPSC : 2;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char TPSC : 2;\r
+#endif\r
+ } BIT;\r
+ } TCRU;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IOC : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char IOC : 5;\r
+#endif\r
+ } BIT;\r
+ } TIORU;\r
+ char wk3[9];\r
+ unsigned short TCNTV;\r
+ unsigned short TGRV;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TPSC : 2;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char TPSC : 2;\r
+#endif\r
+ } BIT;\r
+ } TCRV;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IOC : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char IOC : 5;\r
+#endif\r
+ } BIT;\r
+ } TIORV;\r
+ char wk5[9];\r
+ unsigned short TCNTW;\r
+ unsigned short TGRW;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TPSC : 2;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char TPSC : 2;\r
+#endif\r
+ } BIT;\r
+ } TCRW;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IOC : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char IOC : 5;\r
+#endif\r
+ } BIT;\r
+ } TIORW;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TGIE5W : 1;\r
+ unsigned char TGIE5V : 1;\r
+ unsigned char TGIE5U : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char TGIE5U : 1;\r
+ unsigned char TGIE5V : 1;\r
+ unsigned char TGIE5W : 1;\r
+#endif\r
+ } BIT;\r
+ } TIER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CSTW5 : 1;\r
+ unsigned char CSTV5 : 1;\r
+ unsigned char CSTU5 : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char CSTU5 : 1;\r
+ unsigned char CSTV5 : 1;\r
+ unsigned char CSTW5 : 1;\r
+#endif\r
+ } BIT;\r
+ } TSTR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CMPCLR5W : 1;\r
+ unsigned char CMPCLR5V : 1;\r
+ unsigned char CMPCLR5U : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char CMPCLR5U : 1;\r
+ unsigned char CMPCLR5V : 1;\r
+ unsigned char CMPCLR5W : 1;\r
+#endif\r
+ } BIT;\r
+ } TCNTCMPCLR;\r
+};\r
+\r
+struct st_poe {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short POE0M : 2;\r
+ unsigned short POE1M : 2;\r
+ unsigned short POE2M : 2;\r
+ unsigned short POE3M : 2;\r
+ unsigned short PIE1 : 1;\r
+ unsigned short : 3;\r
+ unsigned short POE0F : 1;\r
+ unsigned short POE1F : 1;\r
+ unsigned short POE2F : 1;\r
+ unsigned short POE3F : 1;\r
+#else\r
+ unsigned short POE3F : 1;\r
+ unsigned short POE2F : 1;\r
+ unsigned short POE1F : 1;\r
+ unsigned short POE0F : 1;\r
+ unsigned short : 3;\r
+ unsigned short PIE1 : 1;\r
+ unsigned short POE3M : 2;\r
+ unsigned short POE2M : 2;\r
+ unsigned short POE1M : 2;\r
+ unsigned short POE0M : 2;\r
+#endif\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 8;\r
+ unsigned short OIE1 : 1;\r
+ unsigned short OCE1 : 1;\r
+ unsigned short : 5;\r
+ unsigned short OSF1 : 1;\r
+#else\r
+ unsigned short OSF1 : 1;\r
+ unsigned short : 5;\r
+ unsigned short OCE1 : 1;\r
+ unsigned short OIE1 : 1;\r
+ unsigned short : 8;\r
+#endif\r
+ } BIT;\r
+ } OCSR1;\r
+ char wk0[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short POE8M : 2;\r
+ unsigned short : 6;\r
+ unsigned short PIE2 : 1;\r
+ unsigned short POE8E : 1;\r
+ unsigned short : 2;\r
+ unsigned short POE8F : 1;\r
+ unsigned short : 3;\r
+#else\r
+ unsigned short : 3;\r
+ unsigned short POE8F : 1;\r
+ unsigned short : 2;\r
+ unsigned short POE8E : 1;\r
+ unsigned short PIE2 : 1;\r
+ unsigned short : 6;\r
+ unsigned short POE8M : 2;\r
+#endif\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CH34HIZ : 1;\r
+ unsigned char CH0HIZ : 1;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char CH0HIZ : 1;\r
+ unsigned char CH34HIZ : 1;\r
+#endif\r
+ } BIT;\r
+ } SPOER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PE0ZE : 1;\r
+ unsigned char PE1ZE : 1;\r
+ unsigned char PE2ZE : 1;\r
+ unsigned char PE3ZE : 1;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char PE3ZE : 1;\r
+ unsigned char PE2ZE : 1;\r
+ unsigned char PE1ZE : 1;\r
+ unsigned char PE0ZE : 1;\r
+#endif\r
+ } BIT;\r
+ } POECR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 4;\r
+ unsigned char P3CZEA : 1;\r
+ unsigned char P2CZEA : 1;\r
+ unsigned char P1CZEA : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char P1CZEA : 1;\r
+ unsigned char P2CZEA : 1;\r
+ unsigned char P3CZEA : 1;\r
+ unsigned char : 4;\r
+#endif\r
+ } BIT;\r
+ } POECR2;\r
+ char wk1[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 9;\r
+ unsigned short OSTSTE : 1;\r
+ unsigned short : 2;\r
+ unsigned short OSTSTF : 1;\r
+ unsigned short : 3;\r
+#else\r
+ unsigned short : 3;\r
+ unsigned short OSTSTF : 1;\r
+ unsigned short : 2;\r
+ unsigned short OSTSTE : 1;\r
+ unsigned short : 9;\r
+#endif\r
+ } BIT;\r
+ } ICSR3;\r
+};\r
+\r
+struct st_port {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 6;\r
+ unsigned char PSEL6 : 1;\r
+ unsigned char PSEL7 : 1;\r
+#else\r
+ unsigned char PSEL7 : 1;\r
+ unsigned char PSEL6 : 1;\r
+ unsigned char : 6;\r
+#endif\r
+ } BIT;\r
+ } PSRA;\r
+};\r
+\r
+struct st_port0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 2;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 2;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 2;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 2;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 2;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 2;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 2;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 2;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 4;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 4;\r
+#endif\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 5;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 5;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[62];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 2;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 2;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[32];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[61];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[33];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B5 : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char B5 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR0;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port4 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+};\r
+\r
+struct st_port5 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[36];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 4;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 4;\r
+#endif\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[57];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port9 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+};\r
+\r
+struct st_porta {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[52];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[42];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[51];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[43];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[50];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portd {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porte {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[45];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[48];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char B5 : 1;\r
+ unsigned char B4 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B1 : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portf {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 6;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 6;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 6;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 6;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 6;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 6;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 6;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 6;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 6;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 6;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porth {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+};\r
+\r
+struct st_portj {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B6 : 1;\r
+ unsigned char B7 : 1;\r
+#else\r
+ unsigned char B7 : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 2;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[49];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 6;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char B6 : 1;\r
+ unsigned char : 6;\r
+#endif\r
+ } BIT;\r
+ } ODR0;\r
+ char wk4[45];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char B0 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char B3 : 1;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char B3 : 1;\r
+ unsigned char B2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char B0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_riic {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SDAI : 1;\r
+ unsigned char SCLI : 1;\r
+ unsigned char SDAO : 1;\r
+ unsigned char SCLO : 1;\r
+ unsigned char SOWP : 1;\r
+ unsigned char CLO : 1;\r
+ unsigned char IICRST : 1;\r
+ unsigned char ICE : 1;\r
+#else\r
+ unsigned char ICE : 1;\r
+ unsigned char IICRST : 1;\r
+ unsigned char CLO : 1;\r
+ unsigned char SOWP : 1;\r
+ unsigned char SCLO : 1;\r
+ unsigned char SDAO : 1;\r
+ unsigned char SCLI : 1;\r
+ unsigned char SDAI : 1;\r
+#endif\r
+ } BIT;\r
+ } ICCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 1;\r
+ unsigned char ST : 1;\r
+ unsigned char RS : 1;\r
+ unsigned char SP : 1;\r
+ unsigned char : 1;\r
+ unsigned char TRS : 1;\r
+ unsigned char MST : 1;\r
+ unsigned char BBSY : 1;\r
+#else\r
+ unsigned char BBSY : 1;\r
+ unsigned char MST : 1;\r
+ unsigned char TRS : 1;\r
+ unsigned char : 1;\r
+ unsigned char SP : 1;\r
+ unsigned char RS : 1;\r
+ unsigned char ST : 1;\r
+ unsigned char : 1;\r
+#endif\r
+ } BIT;\r
+ } ICCR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BC : 3;\r
+ unsigned char BCWP : 1;\r
+ unsigned char CKS : 3;\r
+ unsigned char MTWP : 1;\r
+#else\r
+ unsigned char MTWP : 1;\r
+ unsigned char CKS : 3;\r
+ unsigned char BCWP : 1;\r
+ unsigned char BC : 3;\r
+#endif\r
+ } BIT;\r
+ } ICMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TMOS : 1;\r
+ unsigned char TMOL : 1;\r
+ unsigned char TMOH : 1;\r
+ unsigned char TMWE : 1;\r
+ unsigned char SDDL : 3;\r
+ unsigned char DLCS : 1;\r
+#else\r
+ unsigned char DLCS : 1;\r
+ unsigned char SDDL : 3;\r
+ unsigned char TMWE : 1;\r
+ unsigned char TMOH : 1;\r
+ unsigned char TMOL : 1;\r
+ unsigned char TMOS : 1;\r
+#endif\r
+ } BIT;\r
+ } ICMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NF : 2;\r
+ unsigned char ACKBR : 1;\r
+ unsigned char ACKBT : 1;\r
+ unsigned char ACKWP : 1;\r
+ unsigned char RDRFS : 1;\r
+ unsigned char WAIT : 1;\r
+ unsigned char SMBS : 1;\r
+#else\r
+ unsigned char SMBS : 1;\r
+ unsigned char WAIT : 1;\r
+ unsigned char RDRFS : 1;\r
+ unsigned char ACKWP : 1;\r
+ unsigned char ACKBT : 1;\r
+ unsigned char ACKBR : 1;\r
+ unsigned char NF : 2;\r
+#endif\r
+ } BIT;\r
+ } ICMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TMOE : 1;\r
+ unsigned char MALE : 1;\r
+ unsigned char NALE : 1;\r
+ unsigned char SALE : 1;\r
+ unsigned char NACKE : 1;\r
+ unsigned char NFE : 1;\r
+ unsigned char SCLE : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char SCLE : 1;\r
+ unsigned char NFE : 1;\r
+ unsigned char NACKE : 1;\r
+ unsigned char SALE : 1;\r
+ unsigned char NALE : 1;\r
+ unsigned char MALE : 1;\r
+ unsigned char TMOE : 1;\r
+#endif\r
+ } BIT;\r
+ } ICFER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SAR0E : 1;\r
+ unsigned char SAR1E : 1;\r
+ unsigned char SAR2E : 1;\r
+ unsigned char GCAE : 1;\r
+ unsigned char : 1;\r
+ unsigned char DIDE : 1;\r
+ unsigned char : 1;\r
+ unsigned char HOAE : 1;\r
+#else\r
+ unsigned char HOAE : 1;\r
+ unsigned char : 1;\r
+ unsigned char DIDE : 1;\r
+ unsigned char : 1;\r
+ unsigned char GCAE : 1;\r
+ unsigned char SAR2E : 1;\r
+ unsigned char SAR1E : 1;\r
+ unsigned char SAR0E : 1;\r
+#endif\r
+ } BIT;\r
+ } ICSER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TMOIE : 1;\r
+ unsigned char ALIE : 1;\r
+ unsigned char STIE : 1;\r
+ unsigned char SPIE : 1;\r
+ unsigned char NAKIE : 1;\r
+ unsigned char RIE : 1;\r
+ unsigned char TEIE : 1;\r
+ unsigned char TIE : 1;\r
+#else\r
+ unsigned char TIE : 1;\r
+ unsigned char TEIE : 1;\r
+ unsigned char RIE : 1;\r
+ unsigned char NAKIE : 1;\r
+ unsigned char SPIE : 1;\r
+ unsigned char STIE : 1;\r
+ unsigned char ALIE : 1;\r
+ unsigned char TMOIE : 1;\r
+#endif\r
+ } BIT;\r
+ } ICIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char AAS0 : 1;\r
+ unsigned char AAS1 : 1;\r
+ unsigned char AAS2 : 1;\r
+ unsigned char GCA : 1;\r
+ unsigned char : 1;\r
+ unsigned char DID : 1;\r
+ unsigned char : 1;\r
+ unsigned char HOA : 1;\r
+#else\r
+ unsigned char HOA : 1;\r
+ unsigned char : 1;\r
+ unsigned char DID : 1;\r
+ unsigned char : 1;\r
+ unsigned char GCA : 1;\r
+ unsigned char AAS2 : 1;\r
+ unsigned char AAS1 : 1;\r
+ unsigned char AAS0 : 1;\r
+#endif\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TMOF : 1;\r
+ unsigned char AL : 1;\r
+ unsigned char START : 1;\r
+ unsigned char STOP : 1;\r
+ unsigned char NACKF : 1;\r
+ unsigned char RDRF : 1;\r
+ unsigned char TEND : 1;\r
+ unsigned char TDRE : 1;\r
+#else\r
+ unsigned char TDRE : 1;\r
+ unsigned char TEND : 1;\r
+ unsigned char RDRF : 1;\r
+ unsigned char NACKF : 1;\r
+ unsigned char STOP : 1;\r
+ unsigned char START : 1;\r
+ unsigned char AL : 1;\r
+ unsigned char TMOF : 1;\r
+#endif\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SVA0 : 1;\r
+ unsigned char SVA : 7;\r
+#else\r
+ unsigned char SVA : 7;\r
+ unsigned char SVA0 : 1;\r
+#endif\r
+ } BIT;\r
+ } SARL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTL;\r
+ };\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char FS : 1;\r
+ unsigned char SVA : 2;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char SVA : 2;\r
+ unsigned char FS : 1;\r
+#endif\r
+ } BIT;\r
+ } SARU0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTU;\r
+ };\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SVA0 : 1;\r
+ unsigned char SVA : 7;\r
+#else\r
+ unsigned char SVA : 7;\r
+ unsigned char SVA0 : 1;\r
+#endif\r
+ } BIT;\r
+ } SARL1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char FS : 1;\r
+ unsigned char SVA : 2;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char SVA : 2;\r
+ unsigned char FS : 1;\r
+#endif\r
+ } BIT;\r
+ } SARU1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SVA0 : 1;\r
+ unsigned char SVA : 7;\r
+#else\r
+ unsigned char SVA : 7;\r
+ unsigned char SVA0 : 1;\r
+#endif\r
+ } BIT;\r
+ } SARL2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char FS : 1;\r
+ unsigned char SVA : 2;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char SVA : 2;\r
+ unsigned char FS : 1;\r
+#endif\r
+ } BIT;\r
+ } SARU2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BRL : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char BRL : 5;\r
+#endif\r
+ } BIT;\r
+ } ICBRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BRH : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char BRH : 5;\r
+#endif\r
+ } BIT;\r
+ } ICBRH;\r
+ unsigned char ICDRT;\r
+ unsigned char ICDRR;\r
+};\r
+\r
+struct st_rspi {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SPMS : 1;\r
+ unsigned char TXMD : 1;\r
+ unsigned char MODFEN : 1;\r
+ unsigned char MSTR : 1;\r
+ unsigned char SPEIE : 1;\r
+ unsigned char SPTIE : 1;\r
+ unsigned char SPE : 1;\r
+ unsigned char SPRIE : 1;\r
+#else\r
+ unsigned char SPRIE : 1;\r
+ unsigned char SPE : 1;\r
+ unsigned char SPTIE : 1;\r
+ unsigned char SPEIE : 1;\r
+ unsigned char MSTR : 1;\r
+ unsigned char MODFEN : 1;\r
+ unsigned char TXMD : 1;\r
+ unsigned char SPMS : 1;\r
+#endif\r
+ } BIT;\r
+ } SPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SSL0P : 1;\r
+ unsigned char SSL1P : 1;\r
+ unsigned char SSL2P : 1;\r
+ unsigned char SSL3P : 1;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char SSL3P : 1;\r
+ unsigned char SSL2P : 1;\r
+ unsigned char SSL1P : 1;\r
+ unsigned char SSL0P : 1;\r
+#endif\r
+ } BIT;\r
+ } SSLP;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SPLP : 1;\r
+ unsigned char SPLP2 : 1;\r
+ unsigned char : 2;\r
+ unsigned char MOIFV : 1;\r
+ unsigned char MOIFE : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char MOIFE : 1;\r
+ unsigned char MOIFV : 1;\r
+ unsigned char : 2;\r
+ unsigned char SPLP2 : 1;\r
+ unsigned char SPLP : 1;\r
+#endif\r
+ } BIT;\r
+ } SPPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char OVRF : 1;\r
+ unsigned char IDLNF : 1;\r
+ unsigned char MODF : 1;\r
+ unsigned char PERF : 1;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char PERF : 1;\r
+ unsigned char MODF : 1;\r
+ unsigned char IDLNF : 1;\r
+ unsigned char OVRF : 1;\r
+#endif\r
+ } BIT;\r
+ } SPSR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ } WORD;\r
+ } SPDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SPSLN : 3;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char SPSLN : 3;\r
+#endif\r
+ } BIT;\r
+ } SPSCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SPCP : 3;\r
+ unsigned char : 1;\r
+ unsigned char SPECM : 3;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char SPECM : 3;\r
+ unsigned char : 1;\r
+ unsigned char SPCP : 3;\r
+#endif\r
+ } BIT;\r
+ } SPSSR;\r
+ unsigned char SPBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SPFC : 2;\r
+ unsigned char : 2;\r
+ unsigned char SPRDTD : 1;\r
+ unsigned char SPLW : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char SPLW : 1;\r
+ unsigned char SPRDTD : 1;\r
+ unsigned char : 2;\r
+ unsigned char SPFC : 2;\r
+#endif\r
+ } BIT;\r
+ } SPDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SCKDL : 3;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char SCKDL : 3;\r
+#endif\r
+ } BIT;\r
+ } SPCKD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SLNDL : 3;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char SLNDL : 3;\r
+#endif\r
+ } BIT;\r
+ } SSLND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SPNDL : 3;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char SPNDL : 3;\r
+#endif\r
+ } BIT;\r
+ } SPND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SPPE : 1;\r
+ unsigned char SPOE : 1;\r
+ unsigned char SPIIE : 1;\r
+ unsigned char PTE : 1;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char PTE : 1;\r
+ unsigned char SPIIE : 1;\r
+ unsigned char SPOE : 1;\r
+ unsigned char SPPE : 1;\r
+#endif\r
+ } BIT;\r
+ } SPCR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CPHA : 1;\r
+ unsigned short CPOL : 1;\r
+ unsigned short BRDV : 2;\r
+ unsigned short SSLA : 3;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SCKDEN : 1;\r
+#else\r
+ unsigned short SCKDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SSLA : 3;\r
+ unsigned short BRDV : 2;\r
+ unsigned short CPOL : 1;\r
+ unsigned short CPHA : 1;\r
+#endif\r
+ } BIT;\r
+ } SPCMD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CPHA : 1;\r
+ unsigned short CPOL : 1;\r
+ unsigned short BRDV : 2;\r
+ unsigned short SSLA : 3;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SCKDEN : 1;\r
+#else\r
+ unsigned short SCKDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SSLA : 3;\r
+ unsigned short BRDV : 2;\r
+ unsigned short CPOL : 1;\r
+ unsigned short CPHA : 1;\r
+#endif\r
+ } BIT;\r
+ } SPCMD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CPHA : 1;\r
+ unsigned short CPOL : 1;\r
+ unsigned short BRDV : 2;\r
+ unsigned short SSLA : 3;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SCKDEN : 1;\r
+#else\r
+ unsigned short SCKDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SSLA : 3;\r
+ unsigned short BRDV : 2;\r
+ unsigned short CPOL : 1;\r
+ unsigned short CPHA : 1;\r
+#endif\r
+ } BIT;\r
+ } SPCMD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CPHA : 1;\r
+ unsigned short CPOL : 1;\r
+ unsigned short BRDV : 2;\r
+ unsigned short SSLA : 3;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SCKDEN : 1;\r
+#else\r
+ unsigned short SCKDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SSLA : 3;\r
+ unsigned short BRDV : 2;\r
+ unsigned short CPOL : 1;\r
+ unsigned short CPHA : 1;\r
+#endif\r
+ } BIT;\r
+ } SPCMD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CPHA : 1;\r
+ unsigned short CPOL : 1;\r
+ unsigned short BRDV : 2;\r
+ unsigned short SSLA : 3;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SCKDEN : 1;\r
+#else\r
+ unsigned short SCKDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SSLA : 3;\r
+ unsigned short BRDV : 2;\r
+ unsigned short CPOL : 1;\r
+ unsigned short CPHA : 1;\r
+#endif\r
+ } BIT;\r
+ } SPCMD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CPHA : 1;\r
+ unsigned short CPOL : 1;\r
+ unsigned short BRDV : 2;\r
+ unsigned short SSLA : 3;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SCKDEN : 1;\r
+#else\r
+ unsigned short SCKDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SSLA : 3;\r
+ unsigned short BRDV : 2;\r
+ unsigned short CPOL : 1;\r
+ unsigned short CPHA : 1;\r
+#endif\r
+ } BIT;\r
+ } SPCMD5;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CPHA : 1;\r
+ unsigned short CPOL : 1;\r
+ unsigned short BRDV : 2;\r
+ unsigned short SSLA : 3;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SCKDEN : 1;\r
+#else\r
+ unsigned short SCKDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SSLA : 3;\r
+ unsigned short BRDV : 2;\r
+ unsigned short CPOL : 1;\r
+ unsigned short CPHA : 1;\r
+#endif\r
+ } BIT;\r
+ } SPCMD6;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CPHA : 1;\r
+ unsigned short CPOL : 1;\r
+ unsigned short BRDV : 2;\r
+ unsigned short SSLA : 3;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SCKDEN : 1;\r
+#else\r
+ unsigned short SCKDEN : 1;\r
+ unsigned short SLNDEN : 1;\r
+ unsigned short SPNDEN : 1;\r
+ unsigned short LSBF : 1;\r
+ unsigned short SPB : 4;\r
+ unsigned short SSLKP : 1;\r
+ unsigned short SSLA : 3;\r
+ unsigned short BRDV : 2;\r
+ unsigned short CPOL : 1;\r
+ unsigned short CPHA : 1;\r
+#endif\r
+ } BIT;\r
+ } SPCMD7;\r
+};\r
+\r
+struct st_rtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char F64HZ : 1;\r
+ unsigned char F32HZ : 1;\r
+ unsigned char F16HZ : 1;\r
+ unsigned char F8HZ : 1;\r
+ unsigned char F4HZ : 1;\r
+ unsigned char F2HZ : 1;\r
+ unsigned char F1HZ : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char F1HZ : 1;\r
+ unsigned char F2HZ : 1;\r
+ unsigned char F4HZ : 1;\r
+ unsigned char F8HZ : 1;\r
+ unsigned char F16HZ : 1;\r
+ unsigned char F32HZ : 1;\r
+ unsigned char F64HZ : 1;\r
+#endif\r
+ } BIT;\r
+ } R64CNT;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SEC1 : 4;\r
+ unsigned char SEC10 : 3;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char SEC10 : 3;\r
+ unsigned char SEC1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RSECCNT;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MIN1 : 4;\r
+ unsigned char MIN10 : 3;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char MIN10 : 3;\r
+ unsigned char MIN1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RMINCNT;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char HR1 : 4;\r
+ unsigned char HR10 : 2;\r
+ unsigned char PM : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char PM : 1;\r
+ unsigned char HR10 : 2;\r
+ unsigned char HR1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RHRCNT;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char DAYW : 3;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char DAYW : 3;\r
+#endif\r
+ } BIT;\r
+ } RWKCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char DATE1 : 4;\r
+ unsigned char DATE10 : 2;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char DATE10 : 2;\r
+ unsigned char DATE1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RDAYCNT;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MON1 : 4;\r
+ unsigned char MON10 : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char MON10 : 1;\r
+ unsigned char MON1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RMONCNT;\r
+ char wk6[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short YR1 : 4;\r
+ unsigned short YR10 : 4;\r
+ unsigned short : 8;\r
+#else\r
+ unsigned short : 8;\r
+ unsigned short YR10 : 4;\r
+ unsigned short YR1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RYRCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SEC1 : 4;\r
+ unsigned char SEC10 : 3;\r
+ unsigned char ENB : 1;\r
+#else\r
+ unsigned char ENB : 1;\r
+ unsigned char SEC10 : 3;\r
+ unsigned char SEC1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RSECAR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MIN1 : 4;\r
+ unsigned char MIN10 : 3;\r
+ unsigned char ENB : 1;\r
+#else\r
+ unsigned char ENB : 1;\r
+ unsigned char MIN10 : 3;\r
+ unsigned char MIN1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RMINAR;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char HR1 : 4;\r
+ unsigned char HR10 : 2;\r
+ unsigned char PM : 1;\r
+ unsigned char ENB : 1;\r
+#else\r
+ unsigned char ENB : 1;\r
+ unsigned char PM : 1;\r
+ unsigned char HR10 : 2;\r
+ unsigned char HR1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RHRAR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char DAYW : 3;\r
+ unsigned char : 4;\r
+ unsigned char ENB : 1;\r
+#else\r
+ unsigned char ENB : 1;\r
+ unsigned char : 4;\r
+ unsigned char DAYW : 3;\r
+#endif\r
+ } BIT;\r
+ } RWKAR;\r
+ char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char DATE1 : 4;\r
+ unsigned char DATE10 : 2;\r
+ unsigned char : 1;\r
+ unsigned char ENB : 1;\r
+#else\r
+ unsigned char ENB : 1;\r
+ unsigned char : 1;\r
+ unsigned char DATE10 : 2;\r
+ unsigned char DATE1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RDAYAR;\r
+ char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MON1 : 4;\r
+ unsigned char MON10 : 1;\r
+ unsigned char : 2;\r
+ unsigned char ENB : 1;\r
+#else\r
+ unsigned char ENB : 1;\r
+ unsigned char : 2;\r
+ unsigned char MON10 : 1;\r
+ unsigned char MON1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RMONAR;\r
+ char wk12[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short YR1 : 4;\r
+ unsigned short YR10 : 4;\r
+ unsigned short : 8;\r
+#else\r
+ unsigned short : 8;\r
+ unsigned short YR10 : 4;\r
+ unsigned short YR1 : 4;\r
+#endif\r
+ } BIT;\r
+ } RYRAR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 7;\r
+ unsigned char ENB : 1;\r
+#else\r
+ unsigned char ENB : 1;\r
+ unsigned char : 7;\r
+#endif\r
+ } BIT;\r
+ } RYRAREN;\r
+ char wk13[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char AIE : 1;\r
+ unsigned char CIE : 1;\r
+ unsigned char PIE : 1;\r
+ unsigned char RTCOS : 1;\r
+ unsigned char PES : 4;\r
+#else\r
+ unsigned char PES : 4;\r
+ unsigned char RTCOS : 1;\r
+ unsigned char PIE : 1;\r
+ unsigned char CIE : 1;\r
+ unsigned char AIE : 1;\r
+#endif\r
+ } BIT;\r
+ } RCR1;\r
+ char wk14[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char START : 1;\r
+ unsigned char RESET : 1;\r
+ unsigned char ADJ30 : 1;\r
+ unsigned char RTCOE : 1;\r
+ unsigned char AADJE : 1;\r
+ unsigned char AADJP : 1;\r
+ unsigned char HR24 : 1;\r
+ unsigned char CNTMD : 1;\r
+#else\r
+ unsigned char CNTMD : 1;\r
+ unsigned char HR24 : 1;\r
+ unsigned char AADJP : 1;\r
+ unsigned char AADJE : 1;\r
+ unsigned char RTCOE : 1;\r
+ unsigned char ADJ30 : 1;\r
+ unsigned char RESET : 1;\r
+ unsigned char START : 1;\r
+#endif\r
+ } BIT;\r
+ } RCR2;\r
+ char wk15[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char RTCEN : 1;\r
+ unsigned char RTCDV : 3;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char RTCDV : 3;\r
+ unsigned char RTCEN : 1;\r
+#endif\r
+ } BIT;\r
+ } RCR3;\r
+ char wk16[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char ADJ : 6;\r
+ unsigned char PMADJ : 2;\r
+#else\r
+ unsigned char PMADJ : 2;\r
+ unsigned char ADJ : 6;\r
+#endif\r
+ } BIT;\r
+ } RADJ;\r
+};\r
+\r
+struct st_rtcb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BCNT : 8;\r
+#else\r
+ unsigned char BCNT : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT0;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BCNT : 8;\r
+#else\r
+ unsigned char BCNT : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT1;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BCNT : 8;\r
+#else\r
+ unsigned char BCNT : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BCNT : 8;\r
+#else\r
+ unsigned char BCNT : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT3;\r
+ char wk3[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BCNTAR : 8;\r
+#else\r
+ unsigned char BCNTAR : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT0AR;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BCNTAR : 8;\r
+#else\r
+ unsigned char BCNTAR : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT1AR;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BCNTAR : 8;\r
+#else\r
+ unsigned char BCNTAR : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT2AR;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BCNTAR : 8;\r
+#else\r
+ unsigned char BCNTAR : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT3AR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char ENB : 8;\r
+#else\r
+ unsigned char ENB : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT0AER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char ENB : 8;\r
+#else\r
+ unsigned char ENB : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT1AER;\r
+ char wk9[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short ENB : 8;\r
+ unsigned short : 8;\r
+#else\r
+ unsigned short : 8;\r
+ unsigned short ENB : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT2AER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char ENB : 8;\r
+#else\r
+ unsigned char ENB : 8;\r
+#endif\r
+ } BIT;\r
+ } BCNT3AER;\r
+};\r
+\r
+struct st_s12ad {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short DBLANS : 5;\r
+ unsigned short : 1;\r
+ unsigned short GBADIE : 1;\r
+ unsigned short DBLE : 1;\r
+ unsigned short EXTRG : 1;\r
+ unsigned short TRGE : 1;\r
+ unsigned short ADHSC : 1;\r
+ unsigned short : 1;\r
+ unsigned short ADIE : 1;\r
+ unsigned short ADCS : 2;\r
+ unsigned short ADST : 1;\r
+#else\r
+ unsigned short ADST : 1;\r
+ unsigned short ADCS : 2;\r
+ unsigned short ADIE : 1;\r
+ unsigned short : 1;\r
+ unsigned short ADHSC : 1;\r
+ unsigned short TRGE : 1;\r
+ unsigned short EXTRG : 1;\r
+ unsigned short DBLE : 1;\r
+ unsigned short GBADIE : 1;\r
+ unsigned short : 1;\r
+ unsigned short DBLANS : 5;\r
+#endif\r
+ } BIT;\r
+ } ADCSR;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short ANSA:16;\r
+// } BIT;\r
+ } ADANSA;\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short :10;\r
+// unsigned short ANSA1:1;\r
+// } BIT;\r
+ } ADANSA1;\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short ADS:16;\r
+// } BIT;\r
+ } ADADS;\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short :10;\r
+// unsigned short ADS1:1;\r
+// } BIT;\r
+ } ADADS1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char ADC : 2;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char ADC : 2;\r
+#endif\r
+ } BIT;\r
+ } ADADC;\r
+ char wk1[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 5;\r
+ unsigned short ACE : 1;\r
+ unsigned short : 9;\r
+ unsigned short ADRFMT : 1;\r
+#else\r
+ unsigned short ADRFMT : 1;\r
+ unsigned short : 9;\r
+ unsigned short ACE : 1;\r
+ unsigned short : 5;\r
+#endif\r
+ } BIT;\r
+ } ADCER;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short TRSB : 4;\r
+ unsigned short : 4;\r
+ unsigned short TRSA : 4;\r
+ unsigned short : 4;\r
+#else\r
+ unsigned short : 4;\r
+ unsigned short TRSA : 4;\r
+ unsigned short : 4;\r
+ unsigned short TRSB : 4;\r
+#endif\r
+ } BIT;\r
+ } ADSTRGR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short TSSAD : 1;\r
+ unsigned short OCSAD : 1;\r
+ unsigned short : 6;\r
+ unsigned short TSS : 1;\r
+ unsigned short OCS : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short OCS : 1;\r
+ unsigned short TSS : 1;\r
+ unsigned short : 6;\r
+ unsigned short OCSAD : 1;\r
+ unsigned short TSSAD : 1;\r
+#endif\r
+ } BIT;\r
+ } ADEXICR;\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short ANSB:16;\r
+// } BIT;\r
+ } ADANSB;\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short :10;\r
+// unsigned short ANSB1:1;\r
+// } BIT;\r
+ } ADANSB1;\r
+ unsigned short ADDBLDR;\r
+ unsigned short ADTSDR;\r
+ unsigned short ADOCDR;\r
+ char wk2[2];\r
+ unsigned short ADDR0;\r
+ unsigned short ADDR1;\r
+ unsigned short ADDR2;\r
+ unsigned short ADDR3;\r
+ unsigned short ADDR4;\r
+ unsigned short ADDR5;\r
+ unsigned short ADDR6;\r
+ unsigned short ADDR7;\r
+ unsigned short ADDR8;\r
+ unsigned short ADDR9;\r
+ unsigned short ADDR10;\r
+ unsigned short ADDR11;\r
+ unsigned short ADDR12;\r
+ unsigned short ADDR13;\r
+ unsigned short ADDR14;\r
+ unsigned short ADDR15;\r
+ char wk3[10];\r
+ unsigned short ADDR21;\r
+ char wk4[20];\r
+ unsigned char ADSSTR0;\r
+ unsigned char ADSSTRL;\r
+ char wk5[14];\r
+ unsigned char ADSSTRT;\r
+ unsigned char ADSSTRO;\r
+ char wk6[1];\r
+ unsigned char ADSSTR1;\r
+ unsigned char ADSSTR2;\r
+ unsigned char ADSSTR3;\r
+ unsigned char ADSSTR4;\r
+ unsigned char ADSSTR5;\r
+ unsigned char ADSSTR6;\r
+ unsigned char ADSSTR7;\r
+ char wk7[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char HVREFDIS : 1;\r
+ unsigned char OCSVSEL : 1;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char OCSVSEL : 1;\r
+ unsigned char HVREFDIS : 1;\r
+#endif\r
+ } BIT;\r
+ } ADHVREFCNT;\r
+ char wk8[3];\r
+ unsigned char ADSSTR21;\r
+};\r
+\r
+struct st_sci0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CKS : 2;\r
+ unsigned char MP : 1;\r
+ unsigned char STOP : 1;\r
+ unsigned char PM : 1;\r
+ unsigned char PE : 1;\r
+ unsigned char CHR : 1;\r
+ unsigned char CM : 1;\r
+#else\r
+ unsigned char CM : 1;\r
+ unsigned char CHR : 1;\r
+ unsigned char PE : 1;\r
+ unsigned char PM : 1;\r
+ unsigned char STOP : 1;\r
+ unsigned char MP : 1;\r
+ unsigned char CKS : 2;\r
+#endif\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CKE : 2;\r
+ unsigned char TEIE : 1;\r
+ unsigned char MPIE : 1;\r
+ unsigned char RE : 1;\r
+ unsigned char TE : 1;\r
+ unsigned char RIE : 1;\r
+ unsigned char TIE : 1;\r
+#else\r
+ unsigned char TIE : 1;\r
+ unsigned char RIE : 1;\r
+ unsigned char TE : 1;\r
+ unsigned char RE : 1;\r
+ unsigned char MPIE : 1;\r
+ unsigned char TEIE : 1;\r
+ unsigned char CKE : 2;\r
+#endif\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MPBT : 1;\r
+ unsigned char MPB : 1;\r
+ unsigned char TEND : 1;\r
+ unsigned char PER : 1;\r
+ unsigned char FER : 1;\r
+ unsigned char ORER : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char ORER : 1;\r
+ unsigned char FER : 1;\r
+ unsigned char PER : 1;\r
+ unsigned char TEND : 1;\r
+ unsigned char MPB : 1;\r
+ unsigned char MPBT : 1;\r
+#endif\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SMIF : 1;\r
+ unsigned char : 1;\r
+ unsigned char SINV : 1;\r
+ unsigned char SDIR : 1;\r
+ unsigned char : 3;\r
+ unsigned char BCP2 : 1;\r
+#else\r
+ unsigned char BCP2 : 1;\r
+ unsigned char : 3;\r
+ unsigned char SDIR : 1;\r
+ unsigned char SINV : 1;\r
+ unsigned char : 1;\r
+ unsigned char SMIF : 1;\r
+#endif\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char ACS0 : 1;\r
+ unsigned char : 3;\r
+ unsigned char ABCS : 1;\r
+ unsigned char NFEN : 1;\r
+ unsigned char : 1;\r
+ unsigned char RXDESEL : 1;\r
+#else\r
+ unsigned char RXDESEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char NFEN : 1;\r
+ unsigned char ABCS : 1;\r
+ unsigned char : 3;\r
+ unsigned char ACS0 : 1;\r
+#endif\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NFCS : 3;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char NFCS : 3;\r
+#endif\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IICM : 1;\r
+ unsigned char : 2;\r
+ unsigned char IICDL : 5;\r
+#else\r
+ unsigned char IICDL : 5;\r
+ unsigned char : 2;\r
+ unsigned char IICM : 1;\r
+#endif\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IICINTM : 1;\r
+ unsigned char IICCSC : 1;\r
+ unsigned char : 3;\r
+ unsigned char IICACKT : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char IICACKT : 1;\r
+ unsigned char : 3;\r
+ unsigned char IICCSC : 1;\r
+ unsigned char IICINTM : 1;\r
+#endif\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IICSTAREQ : 1;\r
+ unsigned char IICRSTAREQ : 1;\r
+ unsigned char IICSTPREQ : 1;\r
+ unsigned char IICSTIF : 1;\r
+ unsigned char IICSDAS : 2;\r
+ unsigned char IICSCLS : 2;\r
+#else\r
+ unsigned char IICSCLS : 2;\r
+ unsigned char IICSDAS : 2;\r
+ unsigned char IICSTIF : 1;\r
+ unsigned char IICSTPREQ : 1;\r
+ unsigned char IICRSTAREQ : 1;\r
+ unsigned char IICSTAREQ : 1;\r
+#endif\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IICACKR : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char IICACKR : 1;\r
+#endif\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SSE : 1;\r
+ unsigned char CTSE : 1;\r
+ unsigned char MSS : 1;\r
+ unsigned char : 1;\r
+ unsigned char MFF : 1;\r
+ unsigned char : 1;\r
+ unsigned char CKPOL : 1;\r
+ unsigned char CKPH : 1;\r
+#else\r
+ unsigned char CKPH : 1;\r
+ unsigned char CKPOL : 1;\r
+ unsigned char : 1;\r
+ unsigned char MFF : 1;\r
+ unsigned char : 1;\r
+ unsigned char MSS : 1;\r
+ unsigned char CTSE : 1;\r
+ unsigned char SSE : 1;\r
+#endif\r
+ } BIT;\r
+ } SPMR;\r
+};\r
+\r
+struct st_sci12 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CKS : 2;\r
+ unsigned char MP : 1;\r
+ unsigned char STOP : 1;\r
+ unsigned char PM : 1;\r
+ unsigned char PE : 1;\r
+ unsigned char CHR : 1;\r
+ unsigned char CM : 1;\r
+#else\r
+ unsigned char CM : 1;\r
+ unsigned char CHR : 1;\r
+ unsigned char PE : 1;\r
+ unsigned char PM : 1;\r
+ unsigned char STOP : 1;\r
+ unsigned char MP : 1;\r
+ unsigned char CKS : 2;\r
+#endif\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CKE : 2;\r
+ unsigned char TEIE : 1;\r
+ unsigned char MPIE : 1;\r
+ unsigned char RE : 1;\r
+ unsigned char TE : 1;\r
+ unsigned char RIE : 1;\r
+ unsigned char TIE : 1;\r
+#else\r
+ unsigned char TIE : 1;\r
+ unsigned char RIE : 1;\r
+ unsigned char TE : 1;\r
+ unsigned char RE : 1;\r
+ unsigned char MPIE : 1;\r
+ unsigned char TEIE : 1;\r
+ unsigned char CKE : 2;\r
+#endif\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MPBT : 1;\r
+ unsigned char MPB : 1;\r
+ unsigned char TEND : 1;\r
+ unsigned char PER : 1;\r
+ unsigned char FER : 1;\r
+ unsigned char ORER : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char ORER : 1;\r
+ unsigned char FER : 1;\r
+ unsigned char PER : 1;\r
+ unsigned char TEND : 1;\r
+ unsigned char MPB : 1;\r
+ unsigned char MPBT : 1;\r
+#endif\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SMIF : 1;\r
+ unsigned char : 1;\r
+ unsigned char SINV : 1;\r
+ unsigned char SDIR : 1;\r
+ unsigned char : 3;\r
+ unsigned char BCP2 : 1;\r
+#else\r
+ unsigned char BCP2 : 1;\r
+ unsigned char : 3;\r
+ unsigned char SDIR : 1;\r
+ unsigned char SINV : 1;\r
+ unsigned char : 1;\r
+ unsigned char SMIF : 1;\r
+#endif\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char ACS0 : 1;\r
+ unsigned char : 3;\r
+ unsigned char ABCS : 1;\r
+ unsigned char NFEN : 1;\r
+ unsigned char : 1;\r
+ unsigned char RXDESEL : 1;\r
+#else\r
+ unsigned char RXDESEL : 1;\r
+ unsigned char : 1;\r
+ unsigned char NFEN : 1;\r
+ unsigned char ABCS : 1;\r
+ unsigned char : 3;\r
+ unsigned char ACS0 : 1;\r
+#endif\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char NFCS : 3;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char NFCS : 3;\r
+#endif\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IICM : 1;\r
+ unsigned char : 2;\r
+ unsigned char IICDL : 5;\r
+#else\r
+ unsigned char IICDL : 5;\r
+ unsigned char : 2;\r
+ unsigned char IICM : 1;\r
+#endif\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IICINTM : 1;\r
+ unsigned char IICCSC : 1;\r
+ unsigned char : 3;\r
+ unsigned char IICACKT : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char IICACKT : 1;\r
+ unsigned char : 3;\r
+ unsigned char IICCSC : 1;\r
+ unsigned char IICINTM : 1;\r
+#endif\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IICSTAREQ : 1;\r
+ unsigned char IICRSTAREQ : 1;\r
+ unsigned char IICSTPREQ : 1;\r
+ unsigned char IICSTIF : 1;\r
+ unsigned char IICSDAS : 2;\r
+ unsigned char IICSCLS : 2;\r
+#else\r
+ unsigned char IICSCLS : 2;\r
+ unsigned char IICSDAS : 2;\r
+ unsigned char IICSTIF : 1;\r
+ unsigned char IICSTPREQ : 1;\r
+ unsigned char IICRSTAREQ : 1;\r
+ unsigned char IICSTAREQ : 1;\r
+#endif\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IICACKR : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char IICACKR : 1;\r
+#endif\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SSE : 1;\r
+ unsigned char CTSE : 1;\r
+ unsigned char MSS : 1;\r
+ unsigned char : 1;\r
+ unsigned char MFF : 1;\r
+ unsigned char : 1;\r
+ unsigned char CKPOL : 1;\r
+ unsigned char CKPH : 1;\r
+#else\r
+ unsigned char CKPH : 1;\r
+ unsigned char CKPOL : 1;\r
+ unsigned char : 1;\r
+ unsigned char MFF : 1;\r
+ unsigned char : 1;\r
+ unsigned char MSS : 1;\r
+ unsigned char CTSE : 1;\r
+ unsigned char SSE : 1;\r
+#endif\r
+ } BIT;\r
+ } SPMR;\r
+ char wk0[18];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char ESME : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char ESME : 1;\r
+#endif\r
+ } BIT;\r
+ } ESMER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 1;\r
+ unsigned char SFSF : 1;\r
+ unsigned char RXDSF : 1;\r
+ unsigned char BRME : 1;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char BRME : 1;\r
+ unsigned char RXDSF : 1;\r
+ unsigned char SFSF : 1;\r
+ unsigned char : 1;\r
+#endif\r
+ } BIT;\r
+ } CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BFE : 1;\r
+ unsigned char CF0RE : 1;\r
+ unsigned char CF1DS : 2;\r
+ unsigned char PIBE : 1;\r
+ unsigned char PIBS : 3;\r
+#else\r
+ unsigned char PIBS : 3;\r
+ unsigned char PIBE : 1;\r
+ unsigned char CF1DS : 2;\r
+ unsigned char CF0RE : 1;\r
+ unsigned char BFE : 1;\r
+#endif\r
+ } BIT;\r
+ } CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char DFCS : 3;\r
+ unsigned char : 1;\r
+ unsigned char BCCS : 2;\r
+ unsigned char RTS : 2;\r
+#else\r
+ unsigned char RTS : 2;\r
+ unsigned char BCCS : 2;\r
+ unsigned char : 1;\r
+ unsigned char DFCS : 3;\r
+#endif\r
+ } BIT;\r
+ } CR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SDST : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char SDST : 1;\r
+#endif\r
+ } BIT;\r
+ } CR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TXDXPS : 1;\r
+ unsigned char RXDXPS : 1;\r
+ unsigned char : 2;\r
+ unsigned char SHARPS : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char SHARPS : 1;\r
+ unsigned char : 2;\r
+ unsigned char RXDXPS : 1;\r
+ unsigned char TXDXPS : 1;\r
+#endif\r
+ } BIT;\r
+ } PCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BFDIE : 1;\r
+ unsigned char CF0MIE : 1;\r
+ unsigned char CF1MIE : 1;\r
+ unsigned char PIBDIE : 1;\r
+ unsigned char BCDIE : 1;\r
+ unsigned char AEDIE : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char AEDIE : 1;\r
+ unsigned char BCDIE : 1;\r
+ unsigned char PIBDIE : 1;\r
+ unsigned char CF1MIE : 1;\r
+ unsigned char CF0MIE : 1;\r
+ unsigned char BFDIE : 1;\r
+#endif\r
+ } BIT;\r
+ } ICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BFDF : 1;\r
+ unsigned char CF0MF : 1;\r
+ unsigned char CF1MF : 1;\r
+ unsigned char PIBDF : 1;\r
+ unsigned char BCDF : 1;\r
+ unsigned char AEDF : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char AEDF : 1;\r
+ unsigned char BCDF : 1;\r
+ unsigned char PIBDF : 1;\r
+ unsigned char CF1MF : 1;\r
+ unsigned char CF0MF : 1;\r
+ unsigned char BFDF : 1;\r
+#endif\r
+ } BIT;\r
+ } STR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char BFDCL : 1;\r
+ unsigned char CF0MCL : 1;\r
+ unsigned char CF1MCL : 1;\r
+ unsigned char PIBDCL : 1;\r
+ unsigned char BCDCL : 1;\r
+ unsigned char AEDCL : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char AEDCL : 1;\r
+ unsigned char BCDCL : 1;\r
+ unsigned char PIBDCL : 1;\r
+ unsigned char CF1MCL : 1;\r
+ unsigned char CF0MCL : 1;\r
+ unsigned char BFDCL : 1;\r
+#endif\r
+ } BIT;\r
+ } STCR;\r
+ unsigned char CF0DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CF0CE0 : 1;\r
+ unsigned char CF0CE1 : 1;\r
+ unsigned char CF0CE2 : 1;\r
+ unsigned char CF0CE3 : 1;\r
+ unsigned char CF0CE4 : 1;\r
+ unsigned char CF0CE5 : 1;\r
+ unsigned char CF0CE6 : 1;\r
+ unsigned char CF0CE7 : 1;\r
+#else\r
+ unsigned char CF0CE7 : 1;\r
+ unsigned char CF0CE6 : 1;\r
+ unsigned char CF0CE5 : 1;\r
+ unsigned char CF0CE4 : 1;\r
+ unsigned char CF0CE3 : 1;\r
+ unsigned char CF0CE2 : 1;\r
+ unsigned char CF0CE1 : 1;\r
+ unsigned char CF0CE0 : 1;\r
+#endif\r
+ } BIT;\r
+ } CF0CR;\r
+ unsigned char CF0RR;\r
+ unsigned char PCF1DR;\r
+ unsigned char SCF1DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CF1CE0 : 1;\r
+ unsigned char CF1CE1 : 1;\r
+ unsigned char CF1CE2 : 1;\r
+ unsigned char CF1CE3 : 1;\r
+ unsigned char CF1CE4 : 1;\r
+ unsigned char CF1CE5 : 1;\r
+ unsigned char CF1CE6 : 1;\r
+ unsigned char CF1CE7 : 1;\r
+#else\r
+ unsigned char CF1CE7 : 1;\r
+ unsigned char CF1CE6 : 1;\r
+ unsigned char CF1CE5 : 1;\r
+ unsigned char CF1CE4 : 1;\r
+ unsigned char CF1CE3 : 1;\r
+ unsigned char CF1CE2 : 1;\r
+ unsigned char CF1CE1 : 1;\r
+ unsigned char CF1CE0 : 1;\r
+#endif\r
+ } BIT;\r
+ } CF1CR;\r
+ unsigned char CF1RR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TCST : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char TCST : 1;\r
+#endif\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TOMS : 2;\r
+ unsigned char : 1;\r
+ unsigned char TWRC : 1;\r
+ unsigned char TCSS : 3;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char TCSS : 3;\r
+ unsigned char TWRC : 1;\r
+ unsigned char : 1;\r
+ unsigned char TOMS : 2;\r
+#endif\r
+ } BIT;\r
+ } TMR;\r
+ unsigned char TPRE;\r
+ unsigned char TCNT;\r
+};\r
+\r
+struct st_smci {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CKS : 2;\r
+ unsigned char BCP : 2;\r
+ unsigned char PM : 1;\r
+ unsigned char PE : 1;\r
+ unsigned char BLK : 1;\r
+ unsigned char GM : 1;\r
+#else\r
+ unsigned char GM : 1;\r
+ unsigned char BLK : 1;\r
+ unsigned char PE : 1;\r
+ unsigned char PM : 1;\r
+ unsigned char BCP : 2;\r
+ unsigned char CKS : 2;\r
+#endif\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CKE : 2;\r
+ unsigned char TEIE : 1;\r
+ unsigned char MPIE : 1;\r
+ unsigned char RE : 1;\r
+ unsigned char TE : 1;\r
+ unsigned char RIE : 1;\r
+ unsigned char TIE : 1;\r
+#else\r
+ unsigned char TIE : 1;\r
+ unsigned char RIE : 1;\r
+ unsigned char TE : 1;\r
+ unsigned char RE : 1;\r
+ unsigned char MPIE : 1;\r
+ unsigned char TEIE : 1;\r
+ unsigned char CKE : 2;\r
+#endif\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MPBT : 1;\r
+ unsigned char MPB : 1;\r
+ unsigned char TEND : 1;\r
+ unsigned char PER : 1;\r
+ unsigned char ERS : 1;\r
+ unsigned char ORER : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char ORER : 1;\r
+ unsigned char ERS : 1;\r
+ unsigned char PER : 1;\r
+ unsigned char TEND : 1;\r
+ unsigned char MPB : 1;\r
+ unsigned char MPBT : 1;\r
+#endif\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SMIF : 1;\r
+ unsigned char : 1;\r
+ unsigned char SINV : 1;\r
+ unsigned char SDIR : 1;\r
+ unsigned char : 3;\r
+ unsigned char BCP2 : 1;\r
+#else\r
+ unsigned char BCP2 : 1;\r
+ unsigned char : 3;\r
+ unsigned char SDIR : 1;\r
+ unsigned char SINV : 1;\r
+ unsigned char : 1;\r
+ unsigned char SMIF : 1;\r
+#endif\r
+ } BIT;\r
+ } SCMR;\r
+};\r
+\r
+struct st_ssi {\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned long REN : 1;\r
+ unsigned long TEN : 1;\r
+ unsigned long : 1;\r
+ unsigned long MUEN : 1;\r
+ unsigned long CKDV : 4;\r
+ unsigned long DEL : 1;\r
+ unsigned long PDTA : 1;\r
+ unsigned long SDTA : 1;\r
+ unsigned long SPDP : 1;\r
+ unsigned long SWSP : 1;\r
+ unsigned long SCKP : 1;\r
+ unsigned long SWSD : 1;\r
+ unsigned long SCKD : 1;\r
+ unsigned long SWL : 3;\r
+ unsigned long DWL : 3;\r
+ unsigned long CHNL : 2;\r
+ unsigned long : 1;\r
+ unsigned long IIEN : 1;\r
+ unsigned long ROIEN : 1;\r
+ unsigned long RUIEN : 1;\r
+ unsigned long TOIEN : 1;\r
+ unsigned long TUIEN : 1;\r
+ unsigned long CKS : 1;\r
+ unsigned long : 1;\r
+#else\r
+ unsigned long : 1;\r
+ unsigned long CKS : 1;\r
+ unsigned long TUIEN : 1;\r
+ unsigned long TOIEN : 1;\r
+ unsigned long RUIEN : 1;\r
+ unsigned long ROIEN : 1;\r
+ unsigned long IIEN : 1;\r
+ unsigned long : 1;\r
+ unsigned long CHNL : 2;\r
+ unsigned long DWL : 3;\r
+ unsigned long SWL : 3;\r
+ unsigned long SCKD : 1;\r
+ unsigned long SWSD : 1;\r
+ unsigned long SCKP : 1;\r
+ unsigned long SWSP : 1;\r
+ unsigned long SPDP : 1;\r
+ unsigned long SDTA : 1;\r
+ unsigned long PDTA : 1;\r
+ unsigned long DEL : 1;\r
+ unsigned long CKDV : 4;\r
+ unsigned long MUEN : 1;\r
+ unsigned long : 1;\r
+ unsigned long TEN : 1;\r
+ unsigned long REN : 1;\r
+#endif\r
+ } BIT;\r
+ } SSICR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned long IDST : 1;\r
+ unsigned long RSWNO : 1;\r
+ unsigned long RCHNO : 2;\r
+ unsigned long TSWNO : 1;\r
+ unsigned long TCHNO : 2;\r
+ unsigned long : 18;\r
+ unsigned long IIRQ : 1;\r
+ unsigned long ROIRQ : 1;\r
+ unsigned long RUIRQ : 1;\r
+ unsigned long TOIRQ : 1;\r
+ unsigned long TUIRQ : 1;\r
+ unsigned long : 2;\r
+#else\r
+ unsigned long : 2;\r
+ unsigned long TUIRQ : 1;\r
+ unsigned long TOIRQ : 1;\r
+ unsigned long RUIRQ : 1;\r
+ unsigned long ROIRQ : 1;\r
+ unsigned long IIRQ : 1;\r
+ unsigned long : 18;\r
+ unsigned long TCHNO : 2;\r
+ unsigned long TSWNO : 1;\r
+ unsigned long RCHNO : 2;\r
+ unsigned long RSWNO : 1;\r
+ unsigned long IDST : 1;\r
+#endif\r
+ } BIT;\r
+ } SSISR;\r
+ char wk0[8];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned long RFRST : 1;\r
+ unsigned long TFRST : 1;\r
+ unsigned long RIE : 1;\r
+ unsigned long TIE : 1;\r
+ unsigned long RTRG : 2;\r
+ unsigned long TTRG : 2;\r
+ unsigned long : 8;\r
+ unsigned long SSIRST : 1;\r
+ unsigned long : 14;\r
+ unsigned long AUCKE : 1;\r
+#else\r
+ unsigned long AUCKE : 1;\r
+ unsigned long : 14;\r
+ unsigned long SSIRST : 1;\r
+ unsigned long : 8;\r
+ unsigned long TTRG : 2;\r
+ unsigned long RTRG : 2;\r
+ unsigned long TIE : 1;\r
+ unsigned long RIE : 1;\r
+ unsigned long TFRST : 1;\r
+ unsigned long RFRST : 1;\r
+#endif\r
+ } BIT;\r
+ } SSIFCR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned long RDF : 1;\r
+ unsigned long : 7;\r
+ unsigned long RDC : 4;\r
+ unsigned long : 4;\r
+ unsigned long TDE : 1;\r
+ unsigned long : 7;\r
+ unsigned long TDC : 4;\r
+ unsigned long : 4;\r
+#else\r
+ unsigned long : 4;\r
+ unsigned long TDC : 4;\r
+ unsigned long : 7;\r
+ unsigned long TDE : 1;\r
+ unsigned long : 4;\r
+ unsigned long RDC : 4;\r
+ unsigned long : 7;\r
+ unsigned long RDF : 1;\r
+#endif\r
+ } BIT;\r
+ } SSIFSR;\r
+ unsigned long SSIFTDR;\r
+ unsigned long SSIFRDR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned long : 8;\r
+ unsigned long CONT : 1;\r
+ unsigned long : 23;\r
+#else\r
+ unsigned long : 23;\r
+ unsigned long CONT : 1;\r
+ unsigned long : 8;\r
+#endif\r
+ } BIT;\r
+ } SSITDMR;\r
+};\r
+\r
+struct st_system {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short MD : 1;\r
+ unsigned short : 15;\r
+#else\r
+ unsigned short : 15;\r
+ unsigned short MD : 1;\r
+#endif\r
+ } BIT;\r
+ } MDMONR;\r
+ char wk0[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short RAME : 1;\r
+ unsigned short : 15;\r
+#else\r
+ unsigned short : 15;\r
+ unsigned short RAME : 1;\r
+#endif\r
+ } BIT;\r
+ } SYSCR1;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 15;\r
+ unsigned short SSBY : 1;\r
+#else\r
+ unsigned short SSBY : 1;\r
+ unsigned short : 15;\r
+#endif\r
+ } BIT;\r
+ } SBYCR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned long : 4;\r
+ unsigned long MSTPA4 : 1;\r
+ unsigned long MSTPA5 : 1;\r
+ unsigned long : 3;\r
+ unsigned long MSTPA9 : 1;\r
+ unsigned long : 4;\r
+ unsigned long MSTPA14 : 1;\r
+ unsigned long MSTPA15 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPA17 : 1;\r
+ unsigned long MSTPA18 : 1;\r
+ unsigned long : 9;\r
+ unsigned long MSTPA28 : 1;\r
+ unsigned long : 3;\r
+#else\r
+ unsigned long : 3;\r
+ unsigned long MSTPA28 : 1;\r
+ unsigned long : 9;\r
+ unsigned long MSTPA18 : 1;\r
+ unsigned long MSTPA17 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPA15 : 1;\r
+ unsigned long MSTPA14 : 1;\r
+ unsigned long : 4;\r
+ unsigned long MSTPA9 : 1;\r
+ unsigned long : 3;\r
+ unsigned long MSTPA5 : 1;\r
+ unsigned long MSTPA4 : 1;\r
+ unsigned long : 4;\r
+#endif\r
+ } BIT;\r
+ } MSTPCRA;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned long : 4;\r
+ unsigned long MSTPB4 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPB6 : 1;\r
+ unsigned long : 2;\r
+ unsigned long MSTPB9 : 1;\r
+ unsigned long MSTPB10 : 1;\r
+ unsigned long : 6;\r
+ unsigned long MSTPB17 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPB19 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPB21 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPB23 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPB25 : 1;\r
+ unsigned long MSTPB26 : 1;\r
+ unsigned long : 2;\r
+ unsigned long MSTPB29 : 1;\r
+ unsigned long MSTPB30 : 1;\r
+ unsigned long MSTPB31 : 1;\r
+#else\r
+ unsigned long MSTPB31 : 1;\r
+ unsigned long MSTPB30 : 1;\r
+ unsigned long MSTPB29 : 1;\r
+ unsigned long : 2;\r
+ unsigned long MSTPB26 : 1;\r
+ unsigned long MSTPB25 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPB23 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPB21 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPB19 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPB17 : 1;\r
+ unsigned long : 6;\r
+ unsigned long MSTPB10 : 1;\r
+ unsigned long MSTPB9 : 1;\r
+ unsigned long : 2;\r
+ unsigned long MSTPB6 : 1;\r
+ unsigned long : 1;\r
+ unsigned long MSTPB4 : 1;\r
+ unsigned long : 4;\r
+#endif\r
+ } BIT;\r
+ } MSTPCRB;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned long MSTPC0 : 1;\r
+ unsigned long : 18;\r
+ unsigned long MSTPC19 : 1;\r
+ unsigned long MSTPC20 : 1;\r
+ unsigned long : 5;\r
+ unsigned long MSTPC26 : 1;\r
+ unsigned long MSTPC27 : 1;\r
+ unsigned long : 3;\r
+ unsigned long DSLPE : 1;\r
+#else\r
+ unsigned long DSLPE : 1;\r
+ unsigned long : 3;\r
+ unsigned long MSTPC27 : 1;\r
+ unsigned long MSTPC26 : 1;\r
+ unsigned long : 5;\r
+ unsigned long MSTPC20 : 1;\r
+ unsigned long MSTPC19 : 1;\r
+ unsigned long : 18;\r
+ unsigned long MSTPC0 : 1;\r
+#endif\r
+ } BIT;\r
+ } MSTPCRC;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned long : 10;\r
+ unsigned long MSTPD10 : 1;\r
+ unsigned long MSTPD11 : 1;\r
+ unsigned long : 3;\r
+ unsigned long MSTPD15 : 1;\r
+ unsigned long : 16;\r
+#else\r
+ unsigned long : 16;\r
+ unsigned long MSTPD15 : 1;\r
+ unsigned long : 3;\r
+ unsigned long MSTPD11 : 1;\r
+ unsigned long MSTPD10 : 1;\r
+ unsigned long : 10;\r
+#endif\r
+ } BIT;\r
+ } MSTPCRD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned long PCKD : 4;\r
+ unsigned long : 4;\r
+ unsigned long PCKB : 4;\r
+ unsigned long : 12;\r
+ unsigned long ICK : 4;\r
+ unsigned long FCK : 4;\r
+#else\r
+ unsigned long FCK : 4;\r
+ unsigned long ICK : 4;\r
+ unsigned long : 12;\r
+ unsigned long PCKB : 4;\r
+ unsigned long : 4;\r
+ unsigned long PCKD : 4;\r
+#endif\r
+ } BIT;\r
+ } SCKCR;\r
+ char wk3[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 8;\r
+ unsigned short CKSEL : 3;\r
+ unsigned short : 5;\r
+#else\r
+ unsigned short : 5;\r
+ unsigned short CKSEL : 3;\r
+ unsigned short : 8;\r
+#endif\r
+ } BIT;\r
+ } SCKCR3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PLIDIV : 2;\r
+ unsigned short : 6;\r
+ unsigned short STC : 6;\r
+ unsigned short : 2;\r
+#else\r
+ unsigned short : 2;\r
+ unsigned short STC : 6;\r
+ unsigned short : 6;\r
+ unsigned short PLIDIV : 2;\r
+#endif\r
+ } BIT;\r
+ } PLLCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PLLEN : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char PLLEN : 1;\r
+#endif\r
+ } BIT;\r
+ } PLLCR2;\r
+ char wk4[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short UPLIDIV : 2;\r
+ unsigned short : 2;\r
+ unsigned short UCKUPLLSEL : 1;\r
+ unsigned short : 3;\r
+ unsigned short USTC : 6;\r
+ unsigned short : 2;\r
+#else\r
+ unsigned short : 2;\r
+ unsigned short USTC : 6;\r
+ unsigned short : 3;\r
+ unsigned short UCKUPLLSEL : 1;\r
+ unsigned short : 2;\r
+ unsigned short UPLIDIV : 2;\r
+#endif\r
+ } BIT;\r
+ } UPLLCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char UPLLEN : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char UPLLEN : 1;\r
+#endif\r
+ } BIT;\r
+ } UPLLCR2;\r
+ char wk5[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MOSTP : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char MOSTP : 1;\r
+#endif\r
+ } BIT;\r
+ } MOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SOSTP : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char SOSTP : 1;\r
+#endif\r
+ } BIT;\r
+ } SOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LCSTP : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char LCSTP : 1;\r
+#endif\r
+ } BIT;\r
+ } LOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char ILCSTP : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char ILCSTP : 1;\r
+#endif\r
+ } BIT;\r
+ } ILOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char HCSTP : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char HCSTP : 1;\r
+#endif\r
+ } BIT;\r
+ } HOCOCR;\r
+ char wk6[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MOOVF : 1;\r
+ unsigned char : 1;\r
+ unsigned char PLOVF : 1;\r
+ unsigned char HCOVF : 1;\r
+ unsigned char : 1;\r
+ unsigned char UPLOVF : 1;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char UPLOVF : 1;\r
+ unsigned char : 1;\r
+ unsigned char HCOVF : 1;\r
+ unsigned char PLOVF : 1;\r
+ unsigned char : 1;\r
+ unsigned char MOOVF : 1;\r
+#endif\r
+ } BIT;\r
+ } OSCOVFSR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 8;\r
+ unsigned short CKOSEL : 3;\r
+ unsigned short : 1;\r
+ unsigned short CKODIV : 3;\r
+ unsigned short CKOSTP : 1;\r
+#else\r
+ unsigned short CKOSTP : 1;\r
+ unsigned short CKODIV : 3;\r
+ unsigned short : 1;\r
+ unsigned short CKOSEL : 3;\r
+ unsigned short : 8;\r
+#endif\r
+ } BIT;\r
+ } CKOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char OSTDIE : 1;\r
+ unsigned char : 6;\r
+ unsigned char OSTDE : 1;\r
+#else\r
+ unsigned char OSTDE : 1;\r
+ unsigned char : 6;\r
+ unsigned char OSTDIE : 1;\r
+#endif\r
+ } BIT;\r
+ } OSTDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char OSTDF : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char OSTDF : 1;\r
+#endif\r
+ } BIT;\r
+ } OSTDSR;\r
+ char wk8[14];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LCDSCLKSEL : 3;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char LCDSCLKSEL : 3;\r
+#endif\r
+ } BIT;\r
+ } LCDSCLKCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LCDSCLKSTP : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char LCDSCLKSTP : 1;\r
+#endif\r
+ } BIT;\r
+ } LCDSCLKCR2;\r
+ char wk9[78];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char OPCM : 3;\r
+ unsigned char : 1;\r
+ unsigned char OPCMTSF : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char OPCMTSF : 1;\r
+ unsigned char : 1;\r
+ unsigned char OPCM : 3;\r
+#endif\r
+ } BIT;\r
+ } OPCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char RSTCKSEL : 3;\r
+ unsigned char : 4;\r
+ unsigned char RSTCKEN : 1;\r
+#else\r
+ unsigned char RSTCKEN : 1;\r
+ unsigned char : 4;\r
+ unsigned char RSTCKSEL : 3;\r
+#endif\r
+ } BIT;\r
+ } RSTCKCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char MSTS : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char MSTS : 5;\r
+#endif\r
+ } BIT;\r
+ } MOSCWTCR;\r
+ char wk10[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char HSTS : 5;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char HSTS : 5;\r
+#endif\r
+ } BIT;\r
+ } HOCOWTCR;\r
+ char wk11[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char SOPCM : 1;\r
+ unsigned char : 3;\r
+ unsigned char SOPCMTSF : 1;\r
+ unsigned char : 3;\r
+#else\r
+ unsigned char : 3;\r
+ unsigned char SOPCMTSF : 1;\r
+ unsigned char : 3;\r
+ unsigned char SOPCM : 1;\r
+#endif\r
+ } BIT;\r
+ } SOPCCR;\r
+ char wk12[21];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char IWDTRF : 1;\r
+ unsigned char : 1;\r
+ unsigned char SWRF : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char SWRF : 1;\r
+ unsigned char : 1;\r
+ unsigned char IWDTRF : 1;\r
+#endif\r
+ } BIT;\r
+ } RSTSR2;\r
+ char wk13[1];\r
+ unsigned short SWRR;\r
+ char wk14[28];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LVD1IDTSEL : 2;\r
+ unsigned char LVD1IRQSEL : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char LVD1IRQSEL : 1;\r
+ unsigned char LVD1IDTSEL : 2;\r
+#endif\r
+ } BIT;\r
+ } LVD1CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LVD1DET : 1;\r
+ unsigned char LVD1MON : 1;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char LVD1MON : 1;\r
+ unsigned char LVD1DET : 1;\r
+#endif\r
+ } BIT;\r
+ } LVD1SR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LVD2IDTSEL : 2;\r
+ unsigned char LVD2IRQSEL : 1;\r
+ unsigned char : 5;\r
+#else\r
+ unsigned char : 5;\r
+ unsigned char LVD2IRQSEL : 1;\r
+ unsigned char LVD2IDTSEL : 2;\r
+#endif\r
+ } BIT;\r
+ } LVD2CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LVD2DET : 1;\r
+ unsigned char LVD2MON : 1;\r
+ unsigned char : 6;\r
+#else\r
+ unsigned char : 6;\r
+ unsigned char LVD2MON : 1;\r
+ unsigned char LVD2DET : 1;\r
+#endif\r
+ } BIT;\r
+ } LVD2SR;\r
+ char wk15[794];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PRC0 : 1;\r
+ unsigned short PRC1 : 1;\r
+ unsigned short PRC2 : 1;\r
+ unsigned short PRC3 : 1;\r
+ unsigned short : 4;\r
+ unsigned short PRKEY : 8;\r
+#else\r
+ unsigned short PRKEY : 8;\r
+ unsigned short : 4;\r
+ unsigned short PRC3 : 1;\r
+ unsigned short PRC2 : 1;\r
+ unsigned short PRC1 : 1;\r
+ unsigned short PRC0 : 1;\r
+#endif\r
+ } BIT;\r
+ } PRCR;\r
+ char wk16[48784];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char PORF : 1;\r
+ unsigned char : 1;\r
+ unsigned char LVD1RF : 1;\r
+ unsigned char LVD2RF : 1;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char LVD2RF : 1;\r
+ unsigned char LVD1RF : 1;\r
+ unsigned char : 1;\r
+ unsigned char PORF : 1;\r
+#endif\r
+ } BIT;\r
+ } RSTSR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CWSF : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char CWSF : 1;\r
+#endif\r
+ } BIT;\r
+ } RSTSR1;\r
+ char wk17[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 5;\r
+ unsigned char MODRV21 : 1;\r
+ unsigned char MOSEL : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char MOSEL : 1;\r
+ unsigned char MODRV21 : 1;\r
+ unsigned char : 5;\r
+#endif\r
+ } BIT;\r
+ } MOFCR;\r
+ char wk18[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 3;\r
+ unsigned char EXVCCINP2 : 1;\r
+ unsigned char : 1;\r
+ unsigned char LVD1E : 1;\r
+ unsigned char LVD2E : 1;\r
+ unsigned char : 1;\r
+#else\r
+ unsigned char : 1;\r
+ unsigned char LVD2E : 1;\r
+ unsigned char LVD1E : 1;\r
+ unsigned char : 1;\r
+ unsigned char EXVCCINP2 : 1;\r
+ unsigned char : 3;\r
+#endif\r
+ } BIT;\r
+ } LVCMPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LVD1LVL : 4;\r
+ unsigned char LVD2LVL : 2;\r
+ unsigned char : 2;\r
+#else\r
+ unsigned char : 2;\r
+ unsigned char LVD2LVL : 2;\r
+ unsigned char LVD1LVL : 4;\r
+#endif\r
+ } BIT;\r
+ } LVDLVLR;\r
+ char wk19[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LVD1RIE : 1;\r
+ unsigned char : 1;\r
+ unsigned char LVD1CMPE : 1;\r
+ unsigned char : 3;\r
+ unsigned char LVD1RI : 1;\r
+ unsigned char LVD1RN : 1;\r
+#else\r
+ unsigned char LVD1RN : 1;\r
+ unsigned char LVD1RI : 1;\r
+ unsigned char : 3;\r
+ unsigned char LVD1CMPE : 1;\r
+ unsigned char : 1;\r
+ unsigned char LVD1RIE : 1;\r
+#endif\r
+ } BIT;\r
+ } LVD1CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char LVD2RIE : 1;\r
+ unsigned char : 1;\r
+ unsigned char LVD2CMPE : 1;\r
+ unsigned char : 3;\r
+ unsigned char LVD2RI : 1;\r
+ unsigned char LVD2RN : 1;\r
+#else\r
+ unsigned char LVD2RN : 1;\r
+ unsigned char LVD2RI : 1;\r
+ unsigned char : 3;\r
+ unsigned char LVD2CMPE : 1;\r
+ unsigned char : 1;\r
+ unsigned char LVD2RIE : 1;\r
+#endif\r
+ } BIT;\r
+ } LVD2CR0;\r
+};\r
+\r
+struct st_temps {\r
+ unsigned char TSCDRL;\r
+ unsigned char TSCDRH;\r
+};\r
+\r
+struct st_tmr0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 3;\r
+ unsigned char CCLR : 2;\r
+ unsigned char OVIE : 1;\r
+ unsigned char CMIEA : 1;\r
+ unsigned char CMIEB : 1;\r
+#else\r
+ unsigned char CMIEB : 1;\r
+ unsigned char CMIEA : 1;\r
+ unsigned char OVIE : 1;\r
+ unsigned char CCLR : 2;\r
+ unsigned char : 3;\r
+#endif\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char OSA : 2;\r
+ unsigned char OSB : 2;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char OSB : 2;\r
+ unsigned char OSA : 2;\r
+#endif\r
+ } BIT;\r
+ } TCSR;\r
+ char wk1[1];\r
+ unsigned char TCORA;\r
+ char wk2[1];\r
+ unsigned char TCORB;\r
+ char wk3[1];\r
+ unsigned char TCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CKS : 3;\r
+ unsigned char CSS : 2;\r
+ unsigned char : 2;\r
+ unsigned char TMRIS : 1;\r
+#else\r
+ unsigned char TMRIS : 1;\r
+ unsigned char : 2;\r
+ unsigned char CSS : 2;\r
+ unsigned char CKS : 3;\r
+#endif\r
+ } BIT;\r
+ } TCCR;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char TCS : 1;\r
+ unsigned char : 7;\r
+#else\r
+ unsigned char : 7;\r
+ unsigned char TCS : 1;\r
+#endif\r
+ } BIT;\r
+ } TCSTR;\r
+};\r
+\r
+struct st_tmr1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char : 3;\r
+ unsigned char CCLR : 2;\r
+ unsigned char OVIE : 1;\r
+ unsigned char CMIEA : 1;\r
+ unsigned char CMIEB : 1;\r
+#else\r
+ unsigned char CMIEB : 1;\r
+ unsigned char CMIEA : 1;\r
+ unsigned char OVIE : 1;\r
+ unsigned char CCLR : 2;\r
+ unsigned char : 3;\r
+#endif\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char OSA : 2;\r
+ unsigned char OSB : 2;\r
+ unsigned char : 4;\r
+#else\r
+ unsigned char : 4;\r
+ unsigned char OSB : 2;\r
+ unsigned char OSA : 2;\r
+#endif\r
+ } BIT;\r
+ } TCSR;\r
+ char wk1[1];\r
+ unsigned char TCORA;\r
+ char wk2[1];\r
+ unsigned char TCORB;\r
+ char wk3[1];\r
+ unsigned char TCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned char CKS : 3;\r
+ unsigned char CSS : 2;\r
+ unsigned char : 2;\r
+ unsigned char TMRIS : 1;\r
+#else\r
+ unsigned char TMRIS : 1;\r
+ unsigned char : 2;\r
+ unsigned char CSS : 2;\r
+ unsigned char CKS : 3;\r
+#endif\r
+ } BIT;\r
+ } TCCR;\r
+};\r
+\r
+struct st_tmr01 {\r
+ unsigned short TCORA;\r
+ unsigned short TCORB;\r
+ unsigned short TCNT;\r
+ unsigned short TCCR;\r
+};\r
+\r
+struct st_usb0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short USBE : 1;\r
+ unsigned short : 2;\r
+ unsigned short DMRPU : 1;\r
+ unsigned short DPRPU : 1;\r
+ unsigned short DRPD : 1;\r
+ unsigned short DCFM : 1;\r
+ unsigned short : 1;\r
+ unsigned short CNEN : 1;\r
+ unsigned short : 1;\r
+ unsigned short SCKE : 1;\r
+ unsigned short : 5;\r
+#else\r
+ unsigned short : 5;\r
+ unsigned short SCKE : 1;\r
+ unsigned short : 1;\r
+ unsigned short CNEN : 1;\r
+ unsigned short : 1;\r
+ unsigned short DCFM : 1;\r
+ unsigned short DRPD : 1;\r
+ unsigned short DPRPU : 1;\r
+ unsigned short DMRPU : 1;\r
+ unsigned short : 2;\r
+ unsigned short USBE : 1;\r
+#endif\r
+ } BIT;\r
+ } SYSCFG;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short LNST : 2;\r
+ unsigned short IDMON : 1;\r
+ unsigned short : 3;\r
+ unsigned short HTACT : 1;\r
+ unsigned short : 7;\r
+ unsigned short OVCMON : 2;\r
+#else\r
+ unsigned short OVCMON : 2;\r
+ unsigned short : 7;\r
+ unsigned short HTACT : 1;\r
+ unsigned short : 3;\r
+ unsigned short IDMON : 1;\r
+ unsigned short LNST : 2;\r
+#endif\r
+ } BIT;\r
+ } SYSSTS0;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short RHST : 3;\r
+ unsigned short : 1;\r
+ unsigned short UACT : 1;\r
+ unsigned short RESUME : 1;\r
+ unsigned short USBRST : 1;\r
+ unsigned short RWUPE : 1;\r
+ unsigned short WKUP : 1;\r
+ unsigned short VBUSEN : 1;\r
+ unsigned short EXICEN : 1;\r
+ unsigned short HNPBTOA : 1;\r
+ unsigned short : 4;\r
+#else\r
+ unsigned short : 4;\r
+ unsigned short HNPBTOA : 1;\r
+ unsigned short EXICEN : 1;\r
+ unsigned short VBUSEN : 1;\r
+ unsigned short WKUP : 1;\r
+ unsigned short RWUPE : 1;\r
+ unsigned short USBRST : 1;\r
+ unsigned short RESUME : 1;\r
+ unsigned short UACT : 1;\r
+ unsigned short : 1;\r
+ unsigned short RHST : 3;\r
+#endif\r
+ } BIT;\r
+ } DVSTCTR0;\r
+ char wk2[10];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } CFIFO;\r
+ char wk3[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D0FIFO;\r
+ char wk4[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D1FIFO;\r
+ char wk5[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CURPIPE : 4;\r
+ unsigned short : 1;\r
+ unsigned short ISEL : 1;\r
+ unsigned short : 2;\r
+ unsigned short BIGEND : 1;\r
+ unsigned short : 1;\r
+ unsigned short MBW : 1;\r
+ unsigned short : 3;\r
+ unsigned short REW : 1;\r
+ unsigned short RCNT : 1;\r
+#else\r
+ unsigned short RCNT : 1;\r
+ unsigned short REW : 1;\r
+ unsigned short : 3;\r
+ unsigned short MBW : 1;\r
+ unsigned short : 1;\r
+ unsigned short BIGEND : 1;\r
+ unsigned short : 2;\r
+ unsigned short ISEL : 1;\r
+ unsigned short : 1;\r
+ unsigned short CURPIPE : 4;\r
+#endif\r
+ } BIT;\r
+ } CFIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short DTLN : 9;\r
+ unsigned short : 4;\r
+ unsigned short FRDY : 1;\r
+ unsigned short BCLR : 1;\r
+ unsigned short BVAL : 1;\r
+#else\r
+ unsigned short BVAL : 1;\r
+ unsigned short BCLR : 1;\r
+ unsigned short FRDY : 1;\r
+ unsigned short : 4;\r
+ unsigned short DTLN : 9;\r
+#endif\r
+ } BIT;\r
+ } CFIFOCTR;\r
+ char wk6[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CURPIPE : 4;\r
+ unsigned short : 4;\r
+ unsigned short BIGEND : 1;\r
+ unsigned short : 1;\r
+ unsigned short MBW : 1;\r
+ unsigned short : 1;\r
+ unsigned short DREQE : 1;\r
+ unsigned short DCLRM : 1;\r
+ unsigned short REW : 1;\r
+ unsigned short RCNT : 1;\r
+#else\r
+ unsigned short RCNT : 1;\r
+ unsigned short REW : 1;\r
+ unsigned short DCLRM : 1;\r
+ unsigned short DREQE : 1;\r
+ unsigned short : 1;\r
+ unsigned short MBW : 1;\r
+ unsigned short : 1;\r
+ unsigned short BIGEND : 1;\r
+ unsigned short : 4;\r
+ unsigned short CURPIPE : 4;\r
+#endif\r
+ } BIT;\r
+ } D0FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short DTLN : 9;\r
+ unsigned short : 4;\r
+ unsigned short FRDY : 1;\r
+ unsigned short BCLR : 1;\r
+ unsigned short BVAL : 1;\r
+#else\r
+ unsigned short BVAL : 1;\r
+ unsigned short BCLR : 1;\r
+ unsigned short FRDY : 1;\r
+ unsigned short : 4;\r
+ unsigned short DTLN : 9;\r
+#endif\r
+ } BIT;\r
+ } D0FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CURPIPE : 4;\r
+ unsigned short : 4;\r
+ unsigned short BIGEND : 1;\r
+ unsigned short : 1;\r
+ unsigned short MBW : 1;\r
+ unsigned short : 1;\r
+ unsigned short DREQE : 1;\r
+ unsigned short DCLRM : 1;\r
+ unsigned short REW : 1;\r
+ unsigned short RCNT : 1;\r
+#else\r
+ unsigned short RCNT : 1;\r
+ unsigned short REW : 1;\r
+ unsigned short DCLRM : 1;\r
+ unsigned short DREQE : 1;\r
+ unsigned short : 1;\r
+ unsigned short MBW : 1;\r
+ unsigned short : 1;\r
+ unsigned short BIGEND : 1;\r
+ unsigned short : 4;\r
+ unsigned short CURPIPE : 4;\r
+#endif\r
+ } BIT;\r
+ } D1FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short DTLN : 9;\r
+ unsigned short : 4;\r
+ unsigned short FRDY : 1;\r
+ unsigned short BCLR : 1;\r
+ unsigned short BVAL : 1;\r
+#else\r
+ unsigned short BVAL : 1;\r
+ unsigned short BCLR : 1;\r
+ unsigned short FRDY : 1;\r
+ unsigned short : 4;\r
+ unsigned short DTLN : 9;\r
+#endif\r
+ } BIT;\r
+ } D1FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 8;\r
+ unsigned short BRDYE : 1;\r
+ unsigned short NRDYE : 1;\r
+ unsigned short BEMPE : 1;\r
+ unsigned short CTRE : 1;\r
+ unsigned short DVSE : 1;\r
+ unsigned short SOFE : 1;\r
+ unsigned short RSME : 1;\r
+ unsigned short VBSE : 1;\r
+#else\r
+ unsigned short VBSE : 1;\r
+ unsigned short RSME : 1;\r
+ unsigned short SOFE : 1;\r
+ unsigned short DVSE : 1;\r
+ unsigned short CTRE : 1;\r
+ unsigned short BEMPE : 1;\r
+ unsigned short NRDYE : 1;\r
+ unsigned short BRDYE : 1;\r
+ unsigned short : 8;\r
+#endif\r
+ } BIT;\r
+ } INTENB0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PDDETINTE0 : 1;\r
+ unsigned short : 3;\r
+ unsigned short SACKE : 1;\r
+ unsigned short SIGNE : 1;\r
+ unsigned short EOFERRE : 1;\r
+ unsigned short : 4;\r
+ unsigned short ATTCHE : 1;\r
+ unsigned short DTCHE : 1;\r
+ unsigned short : 1;\r
+ unsigned short BCHGE : 1;\r
+ unsigned short OVRCRE : 1;\r
+#else\r
+ unsigned short OVRCRE : 1;\r
+ unsigned short BCHGE : 1;\r
+ unsigned short : 1;\r
+ unsigned short DTCHE : 1;\r
+ unsigned short ATTCHE : 1;\r
+ unsigned short : 4;\r
+ unsigned short EOFERRE : 1;\r
+ unsigned short SIGNE : 1;\r
+ unsigned short SACKE : 1;\r
+ unsigned short : 3;\r
+ unsigned short PDDETINTE0 : 1;\r
+#endif\r
+ } BIT;\r
+ } INTENB1;\r
+ char wk7[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PIPE0BRDYE : 1;\r
+ unsigned short PIPE1BRDYE : 1;\r
+ unsigned short PIPE2BRDYE : 1;\r
+ unsigned short PIPE3BRDYE : 1;\r
+ unsigned short PIPE4BRDYE : 1;\r
+ unsigned short PIPE5BRDYE : 1;\r
+ unsigned short PIPE6BRDYE : 1;\r
+ unsigned short PIPE7BRDYE : 1;\r
+ unsigned short PIPE8BRDYE : 1;\r
+ unsigned short PIPE9BRDYE : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short PIPE9BRDYE : 1;\r
+ unsigned short PIPE8BRDYE : 1;\r
+ unsigned short PIPE7BRDYE : 1;\r
+ unsigned short PIPE6BRDYE : 1;\r
+ unsigned short PIPE5BRDYE : 1;\r
+ unsigned short PIPE4BRDYE : 1;\r
+ unsigned short PIPE3BRDYE : 1;\r
+ unsigned short PIPE2BRDYE : 1;\r
+ unsigned short PIPE1BRDYE : 1;\r
+ unsigned short PIPE0BRDYE : 1;\r
+#endif\r
+ } BIT;\r
+ } BRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PIPE0NRDYE : 1;\r
+ unsigned short PIPE1NRDYE : 1;\r
+ unsigned short PIPE2NRDYE : 1;\r
+ unsigned short PIPE3NRDYE : 1;\r
+ unsigned short PIPE4NRDYE : 1;\r
+ unsigned short PIPE5NRDYE : 1;\r
+ unsigned short PIPE6NRDYE : 1;\r
+ unsigned short PIPE7NRDYE : 1;\r
+ unsigned short PIPE8NRDYE : 1;\r
+ unsigned short PIPE9NRDYE : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short PIPE9NRDYE : 1;\r
+ unsigned short PIPE8NRDYE : 1;\r
+ unsigned short PIPE7NRDYE : 1;\r
+ unsigned short PIPE6NRDYE : 1;\r
+ unsigned short PIPE5NRDYE : 1;\r
+ unsigned short PIPE4NRDYE : 1;\r
+ unsigned short PIPE3NRDYE : 1;\r
+ unsigned short PIPE2NRDYE : 1;\r
+ unsigned short PIPE1NRDYE : 1;\r
+ unsigned short PIPE0NRDYE : 1;\r
+#endif\r
+ } BIT;\r
+ } NRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PIPE0BEMPE : 1;\r
+ unsigned short PIPE1BEMPE : 1;\r
+ unsigned short PIPE2BEMPE : 1;\r
+ unsigned short PIPE3BEMPE : 1;\r
+ unsigned short PIPE4BEMPE : 1;\r
+ unsigned short PIPE5BEMPE : 1;\r
+ unsigned short PIPE6BEMPE : 1;\r
+ unsigned short PIPE7BEMPE : 1;\r
+ unsigned short PIPE8BEMPE : 1;\r
+ unsigned short PIPE9BEMPE : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short PIPE9BEMPE : 1;\r
+ unsigned short PIPE8BEMPE : 1;\r
+ unsigned short PIPE7BEMPE : 1;\r
+ unsigned short PIPE6BEMPE : 1;\r
+ unsigned short PIPE5BEMPE : 1;\r
+ unsigned short PIPE4BEMPE : 1;\r
+ unsigned short PIPE3BEMPE : 1;\r
+ unsigned short PIPE2BEMPE : 1;\r
+ unsigned short PIPE1BEMPE : 1;\r
+ unsigned short PIPE0BEMPE : 1;\r
+#endif\r
+ } BIT;\r
+ } BEMPENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 4;\r
+ unsigned short EDGESTS : 1;\r
+ unsigned short : 1;\r
+ unsigned short BRDYM : 1;\r
+ unsigned short : 1;\r
+ unsigned short TRNENSEL : 1;\r
+ unsigned short : 7;\r
+#else\r
+ unsigned short : 7;\r
+ unsigned short TRNENSEL : 1;\r
+ unsigned short : 1;\r
+ unsigned short BRDYM : 1;\r
+ unsigned short : 1;\r
+ unsigned short EDGESTS : 1;\r
+ unsigned short : 4;\r
+#endif\r
+ } BIT;\r
+ } SOFCFG;\r
+ char wk8[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short CTSQ : 3;\r
+ unsigned short VALID : 1;\r
+ unsigned short DVSQ : 3;\r
+ unsigned short VBSTS : 1;\r
+ unsigned short BRDY : 1;\r
+ unsigned short NRDY : 1;\r
+ unsigned short BEMP : 1;\r
+ unsigned short CTRT : 1;\r
+ unsigned short DVST : 1;\r
+ unsigned short SOFR : 1;\r
+ unsigned short RESM : 1;\r
+ unsigned short VBINT : 1;\r
+#else\r
+ unsigned short VBINT : 1;\r
+ unsigned short RESM : 1;\r
+ unsigned short SOFR : 1;\r
+ unsigned short DVST : 1;\r
+ unsigned short CTRT : 1;\r
+ unsigned short BEMP : 1;\r
+ unsigned short NRDY : 1;\r
+ unsigned short BRDY : 1;\r
+ unsigned short VBSTS : 1;\r
+ unsigned short DVSQ : 3;\r
+ unsigned short VALID : 1;\r
+ unsigned short CTSQ : 3;\r
+#endif\r
+ } BIT;\r
+ } INTSTS0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PDDETINT0 : 1;\r
+ unsigned short : 3;\r
+ unsigned short SACK : 1;\r
+ unsigned short SIGN : 1;\r
+ unsigned short EOFERR : 1;\r
+ unsigned short : 4;\r
+ unsigned short ATTCH : 1;\r
+ unsigned short DTCH : 1;\r
+ unsigned short : 1;\r
+ unsigned short BCHG : 1;\r
+ unsigned short OVRCR : 1;\r
+#else\r
+ unsigned short OVRCR : 1;\r
+ unsigned short BCHG : 1;\r
+ unsigned short : 1;\r
+ unsigned short DTCH : 1;\r
+ unsigned short ATTCH : 1;\r
+ unsigned short : 4;\r
+ unsigned short EOFERR : 1;\r
+ unsigned short SIGN : 1;\r
+ unsigned short SACK : 1;\r
+ unsigned short : 3;\r
+ unsigned short PDDETINT0 : 1;\r
+#endif\r
+ } BIT;\r
+ } INTSTS1;\r
+ char wk9[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PIPE0BRDY : 1;\r
+ unsigned short PIPE1BRDY : 1;\r
+ unsigned short PIPE2BRDY : 1;\r
+ unsigned short PIPE3BRDY : 1;\r
+ unsigned short PIPE4BRDY : 1;\r
+ unsigned short PIPE5BRDY : 1;\r
+ unsigned short PIPE6BRDY : 1;\r
+ unsigned short PIPE7BRDY : 1;\r
+ unsigned short PIPE8BRDY : 1;\r
+ unsigned short PIPE9BRDY : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short PIPE9BRDY : 1;\r
+ unsigned short PIPE8BRDY : 1;\r
+ unsigned short PIPE7BRDY : 1;\r
+ unsigned short PIPE6BRDY : 1;\r
+ unsigned short PIPE5BRDY : 1;\r
+ unsigned short PIPE4BRDY : 1;\r
+ unsigned short PIPE3BRDY : 1;\r
+ unsigned short PIPE2BRDY : 1;\r
+ unsigned short PIPE1BRDY : 1;\r
+ unsigned short PIPE0BRDY : 1;\r
+#endif\r
+ } BIT;\r
+ } BRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PIPE0NRDY : 1;\r
+ unsigned short PIPE1NRDY : 1;\r
+ unsigned short PIPE2NRDY : 1;\r
+ unsigned short PIPE3NRDY : 1;\r
+ unsigned short PIPE4NRDY : 1;\r
+ unsigned short PIPE5NRDY : 1;\r
+ unsigned short PIPE6NRDY : 1;\r
+ unsigned short PIPE7NRDY : 1;\r
+ unsigned short PIPE8NRDY : 1;\r
+ unsigned short PIPE9NRDY : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short PIPE9NRDY : 1;\r
+ unsigned short PIPE8NRDY : 1;\r
+ unsigned short PIPE7NRDY : 1;\r
+ unsigned short PIPE6NRDY : 1;\r
+ unsigned short PIPE5NRDY : 1;\r
+ unsigned short PIPE4NRDY : 1;\r
+ unsigned short PIPE3NRDY : 1;\r
+ unsigned short PIPE2NRDY : 1;\r
+ unsigned short PIPE1NRDY : 1;\r
+ unsigned short PIPE0NRDY : 1;\r
+#endif\r
+ } BIT;\r
+ } NRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PIPE0BEMP : 1;\r
+ unsigned short PIPE1BEMP : 1;\r
+ unsigned short PIPE2BEMP : 1;\r
+ unsigned short PIPE3BEMP : 1;\r
+ unsigned short PIPE4BEMP : 1;\r
+ unsigned short PIPE5BEMP : 1;\r
+ unsigned short PIPE6BEMP : 1;\r
+ unsigned short PIPE7BEMP : 1;\r
+ unsigned short PIPE8BEMP : 1;\r
+ unsigned short PIPE9BEMP : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short PIPE9BEMP : 1;\r
+ unsigned short PIPE8BEMP : 1;\r
+ unsigned short PIPE7BEMP : 1;\r
+ unsigned short PIPE6BEMP : 1;\r
+ unsigned short PIPE5BEMP : 1;\r
+ unsigned short PIPE4BEMP : 1;\r
+ unsigned short PIPE3BEMP : 1;\r
+ unsigned short PIPE2BEMP : 1;\r
+ unsigned short PIPE1BEMP : 1;\r
+ unsigned short PIPE0BEMP : 1;\r
+#endif\r
+ } BIT;\r
+ } BEMPSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short FRNM : 11;\r
+ unsigned short : 3;\r
+ unsigned short CRCE : 1;\r
+ unsigned short OVRN : 1;\r
+#else\r
+ unsigned short OVRN : 1;\r
+ unsigned short CRCE : 1;\r
+ unsigned short : 3;\r
+ unsigned short FRNM : 11;\r
+#endif\r
+ } BIT;\r
+ } FRMNUM;\r
+ char wk10[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short BMREQUESTTYPE : 8;\r
+ unsigned short BREQUEST : 8;\r
+#else\r
+ unsigned short BREQUEST : 8;\r
+ unsigned short BMREQUESTTYPE : 8;\r
+#endif\r
+ } BIT;\r
+ } USBREQ;\r
+ unsigned short USBVAL;\r
+ unsigned short USBINDX;\r
+ unsigned short USBLENG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 4;\r
+ unsigned short DIR : 1;\r
+ unsigned short : 2;\r
+ unsigned short SHTNAK : 1;\r
+ unsigned short : 8;\r
+#else\r
+ unsigned short : 8;\r
+ unsigned short SHTNAK : 1;\r
+ unsigned short : 2;\r
+ unsigned short DIR : 1;\r
+ unsigned short : 4;\r
+#endif\r
+ } BIT;\r
+ } DCPCFG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short MXPS : 7;\r
+ unsigned short : 5;\r
+ unsigned short DEVSEL : 4;\r
+#else\r
+ unsigned short DEVSEL : 4;\r
+ unsigned short : 5;\r
+ unsigned short MXPS : 7;\r
+#endif\r
+ } BIT;\r
+ } DCPMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PID : 2;\r
+ unsigned short CCPL : 1;\r
+ unsigned short : 2;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short : 2;\r
+ unsigned short SUREQCLR : 1;\r
+ unsigned short : 2;\r
+ unsigned short SUREQ : 1;\r
+ unsigned short BSTS : 1;\r
+#else\r
+ unsigned short BSTS : 1;\r
+ unsigned short SUREQ : 1;\r
+ unsigned short : 2;\r
+ unsigned short SUREQCLR : 1;\r
+ unsigned short : 2;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short : 2;\r
+ unsigned short CCPL : 1;\r
+ unsigned short PID : 2;\r
+#endif\r
+ } BIT;\r
+ } DCPCTR;\r
+ char wk11[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PIPESEL : 4;\r
+ unsigned short : 12;\r
+#else\r
+ unsigned short : 12;\r
+ unsigned short PIPESEL : 4;\r
+#endif\r
+ } BIT;\r
+ } PIPESEL;\r
+ char wk12[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short EPNUM : 4;\r
+ unsigned short DIR : 1;\r
+ unsigned short : 2;\r
+ unsigned short SHTNAK : 1;\r
+ unsigned short : 1;\r
+ unsigned short DBLB : 1;\r
+ unsigned short BFRE : 1;\r
+ unsigned short : 3;\r
+ unsigned short TYPE : 2;\r
+#else\r
+ unsigned short TYPE : 2;\r
+ unsigned short : 3;\r
+ unsigned short BFRE : 1;\r
+ unsigned short DBLB : 1;\r
+ unsigned short : 1;\r
+ unsigned short SHTNAK : 1;\r
+ unsigned short : 2;\r
+ unsigned short DIR : 1;\r
+ unsigned short EPNUM : 4;\r
+#endif\r
+ } BIT;\r
+ } PIPECFG;\r
+ char wk13[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short MXPS : 9;\r
+ unsigned short : 3;\r
+ unsigned short DEVSEL : 4;\r
+#else\r
+ unsigned short DEVSEL : 4;\r
+ unsigned short : 3;\r
+ unsigned short MXPS : 9;\r
+#endif\r
+ } BIT;\r
+ } PIPEMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short IITV : 3;\r
+ unsigned short : 9;\r
+ unsigned short IFIS : 1;\r
+ unsigned short : 3;\r
+#else\r
+ unsigned short : 3;\r
+ unsigned short IFIS : 1;\r
+ unsigned short : 9;\r
+ unsigned short IITV : 3;\r
+#endif\r
+ } BIT;\r
+ } PIPEPERI;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PID : 2;\r
+ unsigned short : 3;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short ATREPM : 1;\r
+ unsigned short : 3;\r
+ unsigned short INBUFM : 1;\r
+ unsigned short BSTS : 1;\r
+#else\r
+ unsigned short BSTS : 1;\r
+ unsigned short INBUFM : 1;\r
+ unsigned short : 3;\r
+ unsigned short ATREPM : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short : 3;\r
+ unsigned short PID : 2;\r
+#endif\r
+ } BIT;\r
+ } PIPE1CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PID : 2;\r
+ unsigned short : 3;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short ATREPM : 1;\r
+ unsigned short : 3;\r
+ unsigned short INBUFM : 1;\r
+ unsigned short BSTS : 1;\r
+#else\r
+ unsigned short BSTS : 1;\r
+ unsigned short INBUFM : 1;\r
+ unsigned short : 3;\r
+ unsigned short ATREPM : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short : 3;\r
+ unsigned short PID : 2;\r
+#endif\r
+ } BIT;\r
+ } PIPE2CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PID : 2;\r
+ unsigned short : 3;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short ATREPM : 1;\r
+ unsigned short : 3;\r
+ unsigned short INBUFM : 1;\r
+ unsigned short BSTS : 1;\r
+#else\r
+ unsigned short BSTS : 1;\r
+ unsigned short INBUFM : 1;\r
+ unsigned short : 3;\r
+ unsigned short ATREPM : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short : 3;\r
+ unsigned short PID : 2;\r
+#endif\r
+ } BIT;\r
+ } PIPE3CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PID : 2;\r
+ unsigned short : 3;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short ATREPM : 1;\r
+ unsigned short : 3;\r
+ unsigned short INBUFM : 1;\r
+ unsigned short BSTS : 1;\r
+#else\r
+ unsigned short BSTS : 1;\r
+ unsigned short INBUFM : 1;\r
+ unsigned short : 3;\r
+ unsigned short ATREPM : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short : 3;\r
+ unsigned short PID : 2;\r
+#endif\r
+ } BIT;\r
+ } PIPE4CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PID : 2;\r
+ unsigned short : 3;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short ATREPM : 1;\r
+ unsigned short : 3;\r
+ unsigned short INBUFM : 1;\r
+ unsigned short BSTS : 1;\r
+#else\r
+ unsigned short BSTS : 1;\r
+ unsigned short INBUFM : 1;\r
+ unsigned short : 3;\r
+ unsigned short ATREPM : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short : 3;\r
+ unsigned short PID : 2;\r
+#endif\r
+ } BIT;\r
+ } PIPE5CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PID : 2;\r
+ unsigned short : 3;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short : 5;\r
+ unsigned short BSTS : 1;\r
+#else\r
+ unsigned short BSTS : 1;\r
+ unsigned short : 5;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short : 3;\r
+ unsigned short PID : 2;\r
+#endif\r
+ } BIT;\r
+ } PIPE6CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PID : 2;\r
+ unsigned short : 3;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short : 5;\r
+ unsigned short BSTS : 1;\r
+#else\r
+ unsigned short BSTS : 1;\r
+ unsigned short : 5;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short : 3;\r
+ unsigned short PID : 2;\r
+#endif\r
+ } BIT;\r
+ } PIPE7CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PID : 2;\r
+ unsigned short : 3;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short : 5;\r
+ unsigned short BSTS : 1;\r
+#else\r
+ unsigned short BSTS : 1;\r
+ unsigned short : 5;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short : 3;\r
+ unsigned short PID : 2;\r
+#endif\r
+ } BIT;\r
+ } PIPE8CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short PID : 2;\r
+ unsigned short : 3;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short : 5;\r
+ unsigned short BSTS : 1;\r
+#else\r
+ unsigned short BSTS : 1;\r
+ unsigned short : 5;\r
+ unsigned short ACLRM : 1;\r
+ unsigned short SQCLR : 1;\r
+ unsigned short SQSET : 1;\r
+ unsigned short SQMON : 1;\r
+ unsigned short PBUSY : 1;\r
+ unsigned short : 3;\r
+ unsigned short PID : 2;\r
+#endif\r
+ } BIT;\r
+ } PIPE9CTR;\r
+ char wk14[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 8;\r
+ unsigned short TRCLR : 1;\r
+ unsigned short TRENB : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short TRENB : 1;\r
+ unsigned short TRCLR : 1;\r
+ unsigned short : 8;\r
+#endif\r
+ } BIT;\r
+ } PIPE1TRE;\r
+ unsigned short PIPE1TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 8;\r
+ unsigned short TRCLR : 1;\r
+ unsigned short TRENB : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short TRENB : 1;\r
+ unsigned short TRCLR : 1;\r
+ unsigned short : 8;\r
+#endif\r
+ } BIT;\r
+ } PIPE2TRE;\r
+ unsigned short PIPE2TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 8;\r
+ unsigned short TRCLR : 1;\r
+ unsigned short TRENB : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short TRENB : 1;\r
+ unsigned short TRCLR : 1;\r
+ unsigned short : 8;\r
+#endif\r
+ } BIT;\r
+ } PIPE3TRE;\r
+ unsigned short PIPE3TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 8;\r
+ unsigned short TRCLR : 1;\r
+ unsigned short TRENB : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short TRENB : 1;\r
+ unsigned short TRCLR : 1;\r
+ unsigned short : 8;\r
+#endif\r
+ } BIT;\r
+ } PIPE4TRE;\r
+ unsigned short PIPE4TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 8;\r
+ unsigned short TRCLR : 1;\r
+ unsigned short TRENB : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short TRENB : 1;\r
+ unsigned short TRCLR : 1;\r
+ unsigned short : 8;\r
+#endif\r
+ } BIT;\r
+ } PIPE5TRE;\r
+ unsigned short PIPE5TRN;\r
+ char wk15[12];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short RPDME0 : 1;\r
+ unsigned short IDPSRCE0 : 1;\r
+ unsigned short IDMSINKE0 : 1;\r
+ unsigned short VDPSRCE0 : 1;\r
+ unsigned short IDPSINKE0 : 1;\r
+ unsigned short VDMSRCE0 : 1;\r
+ unsigned short : 1;\r
+ unsigned short BATCHGE0 : 1;\r
+ unsigned short CHGDETSTS0 : 1;\r
+ unsigned short PDDETSTS0 : 1;\r
+ unsigned short : 6;\r
+#else\r
+ unsigned short : 6;\r
+ unsigned short PDDETSTS0 : 1;\r
+ unsigned short CHGDETSTS0 : 1;\r
+ unsigned short BATCHGE0 : 1;\r
+ unsigned short : 1;\r
+ unsigned short VDMSRCE0 : 1;\r
+ unsigned short IDPSINKE0 : 1;\r
+ unsigned short VDPSRCE0 : 1;\r
+ unsigned short IDMSINKE0 : 1;\r
+ unsigned short IDPSRCE0 : 1;\r
+ unsigned short RPDME0 : 1;\r
+#endif\r
+ } BIT;\r
+ } USBBCCTRL0;\r
+ char wk16[26];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short VDDUSBE : 1;\r
+ unsigned short : 15;\r
+#else\r
+ unsigned short : 15;\r
+ unsigned short VDDUSBE : 1;\r
+#endif\r
+ } BIT;\r
+ } USBMC;\r
+ char wk17[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 6;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 8;\r
+#else\r
+ unsigned short : 8;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 6;\r
+#endif\r
+ } BIT;\r
+ } DEVADD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 6;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 8;\r
+#else\r
+ unsigned short : 8;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 6;\r
+#endif\r
+ } BIT;\r
+ } DEVADD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 6;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 8;\r
+#else\r
+ unsigned short : 8;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 6;\r
+#endif\r
+ } BIT;\r
+ } DEVADD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 6;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 8;\r
+#else\r
+ unsigned short : 8;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 6;\r
+#endif\r
+ } BIT;\r
+ } DEVADD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 6;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 8;\r
+#else\r
+ unsigned short : 8;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 6;\r
+#endif\r
+ } BIT;\r
+ } DEVADD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ \r
+#ifdef __RX_LITTLE_ENDIAN__\r
+ unsigned short : 6;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 8;\r
+#else\r
+ unsigned short : 8;\r
+ unsigned short USBSPD : 2;\r
+ unsigned short : 6;\r
+#endif\r
+ } BIT;\r
+ } DEVADD5;\r
+};\r
+\r
+enum enum_ir {\r
+IR_BSC_BUSERR=16,IR_FCU_FRDYI=23,\r
+IR_ICU_SWINT=27,\r
+IR_CMT0_CMI0,\r
+IR_CMT1_CMI1,\r
+IR_CMT2_CMI2,\r
+IR_CMT3_CMI3,\r
+IR_CAC_FERRF,IR_CAC_MENDF,IR_CAC_OVFF,\r
+IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,\r
+IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,\r
+IR_DOC_DOPCF=57,\r
+IR_CMPB_CMPB0,IR_CMPB_CMPB1,\r
+IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN,\r
+IR_RTC_CUP,\r
+IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,\r
+IR_ELC_ELSR8I=80,\r
+IR_LVD_LVD1=88,IR_LVD_LVD2,\r
+IR_USB0_USBR0,\r
+IR_RTC_ALM=92,IR_RTC_PRD,\r
+IR_S12AD_S12ADI0=102,IR_S12AD_GBADI,\r
+IR_ELC_ELSR18I=106,\r
+IR_SSI0_SSIF0=108,IR_SSI0_SSIRXI0,IR_SSI0_SSITXI0,\r
+IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,\r
+IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,\r
+IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,\r
+IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,\r
+IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,\r
+IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,\r
+IR_POE_OEI1=170,IR_POE_OEI2,\r
+IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0,\r
+IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1,\r
+IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2,\r
+IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3,\r
+IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2,\r
+IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0,\r
+IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,\r
+IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,\r
+IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6,\r
+IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8,\r
+IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9,\r
+IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3,\r
+IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0\r
+};\r
+\r
+enum enum_dtce {\r
+DTCE_ICU_SWINT=27,\r
+DTCE_CMT0_CMI0,\r
+DTCE_CMT1_CMI1,\r
+DTCE_CMT2_CMI2,\r
+DTCE_CMT3_CMI3,\r
+DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,\r
+DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0,\r
+DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1,\r
+DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD,\r
+DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,\r
+DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI,\r
+DTCE_ELC_ELSR18I=106,\r
+DTCE_SSI0_SSIRXI0=109,DTCE_SSI0_SSITXI0,\r
+DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,\r
+DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1,\r
+DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2,\r
+DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,\r
+DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,\r
+DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,\r
+DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0,\r
+DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1,\r
+DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2,\r
+DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3,\r
+DTCE_SCI2_RXI2=187,DTCE_SCI2_TXI2,\r
+DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0,\r
+DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1,\r
+DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5,\r
+DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6,\r
+DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8,\r
+DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9,\r
+DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12,\r
+DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0\r
+};\r
+\r
+enum enum_ier {\r
+IER_BSC_BUSERR=0x02,\r
+IER_FCU_FRDYI=0x02,\r
+IER_ICU_SWINT=0x03,\r
+IER_CMT0_CMI0=0x03,\r
+IER_CMT1_CMI1=0x03,\r
+IER_CMT2_CMI2=0x03,\r
+IER_CMT3_CMI3=0x03,\r
+IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04,\r
+IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,\r
+IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,\r
+IER_DOC_DOPCF=0x07,\r
+IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07,\r
+IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07,\r
+IER_RTC_CUP=0x07,\r
+IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,\r
+IER_ELC_ELSR8I=0x0A,\r
+IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B,\r
+IER_USB0_USBR0=0x0B,\r
+IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B,\r
+IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C,\r
+IER_ELC_ELSR18I=0x0D,\r
+IER_SSI0_SSIF0=0x0D,IER_SSI0_SSIRXI0=0x0D,IER_SSI0_SSITXI0=0x0D,\r
+IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,\r
+IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,\r
+IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,\r
+IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,\r
+IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,\r
+IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11,\r
+IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,\r
+IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16,\r
+IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16,\r
+IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16,\r
+IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17,\r
+IER_SCI2_ERI2=0x17,IER_SCI2_RXI2=0x17,IER_SCI2_TXI2=0x17,IER_SCI2_TEI2=0x17,\r
+IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B,\r
+IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,\r
+IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C,\r
+IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C,\r
+IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D,\r
+IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D,\r
+IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E,\r
+IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F\r
+};\r
+\r
+enum enum_ipr {\r
+IPR_BSC_BUSERR=0,\r
+IPR_FCU_FRDYI=2,\r
+IPR_ICU_SWINT=3,\r
+IPR_CMT0_CMI0=4,\r
+IPR_CMT1_CMI1=5,\r
+IPR_CMT2_CMI2=6,\r
+IPR_CMT3_CMI3=7,\r
+IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34,\r
+IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38,\r
+IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44,\r
+IPR_DOC_DOPCF=57,\r
+IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59,\r
+IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60,\r
+IPR_RTC_CUP=63,\r
+IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,\r
+IPR_ELC_ELSR8I=80,\r
+IPR_LVD_LVD1=88,IPR_LVD_LVD2=89,\r
+IPR_USB0_USBR0=90,\r
+IPR_RTC_ALM=92,IPR_RTC_PRD=93,\r
+IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103,\r
+IPR_ELC_ELSR18I=106,\r
+IPR_SSI0_SSIF0=108,IPR_SSI0_SSIRXI0=108,IPR_SSI0_SSITXI0=108,\r
+IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118,\r
+IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123,\r
+IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127,\r
+IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133,\r
+IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138,\r
+IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139,\r
+IPR_POE_OEI1=170,IPR_POE_OEI2=171,\r
+IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174,\r
+IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177,\r
+IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180,\r
+IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183,\r
+IPR_SCI2_ERI2=186,IPR_SCI2_RXI2=186,IPR_SCI2_TXI2=186,IPR_SCI2_TEI2=186,\r
+IPR_SCI0_ERI0=214,IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214,\r
+IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218,\r
+IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222,\r
+IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226,\r
+IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230,\r
+IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234,\r
+IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245,\r
+IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249\r
+};\r
+\r
+#define IEN_BSC_BUSERR IEN0\r
+#define IEN_FCU_FRDYI IEN7\r
+#define IEN_ICU_SWINT IEN3\r
+#define IEN_CMT0_CMI0 IEN4\r
+#define IEN_CMT1_CMI1 IEN5\r
+#define IEN_CMT2_CMI2 IEN6\r
+#define IEN_CMT3_CMI3 IEN7\r
+#define IEN_CAC_FERRF IEN0\r
+#define IEN_CAC_MENDF IEN1\r
+#define IEN_CAC_OVFF IEN2\r
+#define IEN_USB0_D0FIFO0 IEN4\r
+#define IEN_USB0_D1FIFO0 IEN5\r
+#define IEN_USB0_USBI0 IEN6\r
+#define IEN_RSPI0_SPEI0 IEN4\r
+#define IEN_RSPI0_SPRI0 IEN5\r
+#define IEN_RSPI0_SPTI0 IEN6\r
+#define IEN_RSPI0_SPII0 IEN7\r
+#define IEN_DOC_DOPCF IEN1\r
+#define IEN_CMPB_CMPB0 IEN2\r
+#define IEN_CMPB_CMPB1 IEN3\r
+#define IEN_CTSU_CTSUWR IEN4\r
+#define IEN_CTSU_CTSURD IEN5\r
+#define IEN_CTSU_CTSUFN IEN6\r
+#define IEN_RTC_CUP IEN7\r
+#define IEN_ICU_IRQ0 IEN0\r
+#define IEN_ICU_IRQ1 IEN1\r
+#define IEN_ICU_IRQ2 IEN2\r
+#define IEN_ICU_IRQ3 IEN3\r
+#define IEN_ICU_IRQ4 IEN4\r
+#define IEN_ICU_IRQ5 IEN5\r
+#define IEN_ICU_IRQ6 IEN6\r
+#define IEN_ICU_IRQ7 IEN7\r
+#define IEN_ELC_ELSR8I IEN0\r
+#define IEN_LVD_LVD1 IEN0\r
+#define IEN_LVD_LVD2 IEN1\r
+#define IEN_USB0_USBR0 IEN2\r
+#define IEN_RTC_ALM IEN4\r
+#define IEN_RTC_PRD IEN5\r
+#define IEN_S12AD_S12ADI0 IEN6\r
+#define IEN_S12AD_GBADI IEN7\r
+#define IEN_ELC_ELSR18I IEN2\r
+#define IEN_SSI0_SSIF0 IEN4\r
+#define IEN_SSI0_SSIRXI0 IEN5\r
+#define IEN_SSI0_SSITXI0 IEN6\r
+#define IEN_MTU0_TGIA0 IEN2\r
+#define IEN_MTU0_TGIB0 IEN3\r
+#define IEN_MTU0_TGIC0 IEN4\r
+#define IEN_MTU0_TGID0 IEN5\r
+#define IEN_MTU0_TCIV0 IEN6\r
+#define IEN_MTU0_TGIE0 IEN7\r
+#define IEN_MTU0_TGIF0 IEN0\r
+#define IEN_MTU1_TGIA1 IEN1\r
+#define IEN_MTU1_TGIB1 IEN2\r
+#define IEN_MTU1_TCIV1 IEN3\r
+#define IEN_MTU1_TCIU1 IEN4\r
+#define IEN_MTU2_TGIA2 IEN5\r
+#define IEN_MTU2_TGIB2 IEN6\r
+#define IEN_MTU2_TCIV2 IEN7\r
+#define IEN_MTU2_TCIU2 IEN0\r
+#define IEN_MTU3_TGIA3 IEN1\r
+#define IEN_MTU3_TGIB3 IEN2\r
+#define IEN_MTU3_TGIC3 IEN3\r
+#define IEN_MTU3_TGID3 IEN4\r
+#define IEN_MTU3_TCIV3 IEN5\r
+#define IEN_MTU4_TGIA4 IEN6\r
+#define IEN_MTU4_TGIB4 IEN7\r
+#define IEN_MTU4_TGIC4 IEN0\r
+#define IEN_MTU4_TGID4 IEN1\r
+#define IEN_MTU4_TCIV4 IEN2\r
+#define IEN_MTU5_TGIU5 IEN3\r
+#define IEN_MTU5_TGIV5 IEN4\r
+#define IEN_MTU5_TGIW5 IEN5\r
+#define IEN_POE_OEI1 IEN2\r
+#define IEN_POE_OEI2 IEN3\r
+#define IEN_TMR0_CMIA0 IEN6\r
+#define IEN_TMR0_CMIB0 IEN7\r
+#define IEN_TMR0_OVI0 IEN0\r
+#define IEN_TMR1_CMIA1 IEN1\r
+#define IEN_TMR1_CMIB1 IEN2\r
+#define IEN_TMR1_OVI1 IEN3\r
+#define IEN_TMR2_CMIA2 IEN4\r
+#define IEN_TMR2_CMIB2 IEN5\r
+#define IEN_TMR2_OVI2 IEN6\r
+#define IEN_TMR3_CMIA3 IEN7\r
+#define IEN_TMR3_CMIB3 IEN0\r
+#define IEN_TMR3_OVI3 IEN1\r
+#define IEN_SCI2_ERI2 IEN2\r
+#define IEN_SCI2_RXI2 IEN3\r
+#define IEN_SCI2_TXI2 IEN4\r
+#define IEN_SCI2_TEI2 IEN5\r
+#define IEN_SCI0_ERI0 IEN6\r
+#define IEN_SCI0_RXI0 IEN7\r
+#define IEN_SCI0_TXI0 IEN0\r
+#define IEN_SCI0_TEI0 IEN1\r
+#define IEN_SCI1_ERI1 IEN2\r
+#define IEN_SCI1_RXI1 IEN3\r
+#define IEN_SCI1_TXI1 IEN4\r
+#define IEN_SCI1_TEI1 IEN5\r
+#define IEN_SCI5_ERI5 IEN6\r
+#define IEN_SCI5_RXI5 IEN7\r
+#define IEN_SCI5_TXI5 IEN0\r
+#define IEN_SCI5_TEI5 IEN1\r
+#define IEN_SCI6_ERI6 IEN2\r
+#define IEN_SCI6_RXI6 IEN3\r
+#define IEN_SCI6_TXI6 IEN4\r
+#define IEN_SCI6_TEI6 IEN5\r
+#define IEN_SCI8_ERI8 IEN6\r
+#define IEN_SCI8_RXI8 IEN7\r
+#define IEN_SCI8_TXI8 IEN0\r
+#define IEN_SCI8_TEI8 IEN1\r
+#define IEN_SCI9_ERI9 IEN2\r
+#define IEN_SCI9_RXI9 IEN3\r
+#define IEN_SCI9_TXI9 IEN4\r
+#define IEN_SCI9_TEI9 IEN5\r
+#define IEN_SCI12_ERI12 IEN6\r
+#define IEN_SCI12_RXI12 IEN7\r
+#define IEN_SCI12_TXI12 IEN0\r
+#define IEN_SCI12_TEI12 IEN1\r
+#define IEN_SCI12_SCIX0 IEN2\r
+#define IEN_SCI12_SCIX1 IEN3\r
+#define IEN_SCI12_SCIX2 IEN4\r
+#define IEN_SCI12_SCIX3 IEN5\r
+#define IEN_RIIC0_EEI0 IEN6\r
+#define IEN_RIIC0_RXI0 IEN7\r
+#define IEN_RIIC0_TXI0 IEN0\r
+#define IEN_RIIC0_TEI0 IEN1\r
+\r
+#define VECT_BSC_BUSERR 16\r
+#define VECT_FCU_FRDYI 23\r
+#define VECT_ICU_SWINT 27\r
+#define VECT_CMT0_CMI0 28\r
+#define VECT_CMT1_CMI1 29\r
+#define VECT_CMT2_CMI2 30\r
+#define VECT_CMT3_CMI3 31\r
+#define VECT_CAC_FERRF 32\r
+#define VECT_CAC_MENDF 33\r
+#define VECT_CAC_OVFF 34\r
+#define VECT_USB0_D0FIFO0 36\r
+#define VECT_USB0_D1FIFO0 37\r
+#define VECT_USB0_USBI0 38\r
+#define VECT_RSPI0_SPEI0 44\r
+#define VECT_RSPI0_SPRI0 45\r
+#define VECT_RSPI0_SPTI0 46\r
+#define VECT_RSPI0_SPII0 47\r
+#define VECT_DOC_DOPCF 57\r
+#define VECT_CMPB_CMPB0 58\r
+#define VECT_CMPB_CMPB1 59\r
+#define VECT_CTSU_CTSUWR 60\r
+#define VECT_CTSU_CTSURD 61\r
+#define VECT_CTSU_CTSUFN 62\r
+#define VECT_RTC_CUP 63\r
+#define VECT_ICU_IRQ0 64\r
+#define VECT_ICU_IRQ1 65\r
+#define VECT_ICU_IRQ2 66\r
+#define VECT_ICU_IRQ3 67\r
+#define VECT_ICU_IRQ4 68\r
+#define VECT_ICU_IRQ5 69\r
+#define VECT_ICU_IRQ6 70\r
+#define VECT_ICU_IRQ7 71\r
+#define VECT_ELC_ELSR8I 80\r
+#define VECT_LVD_LVD1 88\r
+#define VECT_LVD_LVD2 89\r
+#define VECT_USB0_USBR0 90\r
+#define VECT_RTC_ALM 92\r
+#define VECT_RTC_PRD 93\r
+#define VECT_S12AD_S12ADI0 102\r
+#define VECT_S12AD_GBADI 103\r
+#define VECT_ELC_ELSR18I 106\r
+#define VECT_SSI0_SSIF0 108\r
+#define VECT_SSI0_SSIRXI0 109\r
+#define VECT_SSI0_SSITXI0 110\r
+#define VECT_MTU0_TGIA0 114\r
+#define VECT_MTU0_TGIB0 115\r
+#define VECT_MTU0_TGIC0 116\r
+#define VECT_MTU0_TGID0 117\r
+#define VECT_MTU0_TCIV0 118\r
+#define VECT_MTU0_TGIE0 119\r
+#define VECT_MTU0_TGIF0 120\r
+#define VECT_MTU1_TGIA1 121\r
+#define VECT_MTU1_TGIB1 122\r
+#define VECT_MTU1_TCIV1 123\r
+#define VECT_MTU1_TCIU1 124\r
+#define VECT_MTU2_TGIA2 125\r
+#define VECT_MTU2_TGIB2 126\r
+#define VECT_MTU2_TCIV2 127\r
+#define VECT_MTU2_TCIU2 128\r
+#define VECT_MTU3_TGIA3 129\r
+#define VECT_MTU3_TGIB3 130\r
+#define VECT_MTU3_TGIC3 131\r
+#define VECT_MTU3_TGID3 132\r
+#define VECT_MTU3_TCIV3 133\r
+#define VECT_MTU4_TGIA4 134\r
+#define VECT_MTU4_TGIB4 135\r
+#define VECT_MTU4_TGIC4 136\r
+#define VECT_MTU4_TGID4 137\r
+#define VECT_MTU4_TCIV4 138\r
+#define VECT_MTU5_TGIU5 139\r
+#define VECT_MTU5_TGIV5 140\r
+#define VECT_MTU5_TGIW5 141\r
+#define VECT_POE_OEI1 170\r
+#define VECT_POE_OEI2 171\r
+#define VECT_TMR0_CMIA0 174\r
+#define VECT_TMR0_CMIB0 175\r
+#define VECT_TMR0_OVI0 176\r
+#define VECT_TMR1_CMIA1 177\r
+#define VECT_TMR1_CMIB1 178\r
+#define VECT_TMR1_OVI1 179\r
+#define VECT_TMR2_CMIA2 180\r
+#define VECT_TMR2_CMIB2 181\r
+#define VECT_TMR2_OVI2 182\r
+#define VECT_TMR3_CMIA3 183\r
+#define VECT_TMR3_CMIB3 184\r
+#define VECT_TMR3_OVI3 185\r
+#define VECT_SCI2_ERI2 186\r
+#define VECT_SCI2_RXI2 187\r
+#define VECT_SCI2_TXI2 188\r
+#define VECT_SCI2_TEI2 189\r
+#define VECT_SCI0_ERI0 214\r
+#define VECT_SCI0_RXI0 215\r
+#define VECT_SCI0_TXI0 216\r
+#define VECT_SCI0_TEI0 217\r
+#define VECT_SCI1_ERI1 218\r
+#define VECT_SCI1_RXI1 219\r
+#define VECT_SCI1_TXI1 220\r
+#define VECT_SCI1_TEI1 221\r
+#define VECT_SCI5_ERI5 222\r
+#define VECT_SCI5_RXI5 223\r
+#define VECT_SCI5_TXI5 224\r
+#define VECT_SCI5_TEI5 225\r
+#define VECT_SCI6_ERI6 226\r
+#define VECT_SCI6_RXI6 227\r
+#define VECT_SCI6_TXI6 228\r
+#define VECT_SCI6_TEI6 229\r
+#define VECT_SCI8_ERI8 230\r
+#define VECT_SCI8_RXI8 231\r
+#define VECT_SCI8_TXI8 232\r
+#define VECT_SCI8_TEI8 233\r
+#define VECT_SCI9_ERI9 234\r
+#define VECT_SCI9_RXI9 235\r
+#define VECT_SCI9_TXI9 236\r
+#define VECT_SCI9_TEI9 237\r
+#define VECT_SCI12_ERI12 238\r
+#define VECT_SCI12_RXI12 239\r
+#define VECT_SCI12_TXI12 240\r
+#define VECT_SCI12_TEI12 241\r
+#define VECT_SCI12_SCIX0 242\r
+#define VECT_SCI12_SCIX1 243\r
+#define VECT_SCI12_SCIX2 244\r
+#define VECT_SCI12_SCIX3 245\r
+#define VECT_RIIC0_EEI0 246\r
+#define VECT_RIIC0_RXI0 247\r
+#define VECT_RIIC0_TXI0 248\r
+#define VECT_RIIC0_TEI0 249\r
+\r
+#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA18\r
+#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17\r
+#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14\r
+#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14\r
+#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
+#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
+#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
+#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
+#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
+#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
+#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23\r
+#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21\r
+#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19\r
+#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17\r
+#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10\r
+#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9\r
+#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6\r
+#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27\r
+#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27\r
+#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26\r
+#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26\r
+#define MSTP_IRDA SYSTEM.MSTPCRC.BIT.MSTPC20\r
+#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19\r
+#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0\r
+#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15\r
+#define MSTP_LCDC SYSTEM.MSTPCRD.BIT.MSTPD11\r
+#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10\r
+\r
+#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR\r
+#define _IR( x ) __IR( x )\r
+#define IR( x , y ) _IR( _ ## x ## _ ## y )\r
+#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE\r
+#define _DTCE( x ) __DTCE( x )\r
+#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )\r
+#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x\r
+#define _IEN( x ) __IEN( x )\r
+#define IEN( x , y ) _IEN( _ ## x ## _ ## y )\r
+#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR\r
+#define _IPR( x ) __IPR( x )\r
+#define IPR( x , y ) _IPR( _ ## x ## _ ## y )\r
+#define __VECT( x ) VECT ## x\r
+#define _VECT( x ) __VECT( x )\r
+#define VECT( x , y ) _VECT( _ ## x ## _ ## y )\r
+#define __MSTP( x ) MSTP ## x\r
+#define _MSTP( x ) __MSTP( x )\r
+#define MSTP( x ) _MSTP( _ ## x )\r
+\r
+#define BSC (*(volatile struct st_bsc *)0x81300)\r
+#define CAC (*(volatile struct st_cac *)0x8B000)\r
+#define CMPB (*(volatile struct st_cmpb *)0x8C580)\r
+#define CMT (*(volatile struct st_cmt *)0x88000)\r
+#define CMT0 (*(volatile struct st_cmt0 *)0x88002)\r
+#define CMT1 (*(volatile struct st_cmt0 *)0x88008)\r
+#define CMT2 (*(volatile struct st_cmt0 *)0x88012)\r
+#define CMT3 (*(volatile struct st_cmt0 *)0x88018)\r
+#define CRC (*(volatile struct st_crc *)0x88280)\r
+#define CTSU (*(volatile struct st_ctsu *)0xA0900)\r
+#define DA (*(volatile struct st_da *)0x88040)\r
+#define DOC (*(volatile struct st_doc *)0x8B080)\r
+#define DTC (*(volatile struct st_dtc *)0x82400)\r
+#define ELC (*(volatile struct st_elc *)0x8B100)\r
+#define FLASH (*(volatile struct st_flash *)0x7FC090)\r
+#define ICU (*(volatile struct st_icu *)0x87000)\r
+#define IRDA (*(volatile struct st_irda *)0x88410)\r
+#define IWDT (*(volatile struct st_iwdt *)0x88030)\r
+#define LCDC (*(volatile struct st_lcdc *)0xA0800)\r
+#define LPT (*(volatile struct st_lpt *)0x800B0)\r
+#define MPC (*(volatile struct st_mpc *)0x8C11F)\r
+#define MTU (*(volatile struct st_mtu *)0x8860A)\r
+#define MTU0 (*(volatile struct st_mtu0 *)0x88690)\r
+#define MTU1 (*(volatile struct st_mtu1 *)0x88690)\r
+#define MTU2 (*(volatile struct st_mtu2 *)0x88692)\r
+#define MTU3 (*(volatile struct st_mtu3 *)0x88600)\r
+#define MTU4 (*(volatile struct st_mtu4 *)0x88600)\r
+#define MTU5 (*(volatile struct st_mtu5 *)0x88694)\r
+#define POE (*(volatile struct st_poe *)0x88900)\r
+#define PORT (*(volatile struct st_port *)0x8C121)\r
+#define PORT0 (*(volatile struct st_port0 *)0x8C000)\r
+#define PORT1 (*(volatile struct st_port1 *)0x8C001)\r
+#define PORT2 (*(volatile struct st_port2 *)0x8C002)\r
+#define PORT3 (*(volatile struct st_port3 *)0x8C003)\r
+#define PORT4 (*(volatile struct st_port4 *)0x8C004)\r
+#define PORT5 (*(volatile struct st_port5 *)0x8C005)\r
+#define PORT9 (*(volatile struct st_port9 *)0x8C009)\r
+#define PORTA (*(volatile struct st_porta *)0x8C00A)\r
+#define PORTB (*(volatile struct st_portb *)0x8C00B)\r
+#define PORTC (*(volatile struct st_portc *)0x8C00C)\r
+#define PORTD (*(volatile struct st_portd *)0x8C00D)\r
+#define PORTE (*(volatile struct st_porte *)0x8C00E)\r
+#define PORTF (*(volatile struct st_portf *)0x8C00F)\r
+#define PORTH (*(volatile struct st_porth *)0x8C051)\r
+#define PORTJ (*(volatile struct st_portj *)0x8C012)\r
+#define RIIC0 (*(volatile struct st_riic *)0x88300)\r
+#define RSPI0 (*(volatile struct st_rspi *)0x88380)\r
+#define RTC (*(volatile struct st_rtc *)0x8C400)\r
+#define RTCB (*(volatile struct st_rtcb *)0x8C402)\r
+#define S12AD (*(volatile struct st_s12ad *)0x89000)\r
+#define SCI0 (*(volatile struct st_sci0 *)0x8A000)\r
+#define SCI1 (*(volatile struct st_sci0 *)0x8A020)\r
+#define SCI2 (*(volatile struct st_sci0 *)0x8A040)\r
+#define SCI5 (*(volatile struct st_sci0 *)0x8A0A0)\r
+#define SCI6 (*(volatile struct st_sci0 *)0x8A0C0)\r
+#define SCI8 (*(volatile struct st_sci0 *)0x8A100)\r
+#define SCI9 (*(volatile struct st_sci0 *)0x8A120)\r
+#define SCI12 (*(volatile struct st_sci12 *)0x8B300)\r
+#define SMCI0 (*(volatile struct st_smci *)0x8A000)\r
+#define SMCI1 (*(volatile struct st_smci *)0x8A020)\r
+#define SMCI2 (*(volatile struct st_smci *)0x8A040)\r
+#define SMCI5 (*(volatile struct st_smci *)0x8A0A0)\r
+#define SMCI6 (*(volatile struct st_smci *)0x8A0C0)\r
+#define SMCI8 (*(volatile struct st_smci *)0x8A100)\r
+#define SMCI9 (*(volatile struct st_smci *)0x8A120)\r
+#define SMCI12 (*(volatile struct st_smci *)0x8B300)\r
+#define SSI0 (*(volatile struct st_ssi *)0x8A500)\r
+#define SYSTEM (*(volatile struct st_system *)0x80000)\r
+#define TEMPS (*(volatile struct st_temps *)0x7FC0AC)\r
+#define TMR0 (*(volatile struct st_tmr0 *)0x88200)\r
+#define TMR1 (*(volatile struct st_tmr1 *)0x88201)\r
+#define TMR2 (*(volatile struct st_tmr0 *)0x88210)\r
+#define TMR3 (*(volatile struct st_tmr1 *)0x88211)\r
+#define TMR01 (*(volatile struct st_tmr01 *)0x88204)\r
+#define TMR23 (*(volatile struct st_tmr01 *)0x88214)\r
+#define USB0 (*(volatile struct st_usb0 *)0xA0000)\r
+\r
+#pragma pack()\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup, standard FreeRTOS hook functions, and the ISR hander called\r
+ * by the RTOS after interrupt entry (including nesting) has been taken care of.\r
+ *\r
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON\r
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO\r
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Renesas includes. */\r
+/* Renesas includes. */\r
+#include <rskrx113def.h>\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_sci.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware as necessary to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ extern void main_blinky( void );\r
+#else\r
+ extern void main_full( void );\r
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Configure the hardware ready to run the demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Set up SCI1 receive buffer */\r
+ R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
+\r
+ /* Enable SCI1 operations */\r
+ R_SCI1_Start();\r
+\r
+ LED0 = LED_OFF;\r
+ LED1 = LED_OFF;\r
+ LED2 = LED_OFF;\r
+ LED3 = LED_OFF;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
+ internally by FreeRTOS API functions that create tasks, queues, software\r
+ timers, and semaphores. The size of the FreeRTOS heap is set by the\r
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeHeapSpace;\r
+\r
+ /* This is just a trivial example of an idle hook. It is called on each\r
+ cycle of the idle task. It must *NOT* attempt to block. In this case the\r
+ idle task just queries the amount of FreeRTOS heap that remains. See the\r
+ memory management section on the http://www.FreeRTOS.org web site for memory\r
+ management options. If there is a lot of heap memory free then the\r
+ configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
+ RAM. */\r
+ xFreeHeapSpace = xPortGetFreeHeapSize();\r
+\r
+ /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
+ ( void ) xFreeHeapSpace;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0\r
+ {\r
+ extern void vFullDemoTickHook( void );\r
+\r
+ vFullDemoTickHook();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The RX port uses this callback function to configure its tick interrupt.\r
+This allows the application to choose the tick interrupt source. */\r
+void vApplicationSetupTimerInterrupt( void )\r
+{\r
+const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL;\r
+\r
+ /* Disable register write protection. */\r
+ SYSTEM.PRCR.WORD = ulEnableRegisterWrite;\r
+\r
+ /* Enable compare match timer 0. */\r
+ MSTP( CMT0 ) = 0;\r
+\r
+ /* Interrupt on compare match. */\r
+ CMT0.CMCR.BIT.CMIE = 1;\r
+\r
+ /* Set the compare match value. */\r
+ CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 );\r
+\r
+ /* Divide the PCLK by 8. */\r
+ CMT0.CMCR.BIT.CKS = 0;\r
+\r
+ /* Enable the interrupt... */\r
+ _IEN( _CMT0_CMI0 ) = 1;\r
+\r
+ /* ...and set its priority to the application defined kernel priority. */\r
+ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;\r
+\r
+ /* Start the timer. */\r
+ CMT.CMSTR0.BIT.STR0 = 1;\r
+\r
+ /* Reneable register protection. */\r
+ SYSTEM.PRCR.WORD = ulDisableRegisterWrite;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __ICCRX__\r
+\r
+ #include <intrinsics.h>\r
+\r
+ /* Called from the C start up code when compiled with IAR. */\r
+ #pragma diag_suppress = Pm011\r
+ int __low_level_init(void)\r
+ #pragma diag_default = Pm011\r
+ {\r
+ extern void R_Systeminit( void );\r
+\r
+ __disable_interrupt();\r
+ R_Systeminit();\r
+\r
+ return (int)(1U);\r
+ }\r
+\r
+#endif /* __ICCRX__ */\r
+\r
+\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only \r
+* intended for use with Renesas products. No other uses are authorized. This \r
+* software is owned by Renesas Electronics Corporation and is protected under \r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING \r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT \r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE \r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR \r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE \r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software \r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : rskrx113def.h\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* H/W Platform : RSKRX113\r
+* Description : Defines macros relating to the RSK user LEDs and switches\r
+* Creation Date: 26/08/2014\r
+*******************************************************************************/\r
+\r
+\r
+#ifndef RSKRX113_H\r
+#define RSKRX113_H\r
+\r
+/*******************************************************************************\r
+User Defines\r
+*******************************************************************************/\r
+/* General Values */\r
+#define LED_ON (0)\r
+#define LED_OFF (1)\r
+#define SET_BIT_HIGH (1)\r
+#define SET_BIT_LOW (0)\r
+#define SET_BYTE_HIGH (0xFF)\r
+#define SET_BYTE_LOW (0x00)\r
+\r
+/* Switches */\r
+#define SW1 (PORTJ.PIDR.BIT.B0)\r
+#define SW2 (PORT3.PIDR.BIT.B2)\r
+#define SW3 (PORT2.PIDR.BIT.B7)\r
+\r
+/* LED port settings */\r
+#define LED0 (PORT2.PODR.BIT.B2)\r
+#define LED1 (PORT2.PODR.BIT.B3)\r
+#define LED2 (PORT2.PODR.BIT.B4)\r
+#define LED3 (PORT2.PODR.BIT.B5)\r
+\r
+\r
+#endif\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="ASCII"?>\r
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+ <sections name="SU">\r
+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4096"/>\r
+ </sections>\r
+ <sections name="SI"/>\r
+ <sections name="B_1"/>\r
+ <sections name="R_1"/>\r
+ <sections name="B_2"/>\r
+ <sections name="R_2"/>\r
+ <sections name="B"/>\r
+ <sections name="R"/>\r
+ <sections name="PResetPRG">\r
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+ </sections>\r
+ <sections name="C_1"/>\r
+ <sections name="C_2"/>\r
+ <sections name="C"/>\r
+ <sections name="C$*"/>\r
+ <sections name="D*"/>\r
+ <sections name="W*"/>\r
+ <sections name="L"/>\r
+ <sections name="PIntPRG"/>\r
+ <sections name="P"/>\r
+ <sections name="FIXEDVECT">\r
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+ <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" name="FIXEDVECT"/>\r
+ </sections>\r
+</com.renesas.linkersection.model:SectionContainer>\r
--- /dev/null
+<?xml version="1.0" encoding="ASCII"?>\r
+<com.renesas.linkersection.model:SectionContainer xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:com.renesas.linkersection.model="http:///LinkerSection.ecore">\r
+ <sections name="SU">\r
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+ <sections name="B_1"/>\r
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+ <sections name="B_2"/>\r
+ <sections name="R_2"/>\r
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+ <sections name="PResetPRG">\r
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+ </sections>\r
+ <sections name="C_1"/>\r
+ <sections name="C_2"/>\r
+ <sections name="C"/>\r
+ <sections name="C$*"/>\r
+ <sections name="D*"/>\r
+ <sections name="W*"/>\r
+ <sections name="L"/>\r
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+ <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294967248"/>\r
+ </sections>\r
+</com.renesas.linkersection.model:SectionContainer>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+ <storageModule moduleId="org.eclipse.cdt.core.settings">\r
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+ <externalSettings/>\r
+ <extensions>\r
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
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+ </extensions>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
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--- /dev/null
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--- /dev/null
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+ </DataElement>\r
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+ </DataElement>\r
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+ </DataElement>\r
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+ </DataElement>\r
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+ </DataElement>\r
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+ </DataElement>\r
+ <DataElement key="mtclkccondition_macroname_macroname_macroname_MacroName" value="">\r
+ </DataElement>\r
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+ </DataElement>\r
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+ </DataElement>\r
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+ <DataElement key="rts5#condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
+ </DataElement>\r
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+ </DataElement>\r
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+ </DataElement>\r
+ <DataElement key="sdacondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
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+ <DataElement key="irq4condition_macroname_MacroName" value="">\r
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+ <DataElement key="ISRName" value="r_cac_mendf_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="OVFF">\r
+ <DataElement key="ISRName" value="r_cac_ovff_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="IRQ7">\r
+ <DataElement key="ISRName" value="r_icu_irq7_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="IRQ6">\r
+ <DataElement key="ISRName" value="r_icu_irq6_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="IRQ5">\r
+ <DataElement key="ISRName" value="r_icu_irq5_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="IRQ4">\r
+ <DataElement key="ISRName" value="r_icu_irq4_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="IRQ3">\r
+ <DataElement key="ISRName" value="r_icu_irq3_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="IRQ2">\r
+ <DataElement key="ISRName" value="r_icu_irq2_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="IRQ1">\r
+ <DataElement key="ISRName" value="r_icu_irq1_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="IRQ0">\r
+ <DataElement key="ISRName" value="r_icu_irq0_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="SWINT">\r
+ <DataElement key="ISRName" value="r_icu_software_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="BUSERR">\r
+ <DataElement key="ISRName" value="r_bsc_buserr_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="OEI2">\r
+ <DataElement key="ISRName" value="r_poe2_oei2_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="OEI1">\r
+ <DataElement key="ISRName" value="r_poe2_oei1_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="CMI0">\r
+ <DataElement key="ISRName" value="r_cmt_cmi0_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="CMI1">\r
+ <DataElement key="ISRName" value="r_cmt_cmi1_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="CMI2">\r
+ <DataElement key="ISRName" value="r_cmt_cmi2_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="CMI3">\r
+ <DataElement key="ISRName" value="r_cmt_cmi3_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="ALM">\r
+ <DataElement key="ISRName" value="r_rtc_alm_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PRD">\r
+ <DataElement key="ISRName" value="r_rtc_prd_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="CUP">\r
+ <DataElement key="ISRName" value="r_rtc_cup_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="CMPB0">\r
+ <DataElement key="ISRName" value="r_cmpb_cmpb0_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="CMPB1">\r
+ <DataElement key="ISRName" value="r_cmpb_cmpb1_interrupt">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="6e598f00-3f67-4caa-b37d-eddbfedf1130">\r
+ <SerializableData name="PinInuse">\r
+ <DataElement key="PinInformationCount" value="100">\r
+ </DataElement>\r
+ <SerializableData name="PinNumber_1">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_2">\r
+ <DataElement key="InusedAs" value="PortJ##PJ0">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_3">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_4">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_5">\r
+ <DataElement key="InusedAs" value="Port2##P25">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_6">\r
+ <DataElement key="InusedAs" value="Port2##P24">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_7">\r
+ <DataElement key="InusedAs" value="Port2##P23">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_8">\r
+ <DataElement key="InusedAs" value="Port2##P22">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_9">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_10">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_11">\r
+ <DataElement key="InusedAs" value="Port2##P27">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_12">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_13">\r
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+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_14">\r
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+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_15">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_16">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_17">\r
+ <DataElement key="InusedAs" value="CGC##XCOUT">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_18">\r
+ <DataElement key="InusedAs" value="CGC##XCIN">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_19">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_20">\r
+ <DataElement key="InusedAs" value="CGC##XTAL">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_21">\r
+ <DataElement key="InusedAs" value="CGC##EXTAL">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_22">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_23">\r
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+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_24">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_25">\r
+ <DataElement key="InusedAs" value="Port3##P32">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_26">\r
+ <DataElement key="InusedAs" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_27">\r
+ <DataElement key="InusedAs" value="SCI1##TXD1">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_28">\r
+ <DataElement key="InusedAs" value="SCI1##RXD1">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_29">\r
+ <DataElement key="InusedAs" value="">\r
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+ </SerializableData>\r
+ <SerializableData name="PinNumber_30">\r
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+ <SerializableData name="PinNumber_31">\r
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+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_32">\r
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+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="PinNumber_33">\r
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+ </SerializableData>\r
+ <SerializableData name="PinNumber_34">\r
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+ </SerializableData>\r
+ <SerializableData name="PinNumber_35">\r
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+ </SerializableData>\r
+ <SerializableData name="PinNumber_36">\r
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+ </SerializableData>\r
+ <SerializableData name="PinNumber_37">\r
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+ <SerializableData name="PinNumber_38">\r
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+ </SerializableData>\r
+ <SerializableData name="PinNumber_39">\r
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+ </SerializableData>\r
+ <SerializableData name="PinNumber_40">\r
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+ <SerializableData name="PinNumber_41">\r
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+ <SerializableData name="PinNumber_42">\r
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+ <SerializableData name="PinNumber_43">\r
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+ <SerializableData name="PinNumber_44">\r
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+ <SerializableData name="PinNumber_45">\r
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+ <SerializableData name="PinNumber_46">\r
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+ <SerializableData name="PinNumber_47">\r
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+ <SerializableData name="PinNumber_48">\r
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+ <SerializableData name="PinNumber_49">\r
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+ <SerializableData name="PinNumber_50">\r
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+ <SerializableData name="PinNumber_51">\r
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+ <SerializableData name="PinNumber_52">\r
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+ <SerializableData name="PinState">\r
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+ </DataElement>\r
+ <SerializableData name="P04">\r
+ <DataElement key="NChannelOpenDrain" value="False">\r
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+ <DataElement key="NoiseFilterFunction" value="False">\r
+ </DataElement>\r
+ <DataElement key="PinInOut" value="IO">\r
+ </DataElement>\r
+ <DataElement key="PullUp" value="False">\r
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+ <DataElement key="TTLBuffer" value="False">\r
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+ </SerializableData>\r
+ <SerializableData name="POE2#">\r
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+ <DataElement key="PinInOut" value="I">\r
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+ </SerializableData>\r
+ <SerializableData name="TMCI3">\r
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+ <DataElement key="TTLBuffer" value="False">\r
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+ </SerializableData>\r
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+ <DataElement key="PinInOut" value="IO">\r
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+ </SerializableData>\r
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+ </SerializableData>\r
+ <SerializableData name="USB0_VBUS">\r
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+ <SerializableData name="USB0_OVRCURB">\r
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+ </SerializableData>\r
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+ </SerializableData>\r
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+ </SerializableData>\r
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+ </SerializableData>\r
+ <SerializableData name="IRQ5">\r
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+ </SerializableData>\r
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+ <DataElement key="PinInOut" value="O">\r
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+ </SerializableData>\r
+ <SerializableData name="UB#">\r
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+ <DataElement key="TTLBuffer" value="False">\r
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+ </SerializableData>\r
+ <SerializableData name="P14">\r
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+ <DataElement key="PinInOut" value="IO">\r
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+ </SerializableData>\r
+ <SerializableData name="DataKey_IWDTCLK">\r
+ <DataElement key="DataValue" value="0">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_CACILCLK">\r
+ <DataElement key="DataValue" value="0">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_CACLCLK">\r
+ <DataElement key="DataValue" value="0">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_CACHCLK">\r
+ <DataElement key="DataValue" value="0">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_CACSCLK">\r
+ <DataElement key="DataValue" value="32768">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_CACMCLK">\r
+ <DataElement key="DataValue" value="16000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_RTCSCLK">\r
+ <DataElement key="DataValue" value="32768">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_MainOSC">\r
+ <DataElement key="DataValue" value="16000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_SubOSC">\r
+ <DataElement key="DataValue" value="32768">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_HOCO">\r
+ <DataElement key="DataValue" value="0">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_LOCO">\r
+ <DataElement key="DataValue" value="0">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_PLL">\r
+ <DataElement key="DataValue" value="1">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_LCDSRCCLK">\r
+ <DataElement key="DataValue" value="0">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_LCDSRC">\r
+ <DataElement key="DataValue" value="0">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_PB0">\r
+ <DataElement key="DataValue" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_PB1">\r
+ <DataElement key="DataValue" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_PB2">\r
+ <DataElement key="DataValue" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_PB3">\r
+ <DataElement key="DataValue" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_PB4">\r
+ <DataElement key="DataValue" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_PB5">\r
+ <DataElement key="DataValue" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_PB6">\r
+ <DataElement key="DataValue" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="DataKey_PB7">\r
+ <DataElement key="DataValue" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="MacroData">\r
+ <SerializableData name="AsynchronousMode_Transmit1">\r
+ <SerializableData name="PCLKB">\r
+ <DataElement key="DataValue" value="32000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="MTIOC1A">\r
+ <DataElement key="DataValue" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="AsynchronousMode_TransmitReceive1">\r
+ <SerializableData name="PCLKB">\r
+ <DataElement key="DataValue" value="32000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="MTIOC1A">\r
+ <DataElement key="DataValue" value="">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="CMT1">\r
+ <SerializableData name="PCLKB">\r
+ <DataElement key="DataValue" value="32000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="CMT0">\r
+ <SerializableData name="PCLKB">\r
+ <DataElement key="DataValue" value="32000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="CMT2">\r
+ <SerializableData name="PCLKB">\r
+ <DataElement key="DataValue" value="32000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="CMT3">\r
+ <SerializableData name="PCLKB">\r
+ <DataElement key="DataValue" value="32000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="TmrChannel0">\r
+ <SerializableData name="PCLKB">\r
+ <DataElement key="DataValue" value="32000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="TmrChannel1">\r
+ <SerializableData name="PCLKB">\r
+ <DataElement key="DataValue" value="32000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="TmrChannel2">\r
+ <SerializableData name="PCLKB">\r
+ <DataElement key="DataValue" value="32000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="TmrChannel3">\r
+ <SerializableData name="PCLKB">\r
+ <DataElement key="DataValue" value="32000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="Tmr0">\r
+ <SerializableData name="PCLKB">\r
+ <DataElement key="DataValue" value="32000">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="238fa7f0-0b4d-4810-8765-43c28724a4e6">\r
+ </SerializableData>\r
+ <SerializableData name="78ccd8bd-f6c2-422f-a681-62d344e94db3">\r
+ <SerializableData name="DeviceTopViewColorSetting">\r
+ <SerializableData name="DeviceTopView">\r
+ <SerializableData name="QfpPinGraph">\r
+ <DataElement key="UnusedPins" value="Black">\r
+ </DataElement>\r
+ <DataElement key="UsedPins" value="Blue">\r
+ </DataElement>\r
+ <DataElement key="WarningPins" value="Orange">\r
+ </DataElement>\r
+ <DataElement key="ConflictPins" value="Red">\r
+ </DataElement>\r
+ <DataElement key="MacroHighLight" value="LightGoldenrodYellow">\r
+ </DataElement>\r
+ <DataElement key="SelectedPin" value="MediumPurple">\r
+ </DataElement>\r
+ </SerializableData>\r
+ <SerializableData name="QfpDeviceGraph">\r
+ <DataElement key="Device" value="Gray">\r
+ </DataElement>\r
+ <DataElement key="DevicePartNum" value="LightGray">\r
+ </DataElement>\r
+ <DataElement key="DeviceGroup" value="LightGray">\r
+ </DataElement>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ </SerializableData>\r
+ <SerializableData name="44ed803d-dded-43f6-8c70-bcc670f78d1b">\r
+ <SerializableData name="CodeGenerator">\r
+ </SerializableData>\r
+ <SerializableData name="PinView">\r
+ </SerializableData>\r
+ <SerializableData name="Fit">\r
+ </SerializableData>\r
+ </SerializableData>\r
+</SerializableData>
\ No newline at end of file
--- /dev/null
+#\r
+#Wed Nov 19 15:44:46 GMT 2014\r
+CGExist=true\r
--- /dev/null
+Build\ project\ excluding\ the\ dependencies=false\r
+Re-generate\ and\ use\ dependencies\ during\ project\ build=true\r
+Use\ existing\ dependencies\ during\ project\ build=false\r
+eclipse.preferences.version=1\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
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+<booleanAttribute key="com.renesas.cdt.core.setStopAt" value="true"/>\r
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+<listAttribute key="com.renesas.cdt.launch.dsf.downloadImages">\r
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+</listAttribute>\r
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+</launchConfiguration>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<launchConfiguration type="com.renesas.cdt.launch.dsf.gdbremote.launchConfigurationType">\r
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+<listAttribute key="com.renesas.cdt.launch.dsf.downloadImages">\r
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+</listAttribute>\r
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+<stringAttribute key="com.renesas.hardwaredebug.e1.jtag.clock.freq" value="16.5"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.jtag.or.fine" value="1"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.le" value="true"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.mode" value="0"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.mode_pin" value="0"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.prog_rewrite_dflash" value="false"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1.prog_rewrite_irom" value="false"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.serial_number" value=""/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1.supply.voltage" value="3.3V"/>\r
+<intAttribute key="com.renesas.hardwaredebug.e1.timer_clock" value="0"/>\r
+<intAttribute key="com.renesas.hardwaredebug.e1.work_ram_start" value="0"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1rl78.communication.method" value="0"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.e1_pwr" value="true"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.eraseFlash" value="true"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.hw_break" value="true"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.le" value="true"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1rl78.main.clock.freq" value="0"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.mask.internal.reset.signal" value="false"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.mask.target.reset.signal" value="false"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1rl78.monitor.clock" value="1"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.permit.flash.programming" value="true"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1rl78.security.id" value="00000000000000000000"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.stopSerialEmu" value="false"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.stopTimerEmu" value="false"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1rl78.sub.clock.freq" value="0"/>\r
+<stringAttribute key="com.renesas.hardwaredebug.e1rl78.supply.voltage" value="0"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.traceEnable" value="false"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.use.wide.voltage.mode" value="true"/>\r
+<booleanAttribute key="com.renesas.hardwaredebug.e1rl78.verify.on.writing.to.memory" value="true"/>\r
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="C:\Users\TallyM\Documents\RSK\RX113 RSK\Samples\DevArea\RTOSDemo\Release\RTOSDemo.abs"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value="0"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="C:\Users\TallyM\Documents\RSK\RX113 RSK\Samples\DevArea\RTOSDemo\Release\RTOSDemo.abs"/>\r
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value="0"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>\r
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${eclipse_home}../DebugComp/rx-elf-gdb"/>\r
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>\r
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>\r
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Release/RTOSDemo.abs"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RTOSDemo"/>\r
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>\r
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">\r
+<listEntry value="/RTOSDemo"/>\r
+</listAttribute>\r
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">\r
+<listEntry value="4"/>\r
+</listAttribute>\r
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>\r
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>\r
+</launchConfiguration>\r
--- /dev/null
+################################################################################\r
+# Automatically-generated file. Do not edit!\r
+################################################################################\r
+\r
+export INC_RX=C:\devtools\Renesas\RX\2_3_0\include
+export RXC_LIB=C:\devtools\Renesas\RX\2_3_0\bin
+export BIN_RX=C:\devtools\Renesas\RX\2_3_0\bin
+PATH := $(PATH):C:\devtools\Renesas\RX\2_3_0\bin
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds...and so on.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles an LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Renesas includes. */\r
+#include <rskrx113def.h>\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_userdefine.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in\r
+ * main.c.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static QueueHandle_t xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ NULL, /* The parameter passed to the task - not used in this case. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+const unsigned long ulExpectedValue = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == ulExpectedValue )\r
+ {\r
+ LED0 = !LED0;\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* Hardware specifics. */\r
+#include "iodefine.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ ( 32000000 ) /* Set in mcu_info.h. */\r
+#define configPERIPHERAL_CLOCK_HZ ( 32000000 ) /* Set in muc_info.h. */\r
+#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+\r
+#define configMAX_PRIORITIES ( 7 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 3 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+\r
+/* The interrupt priority used by the kernel itself for the tick interrupt and\r
+the pended interrupt. This would normally be the lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+\r
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
+Interrupts that use a priority above this will not be effected by anything the\r
+kernel is doing. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros\r
+allow the application writer to add additional code before and after the MCU is\r
+placed into the low power state respectively. The implementations provided in\r
+this demo can be extended to save even more power - for example the analog\r
+input used by the low power demo could be switched off in the pre-sleep macro\r
+and back on again in the post sleep macro. */\r
+void vPreSleepProcessing( unsigned long xExpectedIdleTime );\r
+void vPostSleepProcessing( unsigned long xExpectedIdleTime );\r
+#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime );\r
+#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime );\r
+\r
+/* configTICK_VECTOR must be set to the interrupt vector used by the peripheral\r
+that generates the tick interrupt. */\r
+#define configTICK_VECTOR VECT_CMT0_CMI0\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * This file contains the non-portable and therefore RX62N specific parts of\r
+ * the IntQueue standard demo task - namely the configuration of the timers\r
+ * that generate the interrupts and the interrupt entry points.\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+/* Hardware specifics. */\r
+#include "iodefine.h"\r
+\r
+#define tmrTIMER_0_1_FREQUENCY ( 2000UL )\r
+#define tmrTIMER_2_3_FREQUENCY ( 2407UL )\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+ /* Ensure interrupts do not start until full configuration is complete. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ SYSTEM.PRCR.WORD = 0xa502;\r
+\r
+ /* Cascade two 8bit timer channels to generate the interrupts. \r
+ 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are\r
+ utilised for this test. */\r
+\r
+ /* Enable the timers. */\r
+ SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;\r
+ SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;\r
+\r
+ /* Enable compare match A interrupt request. */\r
+ TMR0.TCR.BIT.CMIEA = 1;\r
+ TMR2.TCR.BIT.CMIEA = 1;\r
+\r
+ /* Clear the timer on compare match A. */\r
+ TMR0.TCR.BIT.CCLR = 1;\r
+ TMR2.TCR.BIT.CCLR = 1;\r
+\r
+ /* Set the compare match value. */\r
+ TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
+ TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
+\r
+ /* 16 bit operation ( count from timer 1,2 ). */\r
+ TMR0.TCCR.BIT.CSS = 3;\r
+ TMR2.TCCR.BIT.CSS = 3;\r
+ \r
+ /* Use PCLK as the input. */\r
+ TMR1.TCCR.BIT.CSS = 1;\r
+ TMR3.TCCR.BIT.CSS = 1;\r
+ \r
+ /* Divide PCLK by 8. */\r
+ TMR1.TCCR.BIT.CKS = 2;\r
+ TMR3.TCCR.BIT.CKS = 2;\r
+\r
+ /* Enable TMR 0, 2 interrupts. */\r
+ TMR0.TCR.BIT.CMIEA = 1;\r
+ TMR2.TCR.BIT.CMIEA = 1;\r
+\r
+ /* Set interrupt priority and enable. */\r
+ IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
+ IR( TMR0, CMIA0 ) = 0U;\r
+ IEN( TMR0, CMIA0 ) = 1U;\r
+\r
+ /* Do the same for TMR2, but to vector 129. */\r
+ IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;\r
+ IR( TMR2, CMIA2 ) = 0U;\r
+ IEN( TMR2, CMIA2 ) = 1U;\r
+ }\r
+ portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma interrupt r_tmr_cmia0_interrupt(vect=VECT(TMR0,CMIA0))\r
+void r_tmr_cmia0_interrupt( void )\r
+{\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#pragma interrupt r_tmr_cmia2_interrupt(vect=VECT(TMR2,CMIA2))\r
+void r_tmr_cmia2_interrupt( void )\r
+{\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+portBASE_TYPE xTimer0Handler( void );\r
+portBASE_TYPE xTimer1Handler( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky\r
+ * style project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to\r
+ * select between the two. See the notes on using\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the\r
+ * comprehensive version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ *\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and software timers, then\r
+ * starts the scheduler. The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" task - The check task period is initially set to three seconds. The\r
+ * task checks that all the standard demo tasks, and the register check tasks,\r
+ * are not only still executing, but are executing without reporting any errors.\r
+ * If the check task discovers that a task has either stalled, or reported an\r
+ * error, then it changes its own execution period from the initial three\r
+ * seconds, to just 200ms. The check task also toggles an LED each time it is\r
+ * called. This provides a visual indication of the system status: If the LED\r
+ * toggles every three seconds, then no issues have been discovered. If the LED\r
+ * toggles every 200ms, then an issue has been discovered with at least one\r
+ * task.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+#include "serial.h"\r
+#include "TimerDemo.h"\r
+#include "QueueOverwrite.h"\r
+#include "IntQueue.h"\r
+#include "EventGroupsDemo.h"\r
+#include "TaskNotify.h"\r
+#include "IntSemTest.h"\r
+\r
+/* Renesas includes. */\r
+#include <rskrx113def.h>\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_userdefine.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )\r
+#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* The priority used by the UART command console task. */\r
+#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )\r
+\r
+/* Parameters that are passed into the register check tasks solely for the\r
+purpose of ensuring parameters are passed into tasks correctly. */\r
+#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL )\r
+#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL )\r
+\r
+/* The base period used by the timer test tasks. */\r
+#define mainTIMER_TEST_PERIOD ( 50 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Entry point for the comprehensive demo (as opposed to the simple blinky\r
+ * demo).\r
+ */\r
+void main_full( void );\r
+\r
+/*\r
+ * The full demo includes some functionality called from the tick hook.\r
+ */\r
+void vFullDemoTickHook( void );\r
+\r
+ /*\r
+ * The check task, as described at the top of this file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the registers, as described at the top of this file. The nature of these\r
+ * files necessitates that they are written in assembly, but the entry points\r
+ * are kept in the C file for the convenience of checking the task parameter.\r
+ */\r
+static void prvRegTest1Task( void *pvParameters );\r
+static void prvRegTest2Task( void *pvParameters );\r
+static void prvRegTest1Implementation( void );\r
+static void prvRegTest2Implementation( void );\r
+\r
+/*\r
+ * A high priority task that does nothing other than execute at a pseudo random\r
+ * time to ensure the other test tasks don't just execute in a repeating\r
+ * pattern.\r
+ */\r
+static void prvPseudoRandomiser( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check task. If the variables keep incrementing,\r
+then the register check tasks have not discovered any errors. If a variable\r
+stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/* String for display in the web server. It is set to an error message if the\r
+check task detects an error. */\r
+const char *pcStatusMessage = "All tasks running without error";\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+ /* Start all the other standard demo/test tasks. They have no particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartInterruptQueueTasks();\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+ vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );\r
+ vStartEventGroupTasks();\r
+ vStartTaskNotifyTask();\r
+ vStartInterruptSemaphoreTasks();\r
+\r
+ /* Create the register check tasks, as described at the top of this file */\r
+ xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the task that just adds a little random behaviour. */\r
+ xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );\r
+\r
+ /* Create the task that performs the 'check' functionality, as described at\r
+ the top of this file. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* The set of tasks created by the following function call have to be\r
+ created last as they keep account of the number of tasks they expect to see\r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was either insufficient FreeRTOS heap memory available for the idle\r
+ and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
+ User mode. See the memory management section on the FreeRTOS web site for\r
+ more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
+ mode from which main() is called is set in the C start up code and must be\r
+ a privileged mode (not user mode). */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
+TickType_t xLastExecutionTime;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
+ works correctly. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. The onboard LED is toggled on each iteration.\r
+ If an error is detected then the delay period is decreased from\r
+ mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
+ effect of increasing the rate at which the onboard LED toggles, and in so\r
+ doing gives visual feedback of the system status. */\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+ if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 0UL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 2UL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 3UL;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 4UL;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 5UL;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 6UL;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 7UL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 8UL;\r
+ }\r
+\r
+ if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )\r
+ {\r
+ ulErrorFound |= 1UL << 9UL;\r
+ }\r
+\r
+ if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 10UL;\r
+ }\r
+\r
+ if( xIsQueueOverwriteTaskStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= 1UL << 11UL;\r
+ }\r
+\r
+ if( xAreEventGroupTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= 1UL << 12UL;\r
+ }\r
+\r
+ if( xAreTaskNotificationTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 13UL;\r
+ }\r
+\r
+ if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound |= 1UL << 14UL;\r
+ }\r
+\r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound |= 1UL << 15UL;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound |= 1UL << 16UL;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ LED0 = !LED0;\r
+\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash the LED\r
+ at a higher frequency to give visible feedback that something has\r
+ gone wrong (it might just be that the loop back connector required\r
+ by the comtest tasks has not been fitted). */\r
+ xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
+ pcStatusMessage = "Error found in at least one task.";\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPseudoRandomiser( void *pvParameters )\r
+{\r
+const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS );\r
+volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;\r
+\r
+ /* This task does nothing other than ensure there is a little bit of\r
+ disruption in the scheduling pattern of the other tasks. Normally this is\r
+ done by generating interrupts at pseudo random times. */\r
+ for( ;; )\r
+ {\r
+ ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;\r
+ ulValue = ( ulNextRand >> 16UL ) & 0xffUL;\r
+\r
+ if( ulValue < ulMinDelay )\r
+ {\r
+ ulValue = ulMinDelay;\r
+ }\r
+\r
+ vTaskDelay( ulValue );\r
+\r
+ while( ulValue > 0 )\r
+ {\r
+ nop();\r
+ nop();\r
+ nop();\r
+ nop();\r
+ nop();\r
+ nop();\r
+ nop();\r
+ nop();\r
+\r
+ ulValue--;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vFullDemoTickHook( void )\r
+{\r
+ /* The full demo includes a software timer demo/test that requires\r
+ prodding periodically from the tick interrupt. */\r
+ vTimerPeriodicISRTests();\r
+\r
+ /* Call the periodic queue overwrite from ISR demo. */\r
+ vQueueOverwritePeriodicISRDemo();\r
+\r
+ /* Call the periodic event group from ISR demo. */\r
+ vPeriodicEventGroupsProcessing();\r
+\r
+ /* Use task notifications from an interrupt. */\r
+ xNotifyTaskFromISR();\r
+\r
+ /* Use mutexes from interrupts. */\r
+ vInterruptSemaphorePeriodicTest();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest1Task( void *pvParameters )\r
+{\r
+ if( pvParameters != mainREG_TEST_1_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ prvRegTest1Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+static void prvRegTest2Task( void *pvParameters )\r
+{\r
+ if( pvParameters != mainREG_TEST_2_PARAMETER )\r
+ {\r
+ /* The parameter did not contain the expected value. */\r
+ for( ;; )\r
+ {\r
+ /* Stop the tick interrupt so its obvious something has gone wrong. */\r
+ taskDISABLE_INTERRUPTS();\r
+ }\r
+ }\r
+\r
+ /* This is an inline asm function that never returns. */\r
+ prvRegTest2Implementation();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+#pragma inline_asm prvRegTest1Implementation\r
+static void prvRegTest1Implementation( void )\r
+{\r
+ ; Put a known value in each register.\r
+ MOV.L #1, R1\r
+ MOV.L #2, R2\r
+ MOV.L #3, R3\r
+ MOV.L #4, R4\r
+ MOV.L #5, R5\r
+ MOV.L #6, R6\r
+ MOV.L #7, R7\r
+ MOV.L #8, R8\r
+ MOV.L #9, R9\r
+ MOV.L #10, R10\r
+ MOV.L #11, R11\r
+ MOV.L #12, R12\r
+ MOV.L #13, R13\r
+ MOV.L #14, R14\r
+ MOV.L #15, R15\r
+\r
+ ; Loop, checking each itteration that each register still contains the\r
+ ; expected value.\r
+TestLoop1:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest1LoopCounter, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register.\r
+ MOV.L #1, R14\r
+ MOV.L #0872E0H, R15\r
+ MOV.B R14, [R15]\r
+ NOP\r
+ NOP\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ ; Now compare each register to ensure it still contains the value that was\r
+ ; set before this loop was entered.\r
+ CMP #1, R1\r
+ BNE RegTest1Error\r
+ CMP #2, R2\r
+ BNE RegTest1Error\r
+ CMP #3, R3\r
+ BNE RegTest1Error\r
+ CMP #4, R4\r
+ BNE RegTest1Error\r
+ CMP #5, R5\r
+ BNE RegTest1Error\r
+ CMP #6, R6\r
+ BNE RegTest1Error\r
+ CMP #7, R7\r
+ BNE RegTest1Error\r
+ CMP #8, R8\r
+ BNE RegTest1Error\r
+ CMP #9, R9\r
+ BNE RegTest1Error\r
+ CMP #10, R10\r
+ BNE RegTest1Error\r
+ CMP #11, R11\r
+ BNE RegTest1Error\r
+ CMP #12, R12\r
+ BNE RegTest1Error\r
+ CMP #13, R13\r
+ BNE RegTest1Error\r
+ CMP #14, R14\r
+ BNE RegTest1Error\r
+ CMP #15, R15\r
+ BNE RegTest1Error\r
+\r
+ ; All comparisons passed, start a new itteratio of this loop.\r
+ BRA TestLoop1\r
+\r
+RegTest1Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; causing the check task to indicate the error.\r
+ BRA RegTest1Error\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of this file. */\r
+#pragma inline_asm prvRegTest2Implementation\r
+static void prvRegTest2Implementation( void )\r
+{\r
+ ; Put a known value in each register.\r
+ MOV.L #10, R1\r
+ MOV.L #20, R2\r
+ MOV.L #30, R3\r
+ MOV.L #40, R4\r
+ MOV.L #50, R5\r
+ MOV.L #60, R6\r
+ MOV.L #70, R7\r
+ MOV.L #80, R8\r
+ MOV.L #90, R9\r
+ MOV.L #100, R10\r
+ MOV.L #110, R11\r
+ MOV.L #120, R12\r
+ MOV.L #130, R13\r
+ MOV.L #140, R14\r
+ MOV.L #150, R15\r
+\r
+ ; Loop, checking on each itteration that each register still contains the\r
+ ; expected value.\r
+TestLoop2:\r
+\r
+ ; Push the registers that are going to get clobbered.\r
+ PUSHM R14-R15\r
+\r
+ ; Increment the loop counter to show this task is still getting CPU time.\r
+ MOV.L #_ulRegTest2LoopCounter, R14\r
+ MOV.L [ R14 ], R15\r
+ ADD #1, R15\r
+ MOV.L R15, [ R14 ]\r
+\r
+ ; Restore the clobbered registers.\r
+ POPM R14-R15\r
+\r
+ CMP #10, R1\r
+ BNE RegTest2Error\r
+ CMP #20, R2\r
+ BNE RegTest2Error\r
+ CMP #30, R3\r
+ BNE RegTest2Error\r
+ CMP #40, R4\r
+ BNE RegTest2Error\r
+ CMP #50, R5\r
+ BNE RegTest2Error\r
+ CMP #60, R6\r
+ BNE RegTest2Error\r
+ CMP #70, R7\r
+ BNE RegTest2Error\r
+ CMP #80, R8\r
+ BNE RegTest2Error\r
+ CMP #90, R9\r
+ BNE RegTest2Error\r
+ CMP #100, R10\r
+ BNE RegTest2Error\r
+ CMP #110, R11\r
+ BNE RegTest2Error\r
+ CMP #120, R12\r
+ BNE RegTest2Error\r
+ CMP #130, R13\r
+ BNE RegTest2Error\r
+ CMP #140, R14\r
+ BNE RegTest2Error\r
+ CMP #150, R15\r
+ BNE RegTest2Error\r
+\r
+ ; All comparisons passed, start a new itteratio of this loop.\r
+ BRA TestLoop2\r
+\r
+RegTest2Error:\r
+ ; A compare failed, just loop here so the loop counter stops incrementing\r
+ ; - causing the check task to indicate the error.\r
+ BRA RegTest2Error\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * DISCLAIMER\r
+ * This software is supplied by Renesas Electronics Corporation and is only\r
+ * intended for use with Renesas products. No other uses are authorized. This\r
+ * software is owned by Renesas Electronics Corporation and is protected under\r
+ * all applicable laws, including copyright laws.\r
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+ * Renesas reserves the right, without notice, to make changes to this software\r
+ * and to discontinue the availability of this software. By using this software,\r
+ * you agree to the additional terms and conditions found by accessing the\r
+ * following link:\r
+ * http://www.renesas.com/disclaimer\r
+ *******************************************************************************/\r
+/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */\r
+/*******************************************************************************\r
+ * File Name : r_rsk_async.c\r
+ * Version : 1.00\r
+ * Device(s) : R5F51138AxFP\r
+ * Tool-Chain : CCRX\r
+ * H/W Platform : RSKRX113\r
+ * Description : Functions used to send data via the SCI in asynchronous mode\r
+ *******************************************************************************/\r
+/*******************************************************************************\r
+ * History : 26.08.2014 Ver. 1.00 First Release\r
+ *******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ System Includes\r
+ *******************************************************************************/\r
+/* Following header file provides string type definitions. */\r
+#include <string.h>\r
+\r
+/*******************************************************************************\r
+ User Includes (Project Level Includes)\r
+ *******************************************************************************/\r
+/* Defines port registers */\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_sci.h"\r
+#include "r_rsk_async.h"\r
+\r
+/*******************************************************************************\r
+ User Defines\r
+ *******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Global Variables\r
+ *******************************************************************************/\r
+\r
+/* Declaration of the command string to clear the terminal screen */\r
+static const char cmd_clr_scr[] =\r
+{ 27, 91, 50, 74, 0, 27, 91, 72, 0 };\r
+\r
+/*******************************************************************************\r
+ * Function Prototypes\r
+ *******************************************************************************/\r
+\r
+/* text_write function prototype */\r
+static void text_write (const char * const msg_string);\r
+\r
+/*******************************************************************************\r
+ * Function Name: R_ASYNC_Init\r
+ * Description : This function initialises the SCI channel connected to the\r
+ * RS232 connector on the RSK. The channel is configured for\r
+ * transmission and reception, and instructions are sent to the\r
+ * terminal.\r
+ * Argument : none\r
+ * Return value : none\r
+ *******************************************************************************/\r
+void R_ASYNC_Init (void)\r
+{\r
+\r
+ /* Set up SCI1 receive buffer */\r
+ R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
+\r
+ /* Enable SCI1 operations */\r
+ R_SCI1_Start();\r
+\r
+ /* Clear the text on terminal window */\r
+ text_write(cmd_clr_scr);\r
+\r
+ /* Display splash screen on terminal window */\r
+ text_write("Renesas RSKRX113 Async Serial \r\n");\r
+\r
+ /* Inform user on how to stop transmission */\r
+ text_write("Press 'z' to stop and any key to resume\r\n\n");\r
+}\r
+/*******************************************************************************\r
+ * End of function R_ASYNC_Init\r
+ *******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Function Name : text_write\r
+ * Description : Transmits null-terminated string.\r
+ * Argument : (char*) msg_string - null terminated string\r
+ * Return value : None\r
+ *******************************************************************************/\r
+static void text_write (const char * const msg_string)\r
+{\r
+ R_SCI1_AsyncTransmit((uint8_t *) msg_string, (uint16_t) strlen(msg_string));\r
+}\r
+/*******************************************************************************\r
+ * End of function text_write\r
+ *******************************************************************************/\r
+\r
--- /dev/null
+/*******************************************************************************\r
+ * DISCLAIMER\r
+ * This software is supplied by Renesas Electronics Corporation and is only\r
+ * intended for use with Renesas products. No other uses are authorized. This\r
+ * software is owned by Renesas Electronics Corporation and is protected under\r
+ * all applicable laws, including copyright laws.\r
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+ * Renesas reserves the right, without notice, to make changes to this software\r
+ * and to discontinue the availability of this software. By using this software,\r
+ * you agree to the additional terms and conditions found by accessing the\r
+ * following link:\r
+ * http://www.renesas.com/disclaimer\r
+ *******************************************************************************/\r
+/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */\r
+/*******************************************************************************\r
+ * File Name : r_rsk_async.h\r
+ * Version : 1.00\r
+ * Device(s) : R5F51138AxFP\r
+ * Tool-Chain : CCRX\r
+ * H/W Platform : RSKRX113\r
+ * Description : Functions used to send data via the SCI in asynchronous mode\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * History : 26.08.2014 Ver. 1.00 First Release\r
+ *******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Macro Definitions\r
+ *******************************************************************************/\r
+/* Multiple inclusion prevention macro */\r
+#ifndef R_RSK_ASYNC_H\r
+#define R_RSK_ASYNC_H\r
+\r
+/*******************************************************************************\r
+ * Global Function Prototypes\r
+ *******************************************************************************/\r
+/* initialise asynchronous transmission*/\r
+void R_ASYNC_Init (void);\r
+\r
+/* End of multiple inclusion prevention macro */\r
+#endif\r
+\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_cgc.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for CGC module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_cgc.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_CGC_Create\r
+* Description : This function initializes the clock generator.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_CGC_Create(void)\r
+{\r
+ uint32_t sckcr_dummy;\r
+ uint32_t w_count;\r
+\r
+ /* Set main clock control registers */\r
+ SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _20_CGC_MAINOSC_OVER10M;\r
+ SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768;\r
+\r
+ /* Set main clock operation */\r
+ SYSTEM.MOSCCR.BIT.MOSTP = 0U;\r
+\r
+ /* Wait for main clock oscillator wait counter overflow */\r
+ while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF);\r
+\r
+ /* Set system clock */\r
+ sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000000_CGC_PCLKB_DIV_1 | _00000000_CGC_ICLK_DIV_1 | \r
+ _00000000_CGC_FCLK_DIV_1;\r
+ SYSTEM.SCKCR.LONG = sckcr_dummy;\r
+\r
+ while (SYSTEM.SCKCR.LONG != sckcr_dummy);\r
+\r
+ /* Set PLL circuit */\r
+ SYSTEM.PLLCR.WORD = _0002_CGC_PLL_FREQ_DIV_4 | _0F00_CGC_PLL_FREQ_MUL_8;\r
+ SYSTEM.PLLCR2.BIT.PLLEN = 0U;\r
+\r
+ /* Wait for PLL wait counter overflow */\r
+ while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF);\r
+\r
+ /* Stop sub-clock */\r
+ SYSTEM.SOSCCR.BIT.SOSTP = 1U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (1U != SYSTEM.SOSCCR.BIT.SOSTP);\r
+\r
+ /* Stop sub-clock */\r
+ RTC.RCR3.BIT.RTCEN = 0U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (0U != RTC.RCR3.BIT.RTCEN);\r
+\r
+ /* Wait for 5 sub-clock cycles */\r
+ for (w_count = 0U; w_count < _007B_CGC_SUBSTPWT_WAIT; w_count++)\r
+ {\r
+ nop();\r
+ }\r
+\r
+ /* Set sub-clock drive capacity */\r
+ RTC.RCR3.BIT.RTCDV = 1U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (1U != RTC.RCR3.BIT.RTCDV);\r
+\r
+ /* Set sub-clock */\r
+ SYSTEM.SOSCCR.BIT.SOSTP = 0U;\r
+\r
+ /* Wait for the register modification to complete */\r
+ while (0U != SYSTEM.SOSCCR.BIT.SOSTP);\r
+\r
+ /* Wait for sub-clock to be stable */\r
+ for (w_count = 0U; w_count < _00061A81_CGC_SUBOSCWT_WAIT; w_count++)\r
+ {\r
+ nop();\r
+ }\r
+\r
+ /* Set clock source */\r
+ SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL;\r
+\r
+ while (SYSTEM.SCKCR3.WORD != _0400_CGC_CLOCKSOURCE_PLL);\r
+\r
+ /* Set LOCO */\r
+ SYSTEM.LOCOCR.BIT.LCSTP = 1U;\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_cgc.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for CGC module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef CGC_H\r
+#define CGC_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+/*\r
+ System Clock Control Register (SCKCR)\r
+*/\r
+/* Peripheral Module Clock D (PCLKD) */\r
+#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */\r
+#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */\r
+#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */\r
+#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */\r
+#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */\r
+#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */\r
+#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */\r
+/* Peripheral Module Clock B (PCLKB) */\r
+#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */\r
+#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */\r
+#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */\r
+#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */\r
+#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */\r
+#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */\r
+#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */\r
+/* System Clock (ICLK) */\r
+#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */\r
+#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */\r
+#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */\r
+#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */\r
+#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */\r
+#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */\r
+#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */\r
+/* System Clock (FCLK) */\r
+#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */\r
+#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */\r
+#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */\r
+#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */\r
+#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */\r
+#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */\r
+#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */\r
+\r
+/*\r
+ System Clock Control Register 3 (SCKCR3)\r
+*/\r
+#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */\r
+#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */\r
+#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */\r
+#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */\r
+#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */\r
+\r
+/*\r
+ PLL Control Register (PLLCR)\r
+*/\r
+/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */\r
+#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */\r
+#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */\r
+#define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */\r
+/* Frequency Multiplication Factor Select (STC[5:0]) */\r
+#define _0B00_CGC_PLL_FREQ_MUL_6 (0x0B00U) /* x6 */\r
+#define _0F00_CGC_PLL_FREQ_MUL_8 (0x0F00U) /* x8 */\r
+\r
+/*\r
+ USB-dedicated PLL Control Register (UPLLCR)\r
+*/\r
+/* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */\r
+#define _0000_CGC_PLL_UPLIDIV_1 (0x0000U) /* x1 */\r
+#define _0001_CGC_PLL_UPLIDIV_2 (0x0001U) /* x1/2 */\r
+#define _0002_CGC_PLL_UPLIDIV_4 (0x0002U) /* x1/4 */\r
+/* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */\r
+#define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */\r
+#define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */\r
+/* Frequency Multiplication Factor Select (USTC[5:0]) */\r
+#define _0B00_CGC_PLL_USTC_6 (0x0B00U) /* x6 */\r
+#define _0F00_CGC_PLL_USTC_8 (0x0F00U) /* x8 */\r
+\r
+/*\r
+ Oscillation Stop Detection Control Register (OSTDCR)\r
+*/\r
+/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */\r
+#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */\r
+#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */\r
+/* Oscillation Stop Detection Function Enable (OSTDE) */\r
+#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */\r
+#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */\r
+\r
+/*\r
+ Main Clock Oscillator Wait Control Register (MOSCWTCR)\r
+*/\r
+/* Main Clock Oscillator Wait Time (MSTS[4:0]) */\r
+#define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */\r
+#define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */\r
+#define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */\r
+#define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */\r
+#define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */\r
+#define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */\r
+#define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */\r
+#define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */\r
+\r
+/*\r
+ HOCO Wait Control Register (HOCOWTCR)\r
+*/\r
+/* HOCO Wait Time (HOCOWTCR) */\r
+#define _05_CGC_HOCO_WAIT_CYCLE_138 (0x05U) /* Wait time = 138 cycles (34.5us) */\r
+#define _06_CGC_HOCO_WAIT_CYCLE_266 (0x06U) /* Wait time = 266 cycles (66.5us) */\r
+\r
+/*\r
+ Clock Output Control Register (CKOCR)\r
+*/\r
+/* Clock Output Source Select (CKOSEL[2:0]) */\r
+#define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */\r
+#define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */\r
+#define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */\r
+#define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */\r
+/* Clock Output Division Ratio Select (CKODIV[2:0]) */\r
+#define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */\r
+#define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */\r
+#define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */\r
+#define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */\r
+#define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */\r
+/* Clock Output Control (CKOSTP) */\r
+#define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */\r
+#define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */\r
+\r
+/*\r
+ Main Clock Oscillator Forced Oscillation Control Register (MOFCR)\r
+*/\r
+/* Main Oscillator Drive Capability Switch (MODRV21) */\r
+#define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */\r
+#define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */\r
+/* Main Clock Oscillator Switch (MOSEL) */\r
+#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */\r
+#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */\r
+\r
+/*\r
+ LCD Source Clock Control Register (LCDSCLKCR)\r
+*/\r
+/* LCD Source Clock Select (LCDSCLKSEL[2:0]) */\r
+#define _00_CGC_LCDSCLKSEL_LOCO (0x00U) /* LOCO */\r
+#define _01_CGC_LCDSCLKSEL_HOCO (0x01U) /* HOCO */\r
+#define _02_CGC_LCDSCLKSEL_MAINCLK (0x02U) /* Main clock oscillator */\r
+#define _03_CGC_LCDSCLKSEL_SUBCLK (0x03U) /* Sub-clock oscillator */\r
+#define _04_CGC_LCDSCLKSEL_IWDT (0x04U) /* IWDT-dedicated on-chip oscillator */\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+#define _007B_CGC_SUBSTPWT_WAIT (0x007BU) /* Wait time for 5 sub clock cycles */\r
+#define _00061A81_CGC_SUBOSCWT_WAIT (0x00061A81U) /* Wait time for sub clock stable */\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void R_CGC_Create(void);\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_cgc_user.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for CGC module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_cgc.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_dbsct.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : Setting of B.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+\r
+#pragma unpack\r
+\r
+#pragma section C C$DSEC\r
+extern const struct {\r
+ uint8_t *rom_s; /* Start address of the initialized data section in ROM */\r
+ uint8_t *rom_e; /* End address of the initialized data section in ROM */\r
+ uint8_t *ram_s; /* Start address of the initialized data section in RAM */\r
+} _DTBL[] = {\r
+ { __sectop("D"), __secend("D"), __sectop("R") },\r
+ { __sectop("D_2"), __secend("D_2"), __sectop("R_2") },\r
+ { __sectop("D_1"), __secend("D_1"), __sectop("R_1") }\r
+};\r
+#pragma section C C$BSEC\r
+extern const struct {\r
+ uint8_t *b_s; /* Start address of non-initialized data section */\r
+ uint8_t *b_e; /* End address of non-initialized data section */\r
+} _BTBL[] = {\r
+ { __sectop("B"), __secend("B") },\r
+ { __sectop("B_2"), __secend("B_2") },\r
+ { __sectop("B_1"), __secend("B_1") }\r
+};\r
+\r
+#pragma section\r
+\r
+/*\r
+** CTBL prevents excessive output of L1100 messages when linking.\r
+** Even if CTBL is deleted, the operation of the program does not change.\r
+*/\r
+uint8_t * const _CTBL[] = {\r
+ __sectop("C_1"), __sectop("C_2"), __sectop("C"),\r
+ __sectop("W_1"), __sectop("W_2"), __sectop("W"),\r
+ __sectop("L"), __sectop("SU"),\r
+ __sectop("C$DSEC"), __sectop("C$BSEC"),\r
+ __sectop("C$INIT"), __sectop("C$VTBL"), __sectop("C$VECT")\r
+};\r
+\r
+#pragma packoption\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_hardware_setup.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements system initializing function.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_cgc.h"\r
+#include "r_cg_port.h"\r
+#include "r_cg_sci.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_Systeminit\r
+* Description : This function initializes every macro.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_Systeminit(void)\r
+{\r
+ /* Enable writing to registers related to operating modes, LPC, CGC and software reset */\r
+ SYSTEM.PRCR.WORD = 0xA50FU; \r
+\r
+ /* Enable writing to MPC pin function control registers */\r
+ MPC.PWPR.BIT.B0WI = 0U; \r
+ MPC.PWPR.BIT.PFSWE = 1U;\r
+\r
+ /* Initialize non-existent pins */\r
+ PORT0.PDR.BYTE = 0x6BU;\r
+ PORT3.PDR.BYTE = 0xD8U;\r
+ PORT4.PDR.BYTE = 0xA0U;\r
+ PORT5.PDR.BYTE = 0x80U;\r
+ PORT9.PDR.BYTE = 0xF8U;\r
+ PORTD.PDR.BYTE = 0xE0U;\r
+ PORTF.PDR.BYTE = 0x3FU;\r
+ PORTJ.PDR.BYTE = 0x32U;\r
+\r
+ /* Set peripheral settings */\r
+ R_CGC_Create();\r
+ R_PORT_Create();\r
+ R_SCI1_Create();\r
+\r
+ /* Disable writing to MPC pin function control registers */\r
+ MPC.PWPR.BIT.PFSWE = 0U; \r
+ MPC.PWPR.BIT.B0WI = 1U; \r
+\r
+ /* Enable protection */\r
+ SYSTEM.PRCR.WORD = 0xA500U; \r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: HardwareSetup\r
+* Description : This function initializes hardware setting.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void HardwareSetup(void)\r
+{\r
+ R_Systeminit();\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_intprg.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : Setting of B.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include <machine.h>\r
+#include "r_cg_vect.h"\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+\r
+#pragma section IntPRG\r
+\r
+/* Undefined exceptions for supervisor instruction, undefined instruction and floating point exceptions */\r
+void r_undefined_exception(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+\r
+/* Reserved */\r
+void r_reserved_exception(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+\r
+/* NMI */\r
+void r_nmi_exception(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+\r
+/* BRK */\r
+void r_brk_exception(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_macrodriver.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements general head file.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef MODULEID_H\r
+#define MODULEID_H\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "../iodefine.h"\r
+#include <machine.h>\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+#ifndef __TYPEDEF__\r
+\r
+/* Status list definition */\r
+#define MD_STATUSBASE (0x00U)\r
+#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */\r
+#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */\r
+#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */\r
+#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */\r
+#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */\r
+\r
+/* Error list definition */\r
+#define MD_ERRORBASE (0x80U)\r
+#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */\r
+#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */\r
+#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */\r
+#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */\r
+#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */\r
+#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */\r
+#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */\r
+\r
+/* BRK handler command options */\r
+typedef enum {\r
+ BRK_NO_COMMAND,\r
+ BRK_ALL_MODULE_CLOCK_STOP,\r
+ BRK_SLEEP,\r
+ BRK_DEEP_SLEEP,\r
+ BRK_STANDBY,\r
+ BRK_LOAD_FINTV_REGISTER\r
+} brk_commands;\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+#ifndef __TYPEDEF__\r
+ #ifndef _STD_USING_INT_TYPES\r
+ #define _SYS_INT_TYPES_H\r
+ #ifndef _STD_USING_BIT_TYPES\r
+ #define __int8_t_defined\r
+ typedef signed char int8_t;\r
+ typedef signed short int16_t;\r
+ #endif\r
+\r
+ typedef unsigned char uint8_t;\r
+ typedef unsigned short uint16_t;\r
+ typedef signed long int32_t;\r
+ typedef unsigned long uint32_t;\r
+\r
+ typedef signed char int_least8_t;\r
+ typedef signed short int_least16_t;\r
+ typedef signed long int_least32_t;\r
+ typedef unsigned char uint_least8_t;\r
+ typedef unsigned short uint_least16_t;\r
+ typedef unsigned long uint_least32_t;\r
+ #endif\r
+\r
+ typedef unsigned short MD_STATUS;\r
+ #define __TYPEDEF__\r
+#endif\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void HardwareSetup(void);\r
+void R_Systeminit(void);\r
+\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_port.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for Port module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_port.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_PORT_Create\r
+* Description : This function initializes the Port I/O.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_PORT_Create(void)\r
+{\r
+ PORT2.PDR.BYTE = _04_Pm2_MODE_OUTPUT | _08_Pm3_MODE_OUTPUT | _10_Pm4_MODE_OUTPUT | _20_Pm5_MODE_OUTPUT | \r
+ _00_Pm7_MODE_INPUT;\r
+ PORT3.PDR.BYTE = _00_Pm2_MODE_INPUT | _D8_PDR3_DEFAULT;\r
+ PORTJ.PDR.BYTE = _00_Pm0_MODE_INPUT | _32_PDRJ_DEFAULT;\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_port.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for Port module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef PORT_H\r
+#define PORT_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+/*\r
+ Port Direction Register (PDR)\r
+*/\r
+/* Pmn Direction Control (B7 - B0) */\r
+#define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */\r
+#define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */\r
+#define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */\r
+#define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */\r
+#define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */\r
+#define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */\r
+#define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */\r
+#define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */\r
+#define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */\r
+#define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */\r
+#define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */\r
+#define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */\r
+#define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */\r
+#define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */\r
+#define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */\r
+#define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */\r
+#define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */\r
+#define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */\r
+#define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */\r
+#define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */\r
+#define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */\r
+#define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */\r
+#define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */\r
+#define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */\r
+\r
+/*\r
+ Port Output Data Register (PODR)\r
+*/\r
+/* Pmn Output Data Store (B7 - B0) */\r
+#define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */\r
+#define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */\r
+#define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */\r
+#define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */\r
+#define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */\r
+#define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */\r
+#define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */\r
+#define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */\r
+#define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */\r
+#define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */\r
+#define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */\r
+#define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */\r
+#define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */\r
+#define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */\r
+#define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */\r
+#define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */\r
+\r
+/*\r
+ Open Drain Control Register 0 (ODR0)\r
+*/\r
+/* Pmn Output Type Select (Pm0 to Pm3) */\r
+#define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
+#define _02_Pm0_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */\r
+#define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
+#define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */\r
+#define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
+#define _20_Pm2_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */\r
+#define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
+#define _80_Pm3_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */\r
+\r
+/*\r
+ Open Drain Control Register 1 (ODR1)\r
+*/\r
+/* Pmn Output Type Select (Pm4 to Pm7) */\r
+#define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
+#define _02_Pm4_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */\r
+#define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
+#define _08_Pm5_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */\r
+#define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
+#define _20_Pm6_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */\r
+#define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */\r
+#define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
+#define _80_Pm7_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */\r
+\r
+/*\r
+ Pull-Up Control Register (PCR)\r
+*/\r
+/* Pm0 Input Pull-Up Resistor Control ((B7 - B0)) */\r
+#define _00_Pm0_PULLUP_OFF (0x00U) /* Pn0 pull-up resistor not connected */\r
+#define _01_Pm0_PULLUP_ON (0x01U) /* Pn0 pull-up resistor connected */\r
+#define _00_Pm1_PULLUP_OFF (0x00U) /* Pn1 pull-up resistor not connected */\r
+#define _02_Pm1_PULLUP_ON (0x02U) /* Pn1 pull-up resistor connected */\r
+#define _00_Pm2_PULLUP_OFF (0x00U) /* Pn2 Pull-up resistor not connected */\r
+#define _04_Pm2_PULLUP_ON (0x04U) /* Pn2 pull-up resistor connected */\r
+#define _00_Pm3_PULLUP_OFF (0x00U) /* Pn3 pull-up resistor not connected */\r
+#define _08_Pm3_PULLUP_ON (0x08U) /* Pn3 pull-up resistor connected */\r
+#define _00_Pm4_PULLUP_OFF (0x00U) /* Pn4 pull-up resistor not connected */\r
+#define _10_Pm4_PULLUP_ON (0x10U) /* Pn4 pull-up resistor connected */\r
+#define _00_Pm5_PULLUP_OFF (0x00U) /* Pn5 pull-up resistor not connected */\r
+#define _20_Pm5_PULLUP_ON (0x20U) /* Pn5 pull-up resistor connected */\r
+#define _00_Pm6_PULLUP_OFF (0x00U) /* Pn6 pull-up resistor not connected */\r
+#define _40_Pm6_PULLUP_ON (0x40U) /* Pn6 pull-up resistor connected */\r
+#define _00_Pm7_PULLUP_OFF (0x00U) /* Pn7 pull-up resistor not connected */\r
+#define _80_Pm7_PULLUP_ON (0x80U) /* Pn7 pull-up resistor connected */\r
+\r
+/*\r
+ Port Switching Register A (PSRA)\r
+*/\r
+/* PB6/PC0 Switching (PSEL6) */\r
+#define _00_PORT_PSEL6_PB6 (0x00U) /* PB6 general I/O port function is selected */\r
+#define _40_PORT_PSEL6_PC0 (0x40U) /* PC0 general I/O port function is selected */\r
+/* PB7/PC1 Switching (PSEL7) */\r
+#define _00_PORT_PSEL7_PB7 (0x00U) /* PB7 general I/O port function is selected */\r
+#define _80_PORT_PSEL7_PC1 (0x80U) /* PC1 general I/O port function is selected */\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+#define _6B_PDR0_DEFAULT (0x6BU) /* PDR0 default value */\r
+#define _D8_PDR3_DEFAULT (0xD8U) /* PDR3 default value */\r
+#define _A0_PDR4_DEFAULT (0xA0U) /* PDR4 default value */\r
+#define _80_PDR5_DEFAULT (0x80U) /* PDR5 default value */\r
+#define _F8_PDR9_DEFAULT (0xF8U) /* PDR9 default value */\r
+#define _E0_PDRD_DEFAULT (0xE0U) /* PDRD default value */\r
+#define _3F_PDRF_DEFAULT (0x3FU) /* PDRF default value */\r
+#define _32_PDRJ_DEFAULT (0x32U) /* PDRJ default value */\r
+\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void R_PORT_Create(void);\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_port_user.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for Port module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_port.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_resetprg.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : Reset program.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include <machine.h>\r
+#include <_h_c_lib.h>\r
+//#include <stddef.h> // Remove the comment when you use errno\r
+//#include <stdlib.h> // Remove the comment when you use rand()\r
+#include "r_cg_stacksct.h"\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+void PowerON_Reset(void);\r
+void main(void);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#define PSW_init 0x00010000 /* PSW bit pattern */\r
+#define FPSW_init 0x00000000 /* FPSW bit base pattern */\r
+\r
+#pragma section ResetPRG /* output PowerON_Reset to PResetPRG section */\r
+\r
+#pragma entry PowerON_Reset\r
+\r
+void PowerON_Reset(void)\r
+{\r
+ set_intb(__sectop("C$VECT"));\r
+\r
+ _INITSCT(); /* Initialize Sections */\r
+ HardwareSetup(); /* Use Hardware Setup */\r
+ nop();\r
+ set_psw(PSW_init); /* Set Ubit & Ibit for PSW */\r
+ main();\r
+ brk();\r
+}\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_sbrk.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : Program of sbrk.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include <stddef.h>\r
+#include <stdio.h>\r
+#include "r_cg_sbrk.h"\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+\r
+int8_t *sbrk(size_t size);\r
+\r
+extern int8_t *_s1ptr;\r
+\r
+union HEAP_TYPE\r
+{\r
+ int16_t dummy ; /* Dummy for 4-byte boundary */\r
+ int8_t heap[HEAPSIZE]; /* Declaration of the area managed by sbrk */\r
+};\r
+\r
+static union HEAP_TYPE heap_area ;\r
+\r
+/* End address allocated by sbrk */\r
+static int8_t *brk = (int8_t *) &heap_area;\r
+\r
+/**************************************************************************/\r
+/* sbrk:Memory area allocation */\r
+/* Return value:Start address of allocated area (Pass) */\r
+/* -1 (Failure) */\r
+/**************************************************************************/\r
+int8_t *sbrk(size_t size) /* Assigned area size */\r
+{\r
+ int8_t *p;\r
+\r
+ if (brk+size > heap_area.heap + HEAPSIZE) /* Empty area size */\r
+ {\r
+ p = (int8_t *)-1;\r
+ }\r
+ else\r
+ {\r
+ p = brk; /* Area assignment */\r
+ brk += size; /* End address update */\r
+ }\r
+\r
+ return p;\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_sbrk.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : Header file of sbrk file.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef _SBRK_H\r
+#define _SBRK_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+#define HEAPSIZE (0x400U) /* Size of area managed by sbrk */\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_sci.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for SCI module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_sci.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+uint8_t * gp_sci1_tx_address; /* SCI1 transmit buffer address */\r
+uint16_t g_sci1_tx_count; /* SCI1 transmit data number */\r
+uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */\r
+uint16_t g_sci1_rx_count; /* SCI1 receive data number */\r
+uint16_t g_sci1_rx_length; /* SCI1 receive data length */\r
+/* Start user code for global. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCI1_Create\r
+* Description : This function initializes the SCI1.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_SCI1_Create(void)\r
+{\r
+ /* Cancel SCI1 module stop state */\r
+ MSTP(SCI1) = 0U;\r
+\r
+ /* Set interrupt priority */\r
+ IPR(SCI1, ERI1) = _0F_SCI_PRIORITY_LEVEL15;\r
+\r
+ /* Clear the SCR.TIE, RIE, TE, RE and TEIE bits */\r
+ SCI1.SCR.BIT.TIE = 0U;\r
+ SCI1.SCR.BIT.RIE = 0U;\r
+ SCI1.SCR.BIT.TE = 0U;\r
+ SCI1.SCR.BIT.RE = 0U;\r
+ SCI1.SCR.BIT.TEIE = 0U;\r
+\r
+ /* Set RXD1 pin */\r
+ MPC.P15PFS.BYTE = 0x0AU;\r
+ PORT1.PMR.BYTE |= 0x20U;\r
+ /* Set TXD1 pin */\r
+ MPC.P16PFS.BYTE = 0x0AU;\r
+ PORT1.PODR.BYTE |= 0x40U;\r
+ PORT1.PDR.BYTE |= 0x40U;\r
+ PORT1.PMR.BYTE |= 0x40U;\r
+\r
+ /* Set clock enable */\r
+ SCI1.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED;\r
+\r
+ /* Clear the SIMR1.IICM, SPMR.CKPH, and CKPOL bit */\r
+ SCI1.SIMR1.BIT.IICM = 0U;\r
+ SCI1.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED;\r
+\r
+ /* Set control registers */\r
+ SCI1.SMR.BYTE = _01_SCI_CLOCK_PCLK_4 | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | \r
+ _00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE;\r
+ SCI1.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | _72_SCI_SCMR_DEFAULT;\r
+\r
+ /* Set SEMR, SNFR */\r
+ SCI1.SEMR.BYTE = _00_SCI_LOW_LEVEL_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK;\r
+\r
+ /* Set bitrate */\r
+ SCI1.BRR = 0x19U;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCI1_Start\r
+* Description : This function starts the SCI1.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_SCI1_Start(void)\r
+{\r
+ IR(SCI1,TXI1) = 0U;\r
+ IR(SCI1,TEI1) = 0U;\r
+ IR(SCI1,RXI1) = 0U;\r
+ IR(SCI1,ERI1) = 0U;\r
+ IEN(SCI1,TXI1) = 1U;\r
+ IEN(SCI1,TEI1) = 1U;\r
+ IEN(SCI1,RXI1) = 1U;\r
+ IEN(SCI1,ERI1) = 1U;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCI1_Stop\r
+* Description : This function stops the SCI1.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+void R_SCI1_Stop(void)\r
+{\r
+ /* Set TXD1 pin */\r
+ PORT1.PMR.BYTE &= 0xBFU;\r
+\r
+ SCI1.SCR.BYTE &= 0xCF; /* Disable serial transmit and receive */\r
+ SCI1.SCR.BIT.TIE = 0U; /* Disable TXI interrupt */\r
+ SCI1.SCR.BIT.RIE = 0U; /* Disable RXI and ERI interrupt */\r
+ IR(SCI1,TXI1) = 0U;\r
+ IEN(SCI1,TXI1) = 0U;\r
+ IR(SCI1,TEI1) = 0U;\r
+ IEN(SCI1,TEI1) = 0U;\r
+ IR(SCI1,RXI1) = 0U;\r
+ IEN(SCI1,RXI1) = 0U;\r
+ IR(SCI1,ERI1) = 0U;\r
+ IEN(SCI1,ERI1) = 0U;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCI1_Serial_Receive\r
+* Description : This function receives SCI1 data.\r
+* Arguments : rx_buf -\r
+* receive buffer pointer (Not used when receive data handled by DTC)\r
+* rx_num -\r
+* buffer size\r
+* Return Value : status -\r
+* MD_OK or MD_ARGERROR\r
+***********************************************************************************************************************/\r
+MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num)\r
+{\r
+ MD_STATUS status = MD_OK;\r
+\r
+ if (rx_num < 1U)\r
+ {\r
+ status = MD_ARGERROR;\r
+ }\r
+ else\r
+ {\r
+ g_sci1_rx_count = 0U;\r
+ g_sci1_rx_length = rx_num;\r
+ gp_sci1_rx_address = rx_buf;\r
+ SCI1.SCR.BIT.RIE = 1U;\r
+ SCI1.SCR.BIT.RE = 1U;\r
+ }\r
+\r
+ return (status);\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: R_SCI1_Serial_Send\r
+* Description : This function transmits SCI1 data.\r
+* Arguments : tx_buf -\r
+* transfer buffer pointer (Not used when transmit data handled by DTC)\r
+* tx_num -\r
+* buffer size\r
+* Return Value : status -\r
+* MD_OK or MD_ARGERROR\r
+***********************************************************************************************************************/\r
+MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num)\r
+{\r
+ MD_STATUS status = MD_OK;\r
+\r
+ if (tx_num < 1U)\r
+ {\r
+ status = MD_ARGERROR;\r
+ }\r
+ else\r
+ {\r
+ gp_sci1_tx_address = tx_buf;\r
+ g_sci1_tx_count = tx_num;\r
+ /* Set TXD1 pin */\r
+ PORT1.PMR.BYTE |= 0x40U;\r
+ SCI1.SCR.BIT.TIE = 1U;\r
+ SCI1.SCR.BIT.TE = 1U;\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_sci.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for SCI module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef SCI_H\r
+#define SCI_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+\r
+/*\r
+ Serial mode register (SMR)\r
+*/\r
+/* Clock select (CKS) */\r
+#define _00_SCI_CLOCK_PCLK (0x00U) /* PCLK */\r
+#define _01_SCI_CLOCK_PCLK_4 (0x01U) /* PCLK/4 */\r
+#define _02_SCI_CLOCK_PCLK_16 (0x02U) /* PCLK/16 */\r
+#define _03_SCI_CLOCK_PCLK_64 (0x03U) /* PCLK/64 */\r
+/* Multi-processor Mode (MP) */\r
+#define _00_SCI_MULTI_PROCESSOR_DISABLE (0x00U) /* Disable multiprocessor mode */\r
+#define _04_SCI_MULTI_PROCESSOR_ENABLE (0x04U) /* Enable multiprocessor mode */\r
+/* Stop bit length (STOP) */\r
+#define _00_SCI_STOP_1 (0x00U) /* 1 stop bit length */\r
+#define _08_SCI_STOP_2 (0x08U) /* 2 stop bits length */\r
+/* Parity mode (PM) */\r
+#define _00_SCI_PARITY_EVEN (0x00U) /* Parity even */\r
+#define _10_SCI_PARITY_ODD (0x10U) /* Parity odd */\r
+/* Parity enable (PE) */\r
+#define _00_SCI_PARITY_DISABLE (0x00U) /* Parity disable */\r
+#define _20_SCI_PARITY_ENABLE (0x20U) /* Parity enable */\r
+/* Character length (CHR) */\r
+#define _00_SCI_DATA_LENGTH_8 (0x00U) /* Data length 8 bits */\r
+#define _40_SCI_DATA_LENGTH_7 (0x40U) /* Data length 7 bits */\r
+/* Communications mode (CM) */\r
+#define _00_SCI_ASYNCHRONOUS_MODE (0x00U) /* Asynchronous mode */\r
+#define _80_SCI_CLOCK_SYNCHRONOUS_MODE (0x80U) /* Clock synchronous mode */\r
+/* Base clock pulse (BCP) */\r
+#define _00_SCI_32_93_CLOCK_CYCLES (0x00U) /* 32 or 93 clock cycles */\r
+#define _04_SCI_64_128_CLOCK_CYCLES (0x04U) /* 64 or 128 clock cycles */\r
+#define _08_SCI_186_372_CLOCK_CYCLES (0x08U) /* 186 or 372 clock cycles */\r
+#define _0C_SCI_256_512_CLOCK_CYCLES (0x0CU) /* 256 or 512 clock cycles */\r
+/* Block transfer mode (BLK) */\r
+#define _00_SCI_BLK_TRANSFER_DISABLE (0x00U) /* Block transfer disable */\r
+#define _40_SCI_BLK_TRANSFER_ENABLE (0x40U) /* Block transfer enable */\r
+/* GSM mode (GSM) */\r
+#define _00_SCI_GSM_DISABLE (0x00U) /* Normal mode operation */\r
+#define _80_SCI_GSM_ENABLE (0x80U) /* GSM mode operation */\r
+\r
+/*\r
+ Serial control register (SCR)\r
+*/\r
+/* Clock enable (CKE) */\r
+#define _00_SCI_INTERNAL_SCK_UNUSED (0x00U) /* Internal clock selected, SCK pin unused */\r
+#define _01_SCI_INTERNAL_SCK_OUTPUT (0x01U) /* Internal clock selected, SCK pin as clock output */\r
+#define _02_SCI_EXTERNAL (0x02U) /* External clock selected */\r
+#define _03_SCI_EXTERNAL (0x03U) /* External clock selected */\r
+/* Transmit end interrupt enable (TEIE) */\r
+#define _00_SCI_TEI_INTERRUPT_DISABLE (0x00U) /* TEI interrupt request disable */\r
+#define _04_SCI_TEI_INTERRUPT_ENABLE (0x04U) /* TEI interrupt request enable */\r
+/* Multi-processor interrupt enable (MPIE) */\r
+#define _00_SCI_MP_INTERRUPT_NORMAL (0x00U) /* Normal reception */\r
+#define _08_SCI_MP_INTERRUPT_SPECIAL (0x08U) /* Multi-processor ID reception */\r
+/* Receive enable (RE) */\r
+#define _00_SCI_RECEIVE_DISABLE (0x00U) /* Disable receive mode */\r
+#define _10_SCI_RECEIVE_ENABLE (0x10U) /* Enable receive mode */\r
+/* Transmit enable (TE) */\r
+#define _00_SCI_TRANSMIT_DISABLE (0x00U) /* Disable transmit mode */\r
+#define _20_SCI_TRANSMIT_ENABLE (0x20U) /* Enable transmit mode */\r
+/* Receive interrupt enable (RIE) */\r
+#define _00_SCI_RXI_ERI_DISABLE (0x00U) /* Disable RXI and ERI interrupt requests */\r
+#define _40_SCI_RXI_ERI_ENABLE (0x40U) /* Enable RXI and ERI interrupt requests */\r
+/* Transmit interrupt enable (TIE) */\r
+#define _00_SCI_TXI_DISABLE (0x00U) /* Disable TXI interrupt requests */\r
+#define _80_SCI_TXI_ENABLE (0x80U) /* Enable TXI interrupt requests */\r
+\r
+/*\r
+ Serial status register (SSR)\r
+*/\r
+/* Multi-Processor bit transfer (MPBT) */\r
+#define _00_SCI_SET_DATA_TRANSFER (0x00U) /* Set data transmission cycles */\r
+#define _01_SCI_SET_ID_TRANSFER (0x01U) /* Set ID transmission cycles */\r
+/* Multi-Processor (MPB) */\r
+#define _00_SCI_DATA_TRANSFER (0x00U) /* In data transmission cycles */\r
+#define _02_SCI_ID_TRANSFER (0x02U) /* In ID transmission cycles */\r
+/* Transmit end flag (TEND) */\r
+#define _00_SCI_TRANSMITTING (0x00U) /* A character is being transmitted */\r
+#define _04_SCI_TRANSMIT_COMPLETE (0x04U) /* Character transfer has been completed */\r
+/* Parity error flag (PER) */\r
+#define _08_SCI_PARITY_ERROR (0x08U) /* A parity error has occurred */\r
+/* Framing error flag (FER) */\r
+#define _10_SCI_FRAME_ERROR (0x10U) /* A framing error has occurred */\r
+/* Overrun error flag (ORER) */\r
+#define _20_SCI_OVERRUN_ERROR (0x20U) /* An overrun error has occurred */\r
+\r
+/*\r
+ Smart card mode register (SCMR)\r
+*/\r
+/* Smart card interface mode select (SMIF) */\r
+#define _00_SCI_SERIAL_MODE (0x00U) /* Serial communications interface mode */\r
+#define _01_SCI_SMART_CARD_MODE (0x01U) /* Smart card interface mode */\r
+/* Transmitted / received data invert (SINV) */\r
+#define _00_SCI_DATA_INVERT_NONE (0x00U) /* Data is not inverted */\r
+#define _04_SCI_DATA_INVERTED (0x04U) /* Data is inverted */\r
+/* Transmitted / received data transfer direction (SDIR) */\r
+#define _00_SCI_DATA_LSB_FIRST (0x00U) /* Transfer data LSB first */\r
+#define _08_SCI_DATA_MSB_FIRST (0x08U) /* Transfer data MSB first */\r
+/* Base clock pulse 2 (BCP2) */\r
+#define _00_SCI_93_128_186_512_CLK (0x00U) /* 93, 128, 186, or 512 clock cycles */\r
+#define _80_SCI_32_64_256_372_CLK (0x80U) /* 32, 64, 256, or 372 clock cycles */\r
+#define _72_SCI_SCMR_DEFAULT (0x72U) /* Write default value of SCMR */\r
+\r
+/* \r
+ Serial extended mode register (SEMR)\r
+*/\r
+/* Asynchronous Mode Clock Source Select (ACS0) */\r
+#define _00_SCI_ASYNC_SOURCE_EXTERNAL (0x00U) /* External clock input */\r
+#define _01_SCI_ASYNC_SOURCE_TMR (0x01U) /* Logical AND of two clock cycles output from TMR */\r
+/* Asynchronous mode base clock select (ABCS) */\r
+#define _00_SCI_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */\r
+#define _10_SCI_8_BASE_CLOCK (0x10U) /* Selects 8 base clock cycles for 1 bit period */ \r
+/* Digital noise filter function enable (NFEN) */\r
+#define _00_SCI_NOISE_FILTER_DISABLE (0x00U) /* Noise filter is disabled */\r
+#define _20_SCI_NOISE_FILTER_ENABLE (0x20U) /* Noise filter is enabled */\r
+/* Asynchronous start bit edge detections select (RXDESEL) */\r
+#define _00_SCI_LOW_LEVEL_START_BIT (0x00U) /* Low level on RXDn pin selected as start bit */\r
+#define _80_SCI_FALLING_EDGE_START_BIT (0x80U) /* Falling edge on RXDn pin selected as start bit */\r
+\r
+/*\r
+ Noise filter setting register (SNFR)\r
+*/\r
+/* Noise filter clock select (NFCS) */\r
+#define _00_SCI_ASYNC_DIV_1 (0x00U) /* Clock signal divided by 1 is used with the noise filter */\r
+#define _01_SCI_IIC_DIV_1 (0x01U) /* Clock signal divided by 1 is used with the noise filter */\r
+#define _02_SCI_IIC_DIV_2 (0x02U) /* Clock signal divided by 2 is used with the noise filter */\r
+#define _03_SCI_IIC_DIV_4 (0x03U) /* Clock signal divided by 4 is used with the noise filter */\r
+#define _04_SCI_IIC_DIV_8 (0x04U) /* Clock signal divided by 8 is used with the noise filter */\r
+\r
+/*\r
+ I2C mode register 1 (SIMR1)\r
+*/\r
+/* Simple IIC mode select (IICM) */\r
+#define _00_SCI_SERIAL_SMART_CARD_MODE (0x00U) /* Serial or smart card mode */\r
+#define _01_SCI_IIC_MODE (0x01U) /* Simple IIC mode */\r
+\r
+/*\r
+ I2C mode register 2 (SIMR2)\r
+*/\r
+/* IIC interrupt mode select (IICINTM) */\r
+#define _00_SCI_ACK_NACK_INTERRUPTS (0x00U) /* Use ACK/NACK interrupts */\r
+#define _01_SCI_RX_TX_INTERRUPTS (0x01U) /* Use reception/transmission interrupts */\r
+/* Clock synchronization (IICCSC) */\r
+#define _00_SCI_NO_SYNCHRONIZATION (0x00U) /* No synchronization with the clock signal */\r
+#define _02_SCI_SYNCHRONIZATION (0x02U) /* Synchronization with the clock signal */\r
+/* ACK transmission data (IICACKT) */\r
+#define _00_SCI_ACK_TRANSMISSION (0x00U) /* ACK transmission */\r
+#define _20_SCI_NACK_TRANSMISSION (0x20U) /* NACK transmission and reception of ACK/NACK */\r
+\r
+/*\r
+ I2C mode register 3 (SIMR3)\r
+*/\r
+/* Start condition generation (IICSTAREQ) */\r
+#define _00_SCI_START_CONDITION_OFF (0x00U) /* Start condition is not generated */\r
+#define _01_SCI_START_CONDITION_ON (0x01U) /* Start condition is generated */\r
+/* Restart condition generation (IICRSTAREQ) */\r
+#define _00_SCI_RESTART_CONDITION_OFF (0x00U) /* Restart condition is not generated */\r
+#define _02_SCI_RESTART_CONDITION_ON (0x02U) /* Restart condition is generated */\r
+/* Stop condition generation (IICSTPREQ) */\r
+#define _00_SCI_STOP_CONDITION_OFF (0x00U) /* Stop condition is not generated */\r
+#define _04_SCI_STOP_CONDITION_ON (0x04U) /* Stop condition is generated */\r
+/* Issuing of start, restart, or sstop condition completed flag (IICSTIF) */\r
+#define _00_SCI_CONDITION_GENERATED (0x00U) /* No requests to generate conditions/conditions generated */\r
+#define _08_SCI_GENERATION_COMPLETED (0x08U) /* All request generation has been completed */\r
+/* SSDA output select (IICSDAS) */\r
+#define _00_SCI_SSDA_DATA_OUTPUT (0x00U) /* SSDA output is serial data output */\r
+#define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10U) /* SSDA output generates start, restart or stop condition */\r
+#define _20_SCI_SSDA_LOW_LEVEL (0x20U) /* SSDA output low level */\r
+#define _30_SCI_SSDA_HIGH_IMPEDANCE (0x30U) /* SSDA output high impedance */\r
+/* SSCL output select (IICSCLS) */\r
+#define _00_SCI_SSCL_CLOCK_OUTPUT (0x00U) /* SSCL output is serial clock output */\r
+#define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40U) /* SSCL output generates start, restart or stop condition */\r
+#define _80_SCI_SSCL_LOW_LEVEL (0x80U) /* SSCL output low level */\r
+#define _C0_SCI_SSCL_HIGH_IMPEDANCE (0xC0U) /* SSCL output high impedance */\r
+\r
+/*\r
+ I2C status register (SISR)\r
+*/\r
+/* ACK reception data flag (IICACKR) */\r
+#define _00_SCI_ACK_RECEIVED (0x00U) /* ACK received */\r
+#define _01_SCI_NACK_RECEIVED (0x01U) /* NACK received */\r
+\r
+/*\r
+ SPI mode register (SPMR)\r
+*/\r
+/* SS pin function enable (SSE) */\r
+#define _00_SCI_SS_PIN_DISABLE (0x00U) /* SS pin function disabled */\r
+#define _01_SCI_SS_PIN_ENABLE (0x01U) /* SS pin function enabled */\r
+/* CTS enable (CTSE) */\r
+#define _00_SCI_RTS (0x00U) /* RTS function is enabled */\r
+#define _02_SCI_CTS (0x02U) /* CTS function is disabled */\r
+/* Master slave select (MSS) */\r
+#define _00_SCI_SPI_MASTER (0x00U) /* Master mode */\r
+#define _04_SCI_SPI_SLAVE (0x04U) /* Slave mode */\r
+/* Mode fault flag (MFF) */\r
+#define _00_SCI_NO_MODE_FAULT (0x00U) /* No mode fault */\r
+#define _10_SCI_MODE_FAULT (0x10U) /* Mode fault */\r
+/* Clock polarity select (CKPOL) */\r
+#define _00_SCI_CLOCK_NOT_INVERTED (0x00U) /* Clock polarity is not inverted */\r
+#define _40_SCI_CLOCK_INVERTED (0x40U) /* Clock polarity is inverted */\r
+/* Clock phase select (CKPH) */\r
+#define _00_SCI_CLOCK_NOT_DELAYED (0x00U) /* Clock is not delayed */\r
+#define _80_SCI_CLOCK_DELAYED (0x80U) /* Clock is delayed */\r
+\r
+/*\r
+ Interrupt Source Priority Register n (IPRn)\r
+*/\r
+/* Interrupt Priority Level Select (IPR[3:0]) */\r
+#define _00_SCI_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */\r
+#define _01_SCI_PRIORITY_LEVEL1 (0x01U) /* Level 1 */\r
+#define _02_SCI_PRIORITY_LEVEL2 (0x02U) /* Level 2 */\r
+#define _03_SCI_PRIORITY_LEVEL3 (0x03U) /* Level 3 */\r
+#define _04_SCI_PRIORITY_LEVEL4 (0x04U) /* Level 4 */\r
+#define _05_SCI_PRIORITY_LEVEL5 (0x05U) /* Level 5 */\r
+#define _06_SCI_PRIORITY_LEVEL6 (0x06U) /* Level 6 */\r
+#define _07_SCI_PRIORITY_LEVEL7 (0x07U) /* Level 7 */\r
+#define _08_SCI_PRIORITY_LEVEL8 (0x08U) /* Level 8 */\r
+#define _09_SCI_PRIORITY_LEVEL9 (0x09U) /* Level 9 */\r
+#define _0A_SCI_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */\r
+#define _0B_SCI_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */\r
+#define _0C_SCI_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */\r
+#define _0D_SCI_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */\r
+#define _0E_SCI_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */\r
+#define _0F_SCI_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */\r
+\r
+/*\r
+ Transfer status control value\r
+*/\r
+/* Simple IIC Transmit Receive Flag */\r
+#define _80_SCI_IIC_TRANSMISSION (0x80U)\r
+#define _00_SCI_IIC_RECEPTION (0x00U)\r
+/* Simple IIC Start Stop Flag */\r
+#define _80_SCI_IIC_START_CYCLE (0x80U)\r
+#define _00_SCI_IIC_STOP_CYCLE (0x00U)\r
+/* Multiprocessor Asynchronous Communication Flag */\r
+#define _80_SCI_ID_TRANSMISSION_CYCLE (0x80U)\r
+#define _00_SCI_DATA_TRANSMISSION_CYCLE (0x00U)\r
+\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+void R_SCI1_Create(void);\r
+void R_SCI1_Start(void);\r
+void R_SCI1_Stop(void);\r
+MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num);\r
+MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num);\r
+static void r_sci1_callback_transmitend(void);\r
+static void r_sci1_callback_receiveend(void);\r
+static void r_sci1_callback_receiveerror(void);\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+\r
+/* Some of the code in this file is generated using "Code Generator" for e2 studio.\r
+ * Warnings exist in this module. */\r
+\r
+/* Exported functions used to transmit a number of bytes and wait for completion */\r
+MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num);\r
+\r
+/* Character is used to receive key presses from PC terminal */\r
+extern uint8_t g_rx_char;\r
+\r
+/* Flag used to control transmission to PC terminal */\r
+extern volatile uint8_t g_tx_flag;\r
+\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_sci_user.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file implements device driver for SCI module.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_sci.h"\r
+/* Start user code for include. Do not edit comment generated here */\r
+#include "rskrx113def.h"\r
+//_RB_#include "r_cg_cmt.h"\r
+/* End user code. Do not edit comment generated here */\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+extern uint8_t * gp_sci1_tx_address; /* SCI1 send buffer address */\r
+extern uint16_t g_sci1_tx_count; /* SCI1 send data number */\r
+extern uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */\r
+extern uint16_t g_sci1_rx_count; /* SCI1 receive data number */\r
+extern uint16_t g_sci1_rx_length; /* SCI1 receive data length */\r
+/* Start user code for global. Do not edit comment generated here */\r
+\r
+/* Global used to receive a character from the PC terminal */\r
+uint8_t g_rx_char;\r
+\r
+/* Flag used to control transmission to PC terminal */\r
+volatile uint8_t g_tx_flag = FALSE;\r
+\r
+/* Flag used locally to detect transmission complete */\r
+static volatile uint8_t sci1_txdone;\r
+\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_transmit_interrupt\r
+* Description : None\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TXI1\r
+#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1),fint)\r
+#else\r
+#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1))\r
+#endif\r
+static void r_sci1_transmit_interrupt(void)\r
+{\r
+ if (g_sci1_tx_count > 0U)\r
+ {\r
+ SCI1.TDR = *gp_sci1_tx_address;\r
+ gp_sci1_tx_address++;\r
+ g_sci1_tx_count--;\r
+ }\r
+ else \r
+ {\r
+ SCI1.SCR.BIT.TIE = 0U;\r
+ SCI1.SCR.BIT.TEIE = 1U;\r
+ }\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_transmitend_interrupt\r
+* Description : None\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TEI1\r
+#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1),fint)\r
+#else\r
+#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1))\r
+#endif\r
+static void r_sci1_transmitend_interrupt(void)\r
+{\r
+ /* Set TXD1 pin */\r
+ PORT1.PMR.BYTE &= 0xBFU;\r
+ SCI1.SCR.BIT.TIE = 0U;\r
+ SCI1.SCR.BIT.TE = 0U;\r
+ SCI1.SCR.BIT.TEIE = 0U;\r
+\r
+ r_sci1_callback_transmitend();\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_receive_interrupt\r
+* Description : None\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+#if FAST_INTERRUPT_VECTOR == VECT_SCI1_RXI1\r
+#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1),fint)\r
+#else\r
+#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1))\r
+#endif\r
+static void r_sci1_receive_interrupt(void)\r
+{\r
+ if (g_sci1_rx_length > g_sci1_rx_count)\r
+ {\r
+ *gp_sci1_rx_address = SCI1.RDR;\r
+ gp_sci1_rx_address++;\r
+ g_sci1_rx_count++;\r
+\r
+ if (g_sci1_rx_length == g_sci1_rx_count)\r
+ {\r
+ r_sci1_callback_receiveend();\r
+ }\r
+ }\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_receiveerror_interrupt\r
+* Description : None\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+#if FAST_INTERRUPT_VECTOR == VECT_SCI1_ERI1\r
+#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1),fint)\r
+#else\r
+#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1))\r
+#endif\r
+static void r_sci1_receiveerror_interrupt(void)\r
+{\r
+ uint8_t err_type;\r
+\r
+ r_sci1_callback_receiveerror();\r
+\r
+ /* Clear overrun, framing and parity error flags */\r
+ err_type = SCI1.SSR.BYTE;\r
+ SCI1.SSR.BYTE = err_type & 0xC7U;\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_callback_transmitend\r
+* Description : This function is a callback function when SCI1 finishes transmission.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+static void r_sci1_callback_transmitend(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ sci1_txdone = TRUE;\r
+\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_callback_receiveend\r
+* Description : This function is a callback function when SCI1 finishes reception.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+static void r_sci1_callback_receiveend(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ /* Check the contents of g_rx_char */\r
+ if ('z' == g_rx_char)\r
+ {\r
+ /* Stop the timer used to control transmission to PC terminal*/\r
+//_RB_ R_CMT0_Stop();\r
+\r
+ /* Turn off LED0 and turn on LED1 to indicate serial transmission\r
+ inactive */\r
+ LED0 = LED_OFF;\r
+ LED1 = LED_ON;\r
+ }\r
+ else\r
+ {\r
+ /* Start the timer used to control transmission to PC terminal*/\r
+//_RB_ R_CMT0_Start();\r
+\r
+ /* Turn on LED0 and turn off LED1 to indicate serial transmission\r
+ active */\r
+ LED0 = LED_ON;\r
+ LED1 = LED_OFF;\r
+ }\r
+\r
+ /* Set up SCI1 receive buffer again */\r
+ R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
+\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+/***********************************************************************************************************************\r
+* Function Name: r_sci1_callback_receiveerror\r
+* Description : This function is a callback function when SCI1 reception encounters error.\r
+* Arguments : None\r
+* Return Value : None\r
+***********************************************************************************************************************/\r
+static void r_sci1_callback_receiveerror(void)\r
+{\r
+ /* Start user code. Do not edit comment generated here */\r
+ /* End user code. Do not edit comment generated here */\r
+}\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/***********************************************************************************************************************\r
+ * Function Name: R_SCI1_AsyncTransmit\r
+ * Description : This function sends SCI1 data and waits for the transmit end flag.\r
+ * Arguments : tx_buf -\r
+ * transfer buffer pointer\r
+ * tx_num -\r
+ * buffer size\r
+ * Return Value : status -\r
+ * MD_OK or MD_ARGERROR\r
+ ***********************************************************************************************************************/\r
+MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num)\r
+{\r
+ MD_STATUS status = MD_OK;\r
+\r
+ /* clear the flag before initiating a new transmission */\r
+ sci1_txdone = FALSE;\r
+\r
+ /* Send the data using the API */\r
+ status = R_SCI1_Serial_Send(tx_buf, tx_num);\r
+\r
+ /* Wait for the transmit end flag */\r
+ while (FALSE == sci1_txdone)\r
+ {\r
+ /* Wait */\r
+ }\r
+ return (status);\r
+}\r
+/***********************************************************************************************************************\r
+ * End of function R_SCI1_AsyncTransmit\r
+ ***********************************************************************************************************************/\r
+\r
+/* End user code. Do not edit comment generated here */\r
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_stacksct.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : Setting of Stack area.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef _STACKSCT_H\r
+#define _STACKSCT_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+#pragma stacksize su=0x100\r
+#pragma stacksize si=0x300\r
+\r
+\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_userdefine.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file includes user definition.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef _USER_DEF_H\r
+#define _USER_DEF_H\r
+\r
+/***********************************************************************************************************************\r
+User definitions\r
+***********************************************************************************************************************/\r
+#define FAST_INTERRUPT_VECTOR 0\r
+\r
+/* Start user code for function. Do not edit comment generated here */\r
+#define TRUE (1)\r
+#define FALSE (0)\r
+/* End user code. Do not edit comment generated here */\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_vect.h\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file contains definition of vector.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+#ifndef _VECT_H\r
+#define _VECT_H\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions (Register bit)\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Macro definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Typedef definitions\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Global functions\r
+***********************************************************************************************************************/\r
+/* Undefined */\r
+#pragma interrupt (r_undefined_exception)\r
+void r_undefined_exception(void);\r
+\r
+/* Reserved */\r
+#pragma interrupt (r_reserved_exception)\r
+void r_reserved_exception(void);\r
+\r
+/* NMI */\r
+#pragma interrupt (r_nmi_exception)\r
+void r_nmi_exception(void);\r
+\r
+/* BRK */\r
+#pragma interrupt (r_brk_exception(vect=0))\r
+void r_brk_exception(void);\r
+\r
+/*;<<VECTOR DATA START (POWER ON RESET)>> */\r
+/*;Power On Reset PC */\r
+extern void PowerON_Reset(void);\r
+/*;<<VECTOR DATA END (POWER ON RESET)>> */\r
+\r
+#endif
\ No newline at end of file
--- /dev/null
+/***********************************************************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
+* applicable laws, including copyright laws. \r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
+* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+* File Name : r_cg_vecttbl.c\r
+* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* Description : This file initializes the vector table.\r
+* Creation Date: 21/09/2015\r
+***********************************************************************************************************************/\r
+\r
+/***********************************************************************************************************************\r
+Pragma directive\r
+***********************************************************************************************************************/\r
+/* Start user code for pragma. Do not edit comment generated here */\r
+/* End user code. Do not edit comment generated here */\r
+\r
+/***********************************************************************************************************************\r
+Includes\r
+***********************************************************************************************************************/\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_vect.h"\r
+#include "r_cg_userdefine.h"\r
+\r
+/***********************************************************************************************************************\r
+Global variables and functions\r
+***********************************************************************************************************************/\r
+\r
+#pragma section C FIXEDVECT\r
+\r
+void (*const Fixed_Vectors[])(void) = {\r
+/*;0xffffffd0 Exception(Supervisor Instruction) */\r
+ r_undefined_exception,\r
+/*;0xffffffd4 Reserved */\r
+ r_undefined_exception,\r
+/*;0xffffffd8 Reserved */\r
+ r_reserved_exception,\r
+/*;0xffffffdc Exception(Undefined Instruction) */\r
+ r_undefined_exception,\r
+/*;0xffffffe0 Reserved */\r
+ r_reserved_exception,\r
+/*;0xffffffe4 Reserved */\r
+ r_reserved_exception,\r
+/*;0xffffffe8 Reserved */\r
+ r_reserved_exception,\r
+/*;0xffffffec Reserved */\r
+ r_reserved_exception,\r
+/*;0xfffffff0 Reserved */\r
+ r_reserved_exception,\r
+/*;0xfffffff4 Reserved */\r
+ r_reserved_exception,\r
+/*;0xfffffff8 NMI */\r
+ r_nmi_exception,\r
+/*;0xfffffffc RESET */\r
+/*;<<VECTOR DATA START (POWER ON RESET)>> */\r
+/*;Power On Reset PC */\r
+ /*(void*)*/ PowerON_Reset\r
+/*;<<VECTOR DATA END (POWER ON RESET)>> */\r
+};\r
+\r
+/* MDE register (Single Chip Mode) */\r
+#pragma address _MDEreg=0xffffff80\r
+#ifdef __BIG\r
+ /* Big endian*/\r
+ const unsigned long _MDEreg = 0xfffffff8;\r
+#else\r
+ /* Little endian */\r
+ const unsigned long _MDEreg = 0xffffffff;\r
+#endif\r
+\r
+/* Set option bytes */\r
+#pragma address OFS0_location = 0xFFFFFF8CUL\r
+#pragma address OFS1_location = 0xFFFFFF88UL\r
+volatile const uint32_t OFS0_location = 0xFFFFFFFFUL;\r
+volatile const uint32_t OFS1_location = 0xFFFFFFFFUL;\r
+\r
+/* Start user code for adding. Do not edit comment generated here */\r
+/* ID codes (Default) */\r
+#pragma address id_code=0xffffffa0\r
+const unsigned long id_code[4] = {\r
+ 0xffffffff,\r
+ 0xffffffff,\r
+ 0xffffffff,\r
+ 0xffffffff,\r
+};\r
+/* End user code. Do not edit comment generated here */\r
+\r
--- /dev/null
+\r
+/*********************************************************************************\r
+*\r
+* Device : RX/RX100/RX113\r
+*\r
+* File Name : iodefine.h\r
+*\r
+* Abstract : Definition of I/O Register.\r
+*\r
+* History : 0.4 (2013-11-18) [Hardware Manual Revision : 0.40]\r
+* : 0.5 (2014-01-05) [Hardware Manual Revision : 0.50]\r
+* : 1.0 (2014-07-22) [Hardware Manual Revision : 1.00]\r
+*\r
+* NOTE : THIS IS A TYPICAL EXAMPLE.\r
+*\r
+* Copyright (C) 2013 (2014) Renesas Electronics Corporation and\r
+* Renesas Solutions Corp. All rights reserved.\r
+*\r
+*********************************************************************************/\r
+/********************************************************************************/\r
+/* */\r
+/* DESCRIPTION : Definition of ICU Register */\r
+/* CPU TYPE : RX113 */\r
+/* */\r
+/* Usage : IR,DTCER,IER,IPR of ICU Register */\r
+/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */\r
+/* The bit access operation is "Bit_Name(interrupt source,name)". */\r
+/* A part of the name can be omitted. */\r
+/* for example : */\r
+/* IR(MTU0,TGIA0) = 0; expands to : */\r
+/* ICU.IR[114].BIT.IR = 0; */\r
+/* */\r
+/* DTCE(ICU,IRQ0) = 1; expands to : */\r
+/* ICU.DTCER[64].BIT.DTCE = 1; */\r
+/* */\r
+/* IEN(CMT0,CMI0) = 1; expands to : */\r
+/* ICU.IER[0x03].BIT.IEN4 = 1; */\r
+/* */\r
+/* Usage : #pragma interrupt Function_Identifier(vect=**) */\r
+/* The number of vector is "(interrupt source, name)". */\r
+/* for example : */\r
+/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */\r
+/* #pragma interrupt INT_IRQ0(vect=64) */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */\r
+/* #pragma interrupt INT_CMT0_CMI0(vect=28) */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */\r
+/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */\r
+/* */\r
+/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */\r
+/* The bit access operation is "MSTP(name)". */\r
+/* The name that can be used is a macro name defined with "iodefine.h". */\r
+/* for example : */\r
+/* MSTP(TMR2) = 0; // TMR23,TMR2,TMR3 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */\r
+/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */\r
+/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */\r
+/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */\r
+/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */\r
+/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */\r
+/* */\r
+/* */\r
+/********************************************************************************/\r
+#ifndef __RX113IODEFINE_HEADER__\r
+#define __RX113IODEFINE_HEADER__\r
+#pragma bit_order left\r
+#pragma unpack\r
+struct st_bsc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char STSCLR:1;\r
+ } BIT;\r
+ } BERCLR;\r
+ char wk0[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TOEN:1;\r
+ unsigned char IGAEN:1;\r
+ } BIT;\r
+ } BEREN;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MST:3;\r
+ unsigned char :2;\r
+ unsigned char TO:1;\r
+ unsigned char IA:1;\r
+ } BIT;\r
+ } BERSR1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADDR:13;\r
+ } BIT;\r
+ } BERSR2;\r
+ char wk3[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short BPFB:2;\r
+ unsigned short :2;\r
+ unsigned short BPGB:2;\r
+ unsigned short BPIB:2;\r
+ unsigned short BPRO:2;\r
+ unsigned short BPRA:2;\r
+ } BIT;\r
+ } BUSPRI;\r
+};\r
+\r
+struct st_cac {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char CFME:1;\r
+ } BIT;\r
+ } CACR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char EDGES:2;\r
+ unsigned char TCSS:2;\r
+ unsigned char FMCS:3;\r
+ unsigned char CACREFE:1;\r
+ } BIT;\r
+ } CACR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DFS:2;\r
+ unsigned char RCDS:2;\r
+ unsigned char RSCS:3;\r
+ unsigned char RPS:1;\r
+ } BIT;\r
+ } CACR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char OVFFCL:1;\r
+ unsigned char MENDFCL:1;\r
+ unsigned char FERRFCL:1;\r
+ unsigned char :1;\r
+ unsigned char OVFIE:1;\r
+ unsigned char MENDIE:1;\r
+ unsigned char FERRIE:1;\r
+ } BIT;\r
+ } CAICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char OVFF:1;\r
+ unsigned char MENDF:1;\r
+ unsigned char FERRF:1;\r
+ } BIT;\r
+ } CASTR;\r
+ char wk0[1];\r
+ unsigned short CAULVR;\r
+ unsigned short CALLVR;\r
+ unsigned short CACNTBR;\r
+};\r
+\r
+struct st_cmpb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char CPB1INI:1;\r
+ unsigned char :3;\r
+ unsigned char CPB0INI:1;\r
+ } BIT;\r
+ } CPBCNT1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char CPB1WCP:1;\r
+ unsigned char :3;\r
+ unsigned char CPB0WCP:1;\r
+ } BIT;\r
+ } CPBCNT2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CPB1OUT:1;\r
+ unsigned char :3;\r
+ unsigned char CPB0OUT:1;\r
+ } BIT;\r
+ } CPBFLG;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CPB1INTPL:1;\r
+ unsigned char CPB1INTEG:1;\r
+ unsigned char CPB1INTEN:1;\r
+ unsigned char :1;\r
+ unsigned char CPB0INTPL:1;\r
+ unsigned char CPB0INTEG:1;\r
+ unsigned char CPB0INTEN:1;\r
+ } BIT;\r
+ } CPBINT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CPB1F:2;\r
+ unsigned char :1;\r
+ unsigned char CPB1FEN:1;\r
+ unsigned char CPB0F:2;\r
+ unsigned char :1;\r
+ unsigned char CPB0FEN:1;\r
+ } BIT;\r
+ } CPBF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char CPBSPDMD:1;\r
+ } BIT;\r
+ } CPBMD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char CPB1VRF:1;\r
+ unsigned char :3;\r
+ unsigned char CPB0VRF:1;\r
+ } BIT;\r
+ } CPBREF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char CPB1OP:1;\r
+ unsigned char CPB1OE:1;\r
+ unsigned char :2;\r
+ unsigned char CPB0OP:1;\r
+ unsigned char CPB0OE:1;\r
+ } BIT;\r
+ } CPBOCR;\r
+};\r
+\r
+struct st_cmt {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :14;\r
+ unsigned short STR1:1;\r
+ unsigned short STR0:1;\r
+ } BIT;\r
+ } CMSTR0;\r
+ char wk0[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :14;\r
+ unsigned short STR3:1;\r
+ unsigned short STR2:1;\r
+ } BIT;\r
+ } CMSTR1;\r
+};\r
+\r
+struct st_cmt0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :9;\r
+ unsigned short CMIE:1;\r
+ unsigned short :4;\r
+ unsigned short CKS:2;\r
+ } BIT;\r
+ } CMCR;\r
+ unsigned short CMCNT;\r
+ unsigned short CMCOR;\r
+};\r
+\r
+struct st_crc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DORCLR:1;\r
+ unsigned char :4;\r
+ unsigned char LMS:1;\r
+ unsigned char GPS:2;\r
+ } BIT;\r
+ } CRCCR;\r
+ unsigned char CRCDIR;\r
+ unsigned short CRCDOR;\r
+};\r
+\r
+struct st_ctsu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char CTSUINIT:1;\r
+ unsigned char CTSUIOC:1;\r
+ unsigned char CTSUSNZ:1;\r
+ unsigned char CTSUCAP:1;\r
+ unsigned char CTSUSTRT:1;\r
+ } BIT;\r
+ } CTSUCR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CTSUMD:2;\r
+ unsigned char CTSUCLK:2;\r
+ unsigned char CTSUATUNE1:1;\r
+ unsigned char CTSUATUNE0:1;\r
+ unsigned char CTSUCSW:1;\r
+ unsigned char CTSUPON:1;\r
+ } BIT;\r
+ } CTSUCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CTSUSOFF:1;\r
+ unsigned char CTSUPRMODE:2;\r
+ unsigned char CTSUPRRATIO:4;\r
+ } BIT;\r
+ } CTSUSDPRS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CTSUSST:8;\r
+ } BIT;\r
+ } CTSUSST;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char CTSUMCH0:4;\r
+ } BIT;\r
+ } CTSUMCH0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char CTSUMCH1:4;\r
+ } BIT;\r
+ } CTSUMCH1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CTSUCHAC07:1;\r
+ unsigned char CTSUCHAC06:1;\r
+ unsigned char CTSUCHAC05:1;\r
+ unsigned char CTSUCHAC04:1;\r
+ unsigned char CTSUCHAC03:1;\r
+ unsigned char CTSUCHAC02:1;\r
+ unsigned char CTSUCHAC01:1;\r
+ unsigned char CTSUCHAC00:1;\r
+ } BIT;\r
+ } CTSUCHAC0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char CTSUCHAC13:1;\r
+ unsigned char CTSUCHAC12:1;\r
+ unsigned char CTSUCHAC11:1;\r
+ unsigned char CTSUCHAC10:1;\r
+ } BIT;\r
+ } CTSUCHAC1;\r
+ char wk0[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CTSUCHTRC07:1;\r
+ unsigned char CTSUCHTRC06:1;\r
+ unsigned char CTSUCHTRC05:1;\r
+ unsigned char CTSUCHTRC04:1;\r
+ unsigned char CTSUCHTRC03:1;\r
+ unsigned char CTSUCHTRC02:1;\r
+ unsigned char CTSUCHTRC01:1;\r
+ unsigned char CTSUCHTRC00:1;\r
+ } BIT;\r
+ } CTSUCHTRC0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char CTSUCHTRC13:1;\r
+ unsigned char CTSUCHTRC12:1;\r
+ unsigned char CTSUCHTRC11:1;\r
+ unsigned char CTSUCHTRC10:1;\r
+ } BIT;\r
+ } CTSUCHTRC1;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char CTSUSSCNT:2;\r
+ unsigned char :2;\r
+ unsigned char CTSUSSMOD:2;\r
+ } BIT;\r
+ } CTSUDCLKC;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CTSUPS:1;\r
+ unsigned char CTSUROVF:1;\r
+ unsigned char CTSUSOVF:1;\r
+ unsigned char CTSUDTSR:1;\r
+ unsigned char :1;\r
+ unsigned char CTSUSTC:3;\r
+ } BIT;\r
+ } CTSUST;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short CTSUSSDIV:4;\r
+ } BIT;\r
+ } CTSUSSC;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CTSUSNUM:6;\r
+ unsigned short CTSUSO:10;\r
+ } BIT;\r
+ } CTSUSO0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :1;\r
+ unsigned short CTSUICOG:2;\r
+ unsigned short CTSUSDPA:5;\r
+ unsigned short CTSURICOA:8;\r
+ } BIT;\r
+ } CTSUSO1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CTSUSC:16;\r
+ } BIT;\r
+ } CTSUSC;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CTSURC:16;\r
+ } BIT;\r
+ } CTSURC;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CTSUICOMP:1;\r
+ } BIT;\r
+ } CTSUERRS;\r
+};\r
+\r
+struct st_da {\r
+ unsigned short DADR0;\r
+ unsigned short DADR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DAOE1:1;\r
+ unsigned char DAOE0:1;\r
+ } BIT;\r
+ } DACR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DPSEL:1;\r
+ } BIT;\r
+ } DADPR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DAADST:1;\r
+ } BIT;\r
+ } DAADSCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char REF:3;\r
+ } BIT;\r
+ } DAVREFCR;\r
+};\r
+\r
+struct st_doc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char DOPCFCL:1;\r
+ unsigned char DOPCF:1;\r
+ unsigned char DOPCIE:1;\r
+ unsigned char :1;\r
+ unsigned char DCSEL:1;\r
+ unsigned char OMS:2;\r
+ } BIT;\r
+ } DOCR;\r
+ char wk0[1];\r
+ unsigned short DODIR;\r
+ unsigned short DODSR;\r
+};\r
+\r
+struct st_dtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char RRS:1;\r
+ } BIT;\r
+ } DTCCR;\r
+ char wk0[3];\r
+ void *DTCVBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SHORT:1;\r
+ } BIT;\r
+ } DTCADMOD;\r
+ char wk1[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCST:1;\r
+ } BIT;\r
+ } DTCST;\r
+ char wk2[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ACT:1;\r
+ unsigned short :7;\r
+ unsigned short VECN:8;\r
+ } BIT;\r
+ } DTCSTS;\r
+};\r
+\r
+struct st_elc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ELCON:1;\r
+ } BIT;\r
+ } ELCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ELS:8;\r
+ } BIT;\r
+ } ELSR[26];\r
+ char wk0[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTU3MD:2;\r
+ unsigned char MTU2MD:2;\r
+ unsigned char MTU1MD:2;\r
+ } BIT;\r
+ } ELOPA;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char MTU4MD:2;\r
+ } BIT;\r
+ } ELOPB;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char CMT1MD:2;\r
+ } BIT;\r
+ } ELOPC;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char TMR2MD:2;\r
+ unsigned char :2;\r
+ unsigned char TMR0MD:2;\r
+ } BIT;\r
+ } ELOPD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PGR7:1;\r
+ unsigned char PGR6:1;\r
+ unsigned char PGR5:1;\r
+ unsigned char PGR4:1;\r
+ unsigned char PGR3:1;\r
+ unsigned char PGR2:1;\r
+ unsigned char PGR1:1;\r
+ unsigned char PGR0:1;\r
+ } BIT;\r
+ } PGR1;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PGCO:3;\r
+ unsigned char :1;\r
+ unsigned char PGCOVE:1;\r
+ unsigned char PGCI:2;\r
+ } BIT;\r
+ } PGC1;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PDBF7:1;\r
+ unsigned char PDBF6:1;\r
+ unsigned char PDBF5:1;\r
+ unsigned char PDBF4:1;\r
+ unsigned char PDBF3:1;\r
+ unsigned char PDBF2:1;\r
+ unsigned char PDBF1:1;\r
+ unsigned char PDBF0:1;\r
+ } BIT;\r
+ } PDBF1;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSM:2;\r
+ unsigned char PSP:2;\r
+ unsigned char PSB:3;\r
+ } BIT;\r
+ } PEL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSM:2;\r
+ unsigned char PSP:2;\r
+ unsigned char PSB:3;\r
+ } BIT;\r
+ } PEL1;\r
+ char wk4[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char WI:1;\r
+ unsigned char WE:1;\r
+ unsigned char :5;\r
+ unsigned char SEG:1;\r
+ } BIT;\r
+ } ELSEGR;\r
+};\r
+\r
+struct st_flash {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DFLEN:1;\r
+ } BIT;\r
+ } DFLCTL;\r
+ char wk0[31];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short SASMF:1;\r
+ } BIT;\r
+ } FSCMR;\r
+ unsigned short FAWSMR;\r
+ unsigned short FAWEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SAS:2;\r
+ unsigned char :1;\r
+ unsigned char PCKA:5;\r
+ } BIT;\r
+ } FISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OPST:1;\r
+ unsigned char :4;\r
+ unsigned char CMD:3;\r
+ } BIT;\r
+ } FEXCR;\r
+ unsigned short FEAML;\r
+// char wk1[1];\r
+ unsigned char FEAMH;\r
+ char wk2[5];\r
+ unsigned char FPR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char PERR:1;\r
+ } BIT;\r
+ } FPSR;\r
+ unsigned short FRBL;\r
+ unsigned short FRBH;\r
+ char wk3[16058];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FMS2:1;\r
+ unsigned char LVPE:1;\r
+ unsigned char :1;\r
+ unsigned char FMS1:1;\r
+ unsigned char RPDIS:1;\r
+ unsigned char :1;\r
+ unsigned char FMS0:1;\r
+ } BIT;\r
+ } FPMCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char EXS:1;\r
+ } BIT;\r
+ } FASR;\r
+ unsigned short FSARL;\r
+// char wk4[1];\r
+ unsigned char FSARH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OPST:1;\r
+ unsigned char STOP:1;\r
+ unsigned char :1;\r
+ unsigned char DRC:1;\r
+ unsigned char CMD:4;\r
+ } BIT;\r
+ } FCR;\r
+ unsigned short FEARL;\r
+ unsigned char FEARH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char FRESET:1;\r
+ } BIT;\r
+ } FRESETR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char EILGLERR:1;\r
+ unsigned char ILGLERR:1;\r
+ unsigned char BCERR:1;\r
+ unsigned char :1;\r
+ unsigned char PRGERR:1;\r
+ unsigned char ERERR:1;\r
+ } BIT;\r
+ } FSTATR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char EXRDY:1;\r
+ unsigned char FRDY:1;\r
+ unsigned char :4;\r
+ unsigned char DRRDY:1;\r
+ } BIT;\r
+ } FSTATR1;\r
+ unsigned short FWBL;\r
+ unsigned short FWBH;\r
+ char wk5[34];\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short FEKEY:8;\r
+// unsigned short FENTRYD:1;\r
+// unsigned short :6;\r
+// unsigned short FENTRY0:1;\r
+// } BIT;\r
+ } FENTRYR;\r
+};\r
+\r
+struct st_icu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IR:1;\r
+ } BIT;\r
+ } IR[250];\r
+ char wk0[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char DTCE:1;\r
+ } BIT;\r
+ } DTCER[249];\r
+ char wk1[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IEN7:1;\r
+ unsigned char IEN6:1;\r
+ unsigned char IEN5:1;\r
+ unsigned char IEN4:1;\r
+ unsigned char IEN3:1;\r
+ unsigned char IEN2:1;\r
+ unsigned char IEN1:1;\r
+ unsigned char IEN0:1;\r
+ } BIT;\r
+ } IER[32];\r
+ char wk2[192];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SWINT:1;\r
+ } BIT;\r
+ } SWINTR;\r
+ char wk3[15];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FIEN:1;\r
+ unsigned short :7;\r
+ unsigned short FVCT:8;\r
+ } BIT;\r
+ } FIR;\r
+ char wk4[14];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IPR:4;\r
+ } BIT;\r
+ } IPR[250];\r
+ char wk5[262];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char IRQMD:2;\r
+ } BIT;\r
+ } IRQCR[8];\r
+ char wk6[8];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char FLTEN7:1;\r
+ unsigned char FLTEN6:1;\r
+ unsigned char FLTEN5:1;\r
+ unsigned char FLTEN4:1;\r
+ unsigned char FLTEN3:1;\r
+ unsigned char FLTEN2:1;\r
+ unsigned char FLTEN1:1;\r
+ unsigned char FLTEN0:1;\r
+ } BIT;\r
+ } IRQFLTE0;\r
+ char wk7[3];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short FCLKSEL7:2;\r
+ unsigned short FCLKSEL6:2;\r
+ unsigned short FCLKSEL5:2;\r
+ unsigned short FCLKSEL4:2;\r
+ unsigned short FCLKSEL3:2;\r
+ unsigned short FCLKSEL2:2;\r
+ unsigned short FCLKSEL1:2;\r
+ unsigned short FCLKSEL0:2;\r
+ } BIT;\r
+ } IRQFLTC0;\r
+ char wk8[106];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2ST:1;\r
+ unsigned char LVD1ST:1;\r
+ unsigned char IWDTST:1;\r
+ unsigned char :1;\r
+ unsigned char OSTST:1;\r
+ unsigned char NMIST:1;\r
+ } BIT;\r
+ } NMISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2EN:1;\r
+ unsigned char LVD1EN:1;\r
+ unsigned char IWDTEN:1;\r
+ unsigned char :1;\r
+ unsigned char OSTEN:1;\r
+ unsigned char NMIEN:1;\r
+ } BIT;\r
+ } NMIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2CLR:1;\r
+ unsigned char LVD1CLR:1;\r
+ unsigned char IWDTCLR:1;\r
+ unsigned char :1;\r
+ unsigned char OSTCLR:1;\r
+ unsigned char NMICLR:1;\r
+ } BIT;\r
+ } NMICLR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char NMIMD:1;\r
+ } BIT;\r
+ } NMICR;\r
+ char wk9[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char NFLTEN:1;\r
+ } BIT;\r
+ } NMIFLTE;\r
+ char wk10[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char NFCLKSEL:2;\r
+ } BIT;\r
+ } NMIFLTC;\r
+};\r
+\r
+struct st_irda {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IRE:1;\r
+ unsigned char IRCKS:3;\r
+ unsigned char IRTXINV:1;\r
+ unsigned char IRRXINV:1;\r
+ } BIT;\r
+ } IRCR;\r
+};\r
+\r
+struct st_iwdt {\r
+ unsigned char IWDTRR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short RPSS:2;\r
+ unsigned short :2;\r
+ unsigned short RPES:2;\r
+ unsigned short CKS:4;\r
+ unsigned short :2;\r
+ unsigned short TOPS:2;\r
+ } BIT;\r
+ } IWDTCR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short REFEF:1;\r
+ unsigned short UNDFF:1;\r
+ unsigned short CNTVAL:14;\r
+ } BIT;\r
+ } IWDTSR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTIRQS:1;\r
+ } BIT;\r
+ } IWDTRCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SLCSTP:1;\r
+ } BIT;\r
+ } IWDTCSTPR;\r
+};\r
+\r
+struct st_lcdc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MDSET:2;\r
+ unsigned char LWAVE:1;\r
+ unsigned char LDTY:3;\r
+ unsigned char LBAS:2;\r
+ } BIT;\r
+ } LCDM0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LCDON:1;\r
+ unsigned char SCOC:1;\r
+ unsigned char VLCON:1;\r
+ unsigned char BLON:1;\r
+ unsigned char LCDSEL:1;\r
+ unsigned char :2;\r
+ unsigned char LCDVLM:1;\r
+ } BIT;\r
+ } LCDM1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LCDC0:6;\r
+ } BIT;\r
+ } LCDC0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char VLCD:5;\r
+ } BIT;\r
+ } VLCD;\r
+ char wk0[60];\r
+ unsigned char SEG00;\r
+ unsigned char SEG01;\r
+ unsigned char SEG02;\r
+ unsigned char SEG03;\r
+ unsigned char SEG04;\r
+ unsigned char SEG05;\r
+ unsigned char SEG06;\r
+ unsigned char SEG07;\r
+ unsigned char SEG08;\r
+ unsigned char SEG09;\r
+ unsigned char SEG10;\r
+ unsigned char SEG11;\r
+ unsigned char SEG12;\r
+ unsigned char SEG13;\r
+ unsigned char SEG14;\r
+ unsigned char SEG15;\r
+ unsigned char SEG16;\r
+ unsigned char SEG17;\r
+ unsigned char SEG18;\r
+ unsigned char SEG19;\r
+ unsigned char SEG20;\r
+ unsigned char SEG21;\r
+ unsigned char SEG22;\r
+ unsigned char SEG23;\r
+ unsigned char SEG24;\r
+ unsigned char SEG25;\r
+ unsigned char SEG26;\r
+ unsigned char SEG27;\r
+ unsigned char SEG28;\r
+ unsigned char SEG29;\r
+ unsigned char SEG30;\r
+ unsigned char SEG31;\r
+ unsigned char SEG32;\r
+ unsigned char SEG33;\r
+ unsigned char SEG34;\r
+ unsigned char SEG35;\r
+ unsigned char SEG36;\r
+ unsigned char SEG37;\r
+ unsigned char SEG38;\r
+ unsigned char SEG39;\r
+};\r
+\r
+struct st_mpc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B0WI:1;\r
+ unsigned char PFSWE:1;\r
+ } BIT;\r
+ } PWPR;\r
+ char wk0[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P02PFS;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P04PFS;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P07PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P10PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P11PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P12PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P13PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P14PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P15PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P16PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P17PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P20PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P21PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P22PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P23PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P24PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P25PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P26PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P27PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P30PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P31PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P32PFS;\r
+ char wk3[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ } BIT;\r
+ } P35PFS;\r
+ char wk4[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P40PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P41PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P42PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P43PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P44PFS;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P46PFS;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P50PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P51PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P52PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P53PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P54PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P55PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } P56PFS;\r
+ char wk7[25];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P90PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P91PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } P92PFS;\r
+ char wk8[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PA7PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PB7PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PC7PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PD4PFS;\r
+ char wk9[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE0PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE1PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE3PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE4PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE5PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ unsigned char ISEL:1;\r
+ unsigned char :1;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PE7PFS;\r
+ char wk10[6];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PF6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PF7PFS;\r
+ char wk11[16];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ0PFS;\r
+ char wk12[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ2PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char PSEL:5;\r
+ } BIT;\r
+ } PJ3PFS;\r
+ char wk13[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ6PFS;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ASEL:1;\r
+ } BIT;\r
+ } PJ7PFS;\r
+};\r
+\r
+struct st_mtu {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OE4D:1;\r
+ unsigned char OE4C:1;\r
+ unsigned char OE3D:1;\r
+ unsigned char OE4B:1;\r
+ unsigned char OE4A:1;\r
+ unsigned char OE3B:1;\r
+ } BIT;\r
+ } TOER;\r
+ char wk0[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BDC:1;\r
+ unsigned char N:1;\r
+ unsigned char P:1;\r
+ unsigned char FB:1;\r
+ unsigned char WF:1;\r
+ unsigned char VF:1;\r
+ unsigned char UF:1;\r
+ } BIT;\r
+ } TGCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PSYE:1;\r
+ unsigned char :2;\r
+ unsigned char TOCL:1;\r
+ unsigned char TOCS:1;\r
+ unsigned char OLSN:1;\r
+ unsigned char OLSP:1;\r
+ } BIT;\r
+ } TOCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BF:2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOCR2;\r
+ char wk1[4];\r
+ unsigned short TCDR;\r
+ unsigned short TDDR;\r
+ char wk2[8];\r
+ unsigned short TCNTS;\r
+ unsigned short TCBR;\r
+ char wk3[12];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char T3AEN:1;\r
+ unsigned char T3ACOR:3;\r
+ unsigned char T4VEN:1;\r
+ unsigned char T4VCOR:3;\r
+ } BIT;\r
+ } TITCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char T3ACNT:3;\r
+ unsigned char :1;\r
+ unsigned char T4VCNT:3;\r
+ } BIT;\r
+ } TITCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char BTE:2;\r
+ } BIT;\r
+ } TBTER;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TDER:1;\r
+ } BIT;\r
+ } TDER;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char OLS3N:1;\r
+ unsigned char OLS3P:1;\r
+ unsigned char OLS2N:1;\r
+ unsigned char OLS2P:1;\r
+ unsigned char OLS1N:1;\r
+ unsigned char OLS1P:1;\r
+ } BIT;\r
+ } TOLBR;\r
+ char wk6[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCE:1;\r
+ unsigned char :6;\r
+ unsigned char WRE:1;\r
+ } BIT;\r
+ } TWCR;\r
+ char wk7[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CST4:1;\r
+ unsigned char CST3:1;\r
+ unsigned char :3;\r
+ unsigned char CST2:1;\r
+ unsigned char CST1:1;\r
+ unsigned char CST0:1;\r
+ } BIT;\r
+ } TSTR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SYNC4:1;\r
+ unsigned char SYNC3:1;\r
+ unsigned char :3;\r
+ unsigned char SYNC2:1;\r
+ unsigned char SYNC1:1;\r
+ unsigned char SYNC0:1;\r
+ } BIT;\r
+ } TSYR;\r
+ char wk8[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char RWE:1;\r
+ } BIT;\r
+ } TRWER;\r
+};\r
+\r
+struct st_mtu0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[111];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char BFE:1;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk1[16];\r
+ unsigned short TGRE;\r
+ unsigned short TGRF;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TGIEF:1;\r
+ unsigned char TGIEE:1;\r
+ } BIT;\r
+ } TIER2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+};\r
+\r
+struct st_mtu1 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[238];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CCLR:2;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk3[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char I2BE:1;\r
+ unsigned char I2AE:1;\r
+ unsigned char I1BE:1;\r
+ unsigned char I1AE:1;\r
+ } BIT;\r
+ } TICCR;\r
+};\r
+\r
+struct st_mtu2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk0[365];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char CCLR:2;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIOR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEU:1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char :2;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ unsigned short TCNT;\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+};\r
+\r
+struct st_mtu3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char :2;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk3[7];\r
+ unsigned short TCNT;\r
+ char wk4[6];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk5[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk6[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk8[90];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu4 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CCLR:3;\r
+ unsigned char CKEG:2;\r
+ unsigned char TPSC:3;\r
+ } BIT;\r
+ } TCR;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char BFB:1;\r
+ unsigned char BFA:1;\r
+ unsigned char MD:4;\r
+ } BIT;\r
+ } TMDR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOB:4;\r
+ unsigned char IOA:4;\r
+ } BIT;\r
+ } TIORH;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IOD:4;\r
+ unsigned char IOC:4;\r
+ } BIT;\r
+ } TIORL;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TTGE:1;\r
+ unsigned char TTGE2:1;\r
+ unsigned char :1;\r
+ unsigned char TCIEV:1;\r
+ unsigned char TGIED:1;\r
+ unsigned char TGIEC:1;\r
+ unsigned char TGIEB:1;\r
+ unsigned char TGIEA:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk4[8];\r
+ unsigned short TCNT;\r
+ char wk5[8];\r
+ unsigned short TGRA;\r
+ unsigned short TGRB;\r
+ char wk6[8];\r
+ unsigned short TGRC;\r
+ unsigned short TGRD;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TCFD:1;\r
+ } BIT;\r
+ } TSR;\r
+ char wk8[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TTSE:1;\r
+ unsigned char TTSB:1;\r
+ unsigned char TTSA:1;\r
+ } BIT;\r
+ } TBTM;\r
+ char wk9[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BF:2;\r
+ unsigned short :6;\r
+ unsigned short UT4AE:1;\r
+ unsigned short DT4AE:1;\r
+ unsigned short UT4BE:1;\r
+ unsigned short DT4BE:1;\r
+ unsigned short ITA3AE:1;\r
+ unsigned short ITA4VE:1;\r
+ unsigned short ITB3AE:1;\r
+ unsigned short ITB4VE:1;\r
+ } BIT;\r
+ } TADCR;\r
+ char wk10[2];\r
+ unsigned short TADCORA;\r
+ unsigned short TADCORB;\r
+ unsigned short TADCOBRA;\r
+ unsigned short TADCOBRB;\r
+ char wk11[72];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char NFDEN:1;\r
+ unsigned char NFCEN:1;\r
+ unsigned char NFBEN:1;\r
+ unsigned char NFAEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+};\r
+\r
+struct st_mtu5 {\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char NFCS:2;\r
+ unsigned char :1;\r
+ unsigned char NFWEN:1;\r
+ unsigned char NFVEN:1;\r
+ unsigned char NFUEN:1;\r
+ } BIT;\r
+ } NFCR;\r
+ char wk1[490];\r
+ unsigned short TCNTU;\r
+ unsigned short TGRU;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRU;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORU;\r
+ char wk3[9];\r
+ unsigned short TCNTV;\r
+ unsigned short TGRV;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRV;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORV;\r
+ char wk5[9];\r
+ unsigned short TCNTW;\r
+ unsigned short TGRW;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char TPSC:2;\r
+ } BIT;\r
+ } TCRW;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char IOC:5;\r
+ } BIT;\r
+ } TIORW;\r
+ char wk7[11];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char TGIE5U:1;\r
+ unsigned char TGIE5V:1;\r
+ unsigned char TGIE5W:1;\r
+ } BIT;\r
+ } TIER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CSTU5:1;\r
+ unsigned char CSTV5:1;\r
+ unsigned char CSTW5:1;\r
+ } BIT;\r
+ } TSTR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char CMPCLR5U:1;\r
+ unsigned char CMPCLR5V:1;\r
+ unsigned char CMPCLR5W:1;\r
+ } BIT;\r
+ } TCNTCMPCLR;\r
+};\r
+\r
+struct st_poe {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char POE3F:1;\r
+ unsigned char POE2F:1;\r
+ unsigned char POE1F:1;\r
+ unsigned char POE0F:1;\r
+ unsigned char :3;\r
+ unsigned char PIE1:1;\r
+ unsigned char POE3M:2;\r
+ unsigned char POE2M:2;\r
+ unsigned char POE1M:2;\r
+ unsigned char POE0M:2;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char OSF1:1;\r
+ unsigned char :5;\r
+ unsigned char OCE1:1;\r
+ unsigned char OIE1:1;\r
+ } BIT;\r
+ } OCSR1;\r
+ char wk0[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char POE8F:1;\r
+ unsigned char :2;\r
+ unsigned char POE8E:1;\r
+ unsigned char PIE2:1;\r
+ unsigned char :6;\r
+ unsigned char POE8M:2;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char CH0HIZ:1;\r
+ unsigned char CH34HIZ:1;\r
+ } BIT;\r
+ } SPOER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PE3ZE:1;\r
+ unsigned char PE2ZE:1;\r
+ unsigned char PE1ZE:1;\r
+ unsigned char PE0ZE:1;\r
+ } BIT;\r
+ } POECR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char P1CZEA:1;\r
+ unsigned char P2CZEA:1;\r
+ unsigned char P3CZEA:1;\r
+ } BIT;\r
+ } POECR2;\r
+ char wk1[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char H;\r
+ unsigned char L;\r
+ } BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char OSTSTF:1;\r
+ unsigned char :2;\r
+ unsigned char OSTSTE:1;\r
+ } BIT;\r
+ } ICSR3;\r
+};\r
+\r
+struct st_port {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PSEL7:1;\r
+ unsigned char PSEL6:1;\r
+ } BIT;\r
+ } PSRA;\r
+};\r
+\r
+struct st_port0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :2;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :2;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :2;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :2;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :5;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[62];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char :2;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[32];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[61];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port2 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[33];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port3 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char B5:1;\r
+ unsigned char :2;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[34];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ char wk4[60];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port4 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+};\r
+\r
+struct st_port5 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[36];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[57];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_port9 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+};\r
+\r
+struct st_porta {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[41];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[52];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[42];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[51];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[43];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[50];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portd {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porte {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[45];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ unsigned char :1;\r
+ unsigned char B4:1;\r
+ unsigned char :1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } ODR1;\r
+ char wk4[48];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char B5:1;\r
+ unsigned char B4:1;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char B1:1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_portf {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[95];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_porth {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ } BIT;\r
+ } PMR;\r
+};\r
+\r
+struct st_portj {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char :2;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PDR;\r
+ char wk0[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char :2;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PODR;\r
+ char wk1[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char :2;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PIDR;\r
+ char wk2[31];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char B7:1;\r
+ unsigned char B6:1;\r
+ unsigned char :2;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PMR;\r
+ char wk3[49];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char B6:1;\r
+ } BIT;\r
+ } ODR0;\r
+ char wk4[45];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char B3:1;\r
+ unsigned char B2:1;\r
+ unsigned char :1;\r
+ unsigned char B0:1;\r
+ } BIT;\r
+ } PCR;\r
+};\r
+\r
+struct st_riic {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ICE:1;\r
+ unsigned char IICRST:1;\r
+ unsigned char CLO:1;\r
+ unsigned char SOWP:1;\r
+ unsigned char SCLO:1;\r
+ unsigned char SDAO:1;\r
+ unsigned char SCLI:1;\r
+ unsigned char SDAI:1;\r
+ } BIT;\r
+ } ICCR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BBSY:1;\r
+ unsigned char MST:1;\r
+ unsigned char TRS:1;\r
+ unsigned char :1;\r
+ unsigned char SP:1;\r
+ unsigned char RS:1;\r
+ unsigned char ST:1;\r
+ } BIT;\r
+ } ICCR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char MTWP:1;\r
+ unsigned char CKS:3;\r
+ unsigned char BCWP:1;\r
+ unsigned char BC:3;\r
+ } BIT;\r
+ } ICMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char DLCS:1;\r
+ unsigned char SDDL:3;\r
+ unsigned char TMWE:1;\r
+ unsigned char TMOH:1;\r
+ unsigned char TMOL:1;\r
+ unsigned char TMOS:1;\r
+ } BIT;\r
+ } ICMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SMBS:1;\r
+ unsigned char WAIT:1;\r
+ unsigned char RDRFS:1;\r
+ unsigned char ACKWP:1;\r
+ unsigned char ACKBT:1;\r
+ unsigned char ACKBR:1;\r
+ unsigned char NF:2;\r
+ } BIT;\r
+ } ICMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SCLE:1;\r
+ unsigned char NFE:1;\r
+ unsigned char NACKE:1;\r
+ unsigned char SALE:1;\r
+ unsigned char NALE:1;\r
+ unsigned char MALE:1;\r
+ unsigned char TMOE:1;\r
+ } BIT;\r
+ } ICFER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOAE:1;\r
+ unsigned char :1;\r
+ unsigned char DIDE:1;\r
+ unsigned char :1;\r
+ unsigned char GCAE:1;\r
+ unsigned char SAR2E:1;\r
+ unsigned char SAR1E:1;\r
+ unsigned char SAR0E:1;\r
+ } BIT;\r
+ } ICSER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char NAKIE:1;\r
+ unsigned char SPIE:1;\r
+ unsigned char STIE:1;\r
+ unsigned char ALIE:1;\r
+ unsigned char TMOIE:1;\r
+ } BIT;\r
+ } ICIER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char HOA:1;\r
+ unsigned char :1;\r
+ unsigned char DID:1;\r
+ unsigned char :1;\r
+ unsigned char GCA:1;\r
+ unsigned char AAS2:1;\r
+ unsigned char AAS1:1;\r
+ unsigned char AAS0:1;\r
+ } BIT;\r
+ } ICSR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TDRE:1;\r
+ unsigned char TEND:1;\r
+ unsigned char RDRF:1;\r
+ unsigned char NACKF:1;\r
+ unsigned char STOP:1;\r
+ unsigned char START:1;\r
+ unsigned char AL:1;\r
+ unsigned char TMOF:1;\r
+ } BIT;\r
+ } ICSR2;\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTL;\r
+ };\r
+ union {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU0;\r
+ union {\r
+ unsigned char BYTE;\r
+ } TMOCNTU;\r
+ };\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SVA:7;\r
+ unsigned char SVA0:1;\r
+ } BIT;\r
+ } SARL2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SVA:2;\r
+ unsigned char FS:1;\r
+ } BIT;\r
+ } SARU2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRL:5;\r
+ } BIT;\r
+ } ICBRL;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char BRH:5;\r
+ } BIT;\r
+ } ICBRH;\r
+ unsigned char ICDRT;\r
+ unsigned char ICDRR;\r
+};\r
+\r
+struct st_rspi {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char SPRIE:1;\r
+ unsigned char SPE:1;\r
+ unsigned char SPTIE:1;\r
+ unsigned char SPEIE:1;\r
+ unsigned char MSTR:1;\r
+ unsigned char MODFEN:1;\r
+ unsigned char TXMD:1;\r
+ unsigned char SPMS:1;\r
+ } BIT;\r
+ } SPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char SSL3P:1;\r
+ unsigned char SSL2P:1;\r
+ unsigned char SSL1P:1;\r
+ unsigned char SSL0P:1;\r
+ } BIT;\r
+ } SSLP;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char MOIFE:1;\r
+ unsigned char MOIFV:1;\r
+ unsigned char :2;\r
+ unsigned char SPLP2:1;\r
+ unsigned char SPLP:1;\r
+ } BIT;\r
+ } SPPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PERF:1;\r
+ unsigned char MODF:1;\r
+ unsigned char IDLNF:1;\r
+ unsigned char OVRF:1;\r
+ } BIT;\r
+ } SPSR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned short H;\r
+ } WORD;\r
+ } SPDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPSLN:3;\r
+ } BIT;\r
+ } SPSCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SPECM:3;\r
+ unsigned char :1;\r
+ unsigned char SPCP:3;\r
+ } BIT;\r
+ } SPSSR;\r
+ unsigned char SPBR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char SPLW:1;\r
+ unsigned char SPRDTD:1;\r
+ unsigned char :2;\r
+ unsigned char SPFC:2;\r
+ } BIT;\r
+ } SPDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SCKDL:3;\r
+ } BIT;\r
+ } SPCKD;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SLNDL:3;\r
+ } BIT;\r
+ } SSLND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SPNDL:3;\r
+ } BIT;\r
+ } SPND;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char PTE:1;\r
+ unsigned char SPIIE:1;\r
+ unsigned char SPOE:1;\r
+ unsigned char SPPE:1;\r
+ } BIT;\r
+ } SPCR2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD5;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD6;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SCKDEN:1;\r
+ unsigned short SLNDEN:1;\r
+ unsigned short SPNDEN:1;\r
+ unsigned short LSBF:1;\r
+ unsigned short SPB:4;\r
+ unsigned short SSLKP:1;\r
+ unsigned short SSLA:3;\r
+ unsigned short BRDV:2;\r
+ unsigned short CPOL:1;\r
+ unsigned short CPHA:1;\r
+ } BIT;\r
+ } SPCMD7;\r
+};\r
+\r
+struct st_rtc {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char F1HZ:1;\r
+ unsigned char F2HZ:1;\r
+ unsigned char F4HZ:1;\r
+ unsigned char F8HZ:1;\r
+ unsigned char F16HZ:1;\r
+ unsigned char F32HZ:1;\r
+ unsigned char F64HZ:1;\r
+ } BIT;\r
+ } R64CNT;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECCNT;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINCNT;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRCNT;\r
+ char wk3[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char DAYW:3;\r
+ } BIT;\r
+ } RWKCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char DATE10:2;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYCNT;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONCNT;\r
+ char wk6[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short YR10:4;\r
+ unsigned short YR1:4;\r
+ } BIT;\r
+ } RYRCNT;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char SEC10:3;\r
+ unsigned char SEC1:4;\r
+ } BIT;\r
+ } RSECAR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char MIN10:3;\r
+ unsigned char MIN1:4;\r
+ } BIT;\r
+ } RMINAR;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char PM:1;\r
+ unsigned char HR10:2;\r
+ unsigned char HR1:4;\r
+ } BIT;\r
+ } RHRAR;\r
+ char wk9[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :4;\r
+ unsigned char DAYW:3;\r
+ } BIT;\r
+ } RWKAR;\r
+ char wk10[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :1;\r
+ unsigned char DATE10:2;\r
+ unsigned char DATE1:4;\r
+ } BIT;\r
+ } RDAYAR;\r
+ char wk11[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ unsigned char :2;\r
+ unsigned char MON10:1;\r
+ unsigned char MON1:4;\r
+ } BIT;\r
+ } RMONAR;\r
+ char wk12[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short YR10:4;\r
+ unsigned short YR1:4;\r
+ } BIT;\r
+ } RYRAR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:1;\r
+ } BIT;\r
+ } RYRAREN;\r
+ char wk13[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PES:4;\r
+ unsigned char RTCOS:1;\r
+ unsigned char PIE:1;\r
+ unsigned char CIE:1;\r
+ unsigned char AIE:1;\r
+ } BIT;\r
+ } RCR1;\r
+ char wk14[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CNTMD:1;\r
+ unsigned char HR24:1;\r
+ unsigned char AADJP:1;\r
+ unsigned char AADJE:1;\r
+ unsigned char RTCOE:1;\r
+ unsigned char ADJ30:1;\r
+ unsigned char RESET:1;\r
+ unsigned char START:1;\r
+ } BIT;\r
+ } RCR2;\r
+ char wk15[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char RTCDV:3;\r
+ unsigned char RTCEN:1;\r
+ } BIT;\r
+ } RCR3;\r
+ char wk16[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PMADJ:2;\r
+ unsigned char ADJ:6;\r
+ } BIT;\r
+ } RADJ;\r
+};\r
+\r
+struct st_rtcb {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT0;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT1;\r
+ char wk1[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT2;\r
+ char wk2[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNT:8;\r
+ } BIT;\r
+ } BCNT3;\r
+ char wk3[7];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT0AR;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT1AR;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT2AR;\r
+ char wk6[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCNTAR:8;\r
+ } BIT;\r
+ } BCNT3AR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT0AER;\r
+ char wk8[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT1AER;\r
+ char wk9[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short ENB:8;\r
+ } BIT;\r
+ } BCNT2AER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char ENB:8;\r
+ } BIT;\r
+ } BCNT3AER;\r
+};\r
+\r
+struct st_s12ad {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADST:1;\r
+ unsigned short ADCS:2;\r
+ unsigned short ADIE:1;\r
+ unsigned short :1;\r
+ unsigned short ADHSC:1;\r
+ unsigned short TRGE:1;\r
+ unsigned short EXTRG:1;\r
+ unsigned short DBLE:1;\r
+ unsigned short GBADIE:1;\r
+ unsigned short :1;\r
+ unsigned short DBLANS:5;\r
+ } BIT;\r
+ } ADCSR;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short ANSA:16;\r
+// } BIT;\r
+ } ADANSA;\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short :10;\r
+// unsigned short ANSA1:1;\r
+// } BIT;\r
+ } ADANSA1;\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short ADS:16;\r
+// } BIT;\r
+ } ADADS;\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short :10;\r
+// unsigned short ADS1:1;\r
+// } BIT;\r
+ } ADADS1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char ADC:2;\r
+ } BIT;\r
+ } ADADC;\r
+ char wk1[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short ADRFMT:1;\r
+ unsigned short :9;\r
+ unsigned short ACE:1;\r
+ } BIT;\r
+ } ADCER;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short TRSA:4;\r
+ unsigned short :4;\r
+ unsigned short TRSB:4;\r
+ } BIT;\r
+ } ADSTRGR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short OCS:1;\r
+ unsigned short TSS:1;\r
+ unsigned short :6;\r
+ unsigned short OCSAD:1;\r
+ unsigned short TSSAD:1;\r
+ } BIT;\r
+ } ADEXICR;\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short ANSB:16;\r
+// } BIT;\r
+ } ADANSB;\r
+ union {\r
+ unsigned short WORD;\r
+// struct {\r
+// unsigned short :10;\r
+// unsigned short ANSB1:1;\r
+// } BIT;\r
+ } ADANSB1;\r
+ unsigned short ADDBLDR;\r
+ unsigned short ADTSDR;\r
+ unsigned short ADOCDR;\r
+ char wk2[2];\r
+ unsigned short ADDR0;\r
+ unsigned short ADDR1;\r
+ unsigned short ADDR2;\r
+ unsigned short ADDR3;\r
+ unsigned short ADDR4;\r
+ unsigned short ADDR5;\r
+ unsigned short ADDR6;\r
+ unsigned short ADDR7;\r
+ unsigned short ADDR8;\r
+ unsigned short ADDR9;\r
+ unsigned short ADDR10;\r
+ unsigned short ADDR11;\r
+ unsigned short ADDR12;\r
+ unsigned short ADDR13;\r
+ unsigned short ADDR14;\r
+ unsigned short ADDR15;\r
+ char wk3[10];\r
+ unsigned short ADDR21;\r
+ char wk4[20];\r
+ unsigned char ADSSTR0;\r
+ unsigned char ADSSTRL;\r
+ char wk5[14];\r
+ unsigned char ADSSTRT;\r
+ unsigned char ADSSTRO;\r
+ char wk6[1];\r
+ unsigned char ADSSTR1;\r
+ unsigned char ADSSTR2;\r
+ unsigned char ADSSTR3;\r
+ unsigned char ADSSTR4;\r
+ unsigned char ADSSTR5;\r
+ unsigned char ADSSTR6;\r
+ unsigned char ADSSTR7;\r
+ char wk7[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char OCSVSEL:1;\r
+ unsigned char HVREFDIS:1;\r
+ } BIT;\r
+ } ADHVREFCNT;\r
+ char wk8[3];\r
+ unsigned char ADSSTR21;\r
+};\r
+\r
+struct st_sci0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RXDESEL:1;\r
+ unsigned char :1;\r
+ unsigned char NFEN:1;\r
+ unsigned char ABCS:1;\r
+ unsigned char :3;\r
+ unsigned char ACS0:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char NFCS:3;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICDL:5;\r
+ unsigned char :2;\r
+ unsigned char IICM:1;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :3;\r
+ unsigned char IICCSC:1;\r
+ unsigned char IICINTM:1;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSCLS:2;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTAREQ:1;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IICACKR:1;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKPH:1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char MSS:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char SSE:1;\r
+ } BIT;\r
+ } SPMR;\r
+};\r
+\r
+struct st_sci12 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CM:1;\r
+ unsigned char CHR:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char STOP:1;\r
+ unsigned char MP:1;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char FER:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RXDESEL:1;\r
+ unsigned char :1;\r
+ unsigned char NFEN:1;\r
+ unsigned char ABCS:1;\r
+ unsigned char :3;\r
+ unsigned char ACS0:1;\r
+ } BIT;\r
+ } SEMR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char NFCS:3;\r
+ } BIT;\r
+ } SNFR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICDL:5;\r
+ unsigned char :2;\r
+ unsigned char IICM:1;\r
+ } BIT;\r
+ } SIMR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char IICACKT:1;\r
+ unsigned char :3;\r
+ unsigned char IICCSC:1;\r
+ unsigned char IICINTM:1;\r
+ } BIT;\r
+ } SIMR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char IICSCLS:2;\r
+ unsigned char IICSDAS:2;\r
+ unsigned char IICSTIF:1;\r
+ unsigned char IICSTPREQ:1;\r
+ unsigned char IICRSTAREQ:1;\r
+ unsigned char IICSTAREQ:1;\r
+ } BIT;\r
+ } SIMR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char IICACKR:1;\r
+ } BIT;\r
+ } SISR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CKPH:1;\r
+ unsigned char CKPOL:1;\r
+ unsigned char :1;\r
+ unsigned char MFF:1;\r
+ unsigned char :1;\r
+ unsigned char MSS:1;\r
+ unsigned char CTSE:1;\r
+ unsigned char SSE:1;\r
+ } BIT;\r
+ } SPMR;\r
+ char wk0[18];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ESME:1;\r
+ } BIT;\r
+ } ESMER;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char BRME:1;\r
+ unsigned char RXDSF:1;\r
+ unsigned char SFSF:1;\r
+ } BIT;\r
+ } CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char PIBS:3;\r
+ unsigned char PIBE:1;\r
+ unsigned char CF1DS:2;\r
+ unsigned char CF0RE:1;\r
+ unsigned char BFE:1;\r
+ } BIT;\r
+ } CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RTS:2;\r
+ unsigned char BCCS:2;\r
+ unsigned char :1;\r
+ unsigned char DFCS:3;\r
+ } BIT;\r
+ } CR2;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SDST:1;\r
+ } BIT;\r
+ } CR3;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char SHARPS:1;\r
+ unsigned char :2;\r
+ unsigned char RXDXPS:1;\r
+ unsigned char TXDXPS:1;\r
+ } BIT;\r
+ } PCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDIE:1;\r
+ unsigned char BCDIE:1;\r
+ unsigned char PIBDIE:1;\r
+ unsigned char CF1MIE:1;\r
+ unsigned char CF0MIE:1;\r
+ unsigned char BFDIE:1;\r
+ } BIT;\r
+ } ICR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDF:1;\r
+ unsigned char BCDF:1;\r
+ unsigned char PIBDF:1;\r
+ unsigned char CF1MF:1;\r
+ unsigned char CF0MF:1;\r
+ unsigned char BFDF:1;\r
+ } BIT;\r
+ } STR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char AEDCL:1;\r
+ unsigned char BCDCL:1;\r
+ unsigned char PIBDCL:1;\r
+ unsigned char CF1MCL:1;\r
+ unsigned char CF0MCL:1;\r
+ unsigned char BFDCL:1;\r
+ } BIT;\r
+ } STCR;\r
+ unsigned char CF0DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF0CE7:1;\r
+ unsigned char CF0CE6:1;\r
+ unsigned char CF0CE5:1;\r
+ unsigned char CF0CE4:1;\r
+ unsigned char CF0CE3:1;\r
+ unsigned char CF0CE2:1;\r
+ unsigned char CF0CE1:1;\r
+ unsigned char CF0CE0:1;\r
+ } BIT;\r
+ } CF0CR;\r
+ unsigned char CF0RR;\r
+ unsigned char PCF1DR;\r
+ unsigned char SCF1DR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CF1CE7:1;\r
+ unsigned char CF1CE6:1;\r
+ unsigned char CF1CE5:1;\r
+ unsigned char CF1CE4:1;\r
+ unsigned char CF1CE3:1;\r
+ unsigned char CF1CE2:1;\r
+ unsigned char CF1CE1:1;\r
+ unsigned char CF1CE0:1;\r
+ } BIT;\r
+ } CF1CR;\r
+ unsigned char CF1RR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TCST:1;\r
+ } BIT;\r
+ } TCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char TCSS:3;\r
+ unsigned char TWRC:1;\r
+ unsigned char :1;\r
+ unsigned char TOMS:2;\r
+ } BIT;\r
+ } TMR;\r
+ unsigned char TPRE;\r
+ unsigned char TCNT;\r
+};\r
+\r
+struct st_smci {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char GM:1;\r
+ unsigned char BLK:1;\r
+ unsigned char PE:1;\r
+ unsigned char PM:1;\r
+ unsigned char BCP:2;\r
+ unsigned char CKS:2;\r
+ } BIT;\r
+ } SMR;\r
+ unsigned char BRR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TIE:1;\r
+ unsigned char RIE:1;\r
+ unsigned char TE:1;\r
+ unsigned char RE:1;\r
+ unsigned char MPIE:1;\r
+ unsigned char TEIE:1;\r
+ unsigned char CKE:2;\r
+ } BIT;\r
+ } SCR;\r
+ unsigned char TDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char ORER:1;\r
+ unsigned char ERS:1;\r
+ unsigned char PER:1;\r
+ unsigned char TEND:1;\r
+ unsigned char MPB:1;\r
+ unsigned char MPBT:1;\r
+ } BIT;\r
+ } SSR;\r
+ unsigned char RDR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char BCP2:1;\r
+ unsigned char :3;\r
+ unsigned char SDIR:1;\r
+ unsigned char SINV:1;\r
+ unsigned char :1;\r
+ unsigned char SMIF:1;\r
+ } BIT;\r
+ } SCMR;\r
+};\r
+\r
+struct st_ssi {\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :1;\r
+ unsigned long CKS:1;\r
+ unsigned long TUIEN:1;\r
+ unsigned long TOIEN:1;\r
+ unsigned long RUIEN:1;\r
+ unsigned long ROIEN:1;\r
+ unsigned long IIEN:1;\r
+ unsigned long :1;\r
+ unsigned long CHNL:2;\r
+ unsigned long DWL:3;\r
+ unsigned long SWL:3;\r
+ unsigned long SCKD:1;\r
+ unsigned long SWSD:1;\r
+ unsigned long SCKP:1;\r
+ unsigned long SWSP:1;\r
+ unsigned long SPDP:1;\r
+ unsigned long SDTA:1;\r
+ unsigned long PDTA:1;\r
+ unsigned long DEL:1;\r
+ unsigned long CKDV:4;\r
+ unsigned long MUEN:1;\r
+ unsigned long :1;\r
+ unsigned long TEN:1;\r
+ unsigned long REN:1;\r
+ } BIT;\r
+ } SSICR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :2;\r
+ unsigned long TUIRQ:1;\r
+ unsigned long TOIRQ:1;\r
+ unsigned long RUIRQ:1;\r
+ unsigned long ROIRQ:1;\r
+ unsigned long IIRQ:1;\r
+ unsigned long :18;\r
+ unsigned long TCHNO:2;\r
+ unsigned long TSWNO:1;\r
+ unsigned long RCHNO:2;\r
+ unsigned long RSWNO:1;\r
+ unsigned long IDST:1;\r
+ } BIT;\r
+ } SSISR;\r
+ char wk0[8];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long AUCKE:1;\r
+ unsigned long :14;\r
+ unsigned long SSIRST:1;\r
+ unsigned long :8;\r
+ unsigned long TTRG:2;\r
+ unsigned long RTRG:2;\r
+ unsigned long TIE:1;\r
+ unsigned long RIE:1;\r
+ unsigned long TFRST:1;\r
+ unsigned long RFRST:1;\r
+ } BIT;\r
+ } SSIFCR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :4;\r
+ unsigned long TDC:4;\r
+ unsigned long :7;\r
+ unsigned long TDE:1;\r
+ unsigned long :4;\r
+ unsigned long RDC:4;\r
+ unsigned long :7;\r
+ unsigned long RDF:1;\r
+ } BIT;\r
+ } SSIFSR;\r
+ unsigned long SSIFTDR;\r
+ unsigned long SSIFRDR;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :23;\r
+ unsigned long CONT:1;\r
+ } BIT;\r
+ } SSITDMR;\r
+};\r
+\r
+struct st_system {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short MD:1;\r
+ } BIT;\r
+ } MDMONR;\r
+ char wk0[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short RAME:1;\r
+ } BIT;\r
+ } SYSCR1;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short SSBY:1;\r
+ } BIT;\r
+ } SBYCR;\r
+ char wk2[2];\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :3;\r
+ unsigned long MSTPA28:1;\r
+ unsigned long :9;\r
+ unsigned long MSTPA18:1;\r
+ unsigned long MSTPA17:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPA15:1;\r
+ unsigned long MSTPA14:1;\r
+ unsigned long :4;\r
+ unsigned long MSTPA9:1;\r
+ unsigned long :3;\r
+ unsigned long MSTPA5:1;\r
+ unsigned long MSTPA4:1;\r
+ } BIT;\r
+ } MSTPCRA;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long MSTPB31:1;\r
+ unsigned long MSTPB30:1;\r
+ unsigned long MSTPB29:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPB26:1;\r
+ unsigned long MSTPB25:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB23:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB21:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB19:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB17:1;\r
+ unsigned long :6;\r
+ unsigned long MSTPB10:1;\r
+ unsigned long MSTPB9:1;\r
+ unsigned long :2;\r
+ unsigned long MSTPB6:1;\r
+ unsigned long :1;\r
+ unsigned long MSTPB4:1;\r
+ } BIT;\r
+ } MSTPCRB;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long DSLPE:1;\r
+ unsigned long :3;\r
+ unsigned long MSTPC27:1;\r
+ unsigned long MSTPC26:1;\r
+ unsigned long :5;\r
+ unsigned long MSTPC20:1;\r
+ unsigned long MSTPC19:1;\r
+ unsigned long :18;\r
+ unsigned long MSTPC0:1;\r
+ } BIT;\r
+ } MSTPCRC;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long :16;\r
+ unsigned long MSTPD15:1;\r
+ unsigned long :3;\r
+ unsigned long MSTPD11:1;\r
+ unsigned long MSTPD10:1;\r
+ } BIT;\r
+ } MSTPCRD;\r
+ union {\r
+ unsigned long LONG;\r
+ struct {\r
+ unsigned long FCK:4;\r
+ unsigned long ICK:4;\r
+ unsigned long :12;\r
+ unsigned long PCKB:4;\r
+ unsigned long :4;\r
+ unsigned long PCKD:4;\r
+ } BIT;\r
+ } SCKCR;\r
+ char wk3[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short CKSEL:3;\r
+ } BIT;\r
+ } SCKCR3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short STC:6;\r
+ unsigned short :6;\r
+ unsigned short PLIDIV:2;\r
+ } BIT;\r
+ } PLLCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char PLLEN:1;\r
+ } BIT;\r
+ } PLLCR2;\r
+ char wk4[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :2;\r
+ unsigned short USTC:6;\r
+ unsigned short :3;\r
+ unsigned short UCKUPLLSEL:1;\r
+ unsigned short :2;\r
+ unsigned short UPLIDIV:2;\r
+ } BIT;\r
+ } UPLLCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char UPLLEN:1;\r
+ } BIT;\r
+ } UPLLCR2;\r
+ char wk5[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char MOSTP:1;\r
+ } BIT;\r
+ } MOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char SOSTP:1;\r
+ } BIT;\r
+ } SOSCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char LCSTP:1;\r
+ } BIT;\r
+ } LOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char ILCSTP:1;\r
+ } BIT;\r
+ } ILOCOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char HCSTP:1;\r
+ } BIT;\r
+ } HOCOCR;\r
+ char wk6[5];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char UPLOVF:1;\r
+ unsigned char :1;\r
+ unsigned char HCOVF:1;\r
+ unsigned char PLOVF:1;\r
+ unsigned char :1;\r
+ unsigned char MOOVF:1;\r
+ } BIT;\r
+ } OSCOVFSR;\r
+ char wk7[1];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short CKOSTP:1;\r
+ unsigned short CKODIV:3;\r
+ unsigned short :1;\r
+ unsigned short CKOSEL:3;\r
+ } BIT;\r
+ } CKOCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char OSTDE:1;\r
+ unsigned char :6;\r
+ unsigned char OSTDIE:1;\r
+ } BIT;\r
+ } OSTDCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char OSTDF:1;\r
+ } BIT;\r
+ } OSTDSR;\r
+ char wk8[14];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char LCDSCLKSEL:3;\r
+ } BIT;\r
+ } LCDSCLKCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char LCDSCLKSTP:1;\r
+ } BIT;\r
+ } LCDSCLKCR2;\r
+ char wk9[78];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char OPCMTSF:1;\r
+ unsigned char :1;\r
+ unsigned char OPCM:3;\r
+ } BIT;\r
+ } OPCCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char RSTCKEN:1;\r
+ unsigned char :4;\r
+ unsigned char RSTCKSEL:3;\r
+ } BIT;\r
+ } RSTCKCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char MSTS:5;\r
+ } BIT;\r
+ } MOSCWTCR;\r
+ char wk10[2];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char HSTS:5;\r
+ } BIT;\r
+ } HOCOWTCR;\r
+ char wk11[4];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :3;\r
+ unsigned char SOPCMTSF:1;\r
+ unsigned char :3;\r
+ unsigned char SOPCM:1;\r
+ } BIT;\r
+ } SOPCCR;\r
+ char wk12[21];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char SWRF:1;\r
+ unsigned char :1;\r
+ unsigned char IWDTRF:1;\r
+ } BIT;\r
+ } RSTSR2;\r
+ char wk13[1];\r
+ unsigned short SWRR;\r
+ char wk14[28];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char LVD1IRQSEL:1;\r
+ unsigned char LVD1IDTSEL:2;\r
+ } BIT;\r
+ } LVD1CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD1MON:1;\r
+ unsigned char LVD1DET:1;\r
+ } BIT;\r
+ } LVD1SR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :5;\r
+ unsigned char LVD2IRQSEL:1;\r
+ unsigned char LVD2IDTSEL:2;\r
+ } BIT;\r
+ } LVD2CR1;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :6;\r
+ unsigned char LVD2MON:1;\r
+ unsigned char LVD2DET:1;\r
+ } BIT;\r
+ } LVD2SR;\r
+ char wk15[794];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short PRKEY:8;\r
+ unsigned short :4;\r
+ unsigned short PRC3:1;\r
+ unsigned short PRC2:1;\r
+ unsigned short PRC1:1;\r
+ unsigned short PRC0:1;\r
+ } BIT;\r
+ } PRCR;\r
+ char wk16[48784];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char LVD2RF:1;\r
+ unsigned char LVD1RF:1;\r
+ unsigned char :1;\r
+ unsigned char PORF:1;\r
+ } BIT;\r
+ } RSTSR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char CWSF:1;\r
+ } BIT;\r
+ } RSTSR1;\r
+ char wk17[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char MOSEL:1;\r
+ unsigned char MODRV21:1;\r
+ } BIT;\r
+ } MOFCR;\r
+ char wk18[3];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :1;\r
+ unsigned char LVD2E:1;\r
+ unsigned char LVD1E:1;\r
+ unsigned char :1;\r
+ unsigned char EXVCCINP2:1;\r
+ } BIT;\r
+ } LVCMPCR;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :2;\r
+ unsigned char LVD2LVL:2;\r
+ unsigned char LVD1LVL:4;\r
+ } BIT;\r
+ } LVDLVLR;\r
+ char wk19[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD1RN:1;\r
+ unsigned char LVD1RI:1;\r
+ unsigned char :3;\r
+ unsigned char LVD1CMPE:1;\r
+ unsigned char :1;\r
+ unsigned char LVD1RIE:1;\r
+ } BIT;\r
+ } LVD1CR0;\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char LVD2RN:1;\r
+ unsigned char LVD2RI:1;\r
+ unsigned char :3;\r
+ unsigned char LVD2CMPE:1;\r
+ unsigned char :1;\r
+ unsigned char LVD2RIE:1;\r
+ } BIT;\r
+ } LVD2CR0;\r
+};\r
+\r
+struct st_temps {\r
+ unsigned char TSCDRL;\r
+ unsigned char TSCDRH;\r
+};\r
+\r
+struct st_tmr0 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CMIEB:1;\r
+ unsigned char CMIEA:1;\r
+ unsigned char OVIE:1;\r
+ unsigned char CCLR:2;\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char OSB:2;\r
+ unsigned char OSA:2;\r
+ } BIT;\r
+ } TCSR;\r
+ char wk1[1];\r
+ unsigned char TCORA;\r
+ char wk2[1];\r
+ unsigned char TCORB;\r
+ char wk3[1];\r
+ unsigned char TCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TMRIS:1;\r
+ unsigned char :2;\r
+ unsigned char CSS:2;\r
+ unsigned char CKS:3;\r
+ } BIT;\r
+ } TCCR;\r
+ char wk5[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :7;\r
+ unsigned char TCS:1;\r
+ } BIT;\r
+ } TCSTR;\r
+};\r
+\r
+struct st_tmr1 {\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char CMIEB:1;\r
+ unsigned char CMIEA:1;\r
+ unsigned char OVIE:1;\r
+ unsigned char CCLR:2;\r
+ } BIT;\r
+ } TCR;\r
+ char wk0[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char :4;\r
+ unsigned char OSB:2;\r
+ unsigned char OSA:2;\r
+ } BIT;\r
+ } TCSR;\r
+ char wk1[1];\r
+ unsigned char TCORA;\r
+ char wk2[1];\r
+ unsigned char TCORB;\r
+ char wk3[1];\r
+ unsigned char TCNT;\r
+ char wk4[1];\r
+ union {\r
+ unsigned char BYTE;\r
+ struct {\r
+ unsigned char TMRIS:1;\r
+ unsigned char :2;\r
+ unsigned char CSS:2;\r
+ unsigned char CKS:3;\r
+ } BIT;\r
+ } TCCR;\r
+};\r
+\r
+struct st_tmr01 {\r
+ unsigned short TCORA;\r
+ unsigned short TCORB;\r
+ unsigned short TCNT;\r
+ unsigned short TCCR;\r
+};\r
+\r
+struct st_usb0 {\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :5;\r
+ unsigned short SCKE:1;\r
+ unsigned short :1;\r
+ unsigned short CNEN:1;\r
+ unsigned short :1;\r
+ unsigned short DCFM:1;\r
+ unsigned short DRPD:1;\r
+ unsigned short DPRPU:1;\r
+ unsigned short DMRPU:1;\r
+ unsigned short :2;\r
+ unsigned short USBE:1;\r
+ } BIT;\r
+ } SYSCFG;\r
+ char wk0[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVCMON:2;\r
+ unsigned short :7;\r
+ unsigned short HTACT:1;\r
+ unsigned short :3;\r
+ unsigned short IDMON:1;\r
+ unsigned short LNST:2;\r
+ } BIT;\r
+ } SYSSTS0;\r
+ char wk1[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :4;\r
+ unsigned short HNPBTOA:1;\r
+ unsigned short EXICEN:1;\r
+ unsigned short VBUSEN:1;\r
+ unsigned short WKUP:1;\r
+ unsigned short RWUPE:1;\r
+ unsigned short USBRST:1;\r
+ unsigned short RESUME:1;\r
+ unsigned short UACT:1;\r
+ unsigned short :1;\r
+ unsigned short RHST:3;\r
+ } BIT;\r
+ } DVSTCTR0;\r
+ char wk2[10];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } CFIFO;\r
+ char wk3[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D0FIFO;\r
+ char wk4[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned char L;\r
+ unsigned char H;\r
+ } BYTE;\r
+ } D1FIFO;\r
+ char wk5[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short :3;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :2;\r
+ unsigned short ISEL:1;\r
+ unsigned short :1;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } CFIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } CFIFOCTR;\r
+ char wk6[4];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D0FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } D0FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short RCNT:1;\r
+ unsigned short REW:1;\r
+ unsigned short DCLRM:1;\r
+ unsigned short DREQE:1;\r
+ unsigned short :1;\r
+ unsigned short MBW:1;\r
+ unsigned short :1;\r
+ unsigned short BIGEND:1;\r
+ unsigned short :4;\r
+ unsigned short CURPIPE:4;\r
+ } BIT;\r
+ } D1FIFOSEL;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BVAL:1;\r
+ unsigned short BCLR:1;\r
+ unsigned short FRDY:1;\r
+ unsigned short :4;\r
+ unsigned short DTLN:9;\r
+ } BIT;\r
+ } D1FIFOCTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBSE:1;\r
+ unsigned short RSME:1;\r
+ unsigned short SOFE:1;\r
+ unsigned short DVSE:1;\r
+ unsigned short CTRE:1;\r
+ unsigned short BEMPE:1;\r
+ unsigned short NRDYE:1;\r
+ unsigned short BRDYE:1;\r
+ } BIT;\r
+ } INTENB0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRCRE:1;\r
+ unsigned short BCHGE:1;\r
+ unsigned short :1;\r
+ unsigned short DTCHE:1;\r
+ unsigned short ATTCHE:1;\r
+ unsigned short :4;\r
+ unsigned short EOFERRE:1;\r
+ unsigned short SIGNE:1;\r
+ unsigned short SACKE:1;\r
+ unsigned short :3;\r
+ unsigned short PDDETINTE0:1;\r
+ } BIT;\r
+ } INTENB1;\r
+ char wk7[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDYE:1;\r
+ unsigned short PIPE8BRDYE:1;\r
+ unsigned short PIPE7BRDYE:1;\r
+ unsigned short PIPE6BRDYE:1;\r
+ unsigned short PIPE5BRDYE:1;\r
+ unsigned short PIPE4BRDYE:1;\r
+ unsigned short PIPE3BRDYE:1;\r
+ unsigned short PIPE2BRDYE:1;\r
+ unsigned short PIPE1BRDYE:1;\r
+ unsigned short PIPE0BRDYE:1;\r
+ } BIT;\r
+ } BRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9NRDYE:1;\r
+ unsigned short PIPE8NRDYE:1;\r
+ unsigned short PIPE7NRDYE:1;\r
+ unsigned short PIPE6NRDYE:1;\r
+ unsigned short PIPE5NRDYE:1;\r
+ unsigned short PIPE4NRDYE:1;\r
+ unsigned short PIPE3NRDYE:1;\r
+ unsigned short PIPE2NRDYE:1;\r
+ unsigned short PIPE1NRDYE:1;\r
+ unsigned short PIPE0NRDYE:1;\r
+ } BIT;\r
+ } NRDYENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BEMPE:1;\r
+ unsigned short PIPE8BEMPE:1;\r
+ unsigned short PIPE7BEMPE:1;\r
+ unsigned short PIPE6BEMPE:1;\r
+ unsigned short PIPE5BEMPE:1;\r
+ unsigned short PIPE4BEMPE:1;\r
+ unsigned short PIPE3BEMPE:1;\r
+ unsigned short PIPE2BEMPE:1;\r
+ unsigned short PIPE1BEMPE:1;\r
+ unsigned short PIPE0BEMPE:1;\r
+ } BIT;\r
+ } BEMPENB;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :7;\r
+ unsigned short TRNENSEL:1;\r
+ unsigned short :1;\r
+ unsigned short BRDYM:1;\r
+ unsigned short :1;\r
+ unsigned short EDGESTS:1;\r
+ } BIT;\r
+ } SOFCFG;\r
+ char wk8[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short VBINT:1;\r
+ unsigned short RESM:1;\r
+ unsigned short SOFR:1;\r
+ unsigned short DVST:1;\r
+ unsigned short CTRT:1;\r
+ unsigned short BEMP:1;\r
+ unsigned short NRDY:1;\r
+ unsigned short BRDY:1;\r
+ unsigned short VBSTS:1;\r
+ unsigned short DVSQ:3;\r
+ unsigned short VALID:1;\r
+ unsigned short CTSQ:3;\r
+ } BIT;\r
+ } INTSTS0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRCR:1;\r
+ unsigned short BCHG:1;\r
+ unsigned short :1;\r
+ unsigned short DTCH:1;\r
+ unsigned short ATTCH:1;\r
+ unsigned short :4;\r
+ unsigned short EOFERR:1;\r
+ unsigned short SIGN:1;\r
+ unsigned short SACK:1;\r
+ unsigned short :3;\r
+ unsigned short PDDETINT0:1;\r
+ } BIT;\r
+ } INTSTS1;\r
+ char wk9[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BRDY:1;\r
+ unsigned short PIPE8BRDY:1;\r
+ unsigned short PIPE7BRDY:1;\r
+ unsigned short PIPE6BRDY:1;\r
+ unsigned short PIPE5BRDY:1;\r
+ unsigned short PIPE4BRDY:1;\r
+ unsigned short PIPE3BRDY:1;\r
+ unsigned short PIPE2BRDY:1;\r
+ unsigned short PIPE1BRDY:1;\r
+ unsigned short PIPE0BRDY:1;\r
+ } BIT;\r
+ } BRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9NRDY:1;\r
+ unsigned short PIPE8NRDY:1;\r
+ unsigned short PIPE7NRDY:1;\r
+ unsigned short PIPE6NRDY:1;\r
+ unsigned short PIPE5NRDY:1;\r
+ unsigned short PIPE4NRDY:1;\r
+ unsigned short PIPE3NRDY:1;\r
+ unsigned short PIPE2NRDY:1;\r
+ unsigned short PIPE1NRDY:1;\r
+ unsigned short PIPE0NRDY:1;\r
+ } BIT;\r
+ } NRDYSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PIPE9BEMP:1;\r
+ unsigned short PIPE8BEMP:1;\r
+ unsigned short PIPE7BEMP:1;\r
+ unsigned short PIPE6BEMP:1;\r
+ unsigned short PIPE5BEMP:1;\r
+ unsigned short PIPE4BEMP:1;\r
+ unsigned short PIPE3BEMP:1;\r
+ unsigned short PIPE2BEMP:1;\r
+ unsigned short PIPE1BEMP:1;\r
+ unsigned short PIPE0BEMP:1;\r
+ } BIT;\r
+ } BEMPSTS;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short OVRN:1;\r
+ unsigned short CRCE:1;\r
+ unsigned short :3;\r
+ unsigned short FRNM:11;\r
+ } BIT;\r
+ } FRMNUM;\r
+ char wk10[6];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BREQUEST:8;\r
+ unsigned short BMREQUESTTYPE:8;\r
+ } BIT;\r
+ } USBREQ;\r
+ unsigned short USBVAL;\r
+ unsigned short USBINDX;\r
+ unsigned short USBLENG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :2;\r
+ unsigned short DIR:1;\r
+ } BIT;\r
+ } DCPCFG;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DEVSEL:4;\r
+ unsigned short :5;\r
+ unsigned short MXPS:7;\r
+ } BIT;\r
+ } DCPMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short SUREQ:1;\r
+ unsigned short :2;\r
+ unsigned short SUREQCLR:1;\r
+ unsigned short :2;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :2;\r
+ unsigned short CCPL:1;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } DCPCTR;\r
+ char wk11[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :12;\r
+ unsigned short PIPESEL:4;\r
+ } BIT;\r
+ } PIPESEL;\r
+ char wk12[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short TYPE:2;\r
+ unsigned short :3;\r
+ unsigned short BFRE:1;\r
+ unsigned short DBLB:1;\r
+ unsigned short :1;\r
+ unsigned short SHTNAK:1;\r
+ unsigned short :2;\r
+ unsigned short DIR:1;\r
+ unsigned short EPNUM:4;\r
+ } BIT;\r
+ } PIPECFG;\r
+ char wk13[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short DEVSEL:4;\r
+ unsigned short :3;\r
+ unsigned short MXPS:9;\r
+ } BIT;\r
+ } PIPEMAXP;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :3;\r
+ unsigned short IFIS:1;\r
+ unsigned short :9;\r
+ unsigned short IITV:3;\r
+ } BIT;\r
+ } PIPEPERI;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE1CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE2CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE3CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE4CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short INBUFM:1;\r
+ unsigned short :3;\r
+ unsigned short ATREPM:1;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE5CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE6CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE7CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE8CTR;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short BSTS:1;\r
+ unsigned short :5;\r
+ unsigned short ACLRM:1;\r
+ unsigned short SQCLR:1;\r
+ unsigned short SQSET:1;\r
+ unsigned short SQMON:1;\r
+ unsigned short PBUSY:1;\r
+ unsigned short :3;\r
+ unsigned short PID:2;\r
+ } BIT;\r
+ } PIPE9CTR;\r
+ char wk14[14];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE1TRE;\r
+ unsigned short PIPE1TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE2TRE;\r
+ unsigned short PIPE2TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE3TRE;\r
+ unsigned short PIPE3TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE4TRE;\r
+ unsigned short PIPE4TRN;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short TRENB:1;\r
+ unsigned short TRCLR:1;\r
+ } BIT;\r
+ } PIPE5TRE;\r
+ unsigned short PIPE5TRN;\r
+ char wk15[12];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :6;\r
+ unsigned short PDDETSTS0:1;\r
+ unsigned short CHGDETSTS0:1;\r
+ unsigned short BATCHGE0:1;\r
+ unsigned short :1;\r
+ unsigned short VDMSRCE0:1;\r
+ unsigned short IDPSINKE0:1;\r
+ unsigned short VDPSRCE0:1;\r
+ unsigned short IDMSINKE0:1;\r
+ unsigned short IDPSRCE0:1;\r
+ unsigned short RPDME0:1;\r
+ } BIT;\r
+ } USBBCCTRL0;\r
+ char wk16[26];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :15;\r
+ unsigned short VDDUSBE:1;\r
+ } BIT;\r
+ } USBMC;\r
+ char wk17[2];\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD0;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD1;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD2;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD3;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD4;\r
+ union {\r
+ unsigned short WORD;\r
+ struct {\r
+ unsigned short :8;\r
+ unsigned short USBSPD:2;\r
+ } BIT;\r
+ } DEVADD5;\r
+};\r
+\r
+enum enum_ir {\r
+IR_BSC_BUSERR=16,IR_ICU_SWINT=27,\r
+IR_CMT0_CMI0,\r
+IR_CMT1_CMI1,\r
+IR_CMT2_CMI2,\r
+IR_CMT3_CMI3,\r
+IR_CAC_FERRF,IR_CAC_MENDF,IR_CAC_OVFF,\r
+IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,\r
+IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,\r
+IR_DOC_DOPCF=57,\r
+IR_CMPB_CMPB0,IR_CMPB_CMPB1,\r
+IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN,\r
+IR_RTC_CUP,\r
+IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,\r
+IR_LVD_LVD1=88,IR_LVD_LVD2,\r
+IR_USB0_USBR0,\r
+IR_RTC_ALM=92,IR_RTC_PRD,\r
+IR_S12AD_S12ADI0=102,IR_S12AD_GBADI,\r
+IR_ELC_ELSR18I=106,\r
+IR_SSI0_SSIF0=108,IR_SSI0_SSIRXI0,IR_SSI0_SSITXI0,\r
+IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,\r
+IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,\r
+IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,\r
+IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,\r
+IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,\r
+IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,\r
+IR_POE_OEI1=170,IR_POE_OEI2,\r
+IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0,\r
+IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1,\r
+IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2,\r
+IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3,\r
+IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2,\r
+IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0,\r
+IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,\r
+IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,\r
+IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6,\r
+IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8,\r
+IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9,\r
+IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3,\r
+IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0\r
+};\r
+\r
+enum enum_dtce {\r
+DTCE_ICU_SWINT=27,\r
+DTCE_CMT0_CMI0,\r
+DTCE_CMT1_CMI1,\r
+DTCE_CMT2_CMI2,\r
+DTCE_CMT3_CMI3,\r
+DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,\r
+DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0,\r
+DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1,\r
+DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD,\r
+DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,\r
+DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI,\r
+DTCE_ELC_ELSR18I=106,\r
+DTCE_SSI0_SSIRXI0=109,DTCE_SSI0_SSITXI0,\r
+DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,\r
+DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1,\r
+DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2,\r
+DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,\r
+DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,\r
+DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,\r
+DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0,\r
+DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1,\r
+DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2,\r
+DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3,\r
+DTCE_SCI2_RXI2=187,DTCE_SCI2_TXI2,\r
+DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0,\r
+DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1,\r
+DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5,\r
+DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6,\r
+DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8,\r
+DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9,\r
+DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12,\r
+DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0\r
+};\r
+\r
+enum enum_ier {\r
+IER_BSC_BUSERR=0x02,\r
+IER_ICU_SWINT=0x03,\r
+IER_CMT0_CMI0=0x03,\r
+IER_CMT1_CMI1=0x03,\r
+IER_CMT2_CMI2=0x03,\r
+IER_CMT3_CMI3=0x03,\r
+IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04,\r
+IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,\r
+IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,\r
+IER_DOC_DOPCF=0x07,\r
+IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07,\r
+IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07,\r
+IER_RTC_CUP=0x07,\r
+IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,\r
+IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B,\r
+IER_USB0_USBR0=0x0B,\r
+IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B,\r
+IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C,\r
+IER_ELC_ELSR18I=0x0D,\r
+IER_SSI0_SSIF0=0x0D,IER_SSI0_SSIRXI0=0x0D,IER_SSI0_SSITXI0=0x0D,\r
+IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,\r
+IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,\r
+IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,\r
+IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,\r
+IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,\r
+IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11,\r
+IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,\r
+IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16,\r
+IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16,\r
+IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16,\r
+IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17,\r
+IER_SCI2_ERI2=0x17,IER_SCI2_RXI2=0x17,IER_SCI2_TXI2=0x17,IER_SCI2_TEI2=0x17,\r
+IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B,\r
+IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,\r
+IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C,\r
+IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C,\r
+IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D,\r
+IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D,\r
+IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E,\r
+IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F\r
+};\r
+\r
+enum enum_ipr {\r
+IPR_BSC_BUSERR=0,\r
+IPR_ICU_SWINT=3,\r
+IPR_CMT0_CMI0=4,\r
+IPR_CMT1_CMI1=5,\r
+IPR_CMT2_CMI2=6,\r
+IPR_CMT3_CMI3=7,\r
+IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34,\r
+IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38,\r
+IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44,\r
+IPR_DOC_DOPCF=57,\r
+IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59,\r
+IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60,\r
+IPR_RTC_CUP=63,\r
+IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,\r
+IPR_LVD_LVD1=88,IPR_LVD_LVD2=89,\r
+IPR_USB0_USBR0=90,\r
+IPR_RTC_ALM=92,IPR_RTC_PRD=93,\r
+IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103,\r
+IPR_ELC_ELSR18I=106,\r
+IPR_SSI0_SSIF0=108,IPR_SSI0_SSIRXI0=108,IPR_SSI0_SSITXI0=108,\r
+IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118,\r
+IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123,\r
+IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127,\r
+IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133,\r
+IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138,\r
+IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139,\r
+IPR_POE_OEI1=170,IPR_POE_OEI2=171,\r
+IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174,\r
+IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177,\r
+IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180,\r
+IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183,\r
+IPR_SCI2_ERI2=186,IPR_SCI2_RXI2=186,IPR_SCI2_TXI2=186,IPR_SCI2_TEI2=186,\r
+IPR_SCI0_ERI0=214,IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214,\r
+IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218,\r
+IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222,\r
+IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226,\r
+IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230,\r
+IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234,\r
+IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245,\r
+IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249\r
+};\r
+\r
+#define IEN_BSC_BUSERR IEN0\r
+#define IEN_ICU_SWINT IEN3\r
+#define IEN_CMT0_CMI0 IEN4\r
+#define IEN_CMT1_CMI1 IEN5\r
+#define IEN_CMT2_CMI2 IEN6\r
+#define IEN_CMT3_CMI3 IEN7\r
+#define IEN_CAC_FERRF IEN0\r
+#define IEN_CAC_MENDF IEN1\r
+#define IEN_CAC_OVFF IEN2\r
+#define IEN_USB0_D0FIFO0 IEN4\r
+#define IEN_USB0_D1FIFO0 IEN5\r
+#define IEN_USB0_USBI0 IEN6\r
+#define IEN_RSPI0_SPEI0 IEN4\r
+#define IEN_RSPI0_SPRI0 IEN5\r
+#define IEN_RSPI0_SPTI0 IEN6\r
+#define IEN_RSPI0_SPII0 IEN7\r
+#define IEN_DOC_DOPCF IEN1\r
+#define IEN_CMPB_CMPB0 IEN2\r
+#define IEN_CMPB_CMPB1 IEN3\r
+#define IEN_CTSU_CTSUWR IEN4\r
+#define IEN_CTSU_CTSURD IEN5\r
+#define IEN_CTSU_CTSUFN IEN6\r
+#define IEN_RTC_CUP IEN7\r
+#define IEN_ICU_IRQ0 IEN0\r
+#define IEN_ICU_IRQ1 IEN1\r
+#define IEN_ICU_IRQ2 IEN2\r
+#define IEN_ICU_IRQ3 IEN3\r
+#define IEN_ICU_IRQ4 IEN4\r
+#define IEN_ICU_IRQ5 IEN5\r
+#define IEN_ICU_IRQ6 IEN6\r
+#define IEN_ICU_IRQ7 IEN7\r
+#define IEN_LVD_LVD1 IEN0\r
+#define IEN_LVD_LVD2 IEN1\r
+#define IEN_USB0_USBR0 IEN2\r
+#define IEN_RTC_ALM IEN4\r
+#define IEN_RTC_PRD IEN5\r
+#define IEN_S12AD_S12ADI0 IEN6\r
+#define IEN_S12AD_GBADI IEN7\r
+#define IEN_ELC_ELSR18I IEN2\r
+#define IEN_SSI0_SSIF0 IEN4\r
+#define IEN_SSI0_SSIRXI0 IEN5\r
+#define IEN_SSI0_SSITXI0 IEN6\r
+#define IEN_MTU0_TGIA0 IEN2\r
+#define IEN_MTU0_TGIB0 IEN3\r
+#define IEN_MTU0_TGIC0 IEN4\r
+#define IEN_MTU0_TGID0 IEN5\r
+#define IEN_MTU0_TCIV0 IEN6\r
+#define IEN_MTU0_TGIE0 IEN7\r
+#define IEN_MTU0_TGIF0 IEN0\r
+#define IEN_MTU1_TGIA1 IEN1\r
+#define IEN_MTU1_TGIB1 IEN2\r
+#define IEN_MTU1_TCIV1 IEN3\r
+#define IEN_MTU1_TCIU1 IEN4\r
+#define IEN_MTU2_TGIA2 IEN5\r
+#define IEN_MTU2_TGIB2 IEN6\r
+#define IEN_MTU2_TCIV2 IEN7\r
+#define IEN_MTU2_TCIU2 IEN0\r
+#define IEN_MTU3_TGIA3 IEN1\r
+#define IEN_MTU3_TGIB3 IEN2\r
+#define IEN_MTU3_TGIC3 IEN3\r
+#define IEN_MTU3_TGID3 IEN4\r
+#define IEN_MTU3_TCIV3 IEN5\r
+#define IEN_MTU4_TGIA4 IEN6\r
+#define IEN_MTU4_TGIB4 IEN7\r
+#define IEN_MTU4_TGIC4 IEN0\r
+#define IEN_MTU4_TGID4 IEN1\r
+#define IEN_MTU4_TCIV4 IEN2\r
+#define IEN_MTU5_TGIU5 IEN3\r
+#define IEN_MTU5_TGIV5 IEN4\r
+#define IEN_MTU5_TGIW5 IEN5\r
+#define IEN_POE_OEI1 IEN2\r
+#define IEN_POE_OEI2 IEN3\r
+#define IEN_TMR0_CMIA0 IEN6\r
+#define IEN_TMR0_CMIB0 IEN7\r
+#define IEN_TMR0_OVI0 IEN0\r
+#define IEN_TMR1_CMIA1 IEN1\r
+#define IEN_TMR1_CMIB1 IEN2\r
+#define IEN_TMR1_OVI1 IEN3\r
+#define IEN_TMR2_CMIA2 IEN4\r
+#define IEN_TMR2_CMIB2 IEN5\r
+#define IEN_TMR2_OVI2 IEN6\r
+#define IEN_TMR3_CMIA3 IEN7\r
+#define IEN_TMR3_CMIB3 IEN0\r
+#define IEN_TMR3_OVI3 IEN1\r
+#define IEN_SCI2_ERI2 IEN2\r
+#define IEN_SCI2_RXI2 IEN3\r
+#define IEN_SCI2_TXI2 IEN4\r
+#define IEN_SCI2_TEI2 IEN5\r
+#define IEN_SCI0_ERI0 IEN6\r
+#define IEN_SCI0_RXI0 IEN7\r
+#define IEN_SCI0_TXI0 IEN0\r
+#define IEN_SCI0_TEI0 IEN1\r
+#define IEN_SCI1_ERI1 IEN2\r
+#define IEN_SCI1_RXI1 IEN3\r
+#define IEN_SCI1_TXI1 IEN4\r
+#define IEN_SCI1_TEI1 IEN5\r
+#define IEN_SCI5_ERI5 IEN6\r
+#define IEN_SCI5_RXI5 IEN7\r
+#define IEN_SCI5_TXI5 IEN0\r
+#define IEN_SCI5_TEI5 IEN1\r
+#define IEN_SCI6_ERI6 IEN2\r
+#define IEN_SCI6_RXI6 IEN3\r
+#define IEN_SCI6_TXI6 IEN4\r
+#define IEN_SCI6_TEI6 IEN5\r
+#define IEN_SCI8_ERI8 IEN6\r
+#define IEN_SCI8_RXI8 IEN7\r
+#define IEN_SCI8_TXI8 IEN0\r
+#define IEN_SCI8_TEI8 IEN1\r
+#define IEN_SCI9_ERI9 IEN2\r
+#define IEN_SCI9_RXI9 IEN3\r
+#define IEN_SCI9_TXI9 IEN4\r
+#define IEN_SCI9_TEI9 IEN5\r
+#define IEN_SCI12_ERI12 IEN6\r
+#define IEN_SCI12_RXI12 IEN7\r
+#define IEN_SCI12_TXI12 IEN0\r
+#define IEN_SCI12_TEI12 IEN1\r
+#define IEN_SCI12_SCIX0 IEN2\r
+#define IEN_SCI12_SCIX1 IEN3\r
+#define IEN_SCI12_SCIX2 IEN4\r
+#define IEN_SCI12_SCIX3 IEN5\r
+#define IEN_RIIC0_EEI0 IEN6\r
+#define IEN_RIIC0_RXI0 IEN7\r
+#define IEN_RIIC0_TXI0 IEN0\r
+#define IEN_RIIC0_TEI0 IEN1\r
+\r
+#define VECT_BSC_BUSERR 16\r
+#define VECT_ICU_SWINT 27\r
+#define VECT_CMT0_CMI0 28\r
+#define VECT_CMT1_CMI1 29\r
+#define VECT_CMT2_CMI2 30\r
+#define VECT_CMT3_CMI3 31\r
+#define VECT_CAC_FERRF 32\r
+#define VECT_CAC_MENDF 33\r
+#define VECT_CAC_OVFF 34\r
+#define VECT_USB0_D0FIFO0 36\r
+#define VECT_USB0_D1FIFO0 37\r
+#define VECT_USB0_USBI0 38\r
+#define VECT_RSPI0_SPEI0 44\r
+#define VECT_RSPI0_SPRI0 45\r
+#define VECT_RSPI0_SPTI0 46\r
+#define VECT_RSPI0_SPII0 47\r
+#define VECT_DOC_DOPCF 57\r
+#define VECT_CMPB_CMPB0 58\r
+#define VECT_CMPB_CMPB1 59\r
+#define VECT_CTSU_CTSUWR 60\r
+#define VECT_CTSU_CTSURD 61\r
+#define VECT_CTSU_CTSUFN 62\r
+#define VECT_RTC_CUP 63\r
+#define VECT_ICU_IRQ0 64\r
+#define VECT_ICU_IRQ1 65\r
+#define VECT_ICU_IRQ2 66\r
+#define VECT_ICU_IRQ3 67\r
+#define VECT_ICU_IRQ4 68\r
+#define VECT_ICU_IRQ5 69\r
+#define VECT_ICU_IRQ6 70\r
+#define VECT_ICU_IRQ7 71\r
+#define VECT_LVD_LVD1 88\r
+#define VECT_LVD_LVD2 89\r
+#define VECT_USB0_USBR0 90\r
+#define VECT_RTC_ALM 92\r
+#define VECT_RTC_PRD 93\r
+#define VECT_S12AD_S12ADI0 102\r
+#define VECT_S12AD_GBADI 103\r
+#define VECT_ELC_ELSR18I 106\r
+#define VECT_SSI0_SSIF0 108\r
+#define VECT_SSI0_SSIRXI0 109\r
+#define VECT_SSI0_SSITXI0 110\r
+#define VECT_MTU0_TGIA0 114\r
+#define VECT_MTU0_TGIB0 115\r
+#define VECT_MTU0_TGIC0 116\r
+#define VECT_MTU0_TGID0 117\r
+#define VECT_MTU0_TCIV0 118\r
+#define VECT_MTU0_TGIE0 119\r
+#define VECT_MTU0_TGIF0 120\r
+#define VECT_MTU1_TGIA1 121\r
+#define VECT_MTU1_TGIB1 122\r
+#define VECT_MTU1_TCIV1 123\r
+#define VECT_MTU1_TCIU1 124\r
+#define VECT_MTU2_TGIA2 125\r
+#define VECT_MTU2_TGIB2 126\r
+#define VECT_MTU2_TCIV2 127\r
+#define VECT_MTU2_TCIU2 128\r
+#define VECT_MTU3_TGIA3 129\r
+#define VECT_MTU3_TGIB3 130\r
+#define VECT_MTU3_TGIC3 131\r
+#define VECT_MTU3_TGID3 132\r
+#define VECT_MTU3_TCIV3 133\r
+#define VECT_MTU4_TGIA4 134\r
+#define VECT_MTU4_TGIB4 135\r
+#define VECT_MTU4_TGIC4 136\r
+#define VECT_MTU4_TGID4 137\r
+#define VECT_MTU4_TCIV4 138\r
+#define VECT_MTU5_TGIU5 139\r
+#define VECT_MTU5_TGIV5 140\r
+#define VECT_MTU5_TGIW5 141\r
+#define VECT_POE_OEI1 170\r
+#define VECT_POE_OEI2 171\r
+#define VECT_TMR0_CMIA0 174\r
+#define VECT_TMR0_CMIB0 175\r
+#define VECT_TMR0_OVI0 176\r
+#define VECT_TMR1_CMIA1 177\r
+#define VECT_TMR1_CMIB1 178\r
+#define VECT_TMR1_OVI1 179\r
+#define VECT_TMR2_CMIA2 180\r
+#define VECT_TMR2_CMIB2 181\r
+#define VECT_TMR2_OVI2 182\r
+#define VECT_TMR3_CMIA3 183\r
+#define VECT_TMR3_CMIB3 184\r
+#define VECT_TMR3_OVI3 185\r
+#define VECT_SCI2_ERI2 186\r
+#define VECT_SCI2_RXI2 187\r
+#define VECT_SCI2_TXI2 188\r
+#define VECT_SCI2_TEI2 189\r
+#define VECT_SCI0_ERI0 214\r
+#define VECT_SCI0_RXI0 215\r
+#define VECT_SCI0_TXI0 216\r
+#define VECT_SCI0_TEI0 217\r
+#define VECT_SCI1_ERI1 218\r
+#define VECT_SCI1_RXI1 219\r
+#define VECT_SCI1_TXI1 220\r
+#define VECT_SCI1_TEI1 221\r
+#define VECT_SCI5_ERI5 222\r
+#define VECT_SCI5_RXI5 223\r
+#define VECT_SCI5_TXI5 224\r
+#define VECT_SCI5_TEI5 225\r
+#define VECT_SCI6_ERI6 226\r
+#define VECT_SCI6_RXI6 227\r
+#define VECT_SCI6_TXI6 228\r
+#define VECT_SCI6_TEI6 229\r
+#define VECT_SCI8_ERI8 230\r
+#define VECT_SCI8_RXI8 231\r
+#define VECT_SCI8_TXI8 232\r
+#define VECT_SCI8_TEI8 233\r
+#define VECT_SCI9_ERI9 234\r
+#define VECT_SCI9_RXI9 235\r
+#define VECT_SCI9_TXI9 236\r
+#define VECT_SCI9_TEI9 237\r
+#define VECT_SCI12_ERI12 238\r
+#define VECT_SCI12_RXI12 239\r
+#define VECT_SCI12_TXI12 240\r
+#define VECT_SCI12_TEI12 241\r
+#define VECT_SCI12_SCIX0 242\r
+#define VECT_SCI12_SCIX1 243\r
+#define VECT_SCI12_SCIX2 244\r
+#define VECT_SCI12_SCIX3 245\r
+#define VECT_RIIC0_EEI0 246\r
+#define VECT_RIIC0_RXI0 247\r
+#define VECT_RIIC0_TXI0 248\r
+#define VECT_RIIC0_TEI0 249\r
+\r
+#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28\r
+#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA18\r
+#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17\r
+#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15\r
+#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14\r
+#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14\r
+#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9\r
+#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5\r
+#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4\r
+#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
+#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
+#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
+#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
+#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
+#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
+#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
+#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
+#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23\r
+#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21\r
+#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19\r
+#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17\r
+#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10\r
+#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9\r
+#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6\r
+#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
+#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27\r
+#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27\r
+#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26\r
+#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26\r
+#define MSTP_IRDA SYSTEM.MSTPCRC.BIT.MSTPC20\r
+#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19\r
+#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0\r
+#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15\r
+#define MSTP_LCDC SYSTEM.MSTPCRD.BIT.MSTPD11\r
+#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10\r
+\r
+#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR\r
+#define _IR( x ) __IR( x )\r
+#define IR( x , y ) _IR( _ ## x ## _ ## y )\r
+#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE\r
+#define _DTCE( x ) __DTCE( x )\r
+#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )\r
+#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x\r
+#define _IEN( x ) __IEN( x )\r
+#define IEN( x , y ) _IEN( _ ## x ## _ ## y )\r
+#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR\r
+#define _IPR( x ) __IPR( x )\r
+#define IPR( x , y ) _IPR( _ ## x ## _ ## y )\r
+#define __VECT( x ) VECT ## x\r
+#define _VECT( x ) __VECT( x )\r
+#define VECT( x , y ) _VECT( _ ## x ## _ ## y )\r
+#define __MSTP( x ) MSTP ## x\r
+#define _MSTP( x ) __MSTP( x )\r
+#define MSTP( x ) _MSTP( _ ## x )\r
+\r
+#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300)\r
+#define CAC (*(volatile struct st_cac __evenaccess *)0x8B000)\r
+#define CMPB (*(volatile struct st_cmpb __evenaccess *)0x8C580)\r
+#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000)\r
+#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002)\r
+#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008)\r
+#define CMT2 (*(volatile struct st_cmt0 __evenaccess *)0x88012)\r
+#define CMT3 (*(volatile struct st_cmt0 __evenaccess *)0x88018)\r
+#define CRC (*(volatile struct st_crc __evenaccess *)0x88280)\r
+#define CTSU (*(volatile struct st_ctsu __evenaccess *)0xA0900)\r
+#define DA (*(volatile struct st_da __evenaccess *)0x88040)\r
+#define DOC (*(volatile struct st_doc __evenaccess *)0x8B080)\r
+#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400)\r
+#define ELC (*(volatile struct st_elc __evenaccess *)0x8B100)\r
+#define FLASH (*(volatile struct st_flash __evenaccess *)0x7FC090)\r
+#define ICU (*(volatile struct st_icu __evenaccess *)0x87000)\r
+#define IRDA (*(volatile struct st_irda __evenaccess *)0x88410)\r
+#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030)\r
+#define LCDC (*(volatile struct st_lcdc __evenaccess *)0xA0800)\r
+#define MPC (*(volatile struct st_mpc __evenaccess *)0x8C11F)\r
+#define MTU (*(volatile struct st_mtu __evenaccess *)0x8860A)\r
+#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0x88690)\r
+#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0x88690)\r
+#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0x88692)\r
+#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0x88600)\r
+#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0x88600)\r
+#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0x88694)\r
+#define POE (*(volatile struct st_poe __evenaccess *)0x88900)\r
+#define PORT (*(volatile struct st_port __evenaccess *)0x8C121)\r
+#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000)\r
+#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001)\r
+#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002)\r
+#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003)\r
+#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004)\r
+#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005)\r
+#define PORT9 (*(volatile struct st_port9 __evenaccess *)0x8C009)\r
+#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A)\r
+#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B)\r
+#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C)\r
+#define PORTD (*(volatile struct st_portd __evenaccess *)0x8C00D)\r
+#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E)\r
+#define PORTF (*(volatile struct st_portf __evenaccess *)0x8C00F)\r
+#define PORTH (*(volatile struct st_porth __evenaccess *)0x8C051)\r
+#define PORTJ (*(volatile struct st_portj __evenaccess *)0x8C012)\r
+#define RIIC0 (*(volatile struct st_riic __evenaccess *)0x88300)\r
+#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0x88380)\r
+#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400)\r
+#define RTCB (*(volatile struct st_rtcb __evenaccess *)0x8C402)\r
+#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000)\r
+#define SCI0 (*(volatile struct st_sci0 __evenaccess *)0x8A000)\r
+#define SCI1 (*(volatile struct st_sci0 __evenaccess *)0x8A020)\r
+#define SCI2 (*(volatile struct st_sci0 __evenaccess *)0x8A040)\r
+#define SCI5 (*(volatile struct st_sci0 __evenaccess *)0x8A0A0)\r
+#define SCI6 (*(volatile struct st_sci0 __evenaccess *)0x8A0C0)\r
+#define SCI8 (*(volatile struct st_sci0 __evenaccess *)0x8A100)\r
+#define SCI9 (*(volatile struct st_sci0 __evenaccess *)0x8A120)\r
+#define SCI12 (*(volatile struct st_sci12 __evenaccess *)0x8B300)\r
+#define SMCI0 (*(volatile struct st_smci __evenaccess *)0x8A000)\r
+#define SMCI1 (*(volatile struct st_smci __evenaccess *)0x8A020)\r
+#define SMCI2 (*(volatile struct st_smci __evenaccess *)0x8A040)\r
+#define SMCI5 (*(volatile struct st_smci __evenaccess *)0x8A0A0)\r
+#define SMCI6 (*(volatile struct st_smci __evenaccess *)0x8A0C0)\r
+#define SMCI8 (*(volatile struct st_smci __evenaccess *)0x8A100)\r
+#define SMCI9 (*(volatile struct st_smci __evenaccess *)0x8A120)\r
+#define SMCI12 (*(volatile struct st_smci __evenaccess *)0x8B300)\r
+#define SSI0 (*(volatile struct st_ssi __evenaccess *)0x8A500)\r
+#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000)\r
+#define TEMPS (*(volatile struct st_temps __evenaccess *)0x7FC0AC)\r
+#define TMR0 (*(volatile struct st_tmr0 __evenaccess *)0x88200)\r
+#define TMR1 (*(volatile struct st_tmr1 __evenaccess *)0x88201)\r
+#define TMR2 (*(volatile struct st_tmr0 __evenaccess *)0x88210)\r
+#define TMR3 (*(volatile struct st_tmr1 __evenaccess *)0x88211)\r
+#define TMR01 (*(volatile struct st_tmr01 __evenaccess *)0x88204)\r
+#define TMR23 (*(volatile struct st_tmr01 __evenaccess *)0x88214)\r
+#define USB0 (*(volatile struct st_usb0 __evenaccess *)0xA0000)\r
+#pragma bit_order\r
+#pragma packoption\r
+#endif\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup, standard FreeRTOS hook functions, and the ISR hander called\r
+ * by the RTOS after interrupt entry (including nesting) has been taken care of.\r
+ *\r
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON\r
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO\r
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Renesas includes. */\r
+/* Renesas includes. */\r
+#include <rskrx113def.h>\r
+#include "r_cg_macrodriver.h"\r
+#include "r_cg_sci.h"\r
+#include "r_rsk_async.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware as necessary to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ extern void main_blinky( void );\r
+#else\r
+ extern void main_full( void );\r
+#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Configure the hardware ready to run the demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Set up SCI1 receive buffer */\r
+ R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
+\r
+ /* Enable SCI1 operations */\r
+ R_SCI1_Start();\r
+\r
+ LED0 = LED_OFF;\r
+ LED1 = LED_OFF;\r
+ LED2 = LED_OFF;\r
+ LED3 = LED_OFF;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
+ internally by FreeRTOS API functions that create tasks, queues, software\r
+ timers, and semaphores. The size of the FreeRTOS heap is set by the\r
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeHeapSpace;\r
+\r
+ /* This is just a trivial example of an idle hook. It is called on each\r
+ cycle of the idle task. It must *NOT* attempt to block. In this case the\r
+ idle task just queries the amount of FreeRTOS heap that remains. See the\r
+ memory management section on the http://www.FreeRTOS.org web site for memory\r
+ management options. If there is a lot of heap memory free then the\r
+ configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
+ RAM. */\r
+ xFreeHeapSpace = xPortGetFreeHeapSize();\r
+\r
+ /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
+ ( void ) xFreeHeapSpace;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0\r
+ {\r
+ extern void vFullDemoTickHook( void );\r
+\r
+ vFullDemoTickHook();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The RX port uses this callback function to configure its tick interrupt.\r
+This allows the application to choose the tick interrupt source. */\r
+void vApplicationSetupTimerInterrupt( void )\r
+{\r
+const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL;\r
+\r
+ /* Disable register write protection. */\r
+ SYSTEM.PRCR.WORD = ulEnableRegisterWrite;\r
+\r
+ /* Enable compare match timer 0. */\r
+ MSTP( CMT0 ) = 0;\r
+\r
+ /* Interrupt on compare match. */\r
+ CMT0.CMCR.BIT.CMIE = 1;\r
+\r
+ /* Set the compare match value. */\r
+ CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 );\r
+\r
+ /* Divide the PCLK by 8. */\r
+ CMT0.CMCR.BIT.CKS = 0;\r
+\r
+ /* Enable the interrupt... */\r
+ _IEN( _CMT0_CMI0 ) = 1;\r
+\r
+ /* ...and set its priority to the application defined kernel priority. */\r
+ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;\r
+\r
+ /* Start the timer. */\r
+ CMT.CMSTR0.BIT.STR0 = 1;\r
+\r
+ /* Reneable register protection. */\r
+ SYSTEM.PRCR.WORD = ulDisableRegisterWrite;\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* DISCLAIMER\r
+* This software is supplied by Renesas Electronics Corporation and is only \r
+* intended for use with Renesas products. No other uses are authorized. This \r
+* software is owned by Renesas Electronics Corporation and is protected under \r
+* all applicable laws, including copyright laws.\r
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING \r
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT \r
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE \r
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR \r
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE \r
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
+* Renesas reserves the right, without notice, to make changes to this software \r
+* and to discontinue the availability of this software. By using this software,\r
+* you agree to the additional terms and conditions found by accessing the \r
+* following link:\r
+* http://www.renesas.com/disclaimer\r
+*\r
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.\r
+*******************************************************************************/\r
+/*******************************************************************************\r
+* File Name : rskrx113def.h\r
+* Device(s) : R5F51138AxFP\r
+* Tool-Chain : CCRX\r
+* H/W Platform : RSKRX113\r
+* Description : Defines macros relating to the RSK user LEDs and switches\r
+* Creation Date: 26/08/2014\r
+*******************************************************************************/\r
+\r
+\r
+#ifndef RSKRX113_H\r
+#define RSKRX113_H\r
+\r
+/*******************************************************************************\r
+User Defines\r
+*******************************************************************************/\r
+/* General Values */\r
+#define LED_ON (0)\r
+#define LED_OFF (1)\r
+#define SET_BIT_HIGH (1)\r
+#define SET_BIT_LOW (0)\r
+#define SET_BYTE_HIGH (0xFF)\r
+#define SET_BYTE_LOW (0x00)\r
+\r
+/* Switches */\r
+#define SW1 (PORTJ.PIDR.BIT.B0)\r
+#define SW2 (PORT3.PIDR.BIT.B2)\r
+#define SW3 (PORT2.PIDR.BIT.B7)\r
+\r
+/* LED port settings */\r
+#define LED0 (PORT2.PODR.BIT.B2)\r
+#define LED1 (PORT2.PODR.BIT.B3)\r
+#define LED2 (PORT2.PODR.BIT.B4)\r
+#define LED3 (PORT2.PODR.BIT.B5)\r
+\r
+\r
+#endif\r
+\r
+++ /dev/null
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- </option>\r
- </data>\r
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- </plugin>\r
- </debuggerPlugins>\r
- </configuration>\r
- <configuration>\r
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- </configuration>\r
-</project>\r
-\r
-\r
+++ /dev/null
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-<project>\r
- <fileVersion>2</fileVersion>\r
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- <toolchain>\r
- <name>RX</name>\r
- </toolchain>\r
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-\r
+++ /dev/null
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-\r
+++ /dev/null
-################################################################################\r
-# Automatically-generated file. Do not edit!\r
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+++ /dev/null
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\ No newline at end of file
+++ /dev/null
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+++ /dev/null
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-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * NOTE 1: This project provides two demo applications. A simple blinky style\r
- * project, and a more comprehensive test and demo application. The\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
- * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
- * in main.c. This file implements the simply blinky style version.\r
- *\r
- * NOTE 2: This file only contains the source code that is specific to the\r
- * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
- * required to configure the hardware are defined in main.c.\r
- ******************************************************************************\r
- *\r
- * main_blinky() creates one queue, and two tasks. It then starts the\r
- * scheduler.\r
- *\r
- * The Queue Send Task:\r
- * The queue send task is implemented by the prvQueueSendTask() function in\r
- * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
- * block for 200 milliseconds, before sending the value 100 to the queue that\r
- * was created within main_blinky(). Once the value is sent, the task loops\r
- * back around to block for another 200 milliseconds...and so on.\r
- *\r
- * The Queue Receive Task:\r
- * The queue receive task is implemented by the prvQueueReceiveTask() function\r
- * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
- * blocks on attempts to read data from the queue that was created within\r
- * main_blinky(). When data is received, the task checks the value of the\r
- * data, and if the value equals the expected 100, toggles an LED. The 'block\r
- * time' parameter passed to the queue receive function specifies that the\r
- * task should be held in the Blocked state indefinitely to wait for data to\r
- * be available on the queue. The queue receive task will only leave the\r
- * Blocked state when the queue send task writes to the queue. As the queue\r
- * send task writes to the queue every 200 milliseconds, the queue receive\r
- * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
- * the LED every 200 milliseconds.\r
- */\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "semphr.h"\r
-\r
-/* Renesas includes. */\r
-#include <rskrx113def.h>\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_userdefine.h"\r
-\r
-/* Priorities at which the tasks are created. */\r
-#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-\r
-/* The rate at which data is sent to the queue. The 200ms value is converted\r
-to ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
-\r
-/* The number of items the queue can hold. This is 1 as the receive task\r
-will remove items as they are added, meaning the send task should always find\r
-the queue empty. */\r
-#define mainQUEUE_LENGTH ( 1 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in\r
- * main.c.\r
- */\r
-void main_blinky( void );\r
-\r
-/*\r
- * The tasks as described in the comments at the top of this file.\r
- */\r
-static void prvQueueReceiveTask( void *pvParameters );\r
-static void prvQueueSendTask( void *pvParameters );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The queue used by both tasks. */\r
-static QueueHandle_t xQueue = NULL;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void main_blinky( void )\r
-{\r
- /* Create the queue. */\r
- xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
-\r
- if( xQueue != NULL )\r
- {\r
- /* Start the two tasks as described in the comments at the top of this\r
- file. */\r
- xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
- "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
- configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
- NULL, /* The parameter passed to the task - not used in this case. */\r
- mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
- NULL ); /* The task handle is not required, so NULL is passed. */\r
-\r
- xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
-\r
- /* Start the tasks and timer running. */\r
- vTaskStartScheduler();\r
- }\r
-\r
- /* If all is well, the scheduler will now be running, and the following\r
- line will never be reached. If the following line does execute, then\r
- there was either insufficient FreeRTOS heap memory available for the idle\r
- and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
- User mode. See the memory management section on the FreeRTOS web site for\r
- more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
- mode from which main() is called is set in the C start up code and must be\r
- a privileged mode (not user mode). */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueSendTask( void *pvParameters )\r
-{\r
-TickType_t xNextWakeTime;\r
-const unsigned long ulValueToSend = 100UL;\r
-\r
- /* Remove compiler warning about unused parameter. */\r
- ( void ) pvParameters;\r
-\r
- /* Initialise xNextWakeTime - this only needs to be done once. */\r
- xNextWakeTime = xTaskGetTickCount();\r
-\r
- for( ;; )\r
- {\r
- /* Place this task in the blocked state until it is time to run again. */\r
- vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
-\r
- /* Send to the queue - causing the queue receive task to unblock and\r
- toggle the LED. 0 is used as the block time so the sending operation\r
- will not block - it shouldn't need to block as the queue should always\r
- be empty at this point in the code. */\r
- xQueueSend( xQueue, &ulValueToSend, 0U );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueReceiveTask( void *pvParameters )\r
-{\r
-unsigned long ulReceivedValue;\r
-const unsigned long ulExpectedValue = 100UL;\r
-\r
- /* Remove compiler warning about unused parameter. */\r
- ( void ) pvParameters;\r
-\r
- for( ;; )\r
- {\r
- /* Wait until something arrives in the queue - this task will block\r
- indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
- FreeRTOSConfig.h. */\r
- xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
-\r
- /* To get here something must have been received from the queue, but\r
- is it the expected value? If it is, toggle the LED. */\r
- if( ulReceivedValue == ulExpectedValue )\r
- {\r
- LED0 = !LED0;\r
- ulReceivedValue = 0U;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-\r
-#ifndef FREERTOS_CONFIG_H\r
-#define FREERTOS_CONFIG_H\r
-\r
-#ifdef __ICCRX__\r
- #include <iorx113.h>\r
- #include <machine.h>\r
-#endif\r
-\r
-#ifdef __GNUC__\r
- #include "iodefine.h"\r
-#endif\r
-\r
-/*-----------------------------------------------------------\r
- * Application specific definitions.\r
- *\r
- * These definitions should be adjusted for your particular hardware and\r
- * application requirements.\r
- *\r
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
- *\r
- * See http://www.freertos.org/a00110.html.\r
- *----------------------------------------------------------*/\r
-\r
-#define configUSE_PREEMPTION 1\r
-#define configUSE_IDLE_HOOK 0\r
-#define configUSE_TICK_HOOK 1\r
-#define configCPU_CLOCK_HZ ( 32000000 ) /* Set in mcu_info.h. */\r
-#define configPERIPHERAL_CLOCK_HZ ( 32000000 ) /* Set in muc_info.h. */\r
-#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 125 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) )\r
-#define configMAX_TASK_NAME_LEN ( 12 )\r
-#define configUSE_TRACE_FACILITY 1\r
-#define configUSE_16_BIT_TICKS 0\r
-#define configIDLE_SHOULD_YIELD 1\r
-#define configUSE_CO_ROUTINES 0\r
-#define configUSE_MUTEXES 1\r
-#define configGENERATE_RUN_TIME_STATS 0\r
-#define configCHECK_FOR_STACK_OVERFLOW 2\r
-#define configUSE_RECURSIVE_MUTEXES 1\r
-#define configQUEUE_REGISTRY_SIZE 0\r
-#define configUSE_MALLOC_FAILED_HOOK 0\r
-#define configUSE_APPLICATION_TASK_TAG 0\r
-#define configUSE_COUNTING_SEMAPHORES 1\r
-\r
-#define configMAX_PRIORITIES ( 7 )\r
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
-\r
-/* Software timer definitions. */\r
-#define configUSE_TIMERS 1\r
-#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
-#define configTIMER_QUEUE_LENGTH 5\r
-#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
-\r
-/* The interrupt priority used by the kernel itself for the tick interrupt and\r
-the pended interrupt. This would normally be the lowest priority. */\r
-#define configKERNEL_INTERRUPT_PRIORITY 1\r
-\r
-/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
-Interrupts that use a priority above this will not be effected by anything the\r
-kernel is doing. */\r
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
-\r
-/* Set the following definitions to 1 to include the API function, or zero\r
-to exclude the API function. */\r
-\r
-#define INCLUDE_vTaskPrioritySet 1\r
-#define INCLUDE_uxTaskPriorityGet 1\r
-#define INCLUDE_vTaskDelete 1\r
-#define INCLUDE_vTaskCleanUpResources 0\r
-#define INCLUDE_vTaskSuspend 1\r
-#define INCLUDE_vTaskDelayUntil 1\r
-#define INCLUDE_vTaskDelay 1\r
-#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
-#define INCLUDE_xTaskGetSchedulerState 1\r
-#define INCLUDE_eTaskGetState 1\r
-#define INCLUDE_xTimerPendFunctionCall 1\r
-\r
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
-\r
-/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros\r
-allow the application writer to add additional code before and after the MCU is\r
-placed into the low power state respectively. The implementations provided in\r
-this demo can be extended to save even more power - for example the analog\r
-input used by the low power demo could be switched off in the pre-sleep macro\r
-and back on again in the post sleep macro. */\r
-void vPreSleepProcessing( unsigned long xExpectedIdleTime );\r
-void vPostSleepProcessing( unsigned long xExpectedIdleTime );\r
-#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime );\r
-#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime );\r
-\r
-/* configTICK_VECTOR must be set to the interrupt vector used by the peripheral\r
-that generates the tick interrupt. */\r
-#define configTICK_VECTOR VECT_CMT0_CMI0\r
-\r
-#endif /* FREERTOS_CONFIG_H */\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*\r
- * This file contains the non-portable and therefore RX62N specific parts of\r
- * the IntQueue standard demo task - namely the configuration of the timers\r
- * that generate the interrupts and the interrupt entry points.\r
- */\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Demo includes. */\r
-#include "IntQueueTimer.h"\r
-#include "IntQueue.h"\r
-\r
-#define tmrTIMER_0_1_FREQUENCY ( 2000UL )\r
-#define tmrTIMER_2_3_FREQUENCY ( 2111UL )\r
-\r
-void vInitialiseTimerForIntQueueTest( void )\r
-{\r
- /* Ensure interrupts do not start until full configuration is complete. */\r
- portENTER_CRITICAL();\r
- {\r
- /* Give write access. */\r
- SYSTEM.PRCR.WORD = 0xa502;\r
-\r
- /* Cascade two 8bit timer channels to generate the interrupts.\r
- 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are\r
- utilised for this test. */\r
-\r
- /* Enable the timers. */\r
- SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;\r
- SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;\r
-\r
- /* Enable compare match A interrupt request. */\r
- TMR0.TCR.BIT.CMIEA = 1;\r
- TMR2.TCR.BIT.CMIEA = 1;\r
-\r
- /* Clear the timer on compare match A. */\r
- TMR0.TCR.BIT.CCLR = 1;\r
- TMR2.TCR.BIT.CCLR = 1;\r
-\r
- /* Set the compare match value. */\r
- TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
- TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
-\r
- /* 16 bit operation ( count from timer 1,2 ). */\r
- TMR0.TCCR.BIT.CSS = 3;\r
- TMR2.TCCR.BIT.CSS = 3;\r
-\r
- /* Use PCLK as the input. */\r
- TMR1.TCCR.BIT.CSS = 1;\r
- TMR3.TCCR.BIT.CSS = 1;\r
-\r
- /* Divide PCLK by 8. */\r
- TMR1.TCCR.BIT.CKS = 2;\r
- TMR3.TCCR.BIT.CKS = 2;\r
-\r
- /* Enable TMR 0, 2 interrupts. */\r
- TMR0.TCR.BIT.CMIEA = 1;\r
- TMR2.TCR.BIT.CMIEA = 1;\r
-\r
- /* Set interrupt priority and enable. */\r
- IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
- IR( TMR0, CMIA0 ) = 0U;\r
- IEN( TMR0, CMIA0 ) = 1U;\r
-\r
- /* Do the same for TMR2, but to vector 129. */\r
- IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;\r
- IR( TMR2, CMIA2 ) = 0U;\r
- IEN( TMR2, CMIA2 ) = 1U;\r
- }\r
- portEXIT_CRITICAL();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#ifdef __GNUC__\r
-\r
- void vIntQTimerISR0( void ) __attribute__ ((interrupt));\r
- void vIntQTimerISR1( void ) __attribute__ ((interrupt));\r
-\r
- void vIntQTimerISR0( void )\r
- {\r
- /* Enable interrupts to allow interrupt nesting. */\r
- __asm volatile( "setpsw i" );\r
-\r
- portYIELD_FROM_ISR( xFirstTimerHandler() );\r
- }\r
- /*-----------------------------------------------------------*/\r
-\r
- void vIntQTimerISR1( void )\r
- {\r
- /* Enable interrupts to allow interrupt nesting. */\r
- __asm volatile( "setpsw i" );\r
-\r
- portYIELD_FROM_ISR( xSecondTimerHandler() );\r
- }\r
-\r
-#endif /* __GNUC__ */\r
-\r
-#ifdef __ICCRX__\r
-\r
-#pragma vector = VECT_TMR0_CMIA0\r
-__interrupt void vT0_1InterruptHandler( void )\r
-{\r
- __enable_interrupt();\r
- portYIELD_FROM_ISR( xFirstTimerHandler() );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#pragma vector = VECT_TMR2_CMIA2\r
-__interrupt void vT2_3InterruptHandler( void )\r
-{\r
- __enable_interrupt();\r
- portYIELD_FROM_ISR( xSecondTimerHandler() );\r
-}\r
-\r
-#endif /* __ICCRX__ */\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-#ifndef INT_QUEUE_TIMER_H\r
-#define INT_QUEUE_TIMER_H\r
-\r
-void vInitialiseTimerForIntQueueTest( void );\r
-portBASE_TYPE xTimer0Handler( void );\r
-portBASE_TYPE xTimer1Handler( void );\r
-\r
-#endif\r
-\r
+++ /dev/null
-;/*\r
-; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
-; All rights reserved\r
-;\r
-; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-;\r
-; ***************************************************************************\r
-; * *\r
-; * FreeRTOS provides completely free yet professionally developed, *\r
-; * robust, strictly quality controlled, supported, and cross *\r
-; * platform software that has become a de facto standard. *\r
-; * *\r
-; * Help yourself get started quickly and support the FreeRTOS *\r
-; * project by purchasing a FreeRTOS tutorial book, reference *\r
-; * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
-; * *\r
-; * Thank you! *\r
-; * *\r
-; ***************************************************************************\r
-;\r
-; This file is part of the FreeRTOS distribution.\r
-;\r
-; FreeRTOS is free software; you can redistribute it and/or modify it under\r
-; the terms of the GNU General Public License (version 2) as published by the\r
-; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-;\r
-; >>! NOTE: The modification to the GPL is included to allow you to distribute\r
-; >>! a combined work that includes FreeRTOS without being obliged to provide\r
-; >>! the source code for proprietary components outside of the FreeRTOS\r
-; >>! kernel.\r
-;\r
-; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
-; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
-; FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
-; link: http://www.freertos.org/a00114.html\r
-;\r
-; 1 tab == 4 spaces!\r
-;\r
-; ***************************************************************************\r
-; * *\r
-; * Having a problem? Start by reading the FAQ "My application does *\r
-; * not run, what could be wrong?" *\r
-; * *\r
-; * http://www.FreeRTOS.org/FAQHelp.html *\r
-; * *\r
-; ***************************************************************************\r
-;\r
-; http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
-; license and Real Time Engineers Ltd. contact details.;\r
-;\r
-; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
-; including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
-; compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-;\r
-; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
-; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
-; licenses offer ticketed support, indemnification and middleware.\r
-;\r
-; http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
-; engineered and independently SIL3 certified version for use in safety and\r
-; mission critical applications that require provable dependability.\r
-;\r
-; 1 tab == 4 spaces!\r
-;*/\r
-\r
- .global _vRegTest1Implementation\r
- .global _vRegTest2Implementation\r
-\r
- .extern _ulRegTest1LoopCounter\r
- .extern _ulRegTest2LoopCounter\r
-\r
- .text\r
-\r
-\r
-;/* This function is explained in the comments at the top of main.c. */\r
-_vRegTest1Implementation:\r
-\r
- ; Put a known value in each register.\r
- MOV.L #1, R1\r
- MOV.L #2, R2\r
- MOV.L #3, R3\r
- MOV.L #4, R4\r
- MOV.L #5, R5\r
- MOV.L #6, R6\r
- MOV.L #7, R7\r
- MOV.L #8, R8\r
- MOV.L #9, R9\r
- MOV.L #10, R10\r
- MOV.L #11, R11\r
- MOV.L #12, R12\r
- MOV.L #13, R13\r
- MOV.L #14, R14\r
- MOV.L #15, R15\r
-\r
- ; Loop, checking each itteration that each register still contains the\r
- ; expected value.\r
-TestLoop1:\r
-\r
- ; Push the registers that are going to get clobbered.\r
- PUSHM R14-R15\r
-\r
- ; Increment the loop counter to show this task is still getting CPU time.\r
- MOV.L #_ulRegTest1LoopCounter, R14\r
- MOV.L [ R14 ], R15\r
- ADD #1, R15\r
- MOV.L R15, [ R14 ]\r
-\r
- ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register.\r
- MOV.L #1, R14\r
- MOV.L #0872E0H, R15\r
- MOV.B R14, [R15]\r
- NOP\r
- NOP\r
-\r
- ; Restore the clobbered registers.\r
- POPM R14-R15\r
-\r
- ; Now compare each register to ensure it still contains the value that was\r
- ; set before this loop was entered.\r
- CMP #1, R1\r
- BNE RegTest1Error\r
- CMP #2, R2\r
- BNE RegTest1Error\r
- CMP #3, R3\r
- BNE RegTest1Error\r
- CMP #4, R4\r
- BNE RegTest1Error\r
- CMP #5, R5\r
- BNE RegTest1Error\r
- CMP #6, R6\r
- BNE RegTest1Error\r
- CMP #7, R7\r
- BNE RegTest1Error\r
- CMP #8, R8\r
- BNE RegTest1Error\r
- CMP #9, R9\r
- BNE RegTest1Error\r
- CMP #10, R10\r
- BNE RegTest1Error\r
- CMP #11, R11\r
- BNE RegTest1Error\r
- CMP #12, R12\r
- BNE RegTest1Error\r
- CMP #13, R13\r
- BNE RegTest1Error\r
- CMP #14, R14\r
- BNE RegTest1Error\r
- CMP #15, R15\r
- BNE RegTest1Error\r
-\r
- ; All comparisons passed, start a new itteratio of this loop.\r
- BRA TestLoop1\r
-\r
-RegTest1Error:\r
- ; A compare failed, just loop here so the loop counter stops incrementing\r
- ; causing the check task to indicate the error.\r
- BRA RegTest1Error\r
-;/*-----------------------------------------------------------*/\r
-\r
-;/* This function is explained in the comments at the top of main.c. */\r
-_vRegTest2Implementation:\r
-\r
- ; Put a known value in each register.\r
- MOV.L #10, R1\r
- MOV.L #20, R2\r
- MOV.L #30, R3\r
- MOV.L #40, R4\r
- MOV.L #50, R5\r
- MOV.L #60, R6\r
- MOV.L #70, R7\r
- MOV.L #80, R8\r
- MOV.L #90, R9\r
- MOV.L #100, R10\r
- MOV.L #110, R11\r
- MOV.L #120, R12\r
- MOV.L #130, R13\r
- MOV.L #140, R14\r
- MOV.L #150, R15\r
-\r
- ; Loop, checking on each itteration that each register still contains the\r
- ; expected value.\r
-TestLoop2:\r
-\r
- ; Push the registers that are going to get clobbered.\r
- PUSHM R14-R15\r
-\r
- ; Increment the loop counter to show this task is still getting CPU time.\r
- MOV.L #_ulRegTest2LoopCounter, R14\r
- MOV.L [ R14 ], R15\r
- ADD #1, R15\r
- MOV.L R15, [ R14 ]\r
-\r
- ; Restore the clobbered registers.\r
- POPM R14-R15\r
-\r
- CMP #10, R1\r
- BNE RegTest2Error\r
- CMP #20, R2\r
- BNE RegTest2Error\r
- CMP #30, R3\r
- BNE RegTest2Error\r
- CMP #40, R4\r
- BNE RegTest2Error\r
- CMP #50, R5\r
- BNE RegTest2Error\r
- CMP #60, R6\r
- BNE RegTest2Error\r
- CMP #70, R7\r
- BNE RegTest2Error\r
- CMP #80, R8\r
- BNE RegTest2Error\r
- CMP #90, R9\r
- BNE RegTest2Error\r
- CMP #100, R10\r
- BNE RegTest2Error\r
- CMP #110, R11\r
- BNE RegTest2Error\r
- CMP #120, R12\r
- BNE RegTest2Error\r
- CMP #130, R13\r
- BNE RegTest2Error\r
- CMP #140, R14\r
- BNE RegTest2Error\r
- CMP #150, R15\r
- BNE RegTest2Error\r
-\r
- ; All comparisons passed, start a new itteratio of this loop.\r
- BRA TestLoop2\r
-\r
-RegTest2Error:\r
- ; A compare failed, just loop here so the loop counter stops incrementing\r
- ; - causing the check task to indicate the error.\r
- BRA RegTest2Error\r
- \r
- .END\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
- PUBLIC _vRegTest1Implementation\r
- PUBLIC _vRegTest2Implementation\r
-\r
- EXTERN _ulRegTest1CycleCount\r
- EXTERN _ulRegTest2CycleCount\r
-\r
- RSEG CODE:CODE(4)\r
-\r
-_vRegTest1Implementation:\r
-\r
- /* Set each register to a known value. */\r
- MOV.L #0x33333333, R15\r
- MVTACHI R15\r
- MOV.L #0x44444444, R15\r
- MVTACLO R15\r
- MOV.L #1, R1\r
- MOV.L #2, R2\r
- MOV.L #3, R3\r
- MOV.L #4, R4\r
- MOV.L #5, R5\r
- MOV.L #6, R6\r
- MOV.L #7, R7\r
- MOV.L #8, R8\r
- MOV.L #9, R9\r
- MOV.L #10, R10\r
- MOV.L #11, R11\r
- MOV.L #12, R12\r
- MOV.L #13, R13\r
- MOV.L #14, R14\r
- MOV.L #15, R15\r
-\r
- /* Loop, checking each iteration that each register still contains the\r
- expected value. */\r
- TestLoop1:\r
-\r
- /* Push the registers that are going to get clobbered. */\r
- PUSHM R14-R15\r
-\r
- /* Increment the loop counter to show this task is still getting CPU\r
- time. */\r
- MOV.L #_ulRegTest1CycleCount, R14\r
- MOV.L [ R14 ], R15\r
- ADD #1, R15\r
- MOV.L R15, [ R14 ]\r
-\r
- /* Yield to extend the text coverage. Set the bit in the ITU SWINTR\r
- register. */\r
- MOV.L #1, R14\r
- MOV.L #0872E0H, R15\r
- MOV.B R14, [R15]\r
- NOP\r
- NOP\r
-\r
- /* Check the accumulator value. */\r
- MVFACHI R15\r
- CMP #0x33333333, R15\r
- BNE RegTest2Error\r
- MVFACMI R15\r
- CMP #0x33334444, R15\r
- BNE RegTest2Error\r
-\r
- /* Restore the clobbered registers. */\r
- POPM R14-R15\r
-\r
- /* Now compare each register to ensure it still contains the value that\r
- was set before this loop was entered. */\r
- CMP #1, R1\r
- BNE RegTest1Error\r
- CMP #2, R2\r
- BNE RegTest1Error\r
- CMP #3, R3\r
- BNE RegTest1Error\r
- CMP #4, R4\r
- BNE RegTest1Error\r
- CMP #5, R5\r
- BNE RegTest1Error\r
- CMP #6, R6\r
- BNE RegTest1Error\r
- CMP #7, R7\r
- BNE RegTest1Error\r
- CMP #8, R8\r
- BNE RegTest1Error\r
- CMP #9, R9\r
- BNE RegTest1Error\r
- CMP #10, R10\r
- BNE RegTest1Error\r
- CMP #11, R11\r
- BNE RegTest1Error\r
- CMP #12, R12\r
- BNE RegTest1Error\r
- CMP #13, R13\r
- BNE RegTest1Error\r
- CMP #14, R14\r
- BNE RegTest1Error\r
- CMP #15, R15\r
- BNE RegTest1Error\r
-\r
- /* All comparisons passed, start a new iteration of this loop. */\r
- BRA TestLoop1\r
-\r
- /* A compare failed, just loop here so the loop counter stops\r
- incrementing causing the check timer to indicate the error. */\r
- RegTest1Error:\r
- BRA RegTest1Error\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-_vRegTest2Implementation:\r
-\r
- /* Set each register to a known value. */\r
- MOV.L #0x11111111, R15\r
- MVTACHI R15\r
- MOV.L #0x22222222, R15\r
- MVTACLO R15\r
- MOV.L #100, R1\r
- MOV.L #200, R2\r
- MOV.L #300, R3\r
- MOV.L #400, R4\r
- MOV.L #500, R5\r
- MOV.L #600, R6\r
- MOV.L #700, R7\r
- MOV.L #800, R8\r
- MOV.L #900, R9\r
- MOV.L #1000, R10\r
- MOV.L #1001, R11\r
- MOV.L #1002, R12\r
- MOV.L #1003, R13\r
- MOV.L #1004, R14\r
- MOV.L #1005, R15\r
-\r
- /* Loop, checking each iteration that each register still contains the\r
- expected value. */\r
- TestLoop2:\r
-\r
- /* Push the registers that are going to get clobbered. */\r
- PUSHM R14-R15\r
-\r
- /* Increment the loop counter to show this task is still getting CPU\r
- time. */\r
- MOV.L #_ulRegTest2CycleCount, R14\r
- MOV.L [ R14 ], R15\r
- ADD #1, R15\r
- MOV.L R15, [ R14 ]\r
-\r
- /* Check the accumulator value. */\r
- MVFACHI R15\r
- CMP #0x11111111, R15\r
- BNE RegTest2Error\r
- MVFACMI R15\r
- CMP #0x11112222, R15\r
- BNE RegTest2Error\r
-\r
- /* Restore the clobbered registers. */\r
- POPM R14-R15\r
-\r
- /* Now compare each register to ensure it still contains the value that\r
- was set before this loop was entered. */\r
- CMP #100, R1\r
- BNE RegTest2Error\r
- CMP #200, R2\r
- BNE RegTest2Error\r
- CMP #300, R3\r
- BNE RegTest2Error\r
- CMP #400, R4\r
- BNE RegTest2Error\r
- CMP #500, R5\r
- BNE RegTest2Error\r
- CMP #600, R6\r
- BNE RegTest2Error\r
- CMP #700, R7\r
- BNE RegTest2Error\r
- CMP #800, R8\r
- BNE RegTest2Error\r
- CMP #900, R9\r
- BNE RegTest2Error\r
- CMP #1000, R10\r
- BNE RegTest2Error\r
- CMP #1001, R11\r
- BNE RegTest2Error\r
- CMP #1002, R12\r
- BNE RegTest2Error\r
- CMP #1003, R13\r
- BNE RegTest2Error\r
- CMP #1004, R14\r
- BNE RegTest2Error\r
- CMP #1005, R15\r
- BNE RegTest2Error\r
-\r
- /* All comparisons passed, start a new iteration of this loop. */\r
- BRA TestLoop2\r
-\r
- /* A compare failed, just loop here so the loop counter stops\r
- incrementing causing the check timer to indicate the error. */\r
- RegTest2Error:\r
- BRA RegTest2Error\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
- END\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * NOTE 1: This project provides two demo applications. A simple blinky\r
- * style project, and a more comprehensive test and demo application. The\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to\r
- * select between the two. See the notes on using\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the\r
- * comprehensive version.\r
- *\r
- * NOTE 2: This file only contains the source code that is specific to the\r
- * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
- * required to configure the hardware, are defined in main.c.\r
- *\r
- ******************************************************************************\r
- *\r
- * main_full() creates all the demo application tasks and software timers, then\r
- * starts the scheduler. The web documentation provides more details of the\r
- * standard demo application tasks, which provide no particular functionality,\r
- * but do provide a good example of how to use the FreeRTOS API.\r
- *\r
- * In addition to the standard demo tasks, the following tasks and tests are\r
- * defined and/or created within this file:\r
- *\r
- * "Reg test" tasks - These fill both the core and floating point registers with\r
- * known values, then check that each register maintains its expected value for\r
- * the lifetime of the task. Each task uses a different set of values. The reg\r
- * test tasks execute with a very low priority, so get preempted very\r
- * frequently. A register containing an unexpected value is indicative of an\r
- * error in the context switching mechanism.\r
- *\r
- * "Check" task - The check task period is initially set to three seconds. The\r
- * task checks that all the standard demo tasks, and the register check tasks,\r
- * are not only still executing, but are executing without reporting any errors.\r
- * If the check task discovers that a task has either stalled, or reported an\r
- * error, then it changes its own execution period from the initial three\r
- * seconds, to just 200ms. The check task also toggles an LED each time it is\r
- * called. This provides a visual indication of the system status: If the LED\r
- * toggles every three seconds, then no issues have been discovered. If the LED\r
- * toggles every 200ms, then an issue has been discovered with at least one\r
- * task.\r
- */\r
-\r
-/* Standard includes. */\r
-#include <stdio.h>\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "timers.h"\r
-#include "semphr.h"\r
-\r
-/* Standard demo application includes. */\r
-#include "flop.h"\r
-#include "semtest.h"\r
-#include "dynamic.h"\r
-#include "BlockQ.h"\r
-#include "blocktim.h"\r
-#include "countsem.h"\r
-#include "GenQTest.h"\r
-#include "recmutex.h"\r
-#include "death.h"\r
-#include "partest.h"\r
-#include "comtest2.h"\r
-#include "serial.h"\r
-#include "TimerDemo.h"\r
-#include "QueueOverwrite.h"\r
-#include "IntQueue.h"\r
-#include "EventGroupsDemo.h"\r
-#include "TaskNotify.h"\r
-#include "IntSemTest.h"\r
-\r
-/* Renesas includes. */\r
-#include <rskrx113def.h>\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_userdefine.h"\r
-\r
-/* Priorities for the demo application tasks. */\r
-#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
-#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
-#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
-#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
-#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )\r
-#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
-#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
-\r
-/* The priority used by the UART command console task. */\r
-#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
-\r
-/* A block time of zero simply means "don't block". */\r
-#define mainDONT_BLOCK ( 0UL )\r
-\r
-/* The period after which the check timer will expire, in ms, provided no errors\r
-have been reported by any of the standard demo tasks. ms are converted to the\r
-equivalent in ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )\r
-\r
-/* The period at which the check timer will expire, in ms, if an error has been\r
-reported in one of the standard demo tasks. ms are converted to the equivalent\r
-in ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )\r
-\r
-/* Parameters that are passed into the register check tasks solely for the\r
-purpose of ensuring parameters are passed into tasks correctly. */\r
-#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL )\r
-#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL )\r
-\r
-/* The base period used by the timer test tasks. */\r
-#define mainTIMER_TEST_PERIOD ( 50 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Entry point for the comprehensive demo (as opposed to the simple blinky\r
- * demo).\r
- */\r
-void main_full( void );\r
-\r
-/*\r
- * The full demo includes some functionality called from the tick hook.\r
- */\r
-void vFullDemoTickHook( void );\r
-\r
- /*\r
- * The check task, as described at the top of this file.\r
- */\r
-static void prvCheckTask( void *pvParameters );\r
-\r
-/*\r
- * Register check tasks, and the tasks used to write over and check the contents\r
- * of the registers, as described at the top of this file. The nature of these\r
- * files necessitates that they are written in assembly, but the entry points\r
- * are kept in the C file for the convenience of checking the task parameter.\r
- */\r
-static void prvRegTest1Task( void *pvParameters );\r
-static void prvRegTest2Task( void *pvParameters );\r
-void vRegTest1Implementation( void );\r
-void vRegTest2Implementation( void );\r
-\r
-/*\r
- * A high priority task that does nothing other than execute at a pseudo random\r
- * time to ensure the other test tasks don't just execute in a repeating\r
- * pattern.\r
- */\r
-static void prvPseudoRandomiser( void *pvParameters );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The following two variables are used to communicate the status of the\r
-register check tasks to the check task. If the variables keep incrementing,\r
-then the register check tasks have not discovered any errors. If a variable\r
-stops incrementing, then an error has been found. */\r
-volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
-\r
-/* String for display in the web server. It is set to an error message if the\r
-check task detects an error. */\r
-const char *pcStatusMessage = "All tasks running without error";\r
-/*-----------------------------------------------------------*/\r
-\r
-void main_full( void )\r
-{\r
- /* Start all the other standard demo/test tasks. They have no particular\r
- functionality, but do demonstrate how to use the FreeRTOS API and test the\r
- kernel port. */\r
- vStartInterruptQueueTasks();\r
- vStartDynamicPriorityTasks();\r
- vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
- vCreateBlockTimeTasks();\r
- vStartCountingSemaphoreTasks();\r
- vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
- vStartRecursiveMutexTasks();\r
- vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
-//_RB_ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
- vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
- vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );\r
- vStartEventGroupTasks();\r
- vStartTaskNotifyTask();\r
- vStartInterruptSemaphoreTasks();\r
-\r
- /* Create the register check tasks, as described at the top of this file */\r
- xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
- xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
-\r
- /* Create the task that just adds a little random behaviour. */\r
- xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );\r
-\r
- /* Create the task that performs the 'check' functionality, as described at\r
- the top of this file. */\r
- xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
-\r
- /* The set of tasks created by the following function call have to be\r
- created last as they keep account of the number of tasks they expect to see\r
- running. */\r
- vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
-\r
- /* Start the scheduler. */\r
- vTaskStartScheduler();\r
-\r
- /* If all is well, the scheduler will now be running, and the following\r
- line will never be reached. If the following line does execute, then\r
- there was either insufficient FreeRTOS heap memory available for the idle\r
- and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
- User mode. See the memory management section on the FreeRTOS web site for\r
- more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
- mode from which main() is called is set in the C start up code and must be\r
- a privileged mode (not user mode). */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvCheckTask( void *pvParameters )\r
-{\r
-TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
-TickType_t xLastExecutionTime;\r
-static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
-unsigned long ulErrorFound = pdFALSE;\r
-\r
- /* Just to stop compiler warnings. */\r
- ( void ) pvParameters;\r
-\r
- /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
- works correctly. */\r
- xLastExecutionTime = xTaskGetTickCount();\r
-\r
- /* Cycle for ever, delaying then checking all the other tasks are still\r
- operating without error. The onboard LED is toggled on each iteration.\r
- If an error is detected then the delay period is decreased from\r
- mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
- effect of increasing the rate at which the onboard LED toggles, and in so\r
- doing gives visual feedback of the system status. */\r
- for( ;; )\r
- {\r
- /* Delay until it is time to execute again. */\r
- vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
-\r
- /* Check all the demo tasks (other than the flash tasks) to ensure\r
- that they are all still running, and that none have detected an error. */\r
- if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 0UL;\r
- }\r
-\r
-#ifdef _RB_\r
- if( xAreMathsTaskStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 1UL;\r
- }\r
-#endif\r
- if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 2UL;\r
- }\r
-\r
- if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 3UL;\r
- }\r
-\r
- if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 4UL;\r
- }\r
-\r
- if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 5UL;\r
- }\r
-\r
- if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 6UL;\r
- }\r
-\r
- if( xIsCreateTaskStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 7UL;\r
- }\r
-\r
- if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 8UL;\r
- }\r
-\r
- if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )\r
- {\r
- ulErrorFound |= 1UL << 9UL;\r
- }\r
-\r
- if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 10UL;\r
- }\r
-\r
- if( xIsQueueOverwriteTaskStillRunning() != pdPASS )\r
- {\r
- ulErrorFound |= 1UL << 11UL;\r
- }\r
-\r
- if( xAreEventGroupTasksStillRunning() != pdPASS )\r
- {\r
- ulErrorFound |= 1UL << 12UL;\r
- }\r
-\r
- if( xAreTaskNotificationTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 13UL;\r
- }\r
-\r
- if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 14UL;\r
- }\r
-\r
- /* Check that the register test 1 task is still running. */\r
- if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
- {\r
- ulErrorFound |= 1UL << 15UL;\r
- }\r
- ulLastRegTest1Value = ulRegTest1LoopCounter;\r
-\r
- /* Check that the register test 2 task is still running. */\r
- if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
- {\r
- ulErrorFound |= 1UL << 16UL;\r
- }\r
- ulLastRegTest2Value = ulRegTest2LoopCounter;\r
-\r
- /* Toggle the check LED to give an indication of the system status. If\r
- the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
- everything is ok. A faster toggle indicates an error. */\r
- LED0 = !LED0;\r
-\r
- if( ulErrorFound != pdFALSE )\r
- {\r
- /* An error has been detected in one of the tasks - flash the LED\r
- at a higher frequency to give visible feedback that something has\r
- gone wrong (it might just be that the loop back connector required\r
- by the comtest tasks has not been fitted). */\r
- xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
- pcStatusMessage = "Error found in at least one task.";\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvPseudoRandomiser( void *pvParameters )\r
-{\r
-const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS );\r
-volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;\r
-\r
- /* This task does nothing other than ensure there is a little bit of\r
- disruption in the scheduling pattern of the other tasks. Normally this is\r
- done by generating interrupts at pseudo random times. */\r
- for( ;; )\r
- {\r
- ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;\r
- ulValue = ( ulNextRand >> 16UL ) & 0xffUL;\r
-\r
- if( ulValue < ulMinDelay )\r
- {\r
- ulValue = ulMinDelay;\r
- }\r
-\r
- vTaskDelay( ulValue );\r
-\r
- while( ulValue > 0 )\r
- {\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
- __asm volatile( "NOP" );\r
-\r
- ulValue--;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vFullDemoTickHook( void )\r
-{\r
- /* The full demo includes a software timer demo/test that requires\r
- prodding periodically from the tick interrupt. */\r
- vTimerPeriodicISRTests();\r
-\r
- /* Call the periodic queue overwrite from ISR demo. */\r
- vQueueOverwritePeriodicISRDemo();\r
-\r
- /* Call the periodic event group from ISR demo. */\r
- vPeriodicEventGroupsProcessing();\r
-\r
- /* Use task notifications from an interrupt. */\r
- xNotifyTaskFromISR();\r
-\r
- /* Use mutexes from interrupts. */\r
- vInterruptSemaphorePeriodicTest();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This function is explained in the comments at the top of this file. */\r
-static void prvRegTest1Task( void *pvParameters )\r
-{\r
- if( pvParameters != mainREG_TEST_1_PARAMETER )\r
- {\r
- /* The parameter did not contain the expected value. */\r
- for( ;; )\r
- {\r
- /* Stop the tick interrupt so its obvious something has gone wrong. */\r
- taskDISABLE_INTERRUPTS();\r
- }\r
- }\r
-\r
- /* This is an inline asm function that never returns. */\r
- vRegTest1Implementation();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This function is explained in the comments at the top of this file. */\r
-static void prvRegTest2Task( void *pvParameters )\r
-{\r
- if( pvParameters != mainREG_TEST_2_PARAMETER )\r
- {\r
- /* The parameter did not contain the expected value. */\r
- for( ;; )\r
- {\r
- /* Stop the tick interrupt so its obvious something has gone wrong. */\r
- taskDISABLE_INTERRUPTS();\r
- }\r
- }\r
-\r
- /* This is an inline asm function that never returns. */\r
- vRegTest2Implementation();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-#ifndef PRIORITY_DEFINITIONS_H\r
-#define PRIORITY_DEFINITIONS_H\r
-\r
-#ifndef __IASMRX__\r
- #error This file is only intended to be included from the FreeRTOS IAR port layer assembly file.\r
-#endif\r
-\r
-/* The interrupt priority used by the kernel itself for the tick interrupt and\r
-the pended interrupt. This would normally be the lowest priority. */\r
-#define configKERNEL_INTERRUPT_PRIORITY 1\r
-\r
-/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
-Interrupts that use a priority above this will not be effected by anything the\r
-kernel is doing. */\r
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
-\r
-#endif /* PRIORITY_DEFINITIONS_H */\r
+++ /dev/null
-/***************************************************************/\r
-/* */\r
-/* PROJECT NAME : RTOSDemo */\r
-/* FILE : interrupt_handlers.c */\r
-/* DESCRIPTION : Interrupt Handler */\r
-/* CPU SERIES : RX100 */\r
-/* CPU TYPE : RX113 */\r
-/* */\r
-/* This file is generated by e2 studio. */\r
-/* */\r
-/***************************************************************/ \r
- \r
- \r
- \r
- \r
-/************************************************************************/\r
-/* File Version: V1.1A */\r
-/* History : 1.00 (2013-11-18) [Hardware Manual Revision : 0.40] */\r
-/* : 1.10 (2014-02-26) [Hardware Manual Revision : 0.50] */\r
-/* : 1.1A (2015-04-20) [Hardware Manual Revision : 1.02] */\r
-/* Date Generated: 25/05/2015 */\r
-/************************************************************************/\r
-\r
-#include "interrupt_handlers.h"\r
-\r
-// INT_Exception(Supervisor Instruction)\r
-void INT_Excep_SuperVisorInst(void){/* brk(){ } */}\r
-\r
-// INT_Exception(Undefined Instruction)\r
-void INT_Excep_UndefinedInst(void){/* brk(){ } */}\r
-\r
-// NMI\r
-void INT_NonMaskableInterrupt(void){/* brk(){ } */}\r
-\r
-// Dummy\r
-void INT_Dummy(void){/* brk(){ } */}\r
-\r
-// BRK\r
-void INT_Excep_BRK(void){/* wait();*/ }\r
-\r
-// BSC BUSERR\r
-void INT_Excep_BSC_BUSERR(void){ }\r
-\r
-// FCU FRDYI\r
-void INT_Excep_FCU_FRDYI(void){ }\r
-\r
-// ICU SWINT\r
-void INT_Excep_ICU_SWINT(void){ }\r
-\r
-// CMT0 CMI0\r
-void INT_Excep_CMT0_CMI0(void){ }\r
-\r
-// CMT1 CMI1\r
-void INT_Excep_CMT1_CMI1(void){ }\r
-\r
-// CMT2 CMI2\r
-void INT_Excep_CMT2_CMI2(void){ }\r
-\r
-// CMT3 CMI3\r
-void INT_Excep_CMT3_CMI3(void){ }\r
-\r
-// CAC FERRF\r
-void INT_Excep_CAC_FERRF(void){ }\r
-\r
-// CAC MENDF\r
-void INT_Excep_CAC_MENDF(void){ }\r
-\r
-// CAC OVFF\r
-void INT_Excep_CAC_OVFF(void){ }\r
-\r
-// USB0 D0FIFO0\r
-void INT_Excep_USB0_D0FIFO0(void){ }\r
-\r
-// USB0 D1FIFO0\r
-void INT_Excep_USB0_D1FIFO0(void){ }\r
-\r
-// USB0 USBI0\r
-void INT_Excep_USB0_USBI0(void){ }\r
-\r
-// RSPI0 SPEI0\r
-void INT_Excep_RSPI0_SPEI0(void){ }\r
-\r
-// RSPI0 SPRI0\r
-void INT_Excep_RSPI0_SPRI0(void){ }\r
-\r
-// RSPI0 SPTI0\r
-void INT_Excep_RSPI0_SPTI0(void){ }\r
-\r
-// RSPI0 SPII0\r
-void INT_Excep_RSPI0_SPII0(void){ }\r
-\r
-// DOC DOPCF\r
-void INT_Excep_DOC_DOPCF(void){ }\r
-\r
-// CMPB CMPB0\r
-void INT_Excep_CMPB_CMPB0(void){ }\r
-\r
-// CMPB CMPB1\r
-void INT_Excep_CMPB_CMPB1(void){ }\r
-\r
-// CTSU CTSUWR\r
-void INT_Excep_CTSU_CTSUWR(void){ }\r
-\r
-// CTSU CTSURD\r
-void INT_Excep_CTSU_CTSURD(void){ }\r
-\r
-// CTSU CTSUFN\r
-void INT_Excep_CTSU_CTSUFN(void){ }\r
-\r
-// RTC CUP\r
-void INT_Excep_RTC_CUP(void){ }\r
-\r
-// ICU IRQ0\r
-void INT_Excep_ICU_IRQ0(void){ }\r
-\r
-// ICU IRQ1\r
-void INT_Excep_ICU_IRQ1(void){ }\r
-\r
-// ICU IRQ2\r
-void INT_Excep_ICU_IRQ2(void){ }\r
-\r
-// ICU IRQ3\r
-void INT_Excep_ICU_IRQ3(void){ }\r
-\r
-// ICU IRQ4\r
-void INT_Excep_ICU_IRQ4(void){ }\r
-\r
-// ICU IRQ5\r
-void INT_Excep_ICU_IRQ5(void){ }\r
-\r
-// ICU IRQ6\r
-void INT_Excep_ICU_IRQ6(void){ }\r
-\r
-// ICU IRQ7\r
-void INT_Excep_ICU_IRQ7(void){ }\r
-\r
-// ELC ELSR8I\r
-void INT_Excep_ELC_ELSR8I(void){ }\r
-\r
-// LVD LVD1\r
-void INT_Excep_LVD_LVD1(void){ }\r
-\r
-// LVD LVD2\r
-void INT_Excep_LVD_LVD2(void){ }\r
-\r
-// USB0 USBR0\r
-void INT_Excep_USB0_USBR0(void){ }\r
-\r
-// RTC ALM\r
-void INT_Excep_RTC_ALM(void){ }\r
-\r
-// RTC PRD\r
-void INT_Excep_RTC_PRD(void){ }\r
-\r
-// S12AD S12ADI0\r
-void INT_Excep_S12AD_S12ADI0(void){ }\r
-\r
-// S12AD GBADI\r
-void INT_Excep_S12AD_GBADI(void){ }\r
-\r
-// ELC ELSR18I\r
-void INT_Excep_ELC_ELSR18I(void){ }\r
-\r
-// SSI0 SSIF0\r
-void INT_Excep_SSI0_SSIF0(void){ }\r
-\r
-// SSI0 SSIRXI0\r
-void INT_Excep_SSI0_SSIRXI0(void){ }\r
-\r
-// SSI0 SSITXI0\r
-void INT_Excep_SSI0_SSITXI0(void){ }\r
-\r
-// MTU0 TGIA0\r
-void INT_Excep_MTU0_TGIA0(void){ }\r
-\r
-// MTU0 TGIB0\r
-void INT_Excep_MTU0_TGIB0(void){ }\r
-\r
-// MTU0 TGIC0\r
-void INT_Excep_MTU0_TGIC0(void){ }\r
-\r
-// MTU0 TGID0\r
-void INT_Excep_MTU0_TGID0(void){ }\r
-\r
-// MTU0 TCIV0\r
-void INT_Excep_MTU0_TCIV0(void){ }\r
-\r
-// MTU0 TGIE0\r
-void INT_Excep_MTU0_TGIE0(void){ }\r
-\r
-// MTU0 TGIF0\r
-void INT_Excep_MTU0_TGIF0(void){ }\r
-\r
-// MTU1 TGIA1\r
-void INT_Excep_MTU1_TGIA1(void){ }\r
-\r
-// MTU1 TGIB1\r
-void INT_Excep_MTU1_TGIB1(void){ }\r
-\r
-// MTU1 TCIV1\r
-void INT_Excep_MTU1_TCIV1(void){ }\r
-\r
-// MTU1 TCIU1\r
-void INT_Excep_MTU1_TCIU1(void){ }\r
-\r
-// MTU2 TGIA2\r
-void INT_Excep_MTU2_TGIA2(void){ }\r
-\r
-// MTU2 TGIB2\r
-void INT_Excep_MTU2_TGIB2(void){ }\r
-\r
-// MTU2 TCIV2\r
-void INT_Excep_MTU2_TCIV2(void){ }\r
-\r
-// MTU2 TCIU2\r
-void INT_Excep_MTU2_TCIU2(void){ }\r
-\r
-// MTU3 TGIA3\r
-void INT_Excep_MTU3_TGIA3(void){ }\r
-\r
-// MTU3 TGIB3\r
-void INT_Excep_MTU3_TGIB3(void){ }\r
-\r
-// MTU3 TGIC3\r
-void INT_Excep_MTU3_TGIC3(void){ }\r
-\r
-// MTU3 TGID3\r
-void INT_Excep_MTU3_TGID3(void){ }\r
-\r
-// MTU3 TCIV3\r
-void INT_Excep_MTU3_TCIV3(void){ }\r
-\r
-// MTU4 TGIA4\r
-void INT_Excep_MTU4_TGIA4(void){ }\r
-\r
-// MTU4 TGIB4\r
-void INT_Excep_MTU4_TGIB4(void){ }\r
-\r
-// MTU4 TGIC4\r
-void INT_Excep_MTU4_TGIC4(void){ }\r
-\r
-// MTU4 TGID4\r
-void INT_Excep_MTU4_TGID4(void){ }\r
-\r
-// MTU4 TCIV4\r
-void INT_Excep_MTU4_TCIV4(void){ }\r
-\r
-// MTU5 TGIU5\r
-void INT_Excep_MTU5_TGIU5(void){ }\r
-\r
-// MTU5 TGIV5\r
-void INT_Excep_MTU5_TGIV5(void){ }\r
-\r
-// MTU5 TGIW5\r
-void INT_Excep_MTU5_TGIW5(void){ }\r
-\r
-// POE OEI1\r
-void INT_Excep_POE_OEI1(void){ }\r
-\r
-// POE OEI2\r
-void INT_Excep_POE_OEI2(void){ }\r
-\r
-// TMR0 CMIA0\r
-void INT_Excep_TMR0_CMIA0(void){ }\r
-\r
-// TMR0 CMIB0\r
-void INT_Excep_TMR0_CMIB0(void){ }\r
-\r
-// TMR0 OVI0\r
-void INT_Excep_TMR0_OVI0(void){ }\r
-\r
-// TMR1 CMIA1\r
-void INT_Excep_TMR1_CMIA1(void){ }\r
-\r
-// TMR1 CMIB1\r
-void INT_Excep_TMR1_CMIB1(void){ }\r
-\r
-// TMR1 OVI1\r
-void INT_Excep_TMR1_OVI1(void){ }\r
-\r
-// TMR2 CMIA2\r
-void INT_Excep_TMR2_CMIA2(void){ }\r
-\r
-// TMR2 CMIB2\r
-void INT_Excep_TMR2_CMIB2(void){ }\r
-\r
-// TMR2 OVI2\r
-void INT_Excep_TMR2_OVI2(void){ }\r
-\r
-// TMR3 CMIA3\r
-void INT_Excep_TMR3_CMIA3(void){ }\r
-\r
-// TMR3 CMIB3\r
-void INT_Excep_TMR3_CMIB3(void){ }\r
-\r
-// TMR3 OVI3\r
-void INT_Excep_TMR3_OVI3(void){ }\r
-\r
-// SCI2 ERI2\r
-void INT_Excep_SCI2_ERI2(void){ }\r
-\r
-// SCI2 RXI2\r
-void INT_Excep_SCI2_RXI2(void){ }\r
-\r
-// SCI2 TXI2\r
-void INT_Excep_SCI2_TXI2(void){ }\r
-\r
-// SCI2 TEI2\r
-void INT_Excep_SCI2_TEI2(void){ }\r
-\r
-// SCI0 ERI0\r
-void INT_Excep_SCI0_ERI0(void){ }\r
-\r
-// SCI0 RXI0\r
-void INT_Excep_SCI0_RXI0(void){ }\r
-\r
-// SCI0 TXI0\r
-void INT_Excep_SCI0_TXI0(void){ }\r
-\r
-// SCI0 TEI0\r
-void INT_Excep_SCI0_TEI0(void){ }\r
-\r
-// SCI1 ERI1\r
-void INT_Excep_SCI1_ERI1(void){ }\r
-\r
-// SCI1 RXI1\r
-void INT_Excep_SCI1_RXI1(void){ }\r
-\r
-// SCI1 TXI1\r
-void INT_Excep_SCI1_TXI1(void){ }\r
-\r
-// SCI1 TEI1\r
-void INT_Excep_SCI1_TEI1(void){ }\r
-\r
-// SCI5 ERI5\r
-void INT_Excep_SCI5_ERI5(void){ }\r
-\r
-// SCI5 RXI5\r
-void INT_Excep_SCI5_RXI5(void){ }\r
-\r
-// SCI5 TXI5\r
-void INT_Excep_SCI5_TXI5(void){ }\r
-\r
-// SCI5 TEI5\r
-void INT_Excep_SCI5_TEI5(void){ }\r
-\r
-// SCI6 ERI6\r
-void INT_Excep_SCI6_ERI6(void){ }\r
-\r
-// SCI6 RXI6\r
-void INT_Excep_SCI6_RXI6(void){ }\r
-\r
-// SCI6 TXI6\r
-void INT_Excep_SCI6_TXI6(void){ }\r
-\r
-// SCI6 TEI6\r
-void INT_Excep_SCI6_TEI6(void){ }\r
-\r
-// SCI8 ERI8\r
-void INT_Excep_SCI8_ERI8(void){ }\r
-\r
-// SCI8 RXI8\r
-void INT_Excep_SCI8_RXI8(void){ }\r
-\r
-// SCI8 TXI8\r
-void INT_Excep_SCI8_TXI8(void){ }\r
-\r
-// SCI8 TEI8\r
-void INT_Excep_SCI8_TEI8(void){ }\r
-\r
-// SCI9 ERI9\r
-void INT_Excep_SCI9_ERI9(void){ }\r
-\r
-// SCI9 RXI9\r
-void INT_Excep_SCI9_RXI9(void){ }\r
-\r
-// SCI9 TXI9\r
-void INT_Excep_SCI9_TXI9(void){ }\r
-\r
-// SCI9 TEI9\r
-void INT_Excep_SCI9_TEI9(void){ }\r
-\r
-// SCI12 ERI12\r
-void INT_Excep_SCI12_ERI12(void){ }\r
-\r
-// SCI12 RXI12\r
-void INT_Excep_SCI12_RXI12(void){ }\r
-\r
-// SCI12 TXI12\r
-void INT_Excep_SCI12_TXI12(void){ }\r
-\r
-// SCI12 TEI12\r
-void INT_Excep_SCI12_TEI12(void){ }\r
-\r
-// SCI12 SCIX0\r
-void INT_Excep_SCI12_SCIX0(void){ }\r
-\r
-// SCI12 SCIX1\r
-void INT_Excep_SCI12_SCIX1(void){ }\r
-\r
-// SCI12 SCIX2\r
-void INT_Excep_SCI12_SCIX2(void){ }\r
-\r
-// SCI12 SCIX3\r
-void INT_Excep_SCI12_SCIX3(void){ }\r
-\r
-// RIIC0 EEI0\r
-void INT_Excep_RIIC0_EEI0(void){ }\r
-\r
-// RIIC0 RXI0\r
-void INT_Excep_RIIC0_RXI0(void){ }\r
-\r
-// RIIC0 TXI0\r
-void INT_Excep_RIIC0_TXI0(void){ }\r
-\r
-// RIIC0 TEI0\r
-void INT_Excep_RIIC0_TEI0(void){ }\r
-\r
+++ /dev/null
-/***************************************************************/\r
-/* */\r
-/* PROJECT NAME : RTOSDemo */\r
-/* FILE : interrupt_handlers.h */\r
-/* DESCRIPTION : Interrupt Handler Declarations */\r
-/* CPU SERIES : RX100 */\r
-/* CPU TYPE : RX113 */\r
-/* */\r
-/* This file is generated by e2 studio. */\r
-/* */\r
-/***************************************************************/ \r
- \r
- \r
- \r
- \r
-/************************************************************************\r
-*\r
-* Device : RX/RX100/RX113\r
-*\r
-* File Name : vect.h\r
-*\r
-* Abstract : Definition of Vector.\r
-*\r
-* History : 1.00 (2013-11-18) [Hardware Manual Revision : 0.40]\r
-* : 1.10 (2014-02-26) [Hardware Manual Revision : 0.50]\r
-* : 1.1A (2015-04-20) [Hardware Manual Revision : 1.02]\r
-*\r
-* NOTE : THIS IS A TYPICAL EXAMPLE.\r
-*\r
-* Copyright (C) 2015 (2013 - 2014) Renesas Electronics Corporation.\r
-*\r
-********************************************************************+++*/\r
-/************************************************************************/\r
-/* File Version: V1.1A */\r
-/* History : 1.00 (2013-11-18) [Hardware Manual Revision : 0.40] */\r
-/* : 1.10 (2014-02-26) [Hardware Manual Revision : 0.50] */\r
-/* : 1.1A (2015-04-20) [Hardware Manual Revision : 1.02] */\r
-/* Date Generated: 25/05/2015 */\r
-/************************************************************************/\r
-\r
-#ifndef INTERRUPT_HANDLERS_H\r
-#define INTERRUPT_HANDLERS_H\r
-\r
-// INT_Exception(Supervisor Instruction)\r
-void INT_Excep_SuperVisorInst(void) __attribute__ ((interrupt));\r
-\r
-// INT_Exception(Undefined Instruction)\r
-void INT_Excep_UndefinedInst(void) __attribute__ ((interrupt));\r
-\r
-// NMI\r
-void INT_NonMaskableInterrupt(void) __attribute__ ((interrupt));\r
-\r
-// Dummy\r
-void INT_Dummy(void) __attribute__ ((interrupt));\r
-\r
-// BRK\r
-void INT_Excep_BRK(void) __attribute__ ((interrupt));\r
-\r
-// BSC BUSERR\r
-void INT_Excep_BSC_BUSERR(void) __attribute__ ((interrupt));\r
-\r
-// FCU FRDYI\r
-void INT_Excep_FCU_FRDYI(void) __attribute__ ((interrupt));\r
-\r
-// ICU SWINT\r
-void INT_Excep_ICU_SWINT(void) __attribute__ ((interrupt));\r
-\r
-// CMT0 CMI0\r
-void INT_Excep_CMT0_CMI0(void) __attribute__ ((interrupt));\r
-\r
-// CMT1 CMI1\r
-void INT_Excep_CMT1_CMI1(void) __attribute__ ((interrupt));\r
-\r
-// CMT2 CMI2\r
-void INT_Excep_CMT2_CMI2(void) __attribute__ ((interrupt));\r
-\r
-// CMT3 CMI3\r
-void INT_Excep_CMT3_CMI3(void) __attribute__ ((interrupt));\r
-\r
-// CAC FERRF\r
-void INT_Excep_CAC_FERRF(void) __attribute__ ((interrupt));\r
-\r
-// CAC MENDF\r
-void INT_Excep_CAC_MENDF(void) __attribute__ ((interrupt));\r
-\r
-// CAC OVFF\r
-void INT_Excep_CAC_OVFF(void) __attribute__ ((interrupt));\r
-\r
-// USB0 D0FIFO0\r
-void INT_Excep_USB0_D0FIFO0(void) __attribute__ ((interrupt));\r
-\r
-// USB0 D1FIFO0\r
-void INT_Excep_USB0_D1FIFO0(void) __attribute__ ((interrupt));\r
-\r
-// USB0 USBI0\r
-void INT_Excep_USB0_USBI0(void) __attribute__ ((interrupt));\r
-\r
-// RSPI0 SPEI0\r
-void INT_Excep_RSPI0_SPEI0(void) __attribute__ ((interrupt));\r
-\r
-// RSPI0 SPRI0\r
-void INT_Excep_RSPI0_SPRI0(void) __attribute__ ((interrupt));\r
-\r
-// RSPI0 SPTI0\r
-void INT_Excep_RSPI0_SPTI0(void) __attribute__ ((interrupt));\r
-\r
-// RSPI0 SPII0\r
-void INT_Excep_RSPI0_SPII0(void) __attribute__ ((interrupt));\r
-\r
-// DOC DOPCF\r
-void INT_Excep_DOC_DOPCF(void) __attribute__ ((interrupt));\r
-\r
-// CMPB CMPB0\r
-void INT_Excep_CMPB_CMPB0(void) __attribute__ ((interrupt));\r
-\r
-// CMPB CMPB1\r
-void INT_Excep_CMPB_CMPB1(void) __attribute__ ((interrupt));\r
-\r
-// CTSU CTSUWR\r
-void INT_Excep_CTSU_CTSUWR(void) __attribute__ ((interrupt));\r
-\r
-// CTSU CTSURD\r
-void INT_Excep_CTSU_CTSURD(void) __attribute__ ((interrupt));\r
-\r
-// CTSU CTSUFN\r
-void INT_Excep_CTSU_CTSUFN(void) __attribute__ ((interrupt));\r
-\r
-// RTC CUP\r
-void INT_Excep_RTC_CUP(void) __attribute__ ((interrupt));\r
-\r
-// ICU IRQ0\r
-void INT_Excep_ICU_IRQ0(void) __attribute__ ((interrupt));\r
-\r
-// ICU IRQ1\r
-void INT_Excep_ICU_IRQ1(void) __attribute__ ((interrupt));\r
-\r
-// ICU IRQ2\r
-void INT_Excep_ICU_IRQ2(void) __attribute__ ((interrupt));\r
-\r
-// ICU IRQ3\r
-void INT_Excep_ICU_IRQ3(void) __attribute__ ((interrupt));\r
-\r
-// ICU IRQ4\r
-void INT_Excep_ICU_IRQ4(void) __attribute__ ((interrupt));\r
-\r
-// ICU IRQ5\r
-void INT_Excep_ICU_IRQ5(void) __attribute__ ((interrupt));\r
-\r
-// ICU IRQ6\r
-void INT_Excep_ICU_IRQ6(void) __attribute__ ((interrupt));\r
-\r
-// ICU IRQ7\r
-void INT_Excep_ICU_IRQ7(void) __attribute__ ((interrupt));\r
-\r
-// ELC ELSR8I\r
-void INT_Excep_ELC_ELSR8I(void) __attribute__ ((interrupt));\r
-\r
-// LVD LVD1\r
-void INT_Excep_LVD_LVD1(void) __attribute__ ((interrupt));\r
-\r
-// LVD LVD2\r
-void INT_Excep_LVD_LVD2(void) __attribute__ ((interrupt));\r
-\r
-// USB0 USBR0\r
-void INT_Excep_USB0_USBR0(void) __attribute__ ((interrupt));\r
-\r
-// RTC ALM\r
-void INT_Excep_RTC_ALM(void) __attribute__ ((interrupt));\r
-\r
-// RTC PRD\r
-void INT_Excep_RTC_PRD(void) __attribute__ ((interrupt));\r
-\r
-// S12AD S12ADI0\r
-void INT_Excep_S12AD_S12ADI0(void) __attribute__ ((interrupt));\r
-\r
-// S12AD GBADI\r
-void INT_Excep_S12AD_GBADI(void) __attribute__ ((interrupt));\r
-\r
-// ELC ELSR18I\r
-void INT_Excep_ELC_ELSR18I(void) __attribute__ ((interrupt));\r
-\r
-// SSI0 SSIF0\r
-void INT_Excep_SSI0_SSIF0(void) __attribute__ ((interrupt));\r
-\r
-// SSI0 SSIRXI0\r
-void INT_Excep_SSI0_SSIRXI0(void) __attribute__ ((interrupt));\r
-\r
-// SSI0 SSITXI0\r
-void INT_Excep_SSI0_SSITXI0(void) __attribute__ ((interrupt));\r
-\r
-// MTU0 TGIA0\r
-void INT_Excep_MTU0_TGIA0(void) __attribute__ ((interrupt));\r
-\r
-// MTU0 TGIB0\r
-void INT_Excep_MTU0_TGIB0(void) __attribute__ ((interrupt));\r
-\r
-// MTU0 TGIC0\r
-void INT_Excep_MTU0_TGIC0(void) __attribute__ ((interrupt));\r
-\r
-// MTU0 TGID0\r
-void INT_Excep_MTU0_TGID0(void) __attribute__ ((interrupt));\r
-\r
-// MTU0 TCIV0\r
-void INT_Excep_MTU0_TCIV0(void) __attribute__ ((interrupt));\r
-\r
-// MTU0 TGIE0\r
-void INT_Excep_MTU0_TGIE0(void) __attribute__ ((interrupt));\r
-\r
-// MTU0 TGIF0\r
-void INT_Excep_MTU0_TGIF0(void) __attribute__ ((interrupt));\r
-\r
-// MTU1 TGIA1\r
-void INT_Excep_MTU1_TGIA1(void) __attribute__ ((interrupt));\r
-\r
-// MTU1 TGIB1\r
-void INT_Excep_MTU1_TGIB1(void) __attribute__ ((interrupt));\r
-\r
-// MTU1 TCIV1\r
-void INT_Excep_MTU1_TCIV1(void) __attribute__ ((interrupt));\r
-\r
-// MTU1 TCIU1\r
-void INT_Excep_MTU1_TCIU1(void) __attribute__ ((interrupt));\r
-\r
-// MTU2 TGIA2\r
-void INT_Excep_MTU2_TGIA2(void) __attribute__ ((interrupt));\r
-\r
-// MTU2 TGIB2\r
-void INT_Excep_MTU2_TGIB2(void) __attribute__ ((interrupt));\r
-\r
-// MTU2 TCIV2\r
-void INT_Excep_MTU2_TCIV2(void) __attribute__ ((interrupt));\r
-\r
-// MTU2 TCIU2\r
-void INT_Excep_MTU2_TCIU2(void) __attribute__ ((interrupt));\r
-\r
-// MTU3 TGIA3\r
-void INT_Excep_MTU3_TGIA3(void) __attribute__ ((interrupt));\r
-\r
-// MTU3 TGIB3\r
-void INT_Excep_MTU3_TGIB3(void) __attribute__ ((interrupt));\r
-\r
-// MTU3 TGIC3\r
-void INT_Excep_MTU3_TGIC3(void) __attribute__ ((interrupt));\r
-\r
-// MTU3 TGID3\r
-void INT_Excep_MTU3_TGID3(void) __attribute__ ((interrupt));\r
-\r
-// MTU3 TCIV3\r
-void INT_Excep_MTU3_TCIV3(void) __attribute__ ((interrupt));\r
-\r
-// MTU4 TGIA4\r
-void INT_Excep_MTU4_TGIA4(void) __attribute__ ((interrupt));\r
-\r
-// MTU4 TGIB4\r
-void INT_Excep_MTU4_TGIB4(void) __attribute__ ((interrupt));\r
-\r
-// MTU4 TGIC4\r
-void INT_Excep_MTU4_TGIC4(void) __attribute__ ((interrupt));\r
-\r
-// MTU4 TGID4\r
-void INT_Excep_MTU4_TGID4(void) __attribute__ ((interrupt));\r
-\r
-// MTU4 TCIV4\r
-void INT_Excep_MTU4_TCIV4(void) __attribute__ ((interrupt));\r
-\r
-// MTU5 TGIU5\r
-void INT_Excep_MTU5_TGIU5(void) __attribute__ ((interrupt));\r
-\r
-// MTU5 TGIV5\r
-void INT_Excep_MTU5_TGIV5(void) __attribute__ ((interrupt));\r
-\r
-// MTU5 TGIW5\r
-void INT_Excep_MTU5_TGIW5(void) __attribute__ ((interrupt));\r
-\r
-// POE OEI1\r
-void INT_Excep_POE_OEI1(void) __attribute__ ((interrupt));\r
-\r
-// POE OEI2\r
-void INT_Excep_POE_OEI2(void) __attribute__ ((interrupt));\r
-\r
-// TMR0 CMIA0\r
-void INT_Excep_TMR0_CMIA0(void) __attribute__ ((interrupt));\r
-\r
-// TMR0 CMIB0\r
-void INT_Excep_TMR0_CMIB0(void) __attribute__ ((interrupt));\r
-\r
-// TMR0 OVI0\r
-void INT_Excep_TMR0_OVI0(void) __attribute__ ((interrupt));\r
-\r
-// TMR1 CMIA1\r
-void INT_Excep_TMR1_CMIA1(void) __attribute__ ((interrupt));\r
-\r
-// TMR1 CMIB1\r
-void INT_Excep_TMR1_CMIB1(void) __attribute__ ((interrupt));\r
-\r
-// TMR1 OVI1\r
-void INT_Excep_TMR1_OVI1(void) __attribute__ ((interrupt));\r
-\r
-// TMR2 CMIA2\r
-void INT_Excep_TMR2_CMIA2(void) __attribute__ ((interrupt));\r
-\r
-// TMR2 CMIB2\r
-void INT_Excep_TMR2_CMIB2(void) __attribute__ ((interrupt));\r
-\r
-// TMR2 OVI2\r
-void INT_Excep_TMR2_OVI2(void) __attribute__ ((interrupt));\r
-\r
-// TMR3 CMIA3\r
-void INT_Excep_TMR3_CMIA3(void) __attribute__ ((interrupt));\r
-\r
-// TMR3 CMIB3\r
-void INT_Excep_TMR3_CMIB3(void) __attribute__ ((interrupt));\r
-\r
-// TMR3 OVI3\r
-void INT_Excep_TMR3_OVI3(void) __attribute__ ((interrupt));\r
-\r
-// SCI2 ERI2\r
-void INT_Excep_SCI2_ERI2(void) __attribute__ ((interrupt));\r
-\r
-// SCI2 RXI2\r
-void INT_Excep_SCI2_RXI2(void) __attribute__ ((interrupt));\r
-\r
-// SCI2 TXI2\r
-void INT_Excep_SCI2_TXI2(void) __attribute__ ((interrupt));\r
-\r
-// SCI2 TEI2\r
-void INT_Excep_SCI2_TEI2(void) __attribute__ ((interrupt));\r
-\r
-// SCI0 ERI0\r
-void INT_Excep_SCI0_ERI0(void) __attribute__ ((interrupt));\r
-\r
-// SCI0 RXI0\r
-void INT_Excep_SCI0_RXI0(void) __attribute__ ((interrupt));\r
-\r
-// SCI0 TXI0\r
-void INT_Excep_SCI0_TXI0(void) __attribute__ ((interrupt));\r
-\r
-// SCI0 TEI0\r
-void INT_Excep_SCI0_TEI0(void) __attribute__ ((interrupt));\r
-\r
-// SCI1 ERI1\r
-void INT_Excep_SCI1_ERI1(void) __attribute__ ((interrupt));\r
-\r
-// SCI1 RXI1\r
-void INT_Excep_SCI1_RXI1(void) __attribute__ ((interrupt));\r
-\r
-// SCI1 TXI1\r
-void INT_Excep_SCI1_TXI1(void) __attribute__ ((interrupt));\r
-\r
-// SCI1 TEI1\r
-void INT_Excep_SCI1_TEI1(void) __attribute__ ((interrupt));\r
-\r
-// SCI5 ERI5\r
-void INT_Excep_SCI5_ERI5(void) __attribute__ ((interrupt));\r
-\r
-// SCI5 RXI5\r
-void INT_Excep_SCI5_RXI5(void) __attribute__ ((interrupt));\r
-\r
-// SCI5 TXI5\r
-void INT_Excep_SCI5_TXI5(void) __attribute__ ((interrupt));\r
-\r
-// SCI5 TEI5\r
-void INT_Excep_SCI5_TEI5(void) __attribute__ ((interrupt));\r
-\r
-// SCI6 ERI6\r
-void INT_Excep_SCI6_ERI6(void) __attribute__ ((interrupt));\r
-\r
-// SCI6 RXI6\r
-void INT_Excep_SCI6_RXI6(void) __attribute__ ((interrupt));\r
-\r
-// SCI6 TXI6\r
-void INT_Excep_SCI6_TXI6(void) __attribute__ ((interrupt));\r
-\r
-// SCI6 TEI6\r
-void INT_Excep_SCI6_TEI6(void) __attribute__ ((interrupt));\r
-\r
-// SCI8 ERI8\r
-void INT_Excep_SCI8_ERI8(void) __attribute__ ((interrupt));\r
-\r
-// SCI8 RXI8\r
-void INT_Excep_SCI8_RXI8(void) __attribute__ ((interrupt));\r
-\r
-// SCI8 TXI8\r
-void INT_Excep_SCI8_TXI8(void) __attribute__ ((interrupt));\r
-\r
-// SCI8 TEI8\r
-void INT_Excep_SCI8_TEI8(void) __attribute__ ((interrupt));\r
-\r
-// SCI9 ERI9\r
-void INT_Excep_SCI9_ERI9(void) __attribute__ ((interrupt));\r
-\r
-// SCI9 RXI9\r
-void INT_Excep_SCI9_RXI9(void) __attribute__ ((interrupt));\r
-\r
-// SCI9 TXI9\r
-void INT_Excep_SCI9_TXI9(void) __attribute__ ((interrupt));\r
-\r
-// SCI9 TEI9\r
-void INT_Excep_SCI9_TEI9(void) __attribute__ ((interrupt));\r
-\r
-// SCI12 ERI12\r
-void INT_Excep_SCI12_ERI12(void) __attribute__ ((interrupt));\r
-\r
-// SCI12 RXI12\r
-void INT_Excep_SCI12_RXI12(void) __attribute__ ((interrupt));\r
-\r
-// SCI12 TXI12\r
-void INT_Excep_SCI12_TXI12(void) __attribute__ ((interrupt));\r
-\r
-// SCI12 TEI12\r
-void INT_Excep_SCI12_TEI12(void) __attribute__ ((interrupt));\r
-\r
-// SCI12 SCIX0\r
-void INT_Excep_SCI12_SCIX0(void) __attribute__ ((interrupt));\r
-\r
-// SCI12 SCIX1\r
-void INT_Excep_SCI12_SCIX1(void) __attribute__ ((interrupt));\r
-\r
-// SCI12 SCIX2\r
-void INT_Excep_SCI12_SCIX2(void) __attribute__ ((interrupt));\r
-\r
-// SCI12 SCIX3\r
-void INT_Excep_SCI12_SCIX3(void) __attribute__ ((interrupt));\r
-\r
-// RIIC0 EEI0\r
-void INT_Excep_RIIC0_EEI0(void) __attribute__ ((interrupt));\r
-\r
-// RIIC0 RXI0\r
-void INT_Excep_RIIC0_RXI0(void) __attribute__ ((interrupt));\r
-\r
-// RIIC0 TXI0\r
-void INT_Excep_RIIC0_TXI0(void) __attribute__ ((interrupt));\r
-\r
-// RIIC0 TEI0\r
-void INT_Excep_RIIC0_TEI0(void) __attribute__ ((interrupt));\r
-\r
-// ;<<VECTOR DATA START (POWER ON RESET)>>\r
-// ;Power On Reset PC\r
-extern void PowerON_Reset_PC(void) __attribute__ ((interrupt)); \r
-// ;<<VECTOR DATA END (POWER ON RESET)>>\r
-\r
-#endif\r
+++ /dev/null
-/*******************************************************************************\r
- * DISCLAIMER\r
- * This software is supplied by Renesas Electronics Corporation and is only\r
- * intended for use with Renesas products. No other uses are authorized. This\r
- * software is owned by Renesas Electronics Corporation and is protected under\r
- * all applicable laws, including copyright laws.\r
- * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
- * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
- * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
- * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
- * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
- * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
- * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
- * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
- * Renesas reserves the right, without notice, to make changes to this software\r
- * and to discontinue the availability of this software. By using this software,\r
- * you agree to the additional terms and conditions found by accessing the\r
- * following link:\r
- * http://www.renesas.com/disclaimer\r
- *******************************************************************************/\r
-/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */\r
-/*******************************************************************************\r
- * File Name : r_rsk_async.c\r
- * Version : 1.00\r
- * Device(s) : R5F51138AxFP\r
- * Tool-Chain : CCRX\r
- * H/W Platform : RSKRX113\r
- * Description : Functions used to send data via the SCI in asynchronous mode\r
- *******************************************************************************/\r
-/*******************************************************************************\r
- * History : 26.08.2014 Ver. 1.00 First Release\r
- *******************************************************************************/\r
-\r
-/*******************************************************************************\r
- System Includes\r
- *******************************************************************************/\r
-/* Following header file provides string type definitions. */\r
-#include <string.h>\r
-\r
-/*******************************************************************************\r
- User Includes (Project Level Includes)\r
- *******************************************************************************/\r
-/* Defines port registers */\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_sci.h"\r
-#include "r_rsk_async.h"\r
-\r
-/*******************************************************************************\r
- User Defines\r
- *******************************************************************************/\r
-\r
-/*******************************************************************************\r
- * Global Variables\r
- *******************************************************************************/\r
-\r
-/* Declaration of the command string to clear the terminal screen */\r
-static const char cmd_clr_scr[] =\r
-{ 27, 91, 50, 74, 0, 27, 91, 72, 0 };\r
-\r
-/*******************************************************************************\r
- * Function Prototypes\r
- *******************************************************************************/\r
-\r
-/* text_write function prototype */\r
-static void text_write (const char * const msg_string);\r
-\r
-/*******************************************************************************\r
- * Function Name: R_ASYNC_Init\r
- * Description : This function initialises the SCI channel connected to the\r
- * RS232 connector on the RSK. The channel is configured for\r
- * transmission and reception, and instructions are sent to the\r
- * terminal.\r
- * Argument : none\r
- * Return value : none\r
- *******************************************************************************/\r
-void R_ASYNC_Init (void)\r
-{\r
-\r
- /* Set up SCI1 receive buffer */\r
- R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
-\r
- /* Enable SCI1 operations */\r
- R_SCI1_Start();\r
-\r
- /* Clear the text on terminal window */\r
- text_write(cmd_clr_scr);\r
-\r
- /* Display splash screen on terminal window */\r
- text_write("Renesas RSKRX113 Async Serial \r\n");\r
-\r
- /* Inform user on how to stop transmission */\r
- text_write("Press 'z' to stop and any key to resume\r\n\n");\r
-}\r
-/*******************************************************************************\r
- * End of function R_ASYNC_Init\r
- *******************************************************************************/\r
-\r
-/*******************************************************************************\r
- * Function Name : text_write\r
- * Description : Transmits null-terminated string.\r
- * Argument : (char*) msg_string - null terminated string\r
- * Return value : None\r
- *******************************************************************************/\r
-static void text_write (const char * const msg_string)\r
-{\r
- R_SCI1_AsyncTransmit((uint8_t *) msg_string, (uint16_t) strlen(msg_string));\r
-}\r
-/*******************************************************************************\r
- * End of function text_write\r
- *******************************************************************************/\r
-\r
+++ /dev/null
-/*******************************************************************************\r
- * DISCLAIMER\r
- * This software is supplied by Renesas Electronics Corporation and is only\r
- * intended for use with Renesas products. No other uses are authorized. This\r
- * software is owned by Renesas Electronics Corporation and is protected under\r
- * all applicable laws, including copyright laws.\r
- * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
- * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
- * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
- * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
- * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
- * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
- * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
- * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
- * Renesas reserves the right, without notice, to make changes to this software\r
- * and to discontinue the availability of this software. By using this software,\r
- * you agree to the additional terms and conditions found by accessing the\r
- * following link:\r
- * http://www.renesas.com/disclaimer\r
- *******************************************************************************/\r
-/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */\r
-/*******************************************************************************\r
- * File Name : r_rsk_async.h\r
- * Version : 1.00\r
- * Device(s) : R5F51138AxFP\r
- * Tool-Chain : CCRX\r
- * H/W Platform : RSKRX113\r
- * Description : Functions used to send data via the SCI in asynchronous mode\r
- ******************************************************************************/\r
-/*******************************************************************************\r
- * History : 26.08.2014 Ver. 1.00 First Release\r
- *******************************************************************************/\r
-\r
-/*******************************************************************************\r
- * Macro Definitions\r
- *******************************************************************************/\r
-/* Multiple inclusion prevention macro */\r
-#ifndef R_RSK_ASYNC_H\r
-#define R_RSK_ASYNC_H\r
-\r
-/*******************************************************************************\r
- * Global Function Prototypes\r
- *******************************************************************************/\r
-/* initialise asynchronous transmission*/\r
-void R_ASYNC_Init (void);\r
-\r
-/* End of multiple inclusion prevention macro */\r
-#endif\r
-\r
+++ /dev/null
-/***************************************************************/\r
-/* */\r
-/* PROJECT NAME : RTOSDemo */\r
-/* FILE : reset_program.asm */\r
-/* DESCRIPTION : Reset Program */\r
-/* CPU SERIES : RX100 */\r
-/* CPU TYPE : RX113 */\r
-/* */\r
-/* This file is generated by e2 studio. */\r
-/* */\r
-/***************************************************************/ \r
- \r
- \r
-/************************************************************************/\r
-/* File Version: V1.01 */\r
-/* Date Generated: 04/03/2015 */\r
-/************************************************************************/\r
-\r
- /*reset_program.asm*/\r
-\r
- .list\r
- .section .text\r
- .global _PowerON_Reset /*global Start routine */\r
- \r
- .extern _HardwareSetup /*external Sub-routine to initialise Hardware*/\r
- .extern _data\r
- .extern _mdata\r
- .extern _ebss\r
- .extern _bss\r
- .extern _edata\r
- .extern _main \r
- .extern _ustack\r
- .extern _istack\r
- .extern _rvectors\r
- .extern _exit\r
-\r
-_PowerON_Reset :\r
-/* initialise user stack pointer */\r
- mvtc #_ustack,USP\r
-\r
-/* initialise interrupt stack pointer */\r
- mvtc #_istack,ISP\r
-\r
-#ifdef __RXv2__\r
-/* setup exception vector */\r
- mvtc #_ExceptVectors, extb /* EXCEPTION VECTOR ADDRESS */\r
-#endif\r
-\r
-/* setup intb */\r
- mvtc #_rvectors_start, intb /* INTERRUPT VECTOR ADDRESS definition */\r
-\r
-/* setup FPSW */\r
- mvtc #100h, fpsw \r
-\r
-/* load data section from ROM to RAM */\r
-\r
- mov #_mdata,r2 /* src ROM address of data section in R2 */\r
- mov #_data,r1 /* dest start RAM address of data section in R1 */\r
- mov #_edata,r3 /* end RAM address of data section in R3 */\r
- sub r1,r3 /* size of data section in R3 (R3=R3-R1) */\r
-#ifdef __RX_ALLOW_STRING_INSNS__\r
- smovf /* block copy R3 bytes from R2 to R1 */\r
-#else\r
- cmp #0, r3\r
- beq 2f\r
-\r
-1: mov.b [r2+], r5\r
- mov.b r5, [r1+]\r
- sub #1, r3\r
- bne 1b\r
-2:\r
-#endif\r
-\r
-\r
-/* bss initialisation : zero out bss */\r
-\r
- mov #00h,r2 /* load R2 reg with zero */\r
- mov #_ebss, r3 /* store the end address of bss in R3 */\r
- mov #_bss, r1 /* store the start address of bss in R1 */\r
- sub r1,r3 /* size of bss section in R3 (R3=R3-R1) */\r
- sstr.b\r
-/* call the hardware initialiser */\r
- mov #_HardwareSetup,r7\r
- jsr r7\r
- nop\r
-\r
-/* setup PSW */\r
- mvtc #10000h, psw /* Set Ubit & Ibit for PSW */\r
-\r
-/* change PSW PM to user-mode */\r
- MVFC PSW,R1\r
-//DO NOT SWITCH TO USER MODE OR #00100000h,R1\r
- PUSH.L R1\r
- MVFC PC,R1\r
- ADD #10,R1\r
- PUSH.L R1\r
- RTE\r
- NOP\r
- NOP\r
-#ifdef CPPAPP\r
- mov #__rx_init,r7\r
- jsr r7\r
-#endif \r
-/* start user program */\r
- mov #_main,r7\r
- jsr r7\r
- mov #_exit,r7\r
- jsr r7\r
-\r
-#ifdef CPPAPP\r
- .global _rx_run_preinit_array\r
- .type _rx_run_preinit_array,@function\r
-_rx_run_preinit_array:\r
- mov #__preinit_array_start,r1\r
- mov #__preinit_array_end,r2\r
- mov #_rx_run_inilist,r7\r
- jsr r7\r
-\r
- .global _rx_run_init_array\r
- .type _rx_run_init_array,@function\r
-_rx_run_init_array:\r
- mov #__init_array_start,r1\r
- mov #__init_array_end,r2\r
- mov #4, r3\r
- mov #_rx_run_inilist,r7\r
- jsr r7\r
-\r
- .global _rx_run_fini_array\r
- .type _rx_run_fini_array,@function\r
-_rx_run_fini_array:\r
- mov #__fini_array_start,r2\r
- mov #__fini_array_end,r1\r
- mov #-4, r3\r
- /* fall through */\r
-\r
-_rx_run_inilist:\r
-next_inilist:\r
- cmp r1,r2\r
- beq.b done_inilist\r
- mov.l [r1],r4\r
- cmp #-1, r4\r
- beq.b skip_inilist\r
- cmp #0, r4\r
- beq.b skip_inilist\r
- pushm r1-r3\r
- jsr r4\r
- popm r1-r3\r
-skip_inilist:\r
- add r3,r1\r
- mov #next_inilist,r7\r
- jsr r7\r
-done_inilist:\r
- rts\r
-\r
- .section .init,"ax"\r
- .balign 4\r
-\r
- .global __rx_init\r
-__rx_init:\r
-\r
- .section .fini,"ax"\r
- .balign 4\r
-\r
- .global __rx_fini\r
-__rx_fini:\r
- mov #_rx_run_fini_array,r7\r
- jsr r7\r
-\r
- .section .sdata\r
- .balign 4\r
- .global __gp\r
- .weak __gp\r
-__gp: \r
-\r
- .section .data\r
- .global ___dso_handle\r
- .weak ___dso_handle\r
-___dso_handle:\r
- .long 0\r
-\r
- .section .init,"ax"\r
- mov #_rx_run_preinit_array,r7\r
- jsr r7\r
- mov #_rx_run_init_array,r7\r
- jsr r7\r
- rts\r
- \r
- .global __rx_init_end\r
-__rx_init_end:\r
-\r
- .section .fini,"ax"\r
-\r
- rts\r
- .global __rx_fini_end\r
-__rx_fini_end:\r
-\r
-#endif\r
-\r
-/* call to exit*/\r
-_exit:\r
- bra _loop_here\r
-_loop_here:\r
- bra _loop_here\r
- \r
- .text \r
- .end\r
+++ /dev/null
-/***************************************************************/\r
-/* */\r
-/* PROJECT NAME : RTOSDemo */\r
-/* FILE : typedefine.h */\r
-/* DESCRIPTION : Aliases of Integer Type */\r
-/* CPU SERIES : RX100 */\r
-/* CPU TYPE : RX113 */\r
-/* */\r
-/* This file is generated by e2 studio. */\r
-/* */\r
-/***************************************************************/ \r
- \r
- \r
-/************************************************************************/\r
-/* File Version: V1.00 */\r
-/* Date Generated: 08/07/2013 */\r
-/************************************************************************/\r
-\r
-typedef signed char _SBYTE;\r
-typedef unsigned char _UBYTE;\r
-typedef signed short _SWORD;\r
-typedef unsigned short _UWORD;\r
-typedef signed int _SINT;\r
-typedef unsigned int _UINT;\r
-typedef signed long _SDWORD;\r
-typedef unsigned long _UDWORD;\r
-typedef signed long long _SQWORD;\r
-typedef unsigned long long _UQWORD;\r
+++ /dev/null
-/***************************************************************/\r
-/* */\r
-/* PROJECT NAME : RTOSDemo */\r
-/* FILE : vector_table.c */\r
-/* DESCRIPTION : Vector Table */\r
-/* CPU SERIES : RX100 */\r
-/* CPU TYPE : RX113 */\r
-/* */\r
-/* This file is generated by e2 studio. */\r
-/* */\r
-/***************************************************************/ \r
- \r
- \r
-/************************************************************************/\r
-/* File Version: V1.00 */\r
-/* Date Generated: 20/08/2014 */\r
-/************************************************************************/\r
-\r
-#include "interrupt_handlers.h"\r
-\r
-typedef void (*fp) (void);\r
-extern void PowerON_Reset (void);\r
-extern void stack (void);\r
-extern void vPortSoftwareInterruptISR( void );\r
-extern void vPortTickISR( void );\r
-extern void vIntQTimerISR0( void );\r
-extern void vIntQTimerISR1( void );\r
-\r
-#define FVECT_SECT __attribute__ ((section (".fvectors")))\r
-\r
-const void *HardwareVectors[] FVECT_SECT = {\r
-//;0xffffff80 MDES Endian Select Register\r
-#ifdef __RX_LITTLE_ENDIAN__ \r
-(fp)0xffffffff,\r
-#endif\r
-#ifdef __RX_BIG_ENDIAN__ \r
-(fp)0xfffffff8,\r
-#endif\r
-//;0xffffff84 Reserved\r
- (fp)0, \r
-//;0xffffff88 OFS1\r
- (fp)0xFFFFFFFF,\r
-//;0xffffff8C OFS0\r
- (fp)0xFFFFFFFF,\r
-//;0xffffff90 Reserved\r
- (fp)0, \r
-//;0xffffff94 Reserved\r
- (fp)0, \r
-//;0xffffff98 Reserved\r
- (fp)0, \r
-//;0xffffff9C Reserved\r
- (fp)0, \r
-//;0xffffffA0 Reserved\r
- (fp)0,\r
- //;0xffffffA4 Reserved\r
- (fp)0,\r
-//;0xffffffA8 Reserved\r
- (fp)0,\r
-//;0xffffffAC Reserved\r
- (fp)0,\r
-//;0xffffffB0 Reserved\r
- (fp)0,\r
-//;0xffffffB4 Reserved\r
- (fp)0,\r
-//;0xffffffB8 Reserved\r
- (fp)0,\r
-//;0xffffffBC Reserved\r
- (fp)0,\r
-//;0xffffffC0 Reserved\r
- (fp)0,\r
-//;0xffffffC4 Reserved\r
- (fp)0,\r
-//;0xffffffC8 Reserved\r
- (fp)0,\r
-//;0xffffffCC Reserved\r
- (fp)0,\r
-//;0xffffffd0 Exception(Supervisor Instruction)\r
- INT_Excep_SuperVisorInst,\r
-//;0xffffffd4 Reserved\r
- (fp)0,\r
-//;0xffffffd8 Reserved\r
- (fp)0,\r
-//;0xffffffdc Exception(Undefined Instruction)\r
- INT_Excep_UndefinedInst,\r
-//;0xffffffe0 Reserved\r
- (fp)0,\r
-//;0xffffffe4 Reserved\r
- (fp)0,\r
-//;0xffffffe8 Reserved\r
- (fp)0,\r
-//;0xffffffec Reserved\r
- (fp)0,\r
-//;0xfffffff0 Reserved\r
- (fp)0,\r
-//;0xfffffff4 Reserved\r
- (fp)0,\r
-//;0xfffffff8 NMI\r
- INT_NonMaskableInterrupt,\r
-//;0xfffffffc RESET\r
-//;<<VECTOR DATA START (POWER ON RESET)>>\r
-//;Power On Reset PC\r
- PowerON_Reset \r
-//;<<VECTOR DATA END (POWER ON RESET)>>\r
-};\r
-#define RVECT_SECT __attribute__ ((section (".rvectors")))\r
-\r
-const fp RelocatableVectors[] RVECT_SECT = {\r
-//;0x0000 BRK\r
- (fp)INT_Excep_BRK,\r
-//;0x0004 Reserved\r
- (fp)0,\r
-//;0x0008 Reserved\r
- (fp)0,\r
-//;0x000C Reserved\r
- (fp)0,\r
-//;0x0010 Reserved\r
- (fp)0,\r
-//;0x0014 Reserved\r
- (fp)0,\r
-//;0x0018 Reserved\r
- (fp)0,\r
-//;0x001C Reserved\r
- (fp)0,\r
-//;0x0020 Reserved\r
- (fp)0,\r
-//;0x0024 Reserved\r
- (fp)0,\r
-//;0x0028 Reserved\r
- (fp)0,\r
-//;0x002C Reserved\r
- (fp)0,\r
-//;0x0030 Reserved\r
- (fp)0,\r
-//;0x0034 Reserved\r
- (fp)0,\r
-//;0x0038 Reserved\r
- (fp)0,\r
-//;0x003C Reserved\r
- (fp)0,\r
-//;0x0040 BSC_BUSERR\r
- (fp)INT_Excep_BSC_BUSERR,\r
-//;0x0044 Reserved\r
- (fp)0,\r
-//;0x0048 Reserved\r
- (fp)0,\r
-//;0x004C Reserved\r
- (fp)0,\r
-//;0x0050 Reserved\r
- (fp)0,\r
-//;0x0054 FCUERR\r
- (fp)0,\r
-//;0x0058 Reserved\r
- (fp)0,\r
-//;0x005C FRDYI\r
- (fp)INT_Excep_FCU_FRDYI,\r
-//;0x0060 Reserved\r
- (fp)0,\r
-//;0x0064 Reserved\r
- (fp)0,\r
-//;0x0068 Reserved\r
- (fp)0,\r
-//;0x006C ICU_SWINT\r
- (fp)vPortSoftwareInterruptISR,\r
-//;0x0070 CMT0_CMI0\r
- (fp)vPortTickISR,\r
-//;0x0074 CMT1_CMI1\r
- (fp)INT_Excep_CMT1_CMI1,\r
-//;0x0078 CMT2_CMI2\r
- (fp)INT_Excep_CMT2_CMI2,\r
-//;0x007C CMT3_CMI3\r
- (fp)INT_Excep_CMT3_CMI3,\r
-//;0x0080 CAC_FERRF\r
- (fp)INT_Excep_CAC_FERRF,\r
-//;0x0084 CAC_MENDF\r
- (fp)INT_Excep_CAC_MENDF,\r
-//;0x0088 CAC_OVFF\r
- (fp)INT_Excep_CAC_OVFF,\r
-//;0x008C Reserved\r
- (fp)0,\r
-//;0x0090 USB0_D0FIFO0\r
- (fp)INT_Excep_USB0_D0FIFO0,\r
-//;0x0094 USB0_D1FIFO0\r
- (fp)INT_Excep_USB0_D1FIFO0,\r
-//;0x0098 USB0_USBI0\r
- (fp)INT_Excep_USB0_USBI0,\r
-//;0x009C Reserved\r
- (fp)0,\r
-//;0x00A0 Reserved\r
- (fp)0,\r
-//;0x00A4 Reserved\r
- (fp)0,\r
-//;0x00A8 Reserved\r
- (fp)0,\r
-//;0x00AC Reserved\r
- (fp)0,\r
-//;0x00B0 RSPI0_SPEI0\r
- (fp)INT_Excep_RSPI0_SPEI0,\r
-//;0x00B4 RSPI0_SPRI0\r
- (fp)INT_Excep_RSPI0_SPRI0,\r
-//;0x00B8 RSPI0_SPTI0\r
- (fp)INT_Excep_RSPI0_SPTI0,\r
-//;0x00BC RSPI0_SPII0\r
- (fp)INT_Excep_RSPI0_SPII0,\r
-//;0x00C0 Reserved\r
- (fp)0,\r
-//;0x00C4 Reserved\r
- (fp)0,\r
-//;0x00C8 Reserved\r
- (fp)0,\r
-//;0x00CC Reserved\r
- (fp)0,\r
-//;0x00D0 Reserved\r
- (fp)0,\r
-//;0x00D4 Reserved\r
- (fp)0,\r
-//;0x00D8 Reserved\r
- (fp)0,\r
-//;0x00DC Reserved\r
- (fp)0,\r
-//;0x00E0 Reserved\r
- (fp)0,\r
-//;0x00E4 DOC_DOPCF\r
- (fp)INT_Excep_DOC_DOPCF,\r
-//;0x00E8 CMPB_CMPB0\r
- (fp)INT_Excep_CMPB_CMPB0,\r
-//;0x00EC CMPB_CMPB1\r
- (fp)INT_Excep_CMPB_CMPB1,\r
-//;0x00F0 CTSU_CTSUWR\r
- (fp)INT_Excep_CTSU_CTSUWR,\r
-//;0x00F4 CTSU_CTSURD\r
- (fp)INT_Excep_CTSU_CTSURD,\r
-//;0x00F8 CTSU_CTSUFN\r
- (fp)INT_Excep_CTSU_CTSUFN,\r
-//;0x00FC Excep_RTC_CUP\r
- (fp)INT_Excep_RTC_CUP,\r
-//;0x0100 IRQ0\r
- (fp)INT_Excep_ICU_IRQ0,\r
-//;0x0104 IRQ1\r
- (fp)INT_Excep_ICU_IRQ1,\r
-//;0x0108 IRQ2\r
- (fp)INT_Excep_ICU_IRQ2,\r
-//;0x010C IRQ3\r
- (fp)INT_Excep_ICU_IRQ3,\r
-//;0x0110 IRQ4\r
- (fp)INT_Excep_ICU_IRQ4,\r
-//;0x0114 IRQ5\r
- (fp)INT_Excep_ICU_IRQ5,\r
-//;0x0118 IRQ6\r
- (fp)INT_Excep_ICU_IRQ6,\r
-//;0x011C IRQ7\r
- (fp)INT_Excep_ICU_IRQ7,\r
-//;0x0120 Reserved\r
- (fp)0,\r
-//;0x0124 Reserved\r
- (fp)0,\r
-//;0x0128 Reserved\r
- (fp)0,\r
-//;0x012C Reserved\r
- (fp)0,\r
-//;0x0130 Reserved\r
- (fp)0,\r
-//;0x0134 Reserved\r
- (fp)0,\r
-//;0x0138 Reserved\r
- (fp)0,\r
-//;0x013C Reserved\r
- (fp)0,\r
-//;0x0140 ELC ELSR8I\r
- (fp)INT_Excep_ELC_ELSR8I,\r
-//;0x0144 Reserved\r
- (fp)0,\r
-//;0x0148 Reserved\r
- (fp)0,\r
-//;0x014C Reserved\r
- (fp)0,\r
-//;0x0150 Reserved\r
- (fp)0,\r
-//;0x0154 Reserved\r
- (fp)0,\r
-//;0x0158 Reserved\r
- (fp)0,\r
-//;0x015C Reserved\r
- (fp)0,\r
-//;0x0160 LVD_LVD1\r
- (fp)INT_Excep_LVD_LVD1,\r
-//;0x0164 LVD_LVD2\r
- (fp)INT_Excep_LVD_LVD2,\r
-//;0x0168 USB0_USBR0\r
- (fp)INT_Excep_USB0_USBR0,\r
-//;0x016C Reserved\r
- (fp)0,\r
-//;0x0170 RTC_ALM\r
- (fp)INT_Excep_RTC_ALM,\r
-//;0x0174 RTC_PRD\r
- (fp)INT_Excep_RTC_PRD,\r
-//;0x0178 Reserved\r
- (fp)0,\r
-//;0x017C Reserved\r
- (fp)0,\r
-//;0x0180 Reserved\r
- (fp)0,\r
-//;0x0184 Reserved\r
- (fp)0,\r
-//;0x0188 Reserved\r
- (fp)0,\r
-//;0x018C Reserved\r
- (fp)0,\r
-//;0x0190 Reserved\r
- (fp)0,\r
-//;0x0194 Reserved\r
- (fp)0,\r
-//;0x0198 S12AD_S12ADI0 \r
- (fp)INT_Excep_S12AD_S12ADI0,\r
-//;0x019C S12AD_GBADI \r
- (fp)INT_Excep_S12AD_GBADI,\r
-//104;0x01A0 Reserved \r
- (fp)0,\r
-//105;0x01A4 Reserved \r
- (fp)0,\r
-//;0x01A8 ELC_ELSR18I\r
- (fp)INT_Excep_ELC_ELSR18I,\r
-//;0x01AC Reserved\r
- (fp)0,\r
-//;0x01B0 SSI0_SSIF0\r
- (fp)INT_Excep_SSI0_SSIF0,\r
-//;0x01B4 SSI0_SSIRXI0\r
- (fp)INT_Excep_SSI0_SSIRXI0,\r
-//;0x01B8 SSI0_SSITXI0\r
- (fp)INT_Excep_SSI0_SSITXI0,\r
-//;0x01BC Reserved\r
- (fp)0,\r
-//;0x01C0 Reserved\r
- (fp)0,\r
-//;0x01C4 Reserved\r
- (fp)0,\r
-//;0x01C8 MTU0_TGIA0 \r
- (fp)INT_Excep_MTU0_TGIA0,\r
-//;0x01CC MTU0_TGIB0 \r
- (fp)INT_Excep_MTU0_TGIB0,\r
-//;0x01D0 MTU0_TGIC0 \r
- (fp)INT_Excep_MTU0_TGIC0,\r
-//;0x01D4 MTU0_TGID0 \r
- (fp)INT_Excep_MTU0_TGID0,\r
-//;0x01D8 MTU0_TCIV0 \r
- (fp)INT_Excep_MTU0_TCIV0,\r
-//;0x01DC MTU0_TGIE0 \r
- (fp)INT_Excep_MTU0_TGIE0,\r
-//;0x01E0 MTU0_TGIF0 \r
- (fp)INT_Excep_MTU0_TGIF0, \r
-//;0x01E4 MTU1_TGIA1 \r
- (fp)INT_Excep_MTU1_TGIA1,\r
-//;0x01E8 MTU1_TGIB1 \r
- (fp)INT_Excep_MTU1_TGIB1,\r
-//;0x01EC MTU1_TCIV1 \r
- (fp)INT_Excep_MTU1_TCIV1,\r
-//;0x01F0 MTU1_TCIU1 \r
- (fp)INT_Excep_MTU1_TCIU1, \r
-//;0x01F4 MTU2_TGIA2 \r
- (fp)INT_Excep_MTU2_TGIA2,\r
-//;0x01F8 MTU2_TGIB2 \r
- (fp)INT_Excep_MTU2_TGIB2,\r
-//;0x01FC MTU2_TCIV2 \r
- (fp)INT_Excep_MTU2_TCIV2,\r
-//;0x0200 MTU2_TCIU2 \r
- (fp)INT_Excep_MTU2_TCIU2, \r
-//;0x0204 MTU3_TGIA3 \r
- (fp)INT_Excep_MTU3_TGIA3,\r
-//;0x0208 MTU3_TGIB3 \r
- (fp)INT_Excep_MTU3_TGIB3,\r
-//;0x020C MTU3_TGIC3 \r
- (fp)INT_Excep_MTU3_TGIC3,\r
-//;0x0210 MTU3_TGID3 \r
- (fp)INT_Excep_MTU3_TGID3,\r
-//;0x0214 MTU3_TCIV3 \r
- (fp)INT_Excep_MTU3_TCIV3, \r
-//;0x0218 MTU4_TGIA4 \r
- (fp)INT_Excep_MTU4_TGIA4,\r
-//;0x021C MTU4_TGIB4 \r
- (fp)INT_Excep_MTU4_TGIB4,\r
-//;0x0220 MTU4_TGIC4 \r
- (fp)INT_Excep_MTU4_TGIC4,\r
-//;0x0224 MTU4_TGID4 \r
- (fp)INT_Excep_MTU4_TGID4,\r
-//;0x0228 MTU4_TCIV4 \r
- (fp)INT_Excep_MTU4_TCIV4, \r
-//;0x022C MTU5_TGIU5 \r
- (fp)INT_Excep_MTU5_TGIU5,\r
-//;0x0230 MTU5_TGIV5 \r
- (fp)INT_Excep_MTU5_TGIV5,\r
-//;0x0234 MTU5_TGIW5 \r
- (fp)INT_Excep_MTU5_TGIW5,\r
-//;0x0238 Reserved\r
- (fp)0,\r
-//;0x023C Reserved\r
- (fp)0,\r
-//;0x0240 Reserved\r
- (fp)0,\r
-//;0x0244 Reserved\r
- (fp)0,\r
-//;0x0248 Reserved\r
- (fp)0,\r
-//;0x024C Reserved\r
- (fp)0,\r
-//;0x0250 Reserved\r
- (fp)0,\r
-//;0x0254 Reserved\r
- (fp)0,\r
-//;0x0258 Reserved\r
- (fp)0,\r
-//;0x025C Reserved\r
- (fp)0,\r
-//;0x0260 Reserved\r
- (fp)0,\r
-//;0x0264 Reserved\r
- (fp)0,\r
-//;0x0268 Reserved\r
- (fp)0,\r
-//;0x026C Reserved\r
- (fp)0,\r
-//;0x0270 Reserved\r
- (fp)0,\r
-//;0x0274 Reserved\r
- (fp)0,\r
-//;0x0278 Reserved\r
- (fp)0,\r
-//;0x027C Reserved\r
- (fp)0,\r
-//;0x0280 Reserved\r
- (fp)0,\r
-//;0x0284 Reserved\r
- (fp)0,\r
-//;0x0288 Reserved\r
- (fp)0,\r
-//;0x028C Reserved\r
- (fp)0,\r
-//;0x0290 Reserved\r
- (fp)0,\r
-//;0x0294 Reserved\r
- (fp)0,\r
-//;0x0298 Reserved\r
- (fp)0,\r
-//;0x029C Reserved\r
- (fp)0,\r
-//;0x02A0 Reserved\r
- (fp)0,\r
-//;0x02A4 Reserved\r
- (fp)0,\r
-//;0x02A8 POE_OEI1\r
- (fp)INT_Excep_POE_OEI1,\r
-//;0x02AC POE_OEI2\r
- (fp)INT_Excep_POE_OEI2,\r
-//;0x02B0 Reserved\r
- (fp)0,\r
-//;0x02B4 Reserved\r
- (fp)0,\r
-//;0x02B8 TMR0_CMIA0\r
- (fp)vIntQTimerISR0,\r
-//;0x02BC TMR0_CMIB0\r
- (fp)INT_Excep_TMR0_CMIB0,\r
-//;0x02C0 TMR0_OVI0\r
- (fp)INT_Excep_TMR0_OVI0,\r
-//;0x02C4 TMR1_CMIA1\r
- (fp)INT_Excep_TMR1_CMIA1,\r
-//;0x02C8 TMR1_CMIB1\r
- (fp)INT_Excep_TMR1_CMIB1,\r
-//;0x02CC TMR1_OVI1\r
- (fp)INT_Excep_TMR1_OVI1,\r
-//;0x02D0 TMR2_CMIA2\r
- (fp)vIntQTimerISR1,\r
-//;0x02D4 TMR2_CMIB2\r
- (fp)INT_Excep_TMR2_CMIB2,\r
-//;0x02D8 TMR2_OVI2\r
- (fp)INT_Excep_TMR2_OVI2,\r
-//;0x02DC TMR3_CMIA3\r
- (fp)INT_Excep_TMR3_CMIA3,\r
-//;0x02E0 TMR3_CMIB3\r
- (fp)INT_Excep_TMR3_CMIB3,\r
-//;0x02E4 TMR3_OVI3\r
- (fp)INT_Excep_TMR3_OVI3,\r
-//;0x02E8 SCI2_ERI2\r
- (fp)INT_Excep_SCI2_ERI2,\r
-//;0x02EC SCI2_RXI2\r
- (fp)INT_Excep_SCI2_RXI2,\r
-//;0x02F0 SCI2_TXI2\r
- (fp)INT_Excep_SCI2_TXI2,\r
-//;0x02F4 SCI2_TEI2\r
- (fp)INT_Excep_SCI2_TEI2,\r
-//;0x02F8 Reserved\r
- (fp)0,\r
-//;0x02FC Reserved\r
- (fp)0,\r
-//;0x0300 Reserved\r
- (fp)0,\r
-//;0x0304 Reserved\r
- (fp)0,\r
-//;0x0308 Reserved\r
- (fp)0,\r
-//;0x030C Reserved\r
- (fp)0,\r
-//;0x0310 Reserved\r
- (fp)0,\r
-//;0x0314 Reserved\r
- (fp)0,\r
-//;0x0318 Reserved\r
- (fp)0,\r
-//;0x031C Reserved\r
- (fp)0,\r
-//;0x0320 Reserved\r
- (fp)0,\r
-//;0x0324 Reserved\r
- (fp)0,\r
-//;0x0328 Reserved\r
- (fp)0,\r
-//;0x032C Reserved\r
- (fp)0,\r
-//;0x0330 Reserved\r
- (fp)0,\r
-//;0x0334 Reserved\r
- (fp)0,\r
-//;0x0338 Reserved\r
- (fp)0,\r
-//;0x033C Reserved\r
- (fp)0,\r
-//;0x0340 Reserved\r
- (fp)0,\r
-//;0x0344 Reserved\r
- (fp)0,\r
-//;0x0348 Reserved\r
- (fp)0,\r
-//;0x034C Reserved\r
- (fp)0,\r
-//;0x0350 Reserved\r
- (fp)0,\r
-//;0x0354 Reserved\r
- (fp)0,\r
-//;0x0358 SCI0_ERI0\r
- (fp)INT_Excep_SCI0_ERI0,\r
-//;0x035C SCI0_RXI0\r
- (fp)INT_Excep_SCI0_RXI0,\r
-//;0x0360 SCI0_TXI0\r
- (fp)INT_Excep_SCI0_TXI0,\r
-//;0x0364 SCI0_TEI0\r
- (fp)INT_Excep_SCI0_TEI0,\r
-//;0x0368 SCI1_ERI1\r
- (fp)INT_Excep_SCI1_ERI1,\r
-//;0x036C SCI1_RXI1\r
- (fp)INT_Excep_SCI1_RXI1,\r
-//;0x0370 SCI1_TXI1\r
- (fp)INT_Excep_SCI1_TXI1,\r
-//;0x0374 SCI1_TEI1\r
- (fp)INT_Excep_SCI1_TEI1,\r
-//;0x0378 SCI5_ERI5\r
- (fp)INT_Excep_SCI5_ERI5,\r
-//;0x037C SCI5_RXI5\r
- (fp)INT_Excep_SCI5_RXI5,\r
-//;0x0380 SCI5_TXI5\r
- (fp)INT_Excep_SCI5_TXI5,\r
-//;0x0384 SCI5_TEI5\r
- (fp)INT_Excep_SCI5_TEI5,\r
-//;0x0388 SCI6_ERI6\r
- (fp)INT_Excep_SCI6_ERI6,\r
-//;0x038C SCI6_RXI6\r
- (fp)INT_Excep_SCI6_RXI6,\r
-//;0x0390 SCI6_TXI6\r
- (fp)INT_Excep_SCI6_TXI6,\r
-//;0x0394 SCI6_TEI6\r
- (fp)INT_Excep_SCI6_TEI6,\r
-//;0x0398 SCI8_ERI8\r
- (fp)INT_Excep_SCI8_ERI8,\r
-//;0x039C SCI8_RXI8\r
- (fp)INT_Excep_SCI8_RXI8,\r
-//;0x03A0 SCI8_TXI8\r
- (fp)INT_Excep_SCI8_TXI8,\r
-//;0x03A4 SCI8_TEI8\r
- (fp)INT_Excep_SCI8_TEI8,\r
-//;0x03A8 SCI9_ERI9\r
- (fp)INT_Excep_SCI9_ERI9,\r
-//;0x03AC SCI9_RXI9\r
- (fp)INT_Excep_SCI9_RXI9,\r
-//;0x03B0 SCI9_TXI9\r
- (fp)INT_Excep_SCI9_TXI9,\r
-//;0x03B4 SCI9_TEI9\r
- (fp)INT_Excep_SCI9_TEI9,\r
-//;0x03B8 SCI12_ERI12\r
- (fp)INT_Excep_SCI12_ERI12,\r
-//;0x03BC SCI12_RXI12\r
- (fp)INT_Excep_SCI12_RXI12,\r
-//;0x03C0 SCI12_TXI12\r
- (fp)INT_Excep_SCI12_TXI12,\r
-//;0x03C4 SCI12_TEI12\r
- (fp)INT_Excep_SCI12_TEI12,\r
-//;0x03C8 SCI12_SCIX0\r
- (fp)INT_Excep_SCI12_SCIX0,\r
-//;0x03CC SCI12_SCIX1\r
- (fp)INT_Excep_SCI12_SCIX1,\r
-//;0x03D0 SCI12_SCIX2\r
- (fp)INT_Excep_SCI12_SCIX2,\r
-//;0x03D4 SCI12_SCIX3\r
- (fp)INT_Excep_SCI12_SCIX3,\r
-//;0x03D8 RIIC0_EEI0\r
- (fp)INT_Excep_RIIC0_EEI0,\r
-//;0x03DC RIIC0_RXI0\r
- (fp)INT_Excep_RIIC0_RXI0,\r
-//;0x03E0 RIIC0_TXI0\r
- (fp)INT_Excep_RIIC0_TXI0,\r
-//;0x03E4 RIIC0_TEI0\r
- (fp)INT_Excep_RIIC0_TEI0,\r
-//;0x03E8 Reserved\r
- (fp)0,\r
-//;0x03EC Reserved\r
- (fp)0,\r
-//;0x03F0 Reserved\r
- (fp)0,\r
-//;0x03F4 Reserved\r
- (fp)0,\r
-//;0x03F8 Reserved\r
- (fp)0,\r
-//;0x03FC Reserved\r
- (fp)0,\r
-};\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_cgc.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for CGC module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_cgc.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-* Function Name: R_CGC_Create\r
-* Description : This function initializes the clock generator.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_CGC_Create(void)\r
-{\r
- uint32_t sckcr_dummy;\r
- uint32_t w_count;\r
-\r
- /* Set main clock control registers */\r
- SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _20_CGC_MAINOSC_OVER10M;\r
- SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768;\r
-\r
- /* Set main clock operation */\r
- SYSTEM.MOSCCR.BIT.MOSTP = 0U;\r
-\r
- /* Wait for main clock oscillator wait counter overflow */\r
- while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF);\r
-\r
- /* Set system clock */\r
- sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000000_CGC_PCLKB_DIV_1 | _00000000_CGC_ICLK_DIV_1 | \r
- _00000000_CGC_FCLK_DIV_1;\r
- SYSTEM.SCKCR.LONG = sckcr_dummy;\r
-\r
- while (SYSTEM.SCKCR.LONG != sckcr_dummy);\r
-\r
- /* Set PLL circuit */\r
- SYSTEM.PLLCR.WORD = _0002_CGC_PLL_FREQ_DIV_4 | _0F00_CGC_PLL_FREQ_MUL_8;\r
- SYSTEM.PLLCR2.BIT.PLLEN = 0U;\r
-\r
- /* Wait for PLL wait counter overflow */\r
- while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF);\r
-\r
- /* Stop sub-clock */\r
- SYSTEM.SOSCCR.BIT.SOSTP = 1U;\r
-\r
- /* Wait for the register modification to complete */\r
- while (1U != SYSTEM.SOSCCR.BIT.SOSTP);\r
-\r
- /* Stop sub-clock */\r
- RTC.RCR3.BIT.RTCEN = 0U;\r
-\r
- /* Wait for the register modification to complete */\r
- while (0U != RTC.RCR3.BIT.RTCEN);\r
-\r
- /* Wait for 5 sub-clock cycles */\r
- for (w_count = 0U; w_count < _007B_CGC_SUBSTPWT_WAIT; w_count++)\r
- {\r
- __asm volatile( "NOP" );\r
- }\r
-\r
- /* Set sub-clock drive capacity */\r
- RTC.RCR3.BIT.RTCDV = 1U;\r
-\r
- /* Wait for the register modification to complete */\r
- while (1U != RTC.RCR3.BIT.RTCDV);\r
-\r
- /* Set sub-clock */\r
- SYSTEM.SOSCCR.BIT.SOSTP = 0U;\r
-\r
- /* Wait for the register modification to complete */\r
- while (0U != SYSTEM.SOSCCR.BIT.SOSTP);\r
-\r
- /* Wait for sub-clock to be stable */\r
- for (w_count = 0U; w_count < _00061A81_CGC_SUBOSCWT_WAIT; w_count++)\r
- {\r
- __asm volatile( "NOP" );\r
- }\r
-\r
- /* Set clock source */\r
- SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL;\r
-\r
- while (SYSTEM.SCKCR3.WORD != _0400_CGC_CLOCKSOURCE_PLL);\r
-\r
- /* Set LOCO */\r
- SYSTEM.LOCOCR.BIT.LCSTP = 1U;\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_cgc.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for CGC module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef CGC_H\r
-#define CGC_H\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-/*\r
- System Clock Control Register (SCKCR)\r
-*/\r
-/* Peripheral Module Clock D (PCLKD) */\r
-#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */\r
-#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */\r
-#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */\r
-#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */\r
-#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */\r
-#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */\r
-#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */\r
-/* Peripheral Module Clock B (PCLKB) */\r
-#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */\r
-#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */\r
-#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */\r
-#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */\r
-#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */\r
-#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */\r
-#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */\r
-/* System Clock (ICLK) */\r
-#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */\r
-#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */\r
-#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */\r
-#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */\r
-#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */\r
-#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */\r
-#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */\r
-/* System Clock (FCLK) */\r
-#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */\r
-#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */\r
-#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */\r
-#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */\r
-#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */\r
-#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */\r
-#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */\r
-\r
-/*\r
- System Clock Control Register 3 (SCKCR3)\r
-*/\r
-#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */\r
-#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */\r
-#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */\r
-#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */\r
-#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */\r
-\r
-/*\r
- PLL Control Register (PLLCR)\r
-*/\r
-/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */\r
-#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */\r
-#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */\r
-#define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */\r
-/* Frequency Multiplication Factor Select (STC[5:0]) */\r
-#define _0B00_CGC_PLL_FREQ_MUL_6 (0x0B00U) /* x6 */\r
-#define _0F00_CGC_PLL_FREQ_MUL_8 (0x0F00U) /* x8 */\r
-\r
-/*\r
- USB-dedicated PLL Control Register (UPLLCR)\r
-*/\r
-/* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */\r
-#define _0000_CGC_PLL_UPLIDIV_1 (0x0000U) /* x1 */\r
-#define _0001_CGC_PLL_UPLIDIV_2 (0x0001U) /* x1/2 */\r
-#define _0002_CGC_PLL_UPLIDIV_4 (0x0002U) /* x1/4 */\r
-/* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */\r
-#define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */\r
-#define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */\r
-/* Frequency Multiplication Factor Select (USTC[5:0]) */\r
-#define _0B00_CGC_PLL_USTC_6 (0x0B00U) /* x6 */\r
-#define _0F00_CGC_PLL_USTC_8 (0x0F00U) /* x8 */\r
-\r
-/*\r
- Oscillation Stop Detection Control Register (OSTDCR)\r
-*/\r
-/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */\r
-#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */\r
-#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */\r
-/* Oscillation Stop Detection Function Enable (OSTDE) */\r
-#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */\r
-#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */\r
-\r
-/*\r
- Main Clock Oscillator Wait Control Register (MOSCWTCR)\r
-*/\r
-/* Main Clock Oscillator Wait Time (MSTS[4:0]) */\r
-#define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */\r
-#define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */\r
-#define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */\r
-#define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */\r
-#define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */\r
-#define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */\r
-#define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */\r
-#define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */\r
-\r
-/*\r
- HOCO Wait Control Register (HOCOWTCR)\r
-*/\r
-/* HOCO Wait Time (HOCOWTCR) */\r
-#define _05_CGC_HOCO_WAIT_CYCLE_138 (0x05U) /* Wait time = 138 cycles (34.5us) */\r
-#define _06_CGC_HOCO_WAIT_CYCLE_266 (0x06U) /* Wait time = 266 cycles (66.5us) */\r
-\r
-/*\r
- Clock Output Control Register (CKOCR)\r
-*/\r
-/* Clock Output Source Select (CKOSEL[2:0]) */\r
-#define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */\r
-#define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */\r
-#define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */\r
-#define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */\r
-/* Clock Output Division Ratio Select (CKODIV[2:0]) */\r
-#define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */\r
-#define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */\r
-#define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */\r
-#define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */\r
-#define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */\r
-/* Clock Output Control (CKOSTP) */\r
-#define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */\r
-#define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */\r
-\r
-/*\r
- Main Clock Oscillator Forced Oscillation Control Register (MOFCR)\r
-*/\r
-/* Main Oscillator Drive Capability Switch (MODRV21) */\r
-#define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */\r
-#define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */\r
-/* Main Clock Oscillator Switch (MOSEL) */\r
-#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */\r
-#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */\r
-\r
-/*\r
- LCD Source Clock Control Register (LCDSCLKCR)\r
-*/\r
-/* LCD Source Clock Select (LCDSCLKSEL[2:0]) */\r
-#define _00_CGC_LCDSCLKSEL_LOCO (0x00U) /* LOCO */\r
-#define _01_CGC_LCDSCLKSEL_HOCO (0x01U) /* HOCO */\r
-#define _02_CGC_LCDSCLKSEL_MAINCLK (0x02U) /* Main clock oscillator */\r
-#define _03_CGC_LCDSCLKSEL_SUBCLK (0x03U) /* Sub-clock oscillator */\r
-#define _04_CGC_LCDSCLKSEL_IWDT (0x04U) /* IWDT-dedicated on-chip oscillator */\r
-\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-#define _007B_CGC_SUBSTPWT_WAIT (0x007BU) /* Wait time for 5 sub clock cycles */\r
-#define _00061A81_CGC_SUBOSCWT_WAIT (0x00061A81U) /* Wait time for sub clock stable */\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-void R_CGC_Create(void);\r
-\r
-/* Start user code for function. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_cgc_user.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for CGC module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_cgc.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_hardware_setup.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements system initializing function.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_cgc.h"\r
-#include "r_cg_port.h"\r
-#include "r_cg_sci.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-* Function Name: R_Systeminit\r
-* Description : This function initializes every macro.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_Systeminit(void)\r
-{\r
- /* Enable writing to registers related to operating modes, LPC, CGC and software reset */\r
- SYSTEM.PRCR.WORD = 0xA50FU; \r
-\r
- /* Enable writing to MPC pin function control registers */\r
- MPC.PWPR.BIT.B0WI = 0U; \r
- MPC.PWPR.BIT.PFSWE = 1U;\r
-\r
- /* Initialize non-existent pins */\r
- PORT0.PDR.BYTE = 0x6BU;\r
- PORT3.PDR.BYTE = 0xD8U;\r
- PORT4.PDR.BYTE = 0xA0U;\r
- PORT5.PDR.BYTE = 0x80U;\r
- PORT9.PDR.BYTE = 0xF8U;\r
- PORTD.PDR.BYTE = 0xE0U;\r
- PORTF.PDR.BYTE = 0x3FU;\r
- PORTJ.PDR.BYTE = 0x32U;\r
-\r
- /* Set peripheral settings */\r
- R_CGC_Create();\r
- R_PORT_Create();\r
- R_SCI1_Create();\r
-\r
- /* Disable writing to MPC pin function control registers */\r
- MPC.PWPR.BIT.PFSWE = 0U; \r
- MPC.PWPR.BIT.B0WI = 1U; \r
-\r
- /* Enable protection */\r
- SYSTEM.PRCR.WORD = 0xA500U; \r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: HardwareSetup\r
-* Description : This function initializes hardware setting.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void HardwareSetup(void)\r
-{\r
- R_Systeminit();\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws.\r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability\r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_macrodriver.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements general head file.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef MODULEID_H\r
-#define MODULEID_H\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "../iodefine.h"\r
-//_RB_#include <machine.h>\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-#ifndef __TYPEDEF__\r
-\r
-/* Status list definition */\r
-#define MD_STATUSBASE (0x00U)\r
-#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */\r
-#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */\r
-#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */\r
-#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */\r
-#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */\r
-\r
-/* Error list definition */\r
-#define MD_ERRORBASE (0x80U)\r
-#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */\r
-#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */\r
-#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */\r
-#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */\r
-#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */\r
-#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */\r
-#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */\r
-\r
-/* BRK handler command options */\r
-typedef enum {\r
- BRK_NO_COMMAND,\r
- BRK_ALL_MODULE_CLOCK_STOP,\r
- BRK_SLEEP,\r
- BRK_DEEP_SLEEP,\r
- BRK_STANDBY,\r
- BRK_LOAD_FINTV_REGISTER\r
-} brk_commands;\r
-#endif\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-#ifndef __TYPEDEF__\r
- #if !defined( _STD_USING_INT_TYPES ) && !defined( _STDINT )\r
- #define _SYS_INT_TYPES_H\r
- #ifndef _STD_USING_BIT_TYPES\r
- #ifndef __int8_t_defined\r
- #define __int8_t_defined\r
- #endif\r
- typedef signed char int8_t;\r
- typedef signed short int16_t;\r
- #endif\r
-\r
- typedef unsigned char uint8_t;\r
- typedef unsigned short uint16_t;\r
- typedef signed long int32_t;\r
- typedef unsigned long uint32_t;\r
-\r
- typedef signed char int_least8_t;\r
- typedef signed short int_least16_t;\r
- typedef signed long int_least32_t;\r
- typedef unsigned char uint_least8_t;\r
- typedef unsigned short uint_least16_t;\r
- typedef unsigned long uint_least32_t;\r
- #endif\r
-\r
- typedef unsigned short MD_STATUS;\r
- #define __TYPEDEF__\r
-#endif\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-void HardwareSetup(void);\r
-void R_Systeminit(void);\r
-\r
-#endif\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_port.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for Port module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_port.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-* Function Name: R_PORT_Create\r
-* Description : This function initializes the Port I/O.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_PORT_Create(void)\r
-{\r
- PORT2.PDR.BYTE = _04_Pm2_MODE_OUTPUT | _08_Pm3_MODE_OUTPUT | _10_Pm4_MODE_OUTPUT | _20_Pm5_MODE_OUTPUT | \r
- _00_Pm7_MODE_INPUT;\r
- PORT3.PDR.BYTE = _00_Pm2_MODE_INPUT | _D8_PDR3_DEFAULT;\r
- PORTJ.PDR.BYTE = _00_Pm0_MODE_INPUT | _32_PDRJ_DEFAULT;\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_port.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for Port module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef PORT_H\r
-#define PORT_H\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-/*\r
- Port Direction Register (PDR)\r
-*/\r
-/* Pmn Direction Control (B7 - B0) */\r
-#define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */\r
-#define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */\r
-#define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */\r
-#define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */\r
-#define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */\r
-#define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */\r
-#define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */\r
-#define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */\r
-#define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */\r
-#define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */\r
-#define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */\r
-#define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */\r
-#define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */\r
-#define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */\r
-#define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */\r
-#define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */\r
-#define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */\r
-#define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */\r
-#define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */\r
-#define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */\r
-#define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */\r
-#define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */\r
-#define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */\r
-#define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */\r
-\r
-/*\r
- Port Output Data Register (PODR)\r
-*/\r
-/* Pmn Output Data Store (B7 - B0) */\r
-#define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */\r
-#define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */\r
-#define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */\r
-#define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */\r
-#define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */\r
-#define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */\r
-#define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */\r
-#define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */\r
-#define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */\r
-#define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */\r
-#define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */\r
-#define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */\r
-#define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */\r
-#define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */\r
-#define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */\r
-#define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */\r
-\r
-/*\r
- Open Drain Control Register 0 (ODR0)\r
-*/\r
-/* Pmn Output Type Select (Pm0 to Pm3) */\r
-#define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
-#define _02_Pm0_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */\r
-#define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
-#define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */\r
-#define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
-#define _20_Pm2_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */\r
-#define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
-#define _80_Pm3_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */\r
-\r
-/*\r
- Open Drain Control Register 1 (ODR1)\r
-*/\r
-/* Pmn Output Type Select (Pm4 to Pm7) */\r
-#define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
-#define _02_Pm4_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */\r
-#define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
-#define _08_Pm5_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */\r
-#define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
-#define _20_Pm6_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */\r
-#define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
-#define _80_Pm7_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */\r
-\r
-/*\r
- Pull-Up Control Register (PCR)\r
-*/\r
-/* Pm0 Input Pull-Up Resistor Control ((B7 - B0)) */\r
-#define _00_Pm0_PULLUP_OFF (0x00U) /* Pn0 pull-up resistor not connected */\r
-#define _01_Pm0_PULLUP_ON (0x01U) /* Pn0 pull-up resistor connected */\r
-#define _00_Pm1_PULLUP_OFF (0x00U) /* Pn1 pull-up resistor not connected */\r
-#define _02_Pm1_PULLUP_ON (0x02U) /* Pn1 pull-up resistor connected */\r
-#define _00_Pm2_PULLUP_OFF (0x00U) /* Pn2 Pull-up resistor not connected */\r
-#define _04_Pm2_PULLUP_ON (0x04U) /* Pn2 pull-up resistor connected */\r
-#define _00_Pm3_PULLUP_OFF (0x00U) /* Pn3 pull-up resistor not connected */\r
-#define _08_Pm3_PULLUP_ON (0x08U) /* Pn3 pull-up resistor connected */\r
-#define _00_Pm4_PULLUP_OFF (0x00U) /* Pn4 pull-up resistor not connected */\r
-#define _10_Pm4_PULLUP_ON (0x10U) /* Pn4 pull-up resistor connected */\r
-#define _00_Pm5_PULLUP_OFF (0x00U) /* Pn5 pull-up resistor not connected */\r
-#define _20_Pm5_PULLUP_ON (0x20U) /* Pn5 pull-up resistor connected */\r
-#define _00_Pm6_PULLUP_OFF (0x00U) /* Pn6 pull-up resistor not connected */\r
-#define _40_Pm6_PULLUP_ON (0x40U) /* Pn6 pull-up resistor connected */\r
-#define _00_Pm7_PULLUP_OFF (0x00U) /* Pn7 pull-up resistor not connected */\r
-#define _80_Pm7_PULLUP_ON (0x80U) /* Pn7 pull-up resistor connected */\r
-\r
-/*\r
- Port Switching Register A (PSRA)\r
-*/\r
-/* PB6/PC0 Switching (PSEL6) */\r
-#define _00_PORT_PSEL6_PB6 (0x00U) /* PB6 general I/O port function is selected */\r
-#define _40_PORT_PSEL6_PC0 (0x40U) /* PC0 general I/O port function is selected */\r
-/* PB7/PC1 Switching (PSEL7) */\r
-#define _00_PORT_PSEL7_PB7 (0x00U) /* PB7 general I/O port function is selected */\r
-#define _80_PORT_PSEL7_PC1 (0x80U) /* PC1 general I/O port function is selected */\r
-\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-#define _6B_PDR0_DEFAULT (0x6BU) /* PDR0 default value */\r
-#define _D8_PDR3_DEFAULT (0xD8U) /* PDR3 default value */\r
-#define _A0_PDR4_DEFAULT (0xA0U) /* PDR4 default value */\r
-#define _80_PDR5_DEFAULT (0x80U) /* PDR5 default value */\r
-#define _F8_PDR9_DEFAULT (0xF8U) /* PDR9 default value */\r
-#define _E0_PDRD_DEFAULT (0xE0U) /* PDRD default value */\r
-#define _3F_PDRF_DEFAULT (0x3FU) /* PDRF default value */\r
-#define _32_PDRJ_DEFAULT (0x32U) /* PDRJ default value */\r
-\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-void R_PORT_Create(void);\r
-\r
-/* Start user code for function. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_port_user.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for Port module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_port.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_sbrk.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : Program of sbrk.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include <stddef.h>\r
-#include <stdio.h>\r
-#include "r_cg_sbrk.h"\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-\r
-int8_t *sbrk(size_t size);\r
-\r
-extern int8_t *_s1ptr;\r
-\r
-union HEAP_TYPE\r
-{\r
- int16_t dummy ; /* Dummy for 4-byte boundary */\r
- int8_t heap[HEAPSIZE]; /* Declaration of the area managed by sbrk */\r
-};\r
-\r
-static union HEAP_TYPE heap_area ;\r
-\r
-/* End address allocated by sbrk */\r
-static int8_t *brk = (int8_t *) &heap_area;\r
-\r
-/**************************************************************************/\r
-/* sbrk:Memory area allocation */\r
-/* Return value:Start address of allocated area (Pass) */\r
-/* -1 (Failure) */\r
-/**************************************************************************/\r
-int8_t *sbrk(size_t size) /* Assigned area size */\r
-{\r
- int8_t *p;\r
-\r
- if (brk+size > heap_area.heap + HEAPSIZE) /* Empty area size */\r
- {\r
- p = (int8_t *)-1;\r
- }\r
- else\r
- {\r
- p = brk; /* Area assignment */\r
- brk += size; /* End address update */\r
- }\r
-\r
- return p;\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_sbrk.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : Header file of sbrk file.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef _SBRK_H\r
-#define _SBRK_H\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-#define HEAPSIZE (0x400U) /* Size of area managed by sbrk */\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_sci.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for SCI module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_sci.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-uint8_t * gp_sci1_tx_address; /* SCI1 transmit buffer address */\r
-uint16_t g_sci1_tx_count; /* SCI1 transmit data number */\r
-uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */\r
-uint16_t g_sci1_rx_count; /* SCI1 receive data number */\r
-uint16_t g_sci1_rx_length; /* SCI1 receive data length */\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-* Function Name: R_SCI1_Create\r
-* Description : This function initializes the SCI1.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_SCI1_Create(void)\r
-{\r
- /* Cancel SCI1 module stop state */\r
- MSTP(SCI1) = 0U;\r
-\r
- /* Set interrupt priority */\r
- IPR(SCI1, ERI1) = _0F_SCI_PRIORITY_LEVEL15;\r
-\r
- /* Clear the SCR.TIE, RIE, TE, RE and TEIE bits */\r
- SCI1.SCR.BIT.TIE = 0U;\r
- SCI1.SCR.BIT.RIE = 0U;\r
- SCI1.SCR.BIT.TE = 0U;\r
- SCI1.SCR.BIT.RE = 0U;\r
- SCI1.SCR.BIT.TEIE = 0U;\r
-\r
- /* Set RXD1 pin */\r
- MPC.P15PFS.BYTE = 0x0AU;\r
- PORT1.PMR.BYTE |= 0x20U;\r
- /* Set TXD1 pin */\r
- MPC.P16PFS.BYTE = 0x0AU;\r
- PORT1.PODR.BYTE |= 0x40U;\r
- PORT1.PDR.BYTE |= 0x40U;\r
- PORT1.PMR.BYTE |= 0x40U;\r
-\r
- /* Set clock enable */\r
- SCI1.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED;\r
-\r
- /* Clear the SIMR1.IICM, SPMR.CKPH, and CKPOL bit */\r
- SCI1.SIMR1.BIT.IICM = 0U;\r
- SCI1.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED;\r
-\r
- /* Set control registers */\r
- SCI1.SMR.BYTE = _01_SCI_CLOCK_PCLK_4 | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | \r
- _00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE;\r
- SCI1.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | _72_SCI_SCMR_DEFAULT;\r
-\r
- /* Set SEMR, SNFR */\r
- SCI1.SEMR.BYTE = _00_SCI_LOW_LEVEL_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK;\r
-\r
- /* Set bitrate */\r
- SCI1.BRR = 0x19U;\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: R_SCI1_Start\r
-* Description : This function starts the SCI1.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_SCI1_Start(void)\r
-{\r
- IR(SCI1,TXI1) = 0U;\r
- IR(SCI1,TEI1) = 0U;\r
- IR(SCI1,RXI1) = 0U;\r
- IR(SCI1,ERI1) = 0U;\r
- IEN(SCI1,TXI1) = 1U;\r
- IEN(SCI1,TEI1) = 1U;\r
- IEN(SCI1,RXI1) = 1U;\r
- IEN(SCI1,ERI1) = 1U;\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: R_SCI1_Stop\r
-* Description : This function stops the SCI1.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_SCI1_Stop(void)\r
-{\r
- /* Set TXD1 pin */\r
- PORT1.PMR.BYTE &= 0xBFU;\r
-\r
- SCI1.SCR.BYTE &= 0xCF; /* Disable serial transmit and receive */\r
- SCI1.SCR.BIT.TIE = 0U; /* Disable TXI interrupt */\r
- SCI1.SCR.BIT.RIE = 0U; /* Disable RXI and ERI interrupt */\r
- IR(SCI1,TXI1) = 0U;\r
- IEN(SCI1,TXI1) = 0U;\r
- IR(SCI1,TEI1) = 0U;\r
- IEN(SCI1,TEI1) = 0U;\r
- IR(SCI1,RXI1) = 0U;\r
- IEN(SCI1,RXI1) = 0U;\r
- IR(SCI1,ERI1) = 0U;\r
- IEN(SCI1,ERI1) = 0U;\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: R_SCI1_Serial_Receive\r
-* Description : This function receives SCI1 data.\r
-* Arguments : rx_buf -\r
-* receive buffer pointer (Not used when receive data handled by DTC)\r
-* rx_num -\r
-* buffer size\r
-* Return Value : status -\r
-* MD_OK or MD_ARGERROR\r
-***********************************************************************************************************************/\r
-MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num)\r
-{\r
- MD_STATUS status = MD_OK;\r
-\r
- if (rx_num < 1U)\r
- {\r
- status = MD_ARGERROR;\r
- }\r
- else\r
- {\r
- g_sci1_rx_count = 0U;\r
- g_sci1_rx_length = rx_num;\r
- gp_sci1_rx_address = rx_buf;\r
- SCI1.SCR.BIT.RIE = 1U;\r
- SCI1.SCR.BIT.RE = 1U;\r
- }\r
-\r
- return (status);\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: R_SCI1_Serial_Send\r
-* Description : This function transmits SCI1 data.\r
-* Arguments : tx_buf -\r
-* transfer buffer pointer (Not used when transmit data handled by DTC)\r
-* tx_num -\r
-* buffer size\r
-* Return Value : status -\r
-* MD_OK or MD_ARGERROR\r
-***********************************************************************************************************************/\r
-MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num)\r
-{\r
- MD_STATUS status = MD_OK;\r
-\r
- if (tx_num < 1U)\r
- {\r
- status = MD_ARGERROR;\r
- }\r
- else\r
- {\r
- gp_sci1_tx_address = tx_buf;\r
- g_sci1_tx_count = tx_num;\r
- /* Set TXD1 pin */\r
- PORT1.PMR.BYTE |= 0x40U;\r
- SCI1.SCR.BIT.TIE = 1U;\r
- SCI1.SCR.BIT.TE = 1U;\r
- }\r
-\r
- return (status);\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_sci.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for SCI module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef SCI_H\r
-#define SCI_H\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-\r
-/*\r
- Serial mode register (SMR)\r
-*/\r
-/* Clock select (CKS) */\r
-#define _00_SCI_CLOCK_PCLK (0x00U) /* PCLK */\r
-#define _01_SCI_CLOCK_PCLK_4 (0x01U) /* PCLK/4 */\r
-#define _02_SCI_CLOCK_PCLK_16 (0x02U) /* PCLK/16 */\r
-#define _03_SCI_CLOCK_PCLK_64 (0x03U) /* PCLK/64 */\r
-/* Multi-processor Mode (MP) */\r
-#define _00_SCI_MULTI_PROCESSOR_DISABLE (0x00U) /* Disable multiprocessor mode */\r
-#define _04_SCI_MULTI_PROCESSOR_ENABLE (0x04U) /* Enable multiprocessor mode */\r
-/* Stop bit length (STOP) */\r
-#define _00_SCI_STOP_1 (0x00U) /* 1 stop bit length */\r
-#define _08_SCI_STOP_2 (0x08U) /* 2 stop bits length */\r
-/* Parity mode (PM) */\r
-#define _00_SCI_PARITY_EVEN (0x00U) /* Parity even */\r
-#define _10_SCI_PARITY_ODD (0x10U) /* Parity odd */\r
-/* Parity enable (PE) */\r
-#define _00_SCI_PARITY_DISABLE (0x00U) /* Parity disable */\r
-#define _20_SCI_PARITY_ENABLE (0x20U) /* Parity enable */\r
-/* Character length (CHR) */\r
-#define _00_SCI_DATA_LENGTH_8 (0x00U) /* Data length 8 bits */\r
-#define _40_SCI_DATA_LENGTH_7 (0x40U) /* Data length 7 bits */\r
-/* Communications mode (CM) */\r
-#define _00_SCI_ASYNCHRONOUS_MODE (0x00U) /* Asynchronous mode */\r
-#define _80_SCI_CLOCK_SYNCHRONOUS_MODE (0x80U) /* Clock synchronous mode */\r
-/* Base clock pulse (BCP) */\r
-#define _00_SCI_32_93_CLOCK_CYCLES (0x00U) /* 32 or 93 clock cycles */\r
-#define _04_SCI_64_128_CLOCK_CYCLES (0x04U) /* 64 or 128 clock cycles */\r
-#define _08_SCI_186_372_CLOCK_CYCLES (0x08U) /* 186 or 372 clock cycles */\r
-#define _0C_SCI_256_512_CLOCK_CYCLES (0x0CU) /* 256 or 512 clock cycles */\r
-/* Block transfer mode (BLK) */\r
-#define _00_SCI_BLK_TRANSFER_DISABLE (0x00U) /* Block transfer disable */\r
-#define _40_SCI_BLK_TRANSFER_ENABLE (0x40U) /* Block transfer enable */\r
-/* GSM mode (GSM) */\r
-#define _00_SCI_GSM_DISABLE (0x00U) /* Normal mode operation */\r
-#define _80_SCI_GSM_ENABLE (0x80U) /* GSM mode operation */\r
-\r
-/*\r
- Serial control register (SCR)\r
-*/\r
-/* Clock enable (CKE) */\r
-#define _00_SCI_INTERNAL_SCK_UNUSED (0x00U) /* Internal clock selected, SCK pin unused */\r
-#define _01_SCI_INTERNAL_SCK_OUTPUT (0x01U) /* Internal clock selected, SCK pin as clock output */\r
-#define _02_SCI_EXTERNAL (0x02U) /* External clock selected */\r
-#define _03_SCI_EXTERNAL (0x03U) /* External clock selected */\r
-/* Transmit end interrupt enable (TEIE) */\r
-#define _00_SCI_TEI_INTERRUPT_DISABLE (0x00U) /* TEI interrupt request disable */\r
-#define _04_SCI_TEI_INTERRUPT_ENABLE (0x04U) /* TEI interrupt request enable */\r
-/* Multi-processor interrupt enable (MPIE) */\r
-#define _00_SCI_MP_INTERRUPT_NORMAL (0x00U) /* Normal reception */\r
-#define _08_SCI_MP_INTERRUPT_SPECIAL (0x08U) /* Multi-processor ID reception */\r
-/* Receive enable (RE) */\r
-#define _00_SCI_RECEIVE_DISABLE (0x00U) /* Disable receive mode */\r
-#define _10_SCI_RECEIVE_ENABLE (0x10U) /* Enable receive mode */\r
-/* Transmit enable (TE) */\r
-#define _00_SCI_TRANSMIT_DISABLE (0x00U) /* Disable transmit mode */\r
-#define _20_SCI_TRANSMIT_ENABLE (0x20U) /* Enable transmit mode */\r
-/* Receive interrupt enable (RIE) */\r
-#define _00_SCI_RXI_ERI_DISABLE (0x00U) /* Disable RXI and ERI interrupt requests */\r
-#define _40_SCI_RXI_ERI_ENABLE (0x40U) /* Enable RXI and ERI interrupt requests */\r
-/* Transmit interrupt enable (TIE) */\r
-#define _00_SCI_TXI_DISABLE (0x00U) /* Disable TXI interrupt requests */\r
-#define _80_SCI_TXI_ENABLE (0x80U) /* Enable TXI interrupt requests */\r
-\r
-/*\r
- Serial status register (SSR)\r
-*/\r
-/* Multi-Processor bit transfer (MPBT) */\r
-#define _00_SCI_SET_DATA_TRANSFER (0x00U) /* Set data transmission cycles */\r
-#define _01_SCI_SET_ID_TRANSFER (0x01U) /* Set ID transmission cycles */\r
-/* Multi-Processor (MPB) */\r
-#define _00_SCI_DATA_TRANSFER (0x00U) /* In data transmission cycles */\r
-#define _02_SCI_ID_TRANSFER (0x02U) /* In ID transmission cycles */\r
-/* Transmit end flag (TEND) */\r
-#define _00_SCI_TRANSMITTING (0x00U) /* A character is being transmitted */\r
-#define _04_SCI_TRANSMIT_COMPLETE (0x04U) /* Character transfer has been completed */\r
-/* Parity error flag (PER) */\r
-#define _08_SCI_PARITY_ERROR (0x08U) /* A parity error has occurred */\r
-/* Framing error flag (FER) */\r
-#define _10_SCI_FRAME_ERROR (0x10U) /* A framing error has occurred */\r
-/* Overrun error flag (ORER) */\r
-#define _20_SCI_OVERRUN_ERROR (0x20U) /* An overrun error has occurred */\r
-\r
-/*\r
- Smart card mode register (SCMR)\r
-*/\r
-/* Smart card interface mode select (SMIF) */\r
-#define _00_SCI_SERIAL_MODE (0x00U) /* Serial communications interface mode */\r
-#define _01_SCI_SMART_CARD_MODE (0x01U) /* Smart card interface mode */\r
-/* Transmitted / received data invert (SINV) */\r
-#define _00_SCI_DATA_INVERT_NONE (0x00U) /* Data is not inverted */\r
-#define _04_SCI_DATA_INVERTED (0x04U) /* Data is inverted */\r
-/* Transmitted / received data transfer direction (SDIR) */\r
-#define _00_SCI_DATA_LSB_FIRST (0x00U) /* Transfer data LSB first */\r
-#define _08_SCI_DATA_MSB_FIRST (0x08U) /* Transfer data MSB first */\r
-/* Base clock pulse 2 (BCP2) */\r
-#define _00_SCI_93_128_186_512_CLK (0x00U) /* 93, 128, 186, or 512 clock cycles */\r
-#define _80_SCI_32_64_256_372_CLK (0x80U) /* 32, 64, 256, or 372 clock cycles */\r
-#define _72_SCI_SCMR_DEFAULT (0x72U) /* Write default value of SCMR */\r
-\r
-/* \r
- Serial extended mode register (SEMR)\r
-*/\r
-/* Asynchronous Mode Clock Source Select (ACS0) */\r
-#define _00_SCI_ASYNC_SOURCE_EXTERNAL (0x00U) /* External clock input */\r
-#define _01_SCI_ASYNC_SOURCE_TMR (0x01U) /* Logical AND of two clock cycles output from TMR */\r
-/* Asynchronous mode base clock select (ABCS) */\r
-#define _00_SCI_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */\r
-#define _10_SCI_8_BASE_CLOCK (0x10U) /* Selects 8 base clock cycles for 1 bit period */ \r
-/* Digital noise filter function enable (NFEN) */\r
-#define _00_SCI_NOISE_FILTER_DISABLE (0x00U) /* Noise filter is disabled */\r
-#define _20_SCI_NOISE_FILTER_ENABLE (0x20U) /* Noise filter is enabled */\r
-/* Asynchronous start bit edge detections select (RXDESEL) */\r
-#define _00_SCI_LOW_LEVEL_START_BIT (0x00U) /* Low level on RXDn pin selected as start bit */\r
-#define _80_SCI_FALLING_EDGE_START_BIT (0x80U) /* Falling edge on RXDn pin selected as start bit */\r
-\r
-/*\r
- Noise filter setting register (SNFR)\r
-*/\r
-/* Noise filter clock select (NFCS) */\r
-#define _00_SCI_ASYNC_DIV_1 (0x00U) /* Clock signal divided by 1 is used with the noise filter */\r
-#define _01_SCI_IIC_DIV_1 (0x01U) /* Clock signal divided by 1 is used with the noise filter */\r
-#define _02_SCI_IIC_DIV_2 (0x02U) /* Clock signal divided by 2 is used with the noise filter */\r
-#define _03_SCI_IIC_DIV_4 (0x03U) /* Clock signal divided by 4 is used with the noise filter */\r
-#define _04_SCI_IIC_DIV_8 (0x04U) /* Clock signal divided by 8 is used with the noise filter */\r
-\r
-/*\r
- I2C mode register 1 (SIMR1)\r
-*/\r
-/* Simple IIC mode select (IICM) */\r
-#define _00_SCI_SERIAL_SMART_CARD_MODE (0x00U) /* Serial or smart card mode */\r
-#define _01_SCI_IIC_MODE (0x01U) /* Simple IIC mode */\r
-\r
-/*\r
- I2C mode register 2 (SIMR2)\r
-*/\r
-/* IIC interrupt mode select (IICINTM) */\r
-#define _00_SCI_ACK_NACK_INTERRUPTS (0x00U) /* Use ACK/NACK interrupts */\r
-#define _01_SCI_RX_TX_INTERRUPTS (0x01U) /* Use reception/transmission interrupts */\r
-/* Clock synchronization (IICCSC) */\r
-#define _00_SCI_NO_SYNCHRONIZATION (0x00U) /* No synchronization with the clock signal */\r
-#define _02_SCI_SYNCHRONIZATION (0x02U) /* Synchronization with the clock signal */\r
-/* ACK transmission data (IICACKT) */\r
-#define _00_SCI_ACK_TRANSMISSION (0x00U) /* ACK transmission */\r
-#define _20_SCI_NACK_TRANSMISSION (0x20U) /* NACK transmission and reception of ACK/NACK */\r
-\r
-/*\r
- I2C mode register 3 (SIMR3)\r
-*/\r
-/* Start condition generation (IICSTAREQ) */\r
-#define _00_SCI_START_CONDITION_OFF (0x00U) /* Start condition is not generated */\r
-#define _01_SCI_START_CONDITION_ON (0x01U) /* Start condition is generated */\r
-/* Restart condition generation (IICRSTAREQ) */\r
-#define _00_SCI_RESTART_CONDITION_OFF (0x00U) /* Restart condition is not generated */\r
-#define _02_SCI_RESTART_CONDITION_ON (0x02U) /* Restart condition is generated */\r
-/* Stop condition generation (IICSTPREQ) */\r
-#define _00_SCI_STOP_CONDITION_OFF (0x00U) /* Stop condition is not generated */\r
-#define _04_SCI_STOP_CONDITION_ON (0x04U) /* Stop condition is generated */\r
-/* Issuing of start, restart, or sstop condition completed flag (IICSTIF) */\r
-#define _00_SCI_CONDITION_GENERATED (0x00U) /* No requests to generate conditions/conditions generated */\r
-#define _08_SCI_GENERATION_COMPLETED (0x08U) /* All request generation has been completed */\r
-/* SSDA output select (IICSDAS) */\r
-#define _00_SCI_SSDA_DATA_OUTPUT (0x00U) /* SSDA output is serial data output */\r
-#define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10U) /* SSDA output generates start, restart or stop condition */\r
-#define _20_SCI_SSDA_LOW_LEVEL (0x20U) /* SSDA output low level */\r
-#define _30_SCI_SSDA_HIGH_IMPEDANCE (0x30U) /* SSDA output high impedance */\r
-/* SSCL output select (IICSCLS) */\r
-#define _00_SCI_SSCL_CLOCK_OUTPUT (0x00U) /* SSCL output is serial clock output */\r
-#define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40U) /* SSCL output generates start, restart or stop condition */\r
-#define _80_SCI_SSCL_LOW_LEVEL (0x80U) /* SSCL output low level */\r
-#define _C0_SCI_SSCL_HIGH_IMPEDANCE (0xC0U) /* SSCL output high impedance */\r
-\r
-/*\r
- I2C status register (SISR)\r
-*/\r
-/* ACK reception data flag (IICACKR) */\r
-#define _00_SCI_ACK_RECEIVED (0x00U) /* ACK received */\r
-#define _01_SCI_NACK_RECEIVED (0x01U) /* NACK received */\r
-\r
-/*\r
- SPI mode register (SPMR)\r
-*/\r
-/* SS pin function enable (SSE) */\r
-#define _00_SCI_SS_PIN_DISABLE (0x00U) /* SS pin function disabled */\r
-#define _01_SCI_SS_PIN_ENABLE (0x01U) /* SS pin function enabled */\r
-/* CTS enable (CTSE) */\r
-#define _00_SCI_RTS (0x00U) /* RTS function is enabled */\r
-#define _02_SCI_CTS (0x02U) /* CTS function is disabled */\r
-/* Master slave select (MSS) */\r
-#define _00_SCI_SPI_MASTER (0x00U) /* Master mode */\r
-#define _04_SCI_SPI_SLAVE (0x04U) /* Slave mode */\r
-/* Mode fault flag (MFF) */\r
-#define _00_SCI_NO_MODE_FAULT (0x00U) /* No mode fault */\r
-#define _10_SCI_MODE_FAULT (0x10U) /* Mode fault */\r
-/* Clock polarity select (CKPOL) */\r
-#define _00_SCI_CLOCK_NOT_INVERTED (0x00U) /* Clock polarity is not inverted */\r
-#define _40_SCI_CLOCK_INVERTED (0x40U) /* Clock polarity is inverted */\r
-/* Clock phase select (CKPH) */\r
-#define _00_SCI_CLOCK_NOT_DELAYED (0x00U) /* Clock is not delayed */\r
-#define _80_SCI_CLOCK_DELAYED (0x80U) /* Clock is delayed */\r
-\r
-/*\r
- Interrupt Source Priority Register n (IPRn)\r
-*/\r
-/* Interrupt Priority Level Select (IPR[3:0]) */\r
-#define _00_SCI_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */\r
-#define _01_SCI_PRIORITY_LEVEL1 (0x01U) /* Level 1 */\r
-#define _02_SCI_PRIORITY_LEVEL2 (0x02U) /* Level 2 */\r
-#define _03_SCI_PRIORITY_LEVEL3 (0x03U) /* Level 3 */\r
-#define _04_SCI_PRIORITY_LEVEL4 (0x04U) /* Level 4 */\r
-#define _05_SCI_PRIORITY_LEVEL5 (0x05U) /* Level 5 */\r
-#define _06_SCI_PRIORITY_LEVEL6 (0x06U) /* Level 6 */\r
-#define _07_SCI_PRIORITY_LEVEL7 (0x07U) /* Level 7 */\r
-#define _08_SCI_PRIORITY_LEVEL8 (0x08U) /* Level 8 */\r
-#define _09_SCI_PRIORITY_LEVEL9 (0x09U) /* Level 9 */\r
-#define _0A_SCI_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */\r
-#define _0B_SCI_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */\r
-#define _0C_SCI_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */\r
-#define _0D_SCI_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */\r
-#define _0E_SCI_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */\r
-#define _0F_SCI_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */\r
-\r
-/*\r
- Transfer status control value\r
-*/\r
-/* Simple IIC Transmit Receive Flag */\r
-#define _80_SCI_IIC_TRANSMISSION (0x80U)\r
-#define _00_SCI_IIC_RECEPTION (0x00U)\r
-/* Simple IIC Start Stop Flag */\r
-#define _80_SCI_IIC_START_CYCLE (0x80U)\r
-#define _00_SCI_IIC_STOP_CYCLE (0x00U)\r
-/* Multiprocessor Asynchronous Communication Flag */\r
-#define _80_SCI_ID_TRANSMISSION_CYCLE (0x80U)\r
-#define _00_SCI_DATA_TRANSMISSION_CYCLE (0x00U)\r
-\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-void R_SCI1_Create(void);\r
-void R_SCI1_Start(void);\r
-void R_SCI1_Stop(void);\r
-MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num);\r
-MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num);\r
-static void r_sci1_callback_transmitend(void);\r
-static void r_sci1_callback_receiveend(void);\r
-static void r_sci1_callback_receiveerror(void);\r
-\r
-/* Start user code for function. Do not edit comment generated here */\r
-\r
-/* Some of the code in this file is generated using "Code Generator" for e2 studio.\r
- * Warnings exist in this module. */\r
-\r
-/* Exported functions used to transmit a number of bytes and wait for completion */\r
-MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num);\r
-\r
-/* Character is used to receive key presses from PC terminal */\r
-extern uint8_t g_rx_char;\r
-\r
-/* Flag used to control transmission to PC terminal */\r
-extern volatile uint8_t g_tx_flag;\r
-\r
-/* End user code. Do not edit comment generated here */\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_sci_user.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for SCI module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_sci.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-#include "rskrx113def.h"\r
-//_RB_#include "r_cg_cmt.h"\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-extern uint8_t * gp_sci1_tx_address; /* SCI1 send buffer address */\r
-extern uint16_t g_sci1_tx_count; /* SCI1 send data number */\r
-extern uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */\r
-extern uint16_t g_sci1_rx_count; /* SCI1 receive data number */\r
-extern uint16_t g_sci1_rx_length; /* SCI1 receive data length */\r
-/* Start user code for global. Do not edit comment generated here */\r
-\r
-/* Global used to receive a character from the PC terminal */\r
-uint8_t g_rx_char;\r
-\r
-/* Flag used to control transmission to PC terminal */\r
-volatile uint8_t g_tx_flag = FALSE;\r
-\r
-/* Flag used locally to detect transmission complete */\r
-static volatile uint8_t sci1_txdone;\r
-\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_transmit_interrupt\r
-* Description : None\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TXI1\r
-#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1),fint)\r
-#else\r
-#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1))\r
-#endif\r
-static void r_sci1_transmit_interrupt(void)\r
-{\r
- if (g_sci1_tx_count > 0U)\r
- {\r
- SCI1.TDR = *gp_sci1_tx_address;\r
- gp_sci1_tx_address++;\r
- g_sci1_tx_count--;\r
- }\r
- else \r
- {\r
- SCI1.SCR.BIT.TIE = 0U;\r
- SCI1.SCR.BIT.TEIE = 1U;\r
- }\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_transmitend_interrupt\r
-* Description : None\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TEI1\r
-#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1),fint)\r
-#else\r
-#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1))\r
-#endif\r
-static void r_sci1_transmitend_interrupt(void)\r
-{\r
- /* Set TXD1 pin */\r
- PORT1.PMR.BYTE &= 0xBFU;\r
- SCI1.SCR.BIT.TIE = 0U;\r
- SCI1.SCR.BIT.TE = 0U;\r
- SCI1.SCR.BIT.TEIE = 0U;\r
-\r
- r_sci1_callback_transmitend();\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_receive_interrupt\r
-* Description : None\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-#if FAST_INTERRUPT_VECTOR == VECT_SCI1_RXI1\r
-#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1),fint)\r
-#else\r
-#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1))\r
-#endif\r
-static void r_sci1_receive_interrupt(void)\r
-{\r
- if (g_sci1_rx_length > g_sci1_rx_count)\r
- {\r
- *gp_sci1_rx_address = SCI1.RDR;\r
- gp_sci1_rx_address++;\r
- g_sci1_rx_count++;\r
-\r
- if (g_sci1_rx_length == g_sci1_rx_count)\r
- {\r
- r_sci1_callback_receiveend();\r
- }\r
- }\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_receiveerror_interrupt\r
-* Description : None\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-#if FAST_INTERRUPT_VECTOR == VECT_SCI1_ERI1\r
-#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1),fint)\r
-#else\r
-#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1))\r
-#endif\r
-static void r_sci1_receiveerror_interrupt(void)\r
-{\r
- uint8_t err_type;\r
-\r
- r_sci1_callback_receiveerror();\r
-\r
- /* Clear overrun, framing and parity error flags */\r
- err_type = SCI1.SSR.BYTE;\r
- SCI1.SSR.BYTE = err_type & 0xC7U;\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_callback_transmitend\r
-* Description : This function is a callback function when SCI1 finishes transmission.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-static void r_sci1_callback_transmitend(void)\r
-{\r
- /* Start user code. Do not edit comment generated here */\r
- sci1_txdone = TRUE;\r
-\r
- /* End user code. Do not edit comment generated here */\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_callback_receiveend\r
-* Description : This function is a callback function when SCI1 finishes reception.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-static void r_sci1_callback_receiveend(void)\r
-{\r
- /* Start user code. Do not edit comment generated here */\r
- /* Check the contents of g_rx_char */\r
- if ('z' == g_rx_char)\r
- {\r
- /* Stop the timer used to control transmission to PC terminal*/\r
-//_RB_ R_CMT0_Stop();\r
-\r
- /* Turn off LED0 and turn on LED1 to indicate serial transmission\r
- inactive */\r
- LED0 = LED_OFF;\r
- LED1 = LED_ON;\r
- }\r
- else\r
- {\r
- /* Start the timer used to control transmission to PC terminal*/\r
-//_RB_ R_CMT0_Start();\r
-\r
- /* Turn on LED0 and turn off LED1 to indicate serial transmission\r
- active */\r
- LED0 = LED_ON;\r
- LED1 = LED_OFF;\r
- }\r
-\r
- /* Set up SCI1 receive buffer again */\r
- R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
-\r
- /* End user code. Do not edit comment generated here */\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_callback_receiveerror\r
-* Description : This function is a callback function when SCI1 reception encounters error.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-static void r_sci1_callback_receiveerror(void)\r
-{\r
- /* Start user code. Do not edit comment generated here */\r
- /* End user code. Do not edit comment generated here */\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/***********************************************************************************************************************\r
- * Function Name: R_SCI1_AsyncTransmit\r
- * Description : This function sends SCI1 data and waits for the transmit end flag.\r
- * Arguments : tx_buf -\r
- * transfer buffer pointer\r
- * tx_num -\r
- * buffer size\r
- * Return Value : status -\r
- * MD_OK or MD_ARGERROR\r
- ***********************************************************************************************************************/\r
-MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num)\r
-{\r
- MD_STATUS status = MD_OK;\r
-\r
- /* clear the flag before initiating a new transmission */\r
- sci1_txdone = FALSE;\r
-\r
- /* Send the data using the API */\r
- status = R_SCI1_Serial_Send(tx_buf, tx_num);\r
-\r
- /* Wait for the transmit end flag */\r
- while (FALSE == sci1_txdone)\r
- {\r
- /* Wait */\r
- }\r
- return (status);\r
-}\r
-/***********************************************************************************************************************\r
- * End of function R_SCI1_AsyncTransmit\r
- ***********************************************************************************************************************/\r
-\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_userdefine.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file includes user definition.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef _USER_DEF_H\r
-#define _USER_DEF_H\r
-\r
-/***********************************************************************************************************************\r
-User definitions\r
-***********************************************************************************************************************/\r
-#define FAST_INTERRUPT_VECTOR 0\r
-\r
-/* Start user code for function. Do not edit comment generated here */\r
-#define TRUE (1)\r
-#define FALSE (0)\r
-/* End user code. Do not edit comment generated here */\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***************************************************************/\r
-/* */\r
-/* PROJECT NAME : RTOSDemo */\r
-/* FILE : iodefine.h */\r
-/* DESCRIPTION : Definition of I/O Registers */\r
-/* CPU SERIES : RX100 */\r
-/* CPU TYPE : RX113 */\r
-/* */\r
-/* This file is generated by e2 studio. */\r
-/* */\r
-/***************************************************************/ \r
- \r
- \r
- \r
- \r
-/*********************************************************************************\r
-*\r
-* Device : RX/RX100/RX113\r
-*\r
-* File Name : iodefine.h\r
-*\r
-* Abstract : Definition of I/O Register.\r
-*\r
-* History : 0.4 (2013-11-18) [Hardware Manual Revision : 0.40]\r
-* : 0.5 (2014-01-05) [Hardware Manual Revision : 0.50]\r
-* : 1.0 (2014-07-22) [Hardware Manual Revision : 1.00]\r
-* : 1.0A (2015-04-20) [Hardware Manual Revision : 1.02 + TU]\r
-*\r
-* NOTE : THIS IS A TYPICAL EXAMPLE.\r
-*\r
-* Copyright (C) 2015 (2013 - 2014) Renesas Electronics Corporation.\r
-*\r
-*********************************************************************************/\r
-/********************************************************************************/\r
-/* */\r
-/* DESCRIPTION : Definition of ICU Register */\r
-/* CPU TYPE : RX113 */\r
-/* */\r
-/* Usage : IR,DTCER,IER,IPR of ICU Register */\r
-/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */\r
-/* The bit access operation is "Bit_Name(interrupt source,name)". */\r
-/* A part of the name can be omitted. */\r
-/* for example : */\r
-/* IR(MTU0,TGIA0) = 0; expands to : */\r
-/* ICU.IR[114].BIT.IR = 0; */\r
-/* */\r
-/* DTCE(ICU,IRQ0) = 1; expands to : */\r
-/* ICU.DTCER[64].BIT.DTCE = 1; */\r
-/* */\r
-/* IEN(CMT0,CMI0) = 1; expands to : */\r
-/* ICU.IER[0x03].BIT.IEN4 = 1; */\r
-/* */\r
-/* Usage : #pragma interrupt Function_Identifier(vect=**) */\r
-/* The number of vector is "(interrupt source, name)". */\r
-/* for example : */\r
-/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */\r
-/* #pragma interrupt INT_IRQ0(vect=64) */\r
-/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */\r
-/* #pragma interrupt INT_CMT0_CMI0(vect=28) */\r
-/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */\r
-/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */\r
-/* */\r
-/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */\r
-/* The bit access operation is "MSTP(name)". */\r
-/* The name that can be used is a macro name defined with "iodefine.h". */\r
-/* for example : */\r
-/* MSTP(TMR2) = 0; // TMR23,TMR2,TMR3 expands to : */\r
-/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */\r
-/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */\r
-/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */\r
-/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */\r
-/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */\r
-/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */\r
-/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */\r
-/* */\r
-/* */\r
-/********************************************************************************/\r
-#ifndef __RX113IODEFINE_HEADER__\r
-#define __RX113IODEFINE_HEADER__\r
-\r
-#pragma pack(4)\r
-\r
-struct st_bsc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char STSCLR : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char STSCLR : 1;\r
-#endif\r
- } BIT;\r
- } BERCLR;\r
- char wk0[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IGAEN : 1;\r
- unsigned char TOEN : 1;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char TOEN : 1;\r
- unsigned char IGAEN : 1;\r
-#endif\r
- } BIT;\r
- } BEREN;\r
- char wk1[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IA : 1;\r
- unsigned char TO : 1;\r
- unsigned char : 2;\r
- unsigned char MST : 3;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char MST : 3;\r
- unsigned char : 2;\r
- unsigned char TO : 1;\r
- unsigned char IA : 1;\r
-#endif\r
- } BIT;\r
- } BERSR1;\r
- char wk2[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 3;\r
- unsigned short ADDR : 13;\r
-#else\r
- unsigned short ADDR : 13;\r
- unsigned short : 3;\r
-#endif\r
- } BIT;\r
- } BERSR2;\r
- char wk3[4];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short BPRA : 2;\r
- unsigned short BPRO : 2;\r
- unsigned short BPIB : 2;\r
- unsigned short BPGB : 2;\r
- unsigned short : 2;\r
- unsigned short BPFB : 2;\r
- unsigned short : 4;\r
-#else\r
- unsigned short : 4;\r
- unsigned short BPFB : 2;\r
- unsigned short : 2;\r
- unsigned short BPGB : 2;\r
- unsigned short BPIB : 2;\r
- unsigned short BPRO : 2;\r
- unsigned short BPRA : 2;\r
-#endif\r
- } BIT;\r
- } BUSPRI;\r
-};\r
-\r
-struct st_cac {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CFME : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char CFME : 1;\r
-#endif\r
- } BIT;\r
- } CACR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CACREFE : 1;\r
- unsigned char FMCS : 3;\r
- unsigned char TCSS : 2;\r
- unsigned char EDGES : 2;\r
-#else\r
- unsigned char EDGES : 2;\r
- unsigned char TCSS : 2;\r
- unsigned char FMCS : 3;\r
- unsigned char CACREFE : 1;\r
-#endif\r
- } BIT;\r
- } CACR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char RPS : 1;\r
- unsigned char RSCS : 3;\r
- unsigned char RCDS : 2;\r
- unsigned char DFS : 2;\r
-#else\r
- unsigned char DFS : 2;\r
- unsigned char RCDS : 2;\r
- unsigned char RSCS : 3;\r
- unsigned char RPS : 1;\r
-#endif\r
- } BIT;\r
- } CACR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char FERRIE : 1;\r
- unsigned char MENDIE : 1;\r
- unsigned char OVFIE : 1;\r
- unsigned char : 1;\r
- unsigned char FERRFCL : 1;\r
- unsigned char MENDFCL : 1;\r
- unsigned char OVFFCL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char OVFFCL : 1;\r
- unsigned char MENDFCL : 1;\r
- unsigned char FERRFCL : 1;\r
- unsigned char : 1;\r
- unsigned char OVFIE : 1;\r
- unsigned char MENDIE : 1;\r
- unsigned char FERRIE : 1;\r
-#endif\r
- } BIT;\r
- } CAICR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char FERRF : 1;\r
- unsigned char MENDF : 1;\r
- unsigned char OVFF : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char OVFF : 1;\r
- unsigned char MENDF : 1;\r
- unsigned char FERRF : 1;\r
-#endif\r
- } BIT;\r
- } CASTR;\r
- char wk0[1];\r
- unsigned short CAULVR;\r
- unsigned short CALLVR;\r
- unsigned short CACNTBR;\r
-};\r
-\r
-struct st_cmpb {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CPB0INI : 1;\r
- unsigned char : 3;\r
- unsigned char CPB1INI : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char CPB1INI : 1;\r
- unsigned char : 3;\r
- unsigned char CPB0INI : 1;\r
-#endif\r
- } BIT;\r
- } CPBCNT1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CPB0WCP : 1;\r
- unsigned char : 3;\r
- unsigned char CPB1WCP : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char CPB1WCP : 1;\r
- unsigned char : 3;\r
- unsigned char CPB0WCP : 1;\r
-#endif\r
- } BIT;\r
- } CPBCNT2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 3;\r
- unsigned char CPB0OUT : 1;\r
- unsigned char : 3;\r
- unsigned char CPB1OUT : 1;\r
-#else\r
- unsigned char CPB1OUT : 1;\r
- unsigned char : 3;\r
- unsigned char CPB0OUT : 1;\r
- unsigned char : 3;\r
-#endif\r
- } BIT;\r
- } CPBFLG;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CPB0INTEN : 1;\r
- unsigned char CPB0INTEG : 1;\r
- unsigned char CPB0INTPL : 1;\r
- unsigned char : 1;\r
- unsigned char CPB1INTEN : 1;\r
- unsigned char CPB1INTEG : 1;\r
- unsigned char CPB1INTPL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char CPB1INTPL : 1;\r
- unsigned char CPB1INTEG : 1;\r
- unsigned char CPB1INTEN : 1;\r
- unsigned char : 1;\r
- unsigned char CPB0INTPL : 1;\r
- unsigned char CPB0INTEG : 1;\r
- unsigned char CPB0INTEN : 1;\r
-#endif\r
- } BIT;\r
- } CPBINT;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CPB0FEN : 1;\r
- unsigned char : 1;\r
- unsigned char CPB0F : 2;\r
- unsigned char CPB1FEN : 1;\r
- unsigned char : 1;\r
- unsigned char CPB1F : 2;\r
-#else\r
- unsigned char CPB1F : 2;\r
- unsigned char : 1;\r
- unsigned char CPB1FEN : 1;\r
- unsigned char CPB0F : 2;\r
- unsigned char : 1;\r
- unsigned char CPB0FEN : 1;\r
-#endif\r
- } BIT;\r
- } CPBF;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CPBSPDMD : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char CPBSPDMD : 1;\r
-#endif\r
- } BIT;\r
- } CPBMD;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CPB0VRF : 1;\r
- unsigned char : 3;\r
- unsigned char CPB1VRF : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char CPB1VRF : 1;\r
- unsigned char : 3;\r
- unsigned char CPB0VRF : 1;\r
-#endif\r
- } BIT;\r
- } CPBREF;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CPB0OE : 1;\r
- unsigned char CPB0OP : 1;\r
- unsigned char : 2;\r
- unsigned char CPB1OE : 1;\r
- unsigned char CPB1OP : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char CPB1OP : 1;\r
- unsigned char CPB1OE : 1;\r
- unsigned char : 2;\r
- unsigned char CPB0OP : 1;\r
- unsigned char CPB0OE : 1;\r
-#endif\r
- } BIT;\r
- } CPBOCR;\r
-};\r
-\r
-struct st_cmt {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short STR0 : 1;\r
- unsigned short STR1 : 1;\r
- unsigned short : 14;\r
-#else\r
- unsigned short : 14;\r
- unsigned short STR1 : 1;\r
- unsigned short STR0 : 1;\r
-#endif\r
- } BIT;\r
- } CMSTR0;\r
- char wk0[14];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short STR2 : 1;\r
- unsigned short STR3 : 1;\r
- unsigned short : 14;\r
-#else\r
- unsigned short : 14;\r
- unsigned short STR3 : 1;\r
- unsigned short STR2 : 1;\r
-#endif\r
- } BIT;\r
- } CMSTR1;\r
-};\r
-\r
-struct st_cmt0 {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CKS : 2;\r
- unsigned short : 4;\r
- unsigned short CMIE : 1;\r
- unsigned short : 9;\r
-#else\r
- unsigned short : 9;\r
- unsigned short CMIE : 1;\r
- unsigned short : 4;\r
- unsigned short CKS : 2;\r
-#endif\r
- } BIT;\r
- } CMCR;\r
- unsigned short CMCNT;\r
- unsigned short CMCOR;\r
-};\r
-\r
-struct st_crc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char GPS : 2;\r
- unsigned char LMS : 1;\r
- unsigned char : 4;\r
- unsigned char DORCLR : 1;\r
-#else\r
- unsigned char DORCLR : 1;\r
- unsigned char : 4;\r
- unsigned char LMS : 1;\r
- unsigned char GPS : 2;\r
-#endif\r
- } BIT;\r
- } CRCCR;\r
- unsigned char CRCDIR;\r
- unsigned short CRCDOR;\r
-};\r
-\r
-struct st_ctsu {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUSTRT : 1;\r
- unsigned char CTSUCAP : 1;\r
- unsigned char CTSUSNZ : 1;\r
- unsigned char : 1;\r
- unsigned char CTSUINIT : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char CTSUINIT : 1;\r
- unsigned char : 1;\r
- unsigned char CTSUSNZ : 1;\r
- unsigned char CTSUCAP : 1;\r
- unsigned char CTSUSTRT : 1;\r
-#endif\r
- } BIT;\r
- } CTSUCR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUPON : 1;\r
- unsigned char CTSUCSW : 1;\r
- unsigned char CTSUATUNE0 : 1;\r
- unsigned char CTSUATUNE1 : 1;\r
- unsigned char CTSUCLK : 2;\r
- unsigned char CTSUMD : 2;\r
-#else\r
- unsigned char CTSUMD : 2;\r
- unsigned char CTSUCLK : 2;\r
- unsigned char CTSUATUNE1 : 1;\r
- unsigned char CTSUATUNE0 : 1;\r
- unsigned char CTSUCSW : 1;\r
- unsigned char CTSUPON : 1;\r
-#endif\r
- } BIT;\r
- } CTSUCR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUPRRATIO : 4;\r
- unsigned char CTSUPRMODE : 2;\r
- unsigned char CTSUSOFF : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char CTSUSOFF : 1;\r
- unsigned char CTSUPRMODE : 2;\r
- unsigned char CTSUPRRATIO : 4;\r
-#endif\r
- } BIT;\r
- } CTSUSDPRS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUSST : 8;\r
-#else\r
- unsigned char CTSUSST : 8;\r
-#endif\r
- } BIT;\r
- } CTSUSST;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUMCH0 : 4;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char CTSUMCH0 : 4;\r
-#endif\r
- } BIT;\r
- } CTSUMCH0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUMCH1 : 4;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char CTSUMCH1 : 4;\r
-#endif\r
- } BIT;\r
- } CTSUMCH1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUCHAC00 : 1;\r
- unsigned char CTSUCHAC01 : 1;\r
- unsigned char CTSUCHAC02 : 1;\r
- unsigned char CTSUCHAC03 : 1;\r
- unsigned char CTSUCHAC04 : 1;\r
- unsigned char CTSUCHAC05 : 1;\r
- unsigned char CTSUCHAC06 : 1;\r
- unsigned char CTSUCHAC07 : 1;\r
-#else\r
- unsigned char CTSUCHAC07 : 1;\r
- unsigned char CTSUCHAC06 : 1;\r
- unsigned char CTSUCHAC05 : 1;\r
- unsigned char CTSUCHAC04 : 1;\r
- unsigned char CTSUCHAC03 : 1;\r
- unsigned char CTSUCHAC02 : 1;\r
- unsigned char CTSUCHAC01 : 1;\r
- unsigned char CTSUCHAC00 : 1;\r
-#endif\r
- } BIT;\r
- } CTSUCHAC0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUCHAC10 : 1;\r
- unsigned char CTSUCHAC11 : 1;\r
- unsigned char CTSUCHAC12 : 1;\r
- unsigned char CTSUCHAC13 : 1;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char CTSUCHAC13 : 1;\r
- unsigned char CTSUCHAC12 : 1;\r
- unsigned char CTSUCHAC11 : 1;\r
- unsigned char CTSUCHAC10 : 1;\r
-#endif\r
- } BIT;\r
- } CTSUCHAC1;\r
- char wk0[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUCHTRC00 : 1;\r
- unsigned char CTSUCHTRC01 : 1;\r
- unsigned char CTSUCHTRC02 : 1;\r
- unsigned char CTSUCHTRC03 : 1;\r
- unsigned char CTSUCHTRC04 : 1;\r
- unsigned char CTSUCHTRC05 : 1;\r
- unsigned char CTSUCHTRC06 : 1;\r
- unsigned char CTSUCHTRC07 : 1;\r
-#else\r
- unsigned char CTSUCHTRC07 : 1;\r
- unsigned char CTSUCHTRC06 : 1;\r
- unsigned char CTSUCHTRC05 : 1;\r
- unsigned char CTSUCHTRC04 : 1;\r
- unsigned char CTSUCHTRC03 : 1;\r
- unsigned char CTSUCHTRC02 : 1;\r
- unsigned char CTSUCHTRC01 : 1;\r
- unsigned char CTSUCHTRC00 : 1;\r
-#endif\r
- } BIT;\r
- } CTSUCHTRC0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUCHTRC10 : 1;\r
- unsigned char CTSUCHTRC11 : 1;\r
- unsigned char CTSUCHTRC12 : 1;\r
- unsigned char CTSUCHTRC13 : 1;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char CTSUCHTRC13 : 1;\r
- unsigned char CTSUCHTRC12 : 1;\r
- unsigned char CTSUCHTRC11 : 1;\r
- unsigned char CTSUCHTRC10 : 1;\r
-#endif\r
- } BIT;\r
- } CTSUCHTRC1;\r
- char wk1[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUSSMOD : 2;\r
- unsigned char : 2;\r
- unsigned char CTSUSSCNT : 2;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char CTSUSSCNT : 2;\r
- unsigned char : 2;\r
- unsigned char CTSUSSMOD : 2;\r
-#endif\r
- } BIT;\r
- } CTSUDCLKC;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CTSUSTC : 3;\r
- unsigned char : 1;\r
- unsigned char CTSUDTSR : 1;\r
- unsigned char CTSUSOVF : 1;\r
- unsigned char CTSUROVF : 1;\r
- unsigned char CTSUPS : 1;\r
-#else\r
- unsigned char CTSUPS : 1;\r
- unsigned char CTSUROVF : 1;\r
- unsigned char CTSUSOVF : 1;\r
- unsigned char CTSUDTSR : 1;\r
- unsigned char : 1;\r
- unsigned char CTSUSTC : 3;\r
-#endif\r
- } BIT;\r
- } CTSUST;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 8;\r
- unsigned short CTSUSSDIV : 4;\r
- unsigned short : 4;\r
-#else\r
- unsigned short : 4;\r
- unsigned short CTSUSSDIV : 4;\r
- unsigned short : 8;\r
-#endif\r
- } BIT;\r
- } CTSUSSC;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CTSUSO : 10;\r
- unsigned short CTSUSNUM : 6;\r
-#else\r
- unsigned short CTSUSNUM : 6;\r
- unsigned short CTSUSO : 10;\r
-#endif\r
- } BIT;\r
- } CTSUSO0;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CTSURICOA : 8;\r
- unsigned short CTSUSDPA : 5;\r
- unsigned short CTSUICOG : 2;\r
- unsigned short : 1;\r
-#else\r
- unsigned short : 1;\r
- unsigned short CTSUICOG : 2;\r
- unsigned short CTSUSDPA : 5;\r
- unsigned short CTSURICOA : 8;\r
-#endif\r
- } BIT;\r
- } CTSUSO1;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CTSUSC : 16;\r
-#else\r
- unsigned short CTSUSC : 16;\r
-#endif\r
- } BIT;\r
- } CTSUSC;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CTSURC : 16;\r
-#else\r
- unsigned short CTSURC : 16;\r
-#endif\r
- } BIT;\r
- } CTSURC;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 15;\r
- unsigned short CTSUICOMP : 1;\r
-#else\r
- unsigned short CTSUICOMP : 1;\r
- unsigned short : 15;\r
-#endif\r
- } BIT;\r
- } CTSUERRS;\r
-};\r
-\r
-struct st_da {\r
- unsigned short DADR0;\r
- unsigned short DADR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 6;\r
- unsigned char DAOE0 : 1;\r
- unsigned char DAOE1 : 1;\r
-#else\r
- unsigned char DAOE1 : 1;\r
- unsigned char DAOE0 : 1;\r
- unsigned char : 6;\r
-#endif\r
- } BIT;\r
- } DACR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char DPSEL : 1;\r
-#else\r
- unsigned char DPSEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } DADPR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char DAADST : 1;\r
-#else\r
- unsigned char DAADST : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } DAADSCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char REF : 3;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char REF : 3;\r
-#endif\r
- } BIT;\r
- } DAVREFCR;\r
-};\r
-\r
-struct st_doc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char OMS : 2;\r
- unsigned char DCSEL : 1;\r
- unsigned char : 1;\r
- unsigned char DOPCIE : 1;\r
- unsigned char DOPCF : 1;\r
- unsigned char DOPCFCL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char DOPCFCL : 1;\r
- unsigned char DOPCF : 1;\r
- unsigned char DOPCIE : 1;\r
- unsigned char : 1;\r
- unsigned char DCSEL : 1;\r
- unsigned char OMS : 2;\r
-#endif\r
- } BIT;\r
- } DOCR;\r
- char wk0[1];\r
- unsigned short DODIR;\r
- unsigned short DODSR;\r
-};\r
-\r
-struct st_dtc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 4;\r
- unsigned char RRS : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char RRS : 1;\r
- unsigned char : 4;\r
-#endif\r
- } BIT;\r
- } DTCCR;\r
- char wk0[3];\r
- void *DTCVBR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SHORT : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char SHORT : 1;\r
-#endif\r
- } BIT;\r
- } DTCADMOD;\r
- char wk1[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char DTCST : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char DTCST : 1;\r
-#endif\r
- } BIT;\r
- } DTCST;\r
- char wk2[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short VECN : 8;\r
- unsigned short : 7;\r
- unsigned short ACT : 1;\r
-#else\r
- unsigned short ACT : 1;\r
- unsigned short : 7;\r
- unsigned short VECN : 8;\r
-#endif\r
- } BIT;\r
- } DTCSTS;\r
-};\r
-\r
-struct st_elc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ELCON : 1;\r
-#else\r
- unsigned char ELCON : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } ELCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char ELS : 8;\r
-#else\r
- unsigned char ELS : 8;\r
-#endif\r
- } BIT;\r
- } ELSR[26];\r
- char wk0[4];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 2;\r
- unsigned char MTU1MD : 2;\r
- unsigned char MTU2MD : 2;\r
- unsigned char MTU3MD : 2;\r
-#else\r
- unsigned char MTU3MD : 2;\r
- unsigned char MTU2MD : 2;\r
- unsigned char MTU1MD : 2;\r
- unsigned char : 2;\r
-#endif\r
- } BIT;\r
- } ELOPA;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MTU4MD : 2;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char MTU4MD : 2;\r
-#endif\r
- } BIT;\r
- } ELOPB;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 2;\r
- unsigned char CMT1MD : 2;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char CMT1MD : 2;\r
- unsigned char : 2;\r
-#endif\r
- } BIT;\r
- } ELOPC;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TMR0MD : 2;\r
- unsigned char : 2;\r
- unsigned char TMR2MD : 2;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char TMR2MD : 2;\r
- unsigned char : 2;\r
- unsigned char TMR0MD : 2;\r
-#endif\r
- } BIT;\r
- } ELOPD;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PGR0 : 1;\r
- unsigned char PGR1 : 1;\r
- unsigned char PGR2 : 1;\r
- unsigned char PGR3 : 1;\r
- unsigned char PGR4 : 1;\r
- unsigned char PGR5 : 1;\r
- unsigned char PGR6 : 1;\r
- unsigned char PGR7 : 1;\r
-#else\r
- unsigned char PGR7 : 1;\r
- unsigned char PGR6 : 1;\r
- unsigned char PGR5 : 1;\r
- unsigned char PGR4 : 1;\r
- unsigned char PGR3 : 1;\r
- unsigned char PGR2 : 1;\r
- unsigned char PGR1 : 1;\r
- unsigned char PGR0 : 1;\r
-#endif\r
- } BIT;\r
- } PGR1;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PGCI : 2;\r
- unsigned char PGCOVE : 1;\r
- unsigned char : 1;\r
- unsigned char PGCO : 3;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char PGCO : 3;\r
- unsigned char : 1;\r
- unsigned char PGCOVE : 1;\r
- unsigned char PGCI : 2;\r
-#endif\r
- } BIT;\r
- } PGC1;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PDBF0 : 1;\r
- unsigned char PDBF1 : 1;\r
- unsigned char PDBF2 : 1;\r
- unsigned char PDBF3 : 1;\r
- unsigned char PDBF4 : 1;\r
- unsigned char PDBF5 : 1;\r
- unsigned char PDBF6 : 1;\r
- unsigned char PDBF7 : 1;\r
-#else\r
- unsigned char PDBF7 : 1;\r
- unsigned char PDBF6 : 1;\r
- unsigned char PDBF5 : 1;\r
- unsigned char PDBF4 : 1;\r
- unsigned char PDBF3 : 1;\r
- unsigned char PDBF2 : 1;\r
- unsigned char PDBF1 : 1;\r
- unsigned char PDBF0 : 1;\r
-#endif\r
- } BIT;\r
- } PDBF1;\r
- char wk3[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSB : 3;\r
- unsigned char PSP : 2;\r
- unsigned char PSM : 2;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char PSM : 2;\r
- unsigned char PSP : 2;\r
- unsigned char PSB : 3;\r
-#endif\r
- } BIT;\r
- } PEL0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSB : 3;\r
- unsigned char PSP : 2;\r
- unsigned char PSM : 2;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char PSM : 2;\r
- unsigned char PSP : 2;\r
- unsigned char PSB : 3;\r
-#endif\r
- } BIT;\r
- } PEL1;\r
- char wk4[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SEG : 1;\r
- unsigned char : 5;\r
- unsigned char WE : 1;\r
- unsigned char WI : 1;\r
-#else\r
- unsigned char WI : 1;\r
- unsigned char WE : 1;\r
- unsigned char : 5;\r
- unsigned char SEG : 1;\r
-#endif\r
- } BIT;\r
- } ELSEGR;\r
-};\r
-\r
-struct st_flash {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char DFLEN : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char DFLEN : 1;\r
-#endif\r
- } BIT;\r
- } DFLCTL;\r
- char wk0[31];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 8;\r
- unsigned short SASMF : 1;\r
- unsigned short : 7;\r
-#else\r
- unsigned short : 7;\r
- unsigned short SASMF : 1;\r
- unsigned short : 8;\r
-#endif\r
- } BIT;\r
- } FSCMR;\r
- unsigned short FAWSMR;\r
- unsigned short FAWEMR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PCKA : 5;\r
- unsigned char : 1;\r
- unsigned char SAS : 2;\r
-#else\r
- unsigned char SAS : 2;\r
- unsigned char : 1;\r
- unsigned char PCKA : 5;\r
-#endif\r
- } BIT;\r
- } FISR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CMD : 3;\r
- unsigned char : 4;\r
- unsigned char OPST : 1;\r
-#else\r
- unsigned char OPST : 1;\r
- unsigned char : 4;\r
- unsigned char CMD : 3;\r
-#endif\r
- } BIT;\r
- } FEXCR;\r
- unsigned short FEAML;\r
-// char wk1[1];\r
- unsigned char FEAMH;\r
- char wk2[5];\r
- unsigned char FPR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PERR : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char PERR : 1;\r
-#endif\r
- } BIT;\r
- } FPSR;\r
- unsigned short FRBL;\r
- unsigned short FRBH;\r
- char wk3[16058];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 1;\r
- unsigned char FMS0 : 1;\r
- unsigned char : 1;\r
- unsigned char RPDIS : 1;\r
- unsigned char FMS1 : 1;\r
- unsigned char : 1;\r
- unsigned char LVPE : 1;\r
- unsigned char FMS2 : 1;\r
-#else\r
- unsigned char FMS2 : 1;\r
- unsigned char LVPE : 1;\r
- unsigned char : 1;\r
- unsigned char FMS1 : 1;\r
- unsigned char RPDIS : 1;\r
- unsigned char : 1;\r
- unsigned char FMS0 : 1;\r
- unsigned char : 1;\r
-#endif\r
- } BIT;\r
- } FPMCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char EXS : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char EXS : 1;\r
-#endif\r
- } BIT;\r
- } FASR;\r
- unsigned short FSARL;\r
-// char wk4[1];\r
- unsigned char FSARH;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CMD : 4;\r
- unsigned char DRC : 1;\r
- unsigned char : 1;\r
- unsigned char STOP : 1;\r
- unsigned char OPST : 1;\r
-#else\r
- unsigned char OPST : 1;\r
- unsigned char STOP : 1;\r
- unsigned char : 1;\r
- unsigned char DRC : 1;\r
- unsigned char CMD : 4;\r
-#endif\r
- } BIT;\r
- } FCR;\r
- unsigned short FEARL;\r
- unsigned char FEARH;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char FRESET : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char FRESET : 1;\r
-#endif\r
- } BIT;\r
- } FRESETR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char ERERR : 1;\r
- unsigned char PRGERR : 1;\r
- unsigned char : 1;\r
- unsigned char BCERR : 1;\r
- unsigned char ILGLERR : 1;\r
- unsigned char EILGLERR : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char EILGLERR : 1;\r
- unsigned char ILGLERR : 1;\r
- unsigned char BCERR : 1;\r
- unsigned char : 1;\r
- unsigned char PRGERR : 1;\r
- unsigned char ERERR : 1;\r
-#endif\r
- } BIT;\r
- } FSTATR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 1;\r
- unsigned char DRRDY : 1;\r
- unsigned char : 4;\r
- unsigned char FRDY : 1;\r
- unsigned char EXRDY : 1;\r
-#else\r
- unsigned char EXRDY : 1;\r
- unsigned char FRDY : 1;\r
- unsigned char : 4;\r
- unsigned char DRRDY : 1;\r
- unsigned char : 1;\r
-#endif\r
- } BIT;\r
- } FSTATR1;\r
- unsigned short FWBL;\r
- unsigned short FWBH;\r
- char wk5[34];\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short FEKEY:8;\r
-// unsigned short FENTRYD:1;\r
-// unsigned short :6;\r
-// unsigned short FENTRY0:1;\r
-// } BIT;\r
- } FENTRYR;\r
-};\r
-\r
-struct st_icu {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IR : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char IR : 1;\r
-#endif\r
- } BIT;\r
- } IR[250];\r
- char wk0[6];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char DTCE : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char DTCE : 1;\r
-#endif\r
- } BIT;\r
- } DTCER[249];\r
- char wk1[7];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IEN0 : 1;\r
- unsigned char IEN1 : 1;\r
- unsigned char IEN2 : 1;\r
- unsigned char IEN3 : 1;\r
- unsigned char IEN4 : 1;\r
- unsigned char IEN5 : 1;\r
- unsigned char IEN6 : 1;\r
- unsigned char IEN7 : 1;\r
-#else\r
- unsigned char IEN7 : 1;\r
- unsigned char IEN6 : 1;\r
- unsigned char IEN5 : 1;\r
- unsigned char IEN4 : 1;\r
- unsigned char IEN3 : 1;\r
- unsigned char IEN2 : 1;\r
- unsigned char IEN1 : 1;\r
- unsigned char IEN0 : 1;\r
-#endif\r
- } BIT;\r
- } IER[32];\r
- char wk2[192];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SWINT : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char SWINT : 1;\r
-#endif\r
- } BIT;\r
- } SWINTR;\r
- char wk3[15];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short FVCT : 8;\r
- unsigned short : 7;\r
- unsigned short FIEN : 1;\r
-#else\r
- unsigned short FIEN : 1;\r
- unsigned short : 7;\r
- unsigned short FVCT : 8;\r
-#endif\r
- } BIT;\r
- } FIR;\r
- char wk4[14];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IPR : 4;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char IPR : 4;\r
-#endif\r
- } BIT;\r
- } IPR[250];\r
- char wk5[262];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 2;\r
- unsigned char IRQMD : 2;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char IRQMD : 2;\r
- unsigned char : 2;\r
-#endif\r
- } BIT;\r
- } IRQCR[8];\r
- char wk6[8];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char FLTEN0 : 1;\r
- unsigned char FLTEN1 : 1;\r
- unsigned char FLTEN2 : 1;\r
- unsigned char FLTEN3 : 1;\r
- unsigned char FLTEN4 : 1;\r
- unsigned char FLTEN5 : 1;\r
- unsigned char FLTEN6 : 1;\r
- unsigned char FLTEN7 : 1;\r
-#else\r
- unsigned char FLTEN7 : 1;\r
- unsigned char FLTEN6 : 1;\r
- unsigned char FLTEN5 : 1;\r
- unsigned char FLTEN4 : 1;\r
- unsigned char FLTEN3 : 1;\r
- unsigned char FLTEN2 : 1;\r
- unsigned char FLTEN1 : 1;\r
- unsigned char FLTEN0 : 1;\r
-#endif\r
- } BIT;\r
- } IRQFLTE0;\r
- char wk7[3];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short FCLKSEL0 : 2;\r
- unsigned short FCLKSEL1 : 2;\r
- unsigned short FCLKSEL2 : 2;\r
- unsigned short FCLKSEL3 : 2;\r
- unsigned short FCLKSEL4 : 2;\r
- unsigned short FCLKSEL5 : 2;\r
- unsigned short FCLKSEL6 : 2;\r
- unsigned short FCLKSEL7 : 2;\r
-#else\r
- unsigned short FCLKSEL7 : 2;\r
- unsigned short FCLKSEL6 : 2;\r
- unsigned short FCLKSEL5 : 2;\r
- unsigned short FCLKSEL4 : 2;\r
- unsigned short FCLKSEL3 : 2;\r
- unsigned short FCLKSEL2 : 2;\r
- unsigned short FCLKSEL1 : 2;\r
- unsigned short FCLKSEL0 : 2;\r
-#endif\r
- } BIT;\r
- } IRQFLTC0;\r
- char wk8[106];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NMIST : 1;\r
- unsigned char OSTST : 1;\r
- unsigned char : 1;\r
- unsigned char IWDTST : 1;\r
- unsigned char LVD1ST : 1;\r
- unsigned char LVD2ST : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char LVD2ST : 1;\r
- unsigned char LVD1ST : 1;\r
- unsigned char IWDTST : 1;\r
- unsigned char : 1;\r
- unsigned char OSTST : 1;\r
- unsigned char NMIST : 1;\r
-#endif\r
- } BIT;\r
- } NMISR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NMIEN : 1;\r
- unsigned char OSTEN : 1;\r
- unsigned char : 1;\r
- unsigned char IWDTEN : 1;\r
- unsigned char LVD1EN : 1;\r
- unsigned char LVD2EN : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char LVD2EN : 1;\r
- unsigned char LVD1EN : 1;\r
- unsigned char IWDTEN : 1;\r
- unsigned char : 1;\r
- unsigned char OSTEN : 1;\r
- unsigned char NMIEN : 1;\r
-#endif\r
- } BIT;\r
- } NMIER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NMICLR : 1;\r
- unsigned char OSTCLR : 1;\r
- unsigned char : 1;\r
- unsigned char IWDTCLR : 1;\r
- unsigned char LVD1CLR : 1;\r
- unsigned char LVD2CLR : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char LVD2CLR : 1;\r
- unsigned char LVD1CLR : 1;\r
- unsigned char IWDTCLR : 1;\r
- unsigned char : 1;\r
- unsigned char OSTCLR : 1;\r
- unsigned char NMICLR : 1;\r
-#endif\r
- } BIT;\r
- } NMICLR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 3;\r
- unsigned char NMIMD : 1;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char NMIMD : 1;\r
- unsigned char : 3;\r
-#endif\r
- } BIT;\r
- } NMICR;\r
- char wk9[12];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NFLTEN : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char NFLTEN : 1;\r
-#endif\r
- } BIT;\r
- } NMIFLTE;\r
- char wk10[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NFCLKSEL : 2;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char NFCLKSEL : 2;\r
-#endif\r
- } BIT;\r
- } NMIFLTC;\r
-};\r
-\r
-struct st_irda {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 2;\r
- unsigned char IRRXINV : 1;\r
- unsigned char IRTXINV : 1;\r
- unsigned char IRCKS : 3;\r
- unsigned char IRE : 1;\r
-#else\r
- unsigned char IRE : 1;\r
- unsigned char IRCKS : 3;\r
- unsigned char IRTXINV : 1;\r
- unsigned char IRRXINV : 1;\r
- unsigned char : 2;\r
-#endif\r
- } BIT;\r
- } IRCR;\r
-};\r
-\r
-struct st_iwdt {\r
- unsigned char IWDTRR;\r
- char wk0[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short TOPS : 2;\r
- unsigned short : 2;\r
- unsigned short CKS : 4;\r
- unsigned short RPES : 2;\r
- unsigned short : 2;\r
- unsigned short RPSS : 2;\r
- unsigned short : 2;\r
-#else\r
- unsigned short : 2;\r
- unsigned short RPSS : 2;\r
- unsigned short : 2;\r
- unsigned short RPES : 2;\r
- unsigned short CKS : 4;\r
- unsigned short : 2;\r
- unsigned short TOPS : 2;\r
-#endif\r
- } BIT;\r
- } IWDTCR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CNTVAL : 14;\r
- unsigned short UNDFF : 1;\r
- unsigned short REFEF : 1;\r
-#else\r
- unsigned short REFEF : 1;\r
- unsigned short UNDFF : 1;\r
- unsigned short CNTVAL : 14;\r
-#endif\r
- } BIT;\r
- } IWDTSR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char RSTIRQS : 1;\r
-#else\r
- unsigned char RSTIRQS : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } IWDTRCR;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char SLCSTP : 1;\r
-#else\r
- unsigned char SLCSTP : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } IWDTCSTPR;\r
-};\r
-\r
-struct st_lcdc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LBAS : 2;\r
- unsigned char LDTY : 3;\r
- unsigned char LWAVE : 1;\r
- unsigned char MDSET : 2;\r
-#else\r
- unsigned char MDSET : 2;\r
- unsigned char LWAVE : 1;\r
- unsigned char LDTY : 3;\r
- unsigned char LBAS : 2;\r
-#endif\r
- } BIT;\r
- } LCDM0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LCDVLM : 1;\r
- unsigned char : 2;\r
- unsigned char LCDSEL : 1;\r
- unsigned char BLON : 1;\r
- unsigned char VLCON : 1;\r
- unsigned char SCOC : 1;\r
- unsigned char LCDON : 1;\r
-#else\r
- unsigned char LCDON : 1;\r
- unsigned char SCOC : 1;\r
- unsigned char VLCON : 1;\r
- unsigned char BLON : 1;\r
- unsigned char LCDSEL : 1;\r
- unsigned char : 2;\r
- unsigned char LCDVLM : 1;\r
-#endif\r
- } BIT;\r
- } LCDM1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LCDC0 : 6;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char LCDC0 : 6;\r
-#endif\r
- } BIT;\r
- } LCDC0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char VLCD : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char VLCD : 5;\r
-#endif\r
- } BIT;\r
- } VLCD;\r
- char wk0[60];\r
- unsigned char SEG00;\r
- unsigned char SEG01;\r
- unsigned char SEG02;\r
- unsigned char SEG03;\r
- unsigned char SEG04;\r
- unsigned char SEG05;\r
- unsigned char SEG06;\r
- unsigned char SEG07;\r
- unsigned char SEG08;\r
- unsigned char SEG09;\r
- unsigned char SEG10;\r
- unsigned char SEG11;\r
- unsigned char SEG12;\r
- unsigned char SEG13;\r
- unsigned char SEG14;\r
- unsigned char SEG15;\r
- unsigned char SEG16;\r
- unsigned char SEG17;\r
- unsigned char SEG18;\r
- unsigned char SEG19;\r
- unsigned char SEG20;\r
- unsigned char SEG21;\r
- unsigned char SEG22;\r
- unsigned char SEG23;\r
- unsigned char SEG24;\r
- unsigned char SEG25;\r
- unsigned char SEG26;\r
- unsigned char SEG27;\r
- unsigned char SEG28;\r
- unsigned char SEG29;\r
- unsigned char SEG30;\r
- unsigned char SEG31;\r
- unsigned char SEG32;\r
- unsigned char SEG33;\r
- unsigned char SEG34;\r
- unsigned char SEG35;\r
- unsigned char SEG36;\r
- unsigned char SEG37;\r
- unsigned char SEG38;\r
- unsigned char SEG39;\r
-};\r
-\r
-struct st_lpt {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LPCNTPSSEL : 3;\r
- unsigned char : 1;\r
- unsigned char LPCNTCKSEL : 1;\r
- unsigned char : 1;\r
- unsigned char LPCMRE0 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char LPCMRE0 : 1;\r
- unsigned char : 1;\r
- unsigned char LPCNTCKSEL : 1;\r
- unsigned char : 1;\r
- unsigned char LPCNTPSSEL : 3;\r
-#endif\r
- } BIT;\r
- } LPTCR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LPCNTSTP : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char LPCNTSTP : 1;\r
-#endif\r
- } BIT;\r
- } LPTCR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LPCNTEN : 1;\r
- unsigned char LPCNTRST : 1;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char LPCNTRST : 1;\r
- unsigned char LPCNTEN : 1;\r
-#endif\r
- } BIT;\r
- } LPTCR3;\r
- char wk0[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short LPCNTPRD : 16;\r
-#else\r
- unsigned short LPCNTPRD : 16;\r
-#endif\r
- } BIT;\r
- } LPTPRD;\r
- char wk1[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short LPCMR0 : 16;\r
-#else\r
- unsigned short LPCMR0 : 16;\r
-#endif\r
- } BIT;\r
- } LPCMR0;\r
- char wk2[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 15;\r
- unsigned short LPWKUPEN : 1;\r
-#else\r
- unsigned short LPWKUPEN : 1;\r
- unsigned short : 15;\r
-#endif\r
- } BIT;\r
- } LPWUCR;\r
-};\r
-\r
-struct st_mpc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 6;\r
- unsigned char PFSWE : 1;\r
- unsigned char B0WI : 1;\r
-#else\r
- unsigned char B0WI : 1;\r
- unsigned char PFSWE : 1;\r
- unsigned char : 6;\r
-#endif\r
- } BIT;\r
- } PWPR;\r
- char wk0[34];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P02PFS;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P04PFS;\r
- char wk2[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P07PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P10PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P11PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P12PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P13PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P14PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P15PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P16PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P17PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P20PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P21PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P22PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P23PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P24PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P25PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P26PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P27PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P30PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P31PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P32PFS;\r
- char wk3[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 6;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 6;\r
-#endif\r
- } BIT;\r
- } P35PFS;\r
- char wk4[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } P40PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } P41PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } P42PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } P43PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } P44PFS;\r
- char wk5[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } P46PFS;\r
- char wk6[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P50PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P51PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P52PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P53PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P54PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P55PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } P56PFS;\r
- char wk7[25];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } P90PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } P91PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } P92PFS;\r
- char wk8[5];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PA0PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PA1PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PA2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PA3PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PA4PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PA5PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PA6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PA7PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PB0PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PB1PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PB2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PB3PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PB4PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PB5PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PB6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PB7PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PC0PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PC1PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PC2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PC3PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PC4PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PC5PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PC6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PC7PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PD0PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PD1PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PD2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PD3PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PD4PFS;\r
- char wk9[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PE0PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PE1PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PE2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PE3PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PE4PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PE5PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PE6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char ISEL : 1;\r
- unsigned char : 1;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PE7PFS;\r
- char wk10[6];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PF6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PF7PFS;\r
- char wk11[16];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } PJ0PFS;\r
- char wk12[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } PJ2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PSEL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char PSEL : 5;\r
-#endif\r
- } BIT;\r
- } PJ3PFS;\r
- char wk13[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } PJ6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ASEL : 1;\r
-#else\r
- unsigned char ASEL : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } PJ7PFS;\r
-};\r
-\r
-struct st_mtu {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char OE3B : 1;\r
- unsigned char OE4A : 1;\r
- unsigned char OE4B : 1;\r
- unsigned char OE3D : 1;\r
- unsigned char OE4C : 1;\r
- unsigned char OE4D : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char OE4D : 1;\r
- unsigned char OE4C : 1;\r
- unsigned char OE3D : 1;\r
- unsigned char OE4B : 1;\r
- unsigned char OE4A : 1;\r
- unsigned char OE3B : 1;\r
-#endif\r
- } BIT;\r
- } TOER;\r
- char wk0[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char UF : 1;\r
- unsigned char VF : 1;\r
- unsigned char WF : 1;\r
- unsigned char FB : 1;\r
- unsigned char P : 1;\r
- unsigned char N : 1;\r
- unsigned char BDC : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char BDC : 1;\r
- unsigned char N : 1;\r
- unsigned char P : 1;\r
- unsigned char FB : 1;\r
- unsigned char WF : 1;\r
- unsigned char VF : 1;\r
- unsigned char UF : 1;\r
-#endif\r
- } BIT;\r
- } TGCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char OLSP : 1;\r
- unsigned char OLSN : 1;\r
- unsigned char TOCS : 1;\r
- unsigned char TOCL : 1;\r
- unsigned char : 2;\r
- unsigned char PSYE : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char PSYE : 1;\r
- unsigned char : 2;\r
- unsigned char TOCL : 1;\r
- unsigned char TOCS : 1;\r
- unsigned char OLSN : 1;\r
- unsigned char OLSP : 1;\r
-#endif\r
- } BIT;\r
- } TOCR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char OLS1P : 1;\r
- unsigned char OLS1N : 1;\r
- unsigned char OLS2P : 1;\r
- unsigned char OLS2N : 1;\r
- unsigned char OLS3P : 1;\r
- unsigned char OLS3N : 1;\r
- unsigned char BF : 2;\r
-#else\r
- unsigned char BF : 2;\r
- unsigned char OLS3N : 1;\r
- unsigned char OLS3P : 1;\r
- unsigned char OLS2N : 1;\r
- unsigned char OLS2P : 1;\r
- unsigned char OLS1N : 1;\r
- unsigned char OLS1P : 1;\r
-#endif\r
- } BIT;\r
- } TOCR2;\r
- char wk1[4];\r
- unsigned short TCDR;\r
- unsigned short TDDR;\r
- char wk2[8];\r
- unsigned short TCNTS;\r
- unsigned short TCBR;\r
- char wk3[12];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char T4VCOR : 3;\r
- unsigned char T4VEN : 1;\r
- unsigned char T3ACOR : 3;\r
- unsigned char T3AEN : 1;\r
-#else\r
- unsigned char T3AEN : 1;\r
- unsigned char T3ACOR : 3;\r
- unsigned char T4VEN : 1;\r
- unsigned char T4VCOR : 3;\r
-#endif\r
- } BIT;\r
- } TITCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char T4VCNT : 3;\r
- unsigned char : 1;\r
- unsigned char T3ACNT : 3;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char T3ACNT : 3;\r
- unsigned char : 1;\r
- unsigned char T4VCNT : 3;\r
-#endif\r
- } BIT;\r
- } TITCNT;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BTE : 2;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char BTE : 2;\r
-#endif\r
- } BIT;\r
- } TBTER;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TDER : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char TDER : 1;\r
-#endif\r
- } BIT;\r
- } TDER;\r
- char wk5[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char OLS1P : 1;\r
- unsigned char OLS1N : 1;\r
- unsigned char OLS2P : 1;\r
- unsigned char OLS2N : 1;\r
- unsigned char OLS3P : 1;\r
- unsigned char OLS3N : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char OLS3N : 1;\r
- unsigned char OLS3P : 1;\r
- unsigned char OLS2N : 1;\r
- unsigned char OLS2P : 1;\r
- unsigned char OLS1N : 1;\r
- unsigned char OLS1P : 1;\r
-#endif\r
- } BIT;\r
- } TOLBR;\r
- char wk6[41];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char WRE : 1;\r
- unsigned char : 6;\r
- unsigned char CCE : 1;\r
-#else\r
- unsigned char CCE : 1;\r
- unsigned char : 6;\r
- unsigned char WRE : 1;\r
-#endif\r
- } BIT;\r
- } TWCR;\r
- char wk7[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CST0 : 1;\r
- unsigned char CST1 : 1;\r
- unsigned char CST2 : 1;\r
- unsigned char : 3;\r
- unsigned char CST3 : 1;\r
- unsigned char CST4 : 1;\r
-#else\r
- unsigned char CST4 : 1;\r
- unsigned char CST3 : 1;\r
- unsigned char : 3;\r
- unsigned char CST2 : 1;\r
- unsigned char CST1 : 1;\r
- unsigned char CST0 : 1;\r
-#endif\r
- } BIT;\r
- } TSTR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SYNC0 : 1;\r
- unsigned char SYNC1 : 1;\r
- unsigned char SYNC2 : 1;\r
- unsigned char : 3;\r
- unsigned char SYNC3 : 1;\r
- unsigned char SYNC4 : 1;\r
-#else\r
- unsigned char SYNC4 : 1;\r
- unsigned char SYNC3 : 1;\r
- unsigned char : 3;\r
- unsigned char SYNC2 : 1;\r
- unsigned char SYNC1 : 1;\r
- unsigned char SYNC0 : 1;\r
-#endif\r
- } BIT;\r
- } TSYR;\r
- char wk8[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char RWE : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char RWE : 1;\r
-#endif\r
- } BIT;\r
- } TRWER;\r
-};\r
-\r
-struct st_mtu0 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NFAEN : 1;\r
- unsigned char NFBEN : 1;\r
- unsigned char NFCEN : 1;\r
- unsigned char NFDEN : 1;\r
- unsigned char NFCS : 2;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char NFCS : 2;\r
- unsigned char NFDEN : 1;\r
- unsigned char NFCEN : 1;\r
- unsigned char NFBEN : 1;\r
- unsigned char NFAEN : 1;\r
-#endif\r
- } BIT;\r
- } NFCR;\r
- char wk0[111];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TPSC : 3;\r
- unsigned char CKEG : 2;\r
- unsigned char CCLR : 3;\r
-#else\r
- unsigned char CCLR : 3;\r
- unsigned char CKEG : 2;\r
- unsigned char TPSC : 3;\r
-#endif\r
- } BIT;\r
- } TCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MD : 4;\r
- unsigned char BFA : 1;\r
- unsigned char BFB : 1;\r
- unsigned char BFE : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char BFE : 1;\r
- unsigned char BFB : 1;\r
- unsigned char BFA : 1;\r
- unsigned char MD : 4;\r
-#endif\r
- } BIT;\r
- } TMDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IOA : 4;\r
- unsigned char IOB : 4;\r
-#else\r
- unsigned char IOB : 4;\r
- unsigned char IOA : 4;\r
-#endif\r
- } BIT;\r
- } TIORH;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IOC : 4;\r
- unsigned char IOD : 4;\r
-#else\r
- unsigned char IOD : 4;\r
- unsigned char IOC : 4;\r
-#endif\r
- } BIT;\r
- } TIORL;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TGIEA : 1;\r
- unsigned char TGIEB : 1;\r
- unsigned char TGIEC : 1;\r
- unsigned char TGIED : 1;\r
- unsigned char TCIEV : 1;\r
- unsigned char : 2;\r
- unsigned char TTGE : 1;\r
-#else\r
- unsigned char TTGE : 1;\r
- unsigned char : 2;\r
- unsigned char TCIEV : 1;\r
- unsigned char TGIED : 1;\r
- unsigned char TGIEC : 1;\r
- unsigned char TGIEB : 1;\r
- unsigned char TGIEA : 1;\r
-#endif\r
- } BIT;\r
- } TIER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char TCFD : 1;\r
-#else\r
- unsigned char TCFD : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } TSR;\r
- unsigned short TCNT;\r
- unsigned short TGRA;\r
- unsigned short TGRB;\r
- unsigned short TGRC;\r
- unsigned short TGRD;\r
- char wk1[16];\r
- unsigned short TGRE;\r
- unsigned short TGRF;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TGIEE : 1;\r
- unsigned char TGIEF : 1;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char TGIEF : 1;\r
- unsigned char TGIEE : 1;\r
-#endif\r
- } BIT;\r
- } TIER2;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TTSA : 1;\r
- unsigned char TTSB : 1;\r
- unsigned char TTSE : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char TTSE : 1;\r
- unsigned char TTSB : 1;\r
- unsigned char TTSA : 1;\r
-#endif\r
- } BIT;\r
- } TBTM;\r
-};\r
-\r
-struct st_mtu1 {\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NFAEN : 1;\r
- unsigned char NFBEN : 1;\r
- unsigned char NFCEN : 1;\r
- unsigned char NFDEN : 1;\r
- unsigned char NFCS : 2;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char NFCS : 2;\r
- unsigned char NFDEN : 1;\r
- unsigned char NFCEN : 1;\r
- unsigned char NFBEN : 1;\r
- unsigned char NFAEN : 1;\r
-#endif\r
- } BIT;\r
- } NFCR;\r
- char wk1[238];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TPSC : 3;\r
- unsigned char CKEG : 2;\r
- unsigned char CCLR : 2;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char CCLR : 2;\r
- unsigned char CKEG : 2;\r
- unsigned char TPSC : 3;\r
-#endif\r
- } BIT;\r
- } TCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MD : 4;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char MD : 4;\r
-#endif\r
- } BIT;\r
- } TMDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IOA : 4;\r
- unsigned char IOB : 4;\r
-#else\r
- unsigned char IOB : 4;\r
- unsigned char IOA : 4;\r
-#endif\r
- } BIT;\r
- } TIOR;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TGIEA : 1;\r
- unsigned char TGIEB : 1;\r
- unsigned char : 2;\r
- unsigned char TCIEV : 1;\r
- unsigned char TCIEU : 1;\r
- unsigned char : 1;\r
- unsigned char TTGE : 1;\r
-#else\r
- unsigned char TTGE : 1;\r
- unsigned char : 1;\r
- unsigned char TCIEU : 1;\r
- unsigned char TCIEV : 1;\r
- unsigned char : 2;\r
- unsigned char TGIEB : 1;\r
- unsigned char TGIEA : 1;\r
-#endif\r
- } BIT;\r
- } TIER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char TCFD : 1;\r
-#else\r
- unsigned char TCFD : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } TSR;\r
- unsigned short TCNT;\r
- unsigned short TGRA;\r
- unsigned short TGRB;\r
- char wk3[4];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char I1AE : 1;\r
- unsigned char I1BE : 1;\r
- unsigned char I2AE : 1;\r
- unsigned char I2BE : 1;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char I2BE : 1;\r
- unsigned char I2AE : 1;\r
- unsigned char I1BE : 1;\r
- unsigned char I1AE : 1;\r
-#endif\r
- } BIT;\r
- } TICCR;\r
-};\r
-\r
-struct st_mtu2 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NFAEN : 1;\r
- unsigned char NFBEN : 1;\r
- unsigned char NFCEN : 1;\r
- unsigned char NFDEN : 1;\r
- unsigned char NFCS : 2;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char NFCS : 2;\r
- unsigned char NFDEN : 1;\r
- unsigned char NFCEN : 1;\r
- unsigned char NFBEN : 1;\r
- unsigned char NFAEN : 1;\r
-#endif\r
- } BIT;\r
- } NFCR;\r
- char wk0[365];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TPSC : 3;\r
- unsigned char CKEG : 2;\r
- unsigned char CCLR : 2;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char CCLR : 2;\r
- unsigned char CKEG : 2;\r
- unsigned char TPSC : 3;\r
-#endif\r
- } BIT;\r
- } TCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MD : 4;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char MD : 4;\r
-#endif\r
- } BIT;\r
- } TMDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IOA : 4;\r
- unsigned char IOB : 4;\r
-#else\r
- unsigned char IOB : 4;\r
- unsigned char IOA : 4;\r
-#endif\r
- } BIT;\r
- } TIOR;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TGIEA : 1;\r
- unsigned char TGIEB : 1;\r
- unsigned char : 2;\r
- unsigned char TCIEV : 1;\r
- unsigned char TCIEU : 1;\r
- unsigned char : 1;\r
- unsigned char TTGE : 1;\r
-#else\r
- unsigned char TTGE : 1;\r
- unsigned char : 1;\r
- unsigned char TCIEU : 1;\r
- unsigned char TCIEV : 1;\r
- unsigned char : 2;\r
- unsigned char TGIEB : 1;\r
- unsigned char TGIEA : 1;\r
-#endif\r
- } BIT;\r
- } TIER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char TCFD : 1;\r
-#else\r
- unsigned char TCFD : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } TSR;\r
- unsigned short TCNT;\r
- unsigned short TGRA;\r
- unsigned short TGRB;\r
-};\r
-\r
-struct st_mtu3 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TPSC : 3;\r
- unsigned char CKEG : 2;\r
- unsigned char CCLR : 3;\r
-#else\r
- unsigned char CCLR : 3;\r
- unsigned char CKEG : 2;\r
- unsigned char TPSC : 3;\r
-#endif\r
- } BIT;\r
- } TCR;\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MD : 4;\r
- unsigned char BFA : 1;\r
- unsigned char BFB : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char BFB : 1;\r
- unsigned char BFA : 1;\r
- unsigned char MD : 4;\r
-#endif\r
- } BIT;\r
- } TMDR;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IOA : 4;\r
- unsigned char IOB : 4;\r
-#else\r
- unsigned char IOB : 4;\r
- unsigned char IOA : 4;\r
-#endif\r
- } BIT;\r
- } TIORH;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IOC : 4;\r
- unsigned char IOD : 4;\r
-#else\r
- unsigned char IOD : 4;\r
- unsigned char IOC : 4;\r
-#endif\r
- } BIT;\r
- } TIORL;\r
- char wk2[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TGIEA : 1;\r
- unsigned char TGIEB : 1;\r
- unsigned char TGIEC : 1;\r
- unsigned char TGIED : 1;\r
- unsigned char TCIEV : 1;\r
- unsigned char : 2;\r
- unsigned char TTGE : 1;\r
-#else\r
- unsigned char TTGE : 1;\r
- unsigned char : 2;\r
- unsigned char TCIEV : 1;\r
- unsigned char TGIED : 1;\r
- unsigned char TGIEC : 1;\r
- unsigned char TGIEB : 1;\r
- unsigned char TGIEA : 1;\r
-#endif\r
- } BIT;\r
- } TIER;\r
- char wk3[7];\r
- unsigned short TCNT;\r
- char wk4[6];\r
- unsigned short TGRA;\r
- unsigned short TGRB;\r
- char wk5[8];\r
- unsigned short TGRC;\r
- unsigned short TGRD;\r
- char wk6[4];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char TCFD : 1;\r
-#else\r
- unsigned char TCFD : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } TSR;\r
- char wk7[11];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TTSA : 1;\r
- unsigned char TTSB : 1;\r
- unsigned char TTSE : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char TTSE : 1;\r
- unsigned char TTSB : 1;\r
- unsigned char TTSA : 1;\r
-#endif\r
- } BIT;\r
- } TBTM;\r
- char wk8[90];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NFAEN : 1;\r
- unsigned char NFBEN : 1;\r
- unsigned char NFCEN : 1;\r
- unsigned char NFDEN : 1;\r
- unsigned char NFCS : 2;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char NFCS : 2;\r
- unsigned char NFDEN : 1;\r
- unsigned char NFCEN : 1;\r
- unsigned char NFBEN : 1;\r
- unsigned char NFAEN : 1;\r
-#endif\r
- } BIT;\r
- } NFCR;\r
-};\r
-\r
-struct st_mtu4 {\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TPSC : 3;\r
- unsigned char CKEG : 2;\r
- unsigned char CCLR : 3;\r
-#else\r
- unsigned char CCLR : 3;\r
- unsigned char CKEG : 2;\r
- unsigned char TPSC : 3;\r
-#endif\r
- } BIT;\r
- } TCR;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MD : 4;\r
- unsigned char BFA : 1;\r
- unsigned char BFB : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char BFB : 1;\r
- unsigned char BFA : 1;\r
- unsigned char MD : 4;\r
-#endif\r
- } BIT;\r
- } TMDR;\r
- char wk2[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IOA : 4;\r
- unsigned char IOB : 4;\r
-#else\r
- unsigned char IOB : 4;\r
- unsigned char IOA : 4;\r
-#endif\r
- } BIT;\r
- } TIORH;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IOC : 4;\r
- unsigned char IOD : 4;\r
-#else\r
- unsigned char IOD : 4;\r
- unsigned char IOC : 4;\r
-#endif\r
- } BIT;\r
- } TIORL;\r
- char wk3[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TGIEA : 1;\r
- unsigned char TGIEB : 1;\r
- unsigned char TGIEC : 1;\r
- unsigned char TGIED : 1;\r
- unsigned char TCIEV : 1;\r
- unsigned char : 1;\r
- unsigned char TTGE2 : 1;\r
- unsigned char TTGE : 1;\r
-#else\r
- unsigned char TTGE : 1;\r
- unsigned char TTGE2 : 1;\r
- unsigned char : 1;\r
- unsigned char TCIEV : 1;\r
- unsigned char TGIED : 1;\r
- unsigned char TGIEC : 1;\r
- unsigned char TGIEB : 1;\r
- unsigned char TGIEA : 1;\r
-#endif\r
- } BIT;\r
- } TIER;\r
- char wk4[8];\r
- unsigned short TCNT;\r
- char wk5[8];\r
- unsigned short TGRA;\r
- unsigned short TGRB;\r
- char wk6[8];\r
- unsigned short TGRC;\r
- unsigned short TGRD;\r
- char wk7[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char TCFD : 1;\r
-#else\r
- unsigned char TCFD : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } TSR;\r
- char wk8[11];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TTSA : 1;\r
- unsigned char TTSB : 1;\r
- unsigned char TTSE : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char TTSE : 1;\r
- unsigned char TTSB : 1;\r
- unsigned char TTSA : 1;\r
-#endif\r
- } BIT;\r
- } TBTM;\r
- char wk9[6];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short ITB4VE : 1;\r
- unsigned short ITB3AE : 1;\r
- unsigned short ITA4VE : 1;\r
- unsigned short ITA3AE : 1;\r
- unsigned short DT4BE : 1;\r
- unsigned short UT4BE : 1;\r
- unsigned short DT4AE : 1;\r
- unsigned short UT4AE : 1;\r
- unsigned short : 6;\r
- unsigned short BF : 2;\r
-#else\r
- unsigned short BF : 2;\r
- unsigned short : 6;\r
- unsigned short UT4AE : 1;\r
- unsigned short DT4AE : 1;\r
- unsigned short UT4BE : 1;\r
- unsigned short DT4BE : 1;\r
- unsigned short ITA3AE : 1;\r
- unsigned short ITA4VE : 1;\r
- unsigned short ITB3AE : 1;\r
- unsigned short ITB4VE : 1;\r
-#endif\r
- } BIT;\r
- } TADCR;\r
- char wk10[2];\r
- unsigned short TADCORA;\r
- unsigned short TADCORB;\r
- unsigned short TADCOBRA;\r
- unsigned short TADCOBRB;\r
- char wk11[72];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NFAEN : 1;\r
- unsigned char NFBEN : 1;\r
- unsigned char NFCEN : 1;\r
- unsigned char NFDEN : 1;\r
- unsigned char NFCS : 2;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char NFCS : 2;\r
- unsigned char NFDEN : 1;\r
- unsigned char NFCEN : 1;\r
- unsigned char NFBEN : 1;\r
- unsigned char NFAEN : 1;\r
-#endif\r
- } BIT;\r
- } NFCR;\r
-};\r
-\r
-struct st_mtu5 {\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NFUEN : 1;\r
- unsigned char NFVEN : 1;\r
- unsigned char NFWEN : 1;\r
- unsigned char : 1;\r
- unsigned char NFCS : 2;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char NFCS : 2;\r
- unsigned char : 1;\r
- unsigned char NFWEN : 1;\r
- unsigned char NFVEN : 1;\r
- unsigned char NFUEN : 1;\r
-#endif\r
- } BIT;\r
- } NFCR;\r
- char wk1[490];\r
- unsigned short TCNTU;\r
- unsigned short TGRU;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TPSC : 2;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char TPSC : 2;\r
-#endif\r
- } BIT;\r
- } TCRU;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IOC : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char IOC : 5;\r
-#endif\r
- } BIT;\r
- } TIORU;\r
- char wk3[9];\r
- unsigned short TCNTV;\r
- unsigned short TGRV;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TPSC : 2;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char TPSC : 2;\r
-#endif\r
- } BIT;\r
- } TCRV;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IOC : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char IOC : 5;\r
-#endif\r
- } BIT;\r
- } TIORV;\r
- char wk5[9];\r
- unsigned short TCNTW;\r
- unsigned short TGRW;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TPSC : 2;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char TPSC : 2;\r
-#endif\r
- } BIT;\r
- } TCRW;\r
- char wk6[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IOC : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char IOC : 5;\r
-#endif\r
- } BIT;\r
- } TIORW;\r
- char wk7[11];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TGIE5W : 1;\r
- unsigned char TGIE5V : 1;\r
- unsigned char TGIE5U : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char TGIE5U : 1;\r
- unsigned char TGIE5V : 1;\r
- unsigned char TGIE5W : 1;\r
-#endif\r
- } BIT;\r
- } TIER;\r
- char wk8[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CSTW5 : 1;\r
- unsigned char CSTV5 : 1;\r
- unsigned char CSTU5 : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char CSTU5 : 1;\r
- unsigned char CSTV5 : 1;\r
- unsigned char CSTW5 : 1;\r
-#endif\r
- } BIT;\r
- } TSTR;\r
- char wk9[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CMPCLR5W : 1;\r
- unsigned char CMPCLR5V : 1;\r
- unsigned char CMPCLR5U : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char CMPCLR5U : 1;\r
- unsigned char CMPCLR5V : 1;\r
- unsigned char CMPCLR5W : 1;\r
-#endif\r
- } BIT;\r
- } TCNTCMPCLR;\r
-};\r
-\r
-struct st_poe {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char H;\r
- unsigned char L;\r
- } BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short POE0M : 2;\r
- unsigned short POE1M : 2;\r
- unsigned short POE2M : 2;\r
- unsigned short POE3M : 2;\r
- unsigned short PIE1 : 1;\r
- unsigned short : 3;\r
- unsigned short POE0F : 1;\r
- unsigned short POE1F : 1;\r
- unsigned short POE2F : 1;\r
- unsigned short POE3F : 1;\r
-#else\r
- unsigned short POE3F : 1;\r
- unsigned short POE2F : 1;\r
- unsigned short POE1F : 1;\r
- unsigned short POE0F : 1;\r
- unsigned short : 3;\r
- unsigned short PIE1 : 1;\r
- unsigned short POE3M : 2;\r
- unsigned short POE2M : 2;\r
- unsigned short POE1M : 2;\r
- unsigned short POE0M : 2;\r
-#endif\r
- } BIT;\r
- } ICSR1;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char H;\r
- unsigned char L;\r
- } BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 8;\r
- unsigned short OIE1 : 1;\r
- unsigned short OCE1 : 1;\r
- unsigned short : 5;\r
- unsigned short OSF1 : 1;\r
-#else\r
- unsigned short OSF1 : 1;\r
- unsigned short : 5;\r
- unsigned short OCE1 : 1;\r
- unsigned short OIE1 : 1;\r
- unsigned short : 8;\r
-#endif\r
- } BIT;\r
- } OCSR1;\r
- char wk0[4];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char H;\r
- unsigned char L;\r
- } BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short POE8M : 2;\r
- unsigned short : 6;\r
- unsigned short PIE2 : 1;\r
- unsigned short POE8E : 1;\r
- unsigned short : 2;\r
- unsigned short POE8F : 1;\r
- unsigned short : 3;\r
-#else\r
- unsigned short : 3;\r
- unsigned short POE8F : 1;\r
- unsigned short : 2;\r
- unsigned short POE8E : 1;\r
- unsigned short PIE2 : 1;\r
- unsigned short : 6;\r
- unsigned short POE8M : 2;\r
-#endif\r
- } BIT;\r
- } ICSR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CH34HIZ : 1;\r
- unsigned char CH0HIZ : 1;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char CH0HIZ : 1;\r
- unsigned char CH34HIZ : 1;\r
-#endif\r
- } BIT;\r
- } SPOER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PE0ZE : 1;\r
- unsigned char PE1ZE : 1;\r
- unsigned char PE2ZE : 1;\r
- unsigned char PE3ZE : 1;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char PE3ZE : 1;\r
- unsigned char PE2ZE : 1;\r
- unsigned char PE1ZE : 1;\r
- unsigned char PE0ZE : 1;\r
-#endif\r
- } BIT;\r
- } POECR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 4;\r
- unsigned char P3CZEA : 1;\r
- unsigned char P2CZEA : 1;\r
- unsigned char P1CZEA : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char P1CZEA : 1;\r
- unsigned char P2CZEA : 1;\r
- unsigned char P3CZEA : 1;\r
- unsigned char : 4;\r
-#endif\r
- } BIT;\r
- } POECR2;\r
- char wk1[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char H;\r
- unsigned char L;\r
- } BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 9;\r
- unsigned short OSTSTE : 1;\r
- unsigned short : 2;\r
- unsigned short OSTSTF : 1;\r
- unsigned short : 3;\r
-#else\r
- unsigned short : 3;\r
- unsigned short OSTSTF : 1;\r
- unsigned short : 2;\r
- unsigned short OSTSTE : 1;\r
- unsigned short : 9;\r
-#endif\r
- } BIT;\r
- } ICSR3;\r
-};\r
-\r
-struct st_port {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 6;\r
- unsigned char PSEL6 : 1;\r
- unsigned char PSEL7 : 1;\r
-#else\r
- unsigned char PSEL7 : 1;\r
- unsigned char PSEL6 : 1;\r
- unsigned char : 6;\r
-#endif\r
- } BIT;\r
- } PSRA;\r
-};\r
-\r
-struct st_port0 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 2;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 2;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char : 2;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 2;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 2;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 2;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char : 2;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 2;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 2;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 2;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char : 2;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 2;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 2;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 2;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char : 2;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 2;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 4;\r
- unsigned char B4 : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char B4 : 1;\r
- unsigned char : 4;\r
-#endif\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 5;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 5;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR1;\r
- char wk4[62];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 2;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 2;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char : 2;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 2;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_port1 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[32];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR1;\r
- char wk4[61];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_port2 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[33];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR1;\r
- char wk4[60];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_port3 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 2;\r
- unsigned char B5 : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char B5 : 1;\r
- unsigned char : 2;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[34];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR0;\r
- char wk4[60];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_port4 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
-};\r
-\r
-struct st_port5 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[36];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 4;\r
- unsigned char B4 : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char B4 : 1;\r
- unsigned char : 4;\r
-#endif\r
- } BIT;\r
- } ODR1;\r
- char wk4[57];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_port9 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
-};\r
-\r
-struct st_porta {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[41];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR1;\r
- char wk4[52];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_portb {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[42];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR1;\r
- char wk4[51];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_portc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[43];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR1;\r
- char wk4[50];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_portd {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[95];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_porte {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[45];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
- unsigned char B4 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } ODR1;\r
- char wk4[48];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char B5 : 1;\r
- unsigned char B4 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B1 : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_portf {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 6;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 6;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 6;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 6;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 6;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 6;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 6;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 6;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[95];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 6;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 6;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_porth {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } PMR;\r
-};\r
-\r
-struct st_portj {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char : 2;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 2;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char : 2;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 2;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char : 2;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 2;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char : 2;\r
- unsigned char B6 : 1;\r
- unsigned char B7 : 1;\r
-#else\r
- unsigned char B7 : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 2;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PMR;\r
- char wk3[49];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 6;\r
- unsigned char B6 : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char B6 : 1;\r
- unsigned char : 6;\r
-#endif\r
- } BIT;\r
- } ODR0;\r
- char wk4[45];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char B0 : 1;\r
- unsigned char : 1;\r
- unsigned char B2 : 1;\r
- unsigned char B3 : 1;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char B3 : 1;\r
- unsigned char B2 : 1;\r
- unsigned char : 1;\r
- unsigned char B0 : 1;\r
-#endif\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_riic {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SDAI : 1;\r
- unsigned char SCLI : 1;\r
- unsigned char SDAO : 1;\r
- unsigned char SCLO : 1;\r
- unsigned char SOWP : 1;\r
- unsigned char CLO : 1;\r
- unsigned char IICRST : 1;\r
- unsigned char ICE : 1;\r
-#else\r
- unsigned char ICE : 1;\r
- unsigned char IICRST : 1;\r
- unsigned char CLO : 1;\r
- unsigned char SOWP : 1;\r
- unsigned char SCLO : 1;\r
- unsigned char SDAO : 1;\r
- unsigned char SCLI : 1;\r
- unsigned char SDAI : 1;\r
-#endif\r
- } BIT;\r
- } ICCR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 1;\r
- unsigned char ST : 1;\r
- unsigned char RS : 1;\r
- unsigned char SP : 1;\r
- unsigned char : 1;\r
- unsigned char TRS : 1;\r
- unsigned char MST : 1;\r
- unsigned char BBSY : 1;\r
-#else\r
- unsigned char BBSY : 1;\r
- unsigned char MST : 1;\r
- unsigned char TRS : 1;\r
- unsigned char : 1;\r
- unsigned char SP : 1;\r
- unsigned char RS : 1;\r
- unsigned char ST : 1;\r
- unsigned char : 1;\r
-#endif\r
- } BIT;\r
- } ICCR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BC : 3;\r
- unsigned char BCWP : 1;\r
- unsigned char CKS : 3;\r
- unsigned char MTWP : 1;\r
-#else\r
- unsigned char MTWP : 1;\r
- unsigned char CKS : 3;\r
- unsigned char BCWP : 1;\r
- unsigned char BC : 3;\r
-#endif\r
- } BIT;\r
- } ICMR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TMOS : 1;\r
- unsigned char TMOL : 1;\r
- unsigned char TMOH : 1;\r
- unsigned char TMWE : 1;\r
- unsigned char SDDL : 3;\r
- unsigned char DLCS : 1;\r
-#else\r
- unsigned char DLCS : 1;\r
- unsigned char SDDL : 3;\r
- unsigned char TMWE : 1;\r
- unsigned char TMOH : 1;\r
- unsigned char TMOL : 1;\r
- unsigned char TMOS : 1;\r
-#endif\r
- } BIT;\r
- } ICMR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NF : 2;\r
- unsigned char ACKBR : 1;\r
- unsigned char ACKBT : 1;\r
- unsigned char ACKWP : 1;\r
- unsigned char RDRFS : 1;\r
- unsigned char WAIT : 1;\r
- unsigned char SMBS : 1;\r
-#else\r
- unsigned char SMBS : 1;\r
- unsigned char WAIT : 1;\r
- unsigned char RDRFS : 1;\r
- unsigned char ACKWP : 1;\r
- unsigned char ACKBT : 1;\r
- unsigned char ACKBR : 1;\r
- unsigned char NF : 2;\r
-#endif\r
- } BIT;\r
- } ICMR3;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TMOE : 1;\r
- unsigned char MALE : 1;\r
- unsigned char NALE : 1;\r
- unsigned char SALE : 1;\r
- unsigned char NACKE : 1;\r
- unsigned char NFE : 1;\r
- unsigned char SCLE : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char SCLE : 1;\r
- unsigned char NFE : 1;\r
- unsigned char NACKE : 1;\r
- unsigned char SALE : 1;\r
- unsigned char NALE : 1;\r
- unsigned char MALE : 1;\r
- unsigned char TMOE : 1;\r
-#endif\r
- } BIT;\r
- } ICFER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SAR0E : 1;\r
- unsigned char SAR1E : 1;\r
- unsigned char SAR2E : 1;\r
- unsigned char GCAE : 1;\r
- unsigned char : 1;\r
- unsigned char DIDE : 1;\r
- unsigned char : 1;\r
- unsigned char HOAE : 1;\r
-#else\r
- unsigned char HOAE : 1;\r
- unsigned char : 1;\r
- unsigned char DIDE : 1;\r
- unsigned char : 1;\r
- unsigned char GCAE : 1;\r
- unsigned char SAR2E : 1;\r
- unsigned char SAR1E : 1;\r
- unsigned char SAR0E : 1;\r
-#endif\r
- } BIT;\r
- } ICSER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TMOIE : 1;\r
- unsigned char ALIE : 1;\r
- unsigned char STIE : 1;\r
- unsigned char SPIE : 1;\r
- unsigned char NAKIE : 1;\r
- unsigned char RIE : 1;\r
- unsigned char TEIE : 1;\r
- unsigned char TIE : 1;\r
-#else\r
- unsigned char TIE : 1;\r
- unsigned char TEIE : 1;\r
- unsigned char RIE : 1;\r
- unsigned char NAKIE : 1;\r
- unsigned char SPIE : 1;\r
- unsigned char STIE : 1;\r
- unsigned char ALIE : 1;\r
- unsigned char TMOIE : 1;\r
-#endif\r
- } BIT;\r
- } ICIER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char AAS0 : 1;\r
- unsigned char AAS1 : 1;\r
- unsigned char AAS2 : 1;\r
- unsigned char GCA : 1;\r
- unsigned char : 1;\r
- unsigned char DID : 1;\r
- unsigned char : 1;\r
- unsigned char HOA : 1;\r
-#else\r
- unsigned char HOA : 1;\r
- unsigned char : 1;\r
- unsigned char DID : 1;\r
- unsigned char : 1;\r
- unsigned char GCA : 1;\r
- unsigned char AAS2 : 1;\r
- unsigned char AAS1 : 1;\r
- unsigned char AAS0 : 1;\r
-#endif\r
- } BIT;\r
- } ICSR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TMOF : 1;\r
- unsigned char AL : 1;\r
- unsigned char START : 1;\r
- unsigned char STOP : 1;\r
- unsigned char NACKF : 1;\r
- unsigned char RDRF : 1;\r
- unsigned char TEND : 1;\r
- unsigned char TDRE : 1;\r
-#else\r
- unsigned char TDRE : 1;\r
- unsigned char TEND : 1;\r
- unsigned char RDRF : 1;\r
- unsigned char NACKF : 1;\r
- unsigned char STOP : 1;\r
- unsigned char START : 1;\r
- unsigned char AL : 1;\r
- unsigned char TMOF : 1;\r
-#endif\r
- } BIT;\r
- } ICSR2;\r
- union {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SVA0 : 1;\r
- unsigned char SVA : 7;\r
-#else\r
- unsigned char SVA : 7;\r
- unsigned char SVA0 : 1;\r
-#endif\r
- } BIT;\r
- } SARL0;\r
- union {\r
- unsigned char BYTE;\r
- } TMOCNTL;\r
- };\r
- union {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char FS : 1;\r
- unsigned char SVA : 2;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char SVA : 2;\r
- unsigned char FS : 1;\r
-#endif\r
- } BIT;\r
- } SARU0;\r
- union {\r
- unsigned char BYTE;\r
- } TMOCNTU;\r
- };\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SVA0 : 1;\r
- unsigned char SVA : 7;\r
-#else\r
- unsigned char SVA : 7;\r
- unsigned char SVA0 : 1;\r
-#endif\r
- } BIT;\r
- } SARL1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char FS : 1;\r
- unsigned char SVA : 2;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char SVA : 2;\r
- unsigned char FS : 1;\r
-#endif\r
- } BIT;\r
- } SARU1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SVA0 : 1;\r
- unsigned char SVA : 7;\r
-#else\r
- unsigned char SVA : 7;\r
- unsigned char SVA0 : 1;\r
-#endif\r
- } BIT;\r
- } SARL2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char FS : 1;\r
- unsigned char SVA : 2;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char SVA : 2;\r
- unsigned char FS : 1;\r
-#endif\r
- } BIT;\r
- } SARU2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BRL : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char BRL : 5;\r
-#endif\r
- } BIT;\r
- } ICBRL;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BRH : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char BRH : 5;\r
-#endif\r
- } BIT;\r
- } ICBRH;\r
- unsigned char ICDRT;\r
- unsigned char ICDRR;\r
-};\r
-\r
-struct st_rspi {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SPMS : 1;\r
- unsigned char TXMD : 1;\r
- unsigned char MODFEN : 1;\r
- unsigned char MSTR : 1;\r
- unsigned char SPEIE : 1;\r
- unsigned char SPTIE : 1;\r
- unsigned char SPE : 1;\r
- unsigned char SPRIE : 1;\r
-#else\r
- unsigned char SPRIE : 1;\r
- unsigned char SPE : 1;\r
- unsigned char SPTIE : 1;\r
- unsigned char SPEIE : 1;\r
- unsigned char MSTR : 1;\r
- unsigned char MODFEN : 1;\r
- unsigned char TXMD : 1;\r
- unsigned char SPMS : 1;\r
-#endif\r
- } BIT;\r
- } SPCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SSL0P : 1;\r
- unsigned char SSL1P : 1;\r
- unsigned char SSL2P : 1;\r
- unsigned char SSL3P : 1;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char SSL3P : 1;\r
- unsigned char SSL2P : 1;\r
- unsigned char SSL1P : 1;\r
- unsigned char SSL0P : 1;\r
-#endif\r
- } BIT;\r
- } SSLP;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SPLP : 1;\r
- unsigned char SPLP2 : 1;\r
- unsigned char : 2;\r
- unsigned char MOIFV : 1;\r
- unsigned char MOIFE : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char MOIFE : 1;\r
- unsigned char MOIFV : 1;\r
- unsigned char : 2;\r
- unsigned char SPLP2 : 1;\r
- unsigned char SPLP : 1;\r
-#endif\r
- } BIT;\r
- } SPPCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char OVRF : 1;\r
- unsigned char IDLNF : 1;\r
- unsigned char MODF : 1;\r
- unsigned char PERF : 1;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char PERF : 1;\r
- unsigned char MODF : 1;\r
- unsigned char IDLNF : 1;\r
- unsigned char OVRF : 1;\r
-#endif\r
- } BIT;\r
- } SPSR;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned short H;\r
- } WORD;\r
- } SPDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SPSLN : 3;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char SPSLN : 3;\r
-#endif\r
- } BIT;\r
- } SPSCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SPCP : 3;\r
- unsigned char : 1;\r
- unsigned char SPECM : 3;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char SPECM : 3;\r
- unsigned char : 1;\r
- unsigned char SPCP : 3;\r
-#endif\r
- } BIT;\r
- } SPSSR;\r
- unsigned char SPBR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SPFC : 2;\r
- unsigned char : 2;\r
- unsigned char SPRDTD : 1;\r
- unsigned char SPLW : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char SPLW : 1;\r
- unsigned char SPRDTD : 1;\r
- unsigned char : 2;\r
- unsigned char SPFC : 2;\r
-#endif\r
- } BIT;\r
- } SPDCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SCKDL : 3;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char SCKDL : 3;\r
-#endif\r
- } BIT;\r
- } SPCKD;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SLNDL : 3;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char SLNDL : 3;\r
-#endif\r
- } BIT;\r
- } SSLND;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SPNDL : 3;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char SPNDL : 3;\r
-#endif\r
- } BIT;\r
- } SPND;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SPPE : 1;\r
- unsigned char SPOE : 1;\r
- unsigned char SPIIE : 1;\r
- unsigned char PTE : 1;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char PTE : 1;\r
- unsigned char SPIIE : 1;\r
- unsigned char SPOE : 1;\r
- unsigned char SPPE : 1;\r
-#endif\r
- } BIT;\r
- } SPCR2;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CPHA : 1;\r
- unsigned short CPOL : 1;\r
- unsigned short BRDV : 2;\r
- unsigned short SSLA : 3;\r
- unsigned short SSLKP : 1;\r
- unsigned short SPB : 4;\r
- unsigned short LSBF : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SCKDEN : 1;\r
-#else\r
- unsigned short SCKDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short LSBF : 1;\r
- unsigned short SPB : 4;\r
- unsigned short SSLKP : 1;\r
- unsigned short SSLA : 3;\r
- unsigned short BRDV : 2;\r
- unsigned short CPOL : 1;\r
- unsigned short CPHA : 1;\r
-#endif\r
- } BIT;\r
- } SPCMD0;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CPHA : 1;\r
- unsigned short CPOL : 1;\r
- unsigned short BRDV : 2;\r
- unsigned short SSLA : 3;\r
- unsigned short SSLKP : 1;\r
- unsigned short SPB : 4;\r
- unsigned short LSBF : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SCKDEN : 1;\r
-#else\r
- unsigned short SCKDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short LSBF : 1;\r
- unsigned short SPB : 4;\r
- unsigned short SSLKP : 1;\r
- unsigned short SSLA : 3;\r
- unsigned short BRDV : 2;\r
- unsigned short CPOL : 1;\r
- unsigned short CPHA : 1;\r
-#endif\r
- } BIT;\r
- } SPCMD1;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CPHA : 1;\r
- unsigned short CPOL : 1;\r
- unsigned short BRDV : 2;\r
- unsigned short SSLA : 3;\r
- unsigned short SSLKP : 1;\r
- unsigned short SPB : 4;\r
- unsigned short LSBF : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SCKDEN : 1;\r
-#else\r
- unsigned short SCKDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short LSBF : 1;\r
- unsigned short SPB : 4;\r
- unsigned short SSLKP : 1;\r
- unsigned short SSLA : 3;\r
- unsigned short BRDV : 2;\r
- unsigned short CPOL : 1;\r
- unsigned short CPHA : 1;\r
-#endif\r
- } BIT;\r
- } SPCMD2;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CPHA : 1;\r
- unsigned short CPOL : 1;\r
- unsigned short BRDV : 2;\r
- unsigned short SSLA : 3;\r
- unsigned short SSLKP : 1;\r
- unsigned short SPB : 4;\r
- unsigned short LSBF : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SCKDEN : 1;\r
-#else\r
- unsigned short SCKDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short LSBF : 1;\r
- unsigned short SPB : 4;\r
- unsigned short SSLKP : 1;\r
- unsigned short SSLA : 3;\r
- unsigned short BRDV : 2;\r
- unsigned short CPOL : 1;\r
- unsigned short CPHA : 1;\r
-#endif\r
- } BIT;\r
- } SPCMD3;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CPHA : 1;\r
- unsigned short CPOL : 1;\r
- unsigned short BRDV : 2;\r
- unsigned short SSLA : 3;\r
- unsigned short SSLKP : 1;\r
- unsigned short SPB : 4;\r
- unsigned short LSBF : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SCKDEN : 1;\r
-#else\r
- unsigned short SCKDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short LSBF : 1;\r
- unsigned short SPB : 4;\r
- unsigned short SSLKP : 1;\r
- unsigned short SSLA : 3;\r
- unsigned short BRDV : 2;\r
- unsigned short CPOL : 1;\r
- unsigned short CPHA : 1;\r
-#endif\r
- } BIT;\r
- } SPCMD4;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CPHA : 1;\r
- unsigned short CPOL : 1;\r
- unsigned short BRDV : 2;\r
- unsigned short SSLA : 3;\r
- unsigned short SSLKP : 1;\r
- unsigned short SPB : 4;\r
- unsigned short LSBF : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SCKDEN : 1;\r
-#else\r
- unsigned short SCKDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short LSBF : 1;\r
- unsigned short SPB : 4;\r
- unsigned short SSLKP : 1;\r
- unsigned short SSLA : 3;\r
- unsigned short BRDV : 2;\r
- unsigned short CPOL : 1;\r
- unsigned short CPHA : 1;\r
-#endif\r
- } BIT;\r
- } SPCMD5;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CPHA : 1;\r
- unsigned short CPOL : 1;\r
- unsigned short BRDV : 2;\r
- unsigned short SSLA : 3;\r
- unsigned short SSLKP : 1;\r
- unsigned short SPB : 4;\r
- unsigned short LSBF : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SCKDEN : 1;\r
-#else\r
- unsigned short SCKDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short LSBF : 1;\r
- unsigned short SPB : 4;\r
- unsigned short SSLKP : 1;\r
- unsigned short SSLA : 3;\r
- unsigned short BRDV : 2;\r
- unsigned short CPOL : 1;\r
- unsigned short CPHA : 1;\r
-#endif\r
- } BIT;\r
- } SPCMD6;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CPHA : 1;\r
- unsigned short CPOL : 1;\r
- unsigned short BRDV : 2;\r
- unsigned short SSLA : 3;\r
- unsigned short SSLKP : 1;\r
- unsigned short SPB : 4;\r
- unsigned short LSBF : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SCKDEN : 1;\r
-#else\r
- unsigned short SCKDEN : 1;\r
- unsigned short SLNDEN : 1;\r
- unsigned short SPNDEN : 1;\r
- unsigned short LSBF : 1;\r
- unsigned short SPB : 4;\r
- unsigned short SSLKP : 1;\r
- unsigned short SSLA : 3;\r
- unsigned short BRDV : 2;\r
- unsigned short CPOL : 1;\r
- unsigned short CPHA : 1;\r
-#endif\r
- } BIT;\r
- } SPCMD7;\r
-};\r
-\r
-struct st_rtc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char F64HZ : 1;\r
- unsigned char F32HZ : 1;\r
- unsigned char F16HZ : 1;\r
- unsigned char F8HZ : 1;\r
- unsigned char F4HZ : 1;\r
- unsigned char F2HZ : 1;\r
- unsigned char F1HZ : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char F1HZ : 1;\r
- unsigned char F2HZ : 1;\r
- unsigned char F4HZ : 1;\r
- unsigned char F8HZ : 1;\r
- unsigned char F16HZ : 1;\r
- unsigned char F32HZ : 1;\r
- unsigned char F64HZ : 1;\r
-#endif\r
- } BIT;\r
- } R64CNT;\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SEC1 : 4;\r
- unsigned char SEC10 : 3;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char SEC10 : 3;\r
- unsigned char SEC1 : 4;\r
-#endif\r
- } BIT;\r
- } RSECCNT;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MIN1 : 4;\r
- unsigned char MIN10 : 3;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char MIN10 : 3;\r
- unsigned char MIN1 : 4;\r
-#endif\r
- } BIT;\r
- } RMINCNT;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char HR1 : 4;\r
- unsigned char HR10 : 2;\r
- unsigned char PM : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char PM : 1;\r
- unsigned char HR10 : 2;\r
- unsigned char HR1 : 4;\r
-#endif\r
- } BIT;\r
- } RHRCNT;\r
- char wk3[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char DAYW : 3;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char DAYW : 3;\r
-#endif\r
- } BIT;\r
- } RWKCNT;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char DATE1 : 4;\r
- unsigned char DATE10 : 2;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char DATE10 : 2;\r
- unsigned char DATE1 : 4;\r
-#endif\r
- } BIT;\r
- } RDAYCNT;\r
- char wk5[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MON1 : 4;\r
- unsigned char MON10 : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char MON10 : 1;\r
- unsigned char MON1 : 4;\r
-#endif\r
- } BIT;\r
- } RMONCNT;\r
- char wk6[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short YR1 : 4;\r
- unsigned short YR10 : 4;\r
- unsigned short : 8;\r
-#else\r
- unsigned short : 8;\r
- unsigned short YR10 : 4;\r
- unsigned short YR1 : 4;\r
-#endif\r
- } BIT;\r
- } RYRCNT;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SEC1 : 4;\r
- unsigned char SEC10 : 3;\r
- unsigned char ENB : 1;\r
-#else\r
- unsigned char ENB : 1;\r
- unsigned char SEC10 : 3;\r
- unsigned char SEC1 : 4;\r
-#endif\r
- } BIT;\r
- } RSECAR;\r
- char wk7[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MIN1 : 4;\r
- unsigned char MIN10 : 3;\r
- unsigned char ENB : 1;\r
-#else\r
- unsigned char ENB : 1;\r
- unsigned char MIN10 : 3;\r
- unsigned char MIN1 : 4;\r
-#endif\r
- } BIT;\r
- } RMINAR;\r
- char wk8[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char HR1 : 4;\r
- unsigned char HR10 : 2;\r
- unsigned char PM : 1;\r
- unsigned char ENB : 1;\r
-#else\r
- unsigned char ENB : 1;\r
- unsigned char PM : 1;\r
- unsigned char HR10 : 2;\r
- unsigned char HR1 : 4;\r
-#endif\r
- } BIT;\r
- } RHRAR;\r
- char wk9[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char DAYW : 3;\r
- unsigned char : 4;\r
- unsigned char ENB : 1;\r
-#else\r
- unsigned char ENB : 1;\r
- unsigned char : 4;\r
- unsigned char DAYW : 3;\r
-#endif\r
- } BIT;\r
- } RWKAR;\r
- char wk10[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char DATE1 : 4;\r
- unsigned char DATE10 : 2;\r
- unsigned char : 1;\r
- unsigned char ENB : 1;\r
-#else\r
- unsigned char ENB : 1;\r
- unsigned char : 1;\r
- unsigned char DATE10 : 2;\r
- unsigned char DATE1 : 4;\r
-#endif\r
- } BIT;\r
- } RDAYAR;\r
- char wk11[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MON1 : 4;\r
- unsigned char MON10 : 1;\r
- unsigned char : 2;\r
- unsigned char ENB : 1;\r
-#else\r
- unsigned char ENB : 1;\r
- unsigned char : 2;\r
- unsigned char MON10 : 1;\r
- unsigned char MON1 : 4;\r
-#endif\r
- } BIT;\r
- } RMONAR;\r
- char wk12[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short YR1 : 4;\r
- unsigned short YR10 : 4;\r
- unsigned short : 8;\r
-#else\r
- unsigned short : 8;\r
- unsigned short YR10 : 4;\r
- unsigned short YR1 : 4;\r
-#endif\r
- } BIT;\r
- } RYRAR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 7;\r
- unsigned char ENB : 1;\r
-#else\r
- unsigned char ENB : 1;\r
- unsigned char : 7;\r
-#endif\r
- } BIT;\r
- } RYRAREN;\r
- char wk13[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char AIE : 1;\r
- unsigned char CIE : 1;\r
- unsigned char PIE : 1;\r
- unsigned char RTCOS : 1;\r
- unsigned char PES : 4;\r
-#else\r
- unsigned char PES : 4;\r
- unsigned char RTCOS : 1;\r
- unsigned char PIE : 1;\r
- unsigned char CIE : 1;\r
- unsigned char AIE : 1;\r
-#endif\r
- } BIT;\r
- } RCR1;\r
- char wk14[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char START : 1;\r
- unsigned char RESET : 1;\r
- unsigned char ADJ30 : 1;\r
- unsigned char RTCOE : 1;\r
- unsigned char AADJE : 1;\r
- unsigned char AADJP : 1;\r
- unsigned char HR24 : 1;\r
- unsigned char CNTMD : 1;\r
-#else\r
- unsigned char CNTMD : 1;\r
- unsigned char HR24 : 1;\r
- unsigned char AADJP : 1;\r
- unsigned char AADJE : 1;\r
- unsigned char RTCOE : 1;\r
- unsigned char ADJ30 : 1;\r
- unsigned char RESET : 1;\r
- unsigned char START : 1;\r
-#endif\r
- } BIT;\r
- } RCR2;\r
- char wk15[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char RTCEN : 1;\r
- unsigned char RTCDV : 3;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char RTCDV : 3;\r
- unsigned char RTCEN : 1;\r
-#endif\r
- } BIT;\r
- } RCR3;\r
- char wk16[7];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char ADJ : 6;\r
- unsigned char PMADJ : 2;\r
-#else\r
- unsigned char PMADJ : 2;\r
- unsigned char ADJ : 6;\r
-#endif\r
- } BIT;\r
- } RADJ;\r
-};\r
-\r
-struct st_rtcb {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BCNT : 8;\r
-#else\r
- unsigned char BCNT : 8;\r
-#endif\r
- } BIT;\r
- } BCNT0;\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BCNT : 8;\r
-#else\r
- unsigned char BCNT : 8;\r
-#endif\r
- } BIT;\r
- } BCNT1;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BCNT : 8;\r
-#else\r
- unsigned char BCNT : 8;\r
-#endif\r
- } BIT;\r
- } BCNT2;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BCNT : 8;\r
-#else\r
- unsigned char BCNT : 8;\r
-#endif\r
- } BIT;\r
- } BCNT3;\r
- char wk3[7];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BCNTAR : 8;\r
-#else\r
- unsigned char BCNTAR : 8;\r
-#endif\r
- } BIT;\r
- } BCNT0AR;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BCNTAR : 8;\r
-#else\r
- unsigned char BCNTAR : 8;\r
-#endif\r
- } BIT;\r
- } BCNT1AR;\r
- char wk5[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BCNTAR : 8;\r
-#else\r
- unsigned char BCNTAR : 8;\r
-#endif\r
- } BIT;\r
- } BCNT2AR;\r
- char wk6[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BCNTAR : 8;\r
-#else\r
- unsigned char BCNTAR : 8;\r
-#endif\r
- } BIT;\r
- } BCNT3AR;\r
- char wk7[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char ENB : 8;\r
-#else\r
- unsigned char ENB : 8;\r
-#endif\r
- } BIT;\r
- } BCNT0AER;\r
- char wk8[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char ENB : 8;\r
-#else\r
- unsigned char ENB : 8;\r
-#endif\r
- } BIT;\r
- } BCNT1AER;\r
- char wk9[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short ENB : 8;\r
- unsigned short : 8;\r
-#else\r
- unsigned short : 8;\r
- unsigned short ENB : 8;\r
-#endif\r
- } BIT;\r
- } BCNT2AER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char ENB : 8;\r
-#else\r
- unsigned char ENB : 8;\r
-#endif\r
- } BIT;\r
- } BCNT3AER;\r
-};\r
-\r
-struct st_s12ad {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short DBLANS : 5;\r
- unsigned short : 1;\r
- unsigned short GBADIE : 1;\r
- unsigned short DBLE : 1;\r
- unsigned short EXTRG : 1;\r
- unsigned short TRGE : 1;\r
- unsigned short ADHSC : 1;\r
- unsigned short : 1;\r
- unsigned short ADIE : 1;\r
- unsigned short ADCS : 2;\r
- unsigned short ADST : 1;\r
-#else\r
- unsigned short ADST : 1;\r
- unsigned short ADCS : 2;\r
- unsigned short ADIE : 1;\r
- unsigned short : 1;\r
- unsigned short ADHSC : 1;\r
- unsigned short TRGE : 1;\r
- unsigned short EXTRG : 1;\r
- unsigned short DBLE : 1;\r
- unsigned short GBADIE : 1;\r
- unsigned short : 1;\r
- unsigned short DBLANS : 5;\r
-#endif\r
- } BIT;\r
- } ADCSR;\r
- char wk0[2];\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short ANSA:16;\r
-// } BIT;\r
- } ADANSA;\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short :10;\r
-// unsigned short ANSA1:1;\r
-// } BIT;\r
- } ADANSA1;\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short ADS:16;\r
-// } BIT;\r
- } ADADS;\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short :10;\r
-// unsigned short ADS1:1;\r
-// } BIT;\r
- } ADADS1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char ADC : 2;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char ADC : 2;\r
-#endif\r
- } BIT;\r
- } ADADC;\r
- char wk1[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 5;\r
- unsigned short ACE : 1;\r
- unsigned short : 9;\r
- unsigned short ADRFMT : 1;\r
-#else\r
- unsigned short ADRFMT : 1;\r
- unsigned short : 9;\r
- unsigned short ACE : 1;\r
- unsigned short : 5;\r
-#endif\r
- } BIT;\r
- } ADCER;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short TRSB : 4;\r
- unsigned short : 4;\r
- unsigned short TRSA : 4;\r
- unsigned short : 4;\r
-#else\r
- unsigned short : 4;\r
- unsigned short TRSA : 4;\r
- unsigned short : 4;\r
- unsigned short TRSB : 4;\r
-#endif\r
- } BIT;\r
- } ADSTRGR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short TSSAD : 1;\r
- unsigned short OCSAD : 1;\r
- unsigned short : 6;\r
- unsigned short TSS : 1;\r
- unsigned short OCS : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short OCS : 1;\r
- unsigned short TSS : 1;\r
- unsigned short : 6;\r
- unsigned short OCSAD : 1;\r
- unsigned short TSSAD : 1;\r
-#endif\r
- } BIT;\r
- } ADEXICR;\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short ANSB:16;\r
-// } BIT;\r
- } ADANSB;\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short :10;\r
-// unsigned short ANSB1:1;\r
-// } BIT;\r
- } ADANSB1;\r
- unsigned short ADDBLDR;\r
- unsigned short ADTSDR;\r
- unsigned short ADOCDR;\r
- char wk2[2];\r
- unsigned short ADDR0;\r
- unsigned short ADDR1;\r
- unsigned short ADDR2;\r
- unsigned short ADDR3;\r
- unsigned short ADDR4;\r
- unsigned short ADDR5;\r
- unsigned short ADDR6;\r
- unsigned short ADDR7;\r
- unsigned short ADDR8;\r
- unsigned short ADDR9;\r
- unsigned short ADDR10;\r
- unsigned short ADDR11;\r
- unsigned short ADDR12;\r
- unsigned short ADDR13;\r
- unsigned short ADDR14;\r
- unsigned short ADDR15;\r
- char wk3[10];\r
- unsigned short ADDR21;\r
- char wk4[20];\r
- unsigned char ADSSTR0;\r
- unsigned char ADSSTRL;\r
- char wk5[14];\r
- unsigned char ADSSTRT;\r
- unsigned char ADSSTRO;\r
- char wk6[1];\r
- unsigned char ADSSTR1;\r
- unsigned char ADSSTR2;\r
- unsigned char ADSSTR3;\r
- unsigned char ADSSTR4;\r
- unsigned char ADSSTR5;\r
- unsigned char ADSSTR6;\r
- unsigned char ADSSTR7;\r
- char wk7[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char HVREFDIS : 1;\r
- unsigned char OCSVSEL : 1;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char OCSVSEL : 1;\r
- unsigned char HVREFDIS : 1;\r
-#endif\r
- } BIT;\r
- } ADHVREFCNT;\r
- char wk8[3];\r
- unsigned char ADSSTR21;\r
-};\r
-\r
-struct st_sci0 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CKS : 2;\r
- unsigned char MP : 1;\r
- unsigned char STOP : 1;\r
- unsigned char PM : 1;\r
- unsigned char PE : 1;\r
- unsigned char CHR : 1;\r
- unsigned char CM : 1;\r
-#else\r
- unsigned char CM : 1;\r
- unsigned char CHR : 1;\r
- unsigned char PE : 1;\r
- unsigned char PM : 1;\r
- unsigned char STOP : 1;\r
- unsigned char MP : 1;\r
- unsigned char CKS : 2;\r
-#endif\r
- } BIT;\r
- } SMR;\r
- unsigned char BRR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CKE : 2;\r
- unsigned char TEIE : 1;\r
- unsigned char MPIE : 1;\r
- unsigned char RE : 1;\r
- unsigned char TE : 1;\r
- unsigned char RIE : 1;\r
- unsigned char TIE : 1;\r
-#else\r
- unsigned char TIE : 1;\r
- unsigned char RIE : 1;\r
- unsigned char TE : 1;\r
- unsigned char RE : 1;\r
- unsigned char MPIE : 1;\r
- unsigned char TEIE : 1;\r
- unsigned char CKE : 2;\r
-#endif\r
- } BIT;\r
- } SCR;\r
- unsigned char TDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MPBT : 1;\r
- unsigned char MPB : 1;\r
- unsigned char TEND : 1;\r
- unsigned char PER : 1;\r
- unsigned char FER : 1;\r
- unsigned char ORER : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char ORER : 1;\r
- unsigned char FER : 1;\r
- unsigned char PER : 1;\r
- unsigned char TEND : 1;\r
- unsigned char MPB : 1;\r
- unsigned char MPBT : 1;\r
-#endif\r
- } BIT;\r
- } SSR;\r
- unsigned char RDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SMIF : 1;\r
- unsigned char : 1;\r
- unsigned char SINV : 1;\r
- unsigned char SDIR : 1;\r
- unsigned char : 3;\r
- unsigned char BCP2 : 1;\r
-#else\r
- unsigned char BCP2 : 1;\r
- unsigned char : 3;\r
- unsigned char SDIR : 1;\r
- unsigned char SINV : 1;\r
- unsigned char : 1;\r
- unsigned char SMIF : 1;\r
-#endif\r
- } BIT;\r
- } SCMR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char ACS0 : 1;\r
- unsigned char : 3;\r
- unsigned char ABCS : 1;\r
- unsigned char NFEN : 1;\r
- unsigned char : 1;\r
- unsigned char RXDESEL : 1;\r
-#else\r
- unsigned char RXDESEL : 1;\r
- unsigned char : 1;\r
- unsigned char NFEN : 1;\r
- unsigned char ABCS : 1;\r
- unsigned char : 3;\r
- unsigned char ACS0 : 1;\r
-#endif\r
- } BIT;\r
- } SEMR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NFCS : 3;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char NFCS : 3;\r
-#endif\r
- } BIT;\r
- } SNFR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IICM : 1;\r
- unsigned char : 2;\r
- unsigned char IICDL : 5;\r
-#else\r
- unsigned char IICDL : 5;\r
- unsigned char : 2;\r
- unsigned char IICM : 1;\r
-#endif\r
- } BIT;\r
- } SIMR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IICINTM : 1;\r
- unsigned char IICCSC : 1;\r
- unsigned char : 3;\r
- unsigned char IICACKT : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char IICACKT : 1;\r
- unsigned char : 3;\r
- unsigned char IICCSC : 1;\r
- unsigned char IICINTM : 1;\r
-#endif\r
- } BIT;\r
- } SIMR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IICSTAREQ : 1;\r
- unsigned char IICRSTAREQ : 1;\r
- unsigned char IICSTPREQ : 1;\r
- unsigned char IICSTIF : 1;\r
- unsigned char IICSDAS : 2;\r
- unsigned char IICSCLS : 2;\r
-#else\r
- unsigned char IICSCLS : 2;\r
- unsigned char IICSDAS : 2;\r
- unsigned char IICSTIF : 1;\r
- unsigned char IICSTPREQ : 1;\r
- unsigned char IICRSTAREQ : 1;\r
- unsigned char IICSTAREQ : 1;\r
-#endif\r
- } BIT;\r
- } SIMR3;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IICACKR : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char IICACKR : 1;\r
-#endif\r
- } BIT;\r
- } SISR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SSE : 1;\r
- unsigned char CTSE : 1;\r
- unsigned char MSS : 1;\r
- unsigned char : 1;\r
- unsigned char MFF : 1;\r
- unsigned char : 1;\r
- unsigned char CKPOL : 1;\r
- unsigned char CKPH : 1;\r
-#else\r
- unsigned char CKPH : 1;\r
- unsigned char CKPOL : 1;\r
- unsigned char : 1;\r
- unsigned char MFF : 1;\r
- unsigned char : 1;\r
- unsigned char MSS : 1;\r
- unsigned char CTSE : 1;\r
- unsigned char SSE : 1;\r
-#endif\r
- } BIT;\r
- } SPMR;\r
-};\r
-\r
-struct st_sci12 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CKS : 2;\r
- unsigned char MP : 1;\r
- unsigned char STOP : 1;\r
- unsigned char PM : 1;\r
- unsigned char PE : 1;\r
- unsigned char CHR : 1;\r
- unsigned char CM : 1;\r
-#else\r
- unsigned char CM : 1;\r
- unsigned char CHR : 1;\r
- unsigned char PE : 1;\r
- unsigned char PM : 1;\r
- unsigned char STOP : 1;\r
- unsigned char MP : 1;\r
- unsigned char CKS : 2;\r
-#endif\r
- } BIT;\r
- } SMR;\r
- unsigned char BRR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CKE : 2;\r
- unsigned char TEIE : 1;\r
- unsigned char MPIE : 1;\r
- unsigned char RE : 1;\r
- unsigned char TE : 1;\r
- unsigned char RIE : 1;\r
- unsigned char TIE : 1;\r
-#else\r
- unsigned char TIE : 1;\r
- unsigned char RIE : 1;\r
- unsigned char TE : 1;\r
- unsigned char RE : 1;\r
- unsigned char MPIE : 1;\r
- unsigned char TEIE : 1;\r
- unsigned char CKE : 2;\r
-#endif\r
- } BIT;\r
- } SCR;\r
- unsigned char TDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MPBT : 1;\r
- unsigned char MPB : 1;\r
- unsigned char TEND : 1;\r
- unsigned char PER : 1;\r
- unsigned char FER : 1;\r
- unsigned char ORER : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char ORER : 1;\r
- unsigned char FER : 1;\r
- unsigned char PER : 1;\r
- unsigned char TEND : 1;\r
- unsigned char MPB : 1;\r
- unsigned char MPBT : 1;\r
-#endif\r
- } BIT;\r
- } SSR;\r
- unsigned char RDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SMIF : 1;\r
- unsigned char : 1;\r
- unsigned char SINV : 1;\r
- unsigned char SDIR : 1;\r
- unsigned char : 3;\r
- unsigned char BCP2 : 1;\r
-#else\r
- unsigned char BCP2 : 1;\r
- unsigned char : 3;\r
- unsigned char SDIR : 1;\r
- unsigned char SINV : 1;\r
- unsigned char : 1;\r
- unsigned char SMIF : 1;\r
-#endif\r
- } BIT;\r
- } SCMR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char ACS0 : 1;\r
- unsigned char : 3;\r
- unsigned char ABCS : 1;\r
- unsigned char NFEN : 1;\r
- unsigned char : 1;\r
- unsigned char RXDESEL : 1;\r
-#else\r
- unsigned char RXDESEL : 1;\r
- unsigned char : 1;\r
- unsigned char NFEN : 1;\r
- unsigned char ABCS : 1;\r
- unsigned char : 3;\r
- unsigned char ACS0 : 1;\r
-#endif\r
- } BIT;\r
- } SEMR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char NFCS : 3;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char NFCS : 3;\r
-#endif\r
- } BIT;\r
- } SNFR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IICM : 1;\r
- unsigned char : 2;\r
- unsigned char IICDL : 5;\r
-#else\r
- unsigned char IICDL : 5;\r
- unsigned char : 2;\r
- unsigned char IICM : 1;\r
-#endif\r
- } BIT;\r
- } SIMR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IICINTM : 1;\r
- unsigned char IICCSC : 1;\r
- unsigned char : 3;\r
- unsigned char IICACKT : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char IICACKT : 1;\r
- unsigned char : 3;\r
- unsigned char IICCSC : 1;\r
- unsigned char IICINTM : 1;\r
-#endif\r
- } BIT;\r
- } SIMR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IICSTAREQ : 1;\r
- unsigned char IICRSTAREQ : 1;\r
- unsigned char IICSTPREQ : 1;\r
- unsigned char IICSTIF : 1;\r
- unsigned char IICSDAS : 2;\r
- unsigned char IICSCLS : 2;\r
-#else\r
- unsigned char IICSCLS : 2;\r
- unsigned char IICSDAS : 2;\r
- unsigned char IICSTIF : 1;\r
- unsigned char IICSTPREQ : 1;\r
- unsigned char IICRSTAREQ : 1;\r
- unsigned char IICSTAREQ : 1;\r
-#endif\r
- } BIT;\r
- } SIMR3;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IICACKR : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char IICACKR : 1;\r
-#endif\r
- } BIT;\r
- } SISR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SSE : 1;\r
- unsigned char CTSE : 1;\r
- unsigned char MSS : 1;\r
- unsigned char : 1;\r
- unsigned char MFF : 1;\r
- unsigned char : 1;\r
- unsigned char CKPOL : 1;\r
- unsigned char CKPH : 1;\r
-#else\r
- unsigned char CKPH : 1;\r
- unsigned char CKPOL : 1;\r
- unsigned char : 1;\r
- unsigned char MFF : 1;\r
- unsigned char : 1;\r
- unsigned char MSS : 1;\r
- unsigned char CTSE : 1;\r
- unsigned char SSE : 1;\r
-#endif\r
- } BIT;\r
- } SPMR;\r
- char wk0[18];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char ESME : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char ESME : 1;\r
-#endif\r
- } BIT;\r
- } ESMER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 1;\r
- unsigned char SFSF : 1;\r
- unsigned char RXDSF : 1;\r
- unsigned char BRME : 1;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char BRME : 1;\r
- unsigned char RXDSF : 1;\r
- unsigned char SFSF : 1;\r
- unsigned char : 1;\r
-#endif\r
- } BIT;\r
- } CR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BFE : 1;\r
- unsigned char CF0RE : 1;\r
- unsigned char CF1DS : 2;\r
- unsigned char PIBE : 1;\r
- unsigned char PIBS : 3;\r
-#else\r
- unsigned char PIBS : 3;\r
- unsigned char PIBE : 1;\r
- unsigned char CF1DS : 2;\r
- unsigned char CF0RE : 1;\r
- unsigned char BFE : 1;\r
-#endif\r
- } BIT;\r
- } CR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char DFCS : 3;\r
- unsigned char : 1;\r
- unsigned char BCCS : 2;\r
- unsigned char RTS : 2;\r
-#else\r
- unsigned char RTS : 2;\r
- unsigned char BCCS : 2;\r
- unsigned char : 1;\r
- unsigned char DFCS : 3;\r
-#endif\r
- } BIT;\r
- } CR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SDST : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char SDST : 1;\r
-#endif\r
- } BIT;\r
- } CR3;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TXDXPS : 1;\r
- unsigned char RXDXPS : 1;\r
- unsigned char : 2;\r
- unsigned char SHARPS : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char SHARPS : 1;\r
- unsigned char : 2;\r
- unsigned char RXDXPS : 1;\r
- unsigned char TXDXPS : 1;\r
-#endif\r
- } BIT;\r
- } PCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BFDIE : 1;\r
- unsigned char CF0MIE : 1;\r
- unsigned char CF1MIE : 1;\r
- unsigned char PIBDIE : 1;\r
- unsigned char BCDIE : 1;\r
- unsigned char AEDIE : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char AEDIE : 1;\r
- unsigned char BCDIE : 1;\r
- unsigned char PIBDIE : 1;\r
- unsigned char CF1MIE : 1;\r
- unsigned char CF0MIE : 1;\r
- unsigned char BFDIE : 1;\r
-#endif\r
- } BIT;\r
- } ICR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BFDF : 1;\r
- unsigned char CF0MF : 1;\r
- unsigned char CF1MF : 1;\r
- unsigned char PIBDF : 1;\r
- unsigned char BCDF : 1;\r
- unsigned char AEDF : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char AEDF : 1;\r
- unsigned char BCDF : 1;\r
- unsigned char PIBDF : 1;\r
- unsigned char CF1MF : 1;\r
- unsigned char CF0MF : 1;\r
- unsigned char BFDF : 1;\r
-#endif\r
- } BIT;\r
- } STR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char BFDCL : 1;\r
- unsigned char CF0MCL : 1;\r
- unsigned char CF1MCL : 1;\r
- unsigned char PIBDCL : 1;\r
- unsigned char BCDCL : 1;\r
- unsigned char AEDCL : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char AEDCL : 1;\r
- unsigned char BCDCL : 1;\r
- unsigned char PIBDCL : 1;\r
- unsigned char CF1MCL : 1;\r
- unsigned char CF0MCL : 1;\r
- unsigned char BFDCL : 1;\r
-#endif\r
- } BIT;\r
- } STCR;\r
- unsigned char CF0DR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CF0CE0 : 1;\r
- unsigned char CF0CE1 : 1;\r
- unsigned char CF0CE2 : 1;\r
- unsigned char CF0CE3 : 1;\r
- unsigned char CF0CE4 : 1;\r
- unsigned char CF0CE5 : 1;\r
- unsigned char CF0CE6 : 1;\r
- unsigned char CF0CE7 : 1;\r
-#else\r
- unsigned char CF0CE7 : 1;\r
- unsigned char CF0CE6 : 1;\r
- unsigned char CF0CE5 : 1;\r
- unsigned char CF0CE4 : 1;\r
- unsigned char CF0CE3 : 1;\r
- unsigned char CF0CE2 : 1;\r
- unsigned char CF0CE1 : 1;\r
- unsigned char CF0CE0 : 1;\r
-#endif\r
- } BIT;\r
- } CF0CR;\r
- unsigned char CF0RR;\r
- unsigned char PCF1DR;\r
- unsigned char SCF1DR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CF1CE0 : 1;\r
- unsigned char CF1CE1 : 1;\r
- unsigned char CF1CE2 : 1;\r
- unsigned char CF1CE3 : 1;\r
- unsigned char CF1CE4 : 1;\r
- unsigned char CF1CE5 : 1;\r
- unsigned char CF1CE6 : 1;\r
- unsigned char CF1CE7 : 1;\r
-#else\r
- unsigned char CF1CE7 : 1;\r
- unsigned char CF1CE6 : 1;\r
- unsigned char CF1CE5 : 1;\r
- unsigned char CF1CE4 : 1;\r
- unsigned char CF1CE3 : 1;\r
- unsigned char CF1CE2 : 1;\r
- unsigned char CF1CE1 : 1;\r
- unsigned char CF1CE0 : 1;\r
-#endif\r
- } BIT;\r
- } CF1CR;\r
- unsigned char CF1RR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TCST : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char TCST : 1;\r
-#endif\r
- } BIT;\r
- } TCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TOMS : 2;\r
- unsigned char : 1;\r
- unsigned char TWRC : 1;\r
- unsigned char TCSS : 3;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char TCSS : 3;\r
- unsigned char TWRC : 1;\r
- unsigned char : 1;\r
- unsigned char TOMS : 2;\r
-#endif\r
- } BIT;\r
- } TMR;\r
- unsigned char TPRE;\r
- unsigned char TCNT;\r
-};\r
-\r
-struct st_smci {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CKS : 2;\r
- unsigned char BCP : 2;\r
- unsigned char PM : 1;\r
- unsigned char PE : 1;\r
- unsigned char BLK : 1;\r
- unsigned char GM : 1;\r
-#else\r
- unsigned char GM : 1;\r
- unsigned char BLK : 1;\r
- unsigned char PE : 1;\r
- unsigned char PM : 1;\r
- unsigned char BCP : 2;\r
- unsigned char CKS : 2;\r
-#endif\r
- } BIT;\r
- } SMR;\r
- unsigned char BRR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CKE : 2;\r
- unsigned char TEIE : 1;\r
- unsigned char MPIE : 1;\r
- unsigned char RE : 1;\r
- unsigned char TE : 1;\r
- unsigned char RIE : 1;\r
- unsigned char TIE : 1;\r
-#else\r
- unsigned char TIE : 1;\r
- unsigned char RIE : 1;\r
- unsigned char TE : 1;\r
- unsigned char RE : 1;\r
- unsigned char MPIE : 1;\r
- unsigned char TEIE : 1;\r
- unsigned char CKE : 2;\r
-#endif\r
- } BIT;\r
- } SCR;\r
- unsigned char TDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MPBT : 1;\r
- unsigned char MPB : 1;\r
- unsigned char TEND : 1;\r
- unsigned char PER : 1;\r
- unsigned char ERS : 1;\r
- unsigned char ORER : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char ORER : 1;\r
- unsigned char ERS : 1;\r
- unsigned char PER : 1;\r
- unsigned char TEND : 1;\r
- unsigned char MPB : 1;\r
- unsigned char MPBT : 1;\r
-#endif\r
- } BIT;\r
- } SSR;\r
- unsigned char RDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SMIF : 1;\r
- unsigned char : 1;\r
- unsigned char SINV : 1;\r
- unsigned char SDIR : 1;\r
- unsigned char : 3;\r
- unsigned char BCP2 : 1;\r
-#else\r
- unsigned char BCP2 : 1;\r
- unsigned char : 3;\r
- unsigned char SDIR : 1;\r
- unsigned char SINV : 1;\r
- unsigned char : 1;\r
- unsigned char SMIF : 1;\r
-#endif\r
- } BIT;\r
- } SCMR;\r
-};\r
-\r
-struct st_ssi {\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned long REN : 1;\r
- unsigned long TEN : 1;\r
- unsigned long : 1;\r
- unsigned long MUEN : 1;\r
- unsigned long CKDV : 4;\r
- unsigned long DEL : 1;\r
- unsigned long PDTA : 1;\r
- unsigned long SDTA : 1;\r
- unsigned long SPDP : 1;\r
- unsigned long SWSP : 1;\r
- unsigned long SCKP : 1;\r
- unsigned long SWSD : 1;\r
- unsigned long SCKD : 1;\r
- unsigned long SWL : 3;\r
- unsigned long DWL : 3;\r
- unsigned long CHNL : 2;\r
- unsigned long : 1;\r
- unsigned long IIEN : 1;\r
- unsigned long ROIEN : 1;\r
- unsigned long RUIEN : 1;\r
- unsigned long TOIEN : 1;\r
- unsigned long TUIEN : 1;\r
- unsigned long CKS : 1;\r
- unsigned long : 1;\r
-#else\r
- unsigned long : 1;\r
- unsigned long CKS : 1;\r
- unsigned long TUIEN : 1;\r
- unsigned long TOIEN : 1;\r
- unsigned long RUIEN : 1;\r
- unsigned long ROIEN : 1;\r
- unsigned long IIEN : 1;\r
- unsigned long : 1;\r
- unsigned long CHNL : 2;\r
- unsigned long DWL : 3;\r
- unsigned long SWL : 3;\r
- unsigned long SCKD : 1;\r
- unsigned long SWSD : 1;\r
- unsigned long SCKP : 1;\r
- unsigned long SWSP : 1;\r
- unsigned long SPDP : 1;\r
- unsigned long SDTA : 1;\r
- unsigned long PDTA : 1;\r
- unsigned long DEL : 1;\r
- unsigned long CKDV : 4;\r
- unsigned long MUEN : 1;\r
- unsigned long : 1;\r
- unsigned long TEN : 1;\r
- unsigned long REN : 1;\r
-#endif\r
- } BIT;\r
- } SSICR;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned long IDST : 1;\r
- unsigned long RSWNO : 1;\r
- unsigned long RCHNO : 2;\r
- unsigned long TSWNO : 1;\r
- unsigned long TCHNO : 2;\r
- unsigned long : 18;\r
- unsigned long IIRQ : 1;\r
- unsigned long ROIRQ : 1;\r
- unsigned long RUIRQ : 1;\r
- unsigned long TOIRQ : 1;\r
- unsigned long TUIRQ : 1;\r
- unsigned long : 2;\r
-#else\r
- unsigned long : 2;\r
- unsigned long TUIRQ : 1;\r
- unsigned long TOIRQ : 1;\r
- unsigned long RUIRQ : 1;\r
- unsigned long ROIRQ : 1;\r
- unsigned long IIRQ : 1;\r
- unsigned long : 18;\r
- unsigned long TCHNO : 2;\r
- unsigned long TSWNO : 1;\r
- unsigned long RCHNO : 2;\r
- unsigned long RSWNO : 1;\r
- unsigned long IDST : 1;\r
-#endif\r
- } BIT;\r
- } SSISR;\r
- char wk0[8];\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned long RFRST : 1;\r
- unsigned long TFRST : 1;\r
- unsigned long RIE : 1;\r
- unsigned long TIE : 1;\r
- unsigned long RTRG : 2;\r
- unsigned long TTRG : 2;\r
- unsigned long : 8;\r
- unsigned long SSIRST : 1;\r
- unsigned long : 14;\r
- unsigned long AUCKE : 1;\r
-#else\r
- unsigned long AUCKE : 1;\r
- unsigned long : 14;\r
- unsigned long SSIRST : 1;\r
- unsigned long : 8;\r
- unsigned long TTRG : 2;\r
- unsigned long RTRG : 2;\r
- unsigned long TIE : 1;\r
- unsigned long RIE : 1;\r
- unsigned long TFRST : 1;\r
- unsigned long RFRST : 1;\r
-#endif\r
- } BIT;\r
- } SSIFCR;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned long RDF : 1;\r
- unsigned long : 7;\r
- unsigned long RDC : 4;\r
- unsigned long : 4;\r
- unsigned long TDE : 1;\r
- unsigned long : 7;\r
- unsigned long TDC : 4;\r
- unsigned long : 4;\r
-#else\r
- unsigned long : 4;\r
- unsigned long TDC : 4;\r
- unsigned long : 7;\r
- unsigned long TDE : 1;\r
- unsigned long : 4;\r
- unsigned long RDC : 4;\r
- unsigned long : 7;\r
- unsigned long RDF : 1;\r
-#endif\r
- } BIT;\r
- } SSIFSR;\r
- unsigned long SSIFTDR;\r
- unsigned long SSIFRDR;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned long : 8;\r
- unsigned long CONT : 1;\r
- unsigned long : 23;\r
-#else\r
- unsigned long : 23;\r
- unsigned long CONT : 1;\r
- unsigned long : 8;\r
-#endif\r
- } BIT;\r
- } SSITDMR;\r
-};\r
-\r
-struct st_system {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short MD : 1;\r
- unsigned short : 15;\r
-#else\r
- unsigned short : 15;\r
- unsigned short MD : 1;\r
-#endif\r
- } BIT;\r
- } MDMONR;\r
- char wk0[6];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short RAME : 1;\r
- unsigned short : 15;\r
-#else\r
- unsigned short : 15;\r
- unsigned short RAME : 1;\r
-#endif\r
- } BIT;\r
- } SYSCR1;\r
- char wk1[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 15;\r
- unsigned short SSBY : 1;\r
-#else\r
- unsigned short SSBY : 1;\r
- unsigned short : 15;\r
-#endif\r
- } BIT;\r
- } SBYCR;\r
- char wk2[2];\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned long : 4;\r
- unsigned long MSTPA4 : 1;\r
- unsigned long MSTPA5 : 1;\r
- unsigned long : 3;\r
- unsigned long MSTPA9 : 1;\r
- unsigned long : 4;\r
- unsigned long MSTPA14 : 1;\r
- unsigned long MSTPA15 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPA17 : 1;\r
- unsigned long MSTPA18 : 1;\r
- unsigned long : 9;\r
- unsigned long MSTPA28 : 1;\r
- unsigned long : 3;\r
-#else\r
- unsigned long : 3;\r
- unsigned long MSTPA28 : 1;\r
- unsigned long : 9;\r
- unsigned long MSTPA18 : 1;\r
- unsigned long MSTPA17 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPA15 : 1;\r
- unsigned long MSTPA14 : 1;\r
- unsigned long : 4;\r
- unsigned long MSTPA9 : 1;\r
- unsigned long : 3;\r
- unsigned long MSTPA5 : 1;\r
- unsigned long MSTPA4 : 1;\r
- unsigned long : 4;\r
-#endif\r
- } BIT;\r
- } MSTPCRA;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned long : 4;\r
- unsigned long MSTPB4 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPB6 : 1;\r
- unsigned long : 2;\r
- unsigned long MSTPB9 : 1;\r
- unsigned long MSTPB10 : 1;\r
- unsigned long : 6;\r
- unsigned long MSTPB17 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPB19 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPB21 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPB23 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPB25 : 1;\r
- unsigned long MSTPB26 : 1;\r
- unsigned long : 2;\r
- unsigned long MSTPB29 : 1;\r
- unsigned long MSTPB30 : 1;\r
- unsigned long MSTPB31 : 1;\r
-#else\r
- unsigned long MSTPB31 : 1;\r
- unsigned long MSTPB30 : 1;\r
- unsigned long MSTPB29 : 1;\r
- unsigned long : 2;\r
- unsigned long MSTPB26 : 1;\r
- unsigned long MSTPB25 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPB23 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPB21 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPB19 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPB17 : 1;\r
- unsigned long : 6;\r
- unsigned long MSTPB10 : 1;\r
- unsigned long MSTPB9 : 1;\r
- unsigned long : 2;\r
- unsigned long MSTPB6 : 1;\r
- unsigned long : 1;\r
- unsigned long MSTPB4 : 1;\r
- unsigned long : 4;\r
-#endif\r
- } BIT;\r
- } MSTPCRB;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned long MSTPC0 : 1;\r
- unsigned long : 18;\r
- unsigned long MSTPC19 : 1;\r
- unsigned long MSTPC20 : 1;\r
- unsigned long : 5;\r
- unsigned long MSTPC26 : 1;\r
- unsigned long MSTPC27 : 1;\r
- unsigned long : 3;\r
- unsigned long DSLPE : 1;\r
-#else\r
- unsigned long DSLPE : 1;\r
- unsigned long : 3;\r
- unsigned long MSTPC27 : 1;\r
- unsigned long MSTPC26 : 1;\r
- unsigned long : 5;\r
- unsigned long MSTPC20 : 1;\r
- unsigned long MSTPC19 : 1;\r
- unsigned long : 18;\r
- unsigned long MSTPC0 : 1;\r
-#endif\r
- } BIT;\r
- } MSTPCRC;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned long : 10;\r
- unsigned long MSTPD10 : 1;\r
- unsigned long MSTPD11 : 1;\r
- unsigned long : 3;\r
- unsigned long MSTPD15 : 1;\r
- unsigned long : 16;\r
-#else\r
- unsigned long : 16;\r
- unsigned long MSTPD15 : 1;\r
- unsigned long : 3;\r
- unsigned long MSTPD11 : 1;\r
- unsigned long MSTPD10 : 1;\r
- unsigned long : 10;\r
-#endif\r
- } BIT;\r
- } MSTPCRD;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned long PCKD : 4;\r
- unsigned long : 4;\r
- unsigned long PCKB : 4;\r
- unsigned long : 12;\r
- unsigned long ICK : 4;\r
- unsigned long FCK : 4;\r
-#else\r
- unsigned long FCK : 4;\r
- unsigned long ICK : 4;\r
- unsigned long : 12;\r
- unsigned long PCKB : 4;\r
- unsigned long : 4;\r
- unsigned long PCKD : 4;\r
-#endif\r
- } BIT;\r
- } SCKCR;\r
- char wk3[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 8;\r
- unsigned short CKSEL : 3;\r
- unsigned short : 5;\r
-#else\r
- unsigned short : 5;\r
- unsigned short CKSEL : 3;\r
- unsigned short : 8;\r
-#endif\r
- } BIT;\r
- } SCKCR3;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PLIDIV : 2;\r
- unsigned short : 6;\r
- unsigned short STC : 6;\r
- unsigned short : 2;\r
-#else\r
- unsigned short : 2;\r
- unsigned short STC : 6;\r
- unsigned short : 6;\r
- unsigned short PLIDIV : 2;\r
-#endif\r
- } BIT;\r
- } PLLCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PLLEN : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char PLLEN : 1;\r
-#endif\r
- } BIT;\r
- } PLLCR2;\r
- char wk4[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short UPLIDIV : 2;\r
- unsigned short : 2;\r
- unsigned short UCKUPLLSEL : 1;\r
- unsigned short : 3;\r
- unsigned short USTC : 6;\r
- unsigned short : 2;\r
-#else\r
- unsigned short : 2;\r
- unsigned short USTC : 6;\r
- unsigned short : 3;\r
- unsigned short UCKUPLLSEL : 1;\r
- unsigned short : 2;\r
- unsigned short UPLIDIV : 2;\r
-#endif\r
- } BIT;\r
- } UPLLCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char UPLLEN : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char UPLLEN : 1;\r
-#endif\r
- } BIT;\r
- } UPLLCR2;\r
- char wk5[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MOSTP : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char MOSTP : 1;\r
-#endif\r
- } BIT;\r
- } MOSCCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SOSTP : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char SOSTP : 1;\r
-#endif\r
- } BIT;\r
- } SOSCCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LCSTP : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char LCSTP : 1;\r
-#endif\r
- } BIT;\r
- } LOCOCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char ILCSTP : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char ILCSTP : 1;\r
-#endif\r
- } BIT;\r
- } ILOCOCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char HCSTP : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char HCSTP : 1;\r
-#endif\r
- } BIT;\r
- } HOCOCR;\r
- char wk6[5];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MOOVF : 1;\r
- unsigned char : 1;\r
- unsigned char PLOVF : 1;\r
- unsigned char HCOVF : 1;\r
- unsigned char : 1;\r
- unsigned char UPLOVF : 1;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char UPLOVF : 1;\r
- unsigned char : 1;\r
- unsigned char HCOVF : 1;\r
- unsigned char PLOVF : 1;\r
- unsigned char : 1;\r
- unsigned char MOOVF : 1;\r
-#endif\r
- } BIT;\r
- } OSCOVFSR;\r
- char wk7[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 8;\r
- unsigned short CKOSEL : 3;\r
- unsigned short : 1;\r
- unsigned short CKODIV : 3;\r
- unsigned short CKOSTP : 1;\r
-#else\r
- unsigned short CKOSTP : 1;\r
- unsigned short CKODIV : 3;\r
- unsigned short : 1;\r
- unsigned short CKOSEL : 3;\r
- unsigned short : 8;\r
-#endif\r
- } BIT;\r
- } CKOCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char OSTDIE : 1;\r
- unsigned char : 6;\r
- unsigned char OSTDE : 1;\r
-#else\r
- unsigned char OSTDE : 1;\r
- unsigned char : 6;\r
- unsigned char OSTDIE : 1;\r
-#endif\r
- } BIT;\r
- } OSTDCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char OSTDF : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char OSTDF : 1;\r
-#endif\r
- } BIT;\r
- } OSTDSR;\r
- char wk8[14];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LCDSCLKSEL : 3;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char LCDSCLKSEL : 3;\r
-#endif\r
- } BIT;\r
- } LCDSCLKCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LCDSCLKSTP : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char LCDSCLKSTP : 1;\r
-#endif\r
- } BIT;\r
- } LCDSCLKCR2;\r
- char wk9[78];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char OPCM : 3;\r
- unsigned char : 1;\r
- unsigned char OPCMTSF : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char OPCMTSF : 1;\r
- unsigned char : 1;\r
- unsigned char OPCM : 3;\r
-#endif\r
- } BIT;\r
- } OPCCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char RSTCKSEL : 3;\r
- unsigned char : 4;\r
- unsigned char RSTCKEN : 1;\r
-#else\r
- unsigned char RSTCKEN : 1;\r
- unsigned char : 4;\r
- unsigned char RSTCKSEL : 3;\r
-#endif\r
- } BIT;\r
- } RSTCKCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char MSTS : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char MSTS : 5;\r
-#endif\r
- } BIT;\r
- } MOSCWTCR;\r
- char wk10[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char HSTS : 5;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char HSTS : 5;\r
-#endif\r
- } BIT;\r
- } HOCOWTCR;\r
- char wk11[4];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char SOPCM : 1;\r
- unsigned char : 3;\r
- unsigned char SOPCMTSF : 1;\r
- unsigned char : 3;\r
-#else\r
- unsigned char : 3;\r
- unsigned char SOPCMTSF : 1;\r
- unsigned char : 3;\r
- unsigned char SOPCM : 1;\r
-#endif\r
- } BIT;\r
- } SOPCCR;\r
- char wk12[21];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char IWDTRF : 1;\r
- unsigned char : 1;\r
- unsigned char SWRF : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char SWRF : 1;\r
- unsigned char : 1;\r
- unsigned char IWDTRF : 1;\r
-#endif\r
- } BIT;\r
- } RSTSR2;\r
- char wk13[1];\r
- unsigned short SWRR;\r
- char wk14[28];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LVD1IDTSEL : 2;\r
- unsigned char LVD1IRQSEL : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char LVD1IRQSEL : 1;\r
- unsigned char LVD1IDTSEL : 2;\r
-#endif\r
- } BIT;\r
- } LVD1CR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LVD1DET : 1;\r
- unsigned char LVD1MON : 1;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char LVD1MON : 1;\r
- unsigned char LVD1DET : 1;\r
-#endif\r
- } BIT;\r
- } LVD1SR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LVD2IDTSEL : 2;\r
- unsigned char LVD2IRQSEL : 1;\r
- unsigned char : 5;\r
-#else\r
- unsigned char : 5;\r
- unsigned char LVD2IRQSEL : 1;\r
- unsigned char LVD2IDTSEL : 2;\r
-#endif\r
- } BIT;\r
- } LVD2CR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LVD2DET : 1;\r
- unsigned char LVD2MON : 1;\r
- unsigned char : 6;\r
-#else\r
- unsigned char : 6;\r
- unsigned char LVD2MON : 1;\r
- unsigned char LVD2DET : 1;\r
-#endif\r
- } BIT;\r
- } LVD2SR;\r
- char wk15[794];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PRC0 : 1;\r
- unsigned short PRC1 : 1;\r
- unsigned short PRC2 : 1;\r
- unsigned short PRC3 : 1;\r
- unsigned short : 4;\r
- unsigned short PRKEY : 8;\r
-#else\r
- unsigned short PRKEY : 8;\r
- unsigned short : 4;\r
- unsigned short PRC3 : 1;\r
- unsigned short PRC2 : 1;\r
- unsigned short PRC1 : 1;\r
- unsigned short PRC0 : 1;\r
-#endif\r
- } BIT;\r
- } PRCR;\r
- char wk16[48784];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char PORF : 1;\r
- unsigned char : 1;\r
- unsigned char LVD1RF : 1;\r
- unsigned char LVD2RF : 1;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char LVD2RF : 1;\r
- unsigned char LVD1RF : 1;\r
- unsigned char : 1;\r
- unsigned char PORF : 1;\r
-#endif\r
- } BIT;\r
- } RSTSR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CWSF : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char CWSF : 1;\r
-#endif\r
- } BIT;\r
- } RSTSR1;\r
- char wk17[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 5;\r
- unsigned char MODRV21 : 1;\r
- unsigned char MOSEL : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char MOSEL : 1;\r
- unsigned char MODRV21 : 1;\r
- unsigned char : 5;\r
-#endif\r
- } BIT;\r
- } MOFCR;\r
- char wk18[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 3;\r
- unsigned char EXVCCINP2 : 1;\r
- unsigned char : 1;\r
- unsigned char LVD1E : 1;\r
- unsigned char LVD2E : 1;\r
- unsigned char : 1;\r
-#else\r
- unsigned char : 1;\r
- unsigned char LVD2E : 1;\r
- unsigned char LVD1E : 1;\r
- unsigned char : 1;\r
- unsigned char EXVCCINP2 : 1;\r
- unsigned char : 3;\r
-#endif\r
- } BIT;\r
- } LVCMPCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LVD1LVL : 4;\r
- unsigned char LVD2LVL : 2;\r
- unsigned char : 2;\r
-#else\r
- unsigned char : 2;\r
- unsigned char LVD2LVL : 2;\r
- unsigned char LVD1LVL : 4;\r
-#endif\r
- } BIT;\r
- } LVDLVLR;\r
- char wk19[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LVD1RIE : 1;\r
- unsigned char : 1;\r
- unsigned char LVD1CMPE : 1;\r
- unsigned char : 3;\r
- unsigned char LVD1RI : 1;\r
- unsigned char LVD1RN : 1;\r
-#else\r
- unsigned char LVD1RN : 1;\r
- unsigned char LVD1RI : 1;\r
- unsigned char : 3;\r
- unsigned char LVD1CMPE : 1;\r
- unsigned char : 1;\r
- unsigned char LVD1RIE : 1;\r
-#endif\r
- } BIT;\r
- } LVD1CR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char LVD2RIE : 1;\r
- unsigned char : 1;\r
- unsigned char LVD2CMPE : 1;\r
- unsigned char : 3;\r
- unsigned char LVD2RI : 1;\r
- unsigned char LVD2RN : 1;\r
-#else\r
- unsigned char LVD2RN : 1;\r
- unsigned char LVD2RI : 1;\r
- unsigned char : 3;\r
- unsigned char LVD2CMPE : 1;\r
- unsigned char : 1;\r
- unsigned char LVD2RIE : 1;\r
-#endif\r
- } BIT;\r
- } LVD2CR0;\r
-};\r
-\r
-struct st_temps {\r
- unsigned char TSCDRL;\r
- unsigned char TSCDRH;\r
-};\r
-\r
-struct st_tmr0 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 3;\r
- unsigned char CCLR : 2;\r
- unsigned char OVIE : 1;\r
- unsigned char CMIEA : 1;\r
- unsigned char CMIEB : 1;\r
-#else\r
- unsigned char CMIEB : 1;\r
- unsigned char CMIEA : 1;\r
- unsigned char OVIE : 1;\r
- unsigned char CCLR : 2;\r
- unsigned char : 3;\r
-#endif\r
- } BIT;\r
- } TCR;\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char OSA : 2;\r
- unsigned char OSB : 2;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char OSB : 2;\r
- unsigned char OSA : 2;\r
-#endif\r
- } BIT;\r
- } TCSR;\r
- char wk1[1];\r
- unsigned char TCORA;\r
- char wk2[1];\r
- unsigned char TCORB;\r
- char wk3[1];\r
- unsigned char TCNT;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CKS : 3;\r
- unsigned char CSS : 2;\r
- unsigned char : 2;\r
- unsigned char TMRIS : 1;\r
-#else\r
- unsigned char TMRIS : 1;\r
- unsigned char : 2;\r
- unsigned char CSS : 2;\r
- unsigned char CKS : 3;\r
-#endif\r
- } BIT;\r
- } TCCR;\r
- char wk5[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char TCS : 1;\r
- unsigned char : 7;\r
-#else\r
- unsigned char : 7;\r
- unsigned char TCS : 1;\r
-#endif\r
- } BIT;\r
- } TCSTR;\r
-};\r
-\r
-struct st_tmr1 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char : 3;\r
- unsigned char CCLR : 2;\r
- unsigned char OVIE : 1;\r
- unsigned char CMIEA : 1;\r
- unsigned char CMIEB : 1;\r
-#else\r
- unsigned char CMIEB : 1;\r
- unsigned char CMIEA : 1;\r
- unsigned char OVIE : 1;\r
- unsigned char CCLR : 2;\r
- unsigned char : 3;\r
-#endif\r
- } BIT;\r
- } TCR;\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char OSA : 2;\r
- unsigned char OSB : 2;\r
- unsigned char : 4;\r
-#else\r
- unsigned char : 4;\r
- unsigned char OSB : 2;\r
- unsigned char OSA : 2;\r
-#endif\r
- } BIT;\r
- } TCSR;\r
- char wk1[1];\r
- unsigned char TCORA;\r
- char wk2[1];\r
- unsigned char TCORB;\r
- char wk3[1];\r
- unsigned char TCNT;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned char CKS : 3;\r
- unsigned char CSS : 2;\r
- unsigned char : 2;\r
- unsigned char TMRIS : 1;\r
-#else\r
- unsigned char TMRIS : 1;\r
- unsigned char : 2;\r
- unsigned char CSS : 2;\r
- unsigned char CKS : 3;\r
-#endif\r
- } BIT;\r
- } TCCR;\r
-};\r
-\r
-struct st_tmr01 {\r
- unsigned short TCORA;\r
- unsigned short TCORB;\r
- unsigned short TCNT;\r
- unsigned short TCCR;\r
-};\r
-\r
-struct st_usb0 {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short USBE : 1;\r
- unsigned short : 2;\r
- unsigned short DMRPU : 1;\r
- unsigned short DPRPU : 1;\r
- unsigned short DRPD : 1;\r
- unsigned short DCFM : 1;\r
- unsigned short : 1;\r
- unsigned short CNEN : 1;\r
- unsigned short : 1;\r
- unsigned short SCKE : 1;\r
- unsigned short : 5;\r
-#else\r
- unsigned short : 5;\r
- unsigned short SCKE : 1;\r
- unsigned short : 1;\r
- unsigned short CNEN : 1;\r
- unsigned short : 1;\r
- unsigned short DCFM : 1;\r
- unsigned short DRPD : 1;\r
- unsigned short DPRPU : 1;\r
- unsigned short DMRPU : 1;\r
- unsigned short : 2;\r
- unsigned short USBE : 1;\r
-#endif\r
- } BIT;\r
- } SYSCFG;\r
- char wk0[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short LNST : 2;\r
- unsigned short IDMON : 1;\r
- unsigned short : 3;\r
- unsigned short HTACT : 1;\r
- unsigned short : 7;\r
- unsigned short OVCMON : 2;\r
-#else\r
- unsigned short OVCMON : 2;\r
- unsigned short : 7;\r
- unsigned short HTACT : 1;\r
- unsigned short : 3;\r
- unsigned short IDMON : 1;\r
- unsigned short LNST : 2;\r
-#endif\r
- } BIT;\r
- } SYSSTS0;\r
- char wk1[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short RHST : 3;\r
- unsigned short : 1;\r
- unsigned short UACT : 1;\r
- unsigned short RESUME : 1;\r
- unsigned short USBRST : 1;\r
- unsigned short RWUPE : 1;\r
- unsigned short WKUP : 1;\r
- unsigned short VBUSEN : 1;\r
- unsigned short EXICEN : 1;\r
- unsigned short HNPBTOA : 1;\r
- unsigned short : 4;\r
-#else\r
- unsigned short : 4;\r
- unsigned short HNPBTOA : 1;\r
- unsigned short EXICEN : 1;\r
- unsigned short VBUSEN : 1;\r
- unsigned short WKUP : 1;\r
- unsigned short RWUPE : 1;\r
- unsigned short USBRST : 1;\r
- unsigned short RESUME : 1;\r
- unsigned short UACT : 1;\r
- unsigned short : 1;\r
- unsigned short RHST : 3;\r
-#endif\r
- } BIT;\r
- } DVSTCTR0;\r
- char wk2[10];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char L;\r
- unsigned char H;\r
- } BYTE;\r
- } CFIFO;\r
- char wk3[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char L;\r
- unsigned char H;\r
- } BYTE;\r
- } D0FIFO;\r
- char wk4[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char L;\r
- unsigned char H;\r
- } BYTE;\r
- } D1FIFO;\r
- char wk5[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CURPIPE : 4;\r
- unsigned short : 1;\r
- unsigned short ISEL : 1;\r
- unsigned short : 2;\r
- unsigned short BIGEND : 1;\r
- unsigned short : 1;\r
- unsigned short MBW : 1;\r
- unsigned short : 3;\r
- unsigned short REW : 1;\r
- unsigned short RCNT : 1;\r
-#else\r
- unsigned short RCNT : 1;\r
- unsigned short REW : 1;\r
- unsigned short : 3;\r
- unsigned short MBW : 1;\r
- unsigned short : 1;\r
- unsigned short BIGEND : 1;\r
- unsigned short : 2;\r
- unsigned short ISEL : 1;\r
- unsigned short : 1;\r
- unsigned short CURPIPE : 4;\r
-#endif\r
- } BIT;\r
- } CFIFOSEL;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short DTLN : 9;\r
- unsigned short : 4;\r
- unsigned short FRDY : 1;\r
- unsigned short BCLR : 1;\r
- unsigned short BVAL : 1;\r
-#else\r
- unsigned short BVAL : 1;\r
- unsigned short BCLR : 1;\r
- unsigned short FRDY : 1;\r
- unsigned short : 4;\r
- unsigned short DTLN : 9;\r
-#endif\r
- } BIT;\r
- } CFIFOCTR;\r
- char wk6[4];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CURPIPE : 4;\r
- unsigned short : 4;\r
- unsigned short BIGEND : 1;\r
- unsigned short : 1;\r
- unsigned short MBW : 1;\r
- unsigned short : 1;\r
- unsigned short DREQE : 1;\r
- unsigned short DCLRM : 1;\r
- unsigned short REW : 1;\r
- unsigned short RCNT : 1;\r
-#else\r
- unsigned short RCNT : 1;\r
- unsigned short REW : 1;\r
- unsigned short DCLRM : 1;\r
- unsigned short DREQE : 1;\r
- unsigned short : 1;\r
- unsigned short MBW : 1;\r
- unsigned short : 1;\r
- unsigned short BIGEND : 1;\r
- unsigned short : 4;\r
- unsigned short CURPIPE : 4;\r
-#endif\r
- } BIT;\r
- } D0FIFOSEL;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short DTLN : 9;\r
- unsigned short : 4;\r
- unsigned short FRDY : 1;\r
- unsigned short BCLR : 1;\r
- unsigned short BVAL : 1;\r
-#else\r
- unsigned short BVAL : 1;\r
- unsigned short BCLR : 1;\r
- unsigned short FRDY : 1;\r
- unsigned short : 4;\r
- unsigned short DTLN : 9;\r
-#endif\r
- } BIT;\r
- } D0FIFOCTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CURPIPE : 4;\r
- unsigned short : 4;\r
- unsigned short BIGEND : 1;\r
- unsigned short : 1;\r
- unsigned short MBW : 1;\r
- unsigned short : 1;\r
- unsigned short DREQE : 1;\r
- unsigned short DCLRM : 1;\r
- unsigned short REW : 1;\r
- unsigned short RCNT : 1;\r
-#else\r
- unsigned short RCNT : 1;\r
- unsigned short REW : 1;\r
- unsigned short DCLRM : 1;\r
- unsigned short DREQE : 1;\r
- unsigned short : 1;\r
- unsigned short MBW : 1;\r
- unsigned short : 1;\r
- unsigned short BIGEND : 1;\r
- unsigned short : 4;\r
- unsigned short CURPIPE : 4;\r
-#endif\r
- } BIT;\r
- } D1FIFOSEL;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short DTLN : 9;\r
- unsigned short : 4;\r
- unsigned short FRDY : 1;\r
- unsigned short BCLR : 1;\r
- unsigned short BVAL : 1;\r
-#else\r
- unsigned short BVAL : 1;\r
- unsigned short BCLR : 1;\r
- unsigned short FRDY : 1;\r
- unsigned short : 4;\r
- unsigned short DTLN : 9;\r
-#endif\r
- } BIT;\r
- } D1FIFOCTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 8;\r
- unsigned short BRDYE : 1;\r
- unsigned short NRDYE : 1;\r
- unsigned short BEMPE : 1;\r
- unsigned short CTRE : 1;\r
- unsigned short DVSE : 1;\r
- unsigned short SOFE : 1;\r
- unsigned short RSME : 1;\r
- unsigned short VBSE : 1;\r
-#else\r
- unsigned short VBSE : 1;\r
- unsigned short RSME : 1;\r
- unsigned short SOFE : 1;\r
- unsigned short DVSE : 1;\r
- unsigned short CTRE : 1;\r
- unsigned short BEMPE : 1;\r
- unsigned short NRDYE : 1;\r
- unsigned short BRDYE : 1;\r
- unsigned short : 8;\r
-#endif\r
- } BIT;\r
- } INTENB0;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PDDETINTE0 : 1;\r
- unsigned short : 3;\r
- unsigned short SACKE : 1;\r
- unsigned short SIGNE : 1;\r
- unsigned short EOFERRE : 1;\r
- unsigned short : 4;\r
- unsigned short ATTCHE : 1;\r
- unsigned short DTCHE : 1;\r
- unsigned short : 1;\r
- unsigned short BCHGE : 1;\r
- unsigned short OVRCRE : 1;\r
-#else\r
- unsigned short OVRCRE : 1;\r
- unsigned short BCHGE : 1;\r
- unsigned short : 1;\r
- unsigned short DTCHE : 1;\r
- unsigned short ATTCHE : 1;\r
- unsigned short : 4;\r
- unsigned short EOFERRE : 1;\r
- unsigned short SIGNE : 1;\r
- unsigned short SACKE : 1;\r
- unsigned short : 3;\r
- unsigned short PDDETINTE0 : 1;\r
-#endif\r
- } BIT;\r
- } INTENB1;\r
- char wk7[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PIPE0BRDYE : 1;\r
- unsigned short PIPE1BRDYE : 1;\r
- unsigned short PIPE2BRDYE : 1;\r
- unsigned short PIPE3BRDYE : 1;\r
- unsigned short PIPE4BRDYE : 1;\r
- unsigned short PIPE5BRDYE : 1;\r
- unsigned short PIPE6BRDYE : 1;\r
- unsigned short PIPE7BRDYE : 1;\r
- unsigned short PIPE8BRDYE : 1;\r
- unsigned short PIPE9BRDYE : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short PIPE9BRDYE : 1;\r
- unsigned short PIPE8BRDYE : 1;\r
- unsigned short PIPE7BRDYE : 1;\r
- unsigned short PIPE6BRDYE : 1;\r
- unsigned short PIPE5BRDYE : 1;\r
- unsigned short PIPE4BRDYE : 1;\r
- unsigned short PIPE3BRDYE : 1;\r
- unsigned short PIPE2BRDYE : 1;\r
- unsigned short PIPE1BRDYE : 1;\r
- unsigned short PIPE0BRDYE : 1;\r
-#endif\r
- } BIT;\r
- } BRDYENB;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PIPE0NRDYE : 1;\r
- unsigned short PIPE1NRDYE : 1;\r
- unsigned short PIPE2NRDYE : 1;\r
- unsigned short PIPE3NRDYE : 1;\r
- unsigned short PIPE4NRDYE : 1;\r
- unsigned short PIPE5NRDYE : 1;\r
- unsigned short PIPE6NRDYE : 1;\r
- unsigned short PIPE7NRDYE : 1;\r
- unsigned short PIPE8NRDYE : 1;\r
- unsigned short PIPE9NRDYE : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short PIPE9NRDYE : 1;\r
- unsigned short PIPE8NRDYE : 1;\r
- unsigned short PIPE7NRDYE : 1;\r
- unsigned short PIPE6NRDYE : 1;\r
- unsigned short PIPE5NRDYE : 1;\r
- unsigned short PIPE4NRDYE : 1;\r
- unsigned short PIPE3NRDYE : 1;\r
- unsigned short PIPE2NRDYE : 1;\r
- unsigned short PIPE1NRDYE : 1;\r
- unsigned short PIPE0NRDYE : 1;\r
-#endif\r
- } BIT;\r
- } NRDYENB;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PIPE0BEMPE : 1;\r
- unsigned short PIPE1BEMPE : 1;\r
- unsigned short PIPE2BEMPE : 1;\r
- unsigned short PIPE3BEMPE : 1;\r
- unsigned short PIPE4BEMPE : 1;\r
- unsigned short PIPE5BEMPE : 1;\r
- unsigned short PIPE6BEMPE : 1;\r
- unsigned short PIPE7BEMPE : 1;\r
- unsigned short PIPE8BEMPE : 1;\r
- unsigned short PIPE9BEMPE : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short PIPE9BEMPE : 1;\r
- unsigned short PIPE8BEMPE : 1;\r
- unsigned short PIPE7BEMPE : 1;\r
- unsigned short PIPE6BEMPE : 1;\r
- unsigned short PIPE5BEMPE : 1;\r
- unsigned short PIPE4BEMPE : 1;\r
- unsigned short PIPE3BEMPE : 1;\r
- unsigned short PIPE2BEMPE : 1;\r
- unsigned short PIPE1BEMPE : 1;\r
- unsigned short PIPE0BEMPE : 1;\r
-#endif\r
- } BIT;\r
- } BEMPENB;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 4;\r
- unsigned short EDGESTS : 1;\r
- unsigned short : 1;\r
- unsigned short BRDYM : 1;\r
- unsigned short : 1;\r
- unsigned short TRNENSEL : 1;\r
- unsigned short : 7;\r
-#else\r
- unsigned short : 7;\r
- unsigned short TRNENSEL : 1;\r
- unsigned short : 1;\r
- unsigned short BRDYM : 1;\r
- unsigned short : 1;\r
- unsigned short EDGESTS : 1;\r
- unsigned short : 4;\r
-#endif\r
- } BIT;\r
- } SOFCFG;\r
- char wk8[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short CTSQ : 3;\r
- unsigned short VALID : 1;\r
- unsigned short DVSQ : 3;\r
- unsigned short VBSTS : 1;\r
- unsigned short BRDY : 1;\r
- unsigned short NRDY : 1;\r
- unsigned short BEMP : 1;\r
- unsigned short CTRT : 1;\r
- unsigned short DVST : 1;\r
- unsigned short SOFR : 1;\r
- unsigned short RESM : 1;\r
- unsigned short VBINT : 1;\r
-#else\r
- unsigned short VBINT : 1;\r
- unsigned short RESM : 1;\r
- unsigned short SOFR : 1;\r
- unsigned short DVST : 1;\r
- unsigned short CTRT : 1;\r
- unsigned short BEMP : 1;\r
- unsigned short NRDY : 1;\r
- unsigned short BRDY : 1;\r
- unsigned short VBSTS : 1;\r
- unsigned short DVSQ : 3;\r
- unsigned short VALID : 1;\r
- unsigned short CTSQ : 3;\r
-#endif\r
- } BIT;\r
- } INTSTS0;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PDDETINT0 : 1;\r
- unsigned short : 3;\r
- unsigned short SACK : 1;\r
- unsigned short SIGN : 1;\r
- unsigned short EOFERR : 1;\r
- unsigned short : 4;\r
- unsigned short ATTCH : 1;\r
- unsigned short DTCH : 1;\r
- unsigned short : 1;\r
- unsigned short BCHG : 1;\r
- unsigned short OVRCR : 1;\r
-#else\r
- unsigned short OVRCR : 1;\r
- unsigned short BCHG : 1;\r
- unsigned short : 1;\r
- unsigned short DTCH : 1;\r
- unsigned short ATTCH : 1;\r
- unsigned short : 4;\r
- unsigned short EOFERR : 1;\r
- unsigned short SIGN : 1;\r
- unsigned short SACK : 1;\r
- unsigned short : 3;\r
- unsigned short PDDETINT0 : 1;\r
-#endif\r
- } BIT;\r
- } INTSTS1;\r
- char wk9[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PIPE0BRDY : 1;\r
- unsigned short PIPE1BRDY : 1;\r
- unsigned short PIPE2BRDY : 1;\r
- unsigned short PIPE3BRDY : 1;\r
- unsigned short PIPE4BRDY : 1;\r
- unsigned short PIPE5BRDY : 1;\r
- unsigned short PIPE6BRDY : 1;\r
- unsigned short PIPE7BRDY : 1;\r
- unsigned short PIPE8BRDY : 1;\r
- unsigned short PIPE9BRDY : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short PIPE9BRDY : 1;\r
- unsigned short PIPE8BRDY : 1;\r
- unsigned short PIPE7BRDY : 1;\r
- unsigned short PIPE6BRDY : 1;\r
- unsigned short PIPE5BRDY : 1;\r
- unsigned short PIPE4BRDY : 1;\r
- unsigned short PIPE3BRDY : 1;\r
- unsigned short PIPE2BRDY : 1;\r
- unsigned short PIPE1BRDY : 1;\r
- unsigned short PIPE0BRDY : 1;\r
-#endif\r
- } BIT;\r
- } BRDYSTS;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PIPE0NRDY : 1;\r
- unsigned short PIPE1NRDY : 1;\r
- unsigned short PIPE2NRDY : 1;\r
- unsigned short PIPE3NRDY : 1;\r
- unsigned short PIPE4NRDY : 1;\r
- unsigned short PIPE5NRDY : 1;\r
- unsigned short PIPE6NRDY : 1;\r
- unsigned short PIPE7NRDY : 1;\r
- unsigned short PIPE8NRDY : 1;\r
- unsigned short PIPE9NRDY : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short PIPE9NRDY : 1;\r
- unsigned short PIPE8NRDY : 1;\r
- unsigned short PIPE7NRDY : 1;\r
- unsigned short PIPE6NRDY : 1;\r
- unsigned short PIPE5NRDY : 1;\r
- unsigned short PIPE4NRDY : 1;\r
- unsigned short PIPE3NRDY : 1;\r
- unsigned short PIPE2NRDY : 1;\r
- unsigned short PIPE1NRDY : 1;\r
- unsigned short PIPE0NRDY : 1;\r
-#endif\r
- } BIT;\r
- } NRDYSTS;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PIPE0BEMP : 1;\r
- unsigned short PIPE1BEMP : 1;\r
- unsigned short PIPE2BEMP : 1;\r
- unsigned short PIPE3BEMP : 1;\r
- unsigned short PIPE4BEMP : 1;\r
- unsigned short PIPE5BEMP : 1;\r
- unsigned short PIPE6BEMP : 1;\r
- unsigned short PIPE7BEMP : 1;\r
- unsigned short PIPE8BEMP : 1;\r
- unsigned short PIPE9BEMP : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short PIPE9BEMP : 1;\r
- unsigned short PIPE8BEMP : 1;\r
- unsigned short PIPE7BEMP : 1;\r
- unsigned short PIPE6BEMP : 1;\r
- unsigned short PIPE5BEMP : 1;\r
- unsigned short PIPE4BEMP : 1;\r
- unsigned short PIPE3BEMP : 1;\r
- unsigned short PIPE2BEMP : 1;\r
- unsigned short PIPE1BEMP : 1;\r
- unsigned short PIPE0BEMP : 1;\r
-#endif\r
- } BIT;\r
- } BEMPSTS;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short FRNM : 11;\r
- unsigned short : 3;\r
- unsigned short CRCE : 1;\r
- unsigned short OVRN : 1;\r
-#else\r
- unsigned short OVRN : 1;\r
- unsigned short CRCE : 1;\r
- unsigned short : 3;\r
- unsigned short FRNM : 11;\r
-#endif\r
- } BIT;\r
- } FRMNUM;\r
- char wk10[6];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short BMREQUESTTYPE : 8;\r
- unsigned short BREQUEST : 8;\r
-#else\r
- unsigned short BREQUEST : 8;\r
- unsigned short BMREQUESTTYPE : 8;\r
-#endif\r
- } BIT;\r
- } USBREQ;\r
- unsigned short USBVAL;\r
- unsigned short USBINDX;\r
- unsigned short USBLENG;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 4;\r
- unsigned short DIR : 1;\r
- unsigned short : 2;\r
- unsigned short SHTNAK : 1;\r
- unsigned short : 8;\r
-#else\r
- unsigned short : 8;\r
- unsigned short SHTNAK : 1;\r
- unsigned short : 2;\r
- unsigned short DIR : 1;\r
- unsigned short : 4;\r
-#endif\r
- } BIT;\r
- } DCPCFG;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short MXPS : 7;\r
- unsigned short : 5;\r
- unsigned short DEVSEL : 4;\r
-#else\r
- unsigned short DEVSEL : 4;\r
- unsigned short : 5;\r
- unsigned short MXPS : 7;\r
-#endif\r
- } BIT;\r
- } DCPMAXP;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PID : 2;\r
- unsigned short CCPL : 1;\r
- unsigned short : 2;\r
- unsigned short PBUSY : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short : 2;\r
- unsigned short SUREQCLR : 1;\r
- unsigned short : 2;\r
- unsigned short SUREQ : 1;\r
- unsigned short BSTS : 1;\r
-#else\r
- unsigned short BSTS : 1;\r
- unsigned short SUREQ : 1;\r
- unsigned short : 2;\r
- unsigned short SUREQCLR : 1;\r
- unsigned short : 2;\r
- unsigned short SQCLR : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short PBUSY : 1;\r
- unsigned short : 2;\r
- unsigned short CCPL : 1;\r
- unsigned short PID : 2;\r
-#endif\r
- } BIT;\r
- } DCPCTR;\r
- char wk11[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PIPESEL : 4;\r
- unsigned short : 12;\r
-#else\r
- unsigned short : 12;\r
- unsigned short PIPESEL : 4;\r
-#endif\r
- } BIT;\r
- } PIPESEL;\r
- char wk12[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short EPNUM : 4;\r
- unsigned short DIR : 1;\r
- unsigned short : 2;\r
- unsigned short SHTNAK : 1;\r
- unsigned short : 1;\r
- unsigned short DBLB : 1;\r
- unsigned short BFRE : 1;\r
- unsigned short : 3;\r
- unsigned short TYPE : 2;\r
-#else\r
- unsigned short TYPE : 2;\r
- unsigned short : 3;\r
- unsigned short BFRE : 1;\r
- unsigned short DBLB : 1;\r
- unsigned short : 1;\r
- unsigned short SHTNAK : 1;\r
- unsigned short : 2;\r
- unsigned short DIR : 1;\r
- unsigned short EPNUM : 4;\r
-#endif\r
- } BIT;\r
- } PIPECFG;\r
- char wk13[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short MXPS : 9;\r
- unsigned short : 3;\r
- unsigned short DEVSEL : 4;\r
-#else\r
- unsigned short DEVSEL : 4;\r
- unsigned short : 3;\r
- unsigned short MXPS : 9;\r
-#endif\r
- } BIT;\r
- } PIPEMAXP;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short IITV : 3;\r
- unsigned short : 9;\r
- unsigned short IFIS : 1;\r
- unsigned short : 3;\r
-#else\r
- unsigned short : 3;\r
- unsigned short IFIS : 1;\r
- unsigned short : 9;\r
- unsigned short IITV : 3;\r
-#endif\r
- } BIT;\r
- } PIPEPERI;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PID : 2;\r
- unsigned short : 3;\r
- unsigned short PBUSY : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short ATREPM : 1;\r
- unsigned short : 3;\r
- unsigned short INBUFM : 1;\r
- unsigned short BSTS : 1;\r
-#else\r
- unsigned short BSTS : 1;\r
- unsigned short INBUFM : 1;\r
- unsigned short : 3;\r
- unsigned short ATREPM : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short PBUSY : 1;\r
- unsigned short : 3;\r
- unsigned short PID : 2;\r
-#endif\r
- } BIT;\r
- } PIPE1CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PID : 2;\r
- unsigned short : 3;\r
- unsigned short PBUSY : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short ATREPM : 1;\r
- unsigned short : 3;\r
- unsigned short INBUFM : 1;\r
- unsigned short BSTS : 1;\r
-#else\r
- unsigned short BSTS : 1;\r
- unsigned short INBUFM : 1;\r
- unsigned short : 3;\r
- unsigned short ATREPM : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short PBUSY : 1;\r
- unsigned short : 3;\r
- unsigned short PID : 2;\r
-#endif\r
- } BIT;\r
- } PIPE2CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PID : 2;\r
- unsigned short : 3;\r
- unsigned short PBUSY : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short ATREPM : 1;\r
- unsigned short : 3;\r
- unsigned short INBUFM : 1;\r
- unsigned short BSTS : 1;\r
-#else\r
- unsigned short BSTS : 1;\r
- unsigned short INBUFM : 1;\r
- unsigned short : 3;\r
- unsigned short ATREPM : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short PBUSY : 1;\r
- unsigned short : 3;\r
- unsigned short PID : 2;\r
-#endif\r
- } BIT;\r
- } PIPE3CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PID : 2;\r
- unsigned short : 3;\r
- unsigned short PBUSY : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short ATREPM : 1;\r
- unsigned short : 3;\r
- unsigned short INBUFM : 1;\r
- unsigned short BSTS : 1;\r
-#else\r
- unsigned short BSTS : 1;\r
- unsigned short INBUFM : 1;\r
- unsigned short : 3;\r
- unsigned short ATREPM : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short PBUSY : 1;\r
- unsigned short : 3;\r
- unsigned short PID : 2;\r
-#endif\r
- } BIT;\r
- } PIPE4CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PID : 2;\r
- unsigned short : 3;\r
- unsigned short PBUSY : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short ATREPM : 1;\r
- unsigned short : 3;\r
- unsigned short INBUFM : 1;\r
- unsigned short BSTS : 1;\r
-#else\r
- unsigned short BSTS : 1;\r
- unsigned short INBUFM : 1;\r
- unsigned short : 3;\r
- unsigned short ATREPM : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short PBUSY : 1;\r
- unsigned short : 3;\r
- unsigned short PID : 2;\r
-#endif\r
- } BIT;\r
- } PIPE5CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PID : 2;\r
- unsigned short : 3;\r
- unsigned short PBUSY : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short : 5;\r
- unsigned short BSTS : 1;\r
-#else\r
- unsigned short BSTS : 1;\r
- unsigned short : 5;\r
- unsigned short ACLRM : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short PBUSY : 1;\r
- unsigned short : 3;\r
- unsigned short PID : 2;\r
-#endif\r
- } BIT;\r
- } PIPE6CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PID : 2;\r
- unsigned short : 3;\r
- unsigned short PBUSY : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short : 5;\r
- unsigned short BSTS : 1;\r
-#else\r
- unsigned short BSTS : 1;\r
- unsigned short : 5;\r
- unsigned short ACLRM : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short PBUSY : 1;\r
- unsigned short : 3;\r
- unsigned short PID : 2;\r
-#endif\r
- } BIT;\r
- } PIPE7CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PID : 2;\r
- unsigned short : 3;\r
- unsigned short PBUSY : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short : 5;\r
- unsigned short BSTS : 1;\r
-#else\r
- unsigned short BSTS : 1;\r
- unsigned short : 5;\r
- unsigned short ACLRM : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short PBUSY : 1;\r
- unsigned short : 3;\r
- unsigned short PID : 2;\r
-#endif\r
- } BIT;\r
- } PIPE8CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short PID : 2;\r
- unsigned short : 3;\r
- unsigned short PBUSY : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short ACLRM : 1;\r
- unsigned short : 5;\r
- unsigned short BSTS : 1;\r
-#else\r
- unsigned short BSTS : 1;\r
- unsigned short : 5;\r
- unsigned short ACLRM : 1;\r
- unsigned short SQCLR : 1;\r
- unsigned short SQSET : 1;\r
- unsigned short SQMON : 1;\r
- unsigned short PBUSY : 1;\r
- unsigned short : 3;\r
- unsigned short PID : 2;\r
-#endif\r
- } BIT;\r
- } PIPE9CTR;\r
- char wk14[14];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 8;\r
- unsigned short TRCLR : 1;\r
- unsigned short TRENB : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short TRENB : 1;\r
- unsigned short TRCLR : 1;\r
- unsigned short : 8;\r
-#endif\r
- } BIT;\r
- } PIPE1TRE;\r
- unsigned short PIPE1TRN;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 8;\r
- unsigned short TRCLR : 1;\r
- unsigned short TRENB : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short TRENB : 1;\r
- unsigned short TRCLR : 1;\r
- unsigned short : 8;\r
-#endif\r
- } BIT;\r
- } PIPE2TRE;\r
- unsigned short PIPE2TRN;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 8;\r
- unsigned short TRCLR : 1;\r
- unsigned short TRENB : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short TRENB : 1;\r
- unsigned short TRCLR : 1;\r
- unsigned short : 8;\r
-#endif\r
- } BIT;\r
- } PIPE3TRE;\r
- unsigned short PIPE3TRN;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 8;\r
- unsigned short TRCLR : 1;\r
- unsigned short TRENB : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short TRENB : 1;\r
- unsigned short TRCLR : 1;\r
- unsigned short : 8;\r
-#endif\r
- } BIT;\r
- } PIPE4TRE;\r
- unsigned short PIPE4TRN;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 8;\r
- unsigned short TRCLR : 1;\r
- unsigned short TRENB : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short TRENB : 1;\r
- unsigned short TRCLR : 1;\r
- unsigned short : 8;\r
-#endif\r
- } BIT;\r
- } PIPE5TRE;\r
- unsigned short PIPE5TRN;\r
- char wk15[12];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short RPDME0 : 1;\r
- unsigned short IDPSRCE0 : 1;\r
- unsigned short IDMSINKE0 : 1;\r
- unsigned short VDPSRCE0 : 1;\r
- unsigned short IDPSINKE0 : 1;\r
- unsigned short VDMSRCE0 : 1;\r
- unsigned short : 1;\r
- unsigned short BATCHGE0 : 1;\r
- unsigned short CHGDETSTS0 : 1;\r
- unsigned short PDDETSTS0 : 1;\r
- unsigned short : 6;\r
-#else\r
- unsigned short : 6;\r
- unsigned short PDDETSTS0 : 1;\r
- unsigned short CHGDETSTS0 : 1;\r
- unsigned short BATCHGE0 : 1;\r
- unsigned short : 1;\r
- unsigned short VDMSRCE0 : 1;\r
- unsigned short IDPSINKE0 : 1;\r
- unsigned short VDPSRCE0 : 1;\r
- unsigned short IDMSINKE0 : 1;\r
- unsigned short IDPSRCE0 : 1;\r
- unsigned short RPDME0 : 1;\r
-#endif\r
- } BIT;\r
- } USBBCCTRL0;\r
- char wk16[26];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short VDDUSBE : 1;\r
- unsigned short : 15;\r
-#else\r
- unsigned short : 15;\r
- unsigned short VDDUSBE : 1;\r
-#endif\r
- } BIT;\r
- } USBMC;\r
- char wk17[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 6;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 8;\r
-#else\r
- unsigned short : 8;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 6;\r
-#endif\r
- } BIT;\r
- } DEVADD0;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 6;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 8;\r
-#else\r
- unsigned short : 8;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 6;\r
-#endif\r
- } BIT;\r
- } DEVADD1;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 6;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 8;\r
-#else\r
- unsigned short : 8;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 6;\r
-#endif\r
- } BIT;\r
- } DEVADD2;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 6;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 8;\r
-#else\r
- unsigned short : 8;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 6;\r
-#endif\r
- } BIT;\r
- } DEVADD3;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 6;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 8;\r
-#else\r
- unsigned short : 8;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 6;\r
-#endif\r
- } BIT;\r
- } DEVADD4;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- \r
-#ifdef __RX_LITTLE_ENDIAN__\r
- unsigned short : 6;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 8;\r
-#else\r
- unsigned short : 8;\r
- unsigned short USBSPD : 2;\r
- unsigned short : 6;\r
-#endif\r
- } BIT;\r
- } DEVADD5;\r
-};\r
-\r
-enum enum_ir {\r
-IR_BSC_BUSERR=16,IR_FCU_FRDYI=23,\r
-IR_ICU_SWINT=27,\r
-IR_CMT0_CMI0,\r
-IR_CMT1_CMI1,\r
-IR_CMT2_CMI2,\r
-IR_CMT3_CMI3,\r
-IR_CAC_FERRF,IR_CAC_MENDF,IR_CAC_OVFF,\r
-IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,\r
-IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,\r
-IR_DOC_DOPCF=57,\r
-IR_CMPB_CMPB0,IR_CMPB_CMPB1,\r
-IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN,\r
-IR_RTC_CUP,\r
-IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,\r
-IR_ELC_ELSR8I=80,\r
-IR_LVD_LVD1=88,IR_LVD_LVD2,\r
-IR_USB0_USBR0,\r
-IR_RTC_ALM=92,IR_RTC_PRD,\r
-IR_S12AD_S12ADI0=102,IR_S12AD_GBADI,\r
-IR_ELC_ELSR18I=106,\r
-IR_SSI0_SSIF0=108,IR_SSI0_SSIRXI0,IR_SSI0_SSITXI0,\r
-IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,\r
-IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,\r
-IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,\r
-IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,\r
-IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,\r
-IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,\r
-IR_POE_OEI1=170,IR_POE_OEI2,\r
-IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0,\r
-IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1,\r
-IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2,\r
-IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3,\r
-IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2,\r
-IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0,\r
-IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,\r
-IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,\r
-IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6,\r
-IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8,\r
-IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9,\r
-IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3,\r
-IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0\r
-};\r
-\r
-enum enum_dtce {\r
-DTCE_ICU_SWINT=27,\r
-DTCE_CMT0_CMI0,\r
-DTCE_CMT1_CMI1,\r
-DTCE_CMT2_CMI2,\r
-DTCE_CMT3_CMI3,\r
-DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,\r
-DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0,\r
-DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1,\r
-DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD,\r
-DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,\r
-DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI,\r
-DTCE_ELC_ELSR18I=106,\r
-DTCE_SSI0_SSIRXI0=109,DTCE_SSI0_SSITXI0,\r
-DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,\r
-DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1,\r
-DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2,\r
-DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,\r
-DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,\r
-DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,\r
-DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0,\r
-DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1,\r
-DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2,\r
-DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3,\r
-DTCE_SCI2_RXI2=187,DTCE_SCI2_TXI2,\r
-DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0,\r
-DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1,\r
-DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5,\r
-DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6,\r
-DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8,\r
-DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9,\r
-DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12,\r
-DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0\r
-};\r
-\r
-enum enum_ier {\r
-IER_BSC_BUSERR=0x02,\r
-IER_FCU_FRDYI=0x02,\r
-IER_ICU_SWINT=0x03,\r
-IER_CMT0_CMI0=0x03,\r
-IER_CMT1_CMI1=0x03,\r
-IER_CMT2_CMI2=0x03,\r
-IER_CMT3_CMI3=0x03,\r
-IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04,\r
-IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,\r
-IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,\r
-IER_DOC_DOPCF=0x07,\r
-IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07,\r
-IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07,\r
-IER_RTC_CUP=0x07,\r
-IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,\r
-IER_ELC_ELSR8I=0x0A,\r
-IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B,\r
-IER_USB0_USBR0=0x0B,\r
-IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B,\r
-IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C,\r
-IER_ELC_ELSR18I=0x0D,\r
-IER_SSI0_SSIF0=0x0D,IER_SSI0_SSIRXI0=0x0D,IER_SSI0_SSITXI0=0x0D,\r
-IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,\r
-IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,\r
-IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,\r
-IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,\r
-IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,\r
-IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11,\r
-IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,\r
-IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16,\r
-IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16,\r
-IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16,\r
-IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17,\r
-IER_SCI2_ERI2=0x17,IER_SCI2_RXI2=0x17,IER_SCI2_TXI2=0x17,IER_SCI2_TEI2=0x17,\r
-IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B,\r
-IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,\r
-IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C,\r
-IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C,\r
-IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D,\r
-IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D,\r
-IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E,\r
-IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F\r
-};\r
-\r
-enum enum_ipr {\r
-IPR_BSC_BUSERR=0,\r
-IPR_FCU_FRDYI=2,\r
-IPR_ICU_SWINT=3,\r
-IPR_CMT0_CMI0=4,\r
-IPR_CMT1_CMI1=5,\r
-IPR_CMT2_CMI2=6,\r
-IPR_CMT3_CMI3=7,\r
-IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34,\r
-IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38,\r
-IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44,\r
-IPR_DOC_DOPCF=57,\r
-IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59,\r
-IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60,\r
-IPR_RTC_CUP=63,\r
-IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,\r
-IPR_ELC_ELSR8I=80,\r
-IPR_LVD_LVD1=88,IPR_LVD_LVD2=89,\r
-IPR_USB0_USBR0=90,\r
-IPR_RTC_ALM=92,IPR_RTC_PRD=93,\r
-IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103,\r
-IPR_ELC_ELSR18I=106,\r
-IPR_SSI0_SSIF0=108,IPR_SSI0_SSIRXI0=108,IPR_SSI0_SSITXI0=108,\r
-IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118,\r
-IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123,\r
-IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127,\r
-IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133,\r
-IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138,\r
-IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139,\r
-IPR_POE_OEI1=170,IPR_POE_OEI2=171,\r
-IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174,\r
-IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177,\r
-IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180,\r
-IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183,\r
-IPR_SCI2_ERI2=186,IPR_SCI2_RXI2=186,IPR_SCI2_TXI2=186,IPR_SCI2_TEI2=186,\r
-IPR_SCI0_ERI0=214,IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214,\r
-IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218,\r
-IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222,\r
-IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226,\r
-IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230,\r
-IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234,\r
-IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245,\r
-IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249\r
-};\r
-\r
-#define IEN_BSC_BUSERR IEN0\r
-#define IEN_FCU_FRDYI IEN7\r
-#define IEN_ICU_SWINT IEN3\r
-#define IEN_CMT0_CMI0 IEN4\r
-#define IEN_CMT1_CMI1 IEN5\r
-#define IEN_CMT2_CMI2 IEN6\r
-#define IEN_CMT3_CMI3 IEN7\r
-#define IEN_CAC_FERRF IEN0\r
-#define IEN_CAC_MENDF IEN1\r
-#define IEN_CAC_OVFF IEN2\r
-#define IEN_USB0_D0FIFO0 IEN4\r
-#define IEN_USB0_D1FIFO0 IEN5\r
-#define IEN_USB0_USBI0 IEN6\r
-#define IEN_RSPI0_SPEI0 IEN4\r
-#define IEN_RSPI0_SPRI0 IEN5\r
-#define IEN_RSPI0_SPTI0 IEN6\r
-#define IEN_RSPI0_SPII0 IEN7\r
-#define IEN_DOC_DOPCF IEN1\r
-#define IEN_CMPB_CMPB0 IEN2\r
-#define IEN_CMPB_CMPB1 IEN3\r
-#define IEN_CTSU_CTSUWR IEN4\r
-#define IEN_CTSU_CTSURD IEN5\r
-#define IEN_CTSU_CTSUFN IEN6\r
-#define IEN_RTC_CUP IEN7\r
-#define IEN_ICU_IRQ0 IEN0\r
-#define IEN_ICU_IRQ1 IEN1\r
-#define IEN_ICU_IRQ2 IEN2\r
-#define IEN_ICU_IRQ3 IEN3\r
-#define IEN_ICU_IRQ4 IEN4\r
-#define IEN_ICU_IRQ5 IEN5\r
-#define IEN_ICU_IRQ6 IEN6\r
-#define IEN_ICU_IRQ7 IEN7\r
-#define IEN_ELC_ELSR8I IEN0\r
-#define IEN_LVD_LVD1 IEN0\r
-#define IEN_LVD_LVD2 IEN1\r
-#define IEN_USB0_USBR0 IEN2\r
-#define IEN_RTC_ALM IEN4\r
-#define IEN_RTC_PRD IEN5\r
-#define IEN_S12AD_S12ADI0 IEN6\r
-#define IEN_S12AD_GBADI IEN7\r
-#define IEN_ELC_ELSR18I IEN2\r
-#define IEN_SSI0_SSIF0 IEN4\r
-#define IEN_SSI0_SSIRXI0 IEN5\r
-#define IEN_SSI0_SSITXI0 IEN6\r
-#define IEN_MTU0_TGIA0 IEN2\r
-#define IEN_MTU0_TGIB0 IEN3\r
-#define IEN_MTU0_TGIC0 IEN4\r
-#define IEN_MTU0_TGID0 IEN5\r
-#define IEN_MTU0_TCIV0 IEN6\r
-#define IEN_MTU0_TGIE0 IEN7\r
-#define IEN_MTU0_TGIF0 IEN0\r
-#define IEN_MTU1_TGIA1 IEN1\r
-#define IEN_MTU1_TGIB1 IEN2\r
-#define IEN_MTU1_TCIV1 IEN3\r
-#define IEN_MTU1_TCIU1 IEN4\r
-#define IEN_MTU2_TGIA2 IEN5\r
-#define IEN_MTU2_TGIB2 IEN6\r
-#define IEN_MTU2_TCIV2 IEN7\r
-#define IEN_MTU2_TCIU2 IEN0\r
-#define IEN_MTU3_TGIA3 IEN1\r
-#define IEN_MTU3_TGIB3 IEN2\r
-#define IEN_MTU3_TGIC3 IEN3\r
-#define IEN_MTU3_TGID3 IEN4\r
-#define IEN_MTU3_TCIV3 IEN5\r
-#define IEN_MTU4_TGIA4 IEN6\r
-#define IEN_MTU4_TGIB4 IEN7\r
-#define IEN_MTU4_TGIC4 IEN0\r
-#define IEN_MTU4_TGID4 IEN1\r
-#define IEN_MTU4_TCIV4 IEN2\r
-#define IEN_MTU5_TGIU5 IEN3\r
-#define IEN_MTU5_TGIV5 IEN4\r
-#define IEN_MTU5_TGIW5 IEN5\r
-#define IEN_POE_OEI1 IEN2\r
-#define IEN_POE_OEI2 IEN3\r
-#define IEN_TMR0_CMIA0 IEN6\r
-#define IEN_TMR0_CMIB0 IEN7\r
-#define IEN_TMR0_OVI0 IEN0\r
-#define IEN_TMR1_CMIA1 IEN1\r
-#define IEN_TMR1_CMIB1 IEN2\r
-#define IEN_TMR1_OVI1 IEN3\r
-#define IEN_TMR2_CMIA2 IEN4\r
-#define IEN_TMR2_CMIB2 IEN5\r
-#define IEN_TMR2_OVI2 IEN6\r
-#define IEN_TMR3_CMIA3 IEN7\r
-#define IEN_TMR3_CMIB3 IEN0\r
-#define IEN_TMR3_OVI3 IEN1\r
-#define IEN_SCI2_ERI2 IEN2\r
-#define IEN_SCI2_RXI2 IEN3\r
-#define IEN_SCI2_TXI2 IEN4\r
-#define IEN_SCI2_TEI2 IEN5\r
-#define IEN_SCI0_ERI0 IEN6\r
-#define IEN_SCI0_RXI0 IEN7\r
-#define IEN_SCI0_TXI0 IEN0\r
-#define IEN_SCI0_TEI0 IEN1\r
-#define IEN_SCI1_ERI1 IEN2\r
-#define IEN_SCI1_RXI1 IEN3\r
-#define IEN_SCI1_TXI1 IEN4\r
-#define IEN_SCI1_TEI1 IEN5\r
-#define IEN_SCI5_ERI5 IEN6\r
-#define IEN_SCI5_RXI5 IEN7\r
-#define IEN_SCI5_TXI5 IEN0\r
-#define IEN_SCI5_TEI5 IEN1\r
-#define IEN_SCI6_ERI6 IEN2\r
-#define IEN_SCI6_RXI6 IEN3\r
-#define IEN_SCI6_TXI6 IEN4\r
-#define IEN_SCI6_TEI6 IEN5\r
-#define IEN_SCI8_ERI8 IEN6\r
-#define IEN_SCI8_RXI8 IEN7\r
-#define IEN_SCI8_TXI8 IEN0\r
-#define IEN_SCI8_TEI8 IEN1\r
-#define IEN_SCI9_ERI9 IEN2\r
-#define IEN_SCI9_RXI9 IEN3\r
-#define IEN_SCI9_TXI9 IEN4\r
-#define IEN_SCI9_TEI9 IEN5\r
-#define IEN_SCI12_ERI12 IEN6\r
-#define IEN_SCI12_RXI12 IEN7\r
-#define IEN_SCI12_TXI12 IEN0\r
-#define IEN_SCI12_TEI12 IEN1\r
-#define IEN_SCI12_SCIX0 IEN2\r
-#define IEN_SCI12_SCIX1 IEN3\r
-#define IEN_SCI12_SCIX2 IEN4\r
-#define IEN_SCI12_SCIX3 IEN5\r
-#define IEN_RIIC0_EEI0 IEN6\r
-#define IEN_RIIC0_RXI0 IEN7\r
-#define IEN_RIIC0_TXI0 IEN0\r
-#define IEN_RIIC0_TEI0 IEN1\r
-\r
-#define VECT_BSC_BUSERR 16\r
-#define VECT_FCU_FRDYI 23\r
-#define VECT_ICU_SWINT 27\r
-#define VECT_CMT0_CMI0 28\r
-#define VECT_CMT1_CMI1 29\r
-#define VECT_CMT2_CMI2 30\r
-#define VECT_CMT3_CMI3 31\r
-#define VECT_CAC_FERRF 32\r
-#define VECT_CAC_MENDF 33\r
-#define VECT_CAC_OVFF 34\r
-#define VECT_USB0_D0FIFO0 36\r
-#define VECT_USB0_D1FIFO0 37\r
-#define VECT_USB0_USBI0 38\r
-#define VECT_RSPI0_SPEI0 44\r
-#define VECT_RSPI0_SPRI0 45\r
-#define VECT_RSPI0_SPTI0 46\r
-#define VECT_RSPI0_SPII0 47\r
-#define VECT_DOC_DOPCF 57\r
-#define VECT_CMPB_CMPB0 58\r
-#define VECT_CMPB_CMPB1 59\r
-#define VECT_CTSU_CTSUWR 60\r
-#define VECT_CTSU_CTSURD 61\r
-#define VECT_CTSU_CTSUFN 62\r
-#define VECT_RTC_CUP 63\r
-#define VECT_ICU_IRQ0 64\r
-#define VECT_ICU_IRQ1 65\r
-#define VECT_ICU_IRQ2 66\r
-#define VECT_ICU_IRQ3 67\r
-#define VECT_ICU_IRQ4 68\r
-#define VECT_ICU_IRQ5 69\r
-#define VECT_ICU_IRQ6 70\r
-#define VECT_ICU_IRQ7 71\r
-#define VECT_ELC_ELSR8I 80\r
-#define VECT_LVD_LVD1 88\r
-#define VECT_LVD_LVD2 89\r
-#define VECT_USB0_USBR0 90\r
-#define VECT_RTC_ALM 92\r
-#define VECT_RTC_PRD 93\r
-#define VECT_S12AD_S12ADI0 102\r
-#define VECT_S12AD_GBADI 103\r
-#define VECT_ELC_ELSR18I 106\r
-#define VECT_SSI0_SSIF0 108\r
-#define VECT_SSI0_SSIRXI0 109\r
-#define VECT_SSI0_SSITXI0 110\r
-#define VECT_MTU0_TGIA0 114\r
-#define VECT_MTU0_TGIB0 115\r
-#define VECT_MTU0_TGIC0 116\r
-#define VECT_MTU0_TGID0 117\r
-#define VECT_MTU0_TCIV0 118\r
-#define VECT_MTU0_TGIE0 119\r
-#define VECT_MTU0_TGIF0 120\r
-#define VECT_MTU1_TGIA1 121\r
-#define VECT_MTU1_TGIB1 122\r
-#define VECT_MTU1_TCIV1 123\r
-#define VECT_MTU1_TCIU1 124\r
-#define VECT_MTU2_TGIA2 125\r
-#define VECT_MTU2_TGIB2 126\r
-#define VECT_MTU2_TCIV2 127\r
-#define VECT_MTU2_TCIU2 128\r
-#define VECT_MTU3_TGIA3 129\r
-#define VECT_MTU3_TGIB3 130\r
-#define VECT_MTU3_TGIC3 131\r
-#define VECT_MTU3_TGID3 132\r
-#define VECT_MTU3_TCIV3 133\r
-#define VECT_MTU4_TGIA4 134\r
-#define VECT_MTU4_TGIB4 135\r
-#define VECT_MTU4_TGIC4 136\r
-#define VECT_MTU4_TGID4 137\r
-#define VECT_MTU4_TCIV4 138\r
-#define VECT_MTU5_TGIU5 139\r
-#define VECT_MTU5_TGIV5 140\r
-#define VECT_MTU5_TGIW5 141\r
-#define VECT_POE_OEI1 170\r
-#define VECT_POE_OEI2 171\r
-#define VECT_TMR0_CMIA0 174\r
-#define VECT_TMR0_CMIB0 175\r
-#define VECT_TMR0_OVI0 176\r
-#define VECT_TMR1_CMIA1 177\r
-#define VECT_TMR1_CMIB1 178\r
-#define VECT_TMR1_OVI1 179\r
-#define VECT_TMR2_CMIA2 180\r
-#define VECT_TMR2_CMIB2 181\r
-#define VECT_TMR2_OVI2 182\r
-#define VECT_TMR3_CMIA3 183\r
-#define VECT_TMR3_CMIB3 184\r
-#define VECT_TMR3_OVI3 185\r
-#define VECT_SCI2_ERI2 186\r
-#define VECT_SCI2_RXI2 187\r
-#define VECT_SCI2_TXI2 188\r
-#define VECT_SCI2_TEI2 189\r
-#define VECT_SCI0_ERI0 214\r
-#define VECT_SCI0_RXI0 215\r
-#define VECT_SCI0_TXI0 216\r
-#define VECT_SCI0_TEI0 217\r
-#define VECT_SCI1_ERI1 218\r
-#define VECT_SCI1_RXI1 219\r
-#define VECT_SCI1_TXI1 220\r
-#define VECT_SCI1_TEI1 221\r
-#define VECT_SCI5_ERI5 222\r
-#define VECT_SCI5_RXI5 223\r
-#define VECT_SCI5_TXI5 224\r
-#define VECT_SCI5_TEI5 225\r
-#define VECT_SCI6_ERI6 226\r
-#define VECT_SCI6_RXI6 227\r
-#define VECT_SCI6_TXI6 228\r
-#define VECT_SCI6_TEI6 229\r
-#define VECT_SCI8_ERI8 230\r
-#define VECT_SCI8_RXI8 231\r
-#define VECT_SCI8_TXI8 232\r
-#define VECT_SCI8_TEI8 233\r
-#define VECT_SCI9_ERI9 234\r
-#define VECT_SCI9_RXI9 235\r
-#define VECT_SCI9_TXI9 236\r
-#define VECT_SCI9_TEI9 237\r
-#define VECT_SCI12_ERI12 238\r
-#define VECT_SCI12_RXI12 239\r
-#define VECT_SCI12_TXI12 240\r
-#define VECT_SCI12_TEI12 241\r
-#define VECT_SCI12_SCIX0 242\r
-#define VECT_SCI12_SCIX1 243\r
-#define VECT_SCI12_SCIX2 244\r
-#define VECT_SCI12_SCIX3 245\r
-#define VECT_RIIC0_EEI0 246\r
-#define VECT_RIIC0_RXI0 247\r
-#define VECT_RIIC0_TXI0 248\r
-#define VECT_RIIC0_TEI0 249\r
-\r
-#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28\r
-#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA18\r
-#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17\r
-#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15\r
-#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15\r
-#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14\r
-#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14\r
-#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5\r
-#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5\r
-#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5\r
-#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4\r
-#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4\r
-#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4\r
-#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
-#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
-#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
-#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
-#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
-#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
-#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
-#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
-#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
-#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
-#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23\r
-#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21\r
-#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19\r
-#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17\r
-#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10\r
-#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9\r
-#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6\r
-#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
-#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
-#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27\r
-#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27\r
-#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26\r
-#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26\r
-#define MSTP_IRDA SYSTEM.MSTPCRC.BIT.MSTPC20\r
-#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19\r
-#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0\r
-#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15\r
-#define MSTP_LCDC SYSTEM.MSTPCRD.BIT.MSTPD11\r
-#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10\r
-\r
-#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR\r
-#define _IR( x ) __IR( x )\r
-#define IR( x , y ) _IR( _ ## x ## _ ## y )\r
-#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE\r
-#define _DTCE( x ) __DTCE( x )\r
-#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )\r
-#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x\r
-#define _IEN( x ) __IEN( x )\r
-#define IEN( x , y ) _IEN( _ ## x ## _ ## y )\r
-#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR\r
-#define _IPR( x ) __IPR( x )\r
-#define IPR( x , y ) _IPR( _ ## x ## _ ## y )\r
-#define __VECT( x ) VECT ## x\r
-#define _VECT( x ) __VECT( x )\r
-#define VECT( x , y ) _VECT( _ ## x ## _ ## y )\r
-#define __MSTP( x ) MSTP ## x\r
-#define _MSTP( x ) __MSTP( x )\r
-#define MSTP( x ) _MSTP( _ ## x )\r
-\r
-#define BSC (*(volatile struct st_bsc *)0x81300)\r
-#define CAC (*(volatile struct st_cac *)0x8B000)\r
-#define CMPB (*(volatile struct st_cmpb *)0x8C580)\r
-#define CMT (*(volatile struct st_cmt *)0x88000)\r
-#define CMT0 (*(volatile struct st_cmt0 *)0x88002)\r
-#define CMT1 (*(volatile struct st_cmt0 *)0x88008)\r
-#define CMT2 (*(volatile struct st_cmt0 *)0x88012)\r
-#define CMT3 (*(volatile struct st_cmt0 *)0x88018)\r
-#define CRC (*(volatile struct st_crc *)0x88280)\r
-#define CTSU (*(volatile struct st_ctsu *)0xA0900)\r
-#define DA (*(volatile struct st_da *)0x88040)\r
-#define DOC (*(volatile struct st_doc *)0x8B080)\r
-#define DTC (*(volatile struct st_dtc *)0x82400)\r
-#define ELC (*(volatile struct st_elc *)0x8B100)\r
-#define FLASH (*(volatile struct st_flash *)0x7FC090)\r
-#define ICU (*(volatile struct st_icu *)0x87000)\r
-#define IRDA (*(volatile struct st_irda *)0x88410)\r
-#define IWDT (*(volatile struct st_iwdt *)0x88030)\r
-#define LCDC (*(volatile struct st_lcdc *)0xA0800)\r
-#define LPT (*(volatile struct st_lpt *)0x800B0)\r
-#define MPC (*(volatile struct st_mpc *)0x8C11F)\r
-#define MTU (*(volatile struct st_mtu *)0x8860A)\r
-#define MTU0 (*(volatile struct st_mtu0 *)0x88690)\r
-#define MTU1 (*(volatile struct st_mtu1 *)0x88690)\r
-#define MTU2 (*(volatile struct st_mtu2 *)0x88692)\r
-#define MTU3 (*(volatile struct st_mtu3 *)0x88600)\r
-#define MTU4 (*(volatile struct st_mtu4 *)0x88600)\r
-#define MTU5 (*(volatile struct st_mtu5 *)0x88694)\r
-#define POE (*(volatile struct st_poe *)0x88900)\r
-#define PORT (*(volatile struct st_port *)0x8C121)\r
-#define PORT0 (*(volatile struct st_port0 *)0x8C000)\r
-#define PORT1 (*(volatile struct st_port1 *)0x8C001)\r
-#define PORT2 (*(volatile struct st_port2 *)0x8C002)\r
-#define PORT3 (*(volatile struct st_port3 *)0x8C003)\r
-#define PORT4 (*(volatile struct st_port4 *)0x8C004)\r
-#define PORT5 (*(volatile struct st_port5 *)0x8C005)\r
-#define PORT9 (*(volatile struct st_port9 *)0x8C009)\r
-#define PORTA (*(volatile struct st_porta *)0x8C00A)\r
-#define PORTB (*(volatile struct st_portb *)0x8C00B)\r
-#define PORTC (*(volatile struct st_portc *)0x8C00C)\r
-#define PORTD (*(volatile struct st_portd *)0x8C00D)\r
-#define PORTE (*(volatile struct st_porte *)0x8C00E)\r
-#define PORTF (*(volatile struct st_portf *)0x8C00F)\r
-#define PORTH (*(volatile struct st_porth *)0x8C051)\r
-#define PORTJ (*(volatile struct st_portj *)0x8C012)\r
-#define RIIC0 (*(volatile struct st_riic *)0x88300)\r
-#define RSPI0 (*(volatile struct st_rspi *)0x88380)\r
-#define RTC (*(volatile struct st_rtc *)0x8C400)\r
-#define RTCB (*(volatile struct st_rtcb *)0x8C402)\r
-#define S12AD (*(volatile struct st_s12ad *)0x89000)\r
-#define SCI0 (*(volatile struct st_sci0 *)0x8A000)\r
-#define SCI1 (*(volatile struct st_sci0 *)0x8A020)\r
-#define SCI2 (*(volatile struct st_sci0 *)0x8A040)\r
-#define SCI5 (*(volatile struct st_sci0 *)0x8A0A0)\r
-#define SCI6 (*(volatile struct st_sci0 *)0x8A0C0)\r
-#define SCI8 (*(volatile struct st_sci0 *)0x8A100)\r
-#define SCI9 (*(volatile struct st_sci0 *)0x8A120)\r
-#define SCI12 (*(volatile struct st_sci12 *)0x8B300)\r
-#define SMCI0 (*(volatile struct st_smci *)0x8A000)\r
-#define SMCI1 (*(volatile struct st_smci *)0x8A020)\r
-#define SMCI2 (*(volatile struct st_smci *)0x8A040)\r
-#define SMCI5 (*(volatile struct st_smci *)0x8A0A0)\r
-#define SMCI6 (*(volatile struct st_smci *)0x8A0C0)\r
-#define SMCI8 (*(volatile struct st_smci *)0x8A100)\r
-#define SMCI9 (*(volatile struct st_smci *)0x8A120)\r
-#define SMCI12 (*(volatile struct st_smci *)0x8B300)\r
-#define SSI0 (*(volatile struct st_ssi *)0x8A500)\r
-#define SYSTEM (*(volatile struct st_system *)0x80000)\r
-#define TEMPS (*(volatile struct st_temps *)0x7FC0AC)\r
-#define TMR0 (*(volatile struct st_tmr0 *)0x88200)\r
-#define TMR1 (*(volatile struct st_tmr1 *)0x88201)\r
-#define TMR2 (*(volatile struct st_tmr0 *)0x88210)\r
-#define TMR3 (*(volatile struct st_tmr1 *)0x88211)\r
-#define TMR01 (*(volatile struct st_tmr01 *)0x88204)\r
-#define TMR23 (*(volatile struct st_tmr01 *)0x88214)\r
-#define USB0 (*(volatile struct st_usb0 *)0xA0000)\r
-\r
-#pragma pack()\r
-#endif\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * This project provides two demo applications. A simple blinky style project,\r
- * and a more comprehensive test and demo application. The\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
- * select between the two. The simply blinky demo is implemented and described\r
- * in main_blinky.c. The more comprehensive test and demo application is\r
- * implemented and described in main_full.c.\r
- *\r
- * This file implements the code that is not demo specific, including the\r
- * hardware setup, standard FreeRTOS hook functions, and the ISR hander called\r
- * by the RTOS after interrupt entry (including nesting) has been taken care of.\r
- *\r
- * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON\r
- * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO\r
- * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!\r
- *\r
- */\r
-\r
-/* Scheduler include files. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "semphr.h"\r
-\r
-/* Renesas includes. */\r
-/* Renesas includes. */\r
-#include <rskrx113def.h>\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_sci.h"\r
-\r
-/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
-or 0 to run the more comprehensive test and demo application. */\r
-#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Configure the hardware as necessary to run this demo.\r
- */\r
-static void prvSetupHardware( void );\r
-\r
-/*\r
- * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
- * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
- */\r
-#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
- extern void main_blinky( void );\r
-#else\r
- extern void main_full( void );\r
-#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */\r
-\r
-/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
-within this file. */\r
-void vApplicationMallocFailedHook( void );\r
-void vApplicationIdleHook( void );\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
-void vApplicationTickHook( void );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-int main( void )\r
-{\r
- /* Configure the hardware ready to run the demo. */\r
- prvSetupHardware();\r
-\r
- /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
- of this file. */\r
- #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
- {\r
- main_blinky();\r
- }\r
- #else\r
- {\r
- main_full();\r
- }\r
- #endif\r
-\r
- return 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvSetupHardware( void )\r
-{\r
- /* Set up SCI1 receive buffer */\r
- R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
-\r
- /* Enable SCI1 operations */\r
- R_SCI1_Start();\r
-\r
- LED0 = LED_OFF;\r
- LED1 = LED_OFF;\r
- LED2 = LED_OFF;\r
- LED3 = LED_OFF;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationMallocFailedHook( void )\r
-{\r
- /* Called if a call to pvPortMalloc() fails because there is insufficient\r
- free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
- internally by FreeRTOS API functions that create tasks, queues, software\r
- timers, and semaphores. The size of the FreeRTOS heap is set by the\r
- configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
-\r
- /* Force an assert. */\r
- configASSERT( ( volatile void * ) NULL );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
-{\r
- ( void ) pcTaskName;\r
- ( void ) pxTask;\r
-\r
- /* Run time stack overflow checking is performed if\r
- configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
- function is called if a stack overflow is detected. */\r
-\r
- /* Force an assert. */\r
- configASSERT( ( volatile void * ) NULL );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationIdleHook( void )\r
-{\r
-volatile size_t xFreeHeapSpace;\r
-\r
- /* This is just a trivial example of an idle hook. It is called on each\r
- cycle of the idle task. It must *NOT* attempt to block. In this case the\r
- idle task just queries the amount of FreeRTOS heap that remains. See the\r
- memory management section on the http://www.FreeRTOS.org web site for memory\r
- management options. If there is a lot of heap memory free then the\r
- configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
- RAM. */\r
- xFreeHeapSpace = xPortGetFreeHeapSize();\r
-\r
- /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
- ( void ) xFreeHeapSpace;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationTickHook( void )\r
-{\r
- #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0\r
- {\r
- extern void vFullDemoTickHook( void );\r
-\r
- vFullDemoTickHook();\r
- }\r
- #endif\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The RX port uses this callback function to configure its tick interrupt.\r
-This allows the application to choose the tick interrupt source. */\r
-void vApplicationSetupTimerInterrupt( void )\r
-{\r
-const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL;\r
-\r
- /* Disable register write protection. */\r
- SYSTEM.PRCR.WORD = ulEnableRegisterWrite;\r
-\r
- /* Enable compare match timer 0. */\r
- MSTP( CMT0 ) = 0;\r
-\r
- /* Interrupt on compare match. */\r
- CMT0.CMCR.BIT.CMIE = 1;\r
-\r
- /* Set the compare match value. */\r
- CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 );\r
-\r
- /* Divide the PCLK by 8. */\r
- CMT0.CMCR.BIT.CKS = 0;\r
-\r
- /* Enable the interrupt... */\r
- _IEN( _CMT0_CMI0 ) = 1;\r
-\r
- /* ...and set its priority to the application defined kernel priority. */\r
- _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;\r
-\r
- /* Start the timer. */\r
- CMT.CMSTR0.BIT.STR0 = 1;\r
-\r
- /* Reneable register protection. */\r
- SYSTEM.PRCR.WORD = ulDisableRegisterWrite;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#ifdef __ICCRX__\r
-\r
- #include <intrinsics.h>\r
-\r
- /* Called from the C start up code when compiled with IAR. */\r
- #pragma diag_suppress = Pm011\r
- int __low_level_init(void)\r
- #pragma diag_default = Pm011\r
- {\r
- extern void R_Systeminit( void );\r
-\r
- __disable_interrupt();\r
- R_Systeminit();\r
-\r
- return (int)(1U);\r
- }\r
-\r
-#endif /* __ICCRX__ */\r
-\r
-\r
-\r
+++ /dev/null
-/*******************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only \r
-* intended for use with Renesas products. No other uses are authorized. This \r
-* software is owned by Renesas Electronics Corporation and is protected under \r
-* all applicable laws, including copyright laws.\r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING \r
-* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT \r
-* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE \r
-* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
-* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
-* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
-* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR \r
-* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE \r
-* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software \r
-* and to discontinue the availability of this software. By using this software,\r
-* you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.\r
-*******************************************************************************/\r
-/*******************************************************************************\r
-* File Name : rskrx113def.h\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* H/W Platform : RSKRX113\r
-* Description : Defines macros relating to the RSK user LEDs and switches\r
-* Creation Date: 26/08/2014\r
-*******************************************************************************/\r
-\r
-\r
-#ifndef RSKRX113_H\r
-#define RSKRX113_H\r
-\r
-/*******************************************************************************\r
-User Defines\r
-*******************************************************************************/\r
-/* General Values */\r
-#define LED_ON (0)\r
-#define LED_OFF (1)\r
-#define SET_BIT_HIGH (1)\r
-#define SET_BIT_LOW (0)\r
-#define SET_BYTE_HIGH (0xFF)\r
-#define SET_BYTE_LOW (0x00)\r
-\r
-/* Switches */\r
-#define SW1 (PORTJ.PIDR.BIT.B0)\r
-#define SW2 (PORT3.PIDR.BIT.B2)\r
-#define SW3 (PORT2.PIDR.BIT.B7)\r
-\r
-/* LED port settings */\r
-#define LED0 (PORT2.PODR.BIT.B2)\r
-#define LED1 (PORT2.PODR.BIT.B3)\r
-#define LED2 (PORT2.PODR.BIT.B4)\r
-#define LED3 (PORT2.PODR.BIT.B5)\r
-\r
-\r
-#endif\r
-\r
+++ /dev/null
-<?xml version="1.0" encoding="ASCII"?>\r
-<com.renesas.linkersection.model:SectionContainer xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:com.renesas.linkersection.model="http:///LinkerSection.ecore">\r
- <sections name="SU">\r
- <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4096"/>\r
- </sections>\r
- <sections name="SI"/>\r
- <sections name="B_1"/>\r
- <sections name="R_1"/>\r
- <sections name="B_2"/>\r
- <sections name="R_2"/>\r
- <sections name="B"/>\r
- <sections name="R"/>\r
- <sections name="PResetPRG">\r
- <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294443008"/>\r
- </sections>\r
- <sections name="C_1"/>\r
- <sections name="C_2"/>\r
- <sections name="C"/>\r
- <sections name="C$*"/>\r
- <sections name="D*"/>\r
- <sections name="W*"/>\r
- <sections name="L"/>\r
- <sections name="PIntPRG"/>\r
- <sections name="P"/>\r
- <sections name="FIXEDVECT">\r
- <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4294967248"/>\r
- <contents xsi:type="com.renesas.linkersection.model:WildCardExpression" name="FIXEDVECT"/>\r
- </sections>\r
-</com.renesas.linkersection.model:SectionContainer>\r
+++ /dev/null
-<?xml version="1.0" encoding="ASCII"?>\r
-<com.renesas.linkersection.model:SectionContainer xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:com.renesas.linkersection.model="http:///LinkerSection.ecore">\r
- <sections name="SU">\r
- <sectionAddress xsi:type="com.renesas.linkersection.model:FixedAddress" fixedAddress="4096"/>\r
- </sections>\r
- <sections name="SI"/>\r
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- </DataElement>\r
- <DataElement key="sck12condition" value="0">\r
- </DataElement>\r
- <DataElement key="sck12condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq0condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="irq0condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="ss12#condition" value="0">\r
- </DataElement>\r
- <DataElement key="ss12#condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="ss5#condition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="ss5#condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="cts12#condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="cts12#condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sscl5condition" value="0">\r
- </DataElement>\r
- <DataElement key="mtclkacondition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtclkacondition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="txd12condition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="txd12condition_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="ss5#condition" value="0">\r
- </DataElement>\r
- <DataElement key="ss1#condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="ss1#condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sscl12condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="sscl12condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc0acondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="irq2condition_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq7condition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="irq7condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="cacrefcondition" value="0">\r
- </DataElement>\r
- <DataElement key="cacrefcondition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc4dcondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc4dcondition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mosiacondition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mosiacondition_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="poe3#condition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="poe3#condition_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="ssda1condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="ssda1condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="rspckacondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="rspckacondition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sclcondition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="sclcondition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="ss5#condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="ss5#condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="txdx12condition" value="0">\r
- </DataElement>\r
- <DataElement key="txdx12condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtic5vcondition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtic5vcondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq0condition" value="0">\r
- </DataElement>\r
- <DataElement key="irq0condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq1condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="irq1condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="ssda1condition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="txd5condition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="txd5condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtic5ucondition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtic5ucondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="cts5#condition" value="0">\r
- </DataElement>\r
- <DataElement key="cts5#condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3bcondition" value="0">\r
- </DataElement>\r
- <DataElement key="mtioc3bcondition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="rts1#condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="rts1#condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc4ccondition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc4ccondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="ssla0condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="ssla0condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="txdx12condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="txdx12condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="smiso5condition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="smiso5condition_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="smiso1condition" value="0">\r
- </DataElement>\r
- <DataElement key="smiso1condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sck12condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="sck12condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3acondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3acondition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc4ccondition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc4ccondition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq6condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="irq6condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc4bcondition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc4bcondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc0acondition" value="0">\r
- </DataElement>\r
- <DataElement key="mtioc0acondition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="rxd1condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="rxd1condition_macroname_macroname_MacroName" value="sci1">\r
- </DataElement>\r
- <DataElement key="sck5condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="sck5condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sdacondition" value="0">\r
- </DataElement>\r
- <DataElement key="sdacondition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="rts12#condition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="rts12#condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sdacondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="sdacondition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc2acondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc2acondition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="rxd5condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="rxd5condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="ssda12condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="ssda12condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtclkacondition" value="0">\r
- </DataElement>\r
- <DataElement key="sscl1condition" value="0">\r
- </DataElement>\r
- <DataElement key="sscl1condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq7condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="smiso1condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="smiso1condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3bcondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3bcondition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtic5vcondition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="rxd12condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="rxd12condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq6condition" value="0">\r
- </DataElement>\r
- <DataElement key="irq6condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sscl5condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="ss5#condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc0bcondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="rxd1condition_macroname_macroname_macroname_macroname" value="sci1">\r
- </DataElement>\r
- <DataElement key="rxd1condition_macroname_macroname_macroname_macroname_MacroName" value="SCI1">\r
- </DataElement>\r
- <DataElement key="mtioc1bcondition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc1bcondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtic5wcondition" value="0">\r
- </DataElement>\r
- <DataElement key="mtic5wcondition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="rxdx12condition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="rxdx12condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="txd1condition_macroname_macroname_macroname" value="sci1">\r
- </DataElement>\r
- <DataElement key="txd1condition_macroname_macroname_macroname_MacroName" value="sci1">\r
- </DataElement>\r
- <DataElement key="mtioc4dcondition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="irq0condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="rts12#condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="txd1condition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="txd1condition_macroname_MacroName" value="sci1">\r
- </DataElement>\r
- <DataElement key="mtioc2bcondition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc2bcondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="ssda5condition" value="0">\r
- </DataElement>\r
- <DataElement key="ssda5condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="smosi12condition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="smosi12condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="smiso12condition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="smiso12condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sck12condition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtclkbcondition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtclkbcondition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="smiso1condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc0bcondition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc2bcondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc2bcondition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="rts5#condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="rts5#condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="txdx12condition_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq7condition" value="0">\r
- </DataElement>\r
- <DataElement key="rxd1condition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="smosi5condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="smosi5condition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3dcondition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3dcondition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="ssda5condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc0ccondition" value="0">\r
- </DataElement>\r
- <DataElement key="mtioc0ccondition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="rtcoutcondition" value="0">\r
- </DataElement>\r
- <DataElement key="sck1condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtclkdcondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq3condition" value="0">\r
- </DataElement>\r
- <DataElement key="irq3condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3acondition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3acondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sck5condition" value="0">\r
- </DataElement>\r
- <DataElement key="sck5condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="txd12condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sscl5condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="sscl5condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3ccondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3ccondition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc0dcondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc0dcondition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc0dcondition_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc2bcondition" value="0">\r
- </DataElement>\r
- <DataElement key="mtioc2bcondition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtclkccondition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtclkccondition_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="cts1#condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="cts1#condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="cts5#condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="smosi1condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="smosi1condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="smosi1condition" value="0">\r
- </DataElement>\r
- <DataElement key="smosi1condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc0dcondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sck1condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc4bcondition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="txd12condition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtclkccondition" value="0">\r
- </DataElement>\r
- <DataElement key="mtclkccondition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="smiso12condition" value="0">\r
- </DataElement>\r
- <DataElement key="mtioc3ccondition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3ccondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sck5condition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc1bcondition" value="0">\r
- </DataElement>\r
- <DataElement key="mtioc1bcondition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq7condition_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc3ccondition" value="0">\r
- </DataElement>\r
- <DataElement key="mtioc3ccondition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtclkbcondition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="adtrg0#condition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="adtrg0#condition_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="rts5#condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="rts5#condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq4condition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtclkccondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc1acondition_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc1acondition_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sck1condition" value="0">\r
- </DataElement>\r
- <DataElement key="sck1condition_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="poe3#condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc4acondition_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="mtioc4acondition_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="sdacondition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="sdacondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtic5vcondition" value="0">\r
- </DataElement>\r
- <DataElement key="ssda5condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="ssda5condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="txd5condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="txd5condition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="misoacondition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
- <DataElement key="misoacondition_macroname_macroname_macroname_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="irq4condition_macroname" value="">\r
- </DataElement>\r
- <DataElement key="irq4condition_macroname_MacroName" value="">\r
- </DataElement>\r
- <DataElement key="mtioc0bcondition" value="0">\r
- </DataElement>\r
- <DataElement key="rxd5condition_macroname_macroname_macroname_macroname" value="">\r
- </DataElement>\r
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- </DataElement>\r
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- </SerializableData>\r
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- </SerializableData>\r
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- <DataElement key="PinInOut" value="IO">\r
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- </SerializableData>\r
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- <DataElement key="PinInOut" value="IO">\r
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- <DataElement key="TTLBuffer" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="RTCOUT">\r
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- <DataElement key="PinInOut" value="O">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
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- </SerializableData>\r
- <SerializableData name="TXD1">\r
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- </SerializableData>\r
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- </DataElement>\r
- <DataElement key="PinInOut" value="IO">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
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- <DataElement key="PinInOut" value="IO">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
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- <DataElement key="PinInOut" value="IO">\r
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- <DataElement key="PullUp" value="False">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
- <SerializableData name="SCL0">\r
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- <DataElement key="TTLBuffer" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="USB0_VBUS">\r
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- <DataElement key="TTLBuffer" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="USB0_OVRCURB">\r
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- <DataElement key="TTLBuffer" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="IRQ6">\r
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- <DataElement key="TTLBuffer" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ADTRG0#">\r
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- </DataElement>\r
- <DataElement key="PinInOut" value="I">\r
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- <DataElement key="PullUp" value="False">\r
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- <DataElement key="TTLBuffer" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="P15">\r
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- </DataElement>\r
- <DataElement key="PinInOut" value="IO">\r
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- <DataElement key="PullUp" value="False">\r
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- <DataElement key="TTLBuffer" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="MTCLKB">\r
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- </DataElement>\r
- <DataElement key="PinInOut" value="I">\r
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- <DataElement key="PullUp" value="False">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
- <SerializableData name="RXD1">\r
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- <DataElement key="PinInOut" value="I">\r
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- <DataElement key="PullUp" value="False">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
- <SerializableData name="SMISO1">\r
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- </DataElement>\r
- <DataElement key="PinInOut" value="IO">\r
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- <DataElement key="PullUp" value="False">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
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- <DataElement key="PinInOut" value="IO">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
- <SerializableData name="RSPCKA">\r
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- <DataElement key="PinInOut" value="IO">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
- <SerializableData name="IRQ5">\r
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- </SerializableData>\r
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- </SerializableData>\r
- <SerializableData name="UB#">\r
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- </SerializableData>\r
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- </SerializableData>\r
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- </SerializableData>\r
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- </SerializableData>\r
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- <SerializableData name="USB0_OVRCURA">\r
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- </SerializableData>\r
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- </SerializableData>\r
- <SerializableData name="USB0_DP">\r
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- </SerializableData>\r
- <SerializableData name="VSS_USB">\r
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- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="P13">\r
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- <DataElement key="PinInOut" value="IO">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
- <SerializableData name="MTIOC0B">\r
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- <DataElement key="PinInOut" value="IO">\r
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- <DataElement key="TTLBuffer" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="SEG00">\r
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- </DataElement>\r
- <DataElement key="PinInOut" value="O">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
- <SerializableData name="P12">\r
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- </DataElement>\r
- <DataElement key="PinInOut" value="IO">\r
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- <DataElement key="TTLBuffer" value="False">\r
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- </SerializableData>\r
- <SerializableData name="TMCI1">\r
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- </DataElement>\r
- <DataElement key="PinInOut" value="I">\r
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- <DataElement key="Tag" value="">\r
- </DataElement>\r
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- </DataElement>\r
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- <DataElement key="CustomValid" value="Valid">\r
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- </SerializableData>\r
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- </SerializableData>\r
- <SerializableData name="cmbPOE0mode">\r
- <DataElement key="ContentItemCount" value="4">\r
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- <DataElement key="SelectedContentItem" value="POE0M_0">\r
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- </DataElement>\r
- <DataElement key="Int" value="">\r
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- </DataElement>\r
- <DataElement key="Text" value="On the falling edge of POE0# input">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE0M_0">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
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- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="POE0PIN=_0001_POE_POE0M_SEL_8">\r
- </DataElement>\r
- <DataElement key="Text" value="When POE0# input has been sampled 16 times at PCLK/8 clock pulses and all are low">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE0M_1">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem3">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="POE0PIN=_0002_POE_POE0M_SEL_16">\r
- </DataElement>\r
- <DataElement key="Text" value="When POE0# input has been sampled 16 times at PCLK/16 clock pulses and all are low">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE0M_2">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem4">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="POE0PIN=_0003_POE_POE0M_SEL_128">\r
- </DataElement>\r
- <DataElement key="Text" value="When POE0# input has been sampled 16 times at PCLK/128 clock pulses and all are low">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE0M_3">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- </SerializableData>\r
- <SerializableData name="chkPOE1Input">\r
- <DataElement key="Checked" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="cmbPOE1pin">\r
- <DataElement key="ContentItemCount" value="2">\r
- </DataElement>\r
- <DataElement key="SelectedContentItem" value="PB5">\r
- </DataElement>\r
- <SerializableData name="ContentItem1">\r
- <DataElement key="Pin" value="PB5">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="PB5">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="PB5">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- </SerializableData>\r
- <SerializableData name="ContentItem2">\r
- <DataElement key="Pin" value="P10">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
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- <DataElement key="Attach" value="POE1M_1">\r
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- <DataElement key="CustomInValidMessage" value="">\r
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- <DataElement key="Attach" value="POE1M_2">\r
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- <DataElement key="Text" value="When POE1# input has been sampled 16 times at PCLK/128 clock pulses and all are low">\r
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- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE1M_3">\r
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- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE2M_1">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- </DataElement>\r
- <DataElement key="Tag" value="POE2PIN=_0020_POE_POE2M_SEL_16">\r
- </DataElement>\r
- <DataElement key="Text" value="When POE2# input has been sampled 16 times at PCLK/16 clock pulses and all are low">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE2M_2">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- </SerializableData>\r
- <SerializableData name="ContentItem4">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="POE2PIN=_0030_POE_POE2M_SEL_128">\r
- </DataElement>\r
- <DataElement key="Text" value="When POE2# input has been sampled 16 times at PCLK/128 clock pulses and all are low">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE2M_3">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- </SerializableData>\r
- <SerializableData name="chkPOE3Input">\r
- <DataElement key="Checked" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="cmbPOE3pin">\r
- <DataElement key="ContentItemCount" value="4">\r
- </DataElement>\r
- <DataElement key="SelectedContentItem" value="PB3">\r
- </DataElement>\r
- <SerializableData name="ContentItem1">\r
- <DataElement key="Pin" value="PB3">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="PB3">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="PB3">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem2">\r
- <DataElement key="Pin" value="PE0">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="PE0">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="PE0">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem3">\r
- <DataElement key="Pin" value="P02">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="P02">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="P02">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem4">\r
- <DataElement key="Pin" value="PD4">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="PD4">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="PD4">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- </SerializableData>\r
- <SerializableData name="cmbPOE3mode">\r
- <DataElement key="ContentItemCount" value="4">\r
- </DataElement>\r
- <DataElement key="SelectedContentItem" value="POE3M_0">\r
- </DataElement>\r
- <SerializableData name="ContentItem1">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="POE3PIN=_0000_POE_POE3M_SEL_DEFAULT">\r
- </DataElement>\r
- <DataElement key="Text" value="On the falling edge of POE3# input">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE3M_0">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem2">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="POE3PIN=_0040_POE_POE3M_SEL_8">\r
- </DataElement>\r
- <DataElement key="Text" value="When POE3# input has been sampled 16 times at PCLK/8 clock pulses and all are low">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE3M_1">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem3">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="POE3PIN=_0080_POE_POE3M_SEL_16">\r
- </DataElement>\r
- <DataElement key="Text" value="When POE3# input has been sampled 16 times at PCLK/16 clock pulses and all are low">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE3M_2">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem4">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="POE3PIN=_00C0_POE_POE3M_SEL_128">\r
- </DataElement>\r
- <DataElement key="Text" value="When POE3# input has been sampled 16 times at PCLK/128 clock pulses and all are low">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="POE3M_3">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- </SerializableData>\r
- <SerializableData name="chkOSF1">\r
- <DataElement key="Checked" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="chkOEI1">\r
- <DataElement key="Checked" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="cmbPriority1">\r
- <DataElement key="ContentItemCount" value="16">\r
- </DataElement>\r
- <DataElement key="SelectedContentItem" value="Level15">\r
- </DataElement>\r
- <SerializableData name="ContentItem1">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level0">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 0 (disabled)">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level0">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem2">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level1">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 1">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level1">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem3">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level2">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 2">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level2">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem4">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
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- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level3">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 3">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level3">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem5">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level4">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 4">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level4">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem6">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level5">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 5">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level5">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem7">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level6">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 6">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level6">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem8">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
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- <DataElement key="Tag" value="Int1Priority=Level7">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 7">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level7">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem9">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level8">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 8">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level8">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem10">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level9">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 9">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level9">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem11">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level10">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 10">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level10">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem12">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level11">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 11">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level11">\r
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- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem13">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level12">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 12">\r
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- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level12">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem14">\r
- <DataElement key="Pin" value="">\r
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- <DataElement key="Int" value="">\r
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- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="Int1Priority=Level13">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 13">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="Level13">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
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- </SerializableData>\r
- <SerializableData name="ContentItem15">\r
- <DataElement key="Pin" value="">\r
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- <DataElement key="Int" value="">\r
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- <DataElement key="Tag" value="Int1Priority=Level14">\r
- </DataElement>\r
- <DataElement key="Text" value="Level 14">\r
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- <DataElement key="CustomInValidMessage" value="">\r
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- <DataElement key="Attach" value="Level14">\r
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- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- <SerializableData name="ContentItem16">\r
- <DataElement key="Pin" value="">\r
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- <DataElement key="Fun" value="">\r
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- </DataElement>\r
- <DataElement key="Text" value="Level 15 (highest)">\r
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- <DataElement key="Attach" value="Level15">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- </SerializableData>\r
- <SerializableData name="chkStpOsc">\r
- <DataElement key="Checked" value="False">\r
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- </SerializableData>\r
- </SerializableData>\r
- </SerializableData>\r
- <SerializableData name="RX113_TMR">\r
- <SerializableData name="Tmr0">\r
- <SerializableData name="TmrChannel0">\r
- <SerializableData name="cmbMode">\r
- <DataElement key="ContentItemCount" value="3">\r
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- <DataElement key="SelectedContentItem" value="16bit">\r
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- <SerializableData name="ContentItem1">\r
- <DataElement key="Pin" value="">\r
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- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="Unused">\r
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- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="unused">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem2">\r
- <DataElement key="Pin" value="">\r
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- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="8-bit count mode">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="8bit">\r
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- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem3">\r
- <DataElement key="Pin" value="">\r
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- <DataElement key="Int" value="">\r
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- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="16-bit count mode">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
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- <DataElement key="Attach" value="16bit">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- </SerializableData>\r
- </SerializableData>\r
- <SerializableData name="16bit0">\r
- <SerializableData name="cmbClkSrc">\r
- <DataElement key="ContentItemCount" value="10">\r
- </DataElement>\r
- <DataElement key="SelectedContentItem" value="pclkb1">\r
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- <SerializableData name="ContentItem1">\r
- <DataElement key="Pin" value="">\r
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- </DataElement>\r
- <DataElement key="Text" value="PCLK">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
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- <DataElement key="Attach" value="pclkb1">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- <SerializableData name="ContentItem2">\r
- <DataElement key="Pin" value="">\r
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- <DataElement key="Fun" value="">\r
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- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="PCLK/2">\r
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- <DataElement key="CustomInValidMessage" value="">\r
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- <DataElement key="Attach" value="pclkb2">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- <SerializableData name="ContentItem3">\r
- <DataElement key="Pin" value="">\r
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- </DataElement>\r
- <DataElement key="Text" value="PCLK/8">\r
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- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
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- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="Transmission/reception">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="TR">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- </SerializableData>\r
- <SerializableData name="SCI_SIMPLE_IIC">\r
- <DataElement key="Checked" value="False">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="SCI_SIMPLE_SPI">\r
- <DataElement key="Checked" value="False">\r
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- <SerializableData name="SCI_SIMPLE_SPI_MODE_SELECT">\r
- <DataElement key="ContentItemCount" value="4">\r
- </DataElement>\r
- <DataElement key="SelectedContentItem" value="STR">\r
- </DataElement>\r
- <SerializableData name="ContentItem1">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="Slave transmit/receive">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="STR">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- <SerializableData name="ContentItem2">\r
- <DataElement key="Pin" value="">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="Slave transmit only">\r
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- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
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- </DataElement>\r
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- <DataElement key="Pin" value="">\r
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- <DataElement key="Int" value="">\r
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- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="Master transmit/receive">\r
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- <DataElement key="CustomInValidMessage" value="">\r
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- <DataElement key="Attach" value="MTR">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- <DataElement key="Pin" value="">\r
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- <DataElement key="Tag" value="">\r
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- <DataElement key="Text" value="Master transmit only">\r
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- <DataElement key="CustomInValidMessage" value="">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- </SerializableData>\r
- <SerializableData name="cmbRXPin">\r
- <DataElement key="ContentItemCount" value="3">\r
- </DataElement>\r
- <DataElement key="SelectedContentItem" value="P15">\r
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- <SerializableData name="ContentItem1">\r
- <DataElement key="Pin" value="P15">\r
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- <DataElement key="Int" value="">\r
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- <DataElement key="Fun" value="">\r
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- <DataElement key="Tag" value="">\r
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- <DataElement key="Text" value="P15">\r
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- <DataElement key="CustomInValidMessage" value="">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- </SerializableData>\r
- <SerializableData name="ContentItem2">\r
- <DataElement key="Pin" value="P30">\r
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- <DataElement key="Int" value="">\r
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- <DataElement key="Fun" value="">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- </SerializableData>\r
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- <DataElement key="Pin" value="PC6">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="PC6">\r
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- <DataElement key="CustomInValidMessage" value="">\r
- </DataElement>\r
- <DataElement key="Attach" value="PC6">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
- </SerializableData>\r
- <SerializableData name="cmbSMISOPin">\r
- <DataElement key="ContentItemCount" value="3">\r
- </DataElement>\r
- <DataElement key="SelectedContentItem" value="P15">\r
- </DataElement>\r
- <SerializableData name="ContentItem1">\r
- <DataElement key="Pin" value="P15">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="P15">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="P15 was used as RXD1.">\r
- </DataElement>\r
- <DataElement key="Attach" value="P15">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- <DataElement key="Pin" value="P30">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
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- <DataElement key="Tag" value="">\r
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- <DataElement key="Text" value="P30">\r
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- <DataElement key="CustomInValidMessage" value="">\r
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- <DataElement key="Attach" value="P30">\r
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- <DataElement key="MutexType" value="NoMutex">\r
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- <DataElement key="Visible" value="True">\r
- </DataElement>\r
- <DataElement key="CustomValid" value="Valid">\r
- </DataElement>\r
- </SerializableData>\r
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- <DataElement key="Pin" value="PC6">\r
- </DataElement>\r
- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
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- <DataElement key="Text" value="PC6">\r
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- <DataElement key="CustomInValidMessage" value="">\r
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- <DataElement key="Attach" value="PC6">\r
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- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- <DataElement key="SelectedContentItem" value="P15">\r
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- <DataElement key="Int" value="">\r
- </DataElement>\r
- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
- </DataElement>\r
- <DataElement key="Text" value="P15">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="P15 was used as RXD1.">\r
- </DataElement>\r
- <DataElement key="Attach" value="P15">\r
- </DataElement>\r
- <DataElement key="MutexType" value="NoMutex">\r
- </DataElement>\r
- <DataElement key="Visible" value="True">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- </DataElement>\r
- <DataElement key="Int" value="">\r
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- <DataElement key="Fun" value="">\r
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- <DataElement key="Tag" value="">\r
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- <DataElement key="Text" value="PC6">\r
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- <DataElement key="CustomInValidMessage" value="">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- <SerializableData name="cmbTXPin">\r
- <DataElement key="ContentItemCount" value="4">\r
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- <DataElement key="SelectedContentItem" value="P16">\r
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- <DataElement key="Pin" value="P26">\r
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- <DataElement key="CustomValid" value="Valid">\r
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- <DataElement key="Pin" value="PC7">\r
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- <DataElement key="Text" value="PC7">\r
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- <DataElement key="Fun" value="">\r
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- <SerializableData name="cmbSMOSIPin">\r
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- <SerializableData name="ContentItem1">\r
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- <DataElement key="Fun" value="">\r
- </DataElement>\r
- <DataElement key="Tag" value="">\r
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- <DataElement key="Text" value="P16">\r
- </DataElement>\r
- <DataElement key="CustomInValidMessage" value="P16 was used as TXD1.">\r
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- <SerializableData name="AsynchronousMode_TransmitReceive1">\r
- <SerializableData name="START_BIT_EDGE_LOW_LEVEL">\r
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- <SerializableData name="START_BIT_EDGE_FALLING">\r
- <DataElement key="Checked" value="False">\r
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- </SerializableData>\r
- <SerializableData name="DATA_LENGTH_8_BITS">\r
- <DataElement key="Checked" value="True">\r
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- <SerializableData name="DATA_LENGTH_7_BITS">\r
- <DataElement key="Checked" value="False">\r
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- <SerializableData name="PARITY_NONE">\r
- <DataElement key="Checked" value="True">\r
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- <SerializableData name="PARITY_EVEN">\r
- <DataElement key="Checked" value="False">\r
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- </SerializableData>\r
- <SerializableData name="PARITY_ODD">\r
- <DataElement key="Checked" value="False">\r
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- </SerializableData>\r
- <SerializableData name="STOP_BIT_1">\r
- <DataElement key="Checked" value="True">\r
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- <DataElement key="Text" value="Level 6">\r
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- </DataElement>\r
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-</SerializableData>
\ No newline at end of file
+++ /dev/null
-#\r
-#Wed Nov 19 15:44:46 GMT 2014\r
-CGExist=true\r
+++ /dev/null
-Build\ project\ excluding\ the\ dependencies=false\r
-Re-generate\ and\ use\ dependencies\ during\ project\ build=true\r
-Use\ existing\ dependencies\ during\ project\ build=false\r
-eclipse.preferences.version=1\r
+++ /dev/null
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-</launchConfiguration>\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
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-<listEntry value="4"/>\r
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-</launchConfiguration>\r
+++ /dev/null
-################################################################################\r
-# Automatically-generated file. Do not edit!\r
-################################################################################\r
-\r
-export INC_RX=C:\devtools\Renesas\RX\2_3_0\include
-export RXC_LIB=C:\devtools\Renesas\RX\2_3_0\bin
-export BIN_RX=C:\devtools\Renesas\RX\2_3_0\bin
-PATH := $(PATH):C:\devtools\Renesas\RX\2_3_0\bin
\ No newline at end of file
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * NOTE 1: This project provides two demo applications. A simple blinky style\r
- * project, and a more comprehensive test and demo application. The\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
- * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
- * in main.c. This file implements the simply blinky style version.\r
- *\r
- * NOTE 2: This file only contains the source code that is specific to the\r
- * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
- * required to configure the hardware are defined in main.c.\r
- ******************************************************************************\r
- *\r
- * main_blinky() creates one queue, and two tasks. It then starts the\r
- * scheduler.\r
- *\r
- * The Queue Send Task:\r
- * The queue send task is implemented by the prvQueueSendTask() function in\r
- * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
- * block for 200 milliseconds, before sending the value 100 to the queue that\r
- * was created within main_blinky(). Once the value is sent, the task loops\r
- * back around to block for another 200 milliseconds...and so on.\r
- *\r
- * The Queue Receive Task:\r
- * The queue receive task is implemented by the prvQueueReceiveTask() function\r
- * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
- * blocks on attempts to read data from the queue that was created within\r
- * main_blinky(). When data is received, the task checks the value of the\r
- * data, and if the value equals the expected 100, toggles an LED. The 'block\r
- * time' parameter passed to the queue receive function specifies that the\r
- * task should be held in the Blocked state indefinitely to wait for data to\r
- * be available on the queue. The queue receive task will only leave the\r
- * Blocked state when the queue send task writes to the queue. As the queue\r
- * send task writes to the queue every 200 milliseconds, the queue receive\r
- * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
- * the LED every 200 milliseconds.\r
- */\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "semphr.h"\r
-\r
-/* Renesas includes. */\r
-#include <rskrx113def.h>\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_userdefine.h"\r
-\r
-/* Priorities at which the tasks are created. */\r
-#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-\r
-/* The rate at which data is sent to the queue. The 200ms value is converted\r
-to ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
-\r
-/* The number of items the queue can hold. This is 1 as the receive task\r
-will remove items as they are added, meaning the send task should always find\r
-the queue empty. */\r
-#define mainQUEUE_LENGTH ( 1 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in\r
- * main.c.\r
- */\r
-void main_blinky( void );\r
-\r
-/*\r
- * The tasks as described in the comments at the top of this file.\r
- */\r
-static void prvQueueReceiveTask( void *pvParameters );\r
-static void prvQueueSendTask( void *pvParameters );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The queue used by both tasks. */\r
-static QueueHandle_t xQueue = NULL;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void main_blinky( void )\r
-{\r
- /* Create the queue. */\r
- xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
-\r
- if( xQueue != NULL )\r
- {\r
- /* Start the two tasks as described in the comments at the top of this\r
- file. */\r
- xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
- "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
- configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
- NULL, /* The parameter passed to the task - not used in this case. */\r
- mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
- NULL ); /* The task handle is not required, so NULL is passed. */\r
-\r
- xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
-\r
- /* Start the tasks and timer running. */\r
- vTaskStartScheduler();\r
- }\r
-\r
- /* If all is well, the scheduler will now be running, and the following\r
- line will never be reached. If the following line does execute, then\r
- there was either insufficient FreeRTOS heap memory available for the idle\r
- and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
- User mode. See the memory management section on the FreeRTOS web site for\r
- more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
- mode from which main() is called is set in the C start up code and must be\r
- a privileged mode (not user mode). */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueSendTask( void *pvParameters )\r
-{\r
-TickType_t xNextWakeTime;\r
-const unsigned long ulValueToSend = 100UL;\r
-\r
- /* Remove compiler warning about unused parameter. */\r
- ( void ) pvParameters;\r
-\r
- /* Initialise xNextWakeTime - this only needs to be done once. */\r
- xNextWakeTime = xTaskGetTickCount();\r
-\r
- for( ;; )\r
- {\r
- /* Place this task in the blocked state until it is time to run again. */\r
- vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
-\r
- /* Send to the queue - causing the queue receive task to unblock and\r
- toggle the LED. 0 is used as the block time so the sending operation\r
- will not block - it shouldn't need to block as the queue should always\r
- be empty at this point in the code. */\r
- xQueueSend( xQueue, &ulValueToSend, 0U );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueReceiveTask( void *pvParameters )\r
-{\r
-unsigned long ulReceivedValue;\r
-const unsigned long ulExpectedValue = 100UL;\r
-\r
- /* Remove compiler warning about unused parameter. */\r
- ( void ) pvParameters;\r
-\r
- for( ;; )\r
- {\r
- /* Wait until something arrives in the queue - this task will block\r
- indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
- FreeRTOSConfig.h. */\r
- xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
-\r
- /* To get here something must have been received from the queue, but\r
- is it the expected value? If it is, toggle the LED. */\r
- if( ulReceivedValue == ulExpectedValue )\r
- {\r
- LED0 = !LED0;\r
- ulReceivedValue = 0U;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-\r
-#ifndef FREERTOS_CONFIG_H\r
-#define FREERTOS_CONFIG_H\r
-\r
-/* Hardware specifics. */\r
-#include "iodefine.h"\r
-\r
-/*-----------------------------------------------------------\r
- * Application specific definitions.\r
- *\r
- * These definitions should be adjusted for your particular hardware and\r
- * application requirements.\r
- *\r
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
- *\r
- * See http://www.freertos.org/a00110.html.\r
- *----------------------------------------------------------*/\r
-\r
-#define configUSE_PREEMPTION 1\r
-#define configUSE_IDLE_HOOK 0\r
-#define configUSE_TICK_HOOK 1\r
-#define configCPU_CLOCK_HZ ( 32000000 ) /* Set in mcu_info.h. */\r
-#define configPERIPHERAL_CLOCK_HZ ( 32000000 ) /* Set in muc_info.h. */\r
-#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )\r
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) )\r
-#define configMAX_TASK_NAME_LEN ( 12 )\r
-#define configUSE_TRACE_FACILITY 1\r
-#define configUSE_16_BIT_TICKS 0\r
-#define configIDLE_SHOULD_YIELD 1\r
-#define configUSE_CO_ROUTINES 0\r
-#define configUSE_MUTEXES 1\r
-#define configGENERATE_RUN_TIME_STATS 0\r
-#define configCHECK_FOR_STACK_OVERFLOW 2\r
-#define configUSE_RECURSIVE_MUTEXES 1\r
-#define configQUEUE_REGISTRY_SIZE 0\r
-#define configUSE_MALLOC_FAILED_HOOK 0\r
-#define configUSE_APPLICATION_TASK_TAG 0\r
-#define configUSE_COUNTING_SEMAPHORES 1\r
-\r
-#define configMAX_PRIORITIES ( 7 )\r
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
-\r
-/* Software timer definitions. */\r
-#define configUSE_TIMERS 1\r
-#define configTIMER_TASK_PRIORITY ( 3 )\r
-#define configTIMER_QUEUE_LENGTH 5\r
-#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
-\r
-/* The interrupt priority used by the kernel itself for the tick interrupt and\r
-the pended interrupt. This would normally be the lowest priority. */\r
-#define configKERNEL_INTERRUPT_PRIORITY 1\r
-\r
-/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
-Interrupts that use a priority above this will not be effected by anything the\r
-kernel is doing. */\r
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
-\r
-/* Set the following definitions to 1 to include the API function, or zero\r
-to exclude the API function. */\r
-\r
-#define INCLUDE_vTaskPrioritySet 1\r
-#define INCLUDE_uxTaskPriorityGet 1\r
-#define INCLUDE_vTaskDelete 1\r
-#define INCLUDE_vTaskCleanUpResources 0\r
-#define INCLUDE_vTaskSuspend 1\r
-#define INCLUDE_vTaskDelayUntil 1\r
-#define INCLUDE_vTaskDelay 1\r
-#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
-#define INCLUDE_xTaskGetSchedulerState 1\r
-#define INCLUDE_eTaskGetState 1\r
-#define INCLUDE_xTimerPendFunctionCall 1\r
-\r
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
-\r
-/* The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros\r
-allow the application writer to add additional code before and after the MCU is\r
-placed into the low power state respectively. The implementations provided in\r
-this demo can be extended to save even more power - for example the analog\r
-input used by the low power demo could be switched off in the pre-sleep macro\r
-and back on again in the post sleep macro. */\r
-void vPreSleepProcessing( unsigned long xExpectedIdleTime );\r
-void vPostSleepProcessing( unsigned long xExpectedIdleTime );\r
-#define configPRE_SLEEP_PROCESSING( xExpectedIdleTime ) vPreSleepProcessing( xExpectedIdleTime );\r
-#define configPOST_SLEEP_PROCESSING( xExpectedIdleTime ) vPostSleepProcessing( xExpectedIdleTime );\r
-\r
-/* configTICK_VECTOR must be set to the interrupt vector used by the peripheral\r
-that generates the tick interrupt. */\r
-#define configTICK_VECTOR VECT_CMT0_CMI0\r
-\r
-#endif /* FREERTOS_CONFIG_H */\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*\r
- * This file contains the non-portable and therefore RX62N specific parts of\r
- * the IntQueue standard demo task - namely the configuration of the timers\r
- * that generate the interrupts and the interrupt entry points.\r
- */\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Demo includes. */\r
-#include "IntQueueTimer.h"\r
-#include "IntQueue.h"\r
-\r
-/* Hardware specifics. */\r
-#include "iodefine.h"\r
-\r
-#define tmrTIMER_0_1_FREQUENCY ( 2000UL )\r
-#define tmrTIMER_2_3_FREQUENCY ( 2407UL )\r
-\r
-void vInitialiseTimerForIntQueueTest( void )\r
-{\r
- /* Ensure interrupts do not start until full configuration is complete. */\r
- portENTER_CRITICAL();\r
- {\r
- SYSTEM.PRCR.WORD = 0xa502;\r
-\r
- /* Cascade two 8bit timer channels to generate the interrupts. \r
- 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are\r
- utilised for this test. */\r
-\r
- /* Enable the timers. */\r
- SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;\r
- SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;\r
-\r
- /* Enable compare match A interrupt request. */\r
- TMR0.TCR.BIT.CMIEA = 1;\r
- TMR2.TCR.BIT.CMIEA = 1;\r
-\r
- /* Clear the timer on compare match A. */\r
- TMR0.TCR.BIT.CCLR = 1;\r
- TMR2.TCR.BIT.CCLR = 1;\r
-\r
- /* Set the compare match value. */\r
- TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
- TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );\r
-\r
- /* 16 bit operation ( count from timer 1,2 ). */\r
- TMR0.TCCR.BIT.CSS = 3;\r
- TMR2.TCCR.BIT.CSS = 3;\r
- \r
- /* Use PCLK as the input. */\r
- TMR1.TCCR.BIT.CSS = 1;\r
- TMR3.TCCR.BIT.CSS = 1;\r
- \r
- /* Divide PCLK by 8. */\r
- TMR1.TCCR.BIT.CKS = 2;\r
- TMR3.TCCR.BIT.CKS = 2;\r
-\r
- /* Enable TMR 0, 2 interrupts. */\r
- TMR0.TCR.BIT.CMIEA = 1;\r
- TMR2.TCR.BIT.CMIEA = 1;\r
-\r
- /* Set interrupt priority and enable. */\r
- IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;\r
- IR( TMR0, CMIA0 ) = 0U;\r
- IEN( TMR0, CMIA0 ) = 1U;\r
-\r
- /* Do the same for TMR2, but to vector 129. */\r
- IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;\r
- IR( TMR2, CMIA2 ) = 0U;\r
- IEN( TMR2, CMIA2 ) = 1U;\r
- }\r
- portEXIT_CRITICAL();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#pragma interrupt r_tmr_cmia0_interrupt(vect=VECT(TMR0,CMIA0))\r
-void r_tmr_cmia0_interrupt( void )\r
-{\r
- portYIELD_FROM_ISR( xFirstTimerHandler() );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#pragma interrupt r_tmr_cmia2_interrupt(vect=VECT(TMR2,CMIA2))\r
-void r_tmr_cmia2_interrupt( void )\r
-{\r
- portYIELD_FROM_ISR( xSecondTimerHandler() );\r
-}\r
-\r
-\r
-\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-#ifndef INT_QUEUE_TIMER_H\r
-#define INT_QUEUE_TIMER_H\r
-\r
-void vInitialiseTimerForIntQueueTest( void );\r
-portBASE_TYPE xTimer0Handler( void );\r
-portBASE_TYPE xTimer1Handler( void );\r
-\r
-#endif\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * NOTE 1: This project provides two demo applications. A simple blinky\r
- * style project, and a more comprehensive test and demo application. The\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to\r
- * select between the two. See the notes on using\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the\r
- * comprehensive version.\r
- *\r
- * NOTE 2: This file only contains the source code that is specific to the\r
- * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
- * required to configure the hardware, are defined in main.c.\r
- *\r
- ******************************************************************************\r
- *\r
- * main_full() creates all the demo application tasks and software timers, then\r
- * starts the scheduler. The web documentation provides more details of the\r
- * standard demo application tasks, which provide no particular functionality,\r
- * but do provide a good example of how to use the FreeRTOS API.\r
- *\r
- * In addition to the standard demo tasks, the following tasks and tests are\r
- * defined and/or created within this file:\r
- *\r
- * "Reg test" tasks - These fill both the core and floating point registers with\r
- * known values, then check that each register maintains its expected value for\r
- * the lifetime of the task. Each task uses a different set of values. The reg\r
- * test tasks execute with a very low priority, so get preempted very\r
- * frequently. A register containing an unexpected value is indicative of an\r
- * error in the context switching mechanism.\r
- *\r
- * "Check" task - The check task period is initially set to three seconds. The\r
- * task checks that all the standard demo tasks, and the register check tasks,\r
- * are not only still executing, but are executing without reporting any errors.\r
- * If the check task discovers that a task has either stalled, or reported an\r
- * error, then it changes its own execution period from the initial three\r
- * seconds, to just 200ms. The check task also toggles an LED each time it is\r
- * called. This provides a visual indication of the system status: If the LED\r
- * toggles every three seconds, then no issues have been discovered. If the LED\r
- * toggles every 200ms, then an issue has been discovered with at least one\r
- * task.\r
- */\r
-\r
-/* Standard includes. */\r
-#include <stdio.h>\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "timers.h"\r
-#include "semphr.h"\r
-\r
-/* Standard demo application includes. */\r
-#include "semtest.h"\r
-#include "dynamic.h"\r
-#include "BlockQ.h"\r
-#include "blocktim.h"\r
-#include "countsem.h"\r
-#include "GenQTest.h"\r
-#include "recmutex.h"\r
-#include "death.h"\r
-#include "partest.h"\r
-#include "comtest2.h"\r
-#include "serial.h"\r
-#include "TimerDemo.h"\r
-#include "QueueOverwrite.h"\r
-#include "IntQueue.h"\r
-#include "EventGroupsDemo.h"\r
-#include "TaskNotify.h"\r
-#include "IntSemTest.h"\r
-\r
-/* Renesas includes. */\r
-#include <rskrx113def.h>\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_userdefine.h"\r
-\r
-/* Priorities for the demo application tasks. */\r
-#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
-#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
-#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
-#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL )\r
-#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
-#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )\r
-\r
-/* The priority used by the UART command console task. */\r
-#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )\r
-\r
-/* A block time of zero simply means "don't block". */\r
-#define mainDONT_BLOCK ( 0UL )\r
-\r
-/* The period after which the check timer will expire, in ms, provided no errors\r
-have been reported by any of the standard demo tasks. ms are converted to the\r
-equivalent in ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )\r
-\r
-/* The period at which the check timer will expire, in ms, if an error has been\r
-reported in one of the standard demo tasks. ms are converted to the equivalent\r
-in ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )\r
-\r
-/* Parameters that are passed into the register check tasks solely for the\r
-purpose of ensuring parameters are passed into tasks correctly. */\r
-#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL )\r
-#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL )\r
-\r
-/* The base period used by the timer test tasks. */\r
-#define mainTIMER_TEST_PERIOD ( 50 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Entry point for the comprehensive demo (as opposed to the simple blinky\r
- * demo).\r
- */\r
-void main_full( void );\r
-\r
-/*\r
- * The full demo includes some functionality called from the tick hook.\r
- */\r
-void vFullDemoTickHook( void );\r
-\r
- /*\r
- * The check task, as described at the top of this file.\r
- */\r
-static void prvCheckTask( void *pvParameters );\r
-\r
-/*\r
- * Register check tasks, and the tasks used to write over and check the contents\r
- * of the registers, as described at the top of this file. The nature of these\r
- * files necessitates that they are written in assembly, but the entry points\r
- * are kept in the C file for the convenience of checking the task parameter.\r
- */\r
-static void prvRegTest1Task( void *pvParameters );\r
-static void prvRegTest2Task( void *pvParameters );\r
-static void prvRegTest1Implementation( void );\r
-static void prvRegTest2Implementation( void );\r
-\r
-/*\r
- * A high priority task that does nothing other than execute at a pseudo random\r
- * time to ensure the other test tasks don't just execute in a repeating\r
- * pattern.\r
- */\r
-static void prvPseudoRandomiser( void *pvParameters );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The following two variables are used to communicate the status of the\r
-register check tasks to the check task. If the variables keep incrementing,\r
-then the register check tasks have not discovered any errors. If a variable\r
-stops incrementing, then an error has been found. */\r
-volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
-\r
-/* String for display in the web server. It is set to an error message if the\r
-check task detects an error. */\r
-const char *pcStatusMessage = "All tasks running without error";\r
-/*-----------------------------------------------------------*/\r
-\r
-void main_full( void )\r
-{\r
- /* Start all the other standard demo/test tasks. They have no particular\r
- functionality, but do demonstrate how to use the FreeRTOS API and test the\r
- kernel port. */\r
- vStartInterruptQueueTasks();\r
- vStartDynamicPriorityTasks();\r
- vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
- vCreateBlockTimeTasks();\r
- vStartCountingSemaphoreTasks();\r
- vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
- vStartRecursiveMutexTasks();\r
- vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
- vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
- vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );\r
- vStartEventGroupTasks();\r
- vStartTaskNotifyTask();\r
- vStartInterruptSemaphoreTasks();\r
-\r
- /* Create the register check tasks, as described at the top of this file */\r
- xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
- xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
-\r
- /* Create the task that just adds a little random behaviour. */\r
- xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );\r
-\r
- /* Create the task that performs the 'check' functionality, as described at\r
- the top of this file. */\r
- xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
-\r
- /* The set of tasks created by the following function call have to be\r
- created last as they keep account of the number of tasks they expect to see\r
- running. */\r
- vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
-\r
- /* Start the scheduler. */\r
- vTaskStartScheduler();\r
-\r
- /* If all is well, the scheduler will now be running, and the following\r
- line will never be reached. If the following line does execute, then\r
- there was either insufficient FreeRTOS heap memory available for the idle\r
- and/or timer tasks to be created, or vTaskStartScheduler() was called from\r
- User mode. See the memory management section on the FreeRTOS web site for\r
- more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The\r
- mode from which main() is called is set in the C start up code and must be\r
- a privileged mode (not user mode). */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvCheckTask( void *pvParameters )\r
-{\r
-TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
-TickType_t xLastExecutionTime;\r
-static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
-unsigned long ulErrorFound = pdFALSE;\r
-\r
- /* Just to stop compiler warnings. */\r
- ( void ) pvParameters;\r
-\r
- /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
- works correctly. */\r
- xLastExecutionTime = xTaskGetTickCount();\r
-\r
- /* Cycle for ever, delaying then checking all the other tasks are still\r
- operating without error. The onboard LED is toggled on each iteration.\r
- If an error is detected then the delay period is decreased from\r
- mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
- effect of increasing the rate at which the onboard LED toggles, and in so\r
- doing gives visual feedback of the system status. */\r
- for( ;; )\r
- {\r
- /* Delay until it is time to execute again. */\r
- vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
-\r
- /* Check all the demo tasks (other than the flash tasks) to ensure\r
- that they are all still running, and that none have detected an error. */\r
- if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 0UL;\r
- }\r
-\r
- if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 2UL;\r
- }\r
-\r
- if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 3UL;\r
- }\r
-\r
- if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 4UL;\r
- }\r
-\r
- if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 5UL;\r
- }\r
-\r
- if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 6UL;\r
- }\r
-\r
- if( xIsCreateTaskStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 7UL;\r
- }\r
-\r
- if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 8UL;\r
- }\r
-\r
- if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS )\r
- {\r
- ulErrorFound |= 1UL << 9UL;\r
- }\r
-\r
- if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 10UL;\r
- }\r
-\r
- if( xIsQueueOverwriteTaskStillRunning() != pdPASS )\r
- {\r
- ulErrorFound |= 1UL << 11UL;\r
- }\r
-\r
- if( xAreEventGroupTasksStillRunning() != pdPASS )\r
- {\r
- ulErrorFound |= 1UL << 12UL;\r
- }\r
-\r
- if( xAreTaskNotificationTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 13UL;\r
- }\r
-\r
- if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound |= 1UL << 14UL;\r
- }\r
-\r
- /* Check that the register test 1 task is still running. */\r
- if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
- {\r
- ulErrorFound |= 1UL << 15UL;\r
- }\r
- ulLastRegTest1Value = ulRegTest1LoopCounter;\r
-\r
- /* Check that the register test 2 task is still running. */\r
- if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
- {\r
- ulErrorFound |= 1UL << 16UL;\r
- }\r
- ulLastRegTest2Value = ulRegTest2LoopCounter;\r
-\r
- /* Toggle the check LED to give an indication of the system status. If\r
- the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
- everything is ok. A faster toggle indicates an error. */\r
- LED0 = !LED0;\r
-\r
- if( ulErrorFound != pdFALSE )\r
- {\r
- /* An error has been detected in one of the tasks - flash the LED\r
- at a higher frequency to give visible feedback that something has\r
- gone wrong (it might just be that the loop back connector required\r
- by the comtest tasks has not been fitted). */\r
- xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
- pcStatusMessage = "Error found in at least one task.";\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvPseudoRandomiser( void *pvParameters )\r
-{\r
-const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS );\r
-volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue;\r
-\r
- /* This task does nothing other than ensure there is a little bit of\r
- disruption in the scheduling pattern of the other tasks. Normally this is\r
- done by generating interrupts at pseudo random times. */\r
- for( ;; )\r
- {\r
- ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;\r
- ulValue = ( ulNextRand >> 16UL ) & 0xffUL;\r
-\r
- if( ulValue < ulMinDelay )\r
- {\r
- ulValue = ulMinDelay;\r
- }\r
-\r
- vTaskDelay( ulValue );\r
-\r
- while( ulValue > 0 )\r
- {\r
- nop();\r
- nop();\r
- nop();\r
- nop();\r
- nop();\r
- nop();\r
- nop();\r
- nop();\r
-\r
- ulValue--;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vFullDemoTickHook( void )\r
-{\r
- /* The full demo includes a software timer demo/test that requires\r
- prodding periodically from the tick interrupt. */\r
- vTimerPeriodicISRTests();\r
-\r
- /* Call the periodic queue overwrite from ISR demo. */\r
- vQueueOverwritePeriodicISRDemo();\r
-\r
- /* Call the periodic event group from ISR demo. */\r
- vPeriodicEventGroupsProcessing();\r
-\r
- /* Use task notifications from an interrupt. */\r
- xNotifyTaskFromISR();\r
-\r
- /* Use mutexes from interrupts. */\r
- vInterruptSemaphorePeriodicTest();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This function is explained in the comments at the top of this file. */\r
-static void prvRegTest1Task( void *pvParameters )\r
-{\r
- if( pvParameters != mainREG_TEST_1_PARAMETER )\r
- {\r
- /* The parameter did not contain the expected value. */\r
- for( ;; )\r
- {\r
- /* Stop the tick interrupt so its obvious something has gone wrong. */\r
- taskDISABLE_INTERRUPTS();\r
- }\r
- }\r
-\r
- /* This is an inline asm function that never returns. */\r
- prvRegTest1Implementation();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This function is explained in the comments at the top of this file. */\r
-static void prvRegTest2Task( void *pvParameters )\r
-{\r
- if( pvParameters != mainREG_TEST_2_PARAMETER )\r
- {\r
- /* The parameter did not contain the expected value. */\r
- for( ;; )\r
- {\r
- /* Stop the tick interrupt so its obvious something has gone wrong. */\r
- taskDISABLE_INTERRUPTS();\r
- }\r
- }\r
-\r
- /* This is an inline asm function that never returns. */\r
- prvRegTest2Implementation();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This function is explained in the comments at the top of this file. */\r
-#pragma inline_asm prvRegTest1Implementation\r
-static void prvRegTest1Implementation( void )\r
-{\r
- ; Put a known value in each register.\r
- MOV.L #1, R1\r
- MOV.L #2, R2\r
- MOV.L #3, R3\r
- MOV.L #4, R4\r
- MOV.L #5, R5\r
- MOV.L #6, R6\r
- MOV.L #7, R7\r
- MOV.L #8, R8\r
- MOV.L #9, R9\r
- MOV.L #10, R10\r
- MOV.L #11, R11\r
- MOV.L #12, R12\r
- MOV.L #13, R13\r
- MOV.L #14, R14\r
- MOV.L #15, R15\r
-\r
- ; Loop, checking each itteration that each register still contains the\r
- ; expected value.\r
-TestLoop1:\r
-\r
- ; Push the registers that are going to get clobbered.\r
- PUSHM R14-R15\r
-\r
- ; Increment the loop counter to show this task is still getting CPU time.\r
- MOV.L #_ulRegTest1LoopCounter, R14\r
- MOV.L [ R14 ], R15\r
- ADD #1, R15\r
- MOV.L R15, [ R14 ]\r
-\r
- ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register.\r
- MOV.L #1, R14\r
- MOV.L #0872E0H, R15\r
- MOV.B R14, [R15]\r
- NOP\r
- NOP\r
-\r
- ; Restore the clobbered registers.\r
- POPM R14-R15\r
-\r
- ; Now compare each register to ensure it still contains the value that was\r
- ; set before this loop was entered.\r
- CMP #1, R1\r
- BNE RegTest1Error\r
- CMP #2, R2\r
- BNE RegTest1Error\r
- CMP #3, R3\r
- BNE RegTest1Error\r
- CMP #4, R4\r
- BNE RegTest1Error\r
- CMP #5, R5\r
- BNE RegTest1Error\r
- CMP #6, R6\r
- BNE RegTest1Error\r
- CMP #7, R7\r
- BNE RegTest1Error\r
- CMP #8, R8\r
- BNE RegTest1Error\r
- CMP #9, R9\r
- BNE RegTest1Error\r
- CMP #10, R10\r
- BNE RegTest1Error\r
- CMP #11, R11\r
- BNE RegTest1Error\r
- CMP #12, R12\r
- BNE RegTest1Error\r
- CMP #13, R13\r
- BNE RegTest1Error\r
- CMP #14, R14\r
- BNE RegTest1Error\r
- CMP #15, R15\r
- BNE RegTest1Error\r
-\r
- ; All comparisons passed, start a new itteratio of this loop.\r
- BRA TestLoop1\r
-\r
-RegTest1Error:\r
- ; A compare failed, just loop here so the loop counter stops incrementing\r
- ; causing the check task to indicate the error.\r
- BRA RegTest1Error\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This function is explained in the comments at the top of this file. */\r
-#pragma inline_asm prvRegTest2Implementation\r
-static void prvRegTest2Implementation( void )\r
-{\r
- ; Put a known value in each register.\r
- MOV.L #10, R1\r
- MOV.L #20, R2\r
- MOV.L #30, R3\r
- MOV.L #40, R4\r
- MOV.L #50, R5\r
- MOV.L #60, R6\r
- MOV.L #70, R7\r
- MOV.L #80, R8\r
- MOV.L #90, R9\r
- MOV.L #100, R10\r
- MOV.L #110, R11\r
- MOV.L #120, R12\r
- MOV.L #130, R13\r
- MOV.L #140, R14\r
- MOV.L #150, R15\r
-\r
- ; Loop, checking on each itteration that each register still contains the\r
- ; expected value.\r
-TestLoop2:\r
-\r
- ; Push the registers that are going to get clobbered.\r
- PUSHM R14-R15\r
-\r
- ; Increment the loop counter to show this task is still getting CPU time.\r
- MOV.L #_ulRegTest2LoopCounter, R14\r
- MOV.L [ R14 ], R15\r
- ADD #1, R15\r
- MOV.L R15, [ R14 ]\r
-\r
- ; Restore the clobbered registers.\r
- POPM R14-R15\r
-\r
- CMP #10, R1\r
- BNE RegTest2Error\r
- CMP #20, R2\r
- BNE RegTest2Error\r
- CMP #30, R3\r
- BNE RegTest2Error\r
- CMP #40, R4\r
- BNE RegTest2Error\r
- CMP #50, R5\r
- BNE RegTest2Error\r
- CMP #60, R6\r
- BNE RegTest2Error\r
- CMP #70, R7\r
- BNE RegTest2Error\r
- CMP #80, R8\r
- BNE RegTest2Error\r
- CMP #90, R9\r
- BNE RegTest2Error\r
- CMP #100, R10\r
- BNE RegTest2Error\r
- CMP #110, R11\r
- BNE RegTest2Error\r
- CMP #120, R12\r
- BNE RegTest2Error\r
- CMP #130, R13\r
- BNE RegTest2Error\r
- CMP #140, R14\r
- BNE RegTest2Error\r
- CMP #150, R15\r
- BNE RegTest2Error\r
-\r
- ; All comparisons passed, start a new itteratio of this loop.\r
- BRA TestLoop2\r
-\r
-RegTest2Error:\r
- ; A compare failed, just loop here so the loop counter stops incrementing\r
- ; - causing the check task to indicate the error.\r
- BRA RegTest2Error\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-\r
-\r
-\r
+++ /dev/null
-/*******************************************************************************\r
- * DISCLAIMER\r
- * This software is supplied by Renesas Electronics Corporation and is only\r
- * intended for use with Renesas products. No other uses are authorized. This\r
- * software is owned by Renesas Electronics Corporation and is protected under\r
- * all applicable laws, including copyright laws.\r
- * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
- * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
- * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
- * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
- * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
- * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
- * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
- * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
- * Renesas reserves the right, without notice, to make changes to this software\r
- * and to discontinue the availability of this software. By using this software,\r
- * you agree to the additional terms and conditions found by accessing the\r
- * following link:\r
- * http://www.renesas.com/disclaimer\r
- *******************************************************************************/\r
-/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */\r
-/*******************************************************************************\r
- * File Name : r_rsk_async.c\r
- * Version : 1.00\r
- * Device(s) : R5F51138AxFP\r
- * Tool-Chain : CCRX\r
- * H/W Platform : RSKRX113\r
- * Description : Functions used to send data via the SCI in asynchronous mode\r
- *******************************************************************************/\r
-/*******************************************************************************\r
- * History : 26.08.2014 Ver. 1.00 First Release\r
- *******************************************************************************/\r
-\r
-/*******************************************************************************\r
- System Includes\r
- *******************************************************************************/\r
-/* Following header file provides string type definitions. */\r
-#include <string.h>\r
-\r
-/*******************************************************************************\r
- User Includes (Project Level Includes)\r
- *******************************************************************************/\r
-/* Defines port registers */\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_sci.h"\r
-#include "r_rsk_async.h"\r
-\r
-/*******************************************************************************\r
- User Defines\r
- *******************************************************************************/\r
-\r
-/*******************************************************************************\r
- * Global Variables\r
- *******************************************************************************/\r
-\r
-/* Declaration of the command string to clear the terminal screen */\r
-static const char cmd_clr_scr[] =\r
-{ 27, 91, 50, 74, 0, 27, 91, 72, 0 };\r
-\r
-/*******************************************************************************\r
- * Function Prototypes\r
- *******************************************************************************/\r
-\r
-/* text_write function prototype */\r
-static void text_write (const char * const msg_string);\r
-\r
-/*******************************************************************************\r
- * Function Name: R_ASYNC_Init\r
- * Description : This function initialises the SCI channel connected to the\r
- * RS232 connector on the RSK. The channel is configured for\r
- * transmission and reception, and instructions are sent to the\r
- * terminal.\r
- * Argument : none\r
- * Return value : none\r
- *******************************************************************************/\r
-void R_ASYNC_Init (void)\r
-{\r
-\r
- /* Set up SCI1 receive buffer */\r
- R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
-\r
- /* Enable SCI1 operations */\r
- R_SCI1_Start();\r
-\r
- /* Clear the text on terminal window */\r
- text_write(cmd_clr_scr);\r
-\r
- /* Display splash screen on terminal window */\r
- text_write("Renesas RSKRX113 Async Serial \r\n");\r
-\r
- /* Inform user on how to stop transmission */\r
- text_write("Press 'z' to stop and any key to resume\r\n\n");\r
-}\r
-/*******************************************************************************\r
- * End of function R_ASYNC_Init\r
- *******************************************************************************/\r
-\r
-/*******************************************************************************\r
- * Function Name : text_write\r
- * Description : Transmits null-terminated string.\r
- * Argument : (char*) msg_string - null terminated string\r
- * Return value : None\r
- *******************************************************************************/\r
-static void text_write (const char * const msg_string)\r
-{\r
- R_SCI1_AsyncTransmit((uint8_t *) msg_string, (uint16_t) strlen(msg_string));\r
-}\r
-/*******************************************************************************\r
- * End of function text_write\r
- *******************************************************************************/\r
-\r
+++ /dev/null
-/*******************************************************************************\r
- * DISCLAIMER\r
- * This software is supplied by Renesas Electronics Corporation and is only\r
- * intended for use with Renesas products. No other uses are authorized. This\r
- * software is owned by Renesas Electronics Corporation and is protected under\r
- * all applicable laws, including copyright laws.\r
- * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING\r
- * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT\r
- * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\r
- * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
- * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS\r
- * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE\r
- * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR\r
- * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE\r
- * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
- * Renesas reserves the right, without notice, to make changes to this software\r
- * and to discontinue the availability of this software. By using this software,\r
- * you agree to the additional terms and conditions found by accessing the\r
- * following link:\r
- * http://www.renesas.com/disclaimer\r
- *******************************************************************************/\r
-/* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. */\r
-/*******************************************************************************\r
- * File Name : r_rsk_async.h\r
- * Version : 1.00\r
- * Device(s) : R5F51138AxFP\r
- * Tool-Chain : CCRX\r
- * H/W Platform : RSKRX113\r
- * Description : Functions used to send data via the SCI in asynchronous mode\r
- ******************************************************************************/\r
-/*******************************************************************************\r
- * History : 26.08.2014 Ver. 1.00 First Release\r
- *******************************************************************************/\r
-\r
-/*******************************************************************************\r
- * Macro Definitions\r
- *******************************************************************************/\r
-/* Multiple inclusion prevention macro */\r
-#ifndef R_RSK_ASYNC_H\r
-#define R_RSK_ASYNC_H\r
-\r
-/*******************************************************************************\r
- * Global Function Prototypes\r
- *******************************************************************************/\r
-/* initialise asynchronous transmission*/\r
-void R_ASYNC_Init (void);\r
-\r
-/* End of multiple inclusion prevention macro */\r
-#endif\r
-\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_cgc.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for CGC module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_cgc.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-* Function Name: R_CGC_Create\r
-* Description : This function initializes the clock generator.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_CGC_Create(void)\r
-{\r
- uint32_t sckcr_dummy;\r
- uint32_t w_count;\r
-\r
- /* Set main clock control registers */\r
- SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _20_CGC_MAINOSC_OVER10M;\r
- SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768;\r
-\r
- /* Set main clock operation */\r
- SYSTEM.MOSCCR.BIT.MOSTP = 0U;\r
-\r
- /* Wait for main clock oscillator wait counter overflow */\r
- while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF);\r
-\r
- /* Set system clock */\r
- sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000000_CGC_PCLKB_DIV_1 | _00000000_CGC_ICLK_DIV_1 | \r
- _00000000_CGC_FCLK_DIV_1;\r
- SYSTEM.SCKCR.LONG = sckcr_dummy;\r
-\r
- while (SYSTEM.SCKCR.LONG != sckcr_dummy);\r
-\r
- /* Set PLL circuit */\r
- SYSTEM.PLLCR.WORD = _0002_CGC_PLL_FREQ_DIV_4 | _0F00_CGC_PLL_FREQ_MUL_8;\r
- SYSTEM.PLLCR2.BIT.PLLEN = 0U;\r
-\r
- /* Wait for PLL wait counter overflow */\r
- while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF);\r
-\r
- /* Stop sub-clock */\r
- SYSTEM.SOSCCR.BIT.SOSTP = 1U;\r
-\r
- /* Wait for the register modification to complete */\r
- while (1U != SYSTEM.SOSCCR.BIT.SOSTP);\r
-\r
- /* Stop sub-clock */\r
- RTC.RCR3.BIT.RTCEN = 0U;\r
-\r
- /* Wait for the register modification to complete */\r
- while (0U != RTC.RCR3.BIT.RTCEN);\r
-\r
- /* Wait for 5 sub-clock cycles */\r
- for (w_count = 0U; w_count < _007B_CGC_SUBSTPWT_WAIT; w_count++)\r
- {\r
- nop();\r
- }\r
-\r
- /* Set sub-clock drive capacity */\r
- RTC.RCR3.BIT.RTCDV = 1U;\r
-\r
- /* Wait for the register modification to complete */\r
- while (1U != RTC.RCR3.BIT.RTCDV);\r
-\r
- /* Set sub-clock */\r
- SYSTEM.SOSCCR.BIT.SOSTP = 0U;\r
-\r
- /* Wait for the register modification to complete */\r
- while (0U != SYSTEM.SOSCCR.BIT.SOSTP);\r
-\r
- /* Wait for sub-clock to be stable */\r
- for (w_count = 0U; w_count < _00061A81_CGC_SUBOSCWT_WAIT; w_count++)\r
- {\r
- nop();\r
- }\r
-\r
- /* Set clock source */\r
- SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL;\r
-\r
- while (SYSTEM.SCKCR3.WORD != _0400_CGC_CLOCKSOURCE_PLL);\r
-\r
- /* Set LOCO */\r
- SYSTEM.LOCOCR.BIT.LCSTP = 1U;\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_cgc.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for CGC module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef CGC_H\r
-#define CGC_H\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-/*\r
- System Clock Control Register (SCKCR)\r
-*/\r
-/* Peripheral Module Clock D (PCLKD) */\r
-#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */\r
-#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */\r
-#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */\r
-#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */\r
-#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */\r
-#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */\r
-#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */\r
-/* Peripheral Module Clock B (PCLKB) */\r
-#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */\r
-#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */\r
-#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */\r
-#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */\r
-#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */\r
-#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */\r
-#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */\r
-/* System Clock (ICLK) */\r
-#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */\r
-#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */\r
-#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */\r
-#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */\r
-#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */\r
-#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */\r
-#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */\r
-/* System Clock (FCLK) */\r
-#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */\r
-#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */\r
-#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */\r
-#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */\r
-#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */\r
-#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */\r
-#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */\r
-\r
-/*\r
- System Clock Control Register 3 (SCKCR3)\r
-*/\r
-#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */\r
-#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */\r
-#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */\r
-#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */\r
-#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */\r
-\r
-/*\r
- PLL Control Register (PLLCR)\r
-*/\r
-/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */\r
-#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */\r
-#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */\r
-#define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */\r
-/* Frequency Multiplication Factor Select (STC[5:0]) */\r
-#define _0B00_CGC_PLL_FREQ_MUL_6 (0x0B00U) /* x6 */\r
-#define _0F00_CGC_PLL_FREQ_MUL_8 (0x0F00U) /* x8 */\r
-\r
-/*\r
- USB-dedicated PLL Control Register (UPLLCR)\r
-*/\r
-/* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */\r
-#define _0000_CGC_PLL_UPLIDIV_1 (0x0000U) /* x1 */\r
-#define _0001_CGC_PLL_UPLIDIV_2 (0x0001U) /* x1/2 */\r
-#define _0002_CGC_PLL_UPLIDIV_4 (0x0002U) /* x1/4 */\r
-/* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */\r
-#define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */\r
-#define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */\r
-/* Frequency Multiplication Factor Select (USTC[5:0]) */\r
-#define _0B00_CGC_PLL_USTC_6 (0x0B00U) /* x6 */\r
-#define _0F00_CGC_PLL_USTC_8 (0x0F00U) /* x8 */\r
-\r
-/*\r
- Oscillation Stop Detection Control Register (OSTDCR)\r
-*/\r
-/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */\r
-#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */\r
-#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */\r
-/* Oscillation Stop Detection Function Enable (OSTDE) */\r
-#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */\r
-#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */\r
-\r
-/*\r
- Main Clock Oscillator Wait Control Register (MOSCWTCR)\r
-*/\r
-/* Main Clock Oscillator Wait Time (MSTS[4:0]) */\r
-#define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */\r
-#define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */\r
-#define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */\r
-#define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */\r
-#define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */\r
-#define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */\r
-#define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */\r
-#define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */\r
-\r
-/*\r
- HOCO Wait Control Register (HOCOWTCR)\r
-*/\r
-/* HOCO Wait Time (HOCOWTCR) */\r
-#define _05_CGC_HOCO_WAIT_CYCLE_138 (0x05U) /* Wait time = 138 cycles (34.5us) */\r
-#define _06_CGC_HOCO_WAIT_CYCLE_266 (0x06U) /* Wait time = 266 cycles (66.5us) */\r
-\r
-/*\r
- Clock Output Control Register (CKOCR)\r
-*/\r
-/* Clock Output Source Select (CKOSEL[2:0]) */\r
-#define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */\r
-#define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */\r
-#define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */\r
-#define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */\r
-/* Clock Output Division Ratio Select (CKODIV[2:0]) */\r
-#define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */\r
-#define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */\r
-#define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */\r
-#define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */\r
-#define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */\r
-/* Clock Output Control (CKOSTP) */\r
-#define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */\r
-#define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */\r
-\r
-/*\r
- Main Clock Oscillator Forced Oscillation Control Register (MOFCR)\r
-*/\r
-/* Main Oscillator Drive Capability Switch (MODRV21) */\r
-#define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */\r
-#define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */\r
-/* Main Clock Oscillator Switch (MOSEL) */\r
-#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */\r
-#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */\r
-\r
-/*\r
- LCD Source Clock Control Register (LCDSCLKCR)\r
-*/\r
-/* LCD Source Clock Select (LCDSCLKSEL[2:0]) */\r
-#define _00_CGC_LCDSCLKSEL_LOCO (0x00U) /* LOCO */\r
-#define _01_CGC_LCDSCLKSEL_HOCO (0x01U) /* HOCO */\r
-#define _02_CGC_LCDSCLKSEL_MAINCLK (0x02U) /* Main clock oscillator */\r
-#define _03_CGC_LCDSCLKSEL_SUBCLK (0x03U) /* Sub-clock oscillator */\r
-#define _04_CGC_LCDSCLKSEL_IWDT (0x04U) /* IWDT-dedicated on-chip oscillator */\r
-\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-#define _007B_CGC_SUBSTPWT_WAIT (0x007BU) /* Wait time for 5 sub clock cycles */\r
-#define _00061A81_CGC_SUBOSCWT_WAIT (0x00061A81U) /* Wait time for sub clock stable */\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-void R_CGC_Create(void);\r
-\r
-/* Start user code for function. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_cgc_user.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for CGC module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_cgc.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_dbsct.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : Setting of B.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-\r
-#pragma unpack\r
-\r
-#pragma section C C$DSEC\r
-extern const struct {\r
- uint8_t *rom_s; /* Start address of the initialized data section in ROM */\r
- uint8_t *rom_e; /* End address of the initialized data section in ROM */\r
- uint8_t *ram_s; /* Start address of the initialized data section in RAM */\r
-} _DTBL[] = {\r
- { __sectop("D"), __secend("D"), __sectop("R") },\r
- { __sectop("D_2"), __secend("D_2"), __sectop("R_2") },\r
- { __sectop("D_1"), __secend("D_1"), __sectop("R_1") }\r
-};\r
-#pragma section C C$BSEC\r
-extern const struct {\r
- uint8_t *b_s; /* Start address of non-initialized data section */\r
- uint8_t *b_e; /* End address of non-initialized data section */\r
-} _BTBL[] = {\r
- { __sectop("B"), __secend("B") },\r
- { __sectop("B_2"), __secend("B_2") },\r
- { __sectop("B_1"), __secend("B_1") }\r
-};\r
-\r
-#pragma section\r
-\r
-/*\r
-** CTBL prevents excessive output of L1100 messages when linking.\r
-** Even if CTBL is deleted, the operation of the program does not change.\r
-*/\r
-uint8_t * const _CTBL[] = {\r
- __sectop("C_1"), __sectop("C_2"), __sectop("C"),\r
- __sectop("W_1"), __sectop("W_2"), __sectop("W"),\r
- __sectop("L"), __sectop("SU"),\r
- __sectop("C$DSEC"), __sectop("C$BSEC"),\r
- __sectop("C$INIT"), __sectop("C$VTBL"), __sectop("C$VECT")\r
-};\r
-\r
-#pragma packoption\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_hardware_setup.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements system initializing function.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_cgc.h"\r
-#include "r_cg_port.h"\r
-#include "r_cg_sci.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-* Function Name: R_Systeminit\r
-* Description : This function initializes every macro.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_Systeminit(void)\r
-{\r
- /* Enable writing to registers related to operating modes, LPC, CGC and software reset */\r
- SYSTEM.PRCR.WORD = 0xA50FU; \r
-\r
- /* Enable writing to MPC pin function control registers */\r
- MPC.PWPR.BIT.B0WI = 0U; \r
- MPC.PWPR.BIT.PFSWE = 1U;\r
-\r
- /* Initialize non-existent pins */\r
- PORT0.PDR.BYTE = 0x6BU;\r
- PORT3.PDR.BYTE = 0xD8U;\r
- PORT4.PDR.BYTE = 0xA0U;\r
- PORT5.PDR.BYTE = 0x80U;\r
- PORT9.PDR.BYTE = 0xF8U;\r
- PORTD.PDR.BYTE = 0xE0U;\r
- PORTF.PDR.BYTE = 0x3FU;\r
- PORTJ.PDR.BYTE = 0x32U;\r
-\r
- /* Set peripheral settings */\r
- R_CGC_Create();\r
- R_PORT_Create();\r
- R_SCI1_Create();\r
-\r
- /* Disable writing to MPC pin function control registers */\r
- MPC.PWPR.BIT.PFSWE = 0U; \r
- MPC.PWPR.BIT.B0WI = 1U; \r
-\r
- /* Enable protection */\r
- SYSTEM.PRCR.WORD = 0xA500U; \r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: HardwareSetup\r
-* Description : This function initializes hardware setting.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void HardwareSetup(void)\r
-{\r
- R_Systeminit();\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_intprg.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : Setting of B.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include <machine.h>\r
-#include "r_cg_vect.h"\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-\r
-#pragma section IntPRG\r
-\r
-/* Undefined exceptions for supervisor instruction, undefined instruction and floating point exceptions */\r
-void r_undefined_exception(void)\r
-{\r
- /* Start user code. Do not edit comment generated here */\r
- /* End user code. Do not edit comment generated here */\r
-}\r
-\r
-/* Reserved */\r
-void r_reserved_exception(void)\r
-{\r
- /* Start user code. Do not edit comment generated here */\r
- /* End user code. Do not edit comment generated here */\r
-}\r
-\r
-/* NMI */\r
-void r_nmi_exception(void)\r
-{\r
- /* Start user code. Do not edit comment generated here */\r
- /* End user code. Do not edit comment generated here */\r
-}\r
-\r
-/* BRK */\r
-void r_brk_exception(void)\r
-{\r
- /* Start user code. Do not edit comment generated here */\r
- /* End user code. Do not edit comment generated here */\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_macrodriver.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements general head file.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef MODULEID_H\r
-#define MODULEID_H\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "../iodefine.h"\r
-#include <machine.h>\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-#ifndef __TYPEDEF__\r
-\r
-/* Status list definition */\r
-#define MD_STATUSBASE (0x00U)\r
-#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */\r
-#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */\r
-#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */\r
-#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */\r
-#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */\r
-\r
-/* Error list definition */\r
-#define MD_ERRORBASE (0x80U)\r
-#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */\r
-#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */\r
-#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */\r
-#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */\r
-#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */\r
-#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */\r
-#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */\r
-\r
-/* BRK handler command options */\r
-typedef enum {\r
- BRK_NO_COMMAND,\r
- BRK_ALL_MODULE_CLOCK_STOP,\r
- BRK_SLEEP,\r
- BRK_DEEP_SLEEP,\r
- BRK_STANDBY,\r
- BRK_LOAD_FINTV_REGISTER\r
-} brk_commands;\r
-#endif\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-#ifndef __TYPEDEF__\r
- #ifndef _STD_USING_INT_TYPES\r
- #define _SYS_INT_TYPES_H\r
- #ifndef _STD_USING_BIT_TYPES\r
- #define __int8_t_defined\r
- typedef signed char int8_t;\r
- typedef signed short int16_t;\r
- #endif\r
-\r
- typedef unsigned char uint8_t;\r
- typedef unsigned short uint16_t;\r
- typedef signed long int32_t;\r
- typedef unsigned long uint32_t;\r
-\r
- typedef signed char int_least8_t;\r
- typedef signed short int_least16_t;\r
- typedef signed long int_least32_t;\r
- typedef unsigned char uint_least8_t;\r
- typedef unsigned short uint_least16_t;\r
- typedef unsigned long uint_least32_t;\r
- #endif\r
-\r
- typedef unsigned short MD_STATUS;\r
- #define __TYPEDEF__\r
-#endif\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-void HardwareSetup(void);\r
-void R_Systeminit(void);\r
-\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_port.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for Port module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_port.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-* Function Name: R_PORT_Create\r
-* Description : This function initializes the Port I/O.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_PORT_Create(void)\r
-{\r
- PORT2.PDR.BYTE = _04_Pm2_MODE_OUTPUT | _08_Pm3_MODE_OUTPUT | _10_Pm4_MODE_OUTPUT | _20_Pm5_MODE_OUTPUT | \r
- _00_Pm7_MODE_INPUT;\r
- PORT3.PDR.BYTE = _00_Pm2_MODE_INPUT | _D8_PDR3_DEFAULT;\r
- PORTJ.PDR.BYTE = _00_Pm0_MODE_INPUT | _32_PDRJ_DEFAULT;\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_port.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for Port module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef PORT_H\r
-#define PORT_H\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-/*\r
- Port Direction Register (PDR)\r
-*/\r
-/* Pmn Direction Control (B7 - B0) */\r
-#define _00_Pm0_MODE_NOT_USED (0x00U) /* Pm0 not used */\r
-#define _00_Pm0_MODE_INPUT (0x00U) /* Pm0 as input */\r
-#define _01_Pm0_MODE_OUTPUT (0x01U) /* Pm0 as output */\r
-#define _00_Pm1_MODE_NOT_USED (0x00U) /* Pm1 not used */\r
-#define _00_Pm1_MODE_INPUT (0x00U) /* Pm1 as input */\r
-#define _02_Pm1_MODE_OUTPUT (0x02U) /* Pm1 as output */\r
-#define _00_Pm2_MODE_NOT_USED (0x00U) /* Pm2 not used */\r
-#define _00_Pm2_MODE_INPUT (0x00U) /* Pm2 as input */\r
-#define _04_Pm2_MODE_OUTPUT (0x04U) /* Pm2 as output */\r
-#define _00_Pm3_MODE_NOT_USED (0x00U) /* Pm3 not used */\r
-#define _00_Pm3_MODE_INPUT (0x00U) /* Pm3 as input */\r
-#define _08_Pm3_MODE_OUTPUT (0x08U) /* Pm3 as output */\r
-#define _00_Pm4_MODE_NOT_USED (0x00U) /* Pm4 not used */\r
-#define _00_Pm4_MODE_INPUT (0x00U) /* Pm4 as input */\r
-#define _10_Pm4_MODE_OUTPUT (0x10U) /* Pm4 as output */\r
-#define _00_Pm5_MODE_NOT_USED (0x00U) /* Pm5 not used */\r
-#define _00_Pm5_MODE_INPUT (0x00U) /* Pm5 as input */\r
-#define _20_Pm5_MODE_OUTPUT (0x20U) /* Pm5 as output */\r
-#define _00_Pm6_MODE_NOT_USED (0x00U) /* Pm6 not used */\r
-#define _00_Pm6_MODE_INPUT (0x00U) /* Pm6 as input */\r
-#define _40_Pm6_MODE_OUTPUT (0x40U) /* Pm6 as output */\r
-#define _00_Pm7_MODE_NOT_USED (0x00U) /* Pm7 not used */\r
-#define _00_Pm7_MODE_INPUT (0x00U) /* Pm7 as input */\r
-#define _80_Pm7_MODE_OUTPUT (0x80U) /* Pm7 as output */\r
-\r
-/*\r
- Port Output Data Register (PODR)\r
-*/\r
-/* Pmn Output Data Store (B7 - B0) */\r
-#define _00_Pm0_OUTPUT_0 (0x00U) /* output low at B0 */\r
-#define _01_Pm0_OUTPUT_1 (0x01U) /* output high at B0 */\r
-#define _00_Pm1_OUTPUT_0 (0x00U) /* output low at B1 */\r
-#define _02_Pm1_OUTPUT_1 (0x02U) /* output high at B1 */\r
-#define _00_Pm2_OUTPUT_0 (0x00U) /* output low at B2 */\r
-#define _04_Pm2_OUTPUT_1 (0x04U) /* output high at B2 */\r
-#define _00_Pm3_OUTPUT_0 (0x00U) /* output low at B3 */\r
-#define _08_Pm3_OUTPUT_1 (0x08U) /* output high at B3 */\r
-#define _00_Pm4_OUTPUT_0 (0x00U) /* output low at B4 */\r
-#define _10_Pm4_OUTPUT_1 (0x10U) /* output high at B4 */\r
-#define _00_Pm5_OUTPUT_0 (0x00U) /* output low at B5 */\r
-#define _20_Pm5_OUTPUT_1 (0x20U) /* output high at B5 */\r
-#define _00_Pm6_OUTPUT_0 (0x00U) /* output low at B6 */\r
-#define _40_Pm6_OUTPUT_1 (0x40U) /* output high at B6 */\r
-#define _00_Pm7_OUTPUT_0 (0x00U) /* output low at B7 */\r
-#define _80_Pm7_OUTPUT_1 (0x80U) /* output high at B7 */\r
-\r
-/*\r
- Open Drain Control Register 0 (ODR0)\r
-*/\r
-/* Pmn Output Type Select (Pm0 to Pm3) */\r
-#define _00_Pm0_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _01_Pm0_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
-#define _02_Pm0_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */\r
-#define _00_Pm1_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _04_Pm1_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
-#define _08_Pm1_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */\r
-#define _00_Pm2_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _10_Pm2_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
-#define _20_Pm2_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */\r
-#define _00_Pm3_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _40_Pm3_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
-#define _80_Pm3_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */\r
-\r
-/*\r
- Open Drain Control Register 1 (ODR1)\r
-*/\r
-/* Pmn Output Type Select (Pm4 to Pm7) */\r
-#define _00_Pm4_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _01_Pm4_NCH_OPEN_DRAIN (0x01U) /* N-channel open-drain output */\r
-#define _02_Pm4_PCH_OPEN_DRAIN (0x02U) /* P-channel open-drain output */\r
-#define _00_Pm5_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _04_Pm5_NCH_OPEN_DRAIN (0x04U) /* N-channel open-drain output */\r
-#define _08_Pm5_PCH_OPEN_DRAIN (0x08U) /* P-channel open-drain output */\r
-#define _00_Pm6_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _10_Pm6_NCH_OPEN_DRAIN (0x10U) /* N-channel open-drain output */\r
-#define _20_Pm6_PCH_OPEN_DRAIN (0x20U) /* P-channel open-drain output */\r
-#define _00_Pm7_CMOS_OUTPUT (0x00U) /* CMOS output */\r
-#define _40_Pm7_NCH_OPEN_DRAIN (0x40U) /* N-channel open-drain output */\r
-#define _80_Pm7_PCH_OPEN_DRAIN (0x80U) /* P-channel open-drain output */\r
-\r
-/*\r
- Pull-Up Control Register (PCR)\r
-*/\r
-/* Pm0 Input Pull-Up Resistor Control ((B7 - B0)) */\r
-#define _00_Pm0_PULLUP_OFF (0x00U) /* Pn0 pull-up resistor not connected */\r
-#define _01_Pm0_PULLUP_ON (0x01U) /* Pn0 pull-up resistor connected */\r
-#define _00_Pm1_PULLUP_OFF (0x00U) /* Pn1 pull-up resistor not connected */\r
-#define _02_Pm1_PULLUP_ON (0x02U) /* Pn1 pull-up resistor connected */\r
-#define _00_Pm2_PULLUP_OFF (0x00U) /* Pn2 Pull-up resistor not connected */\r
-#define _04_Pm2_PULLUP_ON (0x04U) /* Pn2 pull-up resistor connected */\r
-#define _00_Pm3_PULLUP_OFF (0x00U) /* Pn3 pull-up resistor not connected */\r
-#define _08_Pm3_PULLUP_ON (0x08U) /* Pn3 pull-up resistor connected */\r
-#define _00_Pm4_PULLUP_OFF (0x00U) /* Pn4 pull-up resistor not connected */\r
-#define _10_Pm4_PULLUP_ON (0x10U) /* Pn4 pull-up resistor connected */\r
-#define _00_Pm5_PULLUP_OFF (0x00U) /* Pn5 pull-up resistor not connected */\r
-#define _20_Pm5_PULLUP_ON (0x20U) /* Pn5 pull-up resistor connected */\r
-#define _00_Pm6_PULLUP_OFF (0x00U) /* Pn6 pull-up resistor not connected */\r
-#define _40_Pm6_PULLUP_ON (0x40U) /* Pn6 pull-up resistor connected */\r
-#define _00_Pm7_PULLUP_OFF (0x00U) /* Pn7 pull-up resistor not connected */\r
-#define _80_Pm7_PULLUP_ON (0x80U) /* Pn7 pull-up resistor connected */\r
-\r
-/*\r
- Port Switching Register A (PSRA)\r
-*/\r
-/* PB6/PC0 Switching (PSEL6) */\r
-#define _00_PORT_PSEL6_PB6 (0x00U) /* PB6 general I/O port function is selected */\r
-#define _40_PORT_PSEL6_PC0 (0x40U) /* PC0 general I/O port function is selected */\r
-/* PB7/PC1 Switching (PSEL7) */\r
-#define _00_PORT_PSEL7_PB7 (0x00U) /* PB7 general I/O port function is selected */\r
-#define _80_PORT_PSEL7_PC1 (0x80U) /* PC1 general I/O port function is selected */\r
-\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-#define _6B_PDR0_DEFAULT (0x6BU) /* PDR0 default value */\r
-#define _D8_PDR3_DEFAULT (0xD8U) /* PDR3 default value */\r
-#define _A0_PDR4_DEFAULT (0xA0U) /* PDR4 default value */\r
-#define _80_PDR5_DEFAULT (0x80U) /* PDR5 default value */\r
-#define _F8_PDR9_DEFAULT (0xF8U) /* PDR9 default value */\r
-#define _E0_PDRD_DEFAULT (0xE0U) /* PDRD default value */\r
-#define _3F_PDRF_DEFAULT (0x3FU) /* PDRF default value */\r
-#define _32_PDRJ_DEFAULT (0x32U) /* PDRJ default value */\r
-\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-void R_PORT_Create(void);\r
-\r
-/* Start user code for function. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_port_user.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for Port module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_port.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_resetprg.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : Reset program.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include <machine.h>\r
-#include <_h_c_lib.h>\r
-//#include <stddef.h> // Remove the comment when you use errno\r
-//#include <stdlib.h> // Remove the comment when you use rand()\r
-#include "r_cg_stacksct.h"\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-void PowerON_Reset(void);\r
-void main(void);\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#define PSW_init 0x00010000 /* PSW bit pattern */\r
-#define FPSW_init 0x00000000 /* FPSW bit base pattern */\r
-\r
-#pragma section ResetPRG /* output PowerON_Reset to PResetPRG section */\r
-\r
-#pragma entry PowerON_Reset\r
-\r
-void PowerON_Reset(void)\r
-{\r
- set_intb(__sectop("C$VECT"));\r
-\r
- _INITSCT(); /* Initialize Sections */\r
- HardwareSetup(); /* Use Hardware Setup */\r
- nop();\r
- set_psw(PSW_init); /* Set Ubit & Ibit for PSW */\r
- main();\r
- brk();\r
-}\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_sbrk.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : Program of sbrk.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include <stddef.h>\r
-#include <stdio.h>\r
-#include "r_cg_sbrk.h"\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-\r
-int8_t *sbrk(size_t size);\r
-\r
-extern int8_t *_s1ptr;\r
-\r
-union HEAP_TYPE\r
-{\r
- int16_t dummy ; /* Dummy for 4-byte boundary */\r
- int8_t heap[HEAPSIZE]; /* Declaration of the area managed by sbrk */\r
-};\r
-\r
-static union HEAP_TYPE heap_area ;\r
-\r
-/* End address allocated by sbrk */\r
-static int8_t *brk = (int8_t *) &heap_area;\r
-\r
-/**************************************************************************/\r
-/* sbrk:Memory area allocation */\r
-/* Return value:Start address of allocated area (Pass) */\r
-/* -1 (Failure) */\r
-/**************************************************************************/\r
-int8_t *sbrk(size_t size) /* Assigned area size */\r
-{\r
- int8_t *p;\r
-\r
- if (brk+size > heap_area.heap + HEAPSIZE) /* Empty area size */\r
- {\r
- p = (int8_t *)-1;\r
- }\r
- else\r
- {\r
- p = brk; /* Area assignment */\r
- brk += size; /* End address update */\r
- }\r
-\r
- return p;\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_sbrk.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : Header file of sbrk file.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef _SBRK_H\r
-#define _SBRK_H\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-#define HEAPSIZE (0x400U) /* Size of area managed by sbrk */\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_sci.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for SCI module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_sci.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-uint8_t * gp_sci1_tx_address; /* SCI1 transmit buffer address */\r
-uint16_t g_sci1_tx_count; /* SCI1 transmit data number */\r
-uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */\r
-uint16_t g_sci1_rx_count; /* SCI1 receive data number */\r
-uint16_t g_sci1_rx_length; /* SCI1 receive data length */\r
-/* Start user code for global. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-* Function Name: R_SCI1_Create\r
-* Description : This function initializes the SCI1.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_SCI1_Create(void)\r
-{\r
- /* Cancel SCI1 module stop state */\r
- MSTP(SCI1) = 0U;\r
-\r
- /* Set interrupt priority */\r
- IPR(SCI1, ERI1) = _0F_SCI_PRIORITY_LEVEL15;\r
-\r
- /* Clear the SCR.TIE, RIE, TE, RE and TEIE bits */\r
- SCI1.SCR.BIT.TIE = 0U;\r
- SCI1.SCR.BIT.RIE = 0U;\r
- SCI1.SCR.BIT.TE = 0U;\r
- SCI1.SCR.BIT.RE = 0U;\r
- SCI1.SCR.BIT.TEIE = 0U;\r
-\r
- /* Set RXD1 pin */\r
- MPC.P15PFS.BYTE = 0x0AU;\r
- PORT1.PMR.BYTE |= 0x20U;\r
- /* Set TXD1 pin */\r
- MPC.P16PFS.BYTE = 0x0AU;\r
- PORT1.PODR.BYTE |= 0x40U;\r
- PORT1.PDR.BYTE |= 0x40U;\r
- PORT1.PMR.BYTE |= 0x40U;\r
-\r
- /* Set clock enable */\r
- SCI1.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED;\r
-\r
- /* Clear the SIMR1.IICM, SPMR.CKPH, and CKPOL bit */\r
- SCI1.SIMR1.BIT.IICM = 0U;\r
- SCI1.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED;\r
-\r
- /* Set control registers */\r
- SCI1.SMR.BYTE = _01_SCI_CLOCK_PCLK_4 | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | \r
- _00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE;\r
- SCI1.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | _72_SCI_SCMR_DEFAULT;\r
-\r
- /* Set SEMR, SNFR */\r
- SCI1.SEMR.BYTE = _00_SCI_LOW_LEVEL_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK;\r
-\r
- /* Set bitrate */\r
- SCI1.BRR = 0x19U;\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: R_SCI1_Start\r
-* Description : This function starts the SCI1.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_SCI1_Start(void)\r
-{\r
- IR(SCI1,TXI1) = 0U;\r
- IR(SCI1,TEI1) = 0U;\r
- IR(SCI1,RXI1) = 0U;\r
- IR(SCI1,ERI1) = 0U;\r
- IEN(SCI1,TXI1) = 1U;\r
- IEN(SCI1,TEI1) = 1U;\r
- IEN(SCI1,RXI1) = 1U;\r
- IEN(SCI1,ERI1) = 1U;\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: R_SCI1_Stop\r
-* Description : This function stops the SCI1.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-void R_SCI1_Stop(void)\r
-{\r
- /* Set TXD1 pin */\r
- PORT1.PMR.BYTE &= 0xBFU;\r
-\r
- SCI1.SCR.BYTE &= 0xCF; /* Disable serial transmit and receive */\r
- SCI1.SCR.BIT.TIE = 0U; /* Disable TXI interrupt */\r
- SCI1.SCR.BIT.RIE = 0U; /* Disable RXI and ERI interrupt */\r
- IR(SCI1,TXI1) = 0U;\r
- IEN(SCI1,TXI1) = 0U;\r
- IR(SCI1,TEI1) = 0U;\r
- IEN(SCI1,TEI1) = 0U;\r
- IR(SCI1,RXI1) = 0U;\r
- IEN(SCI1,RXI1) = 0U;\r
- IR(SCI1,ERI1) = 0U;\r
- IEN(SCI1,ERI1) = 0U;\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: R_SCI1_Serial_Receive\r
-* Description : This function receives SCI1 data.\r
-* Arguments : rx_buf -\r
-* receive buffer pointer (Not used when receive data handled by DTC)\r
-* rx_num -\r
-* buffer size\r
-* Return Value : status -\r
-* MD_OK or MD_ARGERROR\r
-***********************************************************************************************************************/\r
-MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num)\r
-{\r
- MD_STATUS status = MD_OK;\r
-\r
- if (rx_num < 1U)\r
- {\r
- status = MD_ARGERROR;\r
- }\r
- else\r
- {\r
- g_sci1_rx_count = 0U;\r
- g_sci1_rx_length = rx_num;\r
- gp_sci1_rx_address = rx_buf;\r
- SCI1.SCR.BIT.RIE = 1U;\r
- SCI1.SCR.BIT.RE = 1U;\r
- }\r
-\r
- return (status);\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: R_SCI1_Serial_Send\r
-* Description : This function transmits SCI1 data.\r
-* Arguments : tx_buf -\r
-* transfer buffer pointer (Not used when transmit data handled by DTC)\r
-* tx_num -\r
-* buffer size\r
-* Return Value : status -\r
-* MD_OK or MD_ARGERROR\r
-***********************************************************************************************************************/\r
-MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num)\r
-{\r
- MD_STATUS status = MD_OK;\r
-\r
- if (tx_num < 1U)\r
- {\r
- status = MD_ARGERROR;\r
- }\r
- else\r
- {\r
- gp_sci1_tx_address = tx_buf;\r
- g_sci1_tx_count = tx_num;\r
- /* Set TXD1 pin */\r
- PORT1.PMR.BYTE |= 0x40U;\r
- SCI1.SCR.BIT.TIE = 1U;\r
- SCI1.SCR.BIT.TE = 1U;\r
- }\r
-\r
- return (status);\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_sci.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for SCI module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef SCI_H\r
-#define SCI_H\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-\r
-/*\r
- Serial mode register (SMR)\r
-*/\r
-/* Clock select (CKS) */\r
-#define _00_SCI_CLOCK_PCLK (0x00U) /* PCLK */\r
-#define _01_SCI_CLOCK_PCLK_4 (0x01U) /* PCLK/4 */\r
-#define _02_SCI_CLOCK_PCLK_16 (0x02U) /* PCLK/16 */\r
-#define _03_SCI_CLOCK_PCLK_64 (0x03U) /* PCLK/64 */\r
-/* Multi-processor Mode (MP) */\r
-#define _00_SCI_MULTI_PROCESSOR_DISABLE (0x00U) /* Disable multiprocessor mode */\r
-#define _04_SCI_MULTI_PROCESSOR_ENABLE (0x04U) /* Enable multiprocessor mode */\r
-/* Stop bit length (STOP) */\r
-#define _00_SCI_STOP_1 (0x00U) /* 1 stop bit length */\r
-#define _08_SCI_STOP_2 (0x08U) /* 2 stop bits length */\r
-/* Parity mode (PM) */\r
-#define _00_SCI_PARITY_EVEN (0x00U) /* Parity even */\r
-#define _10_SCI_PARITY_ODD (0x10U) /* Parity odd */\r
-/* Parity enable (PE) */\r
-#define _00_SCI_PARITY_DISABLE (0x00U) /* Parity disable */\r
-#define _20_SCI_PARITY_ENABLE (0x20U) /* Parity enable */\r
-/* Character length (CHR) */\r
-#define _00_SCI_DATA_LENGTH_8 (0x00U) /* Data length 8 bits */\r
-#define _40_SCI_DATA_LENGTH_7 (0x40U) /* Data length 7 bits */\r
-/* Communications mode (CM) */\r
-#define _00_SCI_ASYNCHRONOUS_MODE (0x00U) /* Asynchronous mode */\r
-#define _80_SCI_CLOCK_SYNCHRONOUS_MODE (0x80U) /* Clock synchronous mode */\r
-/* Base clock pulse (BCP) */\r
-#define _00_SCI_32_93_CLOCK_CYCLES (0x00U) /* 32 or 93 clock cycles */\r
-#define _04_SCI_64_128_CLOCK_CYCLES (0x04U) /* 64 or 128 clock cycles */\r
-#define _08_SCI_186_372_CLOCK_CYCLES (0x08U) /* 186 or 372 clock cycles */\r
-#define _0C_SCI_256_512_CLOCK_CYCLES (0x0CU) /* 256 or 512 clock cycles */\r
-/* Block transfer mode (BLK) */\r
-#define _00_SCI_BLK_TRANSFER_DISABLE (0x00U) /* Block transfer disable */\r
-#define _40_SCI_BLK_TRANSFER_ENABLE (0x40U) /* Block transfer enable */\r
-/* GSM mode (GSM) */\r
-#define _00_SCI_GSM_DISABLE (0x00U) /* Normal mode operation */\r
-#define _80_SCI_GSM_ENABLE (0x80U) /* GSM mode operation */\r
-\r
-/*\r
- Serial control register (SCR)\r
-*/\r
-/* Clock enable (CKE) */\r
-#define _00_SCI_INTERNAL_SCK_UNUSED (0x00U) /* Internal clock selected, SCK pin unused */\r
-#define _01_SCI_INTERNAL_SCK_OUTPUT (0x01U) /* Internal clock selected, SCK pin as clock output */\r
-#define _02_SCI_EXTERNAL (0x02U) /* External clock selected */\r
-#define _03_SCI_EXTERNAL (0x03U) /* External clock selected */\r
-/* Transmit end interrupt enable (TEIE) */\r
-#define _00_SCI_TEI_INTERRUPT_DISABLE (0x00U) /* TEI interrupt request disable */\r
-#define _04_SCI_TEI_INTERRUPT_ENABLE (0x04U) /* TEI interrupt request enable */\r
-/* Multi-processor interrupt enable (MPIE) */\r
-#define _00_SCI_MP_INTERRUPT_NORMAL (0x00U) /* Normal reception */\r
-#define _08_SCI_MP_INTERRUPT_SPECIAL (0x08U) /* Multi-processor ID reception */\r
-/* Receive enable (RE) */\r
-#define _00_SCI_RECEIVE_DISABLE (0x00U) /* Disable receive mode */\r
-#define _10_SCI_RECEIVE_ENABLE (0x10U) /* Enable receive mode */\r
-/* Transmit enable (TE) */\r
-#define _00_SCI_TRANSMIT_DISABLE (0x00U) /* Disable transmit mode */\r
-#define _20_SCI_TRANSMIT_ENABLE (0x20U) /* Enable transmit mode */\r
-/* Receive interrupt enable (RIE) */\r
-#define _00_SCI_RXI_ERI_DISABLE (0x00U) /* Disable RXI and ERI interrupt requests */\r
-#define _40_SCI_RXI_ERI_ENABLE (0x40U) /* Enable RXI and ERI interrupt requests */\r
-/* Transmit interrupt enable (TIE) */\r
-#define _00_SCI_TXI_DISABLE (0x00U) /* Disable TXI interrupt requests */\r
-#define _80_SCI_TXI_ENABLE (0x80U) /* Enable TXI interrupt requests */\r
-\r
-/*\r
- Serial status register (SSR)\r
-*/\r
-/* Multi-Processor bit transfer (MPBT) */\r
-#define _00_SCI_SET_DATA_TRANSFER (0x00U) /* Set data transmission cycles */\r
-#define _01_SCI_SET_ID_TRANSFER (0x01U) /* Set ID transmission cycles */\r
-/* Multi-Processor (MPB) */\r
-#define _00_SCI_DATA_TRANSFER (0x00U) /* In data transmission cycles */\r
-#define _02_SCI_ID_TRANSFER (0x02U) /* In ID transmission cycles */\r
-/* Transmit end flag (TEND) */\r
-#define _00_SCI_TRANSMITTING (0x00U) /* A character is being transmitted */\r
-#define _04_SCI_TRANSMIT_COMPLETE (0x04U) /* Character transfer has been completed */\r
-/* Parity error flag (PER) */\r
-#define _08_SCI_PARITY_ERROR (0x08U) /* A parity error has occurred */\r
-/* Framing error flag (FER) */\r
-#define _10_SCI_FRAME_ERROR (0x10U) /* A framing error has occurred */\r
-/* Overrun error flag (ORER) */\r
-#define _20_SCI_OVERRUN_ERROR (0x20U) /* An overrun error has occurred */\r
-\r
-/*\r
- Smart card mode register (SCMR)\r
-*/\r
-/* Smart card interface mode select (SMIF) */\r
-#define _00_SCI_SERIAL_MODE (0x00U) /* Serial communications interface mode */\r
-#define _01_SCI_SMART_CARD_MODE (0x01U) /* Smart card interface mode */\r
-/* Transmitted / received data invert (SINV) */\r
-#define _00_SCI_DATA_INVERT_NONE (0x00U) /* Data is not inverted */\r
-#define _04_SCI_DATA_INVERTED (0x04U) /* Data is inverted */\r
-/* Transmitted / received data transfer direction (SDIR) */\r
-#define _00_SCI_DATA_LSB_FIRST (0x00U) /* Transfer data LSB first */\r
-#define _08_SCI_DATA_MSB_FIRST (0x08U) /* Transfer data MSB first */\r
-/* Base clock pulse 2 (BCP2) */\r
-#define _00_SCI_93_128_186_512_CLK (0x00U) /* 93, 128, 186, or 512 clock cycles */\r
-#define _80_SCI_32_64_256_372_CLK (0x80U) /* 32, 64, 256, or 372 clock cycles */\r
-#define _72_SCI_SCMR_DEFAULT (0x72U) /* Write default value of SCMR */\r
-\r
-/* \r
- Serial extended mode register (SEMR)\r
-*/\r
-/* Asynchronous Mode Clock Source Select (ACS0) */\r
-#define _00_SCI_ASYNC_SOURCE_EXTERNAL (0x00U) /* External clock input */\r
-#define _01_SCI_ASYNC_SOURCE_TMR (0x01U) /* Logical AND of two clock cycles output from TMR */\r
-/* Asynchronous mode base clock select (ABCS) */\r
-#define _00_SCI_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */\r
-#define _10_SCI_8_BASE_CLOCK (0x10U) /* Selects 8 base clock cycles for 1 bit period */ \r
-/* Digital noise filter function enable (NFEN) */\r
-#define _00_SCI_NOISE_FILTER_DISABLE (0x00U) /* Noise filter is disabled */\r
-#define _20_SCI_NOISE_FILTER_ENABLE (0x20U) /* Noise filter is enabled */\r
-/* Asynchronous start bit edge detections select (RXDESEL) */\r
-#define _00_SCI_LOW_LEVEL_START_BIT (0x00U) /* Low level on RXDn pin selected as start bit */\r
-#define _80_SCI_FALLING_EDGE_START_BIT (0x80U) /* Falling edge on RXDn pin selected as start bit */\r
-\r
-/*\r
- Noise filter setting register (SNFR)\r
-*/\r
-/* Noise filter clock select (NFCS) */\r
-#define _00_SCI_ASYNC_DIV_1 (0x00U) /* Clock signal divided by 1 is used with the noise filter */\r
-#define _01_SCI_IIC_DIV_1 (0x01U) /* Clock signal divided by 1 is used with the noise filter */\r
-#define _02_SCI_IIC_DIV_2 (0x02U) /* Clock signal divided by 2 is used with the noise filter */\r
-#define _03_SCI_IIC_DIV_4 (0x03U) /* Clock signal divided by 4 is used with the noise filter */\r
-#define _04_SCI_IIC_DIV_8 (0x04U) /* Clock signal divided by 8 is used with the noise filter */\r
-\r
-/*\r
- I2C mode register 1 (SIMR1)\r
-*/\r
-/* Simple IIC mode select (IICM) */\r
-#define _00_SCI_SERIAL_SMART_CARD_MODE (0x00U) /* Serial or smart card mode */\r
-#define _01_SCI_IIC_MODE (0x01U) /* Simple IIC mode */\r
-\r
-/*\r
- I2C mode register 2 (SIMR2)\r
-*/\r
-/* IIC interrupt mode select (IICINTM) */\r
-#define _00_SCI_ACK_NACK_INTERRUPTS (0x00U) /* Use ACK/NACK interrupts */\r
-#define _01_SCI_RX_TX_INTERRUPTS (0x01U) /* Use reception/transmission interrupts */\r
-/* Clock synchronization (IICCSC) */\r
-#define _00_SCI_NO_SYNCHRONIZATION (0x00U) /* No synchronization with the clock signal */\r
-#define _02_SCI_SYNCHRONIZATION (0x02U) /* Synchronization with the clock signal */\r
-/* ACK transmission data (IICACKT) */\r
-#define _00_SCI_ACK_TRANSMISSION (0x00U) /* ACK transmission */\r
-#define _20_SCI_NACK_TRANSMISSION (0x20U) /* NACK transmission and reception of ACK/NACK */\r
-\r
-/*\r
- I2C mode register 3 (SIMR3)\r
-*/\r
-/* Start condition generation (IICSTAREQ) */\r
-#define _00_SCI_START_CONDITION_OFF (0x00U) /* Start condition is not generated */\r
-#define _01_SCI_START_CONDITION_ON (0x01U) /* Start condition is generated */\r
-/* Restart condition generation (IICRSTAREQ) */\r
-#define _00_SCI_RESTART_CONDITION_OFF (0x00U) /* Restart condition is not generated */\r
-#define _02_SCI_RESTART_CONDITION_ON (0x02U) /* Restart condition is generated */\r
-/* Stop condition generation (IICSTPREQ) */\r
-#define _00_SCI_STOP_CONDITION_OFF (0x00U) /* Stop condition is not generated */\r
-#define _04_SCI_STOP_CONDITION_ON (0x04U) /* Stop condition is generated */\r
-/* Issuing of start, restart, or sstop condition completed flag (IICSTIF) */\r
-#define _00_SCI_CONDITION_GENERATED (0x00U) /* No requests to generate conditions/conditions generated */\r
-#define _08_SCI_GENERATION_COMPLETED (0x08U) /* All request generation has been completed */\r
-/* SSDA output select (IICSDAS) */\r
-#define _00_SCI_SSDA_DATA_OUTPUT (0x00U) /* SSDA output is serial data output */\r
-#define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10U) /* SSDA output generates start, restart or stop condition */\r
-#define _20_SCI_SSDA_LOW_LEVEL (0x20U) /* SSDA output low level */\r
-#define _30_SCI_SSDA_HIGH_IMPEDANCE (0x30U) /* SSDA output high impedance */\r
-/* SSCL output select (IICSCLS) */\r
-#define _00_SCI_SSCL_CLOCK_OUTPUT (0x00U) /* SSCL output is serial clock output */\r
-#define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40U) /* SSCL output generates start, restart or stop condition */\r
-#define _80_SCI_SSCL_LOW_LEVEL (0x80U) /* SSCL output low level */\r
-#define _C0_SCI_SSCL_HIGH_IMPEDANCE (0xC0U) /* SSCL output high impedance */\r
-\r
-/*\r
- I2C status register (SISR)\r
-*/\r
-/* ACK reception data flag (IICACKR) */\r
-#define _00_SCI_ACK_RECEIVED (0x00U) /* ACK received */\r
-#define _01_SCI_NACK_RECEIVED (0x01U) /* NACK received */\r
-\r
-/*\r
- SPI mode register (SPMR)\r
-*/\r
-/* SS pin function enable (SSE) */\r
-#define _00_SCI_SS_PIN_DISABLE (0x00U) /* SS pin function disabled */\r
-#define _01_SCI_SS_PIN_ENABLE (0x01U) /* SS pin function enabled */\r
-/* CTS enable (CTSE) */\r
-#define _00_SCI_RTS (0x00U) /* RTS function is enabled */\r
-#define _02_SCI_CTS (0x02U) /* CTS function is disabled */\r
-/* Master slave select (MSS) */\r
-#define _00_SCI_SPI_MASTER (0x00U) /* Master mode */\r
-#define _04_SCI_SPI_SLAVE (0x04U) /* Slave mode */\r
-/* Mode fault flag (MFF) */\r
-#define _00_SCI_NO_MODE_FAULT (0x00U) /* No mode fault */\r
-#define _10_SCI_MODE_FAULT (0x10U) /* Mode fault */\r
-/* Clock polarity select (CKPOL) */\r
-#define _00_SCI_CLOCK_NOT_INVERTED (0x00U) /* Clock polarity is not inverted */\r
-#define _40_SCI_CLOCK_INVERTED (0x40U) /* Clock polarity is inverted */\r
-/* Clock phase select (CKPH) */\r
-#define _00_SCI_CLOCK_NOT_DELAYED (0x00U) /* Clock is not delayed */\r
-#define _80_SCI_CLOCK_DELAYED (0x80U) /* Clock is delayed */\r
-\r
-/*\r
- Interrupt Source Priority Register n (IPRn)\r
-*/\r
-/* Interrupt Priority Level Select (IPR[3:0]) */\r
-#define _00_SCI_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */\r
-#define _01_SCI_PRIORITY_LEVEL1 (0x01U) /* Level 1 */\r
-#define _02_SCI_PRIORITY_LEVEL2 (0x02U) /* Level 2 */\r
-#define _03_SCI_PRIORITY_LEVEL3 (0x03U) /* Level 3 */\r
-#define _04_SCI_PRIORITY_LEVEL4 (0x04U) /* Level 4 */\r
-#define _05_SCI_PRIORITY_LEVEL5 (0x05U) /* Level 5 */\r
-#define _06_SCI_PRIORITY_LEVEL6 (0x06U) /* Level 6 */\r
-#define _07_SCI_PRIORITY_LEVEL7 (0x07U) /* Level 7 */\r
-#define _08_SCI_PRIORITY_LEVEL8 (0x08U) /* Level 8 */\r
-#define _09_SCI_PRIORITY_LEVEL9 (0x09U) /* Level 9 */\r
-#define _0A_SCI_PRIORITY_LEVEL10 (0x0AU) /* Level 10 */\r
-#define _0B_SCI_PRIORITY_LEVEL11 (0x0BU) /* Level 11 */\r
-#define _0C_SCI_PRIORITY_LEVEL12 (0x0CU) /* Level 12 */\r
-#define _0D_SCI_PRIORITY_LEVEL13 (0x0DU) /* Level 13 */\r
-#define _0E_SCI_PRIORITY_LEVEL14 (0x0EU) /* Level 14 */\r
-#define _0F_SCI_PRIORITY_LEVEL15 (0x0FU) /* Level 15 (highest) */\r
-\r
-/*\r
- Transfer status control value\r
-*/\r
-/* Simple IIC Transmit Receive Flag */\r
-#define _80_SCI_IIC_TRANSMISSION (0x80U)\r
-#define _00_SCI_IIC_RECEPTION (0x00U)\r
-/* Simple IIC Start Stop Flag */\r
-#define _80_SCI_IIC_START_CYCLE (0x80U)\r
-#define _00_SCI_IIC_STOP_CYCLE (0x00U)\r
-/* Multiprocessor Asynchronous Communication Flag */\r
-#define _80_SCI_ID_TRANSMISSION_CYCLE (0x80U)\r
-#define _00_SCI_DATA_TRANSMISSION_CYCLE (0x00U)\r
-\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-void R_SCI1_Create(void);\r
-void R_SCI1_Start(void);\r
-void R_SCI1_Stop(void);\r
-MD_STATUS R_SCI1_Serial_Send(uint8_t * const tx_buf, uint16_t tx_num);\r
-MD_STATUS R_SCI1_Serial_Receive(uint8_t * const rx_buf, uint16_t rx_num);\r
-static void r_sci1_callback_transmitend(void);\r
-static void r_sci1_callback_receiveend(void);\r
-static void r_sci1_callback_receiveerror(void);\r
-\r
-/* Start user code for function. Do not edit comment generated here */\r
-\r
-/* Some of the code in this file is generated using "Code Generator" for e2 studio.\r
- * Warnings exist in this module. */\r
-\r
-/* Exported functions used to transmit a number of bytes and wait for completion */\r
-MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num);\r
-\r
-/* Character is used to receive key presses from PC terminal */\r
-extern uint8_t g_rx_char;\r
-\r
-/* Flag used to control transmission to PC terminal */\r
-extern volatile uint8_t g_tx_flag;\r
-\r
-/* End user code. Do not edit comment generated here */\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_sci_user.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file implements device driver for SCI module.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_sci.h"\r
-/* Start user code for include. Do not edit comment generated here */\r
-#include "rskrx113def.h"\r
-//_RB_#include "r_cg_cmt.h"\r
-/* End user code. Do not edit comment generated here */\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-extern uint8_t * gp_sci1_tx_address; /* SCI1 send buffer address */\r
-extern uint16_t g_sci1_tx_count; /* SCI1 send data number */\r
-extern uint8_t * gp_sci1_rx_address; /* SCI1 receive buffer address */\r
-extern uint16_t g_sci1_rx_count; /* SCI1 receive data number */\r
-extern uint16_t g_sci1_rx_length; /* SCI1 receive data length */\r
-/* Start user code for global. Do not edit comment generated here */\r
-\r
-/* Global used to receive a character from the PC terminal */\r
-uint8_t g_rx_char;\r
-\r
-/* Flag used to control transmission to PC terminal */\r
-volatile uint8_t g_tx_flag = FALSE;\r
-\r
-/* Flag used locally to detect transmission complete */\r
-static volatile uint8_t sci1_txdone;\r
-\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_transmit_interrupt\r
-* Description : None\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TXI1\r
-#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1),fint)\r
-#else\r
-#pragma interrupt r_sci1_transmit_interrupt(vect=VECT(SCI1,TXI1))\r
-#endif\r
-static void r_sci1_transmit_interrupt(void)\r
-{\r
- if (g_sci1_tx_count > 0U)\r
- {\r
- SCI1.TDR = *gp_sci1_tx_address;\r
- gp_sci1_tx_address++;\r
- g_sci1_tx_count--;\r
- }\r
- else \r
- {\r
- SCI1.SCR.BIT.TIE = 0U;\r
- SCI1.SCR.BIT.TEIE = 1U;\r
- }\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_transmitend_interrupt\r
-* Description : None\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-#if FAST_INTERRUPT_VECTOR == VECT_SCI1_TEI1\r
-#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1),fint)\r
-#else\r
-#pragma interrupt r_sci1_transmitend_interrupt(vect=VECT(SCI1,TEI1))\r
-#endif\r
-static void r_sci1_transmitend_interrupt(void)\r
-{\r
- /* Set TXD1 pin */\r
- PORT1.PMR.BYTE &= 0xBFU;\r
- SCI1.SCR.BIT.TIE = 0U;\r
- SCI1.SCR.BIT.TE = 0U;\r
- SCI1.SCR.BIT.TEIE = 0U;\r
-\r
- r_sci1_callback_transmitend();\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_receive_interrupt\r
-* Description : None\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-#if FAST_INTERRUPT_VECTOR == VECT_SCI1_RXI1\r
-#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1),fint)\r
-#else\r
-#pragma interrupt r_sci1_receive_interrupt(vect=VECT(SCI1,RXI1))\r
-#endif\r
-static void r_sci1_receive_interrupt(void)\r
-{\r
- if (g_sci1_rx_length > g_sci1_rx_count)\r
- {\r
- *gp_sci1_rx_address = SCI1.RDR;\r
- gp_sci1_rx_address++;\r
- g_sci1_rx_count++;\r
-\r
- if (g_sci1_rx_length == g_sci1_rx_count)\r
- {\r
- r_sci1_callback_receiveend();\r
- }\r
- }\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_receiveerror_interrupt\r
-* Description : None\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-#if FAST_INTERRUPT_VECTOR == VECT_SCI1_ERI1\r
-#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1),fint)\r
-#else\r
-#pragma interrupt r_sci1_receiveerror_interrupt(vect=VECT(SCI1,ERI1))\r
-#endif\r
-static void r_sci1_receiveerror_interrupt(void)\r
-{\r
- uint8_t err_type;\r
-\r
- r_sci1_callback_receiveerror();\r
-\r
- /* Clear overrun, framing and parity error flags */\r
- err_type = SCI1.SSR.BYTE;\r
- SCI1.SSR.BYTE = err_type & 0xC7U;\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_callback_transmitend\r
-* Description : This function is a callback function when SCI1 finishes transmission.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-static void r_sci1_callback_transmitend(void)\r
-{\r
- /* Start user code. Do not edit comment generated here */\r
- sci1_txdone = TRUE;\r
-\r
- /* End user code. Do not edit comment generated here */\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_callback_receiveend\r
-* Description : This function is a callback function when SCI1 finishes reception.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-static void r_sci1_callback_receiveend(void)\r
-{\r
- /* Start user code. Do not edit comment generated here */\r
- /* Check the contents of g_rx_char */\r
- if ('z' == g_rx_char)\r
- {\r
- /* Stop the timer used to control transmission to PC terminal*/\r
-//_RB_ R_CMT0_Stop();\r
-\r
- /* Turn off LED0 and turn on LED1 to indicate serial transmission\r
- inactive */\r
- LED0 = LED_OFF;\r
- LED1 = LED_ON;\r
- }\r
- else\r
- {\r
- /* Start the timer used to control transmission to PC terminal*/\r
-//_RB_ R_CMT0_Start();\r
-\r
- /* Turn on LED0 and turn off LED1 to indicate serial transmission\r
- active */\r
- LED0 = LED_ON;\r
- LED1 = LED_OFF;\r
- }\r
-\r
- /* Set up SCI1 receive buffer again */\r
- R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
-\r
- /* End user code. Do not edit comment generated here */\r
-}\r
-/***********************************************************************************************************************\r
-* Function Name: r_sci1_callback_receiveerror\r
-* Description : This function is a callback function when SCI1 reception encounters error.\r
-* Arguments : None\r
-* Return Value : None\r
-***********************************************************************************************************************/\r
-static void r_sci1_callback_receiveerror(void)\r
-{\r
- /* Start user code. Do not edit comment generated here */\r
- /* End user code. Do not edit comment generated here */\r
-}\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/***********************************************************************************************************************\r
- * Function Name: R_SCI1_AsyncTransmit\r
- * Description : This function sends SCI1 data and waits for the transmit end flag.\r
- * Arguments : tx_buf -\r
- * transfer buffer pointer\r
- * tx_num -\r
- * buffer size\r
- * Return Value : status -\r
- * MD_OK or MD_ARGERROR\r
- ***********************************************************************************************************************/\r
-MD_STATUS R_SCI1_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num)\r
-{\r
- MD_STATUS status = MD_OK;\r
-\r
- /* clear the flag before initiating a new transmission */\r
- sci1_txdone = FALSE;\r
-\r
- /* Send the data using the API */\r
- status = R_SCI1_Serial_Send(tx_buf, tx_num);\r
-\r
- /* Wait for the transmit end flag */\r
- while (FALSE == sci1_txdone)\r
- {\r
- /* Wait */\r
- }\r
- return (status);\r
-}\r
-/***********************************************************************************************************************\r
- * End of function R_SCI1_AsyncTransmit\r
- ***********************************************************************************************************************/\r
-\r
-/* End user code. Do not edit comment generated here */\r
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_stacksct.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : Setting of Stack area.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef _STACKSCT_H\r
-#define _STACKSCT_H\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-#pragma stacksize su=0x100\r
-#pragma stacksize si=0x300\r
-\r
-\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_userdefine.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file includes user definition.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef _USER_DEF_H\r
-#define _USER_DEF_H\r
-\r
-/***********************************************************************************************************************\r
-User definitions\r
-***********************************************************************************************************************/\r
-#define FAST_INTERRUPT_VECTOR 0\r
-\r
-/* Start user code for function. Do not edit comment generated here */\r
-#define TRUE (1)\r
-#define FALSE (0)\r
-/* End user code. Do not edit comment generated here */\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_vect.h\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file contains definition of vector.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-#ifndef _VECT_H\r
-#define _VECT_H\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions (Register bit)\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Macro definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Typedef definitions\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Global functions\r
-***********************************************************************************************************************/\r
-/* Undefined */\r
-#pragma interrupt (r_undefined_exception)\r
-void r_undefined_exception(void);\r
-\r
-/* Reserved */\r
-#pragma interrupt (r_reserved_exception)\r
-void r_reserved_exception(void);\r
-\r
-/* NMI */\r
-#pragma interrupt (r_nmi_exception)\r
-void r_nmi_exception(void);\r
-\r
-/* BRK */\r
-#pragma interrupt (r_brk_exception(vect=0))\r
-void r_brk_exception(void);\r
-\r
-/*;<<VECTOR DATA START (POWER ON RESET)>> */\r
-/*;Power On Reset PC */\r
-extern void PowerON_Reset(void);\r
-/*;<<VECTOR DATA END (POWER ON RESET)>> */\r
-\r
-#endif
\ No newline at end of file
+++ /dev/null
-/***********************************************************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
-* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
-* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
-* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
-* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
-* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
-* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-* File Name : r_cg_vecttbl.c\r
-* Version : Code Generator for RX113 V1.02.01.02 [28 May 2015]\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* Description : This file initializes the vector table.\r
-* Creation Date: 21/09/2015\r
-***********************************************************************************************************************/\r
-\r
-/***********************************************************************************************************************\r
-Pragma directive\r
-***********************************************************************************************************************/\r
-/* Start user code for pragma. Do not edit comment generated here */\r
-/* End user code. Do not edit comment generated here */\r
-\r
-/***********************************************************************************************************************\r
-Includes\r
-***********************************************************************************************************************/\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_vect.h"\r
-#include "r_cg_userdefine.h"\r
-\r
-/***********************************************************************************************************************\r
-Global variables and functions\r
-***********************************************************************************************************************/\r
-\r
-#pragma section C FIXEDVECT\r
-\r
-void (*const Fixed_Vectors[])(void) = {\r
-/*;0xffffffd0 Exception(Supervisor Instruction) */\r
- r_undefined_exception,\r
-/*;0xffffffd4 Reserved */\r
- r_undefined_exception,\r
-/*;0xffffffd8 Reserved */\r
- r_reserved_exception,\r
-/*;0xffffffdc Exception(Undefined Instruction) */\r
- r_undefined_exception,\r
-/*;0xffffffe0 Reserved */\r
- r_reserved_exception,\r
-/*;0xffffffe4 Reserved */\r
- r_reserved_exception,\r
-/*;0xffffffe8 Reserved */\r
- r_reserved_exception,\r
-/*;0xffffffec Reserved */\r
- r_reserved_exception,\r
-/*;0xfffffff0 Reserved */\r
- r_reserved_exception,\r
-/*;0xfffffff4 Reserved */\r
- r_reserved_exception,\r
-/*;0xfffffff8 NMI */\r
- r_nmi_exception,\r
-/*;0xfffffffc RESET */\r
-/*;<<VECTOR DATA START (POWER ON RESET)>> */\r
-/*;Power On Reset PC */\r
- /*(void*)*/ PowerON_Reset\r
-/*;<<VECTOR DATA END (POWER ON RESET)>> */\r
-};\r
-\r
-/* MDE register (Single Chip Mode) */\r
-#pragma address _MDEreg=0xffffff80\r
-#ifdef __BIG\r
- /* Big endian*/\r
- const unsigned long _MDEreg = 0xfffffff8;\r
-#else\r
- /* Little endian */\r
- const unsigned long _MDEreg = 0xffffffff;\r
-#endif\r
-\r
-/* Set option bytes */\r
-#pragma address OFS0_location = 0xFFFFFF8CUL\r
-#pragma address OFS1_location = 0xFFFFFF88UL\r
-volatile const uint32_t OFS0_location = 0xFFFFFFFFUL;\r
-volatile const uint32_t OFS1_location = 0xFFFFFFFFUL;\r
-\r
-/* Start user code for adding. Do not edit comment generated here */\r
-/* ID codes (Default) */\r
-#pragma address id_code=0xffffffa0\r
-const unsigned long id_code[4] = {\r
- 0xffffffff,\r
- 0xffffffff,\r
- 0xffffffff,\r
- 0xffffffff,\r
-};\r
-/* End user code. Do not edit comment generated here */\r
-\r
+++ /dev/null
-\r
-/*********************************************************************************\r
-*\r
-* Device : RX/RX100/RX113\r
-*\r
-* File Name : iodefine.h\r
-*\r
-* Abstract : Definition of I/O Register.\r
-*\r
-* History : 0.4 (2013-11-18) [Hardware Manual Revision : 0.40]\r
-* : 0.5 (2014-01-05) [Hardware Manual Revision : 0.50]\r
-* : 1.0 (2014-07-22) [Hardware Manual Revision : 1.00]\r
-*\r
-* NOTE : THIS IS A TYPICAL EXAMPLE.\r
-*\r
-* Copyright (C) 2013 (2014) Renesas Electronics Corporation and\r
-* Renesas Solutions Corp. All rights reserved.\r
-*\r
-*********************************************************************************/\r
-/********************************************************************************/\r
-/* */\r
-/* DESCRIPTION : Definition of ICU Register */\r
-/* CPU TYPE : RX113 */\r
-/* */\r
-/* Usage : IR,DTCER,IER,IPR of ICU Register */\r
-/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */\r
-/* The bit access operation is "Bit_Name(interrupt source,name)". */\r
-/* A part of the name can be omitted. */\r
-/* for example : */\r
-/* IR(MTU0,TGIA0) = 0; expands to : */\r
-/* ICU.IR[114].BIT.IR = 0; */\r
-/* */\r
-/* DTCE(ICU,IRQ0) = 1; expands to : */\r
-/* ICU.DTCER[64].BIT.DTCE = 1; */\r
-/* */\r
-/* IEN(CMT0,CMI0) = 1; expands to : */\r
-/* ICU.IER[0x03].BIT.IEN4 = 1; */\r
-/* */\r
-/* Usage : #pragma interrupt Function_Identifier(vect=**) */\r
-/* The number of vector is "(interrupt source, name)". */\r
-/* for example : */\r
-/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */\r
-/* #pragma interrupt INT_IRQ0(vect=64) */\r
-/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */\r
-/* #pragma interrupt INT_CMT0_CMI0(vect=28) */\r
-/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */\r
-/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */\r
-/* */\r
-/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */\r
-/* The bit access operation is "MSTP(name)". */\r
-/* The name that can be used is a macro name defined with "iodefine.h". */\r
-/* for example : */\r
-/* MSTP(TMR2) = 0; // TMR23,TMR2,TMR3 expands to : */\r
-/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */\r
-/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */\r
-/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */\r
-/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */\r
-/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */\r
-/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */\r
-/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */\r
-/* */\r
-/* */\r
-/********************************************************************************/\r
-#ifndef __RX113IODEFINE_HEADER__\r
-#define __RX113IODEFINE_HEADER__\r
-#pragma bit_order left\r
-#pragma unpack\r
-struct st_bsc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char STSCLR:1;\r
- } BIT;\r
- } BERCLR;\r
- char wk0[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char TOEN:1;\r
- unsigned char IGAEN:1;\r
- } BIT;\r
- } BEREN;\r
- char wk1[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char MST:3;\r
- unsigned char :2;\r
- unsigned char TO:1;\r
- unsigned char IA:1;\r
- } BIT;\r
- } BERSR1;\r
- char wk2[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short ADDR:13;\r
- } BIT;\r
- } BERSR2;\r
- char wk3[4];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :4;\r
- unsigned short BPFB:2;\r
- unsigned short :2;\r
- unsigned short BPGB:2;\r
- unsigned short BPIB:2;\r
- unsigned short BPRO:2;\r
- unsigned short BPRA:2;\r
- } BIT;\r
- } BUSPRI;\r
-};\r
-\r
-struct st_cac {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char CFME:1;\r
- } BIT;\r
- } CACR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char EDGES:2;\r
- unsigned char TCSS:2;\r
- unsigned char FMCS:3;\r
- unsigned char CACREFE:1;\r
- } BIT;\r
- } CACR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char DFS:2;\r
- unsigned char RCDS:2;\r
- unsigned char RSCS:3;\r
- unsigned char RPS:1;\r
- } BIT;\r
- } CACR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char OVFFCL:1;\r
- unsigned char MENDFCL:1;\r
- unsigned char FERRFCL:1;\r
- unsigned char :1;\r
- unsigned char OVFIE:1;\r
- unsigned char MENDIE:1;\r
- unsigned char FERRIE:1;\r
- } BIT;\r
- } CAICR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char OVFF:1;\r
- unsigned char MENDF:1;\r
- unsigned char FERRF:1;\r
- } BIT;\r
- } CASTR;\r
- char wk0[1];\r
- unsigned short CAULVR;\r
- unsigned short CALLVR;\r
- unsigned short CACNTBR;\r
-};\r
-\r
-struct st_cmpb {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char CPB1INI:1;\r
- unsigned char :3;\r
- unsigned char CPB0INI:1;\r
- } BIT;\r
- } CPBCNT1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char CPB1WCP:1;\r
- unsigned char :3;\r
- unsigned char CPB0WCP:1;\r
- } BIT;\r
- } CPBCNT2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CPB1OUT:1;\r
- unsigned char :3;\r
- unsigned char CPB0OUT:1;\r
- } BIT;\r
- } CPBFLG;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char CPB1INTPL:1;\r
- unsigned char CPB1INTEG:1;\r
- unsigned char CPB1INTEN:1;\r
- unsigned char :1;\r
- unsigned char CPB0INTPL:1;\r
- unsigned char CPB0INTEG:1;\r
- unsigned char CPB0INTEN:1;\r
- } BIT;\r
- } CPBINT;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CPB1F:2;\r
- unsigned char :1;\r
- unsigned char CPB1FEN:1;\r
- unsigned char CPB0F:2;\r
- unsigned char :1;\r
- unsigned char CPB0FEN:1;\r
- } BIT;\r
- } CPBF;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char CPBSPDMD:1;\r
- } BIT;\r
- } CPBMD;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char CPB1VRF:1;\r
- unsigned char :3;\r
- unsigned char CPB0VRF:1;\r
- } BIT;\r
- } CPBREF;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char CPB1OP:1;\r
- unsigned char CPB1OE:1;\r
- unsigned char :2;\r
- unsigned char CPB0OP:1;\r
- unsigned char CPB0OE:1;\r
- } BIT;\r
- } CPBOCR;\r
-};\r
-\r
-struct st_cmt {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :14;\r
- unsigned short STR1:1;\r
- unsigned short STR0:1;\r
- } BIT;\r
- } CMSTR0;\r
- char wk0[14];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :14;\r
- unsigned short STR3:1;\r
- unsigned short STR2:1;\r
- } BIT;\r
- } CMSTR1;\r
-};\r
-\r
-struct st_cmt0 {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :9;\r
- unsigned short CMIE:1;\r
- unsigned short :4;\r
- unsigned short CKS:2;\r
- } BIT;\r
- } CMCR;\r
- unsigned short CMCNT;\r
- unsigned short CMCOR;\r
-};\r
-\r
-struct st_crc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char DORCLR:1;\r
- unsigned char :4;\r
- unsigned char LMS:1;\r
- unsigned char GPS:2;\r
- } BIT;\r
- } CRCCR;\r
- unsigned char CRCDIR;\r
- unsigned short CRCDOR;\r
-};\r
-\r
-struct st_ctsu {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char CTSUINIT:1;\r
- unsigned char CTSUIOC:1;\r
- unsigned char CTSUSNZ:1;\r
- unsigned char CTSUCAP:1;\r
- unsigned char CTSUSTRT:1;\r
- } BIT;\r
- } CTSUCR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CTSUMD:2;\r
- unsigned char CTSUCLK:2;\r
- unsigned char CTSUATUNE1:1;\r
- unsigned char CTSUATUNE0:1;\r
- unsigned char CTSUCSW:1;\r
- unsigned char CTSUPON:1;\r
- } BIT;\r
- } CTSUCR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char CTSUSOFF:1;\r
- unsigned char CTSUPRMODE:2;\r
- unsigned char CTSUPRRATIO:4;\r
- } BIT;\r
- } CTSUSDPRS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CTSUSST:8;\r
- } BIT;\r
- } CTSUSST;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char CTSUMCH0:4;\r
- } BIT;\r
- } CTSUMCH0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char CTSUMCH1:4;\r
- } BIT;\r
- } CTSUMCH1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CTSUCHAC07:1;\r
- unsigned char CTSUCHAC06:1;\r
- unsigned char CTSUCHAC05:1;\r
- unsigned char CTSUCHAC04:1;\r
- unsigned char CTSUCHAC03:1;\r
- unsigned char CTSUCHAC02:1;\r
- unsigned char CTSUCHAC01:1;\r
- unsigned char CTSUCHAC00:1;\r
- } BIT;\r
- } CTSUCHAC0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char CTSUCHAC13:1;\r
- unsigned char CTSUCHAC12:1;\r
- unsigned char CTSUCHAC11:1;\r
- unsigned char CTSUCHAC10:1;\r
- } BIT;\r
- } CTSUCHAC1;\r
- char wk0[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CTSUCHTRC07:1;\r
- unsigned char CTSUCHTRC06:1;\r
- unsigned char CTSUCHTRC05:1;\r
- unsigned char CTSUCHTRC04:1;\r
- unsigned char CTSUCHTRC03:1;\r
- unsigned char CTSUCHTRC02:1;\r
- unsigned char CTSUCHTRC01:1;\r
- unsigned char CTSUCHTRC00:1;\r
- } BIT;\r
- } CTSUCHTRC0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char CTSUCHTRC13:1;\r
- unsigned char CTSUCHTRC12:1;\r
- unsigned char CTSUCHTRC11:1;\r
- unsigned char CTSUCHTRC10:1;\r
- } BIT;\r
- } CTSUCHTRC1;\r
- char wk1[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char CTSUSSCNT:2;\r
- unsigned char :2;\r
- unsigned char CTSUSSMOD:2;\r
- } BIT;\r
- } CTSUDCLKC;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CTSUPS:1;\r
- unsigned char CTSUROVF:1;\r
- unsigned char CTSUSOVF:1;\r
- unsigned char CTSUDTSR:1;\r
- unsigned char :1;\r
- unsigned char CTSUSTC:3;\r
- } BIT;\r
- } CTSUST;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :4;\r
- unsigned short CTSUSSDIV:4;\r
- } BIT;\r
- } CTSUSSC;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short CTSUSNUM:6;\r
- unsigned short CTSUSO:10;\r
- } BIT;\r
- } CTSUSO0;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :1;\r
- unsigned short CTSUICOG:2;\r
- unsigned short CTSUSDPA:5;\r
- unsigned short CTSURICOA:8;\r
- } BIT;\r
- } CTSUSO1;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short CTSUSC:16;\r
- } BIT;\r
- } CTSUSC;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short CTSURC:16;\r
- } BIT;\r
- } CTSURC;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short CTSUICOMP:1;\r
- } BIT;\r
- } CTSUERRS;\r
-};\r
-\r
-struct st_da {\r
- unsigned short DADR0;\r
- unsigned short DADR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char DAOE1:1;\r
- unsigned char DAOE0:1;\r
- } BIT;\r
- } DACR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char DPSEL:1;\r
- } BIT;\r
- } DADPR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char DAADST:1;\r
- } BIT;\r
- } DAADSCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char REF:3;\r
- } BIT;\r
- } DAVREFCR;\r
-};\r
-\r
-struct st_doc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char DOPCFCL:1;\r
- unsigned char DOPCF:1;\r
- unsigned char DOPCIE:1;\r
- unsigned char :1;\r
- unsigned char DCSEL:1;\r
- unsigned char OMS:2;\r
- } BIT;\r
- } DOCR;\r
- char wk0[1];\r
- unsigned short DODIR;\r
- unsigned short DODSR;\r
-};\r
-\r
-struct st_dtc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char RRS:1;\r
- } BIT;\r
- } DTCCR;\r
- char wk0[3];\r
- void *DTCVBR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char SHORT:1;\r
- } BIT;\r
- } DTCADMOD;\r
- char wk1[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char DTCST:1;\r
- } BIT;\r
- } DTCST;\r
- char wk2[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short ACT:1;\r
- unsigned short :7;\r
- unsigned short VECN:8;\r
- } BIT;\r
- } DTCSTS;\r
-};\r
-\r
-struct st_elc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ELCON:1;\r
- } BIT;\r
- } ELCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ELS:8;\r
- } BIT;\r
- } ELSR[26];\r
- char wk0[4];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char MTU3MD:2;\r
- unsigned char MTU2MD:2;\r
- unsigned char MTU1MD:2;\r
- } BIT;\r
- } ELOPA;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char MTU4MD:2;\r
- } BIT;\r
- } ELOPB;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char CMT1MD:2;\r
- } BIT;\r
- } ELOPC;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char TMR2MD:2;\r
- unsigned char :2;\r
- unsigned char TMR0MD:2;\r
- } BIT;\r
- } ELOPD;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char PGR7:1;\r
- unsigned char PGR6:1;\r
- unsigned char PGR5:1;\r
- unsigned char PGR4:1;\r
- unsigned char PGR3:1;\r
- unsigned char PGR2:1;\r
- unsigned char PGR1:1;\r
- unsigned char PGR0:1;\r
- } BIT;\r
- } PGR1;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char PGCO:3;\r
- unsigned char :1;\r
- unsigned char PGCOVE:1;\r
- unsigned char PGCI:2;\r
- } BIT;\r
- } PGC1;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char PDBF7:1;\r
- unsigned char PDBF6:1;\r
- unsigned char PDBF5:1;\r
- unsigned char PDBF4:1;\r
- unsigned char PDBF3:1;\r
- unsigned char PDBF2:1;\r
- unsigned char PDBF1:1;\r
- unsigned char PDBF0:1;\r
- } BIT;\r
- } PDBF1;\r
- char wk3[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char PSM:2;\r
- unsigned char PSP:2;\r
- unsigned char PSB:3;\r
- } BIT;\r
- } PEL0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char PSM:2;\r
- unsigned char PSP:2;\r
- unsigned char PSB:3;\r
- } BIT;\r
- } PEL1;\r
- char wk4[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char WI:1;\r
- unsigned char WE:1;\r
- unsigned char :5;\r
- unsigned char SEG:1;\r
- } BIT;\r
- } ELSEGR;\r
-};\r
-\r
-struct st_flash {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char DFLEN:1;\r
- } BIT;\r
- } DFLCTL;\r
- char wk0[31];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :7;\r
- unsigned short SASMF:1;\r
- } BIT;\r
- } FSCMR;\r
- unsigned short FAWSMR;\r
- unsigned short FAWEMR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char SAS:2;\r
- unsigned char :1;\r
- unsigned char PCKA:5;\r
- } BIT;\r
- } FISR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char OPST:1;\r
- unsigned char :4;\r
- unsigned char CMD:3;\r
- } BIT;\r
- } FEXCR;\r
- unsigned short FEAML;\r
-// char wk1[1];\r
- unsigned char FEAMH;\r
- char wk2[5];\r
- unsigned char FPR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char PERR:1;\r
- } BIT;\r
- } FPSR;\r
- unsigned short FRBL;\r
- unsigned short FRBH;\r
- char wk3[16058];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char FMS2:1;\r
- unsigned char LVPE:1;\r
- unsigned char :1;\r
- unsigned char FMS1:1;\r
- unsigned char RPDIS:1;\r
- unsigned char :1;\r
- unsigned char FMS0:1;\r
- } BIT;\r
- } FPMCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char EXS:1;\r
- } BIT;\r
- } FASR;\r
- unsigned short FSARL;\r
-// char wk4[1];\r
- unsigned char FSARH;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char OPST:1;\r
- unsigned char STOP:1;\r
- unsigned char :1;\r
- unsigned char DRC:1;\r
- unsigned char CMD:4;\r
- } BIT;\r
- } FCR;\r
- unsigned short FEARL;\r
- unsigned char FEARH;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char FRESET:1;\r
- } BIT;\r
- } FRESETR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char EILGLERR:1;\r
- unsigned char ILGLERR:1;\r
- unsigned char BCERR:1;\r
- unsigned char :1;\r
- unsigned char PRGERR:1;\r
- unsigned char ERERR:1;\r
- } BIT;\r
- } FSTATR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char EXRDY:1;\r
- unsigned char FRDY:1;\r
- unsigned char :4;\r
- unsigned char DRRDY:1;\r
- } BIT;\r
- } FSTATR1;\r
- unsigned short FWBL;\r
- unsigned short FWBH;\r
- char wk5[34];\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short FEKEY:8;\r
-// unsigned short FENTRYD:1;\r
-// unsigned short :6;\r
-// unsigned short FENTRY0:1;\r
-// } BIT;\r
- } FENTRYR;\r
-};\r
-\r
-struct st_icu {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char IR:1;\r
- } BIT;\r
- } IR[250];\r
- char wk0[6];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char DTCE:1;\r
- } BIT;\r
- } DTCER[249];\r
- char wk1[7];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IEN7:1;\r
- unsigned char IEN6:1;\r
- unsigned char IEN5:1;\r
- unsigned char IEN4:1;\r
- unsigned char IEN3:1;\r
- unsigned char IEN2:1;\r
- unsigned char IEN1:1;\r
- unsigned char IEN0:1;\r
- } BIT;\r
- } IER[32];\r
- char wk2[192];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char SWINT:1;\r
- } BIT;\r
- } SWINTR;\r
- char wk3[15];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short FIEN:1;\r
- unsigned short :7;\r
- unsigned short FVCT:8;\r
- } BIT;\r
- } FIR;\r
- char wk4[14];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char IPR:4;\r
- } BIT;\r
- } IPR[250];\r
- char wk5[262];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char IRQMD:2;\r
- } BIT;\r
- } IRQCR[8];\r
- char wk6[8];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char FLTEN7:1;\r
- unsigned char FLTEN6:1;\r
- unsigned char FLTEN5:1;\r
- unsigned char FLTEN4:1;\r
- unsigned char FLTEN3:1;\r
- unsigned char FLTEN2:1;\r
- unsigned char FLTEN1:1;\r
- unsigned char FLTEN0:1;\r
- } BIT;\r
- } IRQFLTE0;\r
- char wk7[3];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short FCLKSEL7:2;\r
- unsigned short FCLKSEL6:2;\r
- unsigned short FCLKSEL5:2;\r
- unsigned short FCLKSEL4:2;\r
- unsigned short FCLKSEL3:2;\r
- unsigned short FCLKSEL2:2;\r
- unsigned short FCLKSEL1:2;\r
- unsigned short FCLKSEL0:2;\r
- } BIT;\r
- } IRQFLTC0;\r
- char wk8[106];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char LVD2ST:1;\r
- unsigned char LVD1ST:1;\r
- unsigned char IWDTST:1;\r
- unsigned char :1;\r
- unsigned char OSTST:1;\r
- unsigned char NMIST:1;\r
- } BIT;\r
- } NMISR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char LVD2EN:1;\r
- unsigned char LVD1EN:1;\r
- unsigned char IWDTEN:1;\r
- unsigned char :1;\r
- unsigned char OSTEN:1;\r
- unsigned char NMIEN:1;\r
- } BIT;\r
- } NMIER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char LVD2CLR:1;\r
- unsigned char LVD1CLR:1;\r
- unsigned char IWDTCLR:1;\r
- unsigned char :1;\r
- unsigned char OSTCLR:1;\r
- unsigned char NMICLR:1;\r
- } BIT;\r
- } NMICLR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char NMIMD:1;\r
- } BIT;\r
- } NMICR;\r
- char wk9[12];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char NFLTEN:1;\r
- } BIT;\r
- } NMIFLTE;\r
- char wk10[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char NFCLKSEL:2;\r
- } BIT;\r
- } NMIFLTC;\r
-};\r
-\r
-struct st_irda {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IRE:1;\r
- unsigned char IRCKS:3;\r
- unsigned char IRTXINV:1;\r
- unsigned char IRRXINV:1;\r
- } BIT;\r
- } IRCR;\r
-};\r
-\r
-struct st_iwdt {\r
- unsigned char IWDTRR;\r
- char wk0[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :2;\r
- unsigned short RPSS:2;\r
- unsigned short :2;\r
- unsigned short RPES:2;\r
- unsigned short CKS:4;\r
- unsigned short :2;\r
- unsigned short TOPS:2;\r
- } BIT;\r
- } IWDTCR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short REFEF:1;\r
- unsigned short UNDFF:1;\r
- unsigned short CNTVAL:14;\r
- } BIT;\r
- } IWDTSR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char RSTIRQS:1;\r
- } BIT;\r
- } IWDTRCR;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char SLCSTP:1;\r
- } BIT;\r
- } IWDTCSTPR;\r
-};\r
-\r
-struct st_lcdc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char MDSET:2;\r
- unsigned char LWAVE:1;\r
- unsigned char LDTY:3;\r
- unsigned char LBAS:2;\r
- } BIT;\r
- } LCDM0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char LCDON:1;\r
- unsigned char SCOC:1;\r
- unsigned char VLCON:1;\r
- unsigned char BLON:1;\r
- unsigned char LCDSEL:1;\r
- unsigned char :2;\r
- unsigned char LCDVLM:1;\r
- } BIT;\r
- } LCDM1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char LCDC0:6;\r
- } BIT;\r
- } LCDC0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char VLCD:5;\r
- } BIT;\r
- } VLCD;\r
- char wk0[60];\r
- unsigned char SEG00;\r
- unsigned char SEG01;\r
- unsigned char SEG02;\r
- unsigned char SEG03;\r
- unsigned char SEG04;\r
- unsigned char SEG05;\r
- unsigned char SEG06;\r
- unsigned char SEG07;\r
- unsigned char SEG08;\r
- unsigned char SEG09;\r
- unsigned char SEG10;\r
- unsigned char SEG11;\r
- unsigned char SEG12;\r
- unsigned char SEG13;\r
- unsigned char SEG14;\r
- unsigned char SEG15;\r
- unsigned char SEG16;\r
- unsigned char SEG17;\r
- unsigned char SEG18;\r
- unsigned char SEG19;\r
- unsigned char SEG20;\r
- unsigned char SEG21;\r
- unsigned char SEG22;\r
- unsigned char SEG23;\r
- unsigned char SEG24;\r
- unsigned char SEG25;\r
- unsigned char SEG26;\r
- unsigned char SEG27;\r
- unsigned char SEG28;\r
- unsigned char SEG29;\r
- unsigned char SEG30;\r
- unsigned char SEG31;\r
- unsigned char SEG32;\r
- unsigned char SEG33;\r
- unsigned char SEG34;\r
- unsigned char SEG35;\r
- unsigned char SEG36;\r
- unsigned char SEG37;\r
- unsigned char SEG38;\r
- unsigned char SEG39;\r
-};\r
-\r
-struct st_mpc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B0WI:1;\r
- unsigned char PFSWE:1;\r
- } BIT;\r
- } PWPR;\r
- char wk0[34];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P02PFS;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P04PFS;\r
- char wk2[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P07PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P10PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P11PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P12PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P13PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P14PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P15PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P16PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P17PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P20PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P21PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P22PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P23PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P24PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P25PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P26PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P27PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P30PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P31PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P32PFS;\r
- char wk3[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- } BIT;\r
- } P35PFS;\r
- char wk4[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } P40PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } P41PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } P42PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } P43PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } P44PFS;\r
- char wk5[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } P46PFS;\r
- char wk6[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P50PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P51PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P52PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P53PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P54PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P55PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } P56PFS;\r
- char wk7[25];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } P90PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } P91PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } P92PFS;\r
- char wk8[5];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PA0PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PA1PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PA2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PA3PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PA4PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PA5PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PA6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PA7PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PB0PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PB1PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PB2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PB3PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PB4PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PB5PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PB6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PB7PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PC0PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PC1PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PC2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PC3PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PC4PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PC5PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PC6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PC7PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PD0PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PD1PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PD2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PD3PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PD4PFS;\r
- char wk9[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PE0PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PE1PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PE2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PE3PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PE4PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PE5PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PE6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- unsigned char ISEL:1;\r
- unsigned char :1;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PE7PFS;\r
- char wk10[6];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PF6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PF7PFS;\r
- char wk11[16];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } PJ0PFS;\r
- char wk12[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } PJ2PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char PSEL:5;\r
- } BIT;\r
- } PJ3PFS;\r
- char wk13[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } PJ6PFS;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ASEL:1;\r
- } BIT;\r
- } PJ7PFS;\r
-};\r
-\r
-struct st_mtu {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char OE4D:1;\r
- unsigned char OE4C:1;\r
- unsigned char OE3D:1;\r
- unsigned char OE4B:1;\r
- unsigned char OE4A:1;\r
- unsigned char OE3B:1;\r
- } BIT;\r
- } TOER;\r
- char wk0[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char BDC:1;\r
- unsigned char N:1;\r
- unsigned char P:1;\r
- unsigned char FB:1;\r
- unsigned char WF:1;\r
- unsigned char VF:1;\r
- unsigned char UF:1;\r
- } BIT;\r
- } TGCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char PSYE:1;\r
- unsigned char :2;\r
- unsigned char TOCL:1;\r
- unsigned char TOCS:1;\r
- unsigned char OLSN:1;\r
- unsigned char OLSP:1;\r
- } BIT;\r
- } TOCR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BF:2;\r
- unsigned char OLS3N:1;\r
- unsigned char OLS3P:1;\r
- unsigned char OLS2N:1;\r
- unsigned char OLS2P:1;\r
- unsigned char OLS1N:1;\r
- unsigned char OLS1P:1;\r
- } BIT;\r
- } TOCR2;\r
- char wk1[4];\r
- unsigned short TCDR;\r
- unsigned short TDDR;\r
- char wk2[8];\r
- unsigned short TCNTS;\r
- unsigned short TCBR;\r
- char wk3[12];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char T3AEN:1;\r
- unsigned char T3ACOR:3;\r
- unsigned char T4VEN:1;\r
- unsigned char T4VCOR:3;\r
- } BIT;\r
- } TITCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char T3ACNT:3;\r
- unsigned char :1;\r
- unsigned char T4VCNT:3;\r
- } BIT;\r
- } TITCNT;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char BTE:2;\r
- } BIT;\r
- } TBTER;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char TDER:1;\r
- } BIT;\r
- } TDER;\r
- char wk5[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char OLS3N:1;\r
- unsigned char OLS3P:1;\r
- unsigned char OLS2N:1;\r
- unsigned char OLS2P:1;\r
- unsigned char OLS1N:1;\r
- unsigned char OLS1P:1;\r
- } BIT;\r
- } TOLBR;\r
- char wk6[41];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CCE:1;\r
- unsigned char :6;\r
- unsigned char WRE:1;\r
- } BIT;\r
- } TWCR;\r
- char wk7[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CST4:1;\r
- unsigned char CST3:1;\r
- unsigned char :3;\r
- unsigned char CST2:1;\r
- unsigned char CST1:1;\r
- unsigned char CST0:1;\r
- } BIT;\r
- } TSTR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char SYNC4:1;\r
- unsigned char SYNC3:1;\r
- unsigned char :3;\r
- unsigned char SYNC2:1;\r
- unsigned char SYNC1:1;\r
- unsigned char SYNC0:1;\r
- } BIT;\r
- } TSYR;\r
- char wk8[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char RWE:1;\r
- } BIT;\r
- } TRWER;\r
-};\r
-\r
-struct st_mtu0 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char NFCS:2;\r
- unsigned char NFDEN:1;\r
- unsigned char NFCEN:1;\r
- unsigned char NFBEN:1;\r
- unsigned char NFAEN:1;\r
- } BIT;\r
- } NFCR;\r
- char wk0[111];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CCLR:3;\r
- unsigned char CKEG:2;\r
- unsigned char TPSC:3;\r
- } BIT;\r
- } TCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char BFE:1;\r
- unsigned char BFB:1;\r
- unsigned char BFA:1;\r
- unsigned char MD:4;\r
- } BIT;\r
- } TMDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IOB:4;\r
- unsigned char IOA:4;\r
- } BIT;\r
- } TIORH;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IOD:4;\r
- unsigned char IOC:4;\r
- } BIT;\r
- } TIORL;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TTGE:1;\r
- unsigned char :2;\r
- unsigned char TCIEV:1;\r
- unsigned char TGIED:1;\r
- unsigned char TGIEC:1;\r
- unsigned char TGIEB:1;\r
- unsigned char TGIEA:1;\r
- } BIT;\r
- } TIER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TCFD:1;\r
- } BIT;\r
- } TSR;\r
- unsigned short TCNT;\r
- unsigned short TGRA;\r
- unsigned short TGRB;\r
- unsigned short TGRC;\r
- unsigned short TGRD;\r
- char wk1[16];\r
- unsigned short TGRE;\r
- unsigned short TGRF;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char TGIEF:1;\r
- unsigned char TGIEE:1;\r
- } BIT;\r
- } TIER2;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char TTSE:1;\r
- unsigned char TTSB:1;\r
- unsigned char TTSA:1;\r
- } BIT;\r
- } TBTM;\r
-};\r
-\r
-struct st_mtu1 {\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char NFCS:2;\r
- unsigned char NFDEN:1;\r
- unsigned char NFCEN:1;\r
- unsigned char NFBEN:1;\r
- unsigned char NFAEN:1;\r
- } BIT;\r
- } NFCR;\r
- char wk1[238];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char CCLR:2;\r
- unsigned char CKEG:2;\r
- unsigned char TPSC:3;\r
- } BIT;\r
- } TCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char MD:4;\r
- } BIT;\r
- } TMDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IOB:4;\r
- unsigned char IOA:4;\r
- } BIT;\r
- } TIOR;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TTGE:1;\r
- unsigned char :1;\r
- unsigned char TCIEU:1;\r
- unsigned char TCIEV:1;\r
- unsigned char :2;\r
- unsigned char TGIEB:1;\r
- unsigned char TGIEA:1;\r
- } BIT;\r
- } TIER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TCFD:1;\r
- } BIT;\r
- } TSR;\r
- unsigned short TCNT;\r
- unsigned short TGRA;\r
- unsigned short TGRB;\r
- char wk3[4];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char I2BE:1;\r
- unsigned char I2AE:1;\r
- unsigned char I1BE:1;\r
- unsigned char I1AE:1;\r
- } BIT;\r
- } TICCR;\r
-};\r
-\r
-struct st_mtu2 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char NFCS:2;\r
- unsigned char NFDEN:1;\r
- unsigned char NFCEN:1;\r
- unsigned char NFBEN:1;\r
- unsigned char NFAEN:1;\r
- } BIT;\r
- } NFCR;\r
- char wk0[365];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char CCLR:2;\r
- unsigned char CKEG:2;\r
- unsigned char TPSC:3;\r
- } BIT;\r
- } TCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char MD:4;\r
- } BIT;\r
- } TMDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IOB:4;\r
- unsigned char IOA:4;\r
- } BIT;\r
- } TIOR;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TTGE:1;\r
- unsigned char :1;\r
- unsigned char TCIEU:1;\r
- unsigned char TCIEV:1;\r
- unsigned char :2;\r
- unsigned char TGIEB:1;\r
- unsigned char TGIEA:1;\r
- } BIT;\r
- } TIER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TCFD:1;\r
- } BIT;\r
- } TSR;\r
- unsigned short TCNT;\r
- unsigned short TGRA;\r
- unsigned short TGRB;\r
-};\r
-\r
-struct st_mtu3 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CCLR:3;\r
- unsigned char CKEG:2;\r
- unsigned char TPSC:3;\r
- } BIT;\r
- } TCR;\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char BFB:1;\r
- unsigned char BFA:1;\r
- unsigned char MD:4;\r
- } BIT;\r
- } TMDR;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IOB:4;\r
- unsigned char IOA:4;\r
- } BIT;\r
- } TIORH;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IOD:4;\r
- unsigned char IOC:4;\r
- } BIT;\r
- } TIORL;\r
- char wk2[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TTGE:1;\r
- unsigned char :2;\r
- unsigned char TCIEV:1;\r
- unsigned char TGIED:1;\r
- unsigned char TGIEC:1;\r
- unsigned char TGIEB:1;\r
- unsigned char TGIEA:1;\r
- } BIT;\r
- } TIER;\r
- char wk3[7];\r
- unsigned short TCNT;\r
- char wk4[6];\r
- unsigned short TGRA;\r
- unsigned short TGRB;\r
- char wk5[8];\r
- unsigned short TGRC;\r
- unsigned short TGRD;\r
- char wk6[4];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TCFD:1;\r
- } BIT;\r
- } TSR;\r
- char wk7[11];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char TTSE:1;\r
- unsigned char TTSB:1;\r
- unsigned char TTSA:1;\r
- } BIT;\r
- } TBTM;\r
- char wk8[90];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char NFCS:2;\r
- unsigned char NFDEN:1;\r
- unsigned char NFCEN:1;\r
- unsigned char NFBEN:1;\r
- unsigned char NFAEN:1;\r
- } BIT;\r
- } NFCR;\r
-};\r
-\r
-struct st_mtu4 {\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CCLR:3;\r
- unsigned char CKEG:2;\r
- unsigned char TPSC:3;\r
- } BIT;\r
- } TCR;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char BFB:1;\r
- unsigned char BFA:1;\r
- unsigned char MD:4;\r
- } BIT;\r
- } TMDR;\r
- char wk2[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IOB:4;\r
- unsigned char IOA:4;\r
- } BIT;\r
- } TIORH;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IOD:4;\r
- unsigned char IOC:4;\r
- } BIT;\r
- } TIORL;\r
- char wk3[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TTGE:1;\r
- unsigned char TTGE2:1;\r
- unsigned char :1;\r
- unsigned char TCIEV:1;\r
- unsigned char TGIED:1;\r
- unsigned char TGIEC:1;\r
- unsigned char TGIEB:1;\r
- unsigned char TGIEA:1;\r
- } BIT;\r
- } TIER;\r
- char wk4[8];\r
- unsigned short TCNT;\r
- char wk5[8];\r
- unsigned short TGRA;\r
- unsigned short TGRB;\r
- char wk6[8];\r
- unsigned short TGRC;\r
- unsigned short TGRD;\r
- char wk7[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TCFD:1;\r
- } BIT;\r
- } TSR;\r
- char wk8[11];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char TTSE:1;\r
- unsigned char TTSB:1;\r
- unsigned char TTSA:1;\r
- } BIT;\r
- } TBTM;\r
- char wk9[6];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BF:2;\r
- unsigned short :6;\r
- unsigned short UT4AE:1;\r
- unsigned short DT4AE:1;\r
- unsigned short UT4BE:1;\r
- unsigned short DT4BE:1;\r
- unsigned short ITA3AE:1;\r
- unsigned short ITA4VE:1;\r
- unsigned short ITB3AE:1;\r
- unsigned short ITB4VE:1;\r
- } BIT;\r
- } TADCR;\r
- char wk10[2];\r
- unsigned short TADCORA;\r
- unsigned short TADCORB;\r
- unsigned short TADCOBRA;\r
- unsigned short TADCOBRB;\r
- char wk11[72];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char NFCS:2;\r
- unsigned char NFDEN:1;\r
- unsigned char NFCEN:1;\r
- unsigned char NFBEN:1;\r
- unsigned char NFAEN:1;\r
- } BIT;\r
- } NFCR;\r
-};\r
-\r
-struct st_mtu5 {\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char NFCS:2;\r
- unsigned char :1;\r
- unsigned char NFWEN:1;\r
- unsigned char NFVEN:1;\r
- unsigned char NFUEN:1;\r
- } BIT;\r
- } NFCR;\r
- char wk1[490];\r
- unsigned short TCNTU;\r
- unsigned short TGRU;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char TPSC:2;\r
- } BIT;\r
- } TCRU;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char IOC:5;\r
- } BIT;\r
- } TIORU;\r
- char wk3[9];\r
- unsigned short TCNTV;\r
- unsigned short TGRV;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char TPSC:2;\r
- } BIT;\r
- } TCRV;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char IOC:5;\r
- } BIT;\r
- } TIORV;\r
- char wk5[9];\r
- unsigned short TCNTW;\r
- unsigned short TGRW;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char TPSC:2;\r
- } BIT;\r
- } TCRW;\r
- char wk6[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char IOC:5;\r
- } BIT;\r
- } TIORW;\r
- char wk7[11];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char TGIE5U:1;\r
- unsigned char TGIE5V:1;\r
- unsigned char TGIE5W:1;\r
- } BIT;\r
- } TIER;\r
- char wk8[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char CSTU5:1;\r
- unsigned char CSTV5:1;\r
- unsigned char CSTW5:1;\r
- } BIT;\r
- } TSTR;\r
- char wk9[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char CMPCLR5U:1;\r
- unsigned char CMPCLR5V:1;\r
- unsigned char CMPCLR5W:1;\r
- } BIT;\r
- } TCNTCMPCLR;\r
-};\r
-\r
-struct st_poe {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char H;\r
- unsigned char L;\r
- } BYTE;\r
- struct {\r
- unsigned char POE3F:1;\r
- unsigned char POE2F:1;\r
- unsigned char POE1F:1;\r
- unsigned char POE0F:1;\r
- unsigned char :3;\r
- unsigned char PIE1:1;\r
- unsigned char POE3M:2;\r
- unsigned char POE2M:2;\r
- unsigned char POE1M:2;\r
- unsigned char POE0M:2;\r
- } BIT;\r
- } ICSR1;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char H;\r
- unsigned char L;\r
- } BYTE;\r
- struct {\r
- unsigned char OSF1:1;\r
- unsigned char :5;\r
- unsigned char OCE1:1;\r
- unsigned char OIE1:1;\r
- } BIT;\r
- } OCSR1;\r
- char wk0[4];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char H;\r
- unsigned char L;\r
- } BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char POE8F:1;\r
- unsigned char :2;\r
- unsigned char POE8E:1;\r
- unsigned char PIE2:1;\r
- unsigned char :6;\r
- unsigned char POE8M:2;\r
- } BIT;\r
- } ICSR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char CH0HIZ:1;\r
- unsigned char CH34HIZ:1;\r
- } BIT;\r
- } SPOER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char PE3ZE:1;\r
- unsigned char PE2ZE:1;\r
- unsigned char PE1ZE:1;\r
- unsigned char PE0ZE:1;\r
- } BIT;\r
- } POECR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char P1CZEA:1;\r
- unsigned char P2CZEA:1;\r
- unsigned char P3CZEA:1;\r
- } BIT;\r
- } POECR2;\r
- char wk1[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char H;\r
- unsigned char L;\r
- } BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char OSTSTF:1;\r
- unsigned char :2;\r
- unsigned char OSTSTE:1;\r
- } BIT;\r
- } ICSR3;\r
-};\r
-\r
-struct st_port {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char PSEL7:1;\r
- unsigned char PSEL6:1;\r
- } BIT;\r
- } PSRA;\r
-};\r
-\r
-struct st_port0 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char :2;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char :2;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char :2;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char :2;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char B4:1;\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :5;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR1;\r
- char wk4[62];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char :2;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_port1 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[32];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR1;\r
- char wk4[61];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_port2 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[33];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR1;\r
- char wk4[60];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_port3 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char B5:1;\r
- unsigned char :2;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[34];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR0;\r
- char wk4[60];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_port4 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
-};\r
-\r
-struct st_port5 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[36];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char B4:1;\r
- } BIT;\r
- } ODR1;\r
- char wk4[57];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_port9 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
-};\r
-\r
-struct st_porta {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[41];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR1;\r
- char wk4[52];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_portb {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[42];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR1;\r
- char wk4[51];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_portc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[43];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR1;\r
- char wk4[50];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_portd {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[95];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_porte {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[45];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- unsigned char :1;\r
- unsigned char B4:1;\r
- unsigned char :1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } ODR1;\r
- char wk4[48];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char B5:1;\r
- unsigned char B4:1;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char B1:1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_portf {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[95];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_porth {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- } BIT;\r
- } PIDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- } BIT;\r
- } PMR;\r
-};\r
-\r
-struct st_portj {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char :2;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PDR;\r
- char wk0[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char :2;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PODR;\r
- char wk1[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char :2;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PIDR;\r
- char wk2[31];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char B7:1;\r
- unsigned char B6:1;\r
- unsigned char :2;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PMR;\r
- char wk3[49];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char B6:1;\r
- } BIT;\r
- } ODR0;\r
- char wk4[45];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char B3:1;\r
- unsigned char B2:1;\r
- unsigned char :1;\r
- unsigned char B0:1;\r
- } BIT;\r
- } PCR;\r
-};\r
-\r
-struct st_riic {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ICE:1;\r
- unsigned char IICRST:1;\r
- unsigned char CLO:1;\r
- unsigned char SOWP:1;\r
- unsigned char SCLO:1;\r
- unsigned char SDAO:1;\r
- unsigned char SCLI:1;\r
- unsigned char SDAI:1;\r
- } BIT;\r
- } ICCR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BBSY:1;\r
- unsigned char MST:1;\r
- unsigned char TRS:1;\r
- unsigned char :1;\r
- unsigned char SP:1;\r
- unsigned char RS:1;\r
- unsigned char ST:1;\r
- } BIT;\r
- } ICCR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char MTWP:1;\r
- unsigned char CKS:3;\r
- unsigned char BCWP:1;\r
- unsigned char BC:3;\r
- } BIT;\r
- } ICMR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char DLCS:1;\r
- unsigned char SDDL:3;\r
- unsigned char TMWE:1;\r
- unsigned char TMOH:1;\r
- unsigned char TMOL:1;\r
- unsigned char TMOS:1;\r
- } BIT;\r
- } ICMR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char SMBS:1;\r
- unsigned char WAIT:1;\r
- unsigned char RDRFS:1;\r
- unsigned char ACKWP:1;\r
- unsigned char ACKBT:1;\r
- unsigned char ACKBR:1;\r
- unsigned char NF:2;\r
- } BIT;\r
- } ICMR3;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char SCLE:1;\r
- unsigned char NFE:1;\r
- unsigned char NACKE:1;\r
- unsigned char SALE:1;\r
- unsigned char NALE:1;\r
- unsigned char MALE:1;\r
- unsigned char TMOE:1;\r
- } BIT;\r
- } ICFER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char HOAE:1;\r
- unsigned char :1;\r
- unsigned char DIDE:1;\r
- unsigned char :1;\r
- unsigned char GCAE:1;\r
- unsigned char SAR2E:1;\r
- unsigned char SAR1E:1;\r
- unsigned char SAR0E:1;\r
- } BIT;\r
- } ICSER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TIE:1;\r
- unsigned char TEIE:1;\r
- unsigned char RIE:1;\r
- unsigned char NAKIE:1;\r
- unsigned char SPIE:1;\r
- unsigned char STIE:1;\r
- unsigned char ALIE:1;\r
- unsigned char TMOIE:1;\r
- } BIT;\r
- } ICIER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char HOA:1;\r
- unsigned char :1;\r
- unsigned char DID:1;\r
- unsigned char :1;\r
- unsigned char GCA:1;\r
- unsigned char AAS2:1;\r
- unsigned char AAS1:1;\r
- unsigned char AAS0:1;\r
- } BIT;\r
- } ICSR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TDRE:1;\r
- unsigned char TEND:1;\r
- unsigned char RDRF:1;\r
- unsigned char NACKF:1;\r
- unsigned char STOP:1;\r
- unsigned char START:1;\r
- unsigned char AL:1;\r
- unsigned char TMOF:1;\r
- } BIT;\r
- } ICSR2;\r
- union {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char SVA:7;\r
- unsigned char SVA0:1;\r
- } BIT;\r
- } SARL0;\r
- union {\r
- unsigned char BYTE;\r
- } TMOCNTL;\r
- };\r
- union {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char SVA:2;\r
- unsigned char FS:1;\r
- } BIT;\r
- } SARU0;\r
- union {\r
- unsigned char BYTE;\r
- } TMOCNTU;\r
- };\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char SVA:7;\r
- unsigned char SVA0:1;\r
- } BIT;\r
- } SARL1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char SVA:2;\r
- unsigned char FS:1;\r
- } BIT;\r
- } SARU1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char SVA:7;\r
- unsigned char SVA0:1;\r
- } BIT;\r
- } SARL2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char SVA:2;\r
- unsigned char FS:1;\r
- } BIT;\r
- } SARU2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char BRL:5;\r
- } BIT;\r
- } ICBRL;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char BRH:5;\r
- } BIT;\r
- } ICBRH;\r
- unsigned char ICDRT;\r
- unsigned char ICDRR;\r
-};\r
-\r
-struct st_rspi {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char SPRIE:1;\r
- unsigned char SPE:1;\r
- unsigned char SPTIE:1;\r
- unsigned char SPEIE:1;\r
- unsigned char MSTR:1;\r
- unsigned char MODFEN:1;\r
- unsigned char TXMD:1;\r
- unsigned char SPMS:1;\r
- } BIT;\r
- } SPCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char SSL3P:1;\r
- unsigned char SSL2P:1;\r
- unsigned char SSL1P:1;\r
- unsigned char SSL0P:1;\r
- } BIT;\r
- } SSLP;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char MOIFE:1;\r
- unsigned char MOIFV:1;\r
- unsigned char :2;\r
- unsigned char SPLP2:1;\r
- unsigned char SPLP:1;\r
- } BIT;\r
- } SPPCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char PERF:1;\r
- unsigned char MODF:1;\r
- unsigned char IDLNF:1;\r
- unsigned char OVRF:1;\r
- } BIT;\r
- } SPSR;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned short H;\r
- } WORD;\r
- } SPDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char SPSLN:3;\r
- } BIT;\r
- } SPSCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char SPECM:3;\r
- unsigned char :1;\r
- unsigned char SPCP:3;\r
- } BIT;\r
- } SPSSR;\r
- unsigned char SPBR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char SPLW:1;\r
- unsigned char SPRDTD:1;\r
- unsigned char :2;\r
- unsigned char SPFC:2;\r
- } BIT;\r
- } SPDCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char SCKDL:3;\r
- } BIT;\r
- } SPCKD;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char SLNDL:3;\r
- } BIT;\r
- } SSLND;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char SPNDL:3;\r
- } BIT;\r
- } SPND;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char PTE:1;\r
- unsigned char SPIIE:1;\r
- unsigned char SPOE:1;\r
- unsigned char SPPE:1;\r
- } BIT;\r
- } SPCR2;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short SCKDEN:1;\r
- unsigned short SLNDEN:1;\r
- unsigned short SPNDEN:1;\r
- unsigned short LSBF:1;\r
- unsigned short SPB:4;\r
- unsigned short SSLKP:1;\r
- unsigned short SSLA:3;\r
- unsigned short BRDV:2;\r
- unsigned short CPOL:1;\r
- unsigned short CPHA:1;\r
- } BIT;\r
- } SPCMD0;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short SCKDEN:1;\r
- unsigned short SLNDEN:1;\r
- unsigned short SPNDEN:1;\r
- unsigned short LSBF:1;\r
- unsigned short SPB:4;\r
- unsigned short SSLKP:1;\r
- unsigned short SSLA:3;\r
- unsigned short BRDV:2;\r
- unsigned short CPOL:1;\r
- unsigned short CPHA:1;\r
- } BIT;\r
- } SPCMD1;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short SCKDEN:1;\r
- unsigned short SLNDEN:1;\r
- unsigned short SPNDEN:1;\r
- unsigned short LSBF:1;\r
- unsigned short SPB:4;\r
- unsigned short SSLKP:1;\r
- unsigned short SSLA:3;\r
- unsigned short BRDV:2;\r
- unsigned short CPOL:1;\r
- unsigned short CPHA:1;\r
- } BIT;\r
- } SPCMD2;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short SCKDEN:1;\r
- unsigned short SLNDEN:1;\r
- unsigned short SPNDEN:1;\r
- unsigned short LSBF:1;\r
- unsigned short SPB:4;\r
- unsigned short SSLKP:1;\r
- unsigned short SSLA:3;\r
- unsigned short BRDV:2;\r
- unsigned short CPOL:1;\r
- unsigned short CPHA:1;\r
- } BIT;\r
- } SPCMD3;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short SCKDEN:1;\r
- unsigned short SLNDEN:1;\r
- unsigned short SPNDEN:1;\r
- unsigned short LSBF:1;\r
- unsigned short SPB:4;\r
- unsigned short SSLKP:1;\r
- unsigned short SSLA:3;\r
- unsigned short BRDV:2;\r
- unsigned short CPOL:1;\r
- unsigned short CPHA:1;\r
- } BIT;\r
- } SPCMD4;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short SCKDEN:1;\r
- unsigned short SLNDEN:1;\r
- unsigned short SPNDEN:1;\r
- unsigned short LSBF:1;\r
- unsigned short SPB:4;\r
- unsigned short SSLKP:1;\r
- unsigned short SSLA:3;\r
- unsigned short BRDV:2;\r
- unsigned short CPOL:1;\r
- unsigned short CPHA:1;\r
- } BIT;\r
- } SPCMD5;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short SCKDEN:1;\r
- unsigned short SLNDEN:1;\r
- unsigned short SPNDEN:1;\r
- unsigned short LSBF:1;\r
- unsigned short SPB:4;\r
- unsigned short SSLKP:1;\r
- unsigned short SSLA:3;\r
- unsigned short BRDV:2;\r
- unsigned short CPOL:1;\r
- unsigned short CPHA:1;\r
- } BIT;\r
- } SPCMD6;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short SCKDEN:1;\r
- unsigned short SLNDEN:1;\r
- unsigned short SPNDEN:1;\r
- unsigned short LSBF:1;\r
- unsigned short SPB:4;\r
- unsigned short SSLKP:1;\r
- unsigned short SSLA:3;\r
- unsigned short BRDV:2;\r
- unsigned short CPOL:1;\r
- unsigned short CPHA:1;\r
- } BIT;\r
- } SPCMD7;\r
-};\r
-\r
-struct st_rtc {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char F1HZ:1;\r
- unsigned char F2HZ:1;\r
- unsigned char F4HZ:1;\r
- unsigned char F8HZ:1;\r
- unsigned char F16HZ:1;\r
- unsigned char F32HZ:1;\r
- unsigned char F64HZ:1;\r
- } BIT;\r
- } R64CNT;\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char SEC10:3;\r
- unsigned char SEC1:4;\r
- } BIT;\r
- } RSECCNT;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char MIN10:3;\r
- unsigned char MIN1:4;\r
- } BIT;\r
- } RMINCNT;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char PM:1;\r
- unsigned char HR10:2;\r
- unsigned char HR1:4;\r
- } BIT;\r
- } RHRCNT;\r
- char wk3[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char DAYW:3;\r
- } BIT;\r
- } RWKCNT;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char DATE10:2;\r
- unsigned char DATE1:4;\r
- } BIT;\r
- } RDAYCNT;\r
- char wk5[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char MON10:1;\r
- unsigned char MON1:4;\r
- } BIT;\r
- } RMONCNT;\r
- char wk6[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :8;\r
- unsigned short YR10:4;\r
- unsigned short YR1:4;\r
- } BIT;\r
- } RYRCNT;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ENB:1;\r
- unsigned char SEC10:3;\r
- unsigned char SEC1:4;\r
- } BIT;\r
- } RSECAR;\r
- char wk7[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ENB:1;\r
- unsigned char MIN10:3;\r
- unsigned char MIN1:4;\r
- } BIT;\r
- } RMINAR;\r
- char wk8[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ENB:1;\r
- unsigned char PM:1;\r
- unsigned char HR10:2;\r
- unsigned char HR1:4;\r
- } BIT;\r
- } RHRAR;\r
- char wk9[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ENB:1;\r
- unsigned char :4;\r
- unsigned char DAYW:3;\r
- } BIT;\r
- } RWKAR;\r
- char wk10[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ENB:1;\r
- unsigned char :1;\r
- unsigned char DATE10:2;\r
- unsigned char DATE1:4;\r
- } BIT;\r
- } RDAYAR;\r
- char wk11[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ENB:1;\r
- unsigned char :2;\r
- unsigned char MON10:1;\r
- unsigned char MON1:4;\r
- } BIT;\r
- } RMONAR;\r
- char wk12[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :8;\r
- unsigned short YR10:4;\r
- unsigned short YR1:4;\r
- } BIT;\r
- } RYRAR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ENB:1;\r
- } BIT;\r
- } RYRAREN;\r
- char wk13[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char PES:4;\r
- unsigned char RTCOS:1;\r
- unsigned char PIE:1;\r
- unsigned char CIE:1;\r
- unsigned char AIE:1;\r
- } BIT;\r
- } RCR1;\r
- char wk14[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CNTMD:1;\r
- unsigned char HR24:1;\r
- unsigned char AADJP:1;\r
- unsigned char AADJE:1;\r
- unsigned char RTCOE:1;\r
- unsigned char ADJ30:1;\r
- unsigned char RESET:1;\r
- unsigned char START:1;\r
- } BIT;\r
- } RCR2;\r
- char wk15[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char RTCDV:3;\r
- unsigned char RTCEN:1;\r
- } BIT;\r
- } RCR3;\r
- char wk16[7];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char PMADJ:2;\r
- unsigned char ADJ:6;\r
- } BIT;\r
- } RADJ;\r
-};\r
-\r
-struct st_rtcb {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BCNT:8;\r
- } BIT;\r
- } BCNT0;\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BCNT:8;\r
- } BIT;\r
- } BCNT1;\r
- char wk1[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BCNT:8;\r
- } BIT;\r
- } BCNT2;\r
- char wk2[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BCNT:8;\r
- } BIT;\r
- } BCNT3;\r
- char wk3[7];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BCNTAR:8;\r
- } BIT;\r
- } BCNT0AR;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BCNTAR:8;\r
- } BIT;\r
- } BCNT1AR;\r
- char wk5[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BCNTAR:8;\r
- } BIT;\r
- } BCNT2AR;\r
- char wk6[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BCNTAR:8;\r
- } BIT;\r
- } BCNT3AR;\r
- char wk7[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ENB:8;\r
- } BIT;\r
- } BCNT0AER;\r
- char wk8[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ENB:8;\r
- } BIT;\r
- } BCNT1AER;\r
- char wk9[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :8;\r
- unsigned short ENB:8;\r
- } BIT;\r
- } BCNT2AER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char ENB:8;\r
- } BIT;\r
- } BCNT3AER;\r
-};\r
-\r
-struct st_s12ad {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short ADST:1;\r
- unsigned short ADCS:2;\r
- unsigned short ADIE:1;\r
- unsigned short :1;\r
- unsigned short ADHSC:1;\r
- unsigned short TRGE:1;\r
- unsigned short EXTRG:1;\r
- unsigned short DBLE:1;\r
- unsigned short GBADIE:1;\r
- unsigned short :1;\r
- unsigned short DBLANS:5;\r
- } BIT;\r
- } ADCSR;\r
- char wk0[2];\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short ANSA:16;\r
-// } BIT;\r
- } ADANSA;\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short :10;\r
-// unsigned short ANSA1:1;\r
-// } BIT;\r
- } ADANSA1;\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short ADS:16;\r
-// } BIT;\r
- } ADADS;\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short :10;\r
-// unsigned short ADS1:1;\r
-// } BIT;\r
- } ADADS1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char ADC:2;\r
- } BIT;\r
- } ADADC;\r
- char wk1[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short ADRFMT:1;\r
- unsigned short :9;\r
- unsigned short ACE:1;\r
- } BIT;\r
- } ADCER;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :4;\r
- unsigned short TRSA:4;\r
- unsigned short :4;\r
- unsigned short TRSB:4;\r
- } BIT;\r
- } ADSTRGR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short OCS:1;\r
- unsigned short TSS:1;\r
- unsigned short :6;\r
- unsigned short OCSAD:1;\r
- unsigned short TSSAD:1;\r
- } BIT;\r
- } ADEXICR;\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short ANSB:16;\r
-// } BIT;\r
- } ADANSB;\r
- union {\r
- unsigned short WORD;\r
-// struct {\r
-// unsigned short :10;\r
-// unsigned short ANSB1:1;\r
-// } BIT;\r
- } ADANSB1;\r
- unsigned short ADDBLDR;\r
- unsigned short ADTSDR;\r
- unsigned short ADOCDR;\r
- char wk2[2];\r
- unsigned short ADDR0;\r
- unsigned short ADDR1;\r
- unsigned short ADDR2;\r
- unsigned short ADDR3;\r
- unsigned short ADDR4;\r
- unsigned short ADDR5;\r
- unsigned short ADDR6;\r
- unsigned short ADDR7;\r
- unsigned short ADDR8;\r
- unsigned short ADDR9;\r
- unsigned short ADDR10;\r
- unsigned short ADDR11;\r
- unsigned short ADDR12;\r
- unsigned short ADDR13;\r
- unsigned short ADDR14;\r
- unsigned short ADDR15;\r
- char wk3[10];\r
- unsigned short ADDR21;\r
- char wk4[20];\r
- unsigned char ADSSTR0;\r
- unsigned char ADSSTRL;\r
- char wk5[14];\r
- unsigned char ADSSTRT;\r
- unsigned char ADSSTRO;\r
- char wk6[1];\r
- unsigned char ADSSTR1;\r
- unsigned char ADSSTR2;\r
- unsigned char ADSSTR3;\r
- unsigned char ADSSTR4;\r
- unsigned char ADSSTR5;\r
- unsigned char ADSSTR6;\r
- unsigned char ADSSTR7;\r
- char wk7[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char OCSVSEL:1;\r
- unsigned char HVREFDIS:1;\r
- } BIT;\r
- } ADHVREFCNT;\r
- char wk8[3];\r
- unsigned char ADSSTR21;\r
-};\r
-\r
-struct st_sci0 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CM:1;\r
- unsigned char CHR:1;\r
- unsigned char PE:1;\r
- unsigned char PM:1;\r
- unsigned char STOP:1;\r
- unsigned char MP:1;\r
- unsigned char CKS:2;\r
- } BIT;\r
- } SMR;\r
- unsigned char BRR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TIE:1;\r
- unsigned char RIE:1;\r
- unsigned char TE:1;\r
- unsigned char RE:1;\r
- unsigned char MPIE:1;\r
- unsigned char TEIE:1;\r
- unsigned char CKE:2;\r
- } BIT;\r
- } SCR;\r
- unsigned char TDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char ORER:1;\r
- unsigned char FER:1;\r
- unsigned char PER:1;\r
- unsigned char TEND:1;\r
- unsigned char MPB:1;\r
- unsigned char MPBT:1;\r
- } BIT;\r
- } SSR;\r
- unsigned char RDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BCP2:1;\r
- unsigned char :3;\r
- unsigned char SDIR:1;\r
- unsigned char SINV:1;\r
- unsigned char :1;\r
- unsigned char SMIF:1;\r
- } BIT;\r
- } SCMR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char RXDESEL:1;\r
- unsigned char :1;\r
- unsigned char NFEN:1;\r
- unsigned char ABCS:1;\r
- unsigned char :3;\r
- unsigned char ACS0:1;\r
- } BIT;\r
- } SEMR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char NFCS:3;\r
- } BIT;\r
- } SNFR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IICDL:5;\r
- unsigned char :2;\r
- unsigned char IICM:1;\r
- } BIT;\r
- } SIMR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char IICACKT:1;\r
- unsigned char :3;\r
- unsigned char IICCSC:1;\r
- unsigned char IICINTM:1;\r
- } BIT;\r
- } SIMR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IICSCLS:2;\r
- unsigned char IICSDAS:2;\r
- unsigned char IICSTIF:1;\r
- unsigned char IICSTPREQ:1;\r
- unsigned char IICRSTAREQ:1;\r
- unsigned char IICSTAREQ:1;\r
- } BIT;\r
- } SIMR3;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char IICACKR:1;\r
- } BIT;\r
- } SISR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CKPH:1;\r
- unsigned char CKPOL:1;\r
- unsigned char :1;\r
- unsigned char MFF:1;\r
- unsigned char :1;\r
- unsigned char MSS:1;\r
- unsigned char CTSE:1;\r
- unsigned char SSE:1;\r
- } BIT;\r
- } SPMR;\r
-};\r
-\r
-struct st_sci12 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CM:1;\r
- unsigned char CHR:1;\r
- unsigned char PE:1;\r
- unsigned char PM:1;\r
- unsigned char STOP:1;\r
- unsigned char MP:1;\r
- unsigned char CKS:2;\r
- } BIT;\r
- } SMR;\r
- unsigned char BRR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TIE:1;\r
- unsigned char RIE:1;\r
- unsigned char TE:1;\r
- unsigned char RE:1;\r
- unsigned char MPIE:1;\r
- unsigned char TEIE:1;\r
- unsigned char CKE:2;\r
- } BIT;\r
- } SCR;\r
- unsigned char TDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char ORER:1;\r
- unsigned char FER:1;\r
- unsigned char PER:1;\r
- unsigned char TEND:1;\r
- unsigned char MPB:1;\r
- unsigned char MPBT:1;\r
- } BIT;\r
- } SSR;\r
- unsigned char RDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BCP2:1;\r
- unsigned char :3;\r
- unsigned char SDIR:1;\r
- unsigned char SINV:1;\r
- unsigned char :1;\r
- unsigned char SMIF:1;\r
- } BIT;\r
- } SCMR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char RXDESEL:1;\r
- unsigned char :1;\r
- unsigned char NFEN:1;\r
- unsigned char ABCS:1;\r
- unsigned char :3;\r
- unsigned char ACS0:1;\r
- } BIT;\r
- } SEMR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char NFCS:3;\r
- } BIT;\r
- } SNFR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IICDL:5;\r
- unsigned char :2;\r
- unsigned char IICM:1;\r
- } BIT;\r
- } SIMR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char IICACKT:1;\r
- unsigned char :3;\r
- unsigned char IICCSC:1;\r
- unsigned char IICINTM:1;\r
- } BIT;\r
- } SIMR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char IICSCLS:2;\r
- unsigned char IICSDAS:2;\r
- unsigned char IICSTIF:1;\r
- unsigned char IICSTPREQ:1;\r
- unsigned char IICRSTAREQ:1;\r
- unsigned char IICSTAREQ:1;\r
- } BIT;\r
- } SIMR3;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char IICACKR:1;\r
- } BIT;\r
- } SISR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CKPH:1;\r
- unsigned char CKPOL:1;\r
- unsigned char :1;\r
- unsigned char MFF:1;\r
- unsigned char :1;\r
- unsigned char MSS:1;\r
- unsigned char CTSE:1;\r
- unsigned char SSE:1;\r
- } BIT;\r
- } SPMR;\r
- char wk0[18];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char ESME:1;\r
- } BIT;\r
- } ESMER;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char BRME:1;\r
- unsigned char RXDSF:1;\r
- unsigned char SFSF:1;\r
- } BIT;\r
- } CR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char PIBS:3;\r
- unsigned char PIBE:1;\r
- unsigned char CF1DS:2;\r
- unsigned char CF0RE:1;\r
- unsigned char BFE:1;\r
- } BIT;\r
- } CR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char RTS:2;\r
- unsigned char BCCS:2;\r
- unsigned char :1;\r
- unsigned char DFCS:3;\r
- } BIT;\r
- } CR2;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char SDST:1;\r
- } BIT;\r
- } CR3;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char SHARPS:1;\r
- unsigned char :2;\r
- unsigned char RXDXPS:1;\r
- unsigned char TXDXPS:1;\r
- } BIT;\r
- } PCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char AEDIE:1;\r
- unsigned char BCDIE:1;\r
- unsigned char PIBDIE:1;\r
- unsigned char CF1MIE:1;\r
- unsigned char CF0MIE:1;\r
- unsigned char BFDIE:1;\r
- } BIT;\r
- } ICR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char AEDF:1;\r
- unsigned char BCDF:1;\r
- unsigned char PIBDF:1;\r
- unsigned char CF1MF:1;\r
- unsigned char CF0MF:1;\r
- unsigned char BFDF:1;\r
- } BIT;\r
- } STR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char AEDCL:1;\r
- unsigned char BCDCL:1;\r
- unsigned char PIBDCL:1;\r
- unsigned char CF1MCL:1;\r
- unsigned char CF0MCL:1;\r
- unsigned char BFDCL:1;\r
- } BIT;\r
- } STCR;\r
- unsigned char CF0DR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CF0CE7:1;\r
- unsigned char CF0CE6:1;\r
- unsigned char CF0CE5:1;\r
- unsigned char CF0CE4:1;\r
- unsigned char CF0CE3:1;\r
- unsigned char CF0CE2:1;\r
- unsigned char CF0CE1:1;\r
- unsigned char CF0CE0:1;\r
- } BIT;\r
- } CF0CR;\r
- unsigned char CF0RR;\r
- unsigned char PCF1DR;\r
- unsigned char SCF1DR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CF1CE7:1;\r
- unsigned char CF1CE6:1;\r
- unsigned char CF1CE5:1;\r
- unsigned char CF1CE4:1;\r
- unsigned char CF1CE3:1;\r
- unsigned char CF1CE2:1;\r
- unsigned char CF1CE1:1;\r
- unsigned char CF1CE0:1;\r
- } BIT;\r
- } CF1CR;\r
- unsigned char CF1RR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char TCST:1;\r
- } BIT;\r
- } TCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char TCSS:3;\r
- unsigned char TWRC:1;\r
- unsigned char :1;\r
- unsigned char TOMS:2;\r
- } BIT;\r
- } TMR;\r
- unsigned char TPRE;\r
- unsigned char TCNT;\r
-};\r
-\r
-struct st_smci {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char GM:1;\r
- unsigned char BLK:1;\r
- unsigned char PE:1;\r
- unsigned char PM:1;\r
- unsigned char BCP:2;\r
- unsigned char CKS:2;\r
- } BIT;\r
- } SMR;\r
- unsigned char BRR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TIE:1;\r
- unsigned char RIE:1;\r
- unsigned char TE:1;\r
- unsigned char RE:1;\r
- unsigned char MPIE:1;\r
- unsigned char TEIE:1;\r
- unsigned char CKE:2;\r
- } BIT;\r
- } SCR;\r
- unsigned char TDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char ORER:1;\r
- unsigned char ERS:1;\r
- unsigned char PER:1;\r
- unsigned char TEND:1;\r
- unsigned char MPB:1;\r
- unsigned char MPBT:1;\r
- } BIT;\r
- } SSR;\r
- unsigned char RDR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char BCP2:1;\r
- unsigned char :3;\r
- unsigned char SDIR:1;\r
- unsigned char SINV:1;\r
- unsigned char :1;\r
- unsigned char SMIF:1;\r
- } BIT;\r
- } SCMR;\r
-};\r
-\r
-struct st_ssi {\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned long :1;\r
- unsigned long CKS:1;\r
- unsigned long TUIEN:1;\r
- unsigned long TOIEN:1;\r
- unsigned long RUIEN:1;\r
- unsigned long ROIEN:1;\r
- unsigned long IIEN:1;\r
- unsigned long :1;\r
- unsigned long CHNL:2;\r
- unsigned long DWL:3;\r
- unsigned long SWL:3;\r
- unsigned long SCKD:1;\r
- unsigned long SWSD:1;\r
- unsigned long SCKP:1;\r
- unsigned long SWSP:1;\r
- unsigned long SPDP:1;\r
- unsigned long SDTA:1;\r
- unsigned long PDTA:1;\r
- unsigned long DEL:1;\r
- unsigned long CKDV:4;\r
- unsigned long MUEN:1;\r
- unsigned long :1;\r
- unsigned long TEN:1;\r
- unsigned long REN:1;\r
- } BIT;\r
- } SSICR;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned long :2;\r
- unsigned long TUIRQ:1;\r
- unsigned long TOIRQ:1;\r
- unsigned long RUIRQ:1;\r
- unsigned long ROIRQ:1;\r
- unsigned long IIRQ:1;\r
- unsigned long :18;\r
- unsigned long TCHNO:2;\r
- unsigned long TSWNO:1;\r
- unsigned long RCHNO:2;\r
- unsigned long RSWNO:1;\r
- unsigned long IDST:1;\r
- } BIT;\r
- } SSISR;\r
- char wk0[8];\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned long AUCKE:1;\r
- unsigned long :14;\r
- unsigned long SSIRST:1;\r
- unsigned long :8;\r
- unsigned long TTRG:2;\r
- unsigned long RTRG:2;\r
- unsigned long TIE:1;\r
- unsigned long RIE:1;\r
- unsigned long TFRST:1;\r
- unsigned long RFRST:1;\r
- } BIT;\r
- } SSIFCR;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned long :4;\r
- unsigned long TDC:4;\r
- unsigned long :7;\r
- unsigned long TDE:1;\r
- unsigned long :4;\r
- unsigned long RDC:4;\r
- unsigned long :7;\r
- unsigned long RDF:1;\r
- } BIT;\r
- } SSIFSR;\r
- unsigned long SSIFTDR;\r
- unsigned long SSIFRDR;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned long :23;\r
- unsigned long CONT:1;\r
- } BIT;\r
- } SSITDMR;\r
-};\r
-\r
-struct st_system {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :15;\r
- unsigned short MD:1;\r
- } BIT;\r
- } MDMONR;\r
- char wk0[6];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :15;\r
- unsigned short RAME:1;\r
- } BIT;\r
- } SYSCR1;\r
- char wk1[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short SSBY:1;\r
- } BIT;\r
- } SBYCR;\r
- char wk2[2];\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned long :3;\r
- unsigned long MSTPA28:1;\r
- unsigned long :9;\r
- unsigned long MSTPA18:1;\r
- unsigned long MSTPA17:1;\r
- unsigned long :1;\r
- unsigned long MSTPA15:1;\r
- unsigned long MSTPA14:1;\r
- unsigned long :4;\r
- unsigned long MSTPA9:1;\r
- unsigned long :3;\r
- unsigned long MSTPA5:1;\r
- unsigned long MSTPA4:1;\r
- } BIT;\r
- } MSTPCRA;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned long MSTPB31:1;\r
- unsigned long MSTPB30:1;\r
- unsigned long MSTPB29:1;\r
- unsigned long :2;\r
- unsigned long MSTPB26:1;\r
- unsigned long MSTPB25:1;\r
- unsigned long :1;\r
- unsigned long MSTPB23:1;\r
- unsigned long :1;\r
- unsigned long MSTPB21:1;\r
- unsigned long :1;\r
- unsigned long MSTPB19:1;\r
- unsigned long :1;\r
- unsigned long MSTPB17:1;\r
- unsigned long :6;\r
- unsigned long MSTPB10:1;\r
- unsigned long MSTPB9:1;\r
- unsigned long :2;\r
- unsigned long MSTPB6:1;\r
- unsigned long :1;\r
- unsigned long MSTPB4:1;\r
- } BIT;\r
- } MSTPCRB;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned long DSLPE:1;\r
- unsigned long :3;\r
- unsigned long MSTPC27:1;\r
- unsigned long MSTPC26:1;\r
- unsigned long :5;\r
- unsigned long MSTPC20:1;\r
- unsigned long MSTPC19:1;\r
- unsigned long :18;\r
- unsigned long MSTPC0:1;\r
- } BIT;\r
- } MSTPCRC;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned long :16;\r
- unsigned long MSTPD15:1;\r
- unsigned long :3;\r
- unsigned long MSTPD11:1;\r
- unsigned long MSTPD10:1;\r
- } BIT;\r
- } MSTPCRD;\r
- union {\r
- unsigned long LONG;\r
- struct {\r
- unsigned long FCK:4;\r
- unsigned long ICK:4;\r
- unsigned long :12;\r
- unsigned long PCKB:4;\r
- unsigned long :4;\r
- unsigned long PCKD:4;\r
- } BIT;\r
- } SCKCR;\r
- char wk3[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :5;\r
- unsigned short CKSEL:3;\r
- } BIT;\r
- } SCKCR3;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :2;\r
- unsigned short STC:6;\r
- unsigned short :6;\r
- unsigned short PLIDIV:2;\r
- } BIT;\r
- } PLLCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char PLLEN:1;\r
- } BIT;\r
- } PLLCR2;\r
- char wk4[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :2;\r
- unsigned short USTC:6;\r
- unsigned short :3;\r
- unsigned short UCKUPLLSEL:1;\r
- unsigned short :2;\r
- unsigned short UPLIDIV:2;\r
- } BIT;\r
- } UPLLCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char UPLLEN:1;\r
- } BIT;\r
- } UPLLCR2;\r
- char wk5[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char MOSTP:1;\r
- } BIT;\r
- } MOSCCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char SOSTP:1;\r
- } BIT;\r
- } SOSCCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char LCSTP:1;\r
- } BIT;\r
- } LOCOCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char ILCSTP:1;\r
- } BIT;\r
- } ILOCOCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char HCSTP:1;\r
- } BIT;\r
- } HOCOCR;\r
- char wk6[5];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char UPLOVF:1;\r
- unsigned char :1;\r
- unsigned char HCOVF:1;\r
- unsigned char PLOVF:1;\r
- unsigned char :1;\r
- unsigned char MOOVF:1;\r
- } BIT;\r
- } OSCOVFSR;\r
- char wk7[1];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short CKOSTP:1;\r
- unsigned short CKODIV:3;\r
- unsigned short :1;\r
- unsigned short CKOSEL:3;\r
- } BIT;\r
- } CKOCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char OSTDE:1;\r
- unsigned char :6;\r
- unsigned char OSTDIE:1;\r
- } BIT;\r
- } OSTDCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char OSTDF:1;\r
- } BIT;\r
- } OSTDSR;\r
- char wk8[14];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char LCDSCLKSEL:3;\r
- } BIT;\r
- } LCDSCLKCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char LCDSCLKSTP:1;\r
- } BIT;\r
- } LCDSCLKCR2;\r
- char wk9[78];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char OPCMTSF:1;\r
- unsigned char :1;\r
- unsigned char OPCM:3;\r
- } BIT;\r
- } OPCCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char RSTCKEN:1;\r
- unsigned char :4;\r
- unsigned char RSTCKSEL:3;\r
- } BIT;\r
- } RSTCKCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char MSTS:5;\r
- } BIT;\r
- } MOSCWTCR;\r
- char wk10[2];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char HSTS:5;\r
- } BIT;\r
- } HOCOWTCR;\r
- char wk11[4];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :3;\r
- unsigned char SOPCMTSF:1;\r
- unsigned char :3;\r
- unsigned char SOPCM:1;\r
- } BIT;\r
- } SOPCCR;\r
- char wk12[21];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char SWRF:1;\r
- unsigned char :1;\r
- unsigned char IWDTRF:1;\r
- } BIT;\r
- } RSTSR2;\r
- char wk13[1];\r
- unsigned short SWRR;\r
- char wk14[28];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char LVD1IRQSEL:1;\r
- unsigned char LVD1IDTSEL:2;\r
- } BIT;\r
- } LVD1CR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char LVD1MON:1;\r
- unsigned char LVD1DET:1;\r
- } BIT;\r
- } LVD1SR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :5;\r
- unsigned char LVD2IRQSEL:1;\r
- unsigned char LVD2IDTSEL:2;\r
- } BIT;\r
- } LVD2CR1;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :6;\r
- unsigned char LVD2MON:1;\r
- unsigned char LVD2DET:1;\r
- } BIT;\r
- } LVD2SR;\r
- char wk15[794];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short PRKEY:8;\r
- unsigned short :4;\r
- unsigned short PRC3:1;\r
- unsigned short PRC2:1;\r
- unsigned short PRC1:1;\r
- unsigned short PRC0:1;\r
- } BIT;\r
- } PRCR;\r
- char wk16[48784];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char LVD2RF:1;\r
- unsigned char LVD1RF:1;\r
- unsigned char :1;\r
- unsigned char PORF:1;\r
- } BIT;\r
- } RSTSR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char CWSF:1;\r
- } BIT;\r
- } RSTSR1;\r
- char wk17[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char MOSEL:1;\r
- unsigned char MODRV21:1;\r
- } BIT;\r
- } MOFCR;\r
- char wk18[3];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :1;\r
- unsigned char LVD2E:1;\r
- unsigned char LVD1E:1;\r
- unsigned char :1;\r
- unsigned char EXVCCINP2:1;\r
- } BIT;\r
- } LVCMPCR;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :2;\r
- unsigned char LVD2LVL:2;\r
- unsigned char LVD1LVL:4;\r
- } BIT;\r
- } LVDLVLR;\r
- char wk19[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char LVD1RN:1;\r
- unsigned char LVD1RI:1;\r
- unsigned char :3;\r
- unsigned char LVD1CMPE:1;\r
- unsigned char :1;\r
- unsigned char LVD1RIE:1;\r
- } BIT;\r
- } LVD1CR0;\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char LVD2RN:1;\r
- unsigned char LVD2RI:1;\r
- unsigned char :3;\r
- unsigned char LVD2CMPE:1;\r
- unsigned char :1;\r
- unsigned char LVD2RIE:1;\r
- } BIT;\r
- } LVD2CR0;\r
-};\r
-\r
-struct st_temps {\r
- unsigned char TSCDRL;\r
- unsigned char TSCDRH;\r
-};\r
-\r
-struct st_tmr0 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CMIEB:1;\r
- unsigned char CMIEA:1;\r
- unsigned char OVIE:1;\r
- unsigned char CCLR:2;\r
- } BIT;\r
- } TCR;\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char OSB:2;\r
- unsigned char OSA:2;\r
- } BIT;\r
- } TCSR;\r
- char wk1[1];\r
- unsigned char TCORA;\r
- char wk2[1];\r
- unsigned char TCORB;\r
- char wk3[1];\r
- unsigned char TCNT;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TMRIS:1;\r
- unsigned char :2;\r
- unsigned char CSS:2;\r
- unsigned char CKS:3;\r
- } BIT;\r
- } TCCR;\r
- char wk5[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :7;\r
- unsigned char TCS:1;\r
- } BIT;\r
- } TCSTR;\r
-};\r
-\r
-struct st_tmr1 {\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char CMIEB:1;\r
- unsigned char CMIEA:1;\r
- unsigned char OVIE:1;\r
- unsigned char CCLR:2;\r
- } BIT;\r
- } TCR;\r
- char wk0[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char :4;\r
- unsigned char OSB:2;\r
- unsigned char OSA:2;\r
- } BIT;\r
- } TCSR;\r
- char wk1[1];\r
- unsigned char TCORA;\r
- char wk2[1];\r
- unsigned char TCORB;\r
- char wk3[1];\r
- unsigned char TCNT;\r
- char wk4[1];\r
- union {\r
- unsigned char BYTE;\r
- struct {\r
- unsigned char TMRIS:1;\r
- unsigned char :2;\r
- unsigned char CSS:2;\r
- unsigned char CKS:3;\r
- } BIT;\r
- } TCCR;\r
-};\r
-\r
-struct st_tmr01 {\r
- unsigned short TCORA;\r
- unsigned short TCORB;\r
- unsigned short TCNT;\r
- unsigned short TCCR;\r
-};\r
-\r
-struct st_usb0 {\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :5;\r
- unsigned short SCKE:1;\r
- unsigned short :1;\r
- unsigned short CNEN:1;\r
- unsigned short :1;\r
- unsigned short DCFM:1;\r
- unsigned short DRPD:1;\r
- unsigned short DPRPU:1;\r
- unsigned short DMRPU:1;\r
- unsigned short :2;\r
- unsigned short USBE:1;\r
- } BIT;\r
- } SYSCFG;\r
- char wk0[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short OVCMON:2;\r
- unsigned short :7;\r
- unsigned short HTACT:1;\r
- unsigned short :3;\r
- unsigned short IDMON:1;\r
- unsigned short LNST:2;\r
- } BIT;\r
- } SYSSTS0;\r
- char wk1[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :4;\r
- unsigned short HNPBTOA:1;\r
- unsigned short EXICEN:1;\r
- unsigned short VBUSEN:1;\r
- unsigned short WKUP:1;\r
- unsigned short RWUPE:1;\r
- unsigned short USBRST:1;\r
- unsigned short RESUME:1;\r
- unsigned short UACT:1;\r
- unsigned short :1;\r
- unsigned short RHST:3;\r
- } BIT;\r
- } DVSTCTR0;\r
- char wk2[10];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char L;\r
- unsigned char H;\r
- } BYTE;\r
- } CFIFO;\r
- char wk3[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char L;\r
- unsigned char H;\r
- } BYTE;\r
- } D0FIFO;\r
- char wk4[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned char L;\r
- unsigned char H;\r
- } BYTE;\r
- } D1FIFO;\r
- char wk5[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short RCNT:1;\r
- unsigned short REW:1;\r
- unsigned short :3;\r
- unsigned short MBW:1;\r
- unsigned short :1;\r
- unsigned short BIGEND:1;\r
- unsigned short :2;\r
- unsigned short ISEL:1;\r
- unsigned short :1;\r
- unsigned short CURPIPE:4;\r
- } BIT;\r
- } CFIFOSEL;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BVAL:1;\r
- unsigned short BCLR:1;\r
- unsigned short FRDY:1;\r
- unsigned short :4;\r
- unsigned short DTLN:9;\r
- } BIT;\r
- } CFIFOCTR;\r
- char wk6[4];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short RCNT:1;\r
- unsigned short REW:1;\r
- unsigned short DCLRM:1;\r
- unsigned short DREQE:1;\r
- unsigned short :1;\r
- unsigned short MBW:1;\r
- unsigned short :1;\r
- unsigned short BIGEND:1;\r
- unsigned short :4;\r
- unsigned short CURPIPE:4;\r
- } BIT;\r
- } D0FIFOSEL;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BVAL:1;\r
- unsigned short BCLR:1;\r
- unsigned short FRDY:1;\r
- unsigned short :4;\r
- unsigned short DTLN:9;\r
- } BIT;\r
- } D0FIFOCTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short RCNT:1;\r
- unsigned short REW:1;\r
- unsigned short DCLRM:1;\r
- unsigned short DREQE:1;\r
- unsigned short :1;\r
- unsigned short MBW:1;\r
- unsigned short :1;\r
- unsigned short BIGEND:1;\r
- unsigned short :4;\r
- unsigned short CURPIPE:4;\r
- } BIT;\r
- } D1FIFOSEL;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BVAL:1;\r
- unsigned short BCLR:1;\r
- unsigned short FRDY:1;\r
- unsigned short :4;\r
- unsigned short DTLN:9;\r
- } BIT;\r
- } D1FIFOCTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short VBSE:1;\r
- unsigned short RSME:1;\r
- unsigned short SOFE:1;\r
- unsigned short DVSE:1;\r
- unsigned short CTRE:1;\r
- unsigned short BEMPE:1;\r
- unsigned short NRDYE:1;\r
- unsigned short BRDYE:1;\r
- } BIT;\r
- } INTENB0;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short OVRCRE:1;\r
- unsigned short BCHGE:1;\r
- unsigned short :1;\r
- unsigned short DTCHE:1;\r
- unsigned short ATTCHE:1;\r
- unsigned short :4;\r
- unsigned short EOFERRE:1;\r
- unsigned short SIGNE:1;\r
- unsigned short SACKE:1;\r
- unsigned short :3;\r
- unsigned short PDDETINTE0:1;\r
- } BIT;\r
- } INTENB1;\r
- char wk7[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short PIPE9BRDYE:1;\r
- unsigned short PIPE8BRDYE:1;\r
- unsigned short PIPE7BRDYE:1;\r
- unsigned short PIPE6BRDYE:1;\r
- unsigned short PIPE5BRDYE:1;\r
- unsigned short PIPE4BRDYE:1;\r
- unsigned short PIPE3BRDYE:1;\r
- unsigned short PIPE2BRDYE:1;\r
- unsigned short PIPE1BRDYE:1;\r
- unsigned short PIPE0BRDYE:1;\r
- } BIT;\r
- } BRDYENB;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short PIPE9NRDYE:1;\r
- unsigned short PIPE8NRDYE:1;\r
- unsigned short PIPE7NRDYE:1;\r
- unsigned short PIPE6NRDYE:1;\r
- unsigned short PIPE5NRDYE:1;\r
- unsigned short PIPE4NRDYE:1;\r
- unsigned short PIPE3NRDYE:1;\r
- unsigned short PIPE2NRDYE:1;\r
- unsigned short PIPE1NRDYE:1;\r
- unsigned short PIPE0NRDYE:1;\r
- } BIT;\r
- } NRDYENB;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short PIPE9BEMPE:1;\r
- unsigned short PIPE8BEMPE:1;\r
- unsigned short PIPE7BEMPE:1;\r
- unsigned short PIPE6BEMPE:1;\r
- unsigned short PIPE5BEMPE:1;\r
- unsigned short PIPE4BEMPE:1;\r
- unsigned short PIPE3BEMPE:1;\r
- unsigned short PIPE2BEMPE:1;\r
- unsigned short PIPE1BEMPE:1;\r
- unsigned short PIPE0BEMPE:1;\r
- } BIT;\r
- } BEMPENB;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :7;\r
- unsigned short TRNENSEL:1;\r
- unsigned short :1;\r
- unsigned short BRDYM:1;\r
- unsigned short :1;\r
- unsigned short EDGESTS:1;\r
- } BIT;\r
- } SOFCFG;\r
- char wk8[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short VBINT:1;\r
- unsigned short RESM:1;\r
- unsigned short SOFR:1;\r
- unsigned short DVST:1;\r
- unsigned short CTRT:1;\r
- unsigned short BEMP:1;\r
- unsigned short NRDY:1;\r
- unsigned short BRDY:1;\r
- unsigned short VBSTS:1;\r
- unsigned short DVSQ:3;\r
- unsigned short VALID:1;\r
- unsigned short CTSQ:3;\r
- } BIT;\r
- } INTSTS0;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short OVRCR:1;\r
- unsigned short BCHG:1;\r
- unsigned short :1;\r
- unsigned short DTCH:1;\r
- unsigned short ATTCH:1;\r
- unsigned short :4;\r
- unsigned short EOFERR:1;\r
- unsigned short SIGN:1;\r
- unsigned short SACK:1;\r
- unsigned short :3;\r
- unsigned short PDDETINT0:1;\r
- } BIT;\r
- } INTSTS1;\r
- char wk9[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short PIPE9BRDY:1;\r
- unsigned short PIPE8BRDY:1;\r
- unsigned short PIPE7BRDY:1;\r
- unsigned short PIPE6BRDY:1;\r
- unsigned short PIPE5BRDY:1;\r
- unsigned short PIPE4BRDY:1;\r
- unsigned short PIPE3BRDY:1;\r
- unsigned short PIPE2BRDY:1;\r
- unsigned short PIPE1BRDY:1;\r
- unsigned short PIPE0BRDY:1;\r
- } BIT;\r
- } BRDYSTS;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short PIPE9NRDY:1;\r
- unsigned short PIPE8NRDY:1;\r
- unsigned short PIPE7NRDY:1;\r
- unsigned short PIPE6NRDY:1;\r
- unsigned short PIPE5NRDY:1;\r
- unsigned short PIPE4NRDY:1;\r
- unsigned short PIPE3NRDY:1;\r
- unsigned short PIPE2NRDY:1;\r
- unsigned short PIPE1NRDY:1;\r
- unsigned short PIPE0NRDY:1;\r
- } BIT;\r
- } NRDYSTS;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short PIPE9BEMP:1;\r
- unsigned short PIPE8BEMP:1;\r
- unsigned short PIPE7BEMP:1;\r
- unsigned short PIPE6BEMP:1;\r
- unsigned short PIPE5BEMP:1;\r
- unsigned short PIPE4BEMP:1;\r
- unsigned short PIPE3BEMP:1;\r
- unsigned short PIPE2BEMP:1;\r
- unsigned short PIPE1BEMP:1;\r
- unsigned short PIPE0BEMP:1;\r
- } BIT;\r
- } BEMPSTS;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short OVRN:1;\r
- unsigned short CRCE:1;\r
- unsigned short :3;\r
- unsigned short FRNM:11;\r
- } BIT;\r
- } FRMNUM;\r
- char wk10[6];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BREQUEST:8;\r
- unsigned short BMREQUESTTYPE:8;\r
- } BIT;\r
- } USBREQ;\r
- unsigned short USBVAL;\r
- unsigned short USBINDX;\r
- unsigned short USBLENG;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :8;\r
- unsigned short SHTNAK:1;\r
- unsigned short :2;\r
- unsigned short DIR:1;\r
- } BIT;\r
- } DCPCFG;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short DEVSEL:4;\r
- unsigned short :5;\r
- unsigned short MXPS:7;\r
- } BIT;\r
- } DCPMAXP;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BSTS:1;\r
- unsigned short SUREQ:1;\r
- unsigned short :2;\r
- unsigned short SUREQCLR:1;\r
- unsigned short :2;\r
- unsigned short SQCLR:1;\r
- unsigned short SQSET:1;\r
- unsigned short SQMON:1;\r
- unsigned short PBUSY:1;\r
- unsigned short :2;\r
- unsigned short CCPL:1;\r
- unsigned short PID:2;\r
- } BIT;\r
- } DCPCTR;\r
- char wk11[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :12;\r
- unsigned short PIPESEL:4;\r
- } BIT;\r
- } PIPESEL;\r
- char wk12[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short TYPE:2;\r
- unsigned short :3;\r
- unsigned short BFRE:1;\r
- unsigned short DBLB:1;\r
- unsigned short :1;\r
- unsigned short SHTNAK:1;\r
- unsigned short :2;\r
- unsigned short DIR:1;\r
- unsigned short EPNUM:4;\r
- } BIT;\r
- } PIPECFG;\r
- char wk13[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short DEVSEL:4;\r
- unsigned short :3;\r
- unsigned short MXPS:9;\r
- } BIT;\r
- } PIPEMAXP;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :3;\r
- unsigned short IFIS:1;\r
- unsigned short :9;\r
- unsigned short IITV:3;\r
- } BIT;\r
- } PIPEPERI;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BSTS:1;\r
- unsigned short INBUFM:1;\r
- unsigned short :3;\r
- unsigned short ATREPM:1;\r
- unsigned short ACLRM:1;\r
- unsigned short SQCLR:1;\r
- unsigned short SQSET:1;\r
- unsigned short SQMON:1;\r
- unsigned short PBUSY:1;\r
- unsigned short :3;\r
- unsigned short PID:2;\r
- } BIT;\r
- } PIPE1CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BSTS:1;\r
- unsigned short INBUFM:1;\r
- unsigned short :3;\r
- unsigned short ATREPM:1;\r
- unsigned short ACLRM:1;\r
- unsigned short SQCLR:1;\r
- unsigned short SQSET:1;\r
- unsigned short SQMON:1;\r
- unsigned short PBUSY:1;\r
- unsigned short :3;\r
- unsigned short PID:2;\r
- } BIT;\r
- } PIPE2CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BSTS:1;\r
- unsigned short INBUFM:1;\r
- unsigned short :3;\r
- unsigned short ATREPM:1;\r
- unsigned short ACLRM:1;\r
- unsigned short SQCLR:1;\r
- unsigned short SQSET:1;\r
- unsigned short SQMON:1;\r
- unsigned short PBUSY:1;\r
- unsigned short :3;\r
- unsigned short PID:2;\r
- } BIT;\r
- } PIPE3CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BSTS:1;\r
- unsigned short INBUFM:1;\r
- unsigned short :3;\r
- unsigned short ATREPM:1;\r
- unsigned short ACLRM:1;\r
- unsigned short SQCLR:1;\r
- unsigned short SQSET:1;\r
- unsigned short SQMON:1;\r
- unsigned short PBUSY:1;\r
- unsigned short :3;\r
- unsigned short PID:2;\r
- } BIT;\r
- } PIPE4CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BSTS:1;\r
- unsigned short INBUFM:1;\r
- unsigned short :3;\r
- unsigned short ATREPM:1;\r
- unsigned short ACLRM:1;\r
- unsigned short SQCLR:1;\r
- unsigned short SQSET:1;\r
- unsigned short SQMON:1;\r
- unsigned short PBUSY:1;\r
- unsigned short :3;\r
- unsigned short PID:2;\r
- } BIT;\r
- } PIPE5CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BSTS:1;\r
- unsigned short :5;\r
- unsigned short ACLRM:1;\r
- unsigned short SQCLR:1;\r
- unsigned short SQSET:1;\r
- unsigned short SQMON:1;\r
- unsigned short PBUSY:1;\r
- unsigned short :3;\r
- unsigned short PID:2;\r
- } BIT;\r
- } PIPE6CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BSTS:1;\r
- unsigned short :5;\r
- unsigned short ACLRM:1;\r
- unsigned short SQCLR:1;\r
- unsigned short SQSET:1;\r
- unsigned short SQMON:1;\r
- unsigned short PBUSY:1;\r
- unsigned short :3;\r
- unsigned short PID:2;\r
- } BIT;\r
- } PIPE7CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BSTS:1;\r
- unsigned short :5;\r
- unsigned short ACLRM:1;\r
- unsigned short SQCLR:1;\r
- unsigned short SQSET:1;\r
- unsigned short SQMON:1;\r
- unsigned short PBUSY:1;\r
- unsigned short :3;\r
- unsigned short PID:2;\r
- } BIT;\r
- } PIPE8CTR;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short BSTS:1;\r
- unsigned short :5;\r
- unsigned short ACLRM:1;\r
- unsigned short SQCLR:1;\r
- unsigned short SQSET:1;\r
- unsigned short SQMON:1;\r
- unsigned short PBUSY:1;\r
- unsigned short :3;\r
- unsigned short PID:2;\r
- } BIT;\r
- } PIPE9CTR;\r
- char wk14[14];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short TRENB:1;\r
- unsigned short TRCLR:1;\r
- } BIT;\r
- } PIPE1TRE;\r
- unsigned short PIPE1TRN;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short TRENB:1;\r
- unsigned short TRCLR:1;\r
- } BIT;\r
- } PIPE2TRE;\r
- unsigned short PIPE2TRN;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short TRENB:1;\r
- unsigned short TRCLR:1;\r
- } BIT;\r
- } PIPE3TRE;\r
- unsigned short PIPE3TRN;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short TRENB:1;\r
- unsigned short TRCLR:1;\r
- } BIT;\r
- } PIPE4TRE;\r
- unsigned short PIPE4TRN;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short TRENB:1;\r
- unsigned short TRCLR:1;\r
- } BIT;\r
- } PIPE5TRE;\r
- unsigned short PIPE5TRN;\r
- char wk15[12];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :6;\r
- unsigned short PDDETSTS0:1;\r
- unsigned short CHGDETSTS0:1;\r
- unsigned short BATCHGE0:1;\r
- unsigned short :1;\r
- unsigned short VDMSRCE0:1;\r
- unsigned short IDPSINKE0:1;\r
- unsigned short VDPSRCE0:1;\r
- unsigned short IDMSINKE0:1;\r
- unsigned short IDPSRCE0:1;\r
- unsigned short RPDME0:1;\r
- } BIT;\r
- } USBBCCTRL0;\r
- char wk16[26];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :15;\r
- unsigned short VDDUSBE:1;\r
- } BIT;\r
- } USBMC;\r
- char wk17[2];\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :8;\r
- unsigned short USBSPD:2;\r
- } BIT;\r
- } DEVADD0;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :8;\r
- unsigned short USBSPD:2;\r
- } BIT;\r
- } DEVADD1;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :8;\r
- unsigned short USBSPD:2;\r
- } BIT;\r
- } DEVADD2;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :8;\r
- unsigned short USBSPD:2;\r
- } BIT;\r
- } DEVADD3;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :8;\r
- unsigned short USBSPD:2;\r
- } BIT;\r
- } DEVADD4;\r
- union {\r
- unsigned short WORD;\r
- struct {\r
- unsigned short :8;\r
- unsigned short USBSPD:2;\r
- } BIT;\r
- } DEVADD5;\r
-};\r
-\r
-enum enum_ir {\r
-IR_BSC_BUSERR=16,IR_ICU_SWINT=27,\r
-IR_CMT0_CMI0,\r
-IR_CMT1_CMI1,\r
-IR_CMT2_CMI2,\r
-IR_CMT3_CMI3,\r
-IR_CAC_FERRF,IR_CAC_MENDF,IR_CAC_OVFF,\r
-IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0,\r
-IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0,\r
-IR_DOC_DOPCF=57,\r
-IR_CMPB_CMPB0,IR_CMPB_CMPB1,\r
-IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN,\r
-IR_RTC_CUP,\r
-IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,\r
-IR_LVD_LVD1=88,IR_LVD_LVD2,\r
-IR_USB0_USBR0,\r
-IR_RTC_ALM=92,IR_RTC_PRD,\r
-IR_S12AD_S12ADI0=102,IR_S12AD_GBADI,\r
-IR_ELC_ELSR18I=106,\r
-IR_SSI0_SSIF0=108,IR_SSI0_SSIRXI0,IR_SSI0_SSITXI0,\r
-IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0,\r
-IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1,\r
-IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2,\r
-IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3,\r
-IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4,\r
-IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5,\r
-IR_POE_OEI1=170,IR_POE_OEI2,\r
-IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0,\r
-IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1,\r
-IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2,\r
-IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3,\r
-IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2,\r
-IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0,\r
-IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1,\r
-IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5,\r
-IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6,\r
-IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8,\r
-IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9,\r
-IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3,\r
-IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0\r
-};\r
-\r
-enum enum_dtce {\r
-DTCE_ICU_SWINT=27,\r
-DTCE_CMT0_CMI0,\r
-DTCE_CMT1_CMI1,\r
-DTCE_CMT2_CMI2,\r
-DTCE_CMT3_CMI3,\r
-DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0,\r
-DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0,\r
-DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1,\r
-DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD,\r
-DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,\r
-DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI,\r
-DTCE_ELC_ELSR18I=106,\r
-DTCE_SSI0_SSIRXI0=109,DTCE_SSI0_SSITXI0,\r
-DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0,\r
-DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1,\r
-DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2,\r
-DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3,\r
-DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4,\r
-DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5,\r
-DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0,\r
-DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1,\r
-DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2,\r
-DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3,\r
-DTCE_SCI2_RXI2=187,DTCE_SCI2_TXI2,\r
-DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0,\r
-DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1,\r
-DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5,\r
-DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6,\r
-DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8,\r
-DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9,\r
-DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12,\r
-DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0\r
-};\r
-\r
-enum enum_ier {\r
-IER_BSC_BUSERR=0x02,\r
-IER_ICU_SWINT=0x03,\r
-IER_CMT0_CMI0=0x03,\r
-IER_CMT1_CMI1=0x03,\r
-IER_CMT2_CMI2=0x03,\r
-IER_CMT3_CMI3=0x03,\r
-IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04,\r
-IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04,\r
-IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05,\r
-IER_DOC_DOPCF=0x07,\r
-IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07,\r
-IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07,\r
-IER_RTC_CUP=0x07,\r
-IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,\r
-IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B,\r
-IER_USB0_USBR0=0x0B,\r
-IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B,\r
-IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C,\r
-IER_ELC_ELSR18I=0x0D,\r
-IER_SSI0_SSIF0=0x0D,IER_SSI0_SSIRXI0=0x0D,IER_SSI0_SSITXI0=0x0D,\r
-IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F,\r
-IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F,\r
-IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10,\r
-IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10,\r
-IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11,\r
-IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11,\r
-IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,\r
-IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16,\r
-IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16,\r
-IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16,\r
-IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17,\r
-IER_SCI2_ERI2=0x17,IER_SCI2_RXI2=0x17,IER_SCI2_TXI2=0x17,IER_SCI2_TEI2=0x17,\r
-IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B,\r
-IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B,\r
-IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C,\r
-IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C,\r
-IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D,\r
-IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D,\r
-IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E,\r
-IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F\r
-};\r
-\r
-enum enum_ipr {\r
-IPR_BSC_BUSERR=0,\r
-IPR_ICU_SWINT=3,\r
-IPR_CMT0_CMI0=4,\r
-IPR_CMT1_CMI1=5,\r
-IPR_CMT2_CMI2=6,\r
-IPR_CMT3_CMI3=7,\r
-IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34,\r
-IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38,\r
-IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44,\r
-IPR_DOC_DOPCF=57,\r
-IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59,\r
-IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60,\r
-IPR_RTC_CUP=63,\r
-IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71,\r
-IPR_LVD_LVD1=88,IPR_LVD_LVD2=89,\r
-IPR_USB0_USBR0=90,\r
-IPR_RTC_ALM=92,IPR_RTC_PRD=93,\r
-IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103,\r
-IPR_ELC_ELSR18I=106,\r
-IPR_SSI0_SSIF0=108,IPR_SSI0_SSIRXI0=108,IPR_SSI0_SSITXI0=108,\r
-IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118,\r
-IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123,\r
-IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127,\r
-IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133,\r
-IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138,\r
-IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139,\r
-IPR_POE_OEI1=170,IPR_POE_OEI2=171,\r
-IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174,\r
-IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177,\r
-IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180,\r
-IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183,\r
-IPR_SCI2_ERI2=186,IPR_SCI2_RXI2=186,IPR_SCI2_TXI2=186,IPR_SCI2_TEI2=186,\r
-IPR_SCI0_ERI0=214,IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214,\r
-IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218,\r
-IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222,\r
-IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226,\r
-IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230,\r
-IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234,\r
-IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245,\r
-IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249\r
-};\r
-\r
-#define IEN_BSC_BUSERR IEN0\r
-#define IEN_ICU_SWINT IEN3\r
-#define IEN_CMT0_CMI0 IEN4\r
-#define IEN_CMT1_CMI1 IEN5\r
-#define IEN_CMT2_CMI2 IEN6\r
-#define IEN_CMT3_CMI3 IEN7\r
-#define IEN_CAC_FERRF IEN0\r
-#define IEN_CAC_MENDF IEN1\r
-#define IEN_CAC_OVFF IEN2\r
-#define IEN_USB0_D0FIFO0 IEN4\r
-#define IEN_USB0_D1FIFO0 IEN5\r
-#define IEN_USB0_USBI0 IEN6\r
-#define IEN_RSPI0_SPEI0 IEN4\r
-#define IEN_RSPI0_SPRI0 IEN5\r
-#define IEN_RSPI0_SPTI0 IEN6\r
-#define IEN_RSPI0_SPII0 IEN7\r
-#define IEN_DOC_DOPCF IEN1\r
-#define IEN_CMPB_CMPB0 IEN2\r
-#define IEN_CMPB_CMPB1 IEN3\r
-#define IEN_CTSU_CTSUWR IEN4\r
-#define IEN_CTSU_CTSURD IEN5\r
-#define IEN_CTSU_CTSUFN IEN6\r
-#define IEN_RTC_CUP IEN7\r
-#define IEN_ICU_IRQ0 IEN0\r
-#define IEN_ICU_IRQ1 IEN1\r
-#define IEN_ICU_IRQ2 IEN2\r
-#define IEN_ICU_IRQ3 IEN3\r
-#define IEN_ICU_IRQ4 IEN4\r
-#define IEN_ICU_IRQ5 IEN5\r
-#define IEN_ICU_IRQ6 IEN6\r
-#define IEN_ICU_IRQ7 IEN7\r
-#define IEN_LVD_LVD1 IEN0\r
-#define IEN_LVD_LVD2 IEN1\r
-#define IEN_USB0_USBR0 IEN2\r
-#define IEN_RTC_ALM IEN4\r
-#define IEN_RTC_PRD IEN5\r
-#define IEN_S12AD_S12ADI0 IEN6\r
-#define IEN_S12AD_GBADI IEN7\r
-#define IEN_ELC_ELSR18I IEN2\r
-#define IEN_SSI0_SSIF0 IEN4\r
-#define IEN_SSI0_SSIRXI0 IEN5\r
-#define IEN_SSI0_SSITXI0 IEN6\r
-#define IEN_MTU0_TGIA0 IEN2\r
-#define IEN_MTU0_TGIB0 IEN3\r
-#define IEN_MTU0_TGIC0 IEN4\r
-#define IEN_MTU0_TGID0 IEN5\r
-#define IEN_MTU0_TCIV0 IEN6\r
-#define IEN_MTU0_TGIE0 IEN7\r
-#define IEN_MTU0_TGIF0 IEN0\r
-#define IEN_MTU1_TGIA1 IEN1\r
-#define IEN_MTU1_TGIB1 IEN2\r
-#define IEN_MTU1_TCIV1 IEN3\r
-#define IEN_MTU1_TCIU1 IEN4\r
-#define IEN_MTU2_TGIA2 IEN5\r
-#define IEN_MTU2_TGIB2 IEN6\r
-#define IEN_MTU2_TCIV2 IEN7\r
-#define IEN_MTU2_TCIU2 IEN0\r
-#define IEN_MTU3_TGIA3 IEN1\r
-#define IEN_MTU3_TGIB3 IEN2\r
-#define IEN_MTU3_TGIC3 IEN3\r
-#define IEN_MTU3_TGID3 IEN4\r
-#define IEN_MTU3_TCIV3 IEN5\r
-#define IEN_MTU4_TGIA4 IEN6\r
-#define IEN_MTU4_TGIB4 IEN7\r
-#define IEN_MTU4_TGIC4 IEN0\r
-#define IEN_MTU4_TGID4 IEN1\r
-#define IEN_MTU4_TCIV4 IEN2\r
-#define IEN_MTU5_TGIU5 IEN3\r
-#define IEN_MTU5_TGIV5 IEN4\r
-#define IEN_MTU5_TGIW5 IEN5\r
-#define IEN_POE_OEI1 IEN2\r
-#define IEN_POE_OEI2 IEN3\r
-#define IEN_TMR0_CMIA0 IEN6\r
-#define IEN_TMR0_CMIB0 IEN7\r
-#define IEN_TMR0_OVI0 IEN0\r
-#define IEN_TMR1_CMIA1 IEN1\r
-#define IEN_TMR1_CMIB1 IEN2\r
-#define IEN_TMR1_OVI1 IEN3\r
-#define IEN_TMR2_CMIA2 IEN4\r
-#define IEN_TMR2_CMIB2 IEN5\r
-#define IEN_TMR2_OVI2 IEN6\r
-#define IEN_TMR3_CMIA3 IEN7\r
-#define IEN_TMR3_CMIB3 IEN0\r
-#define IEN_TMR3_OVI3 IEN1\r
-#define IEN_SCI2_ERI2 IEN2\r
-#define IEN_SCI2_RXI2 IEN3\r
-#define IEN_SCI2_TXI2 IEN4\r
-#define IEN_SCI2_TEI2 IEN5\r
-#define IEN_SCI0_ERI0 IEN6\r
-#define IEN_SCI0_RXI0 IEN7\r
-#define IEN_SCI0_TXI0 IEN0\r
-#define IEN_SCI0_TEI0 IEN1\r
-#define IEN_SCI1_ERI1 IEN2\r
-#define IEN_SCI1_RXI1 IEN3\r
-#define IEN_SCI1_TXI1 IEN4\r
-#define IEN_SCI1_TEI1 IEN5\r
-#define IEN_SCI5_ERI5 IEN6\r
-#define IEN_SCI5_RXI5 IEN7\r
-#define IEN_SCI5_TXI5 IEN0\r
-#define IEN_SCI5_TEI5 IEN1\r
-#define IEN_SCI6_ERI6 IEN2\r
-#define IEN_SCI6_RXI6 IEN3\r
-#define IEN_SCI6_TXI6 IEN4\r
-#define IEN_SCI6_TEI6 IEN5\r
-#define IEN_SCI8_ERI8 IEN6\r
-#define IEN_SCI8_RXI8 IEN7\r
-#define IEN_SCI8_TXI8 IEN0\r
-#define IEN_SCI8_TEI8 IEN1\r
-#define IEN_SCI9_ERI9 IEN2\r
-#define IEN_SCI9_RXI9 IEN3\r
-#define IEN_SCI9_TXI9 IEN4\r
-#define IEN_SCI9_TEI9 IEN5\r
-#define IEN_SCI12_ERI12 IEN6\r
-#define IEN_SCI12_RXI12 IEN7\r
-#define IEN_SCI12_TXI12 IEN0\r
-#define IEN_SCI12_TEI12 IEN1\r
-#define IEN_SCI12_SCIX0 IEN2\r
-#define IEN_SCI12_SCIX1 IEN3\r
-#define IEN_SCI12_SCIX2 IEN4\r
-#define IEN_SCI12_SCIX3 IEN5\r
-#define IEN_RIIC0_EEI0 IEN6\r
-#define IEN_RIIC0_RXI0 IEN7\r
-#define IEN_RIIC0_TXI0 IEN0\r
-#define IEN_RIIC0_TEI0 IEN1\r
-\r
-#define VECT_BSC_BUSERR 16\r
-#define VECT_ICU_SWINT 27\r
-#define VECT_CMT0_CMI0 28\r
-#define VECT_CMT1_CMI1 29\r
-#define VECT_CMT2_CMI2 30\r
-#define VECT_CMT3_CMI3 31\r
-#define VECT_CAC_FERRF 32\r
-#define VECT_CAC_MENDF 33\r
-#define VECT_CAC_OVFF 34\r
-#define VECT_USB0_D0FIFO0 36\r
-#define VECT_USB0_D1FIFO0 37\r
-#define VECT_USB0_USBI0 38\r
-#define VECT_RSPI0_SPEI0 44\r
-#define VECT_RSPI0_SPRI0 45\r
-#define VECT_RSPI0_SPTI0 46\r
-#define VECT_RSPI0_SPII0 47\r
-#define VECT_DOC_DOPCF 57\r
-#define VECT_CMPB_CMPB0 58\r
-#define VECT_CMPB_CMPB1 59\r
-#define VECT_CTSU_CTSUWR 60\r
-#define VECT_CTSU_CTSURD 61\r
-#define VECT_CTSU_CTSUFN 62\r
-#define VECT_RTC_CUP 63\r
-#define VECT_ICU_IRQ0 64\r
-#define VECT_ICU_IRQ1 65\r
-#define VECT_ICU_IRQ2 66\r
-#define VECT_ICU_IRQ3 67\r
-#define VECT_ICU_IRQ4 68\r
-#define VECT_ICU_IRQ5 69\r
-#define VECT_ICU_IRQ6 70\r
-#define VECT_ICU_IRQ7 71\r
-#define VECT_LVD_LVD1 88\r
-#define VECT_LVD_LVD2 89\r
-#define VECT_USB0_USBR0 90\r
-#define VECT_RTC_ALM 92\r
-#define VECT_RTC_PRD 93\r
-#define VECT_S12AD_S12ADI0 102\r
-#define VECT_S12AD_GBADI 103\r
-#define VECT_ELC_ELSR18I 106\r
-#define VECT_SSI0_SSIF0 108\r
-#define VECT_SSI0_SSIRXI0 109\r
-#define VECT_SSI0_SSITXI0 110\r
-#define VECT_MTU0_TGIA0 114\r
-#define VECT_MTU0_TGIB0 115\r
-#define VECT_MTU0_TGIC0 116\r
-#define VECT_MTU0_TGID0 117\r
-#define VECT_MTU0_TCIV0 118\r
-#define VECT_MTU0_TGIE0 119\r
-#define VECT_MTU0_TGIF0 120\r
-#define VECT_MTU1_TGIA1 121\r
-#define VECT_MTU1_TGIB1 122\r
-#define VECT_MTU1_TCIV1 123\r
-#define VECT_MTU1_TCIU1 124\r
-#define VECT_MTU2_TGIA2 125\r
-#define VECT_MTU2_TGIB2 126\r
-#define VECT_MTU2_TCIV2 127\r
-#define VECT_MTU2_TCIU2 128\r
-#define VECT_MTU3_TGIA3 129\r
-#define VECT_MTU3_TGIB3 130\r
-#define VECT_MTU3_TGIC3 131\r
-#define VECT_MTU3_TGID3 132\r
-#define VECT_MTU3_TCIV3 133\r
-#define VECT_MTU4_TGIA4 134\r
-#define VECT_MTU4_TGIB4 135\r
-#define VECT_MTU4_TGIC4 136\r
-#define VECT_MTU4_TGID4 137\r
-#define VECT_MTU4_TCIV4 138\r
-#define VECT_MTU5_TGIU5 139\r
-#define VECT_MTU5_TGIV5 140\r
-#define VECT_MTU5_TGIW5 141\r
-#define VECT_POE_OEI1 170\r
-#define VECT_POE_OEI2 171\r
-#define VECT_TMR0_CMIA0 174\r
-#define VECT_TMR0_CMIB0 175\r
-#define VECT_TMR0_OVI0 176\r
-#define VECT_TMR1_CMIA1 177\r
-#define VECT_TMR1_CMIB1 178\r
-#define VECT_TMR1_OVI1 179\r
-#define VECT_TMR2_CMIA2 180\r
-#define VECT_TMR2_CMIB2 181\r
-#define VECT_TMR2_OVI2 182\r
-#define VECT_TMR3_CMIA3 183\r
-#define VECT_TMR3_CMIB3 184\r
-#define VECT_TMR3_OVI3 185\r
-#define VECT_SCI2_ERI2 186\r
-#define VECT_SCI2_RXI2 187\r
-#define VECT_SCI2_TXI2 188\r
-#define VECT_SCI2_TEI2 189\r
-#define VECT_SCI0_ERI0 214\r
-#define VECT_SCI0_RXI0 215\r
-#define VECT_SCI0_TXI0 216\r
-#define VECT_SCI0_TEI0 217\r
-#define VECT_SCI1_ERI1 218\r
-#define VECT_SCI1_RXI1 219\r
-#define VECT_SCI1_TXI1 220\r
-#define VECT_SCI1_TEI1 221\r
-#define VECT_SCI5_ERI5 222\r
-#define VECT_SCI5_RXI5 223\r
-#define VECT_SCI5_TXI5 224\r
-#define VECT_SCI5_TEI5 225\r
-#define VECT_SCI6_ERI6 226\r
-#define VECT_SCI6_RXI6 227\r
-#define VECT_SCI6_TXI6 228\r
-#define VECT_SCI6_TEI6 229\r
-#define VECT_SCI8_ERI8 230\r
-#define VECT_SCI8_RXI8 231\r
-#define VECT_SCI8_TXI8 232\r
-#define VECT_SCI8_TEI8 233\r
-#define VECT_SCI9_ERI9 234\r
-#define VECT_SCI9_RXI9 235\r
-#define VECT_SCI9_TXI9 236\r
-#define VECT_SCI9_TEI9 237\r
-#define VECT_SCI12_ERI12 238\r
-#define VECT_SCI12_RXI12 239\r
-#define VECT_SCI12_TXI12 240\r
-#define VECT_SCI12_TEI12 241\r
-#define VECT_SCI12_SCIX0 242\r
-#define VECT_SCI12_SCIX1 243\r
-#define VECT_SCI12_SCIX2 244\r
-#define VECT_SCI12_SCIX3 245\r
-#define VECT_RIIC0_EEI0 246\r
-#define VECT_RIIC0_RXI0 247\r
-#define VECT_RIIC0_TXI0 248\r
-#define VECT_RIIC0_TEI0 249\r
-\r
-#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28\r
-#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA18\r
-#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17\r
-#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15\r
-#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15\r
-#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14\r
-#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14\r
-#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9\r
-#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5\r
-#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5\r
-#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5\r
-#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4\r
-#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4\r
-#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4\r
-#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
-#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31\r
-#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
-#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30\r
-#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
-#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29\r
-#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
-#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26\r
-#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
-#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25\r
-#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23\r
-#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21\r
-#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19\r
-#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17\r
-#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10\r
-#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9\r
-#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6\r
-#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
-#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4\r
-#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27\r
-#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27\r
-#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26\r
-#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26\r
-#define MSTP_IRDA SYSTEM.MSTPCRC.BIT.MSTPC20\r
-#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19\r
-#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0\r
-#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15\r
-#define MSTP_LCDC SYSTEM.MSTPCRD.BIT.MSTPD11\r
-#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10\r
-\r
-#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR\r
-#define _IR( x ) __IR( x )\r
-#define IR( x , y ) _IR( _ ## x ## _ ## y )\r
-#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE\r
-#define _DTCE( x ) __DTCE( x )\r
-#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y )\r
-#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x\r
-#define _IEN( x ) __IEN( x )\r
-#define IEN( x , y ) _IEN( _ ## x ## _ ## y )\r
-#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR\r
-#define _IPR( x ) __IPR( x )\r
-#define IPR( x , y ) _IPR( _ ## x ## _ ## y )\r
-#define __VECT( x ) VECT ## x\r
-#define _VECT( x ) __VECT( x )\r
-#define VECT( x , y ) _VECT( _ ## x ## _ ## y )\r
-#define __MSTP( x ) MSTP ## x\r
-#define _MSTP( x ) __MSTP( x )\r
-#define MSTP( x ) _MSTP( _ ## x )\r
-\r
-#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300)\r
-#define CAC (*(volatile struct st_cac __evenaccess *)0x8B000)\r
-#define CMPB (*(volatile struct st_cmpb __evenaccess *)0x8C580)\r
-#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000)\r
-#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002)\r
-#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008)\r
-#define CMT2 (*(volatile struct st_cmt0 __evenaccess *)0x88012)\r
-#define CMT3 (*(volatile struct st_cmt0 __evenaccess *)0x88018)\r
-#define CRC (*(volatile struct st_crc __evenaccess *)0x88280)\r
-#define CTSU (*(volatile struct st_ctsu __evenaccess *)0xA0900)\r
-#define DA (*(volatile struct st_da __evenaccess *)0x88040)\r
-#define DOC (*(volatile struct st_doc __evenaccess *)0x8B080)\r
-#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400)\r
-#define ELC (*(volatile struct st_elc __evenaccess *)0x8B100)\r
-#define FLASH (*(volatile struct st_flash __evenaccess *)0x7FC090)\r
-#define ICU (*(volatile struct st_icu __evenaccess *)0x87000)\r
-#define IRDA (*(volatile struct st_irda __evenaccess *)0x88410)\r
-#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030)\r
-#define LCDC (*(volatile struct st_lcdc __evenaccess *)0xA0800)\r
-#define MPC (*(volatile struct st_mpc __evenaccess *)0x8C11F)\r
-#define MTU (*(volatile struct st_mtu __evenaccess *)0x8860A)\r
-#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0x88690)\r
-#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0x88690)\r
-#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0x88692)\r
-#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0x88600)\r
-#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0x88600)\r
-#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0x88694)\r
-#define POE (*(volatile struct st_poe __evenaccess *)0x88900)\r
-#define PORT (*(volatile struct st_port __evenaccess *)0x8C121)\r
-#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000)\r
-#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001)\r
-#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002)\r
-#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003)\r
-#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004)\r
-#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005)\r
-#define PORT9 (*(volatile struct st_port9 __evenaccess *)0x8C009)\r
-#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A)\r
-#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B)\r
-#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C)\r
-#define PORTD (*(volatile struct st_portd __evenaccess *)0x8C00D)\r
-#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E)\r
-#define PORTF (*(volatile struct st_portf __evenaccess *)0x8C00F)\r
-#define PORTH (*(volatile struct st_porth __evenaccess *)0x8C051)\r
-#define PORTJ (*(volatile struct st_portj __evenaccess *)0x8C012)\r
-#define RIIC0 (*(volatile struct st_riic __evenaccess *)0x88300)\r
-#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0x88380)\r
-#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400)\r
-#define RTCB (*(volatile struct st_rtcb __evenaccess *)0x8C402)\r
-#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000)\r
-#define SCI0 (*(volatile struct st_sci0 __evenaccess *)0x8A000)\r
-#define SCI1 (*(volatile struct st_sci0 __evenaccess *)0x8A020)\r
-#define SCI2 (*(volatile struct st_sci0 __evenaccess *)0x8A040)\r
-#define SCI5 (*(volatile struct st_sci0 __evenaccess *)0x8A0A0)\r
-#define SCI6 (*(volatile struct st_sci0 __evenaccess *)0x8A0C0)\r
-#define SCI8 (*(volatile struct st_sci0 __evenaccess *)0x8A100)\r
-#define SCI9 (*(volatile struct st_sci0 __evenaccess *)0x8A120)\r
-#define SCI12 (*(volatile struct st_sci12 __evenaccess *)0x8B300)\r
-#define SMCI0 (*(volatile struct st_smci __evenaccess *)0x8A000)\r
-#define SMCI1 (*(volatile struct st_smci __evenaccess *)0x8A020)\r
-#define SMCI2 (*(volatile struct st_smci __evenaccess *)0x8A040)\r
-#define SMCI5 (*(volatile struct st_smci __evenaccess *)0x8A0A0)\r
-#define SMCI6 (*(volatile struct st_smci __evenaccess *)0x8A0C0)\r
-#define SMCI8 (*(volatile struct st_smci __evenaccess *)0x8A100)\r
-#define SMCI9 (*(volatile struct st_smci __evenaccess *)0x8A120)\r
-#define SMCI12 (*(volatile struct st_smci __evenaccess *)0x8B300)\r
-#define SSI0 (*(volatile struct st_ssi __evenaccess *)0x8A500)\r
-#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000)\r
-#define TEMPS (*(volatile struct st_temps __evenaccess *)0x7FC0AC)\r
-#define TMR0 (*(volatile struct st_tmr0 __evenaccess *)0x88200)\r
-#define TMR1 (*(volatile struct st_tmr1 __evenaccess *)0x88201)\r
-#define TMR2 (*(volatile struct st_tmr0 __evenaccess *)0x88210)\r
-#define TMR3 (*(volatile struct st_tmr1 __evenaccess *)0x88211)\r
-#define TMR01 (*(volatile struct st_tmr01 __evenaccess *)0x88204)\r
-#define TMR23 (*(volatile struct st_tmr01 __evenaccess *)0x88214)\r
-#define USB0 (*(volatile struct st_usb0 __evenaccess *)0xA0000)\r
-#pragma bit_order\r
-#pragma packoption\r
-#endif\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * This project provides two demo applications. A simple blinky style project,\r
- * and a more comprehensive test and demo application. The\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
- * select between the two. The simply blinky demo is implemented and described\r
- * in main_blinky.c. The more comprehensive test and demo application is\r
- * implemented and described in main_full.c.\r
- *\r
- * This file implements the code that is not demo specific, including the\r
- * hardware setup, standard FreeRTOS hook functions, and the ISR hander called\r
- * by the RTOS after interrupt entry (including nesting) has been taken care of.\r
- *\r
- * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON\r
- * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO\r
- * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!\r
- *\r
- */\r
-\r
-/* Scheduler include files. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "semphr.h"\r
-\r
-/* Renesas includes. */\r
-/* Renesas includes. */\r
-#include <rskrx113def.h>\r
-#include "r_cg_macrodriver.h"\r
-#include "r_cg_sci.h"\r
-#include "r_rsk_async.h"\r
-\r
-/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
-or 0 to run the more comprehensive test and demo application. */\r
-#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Configure the hardware as necessary to run this demo.\r
- */\r
-static void prvSetupHardware( void );\r
-\r
-/*\r
- * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
- * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
- */\r
-#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
- extern void main_blinky( void );\r
-#else\r
- extern void main_full( void );\r
-#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */\r
-\r
-/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
-within this file. */\r
-void vApplicationMallocFailedHook( void );\r
-void vApplicationIdleHook( void );\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
-void vApplicationTickHook( void );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-int main( void )\r
-{\r
- /* Configure the hardware ready to run the demo. */\r
- prvSetupHardware();\r
-\r
- /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
- of this file. */\r
- #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )\r
- {\r
- main_blinky();\r
- }\r
- #else\r
- {\r
- main_full();\r
- }\r
- #endif\r
-\r
- return 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvSetupHardware( void )\r
-{\r
- /* Set up SCI1 receive buffer */\r
- R_SCI1_Serial_Receive((uint8_t *) &g_rx_char, 1);\r
-\r
- /* Enable SCI1 operations */\r
- R_SCI1_Start();\r
-\r
- LED0 = LED_OFF;\r
- LED1 = LED_OFF;\r
- LED2 = LED_OFF;\r
- LED3 = LED_OFF;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationMallocFailedHook( void )\r
-{\r
- /* Called if a call to pvPortMalloc() fails because there is insufficient\r
- free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
- internally by FreeRTOS API functions that create tasks, queues, software\r
- timers, and semaphores. The size of the FreeRTOS heap is set by the\r
- configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
-\r
- /* Force an assert. */\r
- configASSERT( ( volatile void * ) NULL );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
-{\r
- ( void ) pcTaskName;\r
- ( void ) pxTask;\r
-\r
- /* Run time stack overflow checking is performed if\r
- configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
- function is called if a stack overflow is detected. */\r
-\r
- /* Force an assert. */\r
- configASSERT( ( volatile void * ) NULL );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationIdleHook( void )\r
-{\r
-volatile size_t xFreeHeapSpace;\r
-\r
- /* This is just a trivial example of an idle hook. It is called on each\r
- cycle of the idle task. It must *NOT* attempt to block. In this case the\r
- idle task just queries the amount of FreeRTOS heap that remains. See the\r
- memory management section on the http://www.FreeRTOS.org web site for memory\r
- management options. If there is a lot of heap memory free then the\r
- configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
- RAM. */\r
- xFreeHeapSpace = xPortGetFreeHeapSize();\r
-\r
- /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
- ( void ) xFreeHeapSpace;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationTickHook( void )\r
-{\r
- #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0\r
- {\r
- extern void vFullDemoTickHook( void );\r
-\r
- vFullDemoTickHook();\r
- }\r
- #endif\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The RX port uses this callback function to configure its tick interrupt.\r
-This allows the application to choose the tick interrupt source. */\r
-void vApplicationSetupTimerInterrupt( void )\r
-{\r
-const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL;\r
-\r
- /* Disable register write protection. */\r
- SYSTEM.PRCR.WORD = ulEnableRegisterWrite;\r
-\r
- /* Enable compare match timer 0. */\r
- MSTP( CMT0 ) = 0;\r
-\r
- /* Interrupt on compare match. */\r
- CMT0.CMCR.BIT.CMIE = 1;\r
-\r
- /* Set the compare match value. */\r
- CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 );\r
-\r
- /* Divide the PCLK by 8. */\r
- CMT0.CMCR.BIT.CKS = 0;\r
-\r
- /* Enable the interrupt... */\r
- _IEN( _CMT0_CMI0 ) = 1;\r
-\r
- /* ...and set its priority to the application defined kernel priority. */\r
- _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;\r
-\r
- /* Start the timer. */\r
- CMT.CMSTR0.BIT.STR0 = 1;\r
-\r
- /* Reneable register protection. */\r
- SYSTEM.PRCR.WORD = ulDisableRegisterWrite;\r
-}\r
-\r
-\r
-\r
+++ /dev/null
-/*******************************************************************************\r
-* DISCLAIMER\r
-* This software is supplied by Renesas Electronics Corporation and is only \r
-* intended for use with Renesas products. No other uses are authorized. This \r
-* software is owned by Renesas Electronics Corporation and is protected under \r
-* all applicable laws, including copyright laws.\r
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING \r
-* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT \r
-* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE \r
-* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.\r
-* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS \r
-* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE \r
-* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR \r
-* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE \r
-* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software \r
-* and to discontinue the availability of this software. By using this software,\r
-* you agree to the additional terms and conditions found by accessing the \r
-* following link:\r
-* http://www.renesas.com/disclaimer\r
-*\r
-* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.\r
-*******************************************************************************/\r
-/*******************************************************************************\r
-* File Name : rskrx113def.h\r
-* Device(s) : R5F51138AxFP\r
-* Tool-Chain : CCRX\r
-* H/W Platform : RSKRX113\r
-* Description : Defines macros relating to the RSK user LEDs and switches\r
-* Creation Date: 26/08/2014\r
-*******************************************************************************/\r
-\r
-\r
-#ifndef RSKRX113_H\r
-#define RSKRX113_H\r
-\r
-/*******************************************************************************\r
-User Defines\r
-*******************************************************************************/\r
-/* General Values */\r
-#define LED_ON (0)\r
-#define LED_OFF (1)\r
-#define SET_BIT_HIGH (1)\r
-#define SET_BIT_LOW (0)\r
-#define SET_BYTE_HIGH (0xFF)\r
-#define SET_BYTE_LOW (0x00)\r
-\r
-/* Switches */\r
-#define SW1 (PORTJ.PIDR.BIT.B0)\r
-#define SW2 (PORT3.PIDR.BIT.B2)\r
-#define SW3 (PORT2.PIDR.BIT.B7)\r
-\r
-/* LED port settings */\r
-#define LED0 (PORT2.PODR.BIT.B2)\r
-#define LED1 (PORT2.PODR.BIT.B3)\r
-#define LED2 (PORT2.PODR.BIT.B4)\r
-#define LED3 (PORT2.PODR.BIT.B5)\r
-\r
-\r
-#endif\r
-\r
</link>\r
</linkedResources>\r
<filteredResources>\r
+ <filter>\r
+ <id>1443109912507</id>\r
+ <name></name>\r
+ <type>6</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-RTOSDemo.dep</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
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+ <arguments>1.0-name-matches-false-false-RTOSDemo.ewd</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
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+ <matcher>\r
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+ <arguments>1.0-name-matches-false-false-RTOSDemo.ewp</arguments>\r
+ </matcher>\r
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+ <arguments>1.0-name-matches-false-false-RTOSDemo.ewt</arguments>\r
+ </matcher>\r
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+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-RTOSDemo.eww</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1443109912537</id>\r
+ <name></name>\r
+ <type>10</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-Debug</arguments>\r
+ </matcher>\r
+ </filter>\r
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+ <arguments>1.0-name-matches-false-false-PriorityDefinitions.h</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
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+ <name>src</name>\r
+ <type>10</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-IAR_Support</arguments>\r
+ </matcher>\r
+ </filter>\r
<filter>\r
<id>1442956878652</id>\r
<name>src/FreeRTOS_Source</name>\r
<arguments>1.0-name-matches-false-false-croutine.c</arguments>\r
</matcher>\r
</filter>\r
+ <filter>\r
+ <id>1443109933450</id>\r
+ <name>src/Main_Full</name>\r
+ <type>6</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-*IAR.*</arguments>\r
+ </matcher>\r
+ </filter>\r
<filter>\r
<id>1442956966430</id>\r
<name>src/FreeRTOS_Source/portable</name>\r
<configuration id="%com.renesas.cdt.rx.hardwaredebug.win32.configuration.Id.420935881" name="HardwareDebug">\r
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">\r
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>\r
- <provider class="com.renesas.cdt.common.build.spec.RXGCCBuiltinSpecsDetector" console="false" env-hash="-110846299564897653" id="RXGCCBuiltinSpecsDetector" keep-relative-paths="false" name="Renesas GCCBuildinCompilerSettings" options-hash="1410121582" parameter="rx-elf-gcc -E -P -v -dD ${INPUTS}" prefer-non-shared="true">\r
+ <provider class="com.renesas.cdt.common.build.spec.RXGCCBuiltinSpecsDetector" console="false" env-hash="-1183767966702391901" id="RXGCCBuiltinSpecsDetector" keep-relative-paths="false" name="Renesas GCCBuildinCompilerSettings" options-hash="1410121582" parameter="rx-elf-gcc -E -P -v -dD ${INPUTS}" prefer-non-shared="true">\r
<language-scope id="org.eclipse.cdt.core.gcc"/>\r
<language-scope id="org.eclipse.cdt.core.g++"/>\r
</provider>\r
#ifndef FREERTOS_CONFIG_H\r
#define FREERTOS_CONFIG_H\r
\r
-/* Renesas hardware definition header. */\r
-#include "iodefine.h"\r
+#ifdef __ICCRX__\r
+ #include <iorx231.h>\r
+ #include <machine.h>\r
+#endif\r
+\r
+#ifdef __GNUC__\r
+ #include "iodefine.h"\r
+#endif\r
\r
/*-----------------------------------------------------------\r
* Application specific definitions.\r
/* The peripheral used to generate the tick interrupt is configured as part of\r
the application code. This constant should be set to the vector number of the\r
peripheral chosen. As supplied this is CMT0. */\r
-#define configTICK_VECTOR _CMT0_CMI0\r
+#define configTICK_VECTOR VECT_CMT0_CMI0\r
\r
/* Set the following definitions to 1 to include the API function, or zero\r
to exclude the API function. */\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+ PUBLIC _vRegTest1Implementation\r
+ PUBLIC _vRegTest2Implementation\r
+ \r
+ EXTERN _ulRegTest1LoopCounter\r
+ EXTERN _ulRegTest2LoopCounter\r
+\r
+ RSEG CODE:CODE(4)\r
+\r
+/* This function is explained in the comments at the top of main.c. */\r
+_vRegTest1Implementation:\r
+\r
+ ;/* Put a known value in the guard byte of the accumulators. */\r
+ MOV.L #10, R1\r
+ MVTACGU R1, A0\r
+ MOV.L #20, R1\r
+ MVTACGU R1, A1\r
+\r
+ /* Put a known value in each register. */\r
+ MOV #1, R1 \r
+ MOV #2, R2 \r
+ MOV #3, R3 \r
+ MOV #4, R4 \r
+ MOV #5, R5 \r
+ MOV #6, R6 \r
+ MOV #7, R7 \r
+ MOV #8, R8 \r
+ MOV #9, R9 \r
+ MOV #10, R10 \r
+ MOV #11, R11 \r
+ MOV #12, R12 \r
+ MOV #13, R13 \r
+ MOV #14, R14 \r
+ MOV #15, R15 \r
+ \r
+ ;/* Put a known value in the hi and low of the accumulators. */\r
+ MVTACHI R1, A0\r
+ MVTACLO R2, A0\r
+ MVTACHI R3, A1\r
+ MVTACLO R4, A1\r
+ /* Loop, checking each itteration that each register still contains the\r
+ expected value. */\r
+TestLoop1: \r
+\r
+ /* Push the registers that are going to get clobbered. */\r
+ PUSHM R14-R15 \r
+ \r
+ /* Increment the loop counter to show this task is still getting CPU time. */\r
+ MOV #_ulRegTest1LoopCounter, R14 \r
+ MOV [ R14 ], R15 \r
+ ADD #1, R15 \r
+ MOV R15, [ R14 ] \r
+ \r
+ /* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */\r
+ MOV #1, R14 \r
+ MOV #0872E0H, R15 \r
+ MOV.B R14, [R15] \r
+ NOP \r
+ NOP \r
+ \r
+ ;/* Check accumulators. */\r
+ MVFACHI #0, A0, R15\r
+ CMP #1, R15\r
+ BNE RegTest1Error\r
+ MVFACLO #0, A0, R15\r
+ CMP #2, R15\r
+ BNE RegTest1Error\r
+ MVFACGU #0, A0, R15\r
+ CMP #10, R15\r
+ BNE RegTest1Error\r
+ MVFACHI #0, A1, R15\r
+ CMP #3, R15\r
+ BNE RegTest1Error\r
+ MVFACLO #0, A1, R15\r
+ CMP #4, R15\r
+ BNE RegTest1Error\r
+ MVFACGU #0, A1, R15\r
+ CMP #20, R15\r
+ BNE RegTest1Error\r
+\r
+ /* Restore the clobbered registers. */\r
+ POPM R14-R15 \r
+ \r
+ /* Now compare each register to ensure it still contains the value that was\r
+ set before this loop was entered. */\r
+ CMP #1, R1 \r
+ BNE RegTest1Error \r
+ CMP #2, R2 \r
+ BNE RegTest1Error \r
+ CMP #3, R3 \r
+ BNE RegTest1Error \r
+ CMP #4, R4 \r
+ BNE RegTest1Error \r
+ CMP #5, R5 \r
+ BNE RegTest1Error \r
+ CMP #6, R6 \r
+ BNE RegTest1Error \r
+ CMP #7, R7 \r
+ BNE RegTest1Error \r
+ CMP #8, R8 \r
+ BNE RegTest1Error \r
+ CMP #9, R9 \r
+ BNE RegTest1Error \r
+ CMP #10, R10 \r
+ BNE RegTest1Error \r
+ CMP #11, R11 \r
+ BNE RegTest1Error \r
+ CMP #12, R12 \r
+ BNE RegTest1Error \r
+ CMP #13, R13 \r
+ BNE RegTest1Error \r
+ CMP #14, R14 \r
+ BNE RegTest1Error \r
+ CMP #15, R15 \r
+ BNE RegTest1Error \r
+\r
+ /* All comparisons passed, start a new itteratio of this loop. */\r
+ BRA TestLoop1 \r
+ \r
+RegTest1Error: \r
+ /* A compare failed, just loop here so the loop counter stops incrementing\r
+ - causing the check task to indicate the error. */\r
+ BRA RegTest1Error \r
+/*-----------------------------------------------------------*/\r
+\r
+/* This function is explained in the comments at the top of main.c. */\r
+_vRegTest2Implementation:\r
+\r
+ ;/* Put a known value in the guard byte of the accumulators. */\r
+ MOV.L #1H, R1\r
+ MVTACGU R1, A0\r
+ MOV.L #2H, R1\r
+ MVTACGU R1, A1\r
+\r
+ /* Put a known value in each register. */\r
+ MOV #10H, R1 \r
+ MOV #20H, R2 \r
+ MOV #30H, R3 \r
+ MOV #40H, R4 \r
+ MOV #50H, R5 \r
+ MOV #60H, R6 \r
+ MOV #70H, R7 \r
+ MOV #80H, R8 \r
+ MOV #90H, R9 \r
+ MOV #100H, R10 \r
+ MOV #110H, R11 \r
+ MOV #120H, R12 \r
+ MOV #130H, R13 \r
+ MOV #140H, R14 \r
+ MOV #150H, R15 \r
+\r
+ ;/* Put a known value in the hi and low of the accumulators. */\r
+ MVTACHI R1, A0\r
+ MVTACLO R2, A0\r
+ MVTACHI R3, A1\r
+ MVTACLO R4, A1\r
+\r
+ /* Loop, checking each itteration that each register still contains the\r
+ expected value. */\r
+TestLoop2: \r
+\r
+ /* Push the registers that are going to get clobbered. */\r
+ PUSHM R14-R15 \r
+ \r
+ /* Increment the loop counter to show this task is still getting CPU time. */\r
+ MOV #_ulRegTest2LoopCounter, R14 \r
+ MOV [ R14 ], R15 \r
+ ADD #1, R15 \r
+ MOV R15, [ R14 ] \r
+ \r
+ ;/* Check accumulators. */\r
+ MVFACHI #0, A0, R15\r
+ CMP #10H, R15\r
+ BNE RegTest1Error\r
+ MVFACLO #0, A0, R15\r
+ CMP #20H, R15\r
+ BNE RegTest1Error\r
+ MVFACGU #0, A0, R15\r
+ CMP #1H, R15\r
+ BNE RegTest1Error\r
+ MVFACHI #0, A1, R15\r
+ CMP #30H, R15\r
+ BNE RegTest1Error\r
+ MVFACLO #0, A1, R15\r
+ CMP #40H, R15\r
+ BNE RegTest1Error\r
+ MVFACGU #0, A1, R15\r
+ CMP #2H, R15\r
+ BNE RegTest1Error\r
+\r
+ /* Restore the clobbered registers. */\r
+ POPM R14-R15 \r
+ \r
+ /* Now compare each register to ensure it still contains the value that was\r
+ set before this loop was entered. */\r
+ CMP #10H, R1 \r
+ BNE RegTest2Error \r
+ CMP #20H, R2 \r
+ BNE RegTest2Error \r
+ CMP #30H, R3 \r
+ BNE RegTest2Error \r
+ CMP #40H, R4 \r
+ BNE RegTest2Error \r
+ CMP #50H, R5 \r
+ BNE RegTest2Error \r
+ CMP #60H, R6 \r
+ BNE RegTest2Error \r
+ CMP #70H, R7 \r
+ BNE RegTest2Error \r
+ CMP #80H, R8 \r
+ BNE RegTest2Error \r
+ CMP #90H, R9 \r
+ BNE RegTest2Error \r
+ CMP #100H, R10 \r
+ BNE RegTest2Error \r
+ CMP #110H, R11 \r
+ BNE RegTest2Error \r
+ CMP #120H, R12 \r
+ BNE RegTest2Error \r
+ CMP #130H, R13 \r
+ BNE RegTest2Error \r
+ CMP #140H, R14 \r
+ BNE RegTest2Error \r
+ CMP #150H, R15 \r
+ BNE RegTest2Error \r
+\r
+ /* All comparisons passed, start a new itteratio of this loop. */\r
+ BRA TestLoop2 \r
+ \r
+RegTest2Error: \r
+ /* A compare failed, just loop here so the loop counter stops incrementing\r
+ - causing the check task to indicate the error. */\r
+ BRA RegTest2Error \r
+\r
+ \r
+ END\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef PRIORITY_DEFINITIONS_H\r
+#define PRIORITY_DEFINITIONS_H\r
+\r
+#ifndef __IASMRX__\r
+ #error This file is only intended to be included from the FreeRTOS IAR port layer assembly file.\r
+#endif\r
+\r
+/* The interrupt priority used by the kernel itself for the tick interrupt and\r
+the pended interrupt. This would normally be the lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+\r
+/* The maximum interrupt priority from which FreeRTOS API calls can be made.\r
+Interrupts that use a priority above this will not be effected by anything the\r
+kernel is doing. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+#endif /* PRIORITY_DEFINITIONS_H */\r
* DISCLAIMER\r
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.\r
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all\r
-* applicable laws, including copyright laws. \r
+* applicable laws, including copyright laws.\r
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED\r
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY\r
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,\r
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR\r
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.\r
-* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability \r
-* of this software. By using this software, you agree to the additional terms and conditions found by accessing the \r
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability\r
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the\r
* following link:\r
* http://www.renesas.com/disclaimer\r
*\r
/***********************************************************************************************************************\r
Includes\r
***********************************************************************************************************************/\r
-#include "../iodefine.h"\r
-#include "r_cg_interrupt_handlers.h"\r
+#ifdef __ICCRX__\r
+ #include <iorx231.h>\r
+#endif\r
+\r
+#ifdef __GNUC__\r
+ #include "../iodefine.h"\r
+#endif\r
+\r
+//_RB_#include "r_cg_interrupt_handlers.h"\r
\r
/***********************************************************************************************************************\r
Macro definitions (Register bit)\r
typedef unsigned short uint16_t;\r
typedef signed long int32_t;\r
typedef unsigned long uint32_t;\r
- \r
+\r
typedef signed char int_least8_t;\r
typedef signed short int_least16_t;\r
typedef signed long int_least32_t;\r
typedef unsigned char uint_least8_t;\r
typedef unsigned short uint_least16_t;\r
typedef unsigned long uint_least32_t;\r
- #endif \r
+ #endif\r
\r
typedef unsigned short MD_STATUS;\r
#define __TYPEDEF__\r
/* Reneable register protection. */\r
SYSTEM.PRCR.WORD = ulDisableRegisterWrite;\r
}\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __ICCRX__\r
+\r
+ #include <intrinsics.h>\r
+\r
+ /* Called from the C start up code when compiled with IAR. */\r
+ #pragma diag_suppress = Pm011\r
+ int __low_level_init(void)\r
+ #pragma diag_default = Pm011\r
+ {\r
+ extern void R_Systeminit( void );\r
+\r
+ __disable_interrupt();\r
+ R_Systeminit();\r
+\r
+ return (int)(1U);\r
+ }\r
+\r
+#endif /* __ICCRX__ */\r
\r
\r
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InputClock=25.000000\r
ICLK=240.000000\r
AllowClkSrcChange=0\r
<Windows>\r
\r
\r
- <Wnd0>\r
+ <Wnd2>\r
<Tabs>\r
<Tab>\r
<Identity>TabID-13537-752</Identity>\r
</Tab>\r
</Tabs>\r
\r
- <SelectedTab>0</SelectedTab></Wnd0><Wnd1>\r
+ <SelectedTab>0</SelectedTab></Wnd2><Wnd3>\r
<Tabs>\r
<Tab>\r
<Identity>TabID-29660-3316</Identity>\r
</Tab>\r
</Tabs>\r
\r
- <SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+ <SelectedTab>0</SelectedTab></Wnd3></Windows>\r
<Editor>\r
\r
\r
\r
\r
\r
- <Top><Row0><Sizes><Toolbar-007C83D8><key>iaridepm.enu1</key></Toolbar-007C83D8></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>742</Bottom><Right>400</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>239286</sizeVertCX><sizeVertCY>756098</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ <Top><Row0><Sizes><Toolbar-00887B08><key>iaridepm.enu1</key></Toolbar-00887B08></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>742</Bottom><Right>400</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>239286</sizeVertCX><sizeVertCY>756098</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
</Desktop>\r
</Workspace>\r
\r
#include "string.h"\r
\r
/* Hardware specifics. */\r
-#include "iorx111.h"\r
+#warning Used to include the chip specific header here.\r
+#include "machine.h"\r
\r
/*-----------------------------------------------------------*/\r
\r
projects / freertos / commitdiff