--- /dev/null
+REM This file should be executed from the command line prior to the first\r
+REM build. It will be necessary to refresh the Eclipse project once the\r
+REM .bat file has been executed (normally just press F5 to refresh).\r
+\r
+REM Copies all the required files from their location within the standard\r
+REM FreeRTOS directory structure to under the Eclipse project directory.\r
+REM This permits the Eclipse project to be used in 'managed' mode and without\r
+REM having to setup any linked resources.\r
+\r
+REM Standard paths\r
+SET FREERTOS_SOURCE=..\..\Source\r
+SET COMMON_SOURCE=..\Common\minimal\r
+SET COMMON_INCLUDE=..\Common\include\r
+\r
+REM Have the files already been copied?\r
+IF EXIST src\asf\thirdparty\FreeRTOS Goto END\r
+\r
+ REM Create the required directory structure.\r
+ MD src\asf\thirdparty\FreeRTOS\r
+ MD src\asf\thirdparty\FreeRTOS\include\r
+ MD src\asf\thirdparty\FreeRTOS\portable\r
+ MD src\asf\thirdparty\FreeRTOS\portable\GCC\r
+ MD src\asf\thirdparty\FreeRTOS\portable\GCC\ARM_CM3\r
+ MD src\asf\thirdparty\FreeRTOS\portable\MemMang \r
+ MD src\Common-Demo-Source\include\r
+ \r
+ REM Copy the core kernel files into the project directory\r
+ copy %FREERTOS_SOURCE%\tasks.c src\asf\thirdparty\FreeRTOS\r
+ copy %FREERTOS_SOURCE%\queue.c src\asf\thirdparty\FreeRTOS\r
+ copy %FREERTOS_SOURCE%\list.c src\asf\thirdparty\FreeRTOS\r
+ copy %FREERTOS_SOURCE%\timers.c src\asf\thirdparty\FreeRTOS\r
+\r
+ REM Copy the common header files into the project directory\r
+ copy %FREERTOS_SOURCE%\include\*.* src\asf\thirdparty\FreeRTOS\include\r
+ \r
+ REM Copy the portable layer files into the project directory\r
+ copy %FREERTOS_SOURCE%\portable\GCC\ARM_CM3\*.* src\asf\thirdparty\FreeRTOS\portable\GCC\ARM_CM3\r
+ \r
+ REM Copy the memory allocation files into the project directory\r
+ copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c src\asf\thirdparty\FreeRTOS\portable\MemMang\r
+\r
+ REM Copy the files that define the common demo tasks.\r
+ copy %COMMON_SOURCE%\dynamic.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\BlockQ.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\flash_timer.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\death.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\blocktim.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\semtest.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\PollQ.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\GenQTest.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\recmutex.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\countsem.c src\Common-Demo-Source\r
+ copy %COMMON_SOURCE%\integer.c src\Common-Demo-Source\r
+ \r
+ REM Copy the common demo file headers.\r
+ copy %COMMON_INCLUDE%\*.h src\Common-Demo-Source\include\r
+ \r
+: END\r
--- /dev/null
+\r
+Microsoft Visual Studio Solution File, Format Version 11.00\r
+# Atmel Studio Solution File, Format Version 11.00\r
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "RTOSDemo", "RTOSDemo.cproj", "{1A1A7C6E-BD59-4E82-8371-7F51AE9A4BD9}"\r
+EndProject\r
+Global\r
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution\r
+ Debug|ARM = Debug|ARM\r
+ EndGlobalSection\r
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution\r
+ {1A1A7C6E-BD59-4E82-8371-7F51AE9A4BD9}.Debug|ARM.ActiveCfg = Debug|ARM\r
+ {1A1A7C6E-BD59-4E82-8371-7F51AE9A4BD9}.Debug|ARM.Build.0 = Debug|ARM\r
+ EndGlobalSection\r
+ GlobalSection(SolutionProperties) = preSolution\r
+ HideSolutionNode = FALSE\r
+ EndGlobalSection\r
+EndGlobal\r
--- /dev/null
+<?xml version="1.0" encoding="utf-8"?>\r
+<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003" DefaultTargets="Build">\r
+ <PropertyGroup>\r
+ <SchemaVersion>2.0</SchemaVersion>\r
+ <ProjectVersion>6.0</ProjectVersion>\r
+ <ProjectGuid>{1a1a7c6e-bd59-4e82-8371-7f51ae9a4bd9}</ProjectGuid>\r
+ <Name>$(MSBuildProjectName)</Name>\r
+ <AssemblyName>$(MSBuildProjectName)</AssemblyName>\r
+ <RootNamespace>$(MSBuildProjectName)</RootNamespace>\r
+ <AsfVersion>3.3.0</AsfVersion>\r
+ <AsfFrameworkConfig>\r
+ <framework-data>\r
+ <options>\r
+ <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.services.basic.clock" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.services.basic.gpio" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam.drivers.pio" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam.drivers.usart" value="Add" config="" content-id="Atmel.ASF" />\r
+ </options>\r
+ <configurations>\r
+ <configuration key="config.sam.pio.pio_handler" value="yes" default="yes" content-id="Atmel.ASF" />\r
+ </configurations>\r
+ <files>\r
+ <file path="src/asf.h" framework="" version="3.3.0" source="./common/applications/user_application/sam3x8h_sam3x_ek/as5_arm_template/asf.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/main.c" framework="" version="3.3.0" source="common/applications/user_application/main.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/config/conf_board.h" framework="" version="3.3.0" source="common/applications/user_application/sam3x8h_sam3x_ek/conf_board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/boards/board.h" framework="" version="3.3.0" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/gpio/gpio.h" framework="" version="3.3.0" source="common/services/gpio/gpio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/gpio/sam_ioport/sam_gpio.h" framework="" version="3.3.0" source="common/services/gpio/sam_ioport/sam_gpio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/utils/interrupt.h" framework="" version="3.3.0" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.c" framework="" version="3.3.0" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/utils/interrupt/interrupt_sam_nvic.h" framework="" version="3.3.0" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/utils/parts.h" framework="" version="3.3.0" source="common/utils/parts.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/boards/sam3x_ek/init.c" framework="" version="3.3.0" source="sam/boards/sam3x_ek/init.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/boards/sam3x_ek/led.h" framework="" version="3.3.0" source="sam/boards/sam3x_ek/led.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/boards/sam3x_ek/sam3x_ek.h" framework="" version="3.3.0" source="sam/boards/sam3x_ek/sam3x_ek.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio.c" framework="" version="3.3.0" source="sam/drivers/pio/pio.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio.h" framework="" version="3.3.0" source="sam/drivers/pio/pio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio_handler.c" framework="" version="3.3.0" source="sam/drivers/pio/pio_handler.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pio/pio_handler.h" framework="" version="3.3.0" source="sam/drivers/pio/pio_handler.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_adc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_adc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_can.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_can.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_chipid.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_chipid.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_dacc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_dacc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_dmac.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_dmac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_efc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_efc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_emac.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_emac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_gpbr.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_gpbr.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_hsmci.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_hsmci.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_matrix.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_matrix.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_pdc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_pdc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_pio.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_pio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_pmc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_pwm.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_pwm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_rstc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_rstc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_rtc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_rtt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_rtt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_sdramc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_sdramc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_smc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_smc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_spi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_spi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_ssc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_ssc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_supc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_supc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_tc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_tc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_trng.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_trng.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_twi.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_twi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_uart.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_uart.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_uotghs.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_uotghs.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_usart.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_usart.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/component/component_wdt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/component/component_wdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_adc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_adc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_can0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_can0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_can1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_can1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_chipid.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_dacc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_dmac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_efc0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_efc1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_emac.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_emac.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_matrix.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_pioa.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piob.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_piob.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_pioc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piod.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_piod.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pioe.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_pioe.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_piof.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_piof.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_pwm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_rstc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_rtt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_sdramc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_sdramc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_smc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_smc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_spi0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_spi1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_spi1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_ssc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_supc.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_supc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_tc0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_tc1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_tc2.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_trng.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_trng.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_twi0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_twi1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_uart.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_uart.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_usart0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_usart1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_usart2.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_usart3.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/instance/instance_wdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/pio/pio_sam3a4c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/pio/pio_sam3a4c.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/pio/pio_sam3a8c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/pio/pio_sam3a8c.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/pio/pio_sam3x4c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/pio/pio_sam3x4c.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/pio/pio_sam3x4e.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/pio/pio_sam3x4e.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/pio/pio_sam3x8c.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8h.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/pio/pio_sam3x8h.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/sam3a4c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/sam3a4c.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/sam3a8c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/sam3a8c.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/sam3x4c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/sam3x4c.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/sam3x4e.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/sam3x4e.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/sam3x8c.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/sam3x8c.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/sam3x8e.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/sam3x8e.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/sam3x8h.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/sam3x8h.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/include/sam3xa.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/include/sam3xa.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/source/templates/exceptions.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/source/templates/exceptions.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/source/templates/exceptions.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/source/templates/exceptions.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/source/templates/system_sam3x.c" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/source/templates/system_sam3x.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h" framework="" version="3.3.0" source="sam/utils/cmsis/sam3x/source/templates/system_sam3x.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/compiler.h" framework="" version="3.3.0" source="sam/utils/compiler.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/header_files/io.h" framework="" version="3.3.0" source="sam/utils/header_files/io.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld" framework="" version="3.3.0" source="sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/make/Makefile.in" framework="" version="3.3.0" source="sam/utils/make/Makefile.in" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/preprocessor/mrepeat.h" framework="" version="3.3.0" source="sam/utils/preprocessor/mrepeat.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/preprocessor/preprocessor.h" framework="" version="3.3.0" source="sam/utils/preprocessor/preprocessor.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/preprocessor/stringz.h" framework="" version="3.3.0" source="sam/utils/preprocessor/stringz.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/preprocessor/tpaste.h" framework="" version="3.3.0" source="sam/utils/preprocessor/tpaste.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/utils/status_codes.h" framework="" version="3.3.0" source="sam/utils/status_codes.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" framework="" version="3.3.0" source="thirdparty/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/thirdparty/CMSIS/Include/core_cm3.h" framework="" version="3.3.0" source="thirdparty/CMSIS/Include/core_cm3.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/thirdparty/CMSIS/Include/core_cmFunc.h" framework="" version="3.3.0" source="thirdparty/CMSIS/Include/core_cmFunc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/thirdparty/CMSIS/Include/core_cmInstr.h" framework="" version="3.3.0" source="thirdparty/CMSIS/Include/core_cmInstr.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/thirdparty/CMSIS/README.txt" framework="" version="3.3.0" source="thirdparty/CMSIS/README.txt" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/thirdparty/CMSIS/license.txt" framework="" version="3.3.0" source="thirdparty/CMSIS/license.txt" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pmc/pmc.c" framework="" version="" source="sam\drivers\pmc\pmc.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pmc/pmc.h" framework="" version="" source="sam\drivers\pmc\pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/pmc/sleep.h" framework="" version="" source="sam\drivers\pmc\sleep.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/clock/sam3x/sysclk.c" framework="" version="" source="common\services\clock\sam3x\sysclk.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/clock/genclk.h" framework="" version="" source="common\services\clock\genclk.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/clock/osc.h" framework="" version="" source="common\services\clock\osc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/clock/sam3x/pll.h" framework="" version="" source="common\services\clock\sam3x\pll.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/clock/sam3x/sysclk.h" framework="" version="" source="common\services\clock\sam3x\sysclk.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/clock/sam3x/osc.h" framework="" version="" source="common\services\clock\sam3x\osc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/clock/sam3x/genclk.h" framework="" version="" source="common\services\clock\sam3x\genclk.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/clock/sysclk.h" framework="" version="" source="common\services\clock\sysclk.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/common/services/clock/pll.h" framework="" version="" source="common\services\clock\pll.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/config/conf_clock.h" framework="" version="" source="common\services\clock\sam3x\module_config\conf_clock.h" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/usart/usart.c" framework="" version="" source="sam\drivers\usart\usart.c" changed="False" content-id="Atmel.ASF" />\r
+ <file path="src/asf/sam/drivers/usart/usart.h" framework="" version="" source="sam\drivers\usart\usart.h" changed="False" content-id="Atmel.ASF" />\r
+ </files>\r
+ <documentation help="http://asf.atmel.com/docs/3.3.0/common.applications.user_application.sam3x_ek/html/index.html" />\r
+ </framework-data>\r
+ </AsfFrameworkConfig>\r
+ <avrdevice>ATSAM3X8H</avrdevice>\r
+ <avrdeviceseries>sam3x</avrdeviceseries>\r
+ <Language>C</Language>\r
+ <ToolchainName>com.Atmel.ARMGCC</ToolchainName>\r
+ <ArmGccProjectExtensions />\r
+ <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>\r
+ <OutputFileName>$(MSBuildProjectName)</OutputFileName>\r
+ <OutputFileExtension>.elf</OutputFileExtension>\r
+ <OutputType>Executable</OutputType>\r
+ <ToolchainFlavour>Native</ToolchainFlavour>\r
+ <KeepTimersRunning>true</KeepTimersRunning>\r
+ <OverrideVtor>false</OverrideVtor>\r
+ <OverrideVtorValue />\r
+ <eraseonlaunchrule>1</eraseonlaunchrule>\r
+ <avrtoolinterface>JTAG</avrtoolinterface>\r
+ <avrtool>com.atmel.avrdbg.tool.samice</avrtool>\r
+ <com_atmel_avrdbg_tool_samice>\r
+ <ToolType xmlns="">com.atmel.avrdbg.tool.samice</ToolType>\r
+ <ToolName xmlns="">SAM-ICE</ToolName>\r
+ <ToolNumber xmlns="">000158000789</ToolNumber>\r
+ <KeepTimersRunning xmlns="">true</KeepTimersRunning>\r
+ <OverrideVtor xmlns="">false</OverrideVtor>\r
+ <OverrideVtorValue xmlns="">\r
+ </OverrideVtorValue>\r
+ <Channel xmlns="">\r
+ <host>127.0.0.1</host>\r
+ <port>1596</port>\r
+ <ssl>False</ssl>\r
+ </Channel>\r
+ <ToolOptions xmlns="">\r
+ <InterfaceName>JTAG</InterfaceName>\r
+ <InterfaceProperties>\r
+ <JtagDbgClock>4000000</JtagDbgClock>\r
+ <JtagProgClock>1000000</JtagProgClock>\r
+ <IspClock>150000</IspClock>\r
+ <JtagInChain>false</JtagInChain>\r
+ <JtagEnableExtResetOnStartSession>false</JtagEnableExtResetOnStartSession>\r
+ <JtagDevicesBefore>0</JtagDevicesBefore>\r
+ <JtagDevicesAfter>0</JtagDevicesAfter>\r
+ <JtagInstrBitsBefore>0</JtagInstrBitsBefore>\r
+ <JtagInstrBitsAfter>0</JtagInstrBitsAfter>\r
+ </InterfaceProperties>\r
+ </ToolOptions>\r
+ </com_atmel_avrdbg_tool_samice>\r
+ </PropertyGroup>\r
+ <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">\r
+ <ToolchainSettings>\r
+ <ArmGcc>\r
+ <armgcc.common.general.symbols>__SAM3X8H__</armgcc.common.general.symbols>\r
+ <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>\r
+ <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>\r
+ <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>\r
+ <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>\r
+ <armgcc.compiler.symbols.DefSymbols>\r
+ <ListValues>\r
+ <Value>BOARD=SAM3X_EK</Value>\r
+ <Value>__SAM3X8H__</Value>\r
+ </ListValues>\r
+ </armgcc.compiler.symbols.DefSymbols>\r
+ <armgcc.compiler.directories.IncludePaths>\r
+ <ListValues>\r
+ <Value>../src</Value>\r
+ <Value>../src/asf/common/applications/user_application/sam3x8h_sam3x_ek</Value>\r
+ <Value>../src/asf/common/boards</Value>\r
+ <Value>../src/asf/common/services/gpio</Value>\r
+ <Value>../src/asf/common/utils</Value>\r
+ <Value>../src/asf/sam/boards</Value>\r
+ <Value>../src/asf/sam/boards/sam3x_ek</Value>\r
+ <Value>../src/asf/sam/drivers/pio</Value>\r
+ <Value>../src/asf/sam/utils</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/include</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/source/templates</Value>\r
+ <Value>../src/asf/sam/utils/header_files</Value>\r
+ <Value>../src/asf/sam/utils/preprocessor</Value>\r
+ <Value>../src/asf/thirdparty/CMSIS/Include</Value>\r
+ <Value>../src/config</Value>\r
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles</Value>\r
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\CMSIS\Include</Value>\r
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL</Value>\r
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL\sam3xa\include</Value>\r
+ <Value>../src/asf/sam/drivers/pmc</Value>\r
+ <Value>../src/asf/common/services/clock</Value>\r
+ <Value>../src/asf/sam/drivers/usart</Value>\r
+ </ListValues>\r
+ </armgcc.compiler.directories.IncludePaths>\r
+ <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>\r
+ <armgcc.compiler.optimization.OtherFlags>-fdata-sections</armgcc.compiler.optimization.OtherFlags>\r
+ <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>\r
+ <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>\r
+ <armgcc.compiler.miscellaneous.OtherFlags>-pipe -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -Dprintf=iprintf</armgcc.compiler.miscellaneous.OtherFlags>\r
+ <armgcc.linker.general.DoNotUseStandardStartFiles />\r
+ <armgcc.linker.general.DoNotUseDefaultLibraries />\r
+ <armgcc.linker.general.NoStartupOrDefaultLibs />\r
+ <armgcc.linker.optimization.GarbageCollectUnusedSections>True</armgcc.linker.optimization.GarbageCollectUnusedSections>\r
+ <armgcc.linker.miscellaneous.LinkerFlags>-T../src/asf/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld -Wl,--cref -Wl,--entry=Reset_Handler -mthumb</armgcc.linker.miscellaneous.LinkerFlags>\r
+ <armgcc.assembler.general.IncludePaths>\r
+ <ListValues>\r
+ <Value>../src</Value>\r
+ <Value>../src/asf/common/applications/user_application/sam3x8h_sam3x_ek</Value>\r
+ <Value>../src/asf/common/boards</Value>\r
+ <Value>../src/asf/common/services/gpio</Value>\r
+ <Value>../src/asf/common/utils</Value>\r
+ <Value>../src/asf/sam/boards</Value>\r
+ <Value>../src/asf/sam/boards/sam3x_ek</Value>\r
+ <Value>../src/asf/sam/drivers/pio</Value>\r
+ <Value>../src/asf/sam/utils</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/include</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/source/templates</Value>\r
+ <Value>../src/asf/sam/utils/header_files</Value>\r
+ <Value>../src/asf/sam/utils/preprocessor</Value>\r
+ <Value>../src/asf/thirdparty/CMSIS/Include</Value>\r
+ <Value>../src/config</Value>\r
+ <Value>../src/asf/sam/drivers/pmc</Value>\r
+ <Value>../src/asf/common/services/clock</Value>\r
+ <Value>../src/asf/sam/drivers/usart</Value>\r
+ </ListValues>\r
+ </armgcc.assembler.general.IncludePaths>\r
+ <armgcc.preprocessingassembler.general.AssemblerFlags>-DBOARD=SAM3X_EK -D__SAM3X8H__</armgcc.preprocessingassembler.general.AssemblerFlags>\r
+ <armgcc.preprocessingassembler.general.IncludePaths>\r
+ <ListValues>\r
+ <Value>../src</Value>\r
+ <Value>../src/asf/common/applications/user_application/sam3x8h_sam3x_ek</Value>\r
+ <Value>../src/asf/common/boards</Value>\r
+ <Value>../src/asf/common/services/gpio</Value>\r
+ <Value>../src/asf/common/utils</Value>\r
+ <Value>../src/asf/sam/boards</Value>\r
+ <Value>../src/asf/sam/boards/sam3x_ek</Value>\r
+ <Value>../src/asf/sam/drivers/pio</Value>\r
+ <Value>../src/asf/sam/utils</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/include</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/source/templates</Value>\r
+ <Value>../src/asf/sam/utils/header_files</Value>\r
+ <Value>../src/asf/sam/utils/preprocessor</Value>\r
+ <Value>../src/asf/thirdparty/CMSIS/Include</Value>\r
+ <Value>../src/config</Value>\r
+ <Value>../src/asf/sam/drivers/pmc</Value>\r
+ <Value>../src/asf/common/services/clock</Value>\r
+ <Value>../src/asf/sam/drivers/usart</Value>\r
+ </ListValues>\r
+ </armgcc.preprocessingassembler.general.IncludePaths>\r
+ </ArmGcc>\r
+ </ToolchainSettings>\r
+ <GenerateHexFile>True</GenerateHexFile>\r
+ <GenerateMapFile>True</GenerateMapFile>\r
+ <GenerateListFile>True</GenerateListFile>\r
+ <GenerateEepFile>True</GenerateEepFile>\r
+ </PropertyGroup>\r
+ <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">\r
+ <ToolchainSettings>\r
+ <ArmGcc>\r
+ <armgcc.common.general.symbols>__SAM3X8H__</armgcc.common.general.symbols>\r
+ <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>\r
+ <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>\r
+ <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>\r
+ <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>\r
+ <armgcc.compiler.symbols.DefSymbols>\r
+ <ListValues>\r
+ <Value>BOARD=SAM3X_EK</Value>\r
+ <Value>__SAM3X8H__</Value>\r
+ </ListValues>\r
+ </armgcc.compiler.symbols.DefSymbols>\r
+ <armgcc.compiler.directories.IncludePaths>\r
+ <ListValues>\r
+ <Value>../src</Value>\r
+ <Value>../src/asf/common/applications/user_application/sam3x8h_sam3x_ek</Value>\r
+ <Value>../src/asf/common/boards</Value>\r
+ <Value>../src/asf/common/services/gpio</Value>\r
+ <Value>../src/asf/common/utils</Value>\r
+ <Value>../src/asf/sam/boards</Value>\r
+ <Value>../src/asf/sam/boards/sam3x_ek</Value>\r
+ <Value>../src/asf/sam/drivers/pio</Value>\r
+ <Value>../src/asf/sam/utils</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/include</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/source/templates</Value>\r
+ <Value>../src/asf/sam/utils/header_files</Value>\r
+ <Value>../src/asf/sam/utils/preprocessor</Value>\r
+ <Value>../src/asf/thirdparty/CMSIS/Include</Value>\r
+ <Value>../src/config</Value>\r
+ <Value>../src/asf/thirdparty/FreeRTOS/include</Value>\r
+ <Value>../src/asf/thirdparty/FreeRTOS/portable/GCC/ARM_CM3</Value>\r
+ <Value>../src/Common-Demo-Source/include</Value>\r
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles</Value>\r
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\CMSIS\Include</Value>\r
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL</Value>\r
+ <Value>C:\devtools\Atmel\Atmel Studio 6.0\extensions\Atmel\ARMGCC\3.3.1.83\ARMSupportFiles\Device\ATMEL\sam3xa\include</Value>\r
+ <Value>../src/asf/sam/drivers/pmc</Value>\r
+ <Value>../src/asf/common/services/clock</Value>\r
+ <Value>../src/asf/sam/drivers/usart</Value>\r
+ </ListValues>\r
+ </armgcc.compiler.directories.IncludePaths>\r
+ <armgcc.compiler.optimization.OtherFlags>-fdata-sections</armgcc.compiler.optimization.OtherFlags>\r
+ <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>\r
+ <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>\r
+ <armgcc.compiler.warnings.AllWarnings>True</armgcc.compiler.warnings.AllWarnings>\r
+ <armgcc.compiler.miscellaneous.OtherFlags>-pipe -Wall -Wextra -std=gnu99 -ffunction-sections -fdata-sections --param max-inline-insns-single=500 -Dprintf=iprintf</armgcc.compiler.miscellaneous.OtherFlags>\r
+ <armgcc.linker.optimization.GarbageCollectUnusedSections>True</armgcc.linker.optimization.GarbageCollectUnusedSections>\r
+ <armgcc.linker.miscellaneous.LinkerFlags>-T../src/asf/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld -Wl,--cref -Wl,--entry=Reset_Handler -mthumb</armgcc.linker.miscellaneous.LinkerFlags>\r
+ <armgcc.assembler.general.IncludePaths>\r
+ <ListValues>\r
+ <Value>../src</Value>\r
+ <Value>../src/asf/common/applications/user_application/sam3x8h_sam3x_ek</Value>\r
+ <Value>../src/asf/common/boards</Value>\r
+ <Value>../src/asf/common/services/gpio</Value>\r
+ <Value>../src/asf/common/utils</Value>\r
+ <Value>../src/asf/sam/boards</Value>\r
+ <Value>../src/asf/sam/boards/sam3x_ek</Value>\r
+ <Value>../src/asf/sam/drivers/pio</Value>\r
+ <Value>../src/asf/sam/utils</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/include</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/source/templates</Value>\r
+ <Value>../src/asf/sam/utils/header_files</Value>\r
+ <Value>../src/asf/sam/utils/preprocessor</Value>\r
+ <Value>../src/asf/thirdparty/CMSIS/Include</Value>\r
+ <Value>../src/config</Value>\r
+ <Value>../src/asf/sam/drivers/pmc</Value>\r
+ <Value>../src/asf/common/services/clock</Value>\r
+ <Value>../src/asf/sam/drivers/usart</Value>\r
+ </ListValues>\r
+ </armgcc.assembler.general.IncludePaths>\r
+ <armgcc.preprocessingassembler.general.AssemblerFlags>-DBOARD=SAM3X_EK -D__SAM3X8H__</armgcc.preprocessingassembler.general.AssemblerFlags>\r
+ <armgcc.preprocessingassembler.general.IncludePaths>\r
+ <ListValues>\r
+ <Value>../src</Value>\r
+ <Value>../src/asf/common/applications/user_application/sam3x8h_sam3x_ek</Value>\r
+ <Value>../src/asf/common/boards</Value>\r
+ <Value>../src/asf/common/services/gpio</Value>\r
+ <Value>../src/asf/common/utils</Value>\r
+ <Value>../src/asf/sam/boards</Value>\r
+ <Value>../src/asf/sam/boards/sam3x_ek</Value>\r
+ <Value>../src/asf/sam/drivers/pio</Value>\r
+ <Value>../src/asf/sam/utils</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/include</Value>\r
+ <Value>../src/asf/sam/utils/cmsis/sam3x/source/templates</Value>\r
+ <Value>../src/asf/sam/utils/header_files</Value>\r
+ <Value>../src/asf/sam/utils/preprocessor</Value>\r
+ <Value>../src/asf/thirdparty/CMSIS/Include</Value>\r
+ <Value>../src/config</Value>\r
+ <Value>../src/asf/sam/drivers/pmc</Value>\r
+ <Value>../src/asf/common/services/clock</Value>\r
+ <Value>../src/asf/sam/drivers/usart</Value>\r
+ </ListValues>\r
+ </armgcc.preprocessingassembler.general.IncludePaths>\r
+ </ArmGcc>\r
+ </ToolchainSettings>\r
+ <GenerateHexFile>True</GenerateHexFile>\r
+ <GenerateMapFile>True</GenerateMapFile>\r
+ <GenerateListFile>True</GenerateListFile>\r
+ <GenerateEepFile>True</GenerateEepFile>\r
+ </PropertyGroup>\r
+ <ItemGroup>\r
+ <None Include="src\asf\common\services\clock\genclk.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\clock\osc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\clock\sam3x\pll.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\clock\sam3x\osc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\clock\sam3x\genclk.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\clock\pll.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <Compile Include="src\asf\common\services\clock\sam3x\sysclk.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <None Include="src\asf\common\services\clock\sam3x\sysclk.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\clock\sysclk.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <Compile Include="src\asf\common\utils\interrupt\interrupt_sam_nvic.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\sam\boards\sam3x_ek\init.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\sam\drivers\pio\pio.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\sam\drivers\pio\pio_handler.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\sam\drivers\pmc\pmc.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <None Include="src\asf\sam\drivers\pmc\pmc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\drivers\pmc\sleep.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <Compile Include="src\asf\sam\drivers\usart\usart.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <None Include="src\asf\sam\drivers\usart\usart.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <Compile Include="src\asf\sam\utils\cmsis\sam3x\source\templates\exceptions.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\sam\utils\cmsis\sam3x\source\templates\gcc\startup_sam3x.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\sam\utils\cmsis\sam3x\source\templates\system_sam3x.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\include\croutine.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\include\FreeRTOS.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\include\list.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\include\mpu_wrappers.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\include\portable.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\include\projdefs.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\include\queue.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\include\semphr.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\include\StackMacros.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\include\task.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\include\timers.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\list.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\portable\GCC\ARM_CM3\port.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\portable\GCC\ARM_CM3\portmacro.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\portable\MemMang\heap_4.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\queue.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\tasks.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\asf\thirdparty\FreeRTOS\timers.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\BlockQ.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\blocktim.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\comtest.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\countsem.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\death.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\dynamic.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\flash_timer.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\GenQTest.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\AltBlckQ.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\AltBlock.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\AltPollQ.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\AltQTest.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\BlockQ.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\blocktim.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\comtest.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\comtest2.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\comtest_strings.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\countsem.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\crflash.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\crhook.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\death.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\demo_serial.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\dynamic.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\fileIO.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\flash.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\flash_timer.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\flop.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\GenQTest.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\integer.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\IntQueue.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\mevents.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\partest.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\PollQ.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\print.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\QPeek.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\recmutex.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\semtest.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\serial.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\include\TimerDemo.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\integer.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\PollQ.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\recmutex.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\Common-Demo-Source\semtest.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <None Include="src\config\conf_clock.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <Compile Include="src\FreeRTOSConfig.h">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\main.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\main_blinky.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\main_full.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\ParTest.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <Compile Include="src\serial.c">\r
+ <SubType>compile</SubType>\r
+ </Compile>\r
+ <None Include="src\asf.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\boards\board.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\gpio\gpio.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\services\gpio\sam_ioport\sam_gpio.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\utils\interrupt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\utils\interrupt\interrupt_sam_nvic.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\common\utils\parts.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\boards\sam3x_ek\led.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\boards\sam3x_ek\sam3x_ek.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\drivers\pio\pio.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\drivers\pio\pio_handler.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_adc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_can.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_chipid.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_dacc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_dmac.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_efc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_emac.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_gpbr.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_hsmci.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_matrix.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_pdc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_pio.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_pmc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_pwm.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_rstc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_rtc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_rtt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_sdramc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_smc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_spi.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_ssc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_supc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_tc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_trng.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_twi.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_uart.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_uotghs.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_usart.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\component\component_wdt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_adc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_can0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_can1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_chipid.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_dacc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_dmac.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_efc0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_efc1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_emac.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_gpbr.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_hsmci.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_matrix.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_pioa.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_piob.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_pioc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_piod.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_pioe.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_piof.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_pmc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_pwm.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_rstc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_rtc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_rtt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_sdramc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_smc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_spi0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_spi1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_ssc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_supc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_tc0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_tc1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_tc2.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_trng.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_twi0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_twi1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_uart.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_uotghs.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_usart0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_usart1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_usart2.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_usart3.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\instance\instance_wdt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\pio\pio_sam3a4c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\pio\pio_sam3a8c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\pio\pio_sam3x4c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\pio\pio_sam3x4e.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\pio\pio_sam3x8c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\pio\pio_sam3x8e.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\pio\pio_sam3x8h.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\sam3a4c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\sam3a8c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\sam3x4c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\sam3x4e.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\sam3x8c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\sam3x8e.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\sam3x8h.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\include\sam3xa.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\source\templates\exceptions.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam3x\source\templates\system_sam3x.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\compiler.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\header_files\io.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\linker_scripts\sam3x\sam3x8\gcc\flash.ld">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\make\Makefile.in">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\preprocessor\mrepeat.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\preprocessor\preprocessor.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\preprocessor\stringz.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\preprocessor\tpaste.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\status_codes.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\CMSIS END USER LICENCE AGREEMENT.pdf">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\Include\core_cm3.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\Include\core_cmFunc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\Include\core_cmInstr.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\README.txt">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\license.txt">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\FreeRTOS\include\mpu_wrappers.h.bak">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\FreeRTOS\portable\GCC\ARM_CM3\port.c.bak">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\config\conf_board.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ </ItemGroup>\r
+ <ItemGroup>\r
+ <Folder Include="src\" />\r
+ <Folder Include="src\asf\" />\r
+ <Folder Include="src\asf\common\" />\r
+ <Folder Include="src\asf\common\boards\" />\r
+ <Folder Include="src\asf\common\services\" />\r
+ <Folder Include="src\asf\common\services\clock\" />\r
+ <Folder Include="src\asf\common\services\clock\sam3x\" />\r
+ <Folder Include="src\asf\common\services\gpio\" />\r
+ <Folder Include="src\asf\common\services\gpio\sam_ioport\" />\r
+ <Folder Include="src\asf\common\utils\" />\r
+ <Folder Include="src\asf\common\utils\interrupt\" />\r
+ <Folder Include="src\asf\sam\" />\r
+ <Folder Include="src\asf\sam\boards\" />\r
+ <Folder Include="src\asf\sam\boards\sam3x_ek\" />\r
+ <Folder Include="src\asf\sam\drivers\" />\r
+ <Folder Include="src\asf\sam\drivers\pio\" />\r
+ <Folder Include="src\asf\sam\drivers\pmc\" />\r
+ <Folder Include="src\asf\sam\drivers\usart\" />\r
+ <Folder Include="src\asf\sam\utils\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3x\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3x\include\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3x\include\component\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3x\include\instance\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3x\include\pio\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3x\source\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3x\source\templates\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam3x\source\templates\gcc\" />\r
+ <Folder Include="src\asf\sam\utils\header_files\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\sam3x\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\sam3x\sam3x8\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\sam3x\sam3x8\gcc\" />\r
+ <Folder Include="src\asf\sam\utils\make\" />\r
+ <Folder Include="src\asf\sam\utils\preprocessor\" />\r
+ <Folder Include="src\asf\thirdparty\" />\r
+ <Folder Include="src\asf\thirdparty\CMSIS\" />\r
+ <Folder Include="src\asf\thirdparty\CMSIS\Include\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\include\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\portable\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\portable\GCC\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\portable\GCC\ARM_CM3\" />\r
+ <Folder Include="src\asf\thirdparty\FreeRTOS\portable\MemMang\" />\r
+ <Folder Include="src\Common-Demo-Source\" />\r
+ <Folder Include="src\Common-Demo-Source\include\" />\r
+ <Folder Include="src\config\" />\r
+ </ItemGroup>\r
+ <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />\r
+</Project>
\ No newline at end of file
--- /dev/null
+Service , Message , Max , Min , Average , Count , frequency , TimedOut
+\r
+Stream,setLogBits,15.625,15.625,15.625,2,0\r
--- /dev/null
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="UNSPECIFIED"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+/*\r
+ * This version of comtest. c is for use on systems that have limited stack\r
+ * space and no display facilities. The complete version can be found in\r
+ * the Demo/Common/Full directory.\r
+ *\r
+ * Creates two tasks that operate on an interrupt driven serial port. A\r
+ * loopback connector should be used so that everything that is transmitted is\r
+ * also received. The serial port does not use any flow control. On a\r
+ * standard 9way 'D' connector pins two and three should be connected together.\r
+ *\r
+ * The first task posts a sequence of characters to the Tx queue, toggling an\r
+ * LED on each successful post. At the end of the sequence it sleeps for a\r
+ * pseudo-random period before resending the same sequence.\r
+ *\r
+ * The UART Tx end interrupt is enabled whenever data is available in the Tx\r
+ * queue. The Tx end ISR removes a single character from the Tx queue and\r
+ * passes it to the UART for transmission.\r
+ *\r
+ * The second task blocks on the Rx queue waiting for a character to become\r
+ * available. When the UART Rx end interrupt receives a character it places\r
+ * it in the Rx queue, waking the second task. The second task checks that the\r
+ * characters removed from the Rx queue form the same sequence as those posted\r
+ * to the Tx queue, and toggles an LED for each correct character.\r
+ *\r
+ * The receiving task is spawned with a higher priority than the transmitting\r
+ * task. The receiver will therefore wake every time a character is\r
+ * transmitted so neither the Tx or Rx queue should ever hold more than a few\r
+ * characters.\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "demo_serial.h"\r
+#include "comtest2.h"\r
+#include "partest.h"\r
+\r
+#define comSTACK_SIZE configMINIMAL_STACK_SIZE\r
+#define comTX_LED_OFFSET ( 0 )\r
+#define comRX_LED_OFFSET ( 1 )\r
+#define comTOTAL_PERMISSIBLE_ERRORS ( 2 )\r
+\r
+/* The Tx task will transmit the sequence of characters at a pseudo random\r
+interval. This is the maximum and minimum block time between sends. */\r
+#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x96 )\r
+#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0x32 )\r
+#define comOFFSET_TIME ( ( portTickType ) 3 )\r
+\r
+/* We should find that each character can be queued for Tx immediately and we\r
+don't have to block to send. */\r
+#define comNO_BLOCK ( ( portTickType ) 0 )\r
+\r
+/* The Rx task will block on the Rx queue for a long period. */\r
+#define comRX_BLOCK_TIME ( ( portTickType ) 0xffff )\r
+\r
+/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */\r
+#define comFIRST_BYTE ( 'A' )\r
+#define comLAST_BYTE ( 'X' )\r
+\r
+#define comBUFFER_LEN ( ( unsigned portBASE_TYPE ) ( comLAST_BYTE - comFIRST_BYTE ) + ( unsigned portBASE_TYPE ) 1 )\r
+#define comINITIAL_RX_COUNT_VALUE ( 0 )\r
+\r
+/* Handle to the com port used by both tasks. */\r
+static xComPortHandle xPort = NULL;\r
+\r
+/* The transmit task as described at the top of the file. */\r
+static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters );\r
+\r
+/* The receive task as described at the top of the file. */\r
+static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters );\r
+\r
+/* The LED that should be toggled by the Rx and Tx tasks. The Rx task will\r
+toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED\r
+( uxBaseLED + comTX_LED_OFFSET ). */\r
+static unsigned portBASE_TYPE uxBaseLED = 0;\r
+\r
+/* Check variable used to ensure no error have occurred. The Rx task will\r
+increment this variable after every successfully received sequence. If at any\r
+time the sequence is incorrect the the variable will stop being incremented. */\r
+static volatile unsigned portBASE_TYPE uxRxLoops = comINITIAL_RX_COUNT_VALUE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned long ulBaudRate, unsigned portBASE_TYPE uxLED )\r
+{\r
+ /* Initialise the com port then spawn the Rx and Tx tasks. */\r
+ uxBaseLED = uxLED;\r
+ xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN );\r
+\r
+ /* The Tx task is spawned with a lower priority than the Rx task. */\r
+ xTaskCreate( vComTxTask, ( signed char * ) "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( vComRxTask, ( signed char * ) "COMRx", comSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vComTxTask, pvParameters )\r
+{\r
+signed char cByteToSend;\r
+portTickType xTimeToWait;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Simply transmit a sequence of characters from comFIRST_BYTE to\r
+ comLAST_BYTE. */\r
+ for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ )\r
+ {\r
+ if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS )\r
+ {\r
+ vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET );\r
+ }\r
+ }\r
+\r
+ /* Turn the LED off while we are not doing anything. */\r
+ vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE );\r
+\r
+ /* We have posted all the characters in the string - wait before\r
+ re-sending. Wait a pseudo-random time as this will provide a better\r
+ test. */\r
+ xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME;\r
+\r
+ /* Make sure we don't wait too long... */\r
+ xTimeToWait %= comTX_MAX_BLOCK_TIME;\r
+\r
+ /* ...but we do want to wait. */\r
+ if( xTimeToWait < comTX_MIN_BLOCK_TIME )\r
+ {\r
+ xTimeToWait = comTX_MIN_BLOCK_TIME;\r
+ }\r
+\r
+ vTaskDelay( xTimeToWait );\r
+ }\r
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vComRxTask, pvParameters )\r
+{\r
+signed char cExpectedByte, cByteRxed;\r
+portBASE_TYPE xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* We expect to receive the characters from comFIRST_BYTE to\r
+ comLAST_BYTE in an incrementing order. Loop to receive each byte. */\r
+ for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ )\r
+ {\r
+ /* Block on the queue that contains received bytes until a byte is\r
+ available. */\r
+ if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) )\r
+ {\r
+ /* Was this the byte we were expecting? If so, toggle the LED,\r
+ otherwise we are out on sync and should break out of the loop\r
+ until the expected character sequence is about to restart. */\r
+ if( cByteRxed == cExpectedByte )\r
+ {\r
+ vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET );\r
+ }\r
+ else\r
+ {\r
+ xResyncRequired = pdTRUE;\r
+ break; /*lint !e960 Non-switch break allowed. */\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Turn the LED off while we are not doing anything. */\r
+ vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE );\r
+\r
+ /* Did we break out of the loop because the characters were received in\r
+ an unexpected order? If so wait here until the character sequence is\r
+ about to restart. */\r
+ if( xResyncRequired == pdTRUE )\r
+ {\r
+ while( cByteRxed != comLAST_BYTE )\r
+ {\r
+ /* Block until the next char is available. */\r
+ xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME );\r
+ }\r
+\r
+ /* Note that an error occurred which caused us to have to resync.\r
+ We use this to stop incrementing the loop counter so\r
+ sAreComTestTasksStillRunning() will return false - indicating an\r
+ error. */\r
+ xErrorOccurred++;\r
+\r
+ /* We have now resynced with the Tx task and can continue. */\r
+ xResyncRequired = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS )\r
+ {\r
+ /* Increment the count of successful loops. As error\r
+ occurring (i.e. an unexpected character being received) will\r
+ prevent this counter being incremented for the rest of the\r
+ execution. Don't worry about mutual exclusion on this\r
+ variable - it doesn't really matter as we just want it\r
+ to change. */\r
+ uxRxLoops++;\r
+ }\r
+ }\r
+ }\r
+} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xAreComTestTasksStillRunning( void )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ /* If the count of successful reception loops has not changed than at\r
+ some time an error occurred (i.e. a character was received out of sequence)\r
+ and we will return false. */\r
+ if( uxRxLoops == comINITIAL_RX_COUNT_VALUE )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ /* Reset the count of successful Rx loops. When this function is called\r
+ again we expect this to have been incremented. */\r
+ uxRxLoops = comINITIAL_RX_COUNT_VALUE;\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef SERIAL_COMMS_H\r
+#define SERIAL_COMMS_H\r
+\r
+typedef void * xComPortHandle;\r
+\r
+typedef enum\r
+{ \r
+ serCOM1, \r
+ serCOM2, \r
+ serCOM3, \r
+ serCOM4, \r
+ serCOM5, \r
+ serCOM6, \r
+ serCOM7, \r
+ serCOM8 \r
+} eCOMPort;\r
+\r
+typedef enum \r
+{ \r
+ serNO_PARITY, \r
+ serODD_PARITY, \r
+ serEVEN_PARITY, \r
+ serMARK_PARITY, \r
+ serSPACE_PARITY \r
+} eParity;\r
+\r
+typedef enum \r
+{ \r
+ serSTOP_1, \r
+ serSTOP_2 \r
+} eStopBits;\r
+\r
+typedef enum \r
+{ \r
+ serBITS_5, \r
+ serBITS_6, \r
+ serBITS_7, \r
+ serBITS_8 \r
+} eDataBits;\r
+\r
+typedef enum \r
+{ \r
+ ser50, \r
+ ser75, \r
+ ser110, \r
+ ser134, \r
+ ser150, \r
+ ser200,\r
+ ser300, \r
+ ser600, \r
+ ser1200, \r
+ ser1800, \r
+ ser2400, \r
+ ser4800,\r
+ ser9600, \r
+ ser19200, \r
+ ser38400, \r
+ ser57600, \r
+ ser115200\r
+} eBaud;\r
+\r
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength );\r
+xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength );\r
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength );\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime );\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime );\r
+portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort );\r
+void vSerialClose( xComPortHandle xPort );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, training, latest information,\r
+ license and contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
+ the code with commercial support, indemnification, and middleware, under\r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under\r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*\r
+ * The following #error directive is to remind users that a batch file must be\r
+ * executed prior to this project being built. Once it has been executed\r
+ * remove the #error line below.\r
+ */\r
+#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+extern uint32_t SystemCoreClock;\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 4 /* 15 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x0f\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 10\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, training, latest information,\r
+ license and contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
+ the code with commercial support, indemnification, and middleware, under\r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under\r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include <board.h>\r
+#include <gpio.h>\r
+\r
+/* The number of LEDs available to the user on the evaluation kit. */\r
+#define partestNUM_LEDS ( 3UL )\r
+\r
+/* One of the LEDs is wired in the inverse to the others as it is also used as\r
+the power LED. */\r
+#define partstsINVERTED_LED ( 0UL )\r
+\r
+/* The index of the pins to which the LEDs are connected. The ordering of the\r
+LEDs in this array is intentional and matches the order they appear on the\r
+hardware. */\r
+static const uint32_t ulLED[] = { LED2_GPIO, LED0_GPIO, LED1_GPIO };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+unsigned long ul;\r
+\r
+ for( ul = 0; ul < partestNUM_LEDS; ul++ )\r
+ {\r
+ /* Configure the LED, before ensuring it starts in the off state. */\r
+ gpio_configure_pin( ulLED[ ul ], ( PIO_OUTPUT_1 | PIO_DEFAULT ) );\r
+ vParTestSetLED( ul, pdFALSE );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( uxLED < partestNUM_LEDS )\r
+ {\r
+ if( uxLED == partstsINVERTED_LED )\r
+ {\r
+ xValue = !xValue;\r
+ }\r
+\r
+ if( xValue != pdFALSE )\r
+ {\r
+ /* Turn the LED on. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ gpio_set_pin_low( ulLED[ uxLED ]);\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ /* Turn the LED off. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ gpio_set_pin_high( ulLED[ uxLED ]);\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < partestNUM_LEDS )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ gpio_toggle_pin( ulLED[ uxLED ] );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Autogenerated API include file for the Atmel Software Framework (ASF)\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef ASF_H\r
+#define ASF_H\r
+\r
+/*\r
+ * This file includes all API header files for the selected drivers from ASF.\r
+ * Note: There might be duplicate includes required by more than one driver.\r
+ *\r
+ * The file is automatically generated and will be re-written when\r
+ * running the ASF driver selector tool. Any changes will be discarded.\r
+ */\r
+\r
+// From module: Common SAM compiler driver\r
+#include <compiler.h>\r
+#include <status_codes.h>\r
+\r
+// From module: GPIO - General purpose Input/Output\r
+#include <gpio.h>\r
+\r
+// From module: Generic board support\r
+#include <board.h>\r
+\r
+// From module: Interrupt management - SAM3 implementation\r
+#include <interrupt.h>\r
+\r
+// From module: PIO - Parallel Input/Output Controller\r
+#include <pio.h>\r
+\r
+// From module: PMC - Power Management Controller\r
+#include <pmc.h>\r
+#include <sleep.h>\r
+\r
+// From module: Part identification macros\r
+#include <parts.h>\r
+\r
+// From module: System Clock Control - SAM3X/A implementation\r
+#include <sysclk.h>\r
+\r
+// From module: USART - Univ. Syn Async Rec/Trans\r
+#include <usart.h>\r
+\r
+// From module: pio_handler support enabled\r
+#include <pio_handler.h>\r
+\r
+#endif // ASF_H\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Standard board header file.\r
+ *\r
+ * This file includes the appropriate board header file according to the\r
+ * defined board (parameter BOARD).\r
+ *\r
+ * Copyright (c) 2009-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _BOARD_H_\r
+#define _BOARD_H_\r
+\r
+/**\r
+ * \defgroup group_common_boards Generic board support\r
+ *\r
+ * The generic board support module includes board-specific definitions\r
+ * and function prototypes, such as the board initialization function.\r
+ *\r
+ * \{\r
+ */\r
+\r
+#include "compiler.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/*! \name Base Boards\r
+ */\r
+//! @{\r
+#define EVK1100 1 //!< AT32UC3A EVK1100 board.\r
+#define EVK1101 2 //!< AT32UC3B EVK1101 board.\r
+#define UC3C_EK 3 //!< AT32UC3C UC3C_EK board.\r
+#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.\r
+#define EVK1105 5 //!< AT32UC3A EVK1105 board.\r
+#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.\r
+#define UC3L_EK 7 //!< AT32UC3L-EK board.\r
+#define XPLAIN 8 //!< ATxmega128A1 Xplain board.\r
+#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.\r
+#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.\r
+#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.\r
+#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.\r
+#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.\r
+#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.\r
+#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.\r
+#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.\r
+#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board\r
+#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board\r
+#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board\r
+#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.\r
+#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.\r
+#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.\r
+#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.\r
+#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.\r
+#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.\r
+#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards\r
+#define RZ600 31 //!< AT32UC3A RZ600 MCU board\r
+#define SAM3S_EK 32 //!< SAM3S-EK board.\r
+#define SAM3U_EK 33 //!< SAM3U-EK board.\r
+#define SAM3X_EK 34 //!< SAM3X-EK board.\r
+#define SAM3N_EK 35 //!< SAM3N-EK board.\r
+#define SAM3S_EK2 36 //!< SAM3S-EK2 board.\r
+#define SAM4S_EK 37 //!< SAM4S-EK board.\r
+#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.\r
+#define STK600_MEGA 39 //!< STK600 MEGA board.\r
+#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.\r
+#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.\r
+#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.\r
+#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.\r
+#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board\r
+#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices\r
+#define AVR_SIMULATOR_UC3 98 //!< AVR SIMULATOR for AVR UC3 device family.\r
+#define USER_BOARD 99 //!< User-reserved board (if any).\r
+#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader)\r
+//! @}\r
+\r
+/*! \name Extension Boards\r
+ */\r
+//! @{\r
+#define EXT1102 1 //!< AT32UC3B EXT1102 board\r
+#define MC300 2 //!< AT32UC3 MC300 board\r
+#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1\r
+#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2\r
+#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board\r
+#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board\r
+#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"\r
+#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600\r
+#define RZ600_AT86RF230B 9 //!< AT86RF231 RF board in RZ600\r
+#define RZ600_AT86RF212 10 //!< AT86RF231 RF board in RZ600\r
+#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard\r
+#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board\r
+#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).\r
+//! @}\r
+\r
+#if BOARD == EVK1100\r
+# include "evk1100/evk1100.h"\r
+#elif BOARD == EVK1101\r
+# include "evk1101/evk1101.h"\r
+#elif BOARD == UC3C_EK\r
+# include "uc3c_ek/uc3c_ek.h"\r
+#elif BOARD == EVK1104\r
+# include "evk1104/evk1104.h"\r
+#elif BOARD == EVK1105\r
+# include "evk1105/evk1105.h"\r
+#elif BOARD == STK600_RCUC3L0\r
+# include "stk600/rcuc3l0/stk600_rcuc3l0.h"\r
+#elif BOARD == UC3L_EK\r
+# include "uc3l_ek/uc3l_ek.h"\r
+#elif BOARD == STK600_RCUC3L4\r
+# include "stk600/rcuc3l4/stk600_rcuc3l4.h"\r
+#elif BOARD == XPLAIN\r
+# include "xplain/xplain.h"\r
+#elif BOARD == STK600_MEGA\r
+ /*No header-file to include*/\r
+#elif BOARD == STK600_RC044X\r
+# include "stk600/rc044x/stk600_rc044x.h"\r
+#elif BOARD == STK600_RC064X\r
+# include "stk600/rc064x/stk600_rc064x.h"\r
+#elif BOARD == STK600_RC100X\r
+# include "stk600/rc100x/stk600_rc100x.h"\r
+#elif BOARD == UC3_A3_XPLAINED\r
+# include "uc3_a3_xplained/uc3_a3_xplained.h"\r
+#elif BOARD == UC3_L0_XPLAINED\r
+# include "uc3_l0_xplained/uc3_l0_xplained.h"\r
+#elif BOARD == STK600_RCUC3B0\r
+# include "stk600/rcuc3b0/stk600_rcuc3b0.h"\r
+#elif BOARD == STK600_RCUC3D\r
+# include "stk600/rcuc3d/stk600_rcuc3d.h"\r
+#elif BOARD == STK600_RCUC3C0\r
+# include "stk600/rcuc3c0/stk600_rcuc3c0.h"\r
+#elif BOARD == XMEGA_B1_XPLAINED\r
+# include "xmega_b1_xplained/xmega_b1_xplained.h"\r
+#elif BOARD == STK600_RC064X_LCDX\r
+# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"\r
+#elif BOARD == STK600_RC100X_LCDX\r
+# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"\r
+#elif BOARD == XMEGA_A1_XPLAINED\r
+# include "xmega_a1_xplained/xmega_a1_xplained.h"\r
+#elif BOARD == UC3_L0_XPLAINED_BC\r
+# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"\r
+#elif BOARD == SAM3S_EK\r
+# include "sam3s_ek/sam3s_ek.h"\r
+# include "system_sam3s.h"\r
+#elif BOARD == SAM3S_EK2\r
+# include "sam3s_ek2/sam3s_ek2.h"\r
+# include "system_sam3sd8.h"\r
+#elif BOARD == SAM3U_EK\r
+# include "sam3u_ek/sam3u_ek.h"\r
+# include "system_sam3u.h"\r
+#elif BOARD == SAM3X_EK\r
+# include "sam3x_ek/sam3x_ek.h"\r
+# include "system_sam3x.h"\r
+#elif BOARD == SAM3N_EK\r
+# include "sam3n_ek/sam3n_ek.h"\r
+# include "system_sam3n.h"\r
+#elif BOARD == SAM4S_EK\r
+# include "sam4s_ek/sam4s_ek.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == SAM4S_XPLAINED\r
+# include "sam4s_xplained/sam4s_xplained.h"\r
+# include "system_sam4s.h"\r
+#elif BOARD == MEGA_1284P_XPLAINED\r
+ /*No header-file to include*/\r
+#elif BOARD == ARDUINO_DUE_X\r
+# include "arduino_due_x/arduino_due_x.h"\r
+# include "system_sam3x.h"\r
+#elif BOARD == MEGA1284P_XPLAINED_BC\r
+# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"\r
+#elif BOARD == UC3_L0_QT600\r
+# include "uc3_l0_qt600/uc3_l0_qt600.h"\r
+#elif BOARD == XMEGA_A3BU_XPLAINED\r
+# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"\r
+#elif BOARD == UC3B_BOARD_CONTROLLER\r
+# include "uc3b_board_controller/uc3b_board_controller.h"\r
+#elif BOARD == RZ600\r
+# include "rz600/rz600.h"\r
+#elif BOARD == STK600_RCUC3A0\r
+# include "stk600/rcuc3a0/stk600_rcuc3a0.h"\r
+#elif BOARD == ATXMEGA128A1_QT600\r
+# include "atxmega128a1_qt600/atxmega128a1_qt600.h"\r
+#elif BOARD == STK600_RCUC3L3\r
+ #include "stk600/rcuc3l3/stk600_rcuc3l3.h"\r
+#elif BOARD == SIMULATOR_XMEGA_A1\r
+# include "simulator/xmega_a1/simulator_xmega_a1.h"\r
+#elif BOARD == AVR_SIMULATOR_UC3\r
+# include "avr_simulator_uc3/avr_simulator_uc3.h"\r
+#elif BOARD == USER_BOARD\r
+ // User-reserved area: #include the header file of your board here (if any).\r
+# include "user_board.h"\r
+#elif BOARD == DUMMY_BOARD\r
+# include "dummy/dummy_board.h"\r
+#else\r
+# error No known AVR board defined\r
+#endif\r
+\r
+#if (defined EXT_BOARD)\r
+# if EXT_BOARD == MC300\r
+# include "mc300/mc300.h"\r
+# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)\r
+# include "sensors_xplained/sensors_xplained.h"\r
+# elif EXT_BOARD == RZ600_AT86RF231\r
+# include "at86rf231/at86rf231.h"\r
+# elif EXT_BOARD == RZ600_AT86RF230B\r
+# include "at86rf230b/at86rf230b.h"\r
+# elif EXT_BOARD == RZ600_AT86RF212\r
+# include "at86rf212/at86rf212.h"\r
+# elif EXT_BOARD == SECURITY_XPLAINED\r
+# include "security_xplained.h"\r
+# elif EXT_BOARD == USER_EXT_BOARD\r
+ // User-reserved area: #include the header file of your extension board here\r
+ // (if any).\r
+# endif\r
+#endif\r
+\r
+\r
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+/*! \brief This function initializes the board target resources\r
+ *\r
+ * This function should be called to ensure proper initialization of the target\r
+ * board hardware connected to the part.\r
+ */\r
+extern void board_init(void);\r
+\r
+#endif // #ifdef __AVR32_ABI_COMPILER__\r
+#else\r
+/*! \brief This function initializes the board target resources\r
+ *\r
+ * This function should be called to ensure proper initialization of the target\r
+ * board hardware connected to the part.\r
+ */\r
+extern void board_init(void);\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _BOARD_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Generic clock management\r
+ *\r
+ * Copyright (c) 2010-2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef CLK_GENCLK_H_INCLUDED\r
+#define CLK_GENCLK_H_INCLUDED\r
+\r
+#include "parts.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/genclk.h"\r
+#elif SAM3U\r
+# include "sam3u/genclk.h"\r
+#elif SAM3N\r
+# include "sam3n/genclk.h"\r
+#elif SAM3XA\r
+# include "sam3x/genclk.h"\r
+#elif SAM4S\r
+# include "sam4s/genclk.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/genclk.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/genclk.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/genclk.h"\r
+#elif UC3C\r
+# include "uc3c/genclk.h"\r
+#elif UC3D\r
+# include "uc3d/genclk.h"\r
+#elif UC3L\r
+# include "uc3l/genclk.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup genclk_group Generic Clock Management\r
+ *\r
+ * Generic clocks are configurable clocks which run outside the system\r
+ * clock domain. They are often connected to peripherals which have an\r
+ * asynchronous component running independently of the bus clock, e.g.\r
+ * USB controllers, low-power timers and RTCs, etc.\r
+ *\r
+ * Note that not all platforms have support for generic clocks; on such\r
+ * platforms, this API will not be available.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \def GENCLK_DIV_MAX\r
+ * \brief Maximum divider supported by the generic clock implementation\r
+ */\r
+/**\r
+ * \enum genclk_source\r
+ * \brief Generic clock source ID\r
+ *\r
+ * Each generic clock may be generated from a different clock source.\r
+ * These are the available alternatives provided by the chip.\r
+ */\r
+\r
+//! \name Generic clock configuration\r
+//@{\r
+/**\r
+ * \struct genclk_config\r
+ * \brief Hardware representation of a set of generic clock parameters\r
+ */\r
+/**\r
+ * \fn void genclk_config_defaults(struct genclk_config *cfg,\r
+ * unsigned int id)\r
+ * \brief Initialize \a cfg to the default configuration for the clock\r
+ * identified by \a id.\r
+ */\r
+/**\r
+ * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id)\r
+ * \brief Read the currently active configuration of the clock\r
+ * identified by \a id into \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_config_write(const struct genclk_config *cfg,\r
+ * unsigned int id)\r
+ * \brief Activate the configuration \a cfg on the clock identified by\r
+ * \a id.\r
+ */\r
+/**\r
+ * \fn void genclk_config_set_source(struct genclk_config *cfg,\r
+ * enum genclk_source src)\r
+ * \brief Select a new source clock \a src in configuration \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_config_set_divider(struct genclk_config *cfg,\r
+ * unsigned int divider)\r
+ * \brief Set a new \a divider in configuration \a cfg.\r
+ */\r
+/**\r
+ * \fn void genclk_enable_source(enum genclk_source src)\r
+ * \brief Enable the source clock \a src used by a generic clock.\r
+ */\r
+ //@}\r
+\r
+//! \name Enabling and disabling Generic Clocks\r
+//@{\r
+/**\r
+ * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id)\r
+ * \brief Activate the configuration \a cfg on the clock identified by\r
+ * \a id and enable it.\r
+ */\r
+/**\r
+ * \fn void genclk_disable(unsigned int id)\r
+ * \brief Disable the generic clock identified by \a id.\r
+ */\r
+//@}\r
+\r
+/**\r
+ * \brief Enable the configuration defined by \a src and \a divider\r
+ * for the generic clock identified by \a id.\r
+ *\r
+ * \param id The ID of the generic clock.\r
+ * \param src The source clock of the generic clock.\r
+ * \param divider The divider used to generate the generic clock.\r
+ */\r
+static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider)\r
+{\r
+ struct genclk_config gcfg;\r
+\r
+ genclk_config_defaults(&gcfg, id);\r
+ genclk_enable_source(src);\r
+ genclk_config_set_source(&gcfg, src);\r
+ genclk_config_set_divider(&gcfg, divider);\r
+ genclk_enable(&gcfg, id);\r
+}\r
+\r
+//! @}\r
+\r
+#endif /* CLK_GENCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Oscillator management\r
+ *\r
+ * Copyright (c) 2010 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef OSC_H_INCLUDED\r
+#define OSC_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/osc.h"\r
+#elif SAM3XA\r
+# include "sam3x/osc.h"\r
+#elif SAM3U\r
+# include "sam3u/osc.h"\r
+#elif SAM3N\r
+# include "sam3n/osc.h"\r
+#elif SAM4S\r
+# include "sam4s/osc.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/osc.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/osc.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/osc.h"\r
+#elif UC3C\r
+# include "uc3c/osc.h"\r
+#elif UC3D\r
+# include "uc3d/osc.h"\r
+#elif UC3L\r
+# include "uc3l/osc.h"\r
+#elif XMEGA\r
+# include "xmega/osc.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup osc_group Oscillator Management\r
+ *\r
+ * This group contains functions and definitions related to configuring\r
+ * and enabling/disabling on-chip oscillators. Internal RC-oscillators,\r
+ * external crystal oscillators and external clock generators are\r
+ * supported by this module. What all of these have in common is that\r
+ * they swing at a fixed, nominal frequency which is normally not\r
+ * adjustable.\r
+ *\r
+ * \par Example: Enabling an oscillator\r
+ *\r
+ * The following example demonstrates how to enable the external\r
+ * oscillator on XMEGA A and wait for it to be ready to use. The\r
+ * oscillator identifiers are platform-specific, so while the same\r
+ * procedure is used on all platforms, the parameter to osc_enable()\r
+ * will be different from device to device.\r
+ * \code\r
+ osc_enable(OSC_ID_XOSC);\r
+ osc_wait_ready(OSC_ID_XOSC); \endcode\r
+ *\r
+ * \section osc_group_board Board-specific Definitions\r
+ * If external oscillators are used, the board code must provide the\r
+ * following definitions for each of those:\r
+ * - \b BOARD_<osc name>_HZ: The nominal frequency of the oscillator.\r
+ * - \b BOARD_<osc name>_STARTUP_US: The startup time of the\r
+ * oscillator in microseconds.\r
+ * - \b BOARD_<osc name>_TYPE: The type of oscillator connected, i.e.\r
+ * whether it's a crystal or external clock, and sometimes what kind\r
+ * of crystal it is. The meaning of this value is platform-specific.\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name Oscillator Management\r
+//@{\r
+/**\r
+ * \fn void osc_enable(uint8_t id)\r
+ * \brief Enable oscillator \a id\r
+ *\r
+ * The startup time and mode value is automatically determined based on\r
+ * definitions in the board code.\r
+ */\r
+/**\r
+ * \fn void osc_disable(uint8_t id)\r
+ * \brief Disable oscillator \a id\r
+ */\r
+/**\r
+ * \fn osc_is_ready(uint8_t id)\r
+ * \brief Determine whether oscillator \a id is ready.\r
+ * \retval true Oscillator \a id is running and ready to use as a clock\r
+ * source.\r
+ * \retval false Oscillator \a id is not running.\r
+ */\r
+/**\r
+ * \fn uint32_t osc_get_rate(uint8_t id)\r
+ * \brief Return the frequency of oscillator \a id in Hz\r
+ */\r
+\r
+#ifndef __ASSEMBLY__\r
+\r
+/**\r
+ * \brief Wait until the oscillator identified by \a id is ready\r
+ *\r
+ * This function will busy-wait for the oscillator identified by \a id\r
+ * to become stable and ready to use as a clock source.\r
+ *\r
+ * \param id A number identifying the oscillator to wait for.\r
+ */\r
+static inline void osc_wait_ready(uint8_t id)\r
+{\r
+ while (!osc_is_ready(id)) {\r
+ /* Do nothing */\r
+ }\r
+}\r
+\r
+#endif /* __ASSEMBLY__ */\r
+\r
+//@}\r
+\r
+//! @}\r
+\r
+#endif /* OSC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief PLL management\r
+ *\r
+ * Copyright (c) 2010-2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef CLK_PLL_H_INCLUDED\r
+#define CLK_PLL_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/pll.h"\r
+#elif SAM3XA\r
+# include "sam3x/pll.h"\r
+#elif SAM3U\r
+# include "sam3u/pll.h"\r
+#elif SAM3N\r
+# include "sam3n/pll.h"\r
+#elif SAM4S\r
+# include "sam4s/pll.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/pll.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/pll.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/pll.h"\r
+#elif UC3C\r
+# include "uc3c/pll.h"\r
+#elif UC3D\r
+# include "uc3d/pll.h"\r
+#elif (UC3L0128 || UC3L0256 || UC3L3_L4)\r
+# include "uc3l/pll.h"\r
+#elif XMEGA\r
+# include "xmega/pll.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup pll_group PLL Management\r
+ *\r
+ * This group contains functions and definitions related to configuring\r
+ * and enabling/disabling on-chip PLLs. A PLL will take an input signal\r
+ * (the \em source), optionally divide the frequency by a configurable\r
+ * \em divider, and then multiply the frequency by a configurable \em\r
+ * multiplier.\r
+ *\r
+ * Some devices don't support input dividers; specifying any other\r
+ * divisor than 1 on these devices will result in an assertion failure.\r
+ * Other devices may have various restrictions to the frequency range of\r
+ * the input and output signals.\r
+ *\r
+ * \par Example: Setting up PLL0 with default parameters\r
+ *\r
+ * The following example shows how to configure and enable PLL0 using\r
+ * the default parameters specified using the configuration symbols\r
+ * listed above.\r
+ * \code\r
+ pll_enable_config_defaults(0); \endcode\r
+ *\r
+ * To configure, enable PLL0 using the default parameters and to disable\r
+ * a specific feature like Wide Bandwidth Mode (a UC3A3-specific\r
+ * PLL option.), you can use this initialization process.\r
+ * \code\r
+ struct pll_config pllcfg;\r
+ if (pll_is_locked(pll_id)) {\r
+ return; // Pll already running\r
+ }\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0); \endcode\r
+ *\r
+ * When the last function call returns, PLL0 is ready to be used as the\r
+ * main system clock source.\r
+ *\r
+ * \section pll_group_config Configuration Symbols\r
+ *\r
+ * Each PLL has a set of default parameters determined by the following\r
+ * configuration symbols in the application's configuration file:\r
+ * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the\r
+ * input of PLL \a n. Must be one of the values defined by the\r
+ * #pll_source enum.\r
+ * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL\r
+ * \a n.\r
+ * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n.\r
+ *\r
+ * These configuration symbols determine the result of calling\r
+ * pll_config_defaults() and pll_get_default_rate().\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name Chip-specific PLL characteristics\r
+//@{\r
+/**\r
+ * \def PLL_MAX_STARTUP_CYCLES\r
+ * \brief Maximum PLL startup time in number of slow clock cycles\r
+ */\r
+/**\r
+ * \def NR_PLLS\r
+ * \brief Number of on-chip PLLs\r
+ */\r
+\r
+/**\r
+ * \def PLL_MIN_HZ\r
+ * \brief Minimum frequency that the PLL can generate\r
+ */\r
+/**\r
+ * \def PLL_MAX_HZ\r
+ * \brief Maximum frequency that the PLL can generate\r
+ */\r
+/**\r
+ * \def PLL_NR_OPTIONS\r
+ * \brief Number of PLL option bits\r
+ */\r
+//@}\r
+\r
+/**\r
+ * \enum pll_source\r
+ * \brief PLL clock source\r
+ */\r
+\r
+//! \name PLL configuration\r
+//@{\r
+\r
+/**\r
+ * \struct pll_config\r
+ * \brief Hardware-specific representation of PLL configuration.\r
+ *\r
+ * This structure contains one or more device-specific values\r
+ * representing the current PLL configuration. The contents of this\r
+ * structure is typically different from platform to platform, and the\r
+ * user should not access any fields except through the PLL\r
+ * configuration API.\r
+ */\r
+\r
+/**\r
+ * \fn void pll_config_init(struct pll_config *cfg,\r
+ * enum pll_source src, unsigned int div, unsigned int mul)\r
+ * \brief Initialize PLL configuration from standard parameters.\r
+ *\r
+ * \note This function may be defined inline because it is assumed to be\r
+ * called very few times, and usually with constant parameters. Inlining\r
+ * it will in such cases reduce the code size significantly.\r
+ *\r
+ * \param cfg The PLL configuration to be initialized.\r
+ * \param src The oscillator to be used as input to the PLL.\r
+ * \param div PLL input divider.\r
+ * \param mul PLL loop divider (i.e. multiplier).\r
+ *\r
+ * \return A configuration which will make the PLL run at\r
+ * (\a mul / \a div) times the frequency of \a src\r
+ */\r
+/**\r
+ * \def pll_config_defaults(cfg, pll_id)\r
+ * \brief Initialize PLL configuration using default parameters.\r
+ *\r
+ * After this function returns, \a cfg will contain a configuration\r
+ * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV)\r
+ * times the frequency of CONFIG_PLLx_SOURCE.\r
+ *\r
+ * \param cfg The PLL configuration to be initialized.\r
+ * \param pll_id Use defaults for this PLL.\r
+ */\r
+/**\r
+ * \def pll_get_default_rate(pll_id)\r
+ * \brief Get the default rate in Hz of \a pll_id\r
+ */\r
+/**\r
+ * \fn void pll_config_set_option(struct pll_config *cfg,\r
+ * unsigned int option)\r
+ * \brief Set the PLL option bit \a option in the configuration \a cfg.\r
+ *\r
+ * \param cfg The PLL configuration to be changed.\r
+ * \param option The PLL option bit to be set.\r
+ */\r
+/**\r
+ * \fn void pll_config_clear_option(struct pll_config *cfg,\r
+ * unsigned int option)\r
+ * \brief Clear the PLL option bit \a option in the configuration \a cfg.\r
+ *\r
+ * \param cfg The PLL configuration to be changed.\r
+ * \param option The PLL option bit to be cleared.\r
+ */\r
+/**\r
+ * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id)\r
+ * \brief Read the currently active configuration of \a pll_id.\r
+ *\r
+ * \param cfg The configuration object into which to store the currently\r
+ * active configuration.\r
+ * \param pll_id The ID of the PLL to be accessed.\r
+ */\r
+/**\r
+ * \fn void pll_config_write(const struct pll_config *cfg,\r
+ * unsigned int pll_id)\r
+ * \brief Activate the configuration \a cfg on \a pll_id\r
+ *\r
+ * \param cfg The configuration object representing the PLL\r
+ * configuration to be activated.\r
+ * \param pll_id The ID of the PLL to be updated.\r
+ */\r
+\r
+//@}\r
+\r
+//! \name Interaction with the PLL hardware\r
+//@{\r
+/**\r
+ * \fn void pll_enable(const struct pll_config *cfg,\r
+ * unsigned int pll_id)\r
+ * \brief Activate the configuration \a cfg and enable PLL \a pll_id.\r
+ *\r
+ * \param cfg The PLL configuration to be activated.\r
+ * \param pll_id The ID of the PLL to be enabled.\r
+ */\r
+/**\r
+ * \fn void pll_disable(unsigned int pll_id)\r
+ * \brief Disable the PLL identified by \a pll_id.\r
+ *\r
+ * After this function is called, the PLL identified by \a pll_id will\r
+ * be disabled. The PLL configuration stored in hardware may be affected\r
+ * by this, so if the caller needs to restore the same configuration\r
+ * later, it should either do a pll_config_read() before disabling the\r
+ * PLL, or remember the last configuration written to the PLL.\r
+ *\r
+ * \param pll_id The ID of the PLL to be disabled.\r
+ */\r
+/**\r
+ * \fn bool pll_is_locked(unsigned int pll_id)\r
+ * \brief Determine whether the PLL is locked or not.\r
+ *\r
+ * \param pll_id The ID of the PLL to check.\r
+ *\r
+ * \retval true The PLL is locked and ready to use as a clock source\r
+ * \retval false The PLL is not yet locked, or has not been enabled.\r
+ */\r
+/**\r
+ * \fn void pll_enable_source(enum pll_source src)\r
+ * \brief Enable the source of the pll.\r
+ * The source is enabled, if the source is not already running.\r
+ *\r
+ * \param src The ID of the PLL source to enable.\r
+ */\r
+/**\r
+ * \fn void pll_enable_config_defaults(unsigned int pll_id)\r
+ * \brief Enable the pll with the default configuration.\r
+ * PLL is enabled, if the PLL is not already locked.\r
+ *\r
+ * \param pll_id The ID of the PLL to enable.\r
+ */\r
+\r
+/**\r
+ * \brief Wait for PLL \a pll_id to become locked\r
+ *\r
+ * \todo Use a timeout to avoid waiting forever and hanging the system\r
+ *\r
+ * \param pll_id The ID of the PLL to wait for.\r
+ *\r
+ * \retval STATUS_OK The PLL is now locked.\r
+ * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.\r
+ */\r
+static inline int pll_wait_for_lock(unsigned int pll_id)\r
+{\r
+ Assert(pll_id < NR_PLLS);\r
+\r
+ while (!pll_is_locked(pll_id)) {\r
+ /* Do nothing */\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+//@}\r
+//! @}\r
+\r
+#endif /* CLK_PLL_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific generic clock management.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.s\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_GENCLK_H_INCLUDED\r
+#define CHIP_GENCLK_H_INCLUDED\r
+\r
+#include <osc.h>\r
+#include <pll.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup genclk_group\r
+ * @{\r
+ */\r
+\r
+//! \name Programmable Clock Identifiers (PCK)\r
+//@{\r
+#define GENCLK_PCK_0 0 //!< PCK0 ID\r
+#define GENCLK_PCK_1 1 //!< PCK1 ID\r
+#define GENCLK_PCK_2 2 //!< PCK2 ID\r
+//@}\r
+\r
+//! \name Programmable Clock Sources (PCK)\r
+//@{\r
+\r
+enum genclk_source {\r
+ GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock\r
+ GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock\r
+ GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock\r
+};\r
+\r
+//@}\r
+\r
+//! \name Programmable Clock Prescalers (PCK)\r
+//@{\r
+\r
+enum genclk_divider {\r
+ GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1\r
+ GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2\r
+ GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4\r
+ GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8\r
+ GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16\r
+ GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32\r
+ GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64\r
+};\r
+\r
+//@}\r
+\r
+struct genclk_config {\r
+ uint32_t ctrl;\r
+};\r
+\r
+static inline void genclk_config_defaults(struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ ul_id = ul_id;\r
+ p_cfg->ctrl = 0;\r
+}\r
+\r
+static inline void genclk_config_read(struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ p_cfg->ctrl = PMC->PMC_PCK[ul_id];\r
+}\r
+\r
+static inline void genclk_config_write(const struct genclk_config *p_cfg,\r
+ uint32_t ul_id)\r
+{\r
+ PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
+}\r
+\r
+//! \name Programmable Clock Source and Prescaler configuration\r
+//@{\r
+\r
+static inline void genclk_config_set_source(struct genclk_config *p_cfg,\r
+ enum genclk_source e_src)\r
+{\r
+ p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);\r
+\r
+ switch (e_src) {\r
+ case GENCLK_PCK_SRC_SLCK_RC:\r
+ case GENCLK_PCK_SRC_SLCK_XTAL:\r
+ case GENCLK_PCK_SRC_SLCK_BYPASS:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_SLOW_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
+ case GENCLK_PCK_SRC_MAINCK_XTAL:\r
+ case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_MAIN_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_PLLACK:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_PLLA_CLK);\r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_PLLBCK:\r
+ p_cfg->ctrl |= (PMC_MCKR_CSS_UPLL_CLK);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void genclk_config_set_divider(struct genclk_config *p_cfg,\r
+ uint32_t e_divider)\r
+{\r
+ p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;\r
+ p_cfg->ctrl |= e_divider; \r
+}\r
+\r
+//@}\r
+\r
+static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)\r
+{\r
+ PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
+ pmc_enable_pck(ul_id);\r
+}\r
+\r
+static inline void genclk_disable(uint32_t ul_id)\r
+{\r
+ pmc_disable_pck(ul_id);\r
+}\r
+\r
+static inline void genclk_enable_source(enum genclk_source e_src)\r
+{\r
+ switch (e_src) {\r
+ case GENCLK_PCK_SRC_SLCK_RC:\r
+ if (!osc_is_ready(OSC_SLCK_32K_RC)) {\r
+ osc_enable(OSC_SLCK_32K_RC);\r
+ osc_wait_ready(OSC_SLCK_32K_RC);\r
+ } \r
+ break;\r
+ \r
+ case GENCLK_PCK_SRC_SLCK_XTAL:\r
+ if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {\r
+ osc_enable(OSC_SLCK_32K_XTAL);\r
+ osc_wait_ready(OSC_SLCK_32K_XTAL);\r
+ }\r
+ break;\r
+ \r
+ case GENCLK_PCK_SRC_SLCK_BYPASS:\r
+ if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {\r
+ osc_enable(OSC_SLCK_32K_BYPASS);\r
+ osc_wait_ready(OSC_SLCK_32K_BYPASS); \r
+ } \r
+ break;\r
+ \r
+ case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_4M_RC)) {\r
+ osc_enable(OSC_MAINCK_4M_RC);\r
+ osc_wait_ready(OSC_MAINCK_4M_RC); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_8M_RC)) {\r
+ osc_enable(OSC_MAINCK_8M_RC);\r
+ osc_wait_ready(OSC_MAINCK_8M_RC); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
+ if (!osc_is_ready(OSC_MAINCK_12M_RC)) {\r
+ osc_enable(OSC_MAINCK_12M_RC);\r
+ osc_wait_ready(OSC_MAINCK_12M_RC); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_XTAL:\r
+ if (!osc_is_ready(OSC_MAINCK_XTAL)) {\r
+ osc_enable(OSC_MAINCK_XTAL);\r
+ osc_wait_ready(OSC_MAINCK_XTAL); \r
+ } \r
+ break;\r
+\r
+ case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
+ if (!osc_is_ready(OSC_MAINCK_BYPASS)) {\r
+ osc_enable(OSC_MAINCK_BYPASS);\r
+ osc_wait_ready(OSC_MAINCK_BYPASS); \r
+ } \r
+ break;\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case GENCLK_PCK_SRC_PLLACK:\r
+ pll_enable_config_defaults(0); \r
+ break; \r
+#endif\r
+\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case GENCLK_PCK_SRC_PLLBCK:\r
+ pll_enable_config_defaults(1); \r
+ break; \r
+#endif \r
+\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_GENCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific oscillator management functions.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_OSC_H_INCLUDED\r
+#define CHIP_OSC_H_INCLUDED\r
+\r
+#include "board.h"\r
+#include "pmc.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup osc_group\r
+ * @{\r
+ */\r
+\r
+//! \name Oscillator identifiers\r
+//@{\r
+#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator.\r
+#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator.\r
+#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator.\r
+#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator.\r
+#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator.\r
+#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator.\r
+#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator.\r
+#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator.\r
+//@}\r
+\r
+//! \name Oscillator clock speed in hertz\r
+//@{\r
+#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator.\r
+#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator.\r
+#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator.\r
+#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator.\r
+#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator.\r
+#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator.\r
+#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator.\r
+#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator.\r
+//@}\r
+\r
+static inline void osc_enable(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ break;\r
+\r
+ case OSC_SLCK_32K_XTAL:\r
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ break;\r
+\r
+ case OSC_SLCK_32K_BYPASS:\r
+ pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS);\r
+ break;\r
+\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ break;\r
+\r
+ case OSC_MAINCK_8M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ break;\r
+\r
+ case OSC_MAINCK_12M_RC:\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ break;\r
+\r
+\r
+ case OSC_MAINCK_XTAL:\r
+ pmc_switch_mainck_to_xtal(PMC_OSC_XTAL);\r
+ break;\r
+\r
+ case OSC_MAINCK_BYPASS:\r
+ pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void osc_disable(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ case OSC_SLCK_32K_XTAL:\r
+ case OSC_SLCK_32K_BYPASS:\r
+ break;\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ case OSC_MAINCK_8M_RC:\r
+ case OSC_MAINCK_12M_RC:\r
+ pmc_osc_disable_fastrc();\r
+ break;\r
+\r
+ case OSC_MAINCK_XTAL:\r
+ pmc_osc_disable_xtal(PMC_OSC_XTAL);\r
+ break;\r
+\r
+ case OSC_MAINCK_BYPASS:\r
+ pmc_osc_disable_xtal(PMC_OSC_BYPASS);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline bool osc_is_ready(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ return 1;\r
+\r
+ case OSC_SLCK_32K_XTAL:\r
+ case OSC_SLCK_32K_BYPASS:\r
+ return pmc_osc_is_ready_32kxtal();\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ case OSC_MAINCK_8M_RC:\r
+ case OSC_MAINCK_12M_RC:\r
+ case OSC_MAINCK_XTAL:\r
+ case OSC_MAINCK_BYPASS:\r
+ return pmc_osc_is_ready_mainck();\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+static inline uint32_t osc_get_rate(uint32_t ul_id)\r
+{\r
+ switch (ul_id) {\r
+ case OSC_SLCK_32K_RC:\r
+ return OSC_SLCK_32K_RC_HZ;\r
+\r
+#ifdef BOARD_FREQ_SLCK_XTAL\r
+ case OSC_SLCK_32K_XTAL:\r
+ return BOARD_FREQ_SLCK_XTAL;\r
+#endif\r
+\r
+#ifdef BOARD_FREQ_SLCK_BYPASS\r
+ case OSC_SLCK_32K_BYPASS:\r
+ return BOARD_FREQ_SLCK_BYPASS;\r
+#endif\r
+\r
+ case OSC_MAINCK_4M_RC:\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+\r
+ case OSC_MAINCK_8M_RC:\r
+ return OSC_MAINCK_8M_RC_HZ;\r
+\r
+ case OSC_MAINCK_12M_RC:\r
+ return OSC_MAINCK_12M_RC_HZ;\r
+\r
+#ifdef BOARD_FREQ_MAINCK_XTAL\r
+ case OSC_MAINCK_XTAL:\r
+ return BOARD_FREQ_MAINCK_XTAL;\r
+#endif\r
+\r
+#ifdef BOARD_FREQ_MAINCK_BYPASS\r
+ case OSC_MAINCK_BYPASS:\r
+ return BOARD_FREQ_MAINCK_BYPASS;\r
+#endif\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_OSC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific PLL definitions.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_PLL_H_INCLUDED\r
+#define CHIP_PLL_H_INCLUDED\r
+\r
+#include <osc.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup pll_group\r
+ * @{\r
+ */\r
+\r
+#define PLL_OUTPUT_MIN_HZ 84000000\r
+#define PLL_OUTPUT_MAX_HZ 192000000\r
+\r
+#define PLL_INPUT_MIN_HZ 8000000\r
+#define PLL_INPUT_MAX_HZ 16000000\r
+\r
+#define NR_PLLS 2\r
+#define PLLA_ID 0\r
+#define UPLL_ID 1 //!< USB UTMI PLL.\r
+\r
+#define PLL_UPLL_HZ 480000000\r
+ \r
+#define PLL_COUNT 0x3fU\r
+\r
+enum pll_source {\r
+ PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, //!< Internal 4MHz RC oscillator.\r
+ PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, //!< Internal 8MHz RC oscillator.\r
+ PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, //!< Internal 12MHz RC oscillator.\r
+ PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, //!< External crystal oscillator.\r
+ PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, //!< External bypass oscillator.\r
+ PLL_NR_SOURCES, //!< Number of PLL sources.\r
+};\r
+\r
+struct pll_config {\r
+ uint32_t ctrl;\r
+};\r
+\r
+#define pll_get_default_rate(pll_id) \\r
+ ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \\r
+ * CONFIG_PLL##pll_id##_MUL) \\r
+ / CONFIG_PLL##pll_id##_DIV)\r
+\r
+/* Force UTMI PLL parameters (Hardware defined) */\r
+#ifdef CONFIG_PLL1_SOURCE\r
+# undef CONFIG_PLL1_SOURCE\r
+#endif\r
+#ifdef CONFIG_PLL1_MUL\r
+# undef CONFIG_PLL1_MUL\r
+#endif\r
+#ifdef CONFIG_PLL1_DIV\r
+# undef CONFIG_PLL1_DIV\r
+#endif\r
+#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL\r
+#define CONFIG_PLL1_MUL 0\r
+#define CONFIG_PLL1_DIV 0\r
+\r
+/**\r
+ * \note The SAM3X PLL hardware interprets mul as mul+1. For readability the hardware mul+1\r
+ * is hidden in this implementation. Use mul as mul effective value.\r
+ */\r
+static inline void pll_config_init(struct pll_config *p_cfg,\r
+ enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)\r
+{\r
+ uint32_t vco_hz;\r
+\r
+ Assert(e_src < PLL_NR_SOURCES);\r
+\r
+ if (ul_div == 0 && ul_mul == 0) { /* Must only be true for UTMI PLL */\r
+ p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT);\r
+ } else { /* PLLA */\r
+ /* Calculate internal VCO frequency */\r
+ vco_hz = osc_get_rate(e_src) / ul_div;\r
+ Assert(vco_hz >= PLL_INPUT_MIN_HZ);\r
+ Assert(vco_hz <= PLL_INPUT_MAX_HZ);\r
+ \r
+ vco_hz *= ul_mul;\r
+ Assert(vco_hz >= PLL_OUTPUT_MIN_HZ);\r
+ Assert(vco_hz <= PLL_OUTPUT_MAX_HZ);\r
+ \r
+ /* PMC hardware will automatically make it mul+1 */\r
+ p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_DIVA(ul_div) | CKGR_PLLAR_PLLACOUNT(PLL_COUNT);\r
+ }\r
+}\r
+\r
+#define pll_config_defaults(cfg, pll_id) \\r
+ pll_config_init(cfg, \\r
+ CONFIG_PLL##pll_id##_SOURCE, \\r
+ CONFIG_PLL##pll_id##_DIV, \\r
+ CONFIG_PLL##pll_id##_MUL)\r
+\r
+static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+\r
+ if (ul_pll_id == PLLA_ID)\r
+ p_cfg->ctrl = PMC->CKGR_PLLAR;\r
+ else\r
+ p_cfg->ctrl = PMC->CKGR_UCKR;\r
+}\r
+\r
+static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+ \r
+ if (ul_pll_id == PLLA_ID) {\r
+ pmc_disable_pllack(); // Always stop PLL first!\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;\r
+ } else {\r
+ PMC->CKGR_UCKR = p_cfg->ctrl;\r
+ }\r
+}\r
+\r
+static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+ \r
+ if (ul_pll_id == PLLA_ID) {\r
+ pmc_disable_pllack(); // Always stop PLL first!\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;\r
+ } else {\r
+ PMC->CKGR_UCKR = p_cfg->ctrl | CKGR_UCKR_UPLLEN;\r
+ }\r
+}\r
+\r
+/** \r
+ * \note This will only disable the selected PLL, not the underlying oscillator (mainck).\r
+ */\r
+static inline void pll_disable(uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+\r
+ if (ul_pll_id == PLLA_ID)\r
+ pmc_disable_pllack();\r
+ else\r
+ PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;\r
+}\r
+\r
+static inline uint32_t pll_is_locked(uint32_t ul_pll_id)\r
+{\r
+ Assert(ul_pll_id < NR_PLLS);\r
+ \r
+ if (ul_pll_id == PLLA_ID)\r
+ return pmc_is_locked_pllack();\r
+ else\r
+ return pmc_is_locked_upll();\r
+}\r
+\r
+static inline void pll_enable_source(enum pll_source e_src)\r
+{\r
+ switch (e_src) {\r
+ case PLL_SRC_MAINCK_4M_RC:\r
+ case PLL_SRC_MAINCK_8M_RC:\r
+ case PLL_SRC_MAINCK_12M_RC:\r
+ case PLL_SRC_MAINCK_XTAL:\r
+ case PLL_SRC_MAINCK_BYPASS:\r
+ osc_enable(e_src);\r
+ osc_wait_ready(e_src);\r
+ break;\r
+\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+}\r
+\r
+static inline void pll_enable_config_defaults(unsigned int ul_pll_id)\r
+{\r
+ struct pll_config pllcfg;\r
+\r
+ if (pll_is_locked(ul_pll_id)) {\r
+ return; // Pll already running\r
+ }\r
+ switch (ul_pll_id) {\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case 0:\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_init(&pllcfg,\r
+ CONFIG_PLL0_SOURCE,\r
+ CONFIG_PLL0_DIV,\r
+ CONFIG_PLL0_MUL);\r
+ break;\r
+#endif\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case 1:\r
+ pll_enable_source(CONFIG_PLL1_SOURCE);\r
+ pll_config_init(&pllcfg,\r
+ CONFIG_PLL1_SOURCE,\r
+ CONFIG_PLL1_DIV,\r
+ CONFIG_PLL1_MUL);\r
+ break;\r
+#endif\r
+ default:\r
+ Assert(false);\r
+ break;\r
+ }\r
+ pll_enable(&pllcfg, ul_pll_id);\r
+ while (!pll_is_locked(ul_pll_id));\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_PLL_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific system clock management functions.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include <sysclk.h>\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup sysclk_group\r
+ * @{\r
+ */\r
+\r
+#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+/**\r
+ * \brief boolean signalling that the sysclk_init is done.\r
+ */\r
+uint32_t sysclk_initialized = 0;\r
+#endif\r
+\r
+/**\r
+ * \brief Set system clock prescaler configuration\r
+ *\r
+ * This function will change the system clock prescaler configuration to\r
+ * match the parameters.\r
+ *\r
+ * \note The parameters to this function are device-specific.\r
+ *\r
+ * \param cpu_shift The CPU clock will be divided by \f$2^{mck\_pres}\f$\r
+ */\r
+void sysclk_set_prescalers(uint32_t ul_pres)\r
+{\r
+ pmc_mck_set_prescaler(ul_pres);\r
+ SystemCoreClockUpdate();\r
+}\r
+\r
+/**\r
+ * \brief Change the source of the main system clock.\r
+ *\r
+ * \param src The new system clock source. Must be one of the constants\r
+ * from the <em>System Clock Sources</em> section.\r
+ */\r
+void sysclk_set_source(uint32_t ul_src)\r
+{\r
+ switch (ul_src) {\r
+ case SYSCLK_SRC_SLCK_RC:\r
+ case SYSCLK_SRC_SLCK_XTAL:\r
+ case SYSCLK_SRC_SLCK_BYPASS:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK);\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_4M_RC:\r
+ case SYSCLK_SRC_MAINCK_8M_RC:\r
+ case SYSCLK_SRC_MAINCK_12M_RC:\r
+ case SYSCLK_SRC_MAINCK_XTAL:\r
+ case SYSCLK_SRC_MAINCK_BYPASS:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);\r
+ break;\r
+\r
+ case SYSCLK_SRC_PLLACK:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK);\r
+ break;\r
+\r
+ case SYSCLK_SRC_UPLLCK:\r
+ pmc_mck_set_source(PMC_MCKR_CSS_UPLL_CLK);\r
+ break;\r
+ }\r
+\r
+ SystemCoreClockUpdate();\r
+}\r
+\r
+#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)\r
+/**\r
+ * \brief Enable full speed USB clock.\r
+ *\r
+ * \note The SAM3X UDP hardware interprets div as div+1. For readability the hardware div+1\r
+ * is hidden in this implementation. Use div as div effective value.\r
+ *\r
+ * \param pll_id Source of the USB clock.\r
+ * \param div Actual clock divisor. Must be superior to 0.\r
+ */\r
+void sysclk_enable_usb(void)\r
+{\r
+ Assert(CONFIG_USBCLK_DIV > 0);\r
+\r
+ switch (CONFIG_USBCLK_SOURCE) {\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case USBCLK_SRC_PLL0: {\r
+ struct pll_config pllcfg;\r
+\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0);\r
+ pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1);\r
+ pmc_enable_udpck();\r
+ break;\r
+ }\r
+#endif\r
+\r
+ case USBCLK_SRC_UPLL: {\r
+\r
+ pmc_enable_upll_clock();\r
+ pmc_switch_udpck_to_upllck(CONFIG_USBCLK_DIV - 1);\r
+ pmc_enable_udpck();\r
+ break;\r
+ }\r
+\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable full speed USB clock.\r
+ *\r
+ * \note This implementation does not switch off the PLL, it just turns off the USB clock.\r
+ */\r
+void sysclk_disable_usb(void)\r
+{\r
+ pll_disable(1);\r
+}\r
+#endif // CONFIG_USBCLK_SOURCE\r
+\r
+void sysclk_init(void)\r
+{\r
+ struct pll_config pllcfg;\r
+\r
+ /* Set a flash wait state depending on the new cpu frequency */\r
+ system_init_flash(sysclk_get_cpu_hz());\r
+\r
+ /* Config system clock setting */\r
+ switch (CONFIG_SYSCLK_SOURCE) {\r
+ case SYSCLK_SRC_SLCK_RC:\r
+ osc_enable(OSC_SLCK_32K_RC);\r
+ osc_wait_ready(OSC_SLCK_32K_RC);\r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+ case SYSCLK_SRC_SLCK_XTAL:\r
+ osc_enable(OSC_SLCK_32K_XTAL);\r
+ osc_wait_ready(OSC_SLCK_32K_XTAL);\r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+ case SYSCLK_SRC_SLCK_BYPASS:\r
+ osc_enable(OSC_SLCK_32K_BYPASS);\r
+ osc_wait_ready(OSC_SLCK_32K_BYPASS);\r
+ pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_4M_RC:\r
+ /* Already running from SYSCLK_SRC_MAINCK_4M_RC */\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_8M_RC:\r
+ osc_enable(OSC_MAINCK_8M_RC);\r
+ osc_wait_ready(OSC_MAINCK_8M_RC);\r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_12M_RC:\r
+ osc_enable(OSC_MAINCK_12M_RC);\r
+ osc_wait_ready(OSC_MAINCK_12M_RC);\r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+\r
+ case SYSCLK_SRC_MAINCK_XTAL:\r
+ osc_enable(OSC_MAINCK_XTAL);\r
+ osc_wait_ready(OSC_MAINCK_XTAL);\r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+ case SYSCLK_SRC_MAINCK_BYPASS:\r
+ osc_enable(OSC_MAINCK_BYPASS);\r
+ osc_wait_ready(OSC_MAINCK_BYPASS);\r
+ pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case SYSCLK_SRC_PLLACK:\r
+ pll_enable_source(CONFIG_PLL0_SOURCE);\r
+ pll_config_defaults(&pllcfg, 0);\r
+ pll_enable(&pllcfg, 0);\r
+ pll_wait_for_lock(0);\r
+ pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES);\r
+ break;\r
+#endif\r
+\r
+ case SYSCLK_SRC_UPLLCK:\r
+ pll_enable_source(CONFIG_PLL1_SOURCE);\r
+ pll_config_defaults(&pllcfg, 1);\r
+ pll_enable(&pllcfg, 1);\r
+ pll_wait_for_lock(1);\r
+ pmc_switch_mck_to_upllck(CONFIG_SYSCLK_PRES);\r
+ break;\r
+ }\r
+\r
+ /* Update the SystemFrequency variable */\r
+ SystemCoreClockUpdate();\r
+\r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+ /* Signal that the internal frequencies are setup */\r
+ sysclk_initialized = 1;\r
+#endif\r
+}\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Chip-specific system clock management functions.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CHIP_SYSCLK_H_INCLUDED\r
+#define CHIP_SYSCLK_H_INCLUDED\r
+\r
+#include <osc.h>\r
+#include <pll.h>\r
+\r
+/**\r
+ * \page sysclk_quickstart Quick Start Guide for the System Clock Management service (SAM3A)\r
+ *\r
+ * This is the quick start guide for the \ref sysclk_group "System Clock Management"\r
+ * service, with step-by-step instructions on how to configure and use the service for\r
+ * specific use cases.\r
+ *\r
+ * \section sysclk_quickstart_usecases System Clock Management use cases\r
+ * - \ref sysclk_quickstart_basic\r
+ *\r
+ * \section sysclk_quickstart_basic Basic usage of the System Clock Management service\r
+ * This section will present a basic use case for the System Clock Management service.\r
+ * This use case will configure the main system clock to 84MHz, using an internal PLL\r
+ * module to multiply the frequency of a crystal attached to the microcontroller.\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites\r
+ * - None\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow\r
+ * -# Configure the system clocks according to the settings in conf_clock.h:\r
+ * \code sysclk_init(); \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_example_code Example code\r
+ * Add or uncomment the following in your conf_clock.h header file, commenting out all other\r
+ * definitions of the same symbol(s):\r
+ * \code\r
+ * #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK\r
+ *\r
+ * // Fpll0 = (Fclk * PLL_mul) / PLL_div\r
+ * #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL\r
+ * #define CONFIG_PLL0_MUL (84000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1\r
+ *\r
+ * // Fbus = Fsys / BUS_div\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ * \endcode\r
+ *\r
+ * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow\r
+ * -# Configure the main system clock to use the output of the PLL module as its source:\r
+ * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode\r
+ * -# Configure the PLL module to use the fast external fast crystal oscillator as its source:\r
+ * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode\r
+ * -# Configure the PLL module to multiply the external fast crystal oscillator frequency up to 84MHz:\r
+ * \code\r
+ * #define CONFIG_PLL0_MUL (84000000UL / BOARD_FREQ_MAINCK_XTAL)\r
+ * #define CONFIG_PLL0_DIV 1 \r
+ * \endcode\r
+ * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the board \c conf_board.h configuration\r
+ * file as the frequency of the fast crystal attached to the microcontroller.\r
+ * -# Configure the main clock to run at the full 84MHz, disable scaling of the main system clock speed:\r
+ * \code\r
+ * #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+ * \endcode\r
+ * \note Some dividers are powers of two, while others are integer division factors. Refer to the\r
+ * formulas in the conf_clock.h template commented above each division define.\r
+ */\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \weakgroup sysclk_group\r
+ * @{\r
+ */\r
+ \r
+//! \name Configuration Symbols\r
+//@{\r
+/**\r
+ * \def CONFIG_SYSCLK_SOURCE\r
+ * \brief Initial/static main system clock source\r
+ *\r
+ * The main system clock will be configured to use this clock during\r
+ * initialization.\r
+ */\r
+#ifndef CONFIG_SYSCLK_SOURCE\r
+# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC\r
+#endif\r
+/**\r
+ * \def CONFIG_SYSCLK_PRES\r
+ * \brief Initial CPU clock divider (mck)\r
+ *\r
+ * The MCK will run at\r
+ * \f[\r
+ * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz}\r
+ * \f]\r
+ * after initialization.\r
+ */\r
+#ifndef CONFIG_SYSCLK_PRES\r
+# define CONFIG_SYSCLK_PRES 0\r
+#endif\r
+\r
+//@}\r
+\r
+//! \name Master Clock Sources (MCK)\r
+//@{\r
+#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock\r
+#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock\r
+#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock\r
+#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock\r
+#define SYSCLK_SRC_UPLLCK 9 //!< Use UPLLCK as master source clock\r
+//@}\r
+\r
+//! \name Master Clock Prescalers (MCK)\r
+//@{\r
+#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1\r
+#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2\r
+#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4\r
+#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8\r
+#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16\r
+#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32\r
+#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64\r
+#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3\r
+//@}\r
+\r
+//! \name USB Clock Sources\r
+//@{\r
+#define USBCLK_SRC_PLL0 0 //!< Use PLLA\r
+#define USBCLK_SRC_UPLL 1 //!< Use UPLL\r
+//@}\r
+\r
+/**\r
+ * \def CONFIG_USBCLK_SOURCE\r
+ * \brief Configuration symbol for the USB generic clock source\r
+ *\r
+ * Sets the clock source to use for the USB. The source must also be properly\r
+ * configured.\r
+ *\r
+ * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if\r
+ * USB is not required.\r
+ */\r
+#ifdef __DOXYGEN__\r
+# define CONFIG_USBCLK_SOURCE\r
+#endif\r
+\r
+/**\r
+ * \def CONFIG_USBCLK_DIV\r
+ * \brief Configuration symbol for the USB generic clock divider setting\r
+ *\r
+ * Sets the clock division for the USB generic clock. If a USB clock source is\r
+ * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be\r
+ * defined.\r
+ */\r
+#ifdef __DOXYGEN__\r
+# define CONFIG_USBCLK_DIV\r
+#endif\r
+\r
+/**\r
+ * \name Querying the system clock\r
+ *\r
+ * The following functions may be used to query the current frequency of\r
+ * the system clock and the CPU and bus clocks derived from it.\r
+ * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be\r
+ * available on all platforms, although some platforms may define\r
+ * additional accessors for various chip-internal bus clocks. These are\r
+ * usually not intended to be queried directly by generic code.\r
+ */\r
+//@{\r
+\r
+/**\r
+ * \brief Return the current rate in Hz of the main system clock\r
+ *\r
+ * \todo This function assumes that the main clock source never changes\r
+ * once it's been set up, and that PLL0 always runs at the compile-time\r
+ * configured default rate. While this is probably the most common\r
+ * configuration, which we want to support as a special case for\r
+ * performance reasons, we will at some point need to support more\r
+ * dynamic setups as well.\r
+ */\r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+extern uint32_t sysclk_initialized;\r
+#endif\r
+static inline uint32_t sysclk_get_main_hz(void)\r
+{\r
+#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)\r
+ if (!sysclk_initialized ) {\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+ }\r
+#endif\r
+\r
+ /* Config system clock setting */\r
+ switch (CONFIG_SYSCLK_SOURCE) {\r
+ case SYSCLK_SRC_SLCK_RC:\r
+ return OSC_SLCK_32K_RC_HZ;\r
+ \r
+ case SYSCLK_SRC_SLCK_XTAL:\r
+ return OSC_SLCK_32K_XTAL_HZ;\r
+ \r
+ case SYSCLK_SRC_SLCK_BYPASS:\r
+ return OSC_SLCK_32K_BYPASS_HZ;\r
+\r
+\r
+ case SYSCLK_SRC_MAINCK_4M_RC:\r
+ return OSC_MAINCK_4M_RC_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_8M_RC:\r
+ return OSC_MAINCK_8M_RC_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_12M_RC:\r
+ return OSC_MAINCK_12M_RC_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_XTAL:\r
+ return OSC_MAINCK_XTAL_HZ;\r
+\r
+ case SYSCLK_SRC_MAINCK_BYPASS:\r
+ return OSC_MAINCK_BYPASS_HZ;\r
+\r
+#ifdef CONFIG_PLL0_SOURCE\r
+ case SYSCLK_SRC_PLLACK:\r
+ return pll_get_default_rate(0); \r
+#endif\r
+\r
+#ifdef CONFIG_PLL1_SOURCE\r
+ case SYSCLK_SRC_UPLLCK:\r
+ return PLL_UPLL_HZ; \r
+#endif\r
+ \r
+ default:\r
+ /* unhandled_case(CONFIG_SYSCLK_SOURCE); */\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Return the current rate in Hz of the CPU clock\r
+ *\r
+ * \todo This function assumes that the CPU always runs at the system\r
+ * clock frequency. We want to support at least two more scenarios:\r
+ * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus\r
+ * clock dividers (which may change at run time). Ditto for all the bus\r
+ * clocks.\r
+ *\r
+ * \return Frequency of the CPU clock, in Hz.\r
+ */\r
+static inline uint32_t sysclk_get_cpu_hz(void)\r
+{\r
+ /* CONFIG_SYSCLK_PRES is the register value for setting the expected */\r
+ /* prescaler, not an immediate value. */\r
+ return sysclk_get_main_hz() / ((CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos) + 1);\r
+}\r
+\r
+/**\r
+ * \brief Retrieves the current rate in Hz of the peripheral clocks.\r
+ *\r
+ * \return Frequency of the peripheral clocks, in Hz.\r
+ */\r
+static inline uint32_t sysclk_get_peripheral_hz(void)\r
+{\r
+ /* CONFIG_SYSCLK_PRES is the register value for setting the expected */\r
+ /* prescaler, not an immediate value. */\r
+ return sysclk_get_main_hz() / ((CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos) + 1);\r
+}\r
+\r
+//@}\r
+\r
+//! \name Enabling and disabling synchronous clocks\r
+//@{\r
+\r
+/**\r
+ * \brief Enable a peripheral's clock.\r
+ *\r
+ * \param ul_id Id (number) of the peripheral clock.\r
+ */\r
+static inline void sysclk_enable_peripheral_clock(uint32_t ul_id)\r
+{\r
+ pmc_enable_periph_clk(ul_id);\r
+}\r
+\r
+/**\r
+ * \brief Disable a peripheral's clock.\r
+ *\r
+ * \param ul_id Id (number) of the peripheral clock.\r
+ */\r
+static inline void sysclk_disable_peripheral_clock(uint32_t ul_id)\r
+{\r
+ pmc_disable_periph_clk(ul_id);\r
+}\r
+\r
+//@}\r
+\r
+//! \name System Clock Source and Prescaler configuration\r
+//@{\r
+\r
+extern void sysclk_set_prescalers(uint32_t ul_pres);\r
+extern void sysclk_set_source(uint32_t ul_src);\r
+\r
+//@}\r
+\r
+extern void sysclk_enable_usb(void);\r
+extern void sysclk_disable_usb(void);\r
+\r
+extern void sysclk_init(void);\r
+\r
+//! @}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* CHIP_SYSCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief System clock management\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef SYSCLK_H_INCLUDED\r
+#define SYSCLK_H_INCLUDED\r
+\r
+#include "parts.h"\r
+#include "conf_clock.h"\r
+\r
+#if SAM3S\r
+# include "sam3s/sysclk.h"\r
+#elif SAM3U\r
+# include "sam3u/sysclk.h"\r
+#elif SAM3N\r
+# include "sam3n/sysclk.h"\r
+#elif SAM3XA\r
+# include "sam3x/sysclk.h"\r
+#elif SAM4S\r
+# include "sam4s/sysclk.h"\r
+#elif (UC3A0 || UC3A1)\r
+# include "uc3a0_a1/sysclk.h"\r
+#elif UC3A3\r
+# include "uc3a3_a4/sysclk.h"\r
+#elif UC3B\r
+# include "uc3b0_b1/sysclk.h"\r
+#elif UC3C\r
+# include "uc3c/sysclk.h"\r
+#elif UC3D\r
+# include "uc3d/sysclk.h"\r
+#elif UC3L\r
+# include "uc3l/sysclk.h"\r
+#elif XMEGA\r
+# include "xmega/sysclk.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+/**\r
+ * \defgroup clk_group Clock Management\r
+ */\r
+\r
+/**\r
+ * \ingroup clk_group\r
+ * \defgroup sysclk_group System Clock Management\r
+ *\r
+ * See \ref sysclk_quickstart.\r
+ *\r
+ * The <em>sysclk</em> API covers the <em>system clock</em> and all\r
+ * clocks derived from it. The system clock is a chip-internal clock on\r
+ * which all <em>synchronous clocks</em>, i.e. CPU and bus/peripheral\r
+ * clocks, are based. The system clock is typically generated from one\r
+ * of a variety of sources, which may include crystal and RC oscillators\r
+ * as well as PLLs. The clocks derived from the system clock are\r
+ * sometimes also known as <em>synchronous clocks</em>, since they\r
+ * always run synchronously with respect to each other, as opposed to\r
+ * <em>generic clocks</em> which may run from different oscillators or\r
+ * PLLs.\r
+ *\r
+ * Most applications should simply call sysclk_init() to initialize\r
+ * everything related to the system clock and its source (oscillator,\r
+ * PLL or DFLL), and leave it at that. More advanced applications, and\r
+ * platform-specific drivers, may require additional services from the\r
+ * clock system, some of which may be platform-specific.\r
+ *\r
+ * \section sysclk_group_platform Platform Dependencies\r
+ *\r
+ * The sysclk API is partially chip- or platform-specific. While all\r
+ * platforms provide mostly the same functionality, there are some\r
+ * variations around how different bus types and clock tree structures\r
+ * are handled.\r
+ *\r
+ * The following functions are available on all platforms with the same\r
+ * parameters and functionality. These functions may be called freely by\r
+ * portable applications, drivers and services:\r
+ * - sysclk_init()\r
+ * - sysclk_set_source()\r
+ * - sysclk_get_main_hz()\r
+ * - sysclk_get_cpu_hz()\r
+ * - sysclk_get_peripheral_bus_hz()\r
+ *\r
+ * The following functions are available on all platforms, but there may\r
+ * be variations in the function signature (i.e. parameters) and\r
+ * behavior. These functions are typically called by platform-specific\r
+ * parts of drivers, and applications that aren't intended to be\r
+ * portable:\r
+ * - sysclk_enable_peripheral_clock()\r
+ * - sysclk_disable_peripheral_clock()\r
+ * - sysclk_enable_module()\r
+ * - sysclk_disable_module()\r
+ * - sysclk_module_is_enabled()\r
+ * - sysclk_set_prescalers()\r
+ *\r
+ * All other functions should be considered platform-specific.\r
+ * Enabling/disabling clocks to specific peripherals as well as\r
+ * determining the speed of these clocks should be done by calling\r
+ * functions provided by the driver for that peripheral.\r
+ *\r
+ * @{\r
+ */\r
+\r
+//! \name System Clock Initialization\r
+//@{\r
+/**\r
+ * \fn void sysclk_init(void)\r
+ * \brief Initialize the synchronous clock system.\r
+ *\r
+ * This function will initialize the system clock and its source. This\r
+ * includes:\r
+ * - Mask all synchronous clocks except for any clocks which are\r
+ * essential for normal operation (for example internal memory\r
+ * clocks).\r
+ * - Set up the system clock prescalers as specified by the\r
+ * application's configuration file.\r
+ * - Enable the clock source specified by the application's\r
+ * configuration file (oscillator or PLL) and wait for it to become\r
+ * stable.\r
+ * - Set the main system clock source to the clock specified by the\r
+ * application's configuration file.\r
+ *\r
+ * Since all non-essential peripheral clocks are initially disabled, it\r
+ * is the responsibility of the peripheral driver to re-enable any\r
+ * clocks that are needed for normal operation.\r
+ */\r
+//@}\r
+\r
+//! @}\r
+\r
+#endif /* SYSCLK_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Common GPIO API.\r
+ *\r
+ * Copyright (c) 2010 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef _GPIO_H_\r
+#define _GPIO_H_\r
+\r
+#include <parts.h>\r
+\r
+#if ( SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S )\r
+# include "sam_ioport/sam_gpio.h"\r
+#elif XMEGA\r
+# include "xmega_ioport/xmega_gpio.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+\r
+/**\r
+ * \defgroup gpio_group General Purpose Input/Output\r
+ *\r
+ * This is the common API for GPIO. Additional features are available\r
+ * in the documentation of the specific modules.\r
+ *\r
+ * \section io_group_platform Platform Dependencies\r
+ *\r
+ * The following functions are available on all platforms, but there may\r
+ * be variations in the function signature (i.e. parameters) and\r
+ * behaviour. These functions are typically called by platform-specific\r
+ * parts of drivers, and applications that aren't intended to be\r
+ * portable:\r
+ * - gpio_pin_is_low()\r
+ * - gpio_pin_is_high()\r
+ * - gpio_set_pin_high()\r
+ * - gpio_set_pin_group_high()\r
+ * - gpio_set_pin_low()\r
+ * - gpio_set_pin_group_low()\r
+ * - gpio_toggle_pin()\r
+ * - gpio_toggle_pin_group()\r
+ * - gpio_configure_pin()\r
+ * - gpio_configure_group()\r
+ */\r
+\r
+#endif // _GPIO_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief GPIO service for SAM.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SAM_GPIO_H_INCLUDED\r
+#define SAM_GPIO_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+#include "pio.h"\r
+\r
+#define gpio_pin_is_low(io_id) \\r
+ (pio_get_pin_value(io_id) ? 0 : 1)\r
+\r
+#define gpio_pin_is_high(io_id) \\r
+ (pio_get_pin_value(io_id) ? 1 : 0)\r
+\r
+#define gpio_set_pin_high(io_id) \\r
+ pio_set_pin_high(io_id)\r
+\r
+#define gpio_set_pin_low(io_id) \\r
+ pio_set_pin_low(io_id)\r
+\r
+#define gpio_toggle_pin(io_id) \\r
+ pio_toggle_pin(io_id)\r
+\r
+#define gpio_configure_pin(io_id,io_flags) \\r
+ pio_configure_pin(io_id,io_flags)\r
+\r
+#define gpio_configure_group(port_id,port_mask,io_flags) \\r
+ pio_configure_pin_group(port_id,port_mask,io_flags)\r
+\r
+#define gpio_set_pin_group_high(port_id,mask) \\r
+ pio_set_pin_group_high(port_id,mask)\r
+\r
+#define gpio_set_pin_group_low(port_id,mask) \\r
+ pio_set_pin_group_low(port_id,mask)\r
+\r
+#define gpio_toggle_pin_group(port_id,mask) \\r
+ pio_toggle_pin_group(port_id,mask)\r
+\r
+#endif /* SAM_GPIO_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for 8- and 32-bit AVR\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef UTILS_INTERRUPT_H\r
+#define UTILS_INTERRUPT_H\r
+\r
+#include <parts.h>\r
+\r
+#if XMEGA || MEGA\r
+# include "interrupt/interrupt_avr8.h"\r
+#elif UC3\r
+# include "interrupt/interrupt_avr32.h"\r
+#elif SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S\r
+# include "interrupt/interrupt_sam_nvic.h"\r
+#else\r
+# error Unsupported device.\r
+#endif\r
+\r
+/**\r
+ * \defgroup interrupt_group Global interrupt management\r
+ *\r
+ * This is a driver for global enabling and disabling of interrupts.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#if defined(__DOXYGEN__)\r
+/**\r
+ * \def CONFIG_INTERRUPT_FORCE_INTC\r
+ * \brief Force usage of the ASF INTC driver\r
+ *\r
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.\r
+ * This is useful to ensure compatibilty accross compilers and shall be used only when required\r
+ * by the application needs.\r
+ */\r
+# define CONFIG_INTERRUPT_FORCE_INTC\r
+#endif\r
+\r
+//! \name Global interrupt flags\r
+//@{\r
+/**\r
+ * \typedef irqflags_t\r
+ * \brief Type used for holding state of interrupt flag\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_enable\r
+ * \brief Enable interrupts globally\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_disable\r
+ * \brief Disable interrupts globally\r
+ */\r
+\r
+/**\r
+ * \fn irqflags_t cpu_irq_save(void)\r
+ * \brief Get and clear the global interrupt flags\r
+ *\r
+ * Use in conjunction with \ref cpu_irq_restore.\r
+ *\r
+ * \return Current state of interrupt flags.\r
+ *\r
+ * \note This function leaves interrupts disabled.\r
+ */\r
+\r
+/**\r
+ * \fn void cpu_irq_restore(irqflags_t flags)\r
+ * \brief Restore global interrupt flags\r
+ *\r
+ * Use in conjunction with \ref cpu_irq_save.\r
+ *\r
+ * \param flags State to set interrupt flag to.\r
+ */\r
+\r
+/**\r
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)\r
+ * \brief Check if interrupts are globally enabled in supplied flags\r
+ *\r
+ * \param flags Currents state of interrupt flags.\r
+ *\r
+ * \return True if interrupts are enabled.\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_is_enabled\r
+ * \brief Check if interrupts are globally enabled\r
+ *\r
+ * \return True if interrupts are enabled.\r
+ */\r
+//@}\r
+\r
+//! @}\r
+\r
+/**\r
+ * \ingroup interrupt_group\r
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions\r
+ */\r
+\r
+#endif /* UTILS_INTERRUPT_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for SAM3 and SAM4 (NVIC based)\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "interrupt_sam_nvic.h"\r
+\r
+//! Global NVIC interrupt enable status (by default it's enabled)\r
+bool g_interrupt_enabled = true;\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for SAM3 and SAM4 (NVIC based)\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef UTILS_INTERRUPT_INTERRUPT_H\r
+#define UTILS_INTERRUPT_INTERRUPT_H\r
+\r
+#include <compiler.h>\r
+#include <parts.h>\r
+\r
+/**\r
+ * \weakgroup interrupt_group\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Interrupt Service Routine definition\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Define service routine\r
+ *\r
+ * \note For NVIC devices the interrupt service routines are predefined to\r
+ * add to vector table in binary generation, so there is no service\r
+ * register at run time. The routine collections are in exceptions.h.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ * ISR(foo_irq_handler)\r
+ * {\r
+ * // Function definition\r
+ * ...\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \param func Name for the function.\r
+ */\r
+# define ISR(func) \\r
+ void func (void)\r
+\r
+/**\r
+ * \brief Initialize interrupt vectors\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to initialize them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * This must be called prior to \ref irq_register_handler.\r
+ */\r
+# define irq_initialize_vectors() \\r
+ do { \\r
+ } while(0)\r
+\r
+/**\r
+ * \brief Register handler for interrupt\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to register them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ * irq_initialize_vectors();\r
+ * irq_register_handler(foo_irq_handler);\r
+ * \endcode\r
+ *\r
+ * \note The function \a func must be defined with the \ref ISR macro.\r
+ * \note The functions prototypes can be found in the device exception header\r
+ * files (exceptions.h).\r
+ */\r
+# define irq_register_handler(...) \\r
+ do { \\r
+ } while(0)\r
+\r
+//@}\r
+\r
+# define cpu_irq_enable() \\r
+ do { \\r
+ g_interrupt_enabled = true; \\r
+ __DMB(); \\r
+ __enable_irq(); \\r
+ } while (0)\r
+# define cpu_irq_disable() \\r
+ do { \\r
+ __disable_irq(); \\r
+ __DMB(); \\r
+ g_interrupt_enabled = false; \\r
+ } while (0)\r
+\r
+typedef uint32_t irqflags_t;\r
+extern bool g_interrupt_enabled;\r
+\r
+static inline irqflags_t cpu_irq_save(void)\r
+{\r
+ irqflags_t flags = g_interrupt_enabled;\r
+ cpu_irq_disable();\r
+ return flags;\r
+}\r
+\r
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)\r
+{\r
+ return (flags);\r
+}\r
+\r
+static inline void cpu_irq_restore(irqflags_t flags)\r
+{\r
+ if (cpu_irq_is_enabled_flags(flags))\r
+ cpu_irq_enable();\r
+}\r
+\r
+#define cpu_irq_is_enabled() g_interrupt_enabled\r
+\r
+/**\r
+ * \weakgroup interrupt_deprecated_group\r
+ * @{\r
+ */\r
+\r
+#define Enable_global_interrupt() cpu_irq_enable()\r
+#define Disable_global_interrupt() cpu_irq_disable()\r
+#define Is_global_interrupt_enabled() cpu_irq_is_enabled()\r
+\r
+//@}\r
+\r
+//@}\r
+\r
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Atmel part identification macros\r
+ *\r
+ * Copyright (C) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef ATMEL_PARTS_H\r
+#define ATMEL_PARTS_H\r
+\r
+/**\r
+ * \defgroup part_macros_group Atmel part identification macros\r
+ *\r
+ * This collection of macros identify which series and families that the various\r
+ * Atmel parts belong to. These can be used to select part-dependent sections of\r
+ * code at compile time.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Convenience macros for part checking\r
+ * @{\r
+ */\r
+//! Check GCC and IAR part definition for 8-bit AVR\r
+#define AVR8_PART_IS_DEFINED(part) \\r
+ (defined(__ ## part ## __) || defined(__AVR_ ## part ## __))\r
+\r
+//! Check GCC and IAR part definition for 32-bit AVR\r
+#define AVR32_PART_IS_DEFINED(part) \\r
+ (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))\r
+\r
+//! Check GCC and IAR part definition for SAM\r
+#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup uc3_part_macros_group AVR UC3 parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name AVR UC3 A series\r
+ * @{\r
+ */\r
+#define UC3A0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A0128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A0256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A0512) \\r
+ )\r
+\r
+#define UC3A1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A1128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A1256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A1512) \\r
+ )\r
+\r
+#define UC3A3 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A364) || \\r
+ AVR32_PART_IS_DEFINED(UC3A364S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3128S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A3256S) \\r
+ )\r
+\r
+#define UC3A4 ( \\r
+ AVR32_PART_IS_DEFINED(UC3A464) || \\r
+ AVR32_PART_IS_DEFINED(UC3A464S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4128) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4128S) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4256) || \\r
+ AVR32_PART_IS_DEFINED(UC3A4256S) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 B series\r
+ * @{\r
+ */\r
+#define UC3B0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3B064) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0128) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0256) || \\r
+ AVR32_PART_IS_DEFINED(UC3B0512) \\r
+ )\r
+\r
+#define UC3B1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3B164) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1128) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1256) || \\r
+ AVR32_PART_IS_DEFINED(UC3B1512) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 C series\r
+ * @{\r
+ */\r
+#define UC3C0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C064C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C0512C) \\r
+ )\r
+\r
+#define UC3C1 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C164C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C1512C) \\r
+ )\r
+\r
+#define UC3C2 ( \\r
+ AVR32_PART_IS_DEFINED(UC3C264C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2128C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2256C) || \\r
+ AVR32_PART_IS_DEFINED(UC3C2512C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 D series\r
+ * @{\r
+ */\r
+#define UC3D3 ( \\r
+ AVR32_PART_IS_DEFINED(UC64D3) || \\r
+ AVR32_PART_IS_DEFINED(UC128D3) \\r
+ )\r
+\r
+#define UC3D4 ( \\r
+ AVR32_PART_IS_DEFINED(UC64D4) || \\r
+ AVR32_PART_IS_DEFINED(UC128D4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 L series\r
+ * @{\r
+ */\r
+#define UC3L0 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L016) || \\r
+ AVR32_PART_IS_DEFINED(UC3L032) || \\r
+ AVR32_PART_IS_DEFINED(UC3L064) \\r
+ )\r
+\r
+#define UC3L0128 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L0128) \\r
+ )\r
+\r
+#define UC3L0256 ( \\r
+ AVR32_PART_IS_DEFINED(UC3L0256) \\r
+ )\r
+\r
+#define UC3L3 ( \\r
+ AVR32_PART_IS_DEFINED(UC64L3U) || \\r
+ AVR32_PART_IS_DEFINED(UC128L3U) || \\r
+ AVR32_PART_IS_DEFINED(UC256L3U) \\r
+ )\r
+\r
+#define UC3L4 ( \\r
+ AVR32_PART_IS_DEFINED(UC64L4U) || \\r
+ AVR32_PART_IS_DEFINED(UC128L4U) || \\r
+ AVR32_PART_IS_DEFINED(UC256L4U) \\r
+ )\r
+\r
+#define UC3L3_L4 (UC3L3 || UC3L4)\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR UC3 families\r
+ * @{\r
+ */\r
+/** AVR UC3 A family */\r
+#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4)\r
+\r
+/** AVR UC3 B family */\r
+#define UC3B (UC3B0 || UC3B1)\r
+\r
+/** AVR UC3 C family */\r
+#define UC3C (UC3C0 || UC3C1 || UC3C2)\r
+\r
+/** AVR UC3 D family */\r
+#define UC3D (UC3D3 || UC3D4)\r
+\r
+/** AVR UC3 L family */\r
+#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4)\r
+/** @} */\r
+\r
+/** AVR UC3 product line */\r
+#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup xmega_part_macros_group AVR XMEGA parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name AVR XMEGA A series\r
+ * @{\r
+ */\r
+#define XMEGA_A1 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A1) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A1) \\r
+ )\r
+\r
+#define XMEGA_A3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192A3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3) \\r
+ )\r
+\r
+#define XMEGA_A3B ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3B) \\r
+ )\r
+\r
+#define XMEGA_A4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16A4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32A4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA AU series\r
+ * @{\r
+ */\r
+#define XMEGA_A1U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A1U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A1U) \\r
+ )\r
+\r
+#define XMEGA_A3U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192A3U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3U) \\r
+ )\r
+\r
+#define XMEGA_A3BU ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega256A3BU) \\r
+ )\r
+\r
+#define XMEGA_A4U ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega64A4U) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128A4U) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA B series\r
+ * @{\r
+ */\r
+#define XMEGA_B1 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64B1) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128B1) \\r
+ )\r
+\r
+#define XMEGA_B3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64B3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128B3) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA C series\r
+ * @{\r
+ */\r
+#define XMEGA_C3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega384C3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256C3) \\r
+ )\r
+\r
+#define XMEGA_C4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega32C4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega16C4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA D series\r
+ * @{\r
+ */\r
+#define XMEGA_D3 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega64D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega192D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega256D3) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega384D3) \\r
+ )\r
+\r
+#define XMEGA_D4 ( \\r
+ AVR8_PART_IS_DEFINED(ATxmega16D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega32D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega64D4) || \\r
+ AVR8_PART_IS_DEFINED(ATxmega128D4) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name AVR XMEGA families\r
+ * @{\r
+ */\r
+/** AVR XMEGA A family */\r
+#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4)\r
+\r
+/** AVR XMEGA AU family */\r
+#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U)\r
+\r
+/** AVR XMEGA B family */\r
+#define XMEGA_B (XMEGA_B1 || XMEGA_B3)\r
+\r
+/** AVR XMEGA C family */\r
+#define XMEGA_C (XMEGA_C3 || XMEGA_C4)\r
+\r
+/** AVR XMEGA D family */\r
+#define XMEGA_D (XMEGA_D3 || XMEGA_D4)\r
+/** @} */\r
+\r
+/** AVR XMEGA product line */\r
+#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup mega_part_macros_group megaAVR parts\r
+ *\r
+ * \note These megaAVR groupings are based on the groups in AVR Libc for the\r
+ * part header files. They are not names of official megaAVR device series or\r
+ * families.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name ATmegaxx0/xx1 subgroups\r
+ * @{\r
+ */\r
+#define MEGA_XX0 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega640) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1280) || \\r
+ AVR8_PART_IS_DEFINED(ATmega2560) \\r
+ )\r
+\r
+#define MEGA_XX1 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega1281) || \\r
+ AVR8_PART_IS_DEFINED(ATmega2561) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name megaAVR groups\r
+ * @{\r
+ */\r
+/** ATmegaxx0/xx1 group */\r
+#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1)\r
+\r
+/** ATmegaxx4 group */\r
+#define MEGA_XX4 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega164A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1284P) \\r
+ )\r
+\r
+/** ATmegaxx4 group */\r
+#define MEGA_XX4_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega164A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega164PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega324PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega644PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega1284P) \\r
+ )\r
+\r
+/** ATmegaxx8 group */\r
+#define MEGA_XX8 ( \\r
+ AVR8_PART_IS_DEFINED(ATmega48) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328P) \\r
+ )\r
+\r
+/** ATmegaxx8A/P/PA group */\r
+#define MEGA_XX8_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega48A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega48PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega88PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega168PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega328P) \\r
+ )\r
+\r
+/** ATmegaxx group */\r
+#define MEGA_XX ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) \\r
+ )\r
+\r
+/** ATmegaxxA/P/PA group */\r
+#define MEGA_XX_A ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) \\r
+ )\r
+\r
+/** Unspecified group */\r
+#define MEGA_UNSPECIFIED ( \\r
+ AVR8_PART_IS_DEFINED(ATmega16) || \\r
+ AVR8_PART_IS_DEFINED(ATmega16A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32) || \\r
+ AVR8_PART_IS_DEFINED(ATmega32A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64) || \\r
+ AVR8_PART_IS_DEFINED(ATmega64A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128) || \\r
+ AVR8_PART_IS_DEFINED(ATmega128A) || \\r
+ AVR8_PART_IS_DEFINED(ATmega169P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega169PA) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329P) || \\r
+ AVR8_PART_IS_DEFINED(ATmega329PA) \\r
+ )\r
+/** @} */\r
+\r
+/** megaAVR product line */\r
+#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_UNSPECIFIED)\r
+\r
+/** @} */\r
+\r
+/**\r
+ * \defgroup sam_part_macros_group SAM parts\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name SAM3S series\r
+ * @{\r
+ */\r
+#define SAM3S1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S1A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S1B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S1C) \\r
+ )\r
+\r
+#define SAM3S2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S2A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S2B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S2C) \\r
+ )\r
+\r
+#define SAM3S4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S4A) || \\r
+ SAM_PART_IS_DEFINED(SAM3S4B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S4C) \\r
+ )\r
+\r
+#define SAM3S8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3S8B) || \\r
+ SAM_PART_IS_DEFINED(SAM3S8C) \\r
+ )\r
+\r
+#define SAM3SD8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3SD8B) || \\r
+ SAM_PART_IS_DEFINED(SAM3SD8C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3U series\r
+ * @{\r
+ */\r
+#define SAM3U1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U1C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U1E) \\r
+ )\r
+\r
+#define SAM3U2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U2C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U2E) \\r
+ )\r
+\r
+#define SAM3U4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3U4C) || \\r
+ SAM_PART_IS_DEFINED(SAM3U4E) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3N series\r
+ * @{\r
+ */\r
+#define SAM3N1 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N1A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N1B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N1C) \\r
+ )\r
+\r
+#define SAM3N2 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N2A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N2B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N2C) \\r
+ )\r
+\r
+#define SAM3N4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3N4A) || \\r
+ SAM_PART_IS_DEFINED(SAM3N4B) || \\r
+ SAM_PART_IS_DEFINED(SAM3N4C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3X series\r
+ * @{\r
+ */\r
+#define SAM3X4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3X4C) || \\r
+ SAM_PART_IS_DEFINED(SAM3X4E) \\r
+ )\r
+\r
+#define SAM3X8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3X8C) || \\r
+ SAM_PART_IS_DEFINED(SAM3X8E) || \\r
+ SAM_PART_IS_DEFINED(SAM3X8H) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM3A series\r
+ * @{\r
+ */\r
+#define SAM3A4 ( \\r
+ SAM_PART_IS_DEFINED(SAM3A4C) \\r
+ )\r
+\r
+#define SAM3A8 ( \\r
+ SAM_PART_IS_DEFINED(SAM3A8C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM4S series\r
+ * @{\r
+ */\r
+#define SAM4S8 ( \\r
+ SAM_PART_IS_DEFINED(SAM4S8B) || \\r
+ SAM_PART_IS_DEFINED(SAM4S8C) \\r
+ )\r
+\r
+#define SAM4S16 ( \\r
+ SAM_PART_IS_DEFINED(SAM4S16B) || \\r
+ SAM_PART_IS_DEFINED(SAM4S16C) \\r
+ )\r
+/** @} */\r
+\r
+/**\r
+ * \name SAM families\r
+ * @{\r
+ */\r
+/** SAM3S Family */\r
+#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)\r
+\r
+/** SAM3U Family */\r
+#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)\r
+\r
+/** SAM3N Family */\r
+#define SAM3N (SAM3N1 || SAM3N2 || SAM3N4)\r
+\r
+/** SAM3XA Family */\r
+#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)\r
+\r
+/** SAM4S Family */\r
+#define SAM4S (SAM4S8 || SAM4S16)\r
+/** @} */\r
+\r
+/** SAM product line */\r
+#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S)\r
+\r
+/** @} */\r
+\r
+/** @} */\r
+\r
+#endif /* ATMEL_PARTS_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM3X-EK board init.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "compiler.h"\r
+#include "board.h"\r
+#include "conf_board.h"\r
+#include "gpio.h"\r
+\r
+void board_init(void)\r
+{\r
+#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT\r
+ /* Disable the watchdog */\r
+ WDT->WDT_MR = WDT_MR_WDDIS;\r
+#endif\r
+\r
+ /* Configure Power LED */\r
+ gpio_configure_pin(LED3_GPIO, LED3_FLAGS);\r
+ gpio_set_pin_high(LED3_GPIO); /* Turned on by default */\r
+\r
+ /* Configure User LED pins */\r
+ gpio_configure_pin(LED0_GPIO, LED0_FLAGS);\r
+ gpio_configure_pin(LED1_GPIO, LED1_FLAGS);\r
+ gpio_configure_pin(LED2_GPIO, LED2_FLAGS);\r
+\r
+ /* Configure Push Button pins */\r
+ gpio_configure_pin(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS);\r
+ gpio_configure_pin(GPIO_PUSH_BUTTON_2, GPIO_PUSH_BUTTON_2_FLAGS);\r
+\r
+#ifdef CONF_BOARD_UART_CONSOLE\r
+ /* Configure UART pins */\r
+ gpio_configure_group(PINS_UART_PIO, PINS_UART, PINS_UART_FLAGS);\r
+#endif\r
+\r
+ /* Configure ADC example pins */\r
+#ifdef CONF_BOARD_ADC\r
+ /* TC TIOA configuration */\r
+ gpio_configure_pin(PIN_TC0_TIOA0,PIN_TC0_TIOA0_FLAGS);\r
+\r
+ /* ADC Trigger configuration */\r
+ gpio_configure_pin(PINS_ADC_TRIG, PINS_ADC_TRIG_FLAG);\r
+\r
+ /* PWMH0 configuration */\r
+ gpio_configure_pin(PIN_PWMC_PWMH0_TRIG, PIN_PWMC_PWMH0_TRIG_FLAG);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED0\r
+ /* Configure PWM LED0 pin */\r
+ gpio_configure_pin(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED1\r
+ /* Configure PWM LED1 pin */\r
+ gpio_configure_pin(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED2\r
+ /* Configure PWM LED2 pin */\r
+ gpio_configure_pin(PIN_PWM_LED2_GPIO, PIN_PWM_LED2_FLAGS);\r
+#endif\r
+\r
+ /* Configure SPI0 pins */\r
+#ifdef CONF_BOARD_SPI0\r
+ gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS);\r
+ gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS);\r
+ gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS);\r
+\r
+ /**\r
+ * For NPCS 1, 2, and 3, different PINs can be used to access the same\r
+ * NPCS line.\r
+ * Depending on the application requirements, the default PIN may not be\r
+ * available.\r
+ * Hence a different PIN should be selected using the\r
+ * CONF_BOARD_SPI_NPCS_GPIO and\r
+ * CONF_BOARD_SPI_NPCS_FLAGS macros.\r
+ */\r
+\r
+# ifdef CONF_BOARD_SPI0_NPCS0\r
+ gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS);\r
+# endif\r
+\r
+# ifdef CONF_BOARD_SPI0_NPCS1\r
+# if defined(CONF_BOARD_SPI0_NPCS1_GPIO) && \\r
+ defined(CONF_BOARD_SPI0_NPCS1_FLAGS)\r
+ gpio_configure_pin(CONF_BOARD_SPI0_NPCS1_GPIO,\r
+ CONF_BOARD_SPI0_NPCS1_FLAGS);\r
+# else\r
+ gpio_configure_pin(SPI0_NPCS1_PA29_GPIO,\r
+ SPI0_NPCS1_PA29_FLAGS);\r
+# endif\r
+# endif\r
+\r
+# ifdef CONF_BOARD_SPI0_NPCS2\r
+# if defined(CONF_BOARD_SPI0_NPCS2_GPIO) && \\r
+ defined(CONF_BOARD_SPI0_NPCS2_FLAGS)\r
+ gpio_configure_pin(CONF_BOARD_SPI0_NPCS2_GPIO,\r
+ CONF_BOARD_SPI0_NPCS2_FLAGS);\r
+# else\r
+ gpio_configure_pin(SPI0_NPCS2_PA30_GPIO,\r
+ SPI0_NPCS2_PA30_FLAGS);\r
+# endif\r
+# endif\r
+\r
+# ifdef CONF_BOARD_SPI0_NPCS3\r
+# if defined(CONF_BOARD_SPI0_NPCS3_GPIO) && \\r
+ defined(CONF_BOARD_SPI0_NPCS3_FLAGS)\r
+ gpio_configure_pin(CONF_BOARD_SPI0_NPCS3_GPIO,\r
+ CONF_BOARD_SPI0_NPCS3_FLAGS);\r
+# else\r
+ gpio_configure_pin(SPI0_NPCS3_PA31_GPIO,\r
+ SPI0_NPCS3_PA31_FLAGS);\r
+# endif\r
+# endif\r
+#endif // #ifdef CONF_BOARD_SPI0\r
+\r
+ /* Configure SPI1 pins */\r
+#ifdef CONF_BOARD_SPI1\r
+ gpio_configure_pin(SPI1_MISO_GPIO, SPI1_MISO_FLAGS);\r
+ gpio_configure_pin(SPI1_MOSI_GPIO, SPI1_MOSI_FLAGS);\r
+ gpio_configure_pin(SPI1_SPCK_GPIO, SPI1_SPCK_FLAGS);\r
+\r
+# ifdef CONF_BOARD_SPI1_NPCS0\r
+ gpio_configure_pin(SPI1_NPCS0_GPIO, SPI1_NPCS0_FLAGS);\r
+# endif\r
+\r
+# ifdef CONF_BOARD_SPI1_NPCS1\r
+ gpio_configure_pin(SPI1_NPCS1_GPIO, SPI1_NPCS1_FLAGS);\r
+# endif\r
+\r
+# ifdef CONF_BOARD_SPI1_NPCS2\r
+ gpio_configure_pin(SPI1_NPCS2_GPIO, SPI1_NPCS2_FLAGS);\r
+# endif\r
+\r
+# ifdef CONF_BOARD_SPI1_NPCS3\r
+ gpio_configure_pin(SPI1_NPCS3_GPIO, SPI1_NPCS3_FLAGS);\r
+# endif\r
+#endif\r
+\r
+#ifdef CONF_BOARD_TWI0\r
+ gpio_configure_pin(TWI0_DATA_GPIO, TWI0_DATA_FLAGS);\r
+ gpio_configure_pin(TWI0_CLK_GPIO, TWI0_CLK_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_TWI1\r
+ gpio_configure_pin(TWI1_DATA_GPIO, TWI1_DATA_FLAGS);\r
+ gpio_configure_pin(TWI1_CLK_GPIO, TWI1_CLK_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_RXD\r
+ /* Configure USART RXD pin */\r
+ gpio_configure_pin(PIN_USART0_RXD_IDX, PIN_USART0_RXD_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_TXD\r
+ /* Configure USART TXD pin */\r
+ gpio_configure_pin(PIN_USART0_TXD_IDX, PIN_USART0_TXD_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_CTS\r
+ /* Configure USART CTS pin */\r
+ gpio_configure_pin(PIN_USART0_CTS_IDX, PIN_USART0_CTS_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_RTS\r
+ /* Configure USART RTS pin */\r
+ gpio_configure_pin(PIN_USART0_RTS_IDX, PIN_USART0_RTS_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_SCK\r
+ /* Configure USART synchronous communication SCK pin */\r
+ gpio_configure_pin(PIN_USART0_SCK_IDX, PIN_USART0_SCK_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ADM3312_EN\r
+ /* Configure ADM3312 enable pin */\r
+ gpio_configure_pin(PIN_USART0_EN_IDX, PIN_USART0_EN_FLAGS);\r
+ gpio_set_pin_low(PIN_USART0_EN_IDX);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_TFDU4300_SD\r
+ /* Configure IrDA transceiver shutdown pin */\r
+ gpio_configure_pin(PIN_IRDA_SD_IDX, PIN_IRDA_SD_FLAGS);\r
+ gpio_set_pin_low(PIN_IRDA_SD_IDX);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ADM3485_RE\r
+ /* Configure RS485 transceiver ADM3485 RE pin */\r
+ gpio_configure_pin(PIN_RE_IDX, PIN_RE_FLAGS);\r
+ gpio_set_pin_low(PIN_RE_IDX);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_SMC_PSRAM\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D0, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D1, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D2, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D3, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D4, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D5, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D6, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D7, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D8, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D9, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D10, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D11, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D12, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D13, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D14, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D15, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NRD, PIN_EBI_NRD_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NWE, PIN_EBI_NWE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NCS0, PIN_EBI_NCS0_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_NBS0, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_NBS1, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A1, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A2, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A3, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A4, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A5, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A6, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A7, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A8, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A9, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A10, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A11, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A12, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A13, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A14, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A15, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A16, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A17, PIN_EBI_ADDR_BUS_FLAG1);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A18, PIN_EBI_ADDR_BUS_FLAG2);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A19, PIN_EBI_ADDR_BUS_FLAG2);\r
+ gpio_configure_pin(PIN_EBI_ADDR_BUS_A20, PIN_EBI_ADDR_BUS_FLAG2);\r
+#endif // #ifdef CONF_BOARD_SMC_PSRAM\r
+\r
+#ifdef CONF_BOARD_HX8347A\r
+ /* Configure LCD EBI pins */\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D0, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D1, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D2, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D3, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D4, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D5, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D6, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D7, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D8, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D9, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D10, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D11, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D12, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D13, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D14, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D15, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NRD, PIN_EBI_NRD_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NWE, PIN_EBI_NWE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NCS2, PIN_EBI_NCS2_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_LCD_RS, PIN_EBI_LCD_RS_FLAGS);\r
+#endif // #ifdef CONF_BOARD_HX8347A\r
+\r
+#ifdef CONF_BOARD_AAT3194\r
+ /* Configure Backlight control pin */\r
+ gpio_configure_pin(BOARD_BACKLIGHT, BOARD_BACKLIGHT_FLAG);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USB_PORT\r
+ /* Configure USB_ID (UOTGID) pin */\r
+ gpio_configure_pin(USB_ID_GPIO, USB_ID_FLAGS);\r
+ /* Configure USB_VBOF (UOTGVBOF) pin */\r
+ gpio_configure_pin(USB_VBOF_GPIO, USB_VBOF_FLAGS);\r
+ /* Configure FAULT detect pin */\r
+ gpio_configure_pin(USB_OVERCURRENT_DETECT_GPIO,\r
+ USB_OVERCURRENT_DETECT_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_MMA7341L\r
+ /* Configure MMA7341L mode set control pin */\r
+ gpio_configure_pin(PIN_MMA7341L_MODE, PIN_MMA7341L_MODE_FLAG);\r
+ /* Configure MMA7341L x,y,z axis output voltage pin */\r
+ gpio_configure_pin(PIN_MMA7341L_X_AXIS, PIN_MMA7341L_X_AXIS_FLAG);\r
+ gpio_configure_pin(PIN_MMA7341L_Y_AXIS, PIN_MMA7341L_Y_AXIS_FLAG);\r
+ gpio_configure_pin(PIN_MMA7341L_Z_AXIS, PIN_MMA7341L_Z_AXIS_FLAG);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ISO7816_RST\r
+ /* Configure ISO7816 card reset pin */\r
+ gpio_configure_pin(PIN_ISO7816_RST_IDX, PIN_ISO7816_RST_FLAG);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ISO7816\r
+ /* Configure ISO7816 interface TXD & SCK pin */\r
+ gpio_configure_pin(PIN_USART0_TXD_IDX, PIN_USART0_TXD_FLAGS);\r
+ gpio_configure_pin(PIN_USART0_SCK_IDX, PIN_USART0_SCK_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_CAN0\r
+ /* Configure the CAN0 TX and RX pins. */\r
+ gpio_configure_pin(PIN_CAN0_RX_IDX, PIN_CAN0_RX_FLAGS);\r
+ gpio_configure_pin(PIN_CAN0_TX_IDX, PIN_CAN0_TX_FLAGS);\r
+ /* Configure the transiver0 RS & EN pins. */\r
+ gpio_configure_pin(PIN_CAN0_TR_RS_IDX, PIN_CAN0_TR_RS_FLAGS);\r
+ gpio_configure_pin(PIN_CAN0_TR_EN_IDX, PIN_CAN0_TR_EN_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_CAN1\r
+ /* Configure the CAN1 TX and RX pin. */\r
+ gpio_configure_pin(PIN_CAN1_RX_IDX, PIN_CAN1_RX_FLAGS);\r
+ gpio_configure_pin(PIN_CAN1_TX_IDX, PIN_CAN1_TX_FLAGS);\r
+ /* Configure the transiver1 RS & EN pins. */\r
+ gpio_configure_pin(PIN_CAN1_TR_RS_IDX, PIN_CAN1_TR_RS_FLAGS);\r
+ gpio_configure_pin(PIN_CAN1_TR_EN_IDX, PIN_CAN1_TR_EN_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_SDRAMC\r
+ gpio_configure_pin(PIN_SDRAM_SDCKE, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDCS, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_RAS, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_CAS, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_BA0, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_BA1, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDWE, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_NBS0, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_NBS1, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA0, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA1, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA2, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA3, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA4, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA5, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA6, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA7, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA8, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA9, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA10, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA11, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA12, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA13, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA14, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_DATA15, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA0, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA1, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA2, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA3, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA4, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA5, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA6, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA7, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA8, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA9, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA10, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA11, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_SDA12, PIN_SDRAM_FLAGS);\r
+ gpio_configure_pin(PIN_SDRAM_EN, PIN_SDRAM_EN_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_EMAC\r
+ gpio_configure_pin(PIN_EEMAC_EREFCK, PIN_EMAC_FLAGS);\r
+ gpio_configure_pin(PIN_EMAC_ETX0, PIN_EMAC_FLAGS);\r
+ gpio_configure_pin(PIN_EMAC_ETX1, PIN_EMAC_FLAGS);\r
+ gpio_configure_pin(PIN_EMAC_ETXEN, PIN_EMAC_FLAGS);\r
+ gpio_configure_pin(PIN_EMAC_ECRSDV, PIN_EMAC_FLAGS);\r
+ gpio_configure_pin(PIN_EMAC_ERX0, PIN_EMAC_FLAGS);\r
+ gpio_configure_pin(PIN_EMAC_ERX1, PIN_EMAC_FLAGS);\r
+ gpio_configure_pin(PIN_EMAC_ERXER, PIN_EMAC_FLAGS);\r
+ gpio_configure_pin(PIN_EMAC_EMDC, PIN_EMAC_FLAGS);\r
+ gpio_configure_pin(PIN_EMAC_EMDIO, PIN_EMAC_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_NAND\r
+ gpio_configure_pin(PIN_EBI_NANDOE, PIN_EBI_NANDOE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDWE, PIN_EBI_NANDWE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDCLE, PIN_EBI_NANDCLE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDALE, PIN_EBI_NANDALE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_0, PIN_EBI_NANDIO_0_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_1, PIN_EBI_NANDIO_1_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_2, PIN_EBI_NANDIO_2_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_3, PIN_EBI_NANDIO_3_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_4, PIN_EBI_NANDIO_4_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_5, PIN_EBI_NANDIO_5_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_6, PIN_EBI_NANDIO_6_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NANDIO_7, PIN_EBI_NANDIO_7_FLAGS);\r
+ gpio_configure_pin(PIN_NF_CE_IDX, PIN_NF_CE_FLAGS);\r
+ gpio_configure_pin(PIN_NF_RB_IDX, PIN_NF_RB_FLAGS);\r
+#endif\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM3X-EK LEDs support package.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _LED_H_\r
+#define _LED_H_\r
+\r
+#include "gpio.h"\r
+\r
+/*! \brief Turns off the specified LEDs.\r
+ *\r
+ * \param led_gpio LED to turn off (LEDx_GPIO).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+#define LED_Off(led_gpio) gpio_set_pin_high(led_gpio)\r
+\r
+/*! \brief Turns on the specified LEDs.\r
+ *\r
+ * \param led_gpio LED to turn on (LEDx_GPIO).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+#define LED_On(led_gpio) gpio_set_pin_low(led_gpio)\r
+\r
+/*! \brief Toggles the specified LEDs.\r
+ *\r
+ * \param led_gpio LED to toggle (LEDx_GPIO).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+#define LED_Toggle(led_gpio) gpio_toggle_pin(led_gpio)\r
+\r
+#endif // _LED_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM3X-EK Board Definition.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X_EK_H_\r
+#define _SAM3X_EK_H_\r
+\r
+#include "compiler.h"\r
+#include "system_sam3x.h"\r
+#include "exceptions.h"\r
+\r
+/*#define BOARD_REV_A */\r
+#define BOARD_REV_B\r
+\r
+/* ------------------------------------------------------------------------ */\r
+\r
+/**\r
+ * \page sam3x_ek_opfreq "SAM3X-EK - Operating frequencies"\r
+ * This page lists several definition related to the board operating frequency\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_FREQ_*\r
+ * - \ref BOARD_MCK\r
+ */\r
+\r
+/*! Board oscillator settings */\r
+#define BOARD_FREQ_SLCK_XTAL (32768U)\r
+#define BOARD_FREQ_SLCK_BYPASS (32768U)\r
+#define BOARD_FREQ_MAINCK_XTAL (12000000U)\r
+#define BOARD_FREQ_MAINCK_BYPASS (12000000U)\r
+\r
+/*! Master clock frequency */\r
+#define BOARD_MCK CHIP_FREQ_CPU_MAX\r
+\r
+/* ------------------------------------------------------------------------ */\r
+\r
+/**\r
+ * \page sam3x_ek_board_info "SAM3X-EK - Board informations"\r
+ * This page lists several definition related to the board description.\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_NAME\r
+ */\r
+\r
+/*! Name of the board */\r
+#define BOARD_NAME "SAM3X-EK"\r
+/*! Board definition */\r
+#define sam3xek\r
+/*! Family definition (already defined) */\r
+#define sam3x\r
+/*! Core definition */\r
+#define cortexm3\r
+\r
+/* ------------------------------------------------------------------------ */\r
+\r
+/**\r
+ * \page sam3x_ek_piodef "SAM3X-EK - PIO definitions"\r
+ * This pages lists all the pio definitions. The constants\r
+ * are named using the following convention: PIN_* for a constant which defines\r
+ * a single Pin instance (but may include several PIOs sharing the same\r
+ * controller), and PINS_* for a list of Pin instances.\r
+ *\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * ADC\r
+ * - \ref PIN_ADC0_AD1\r
+ * - \ref PINS_ADC\r
+ *\r
+ */\r
+\r
+/*! ADC_AD1 pin definition. */\r
+#define PIN_ADC0_AD1 {PIO_PA3X1_AD1, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+#define PINS_ADC_TRIG PIO_PA11_IDX\r
+#define PINS_ADC_TRIG_FLAG (PIO_PERIPH_B | PIO_DEFAULT)\r
+/*! Pins ADC */\r
+#define PINS_ADC PIN_ADC0_AD1\r
+\r
+/**\r
+ * \file\r
+ * EBI\r
+ * - \ref PIN_EBI_DATA_BUS\r
+ * - \ref PIN_EBI_NRD\r
+ * - \ref PIN_EBI_NWE\r
+ * - \ref PIN_EBI_NCS0\r
+ * - \ref PIN_EBI_PSRAM_ADDR_BUS\r
+ * - \ref PIN_EBI_PSRAM_NBS\r
+ * - \ref PIN_EBI_A1\r
+ * - \ref PIN_EBI_NCS1\r
+ * - \ref PIN_EBI_LCD_RS\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* EBI */\r
+/* ------------------------------------------------------------------------ */\r
+/*! EBI Data Bus pins */\r
+#define PIN_EBI_DATA_BUS_D0 PIO_PC2_IDX\r
+#define PIN_EBI_DATA_BUS_D1 PIO_PC3_IDX\r
+#define PIN_EBI_DATA_BUS_D2 PIO_PC4_IDX\r
+#define PIN_EBI_DATA_BUS_D3 PIO_PC5_IDX\r
+#define PIN_EBI_DATA_BUS_D4 PIO_PC6_IDX\r
+#define PIN_EBI_DATA_BUS_D5 PIO_PC7_IDX\r
+#define PIN_EBI_DATA_BUS_D6 PIO_PC8_IDX\r
+#define PIN_EBI_DATA_BUS_D7 PIO_PC9_IDX\r
+#define PIN_EBI_DATA_BUS_D8 PIO_PC10_IDX\r
+#define PIN_EBI_DATA_BUS_D9 PIO_PC11_IDX\r
+#define PIN_EBI_DATA_BUS_D10 PIO_PC12_IDX\r
+#define PIN_EBI_DATA_BUS_D11 PIO_PC13_IDX\r
+#define PIN_EBI_DATA_BUS_D12 PIO_PC14_IDX\r
+#define PIN_EBI_DATA_BUS_D13 PIO_PC15_IDX\r
+#define PIN_EBI_DATA_BUS_D14 PIO_PC16_IDX\r
+#define PIN_EBI_DATA_BUS_D15 PIO_PC17_IDX\r
+#define PIN_EBI_DATA_BUS_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+/*! EBI NRD pin */\r
+#define PIN_EBI_NRD PIO_PA29_IDX\r
+#define PIN_EBI_NRD_FLAGS (PIO_PERIPH_B | PIO_PULLUP)\r
+#define PIN_EBI_NRD_MASK (1 << 29)\r
+#define PIN_EBI_NRD_PIO PIOB\r
+#define PIN_EBI_NRD_ID ID_PIOB\r
+#define PIN_EBI_NRD_TYPE PIO_PERIPH_B\r
+#define PIN_EBI_NRD_ATTR PIO_PULLUP\r
+/*! EBI NWE pin */\r
+#define PIN_EBI_NWE PIO_PC18_IDX\r
+#define PIN_EBI_NWE_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+#define PIN_EBI_NWE_MASK (1 << 18)\r
+#define PIN_EBI_NWE_PIO PIOC\r
+#define PIN_EBI_NWE_ID ID_PIOC\r
+#define PIN_EBI_NWE_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_NWE_ATTR PIO_PULLUP\r
+/*! EBI NCS0 pin */\r
+#define PIN_EBI_NCS0 PIO_PA6_IDX\r
+#define PIN_EBI_NCS0_FLAGS (PIO_PERIPH_B | PIO_PULLUP)\r
+#define PIN_EBI_NCS0_MASK (1 << 6)\r
+#define PIN_EBI_NCS0_PIO PIOA\r
+#define PIN_EBI_NCS0_ID ID_PIOA\r
+#define PIN_EBI_NCS0_TYPE PIO_PERIPH_B\r
+#define PIN_EBI_NCS0_ATTR PIO_PULLUP\r
+/*! EBI address bus pins */\r
+#define PIN_EBI_ADDR_BUS_A0 PIO_PC21_IDX\r
+#define PIN_EBI_ADDR_BUS_NBS0 PIO_PC21_IDX\r
+#define PIN_EBI_ADDR_BUS_A1 PIO_PC22_IDX\r
+#define PIN_EBI_ADDR_BUS_NBS1 PIO_PD10_IDX\r
+#define PIN_EBI_ADDR_BUS_A2 PIO_PC23_IDX\r
+#define PIN_EBI_ADDR_BUS_A3 PIO_PC24_IDX\r
+#define PIN_EBI_ADDR_BUS_A4 PIO_PC25_IDX\r
+#define PIN_EBI_ADDR_BUS_A5 PIO_PC26_IDX\r
+#define PIN_EBI_ADDR_BUS_A6 PIO_PC27_IDX\r
+#define PIN_EBI_ADDR_BUS_A7 PIO_PC28_IDX\r
+#define PIN_EBI_ADDR_BUS_A8 PIO_PC29_IDX\r
+#define PIN_EBI_ADDR_BUS_A9 PIO_PC30_IDX\r
+#define PIN_EBI_ADDR_BUS_A10 PIO_PD0_IDX\r
+#define PIN_EBI_ADDR_BUS_A11 PIO_PD1_IDX\r
+#define PIN_EBI_ADDR_BUS_A12 PIO_PD2_IDX\r
+#define PIN_EBI_ADDR_BUS_A13 PIO_PD3_IDX\r
+#define PIN_EBI_ADDR_BUS_A14 PIO_PD4_IDX\r
+#define PIN_EBI_ADDR_BUS_A15 PIO_PD5_IDX\r
+#define PIN_EBI_ADDR_BUS_A16 PIO_PD6_IDX\r
+#define PIN_EBI_ADDR_BUS_A17 PIO_PD7_IDX\r
+#define PIN_EBI_ADDR_BUS_FLAG1 (PIO_PERIPH_A | PIO_PULLUP)\r
+#define PIN_EBI_ADDR_BUS_A18 PIO_PA25_IDX\r
+#define PIN_EBI_ADDR_BUS_A19 PIO_PA26_IDX\r
+#define PIN_EBI_ADDR_BUS_A20 PIO_PA27_IDX\r
+#define PIN_EBI_ADDR_BUS_FLAG2 (PIO_PERIPH_B | PIO_PULLUP)\r
+/*! EBI pin for LCD CS */\r
+#define PIN_EBI_NCS2 PIO_PB24_IDX\r
+#define PIN_EBI_NCS2_FLAGS (PIO_PERIPH_B | PIO_PULLUP)\r
+#define PIN_EBI_NCS2_MASK (1 << 24)\r
+#define PIN_EBI_NCS2_PIO PIOB\r
+#define PIN_EBI_NCS2_ID ID_PIOB\r
+#define PIN_EBI_NCS2_TYPE PIO_PERIPH_B\r
+#define PIN_EBI_NCS2_ATTR PIO_PULLUP\r
+/*! EBI pin for LCD RS */\r
+#define PIN_EBI_LCD_RS PIO_PC22_IDX\r
+#define PIN_EBI_LCD_RS_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+#define PIN_EBI_LCD_RS_MASK (1 << 22)\r
+#define PIN_EBI_LCD_RS_PIO PIOC\r
+#define PIN_EBI_LCD_RS_ID ID_PIOC\r
+#define PIN_EBI_LCD_RS_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_LCD_RS_ATTR PIO_PULLUP\r
+\r
+/**\r
+ * \file\r
+ * LEDs\r
+ * - \ref PIN_USER_LED1\r
+ * - \ref PIN_USER_LED2\r
+ * - \ref PIN_USER_LED3\r
+ * - \ref PIN_POWER_LED\r
+ * - \ref PINS_LEDS\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* LEDS */\r
+/* ------------------------------------------------------------------------ */\r
+/*! LED #0 pin definition (GREEN). D4 */\r
+#define PIN_USER_LED1 {PIO_PB13, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT}\r
+/*! LED #1 pin definition (AMBER). D3 */\r
+#define PIN_USER_LED2 {PIO_PB12, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT}\r
+/*! LED #1 pin definition (BLUE). D2 */\r
+#define PIN_USER_LED3 {PIO_PA12, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}\r
+/*! LED #2 pin definition (RED). D5 */\r
+#define PIN_POWER_LED {PIO_PA13, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}\r
+\r
+#define LED_GREEN 0\r
+#define LED_AMBER 1\r
+#define LED_BLUE 2\r
+#define LED_RED 3\r
+\r
+/*! List of all LEDs definitions. */\r
+#define PINS_LEDS PIN_USER_LED1, PIN_USER_LED2, PIN_USER_LED3, PIN_POWER_LED\r
+\r
+/*! LED #0 pin definition (BLUE). */\r
+#define LED_0_NAME "blue LED D2"\r
+#define LED0_GPIO (PIO_PA12_IDX)\r
+#define LED0_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+#define PIN_LED_0 {1 << 12, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+#define PIN_LED_0_MASK (1 << 12)\r
+#define PIN_LED_0_PIO PIOA\r
+#define PIN_LED_0_ID ID_PIOA\r
+#define PIN_LED_0_TYPE PIO_OUTPUT_0\r
+#define PIN_LED_0_ATTR PIO_DEFAULT\r
+\r
+/*! LED #1 pin definition (GREEN). */\r
+#define LED_1_NAME "green LED D4"\r
+#define LED1_GPIO (PIO_PB13_IDX)\r
+#define LED1_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+#define PIN_LED_1 {1 << 13, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT}\r
+#define PIN_LED_1_MASK (1 << 13)\r
+#define PIN_LED_1_PIO PIOB\r
+#define PIN_LED_1_ID ID_PIOB\r
+#define PIN_LED_1_TYPE PIO_OUTPUT_1\r
+#define PIN_LED_1_ATTR PIO_DEFAULT\r
+\r
+/*! LED #2 pin detection (AMBER). */\r
+#define LED2_GPIO (PIO_PB12_IDX)\r
+#define LED2_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+/*! LED #3 pin detection (power) */\r
+#define LED3_GPIO (PIO_PA13_IDX)\r
+#define LED3_FLAGS (PIO_TYPE_PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+/**\r
+ * \file\r
+ * Push buttons\r
+ * - \ref PIN_PB_LEFT_CLICK\r
+ * - \ref PIN_PB_RIGHT_CLICK\r
+ * - \ref PINS_PUSHBUTTONS\r
+ * - \ref PUSHBUTTON_BP1\r
+ * - \ref PUSHBUTTON_BP2\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* PUSHBUTTONS */\r
+/* ------------------------------------------------------------------------ */\r
+\r
+/** Push button LEFT CLICK definition.\r
+ * Attributes = pull-up + debounce + interrupt on falling edge. */\r
+#define PIN_PB_LEFT_CLICK {PIO_PE7, PIOE, ID_PIOE, PIO_INPUT,\\r
+ PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}\r
+\r
+/** Push button RIGHT CLICK definition.\r
+ * Attributes = pull-up + debounce + interrupt on falling edge. */\r
+#define PIN_PB_RIGHT_CLICK {PIO_PB23, PIOB, ID_PIOB, PIO_INPUT,\\r
+ PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}\r
+\r
+/*! List of all push button definitions. */\r
+#define PINS_PUSHBUTTONS PIN_PB_LEFT_CLICK, PIN_PB_RIGHT_CLICK\r
+\r
+/*! Push button #1 index. */\r
+#define PUSHBUTTON_BP1 0\r
+/*! Push button #2 index. */\r
+#define PUSHBUTTON_BP2 1\r
+\r
+/*! Push button LEFT CLICK index. */\r
+#define PUSHBUTTON_LEFT 0\r
+/*! Push button RIGHT CLICK index. */\r
+#define PUSHBUTTON_RIGHT 1\r
+\r
+/** Push button #0 definition.\r
+ * Attributes = pull-up + debounce + interrupt on rising edge. */\r
+#define PUSHBUTTON_1_NAME "LEFT CLICK"\r
+#define GPIO_PUSH_BUTTON_1 (PIO_PE7_IDX)\r
+#define GPIO_PUSH_BUTTON_1_FLAGS\\r
+ (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)\r
+\r
+#define PIN_PUSHBUTTON_1 {PIO_PE7, PIOE, ID_PIOE, PIO_INPUT,\\r
+ PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}\r
+#define PIN_PUSHBUTTON_1_MASK PIO_PE7\r
+#define PIN_PUSHBUTTON_1_PIO PIOE\r
+#define PIN_PUSHBUTTON_1_ID ID_PIOE\r
+#define PIN_PUSHBUTTON_1_TYPE PIO_INPUT\r
+#define PIN_PUSHBUTTON_1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)\r
+\r
+/** Push button #1 definition.\r
+ * Attributes = pull-up + debounce + interrupt on falling edge. */\r
+#define PUSHBUTTON_2_NAME "RIGHT CLICK"\r
+#define GPIO_PUSH_BUTTON_2 (PIO_PB23_IDX)\r
+#define GPIO_PUSH_BUTTON_2_FLAGS\\r
+ (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE)\r
+\r
+#define PIN_PUSHBUTTON_2 {PIO_PB23, PIOB, ID_PIOB, PIO_INPUT,\\r
+ PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}\r
+#define PIN_PUSHBUTTON_2_MASK PIO_PB23\r
+#define PIN_PUSHBUTTON_2_PIO PIOB\r
+#define PIN_PUSHBUTTON_2_ID ID_PIOB\r
+#define PIN_PUSHBUTTON_2_TYPE PIO_INPUT\r
+#define PIN_PUSHBUTTON_2_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE)\r
+\r
+#define PIN_TC0_TIOA0 (PIO_PB25_IDX)\r
+#define PIN_TC0_TIOA0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+#define PIN_TC0_TIOA1 (PIO_PA2_IDX)\r
+#define PIN_TC0_TIOA1_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+#define PIN_TC0_TIOA1_PIO PIOA\r
+#define PIN_TC0_TIOA1_MASK PIO_PA2\r
+#define PIN_TC0_TIOA1_ID ID_PIOA\r
+#define PIN_TC0_TIOA1_TYPE PIO_PERIPH_A\r
+#define PIN_TC0_TIOA1_ATTR PIO_DEFAULT\r
+\r
+#define PIN_TC0_TIOA2 (PIO_PA5_IDX)\r
+#define PIN_TC0_TIOA2_FLAGS (PIO_INPUT | PIO_DEFAULT)\r
+\r
+#define PIN_TC0_TIOA2_PIO PIOA\r
+#define PIN_TC0_TIOA2_MASK PIO_PA5\r
+#define PIN_TC0_TIOA2_ID ID_PIOA\r
+#define PIN_TC0_TIOA2_TYPE PIO_INPUT\r
+#define PIN_TC0_TIOA2_ATTR PIO_DEFAULT\r
+\r
+/**\r
+ * \file\r
+ * PWMC\r
+ * - \ref PIN_PWMC_PWMH0\r
+ * - \ref PIN_PWMC_PWML0\r
+ * - \ref PIN_PWMC_PWMH1\r
+ * - \ref PIN_PWMC_PWML1\r
+ * - \ref PIN_PWMC_PWMH2\r
+ * - \ref PIN_PWMC_PWML2\r
+ * - \ref PIN_PWMC_PWMH3\r
+ * - \ref PIN_PWMC_PWML3\r
+ * - \ref PIN_PWM_LED0\r
+ * - \ref PIN_PWM_LED1\r
+ * - \ref PIN_PWM_LED2\r
+ * - \ref CHANNEL_PWM_LED0\r
+ * - \ref CHANNEL_PWM_LED1\r
+ * - \ref CHANNEL_PWM_LED2\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* PWM */\r
+/* ------------------------------------------------------------------------ */\r
+/*! PWMC PWM0 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH0\\r
+ {PIO_PB12B_PWMH0, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_PWMC_PWMH0_TRIG PIO_PB12_IDX\r
+#define PIN_PWMC_PWMH0_TRIG_FLAG PIO_PERIPH_B | PIO_DEFAULT\r
+/*! PWMC PWM0 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML0\\r
+ {PIO_PA21B_PWML0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+/*! PWMC PWM1 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH1\\r
+ {PIO_PB13B_PWMH1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}\r
+/*! PWMC PWM1 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML1\\r
+ {PIO_PB17B_PWML1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}\r
+/*! PWMC PWM2 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH2\\r
+ {PIO_PA13B_PWMH2, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+/*! PWMC PWM2 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML2\\r
+ {PIO_PA20B_PWML2, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+/*! PWMC PWM3 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH3\\r
+ {PIO_PA9B_PWMH3, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+/*! PWMC PWM3 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML3\\r
+ {PIO_PC8B_PWML3, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}\r
+/*! PWM pins definition for LED0 */\r
+#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0\r
+/*! PWM pins definition for LED1 */\r
+#define PIN_PWM_LED1 PIN_PWMC_PWMH1, PIN_PWMC_PWML1\r
+/*! PWM pins definition for LED2 */\r
+#define PIN_PWM_LED2 PIN_PWMC_PWMH2, PIN_PWMC_PWML2\r
+/*! PWM channel for LED0 */\r
+#define CHANNEL_PWM_LED0 0\r
+/*! PWM channel for LED1 */\r
+#define CHANNEL_PWM_LED1 1\r
+/*! PWM channel for LED2 */\r
+#define CHANNEL_PWM_LED2 2\r
+\r
+/*! PWM LED0 pin definitions. */\r
+#define PIN_PWM_LED0_GPIO PIO_PB13_IDX\r
+#define PIN_PWM_LED0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define PIN_PWM_LED0_CHANNEL PWM_CHANNEL_1\r
+\r
+/*! PWM LED1 pin definitions. */\r
+#define PIN_PWM_LED1_GPIO PIO_PB12_IDX\r
+#define PIN_PWM_LED1_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define PIN_PWM_LED1_CHANNEL PWM_CHANNEL_0\r
+\r
+/*! PWM LED2 pin definitions. */\r
+#define PIN_PWM_LED2_GPIO PIO_PA12_IDX\r
+#define PIN_PWM_LED2_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+/**\r
+ * \file\r
+ * SPI\r
+ * - \ref PIN_SPI_MISO\r
+ * - \ref PIN_SPI_MOSI\r
+ * - \ref PIN_SPI_SPCK\r
+ * - \ref PINS_SPI\r
+ * - \ref PIN_SPI_NPCS0\r
+ * - \ref PIN_SPI1_MISO\r
+ * - \ref PIN_SPI1_MOSI\r
+ * - \ref PIN_SPI1_SPCK\r
+ * - \ref PINS_SPI1\r
+ * - \ref PIN_SPI1_NPCS0\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* SPI */\r
+/* ------------------------------------------------------------------------ */\r
+/*! SPI MISO pin definition. */\r
+#define PIN_SPI0_MISO\\r
+ {PIO_PA25A_SPI0_MISO, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! SPI MOSI pin definition. */\r
+#define PIN_SPI0_MOSI\\r
+ {PIO_PA26A_SPI0_MOSI, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! SPI SPCK pin definition. */\r
+#define PIN_SPI0_SPCK\\r
+ {PIO_PA27A_SPI0_SPCK, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! SPI chip select pin definition. */\r
+#define PIN_SPI0_NPCS0\\r
+ {PIO_PA28A_SPI0_NPCS0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! List of SPI pin definitions (MISO, MOSI & SPCK). */\r
+#define PINS_SPI0 PIN_SPI0_MISO, PIN_SPI0_MOSI, PIN_SPI0_SPCK\r
+\r
+/*! SPI0 MISO pin definition. */\r
+#define SPI0_MISO_GPIO (PIO_PA25_IDX)\r
+#define SPI0_MISO_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! SPI0 MOSI pin definition. */\r
+#define SPI0_MOSI_GPIO (PIO_PA26_IDX)\r
+#define SPI0_MOSI_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! SPI0 SPCK pin definition. */\r
+#define SPI0_SPCK_GPIO (PIO_PA27_IDX)\r
+#define SPI0_SPCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/*! SPI0 chip select 0 pin definition. (Only one configuration is possible) */\r
+#define SPI0_NPCS0_GPIO (PIO_PA28_IDX)\r
+#define SPI0_NPCS0_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! SPI0 chip select 1 pin definition. (multiple configurations are possible) */\r
+#define SPI0_NPCS1_PA29_GPIO (PIO_PA29_IDX)\r
+#define SPI0_NPCS1_PA29_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define SPI0_NPCS1_PB20_GPIO (PIO_PB20_IDX)\r
+#define SPI0_NPCS1_PB20_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+/*! SPI0 chip select 2 pin definition. (multiple configurations are possible) */\r
+#define SPI0_NPCS2_PA30_GPIO (PIO_PA30_IDX)\r
+#define SPI0_NPCS2_PA30_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define SPI0_NPCS2_PB21_GPIO (PIO_PB21_IDX)\r
+#define SPI0_NPCS2_PB21_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+/*! SPI0 chip select 3 pin definition. (multiple configurations are possible) */\r
+#define SPI0_NPCS3_PA31_GPIO (PIO_PA31_IDX)\r
+#define SPI0_NPCS3_PA31_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define SPI0_NPCS3_PB23_GPIO (PIO_PB23_IDX)\r
+#define SPI0_NPCS3_PB23_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+/*! SPI1 MISO pin definition. */\r
+#define PIN_SPI1_MISO\\r
+ {PIO_PE28A_SPI1_MISO, PIOE, ID_PIOE, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! SPI1 MOSI pin definition. */\r
+#define PIN_SPI1_MOSI\\r
+ {PIO_PE29A_SPI1_MOSI, PIOE, ID_PIOE, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! SPI1 SPCK pin definition. */\r
+#define PIN_SPI1_SPCK\\r
+ {PIO_PE30A_SPI1_SPCK, PIOE, ID_PIOE, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! SPI1 chip select pin definition. */\r
+#define PIN_SPI1_NPCS0\\r
+ {PIO_PE31A_SPI1_NPCS0, PIOE, ID_PIOE, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! List of SPI1 pin definitions (MISO, MOSI & SPCK). */\r
+#define PINS_SPI1 PIN_SPI1_MISO, PIN_SPI1_MOSI, PIN_SPI1_SPCK\r
+\r
+/*! SPI1 MISO pin definition. */\r
+#define SPI1_MISO_GPIO (PIO_PE28_IDX)\r
+#define SPI1_MISO_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! SPI1 MOSI pin definition. */\r
+#define SPI1_MOSI_GPIO (PIO_PE29_IDX)\r
+#define SPI1_MOSI_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! SPI1 SPCK pin definition. */\r
+#define SPI1_SPCK_GPIO (PIO_PE30_IDX)\r
+#define SPI1_SPCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! SPI1 chip select 0 pin definition. (Only one configuration is possible) */\r
+#define SPI1_NPCS0_GPIO (PIO_PE31_IDX)\r
+#define SPI1_NPCS0_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! SPI1 chip select 1 pin definition. (Only one configuration is possible) */\r
+#define SPI1_NPCS1_GPIO (PIO_PF0_IDX)\r
+#define SPI1_NPCS1_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! SPI1 chip select 2 pin definition. (Only one configuration is possible) */\r
+#define SPI1_NPCS2_GPIO (PIO_PF1_IDX)\r
+#define SPI1_NPCS2_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! SPI1 chip select 3 pin definition. (Only one configuration is possible) */\r
+#define SPI1_NPCS3_GPIO (PIO_PF2_IDX)\r
+#define SPI1_NPCS3_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/**\r
+ * \file\r
+ * SSC\r
+ * - \ref PIN_SSC_TD\r
+ * - \ref PIN_SSC_TK\r
+ * - \ref PIN_SSC_TF\r
+ * - \ref PINS_SSC_CODEC\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* SSC */\r
+/* ------------------------------------------------------------------------ */\r
+/*! SSC pin Transmitter Data (TD) */\r
+#define PIN_SSC_TD {PIO_PA16B_TD, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+/*! SSC pin Transmitter Clock (TK) */\r
+#define PIN_SSC_TK {PIO_PA14B_TK, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+/*! SSC pin Transmitter FrameSync (TF) */\r
+#define PIN_SSC_TF {PIO_PA15B_TF, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+\r
+/*! SSC pin Receiver Data (RD) */\r
+#define PIN_SSC_RD {PIO_PB18A_RD, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! SSC pin Receiver Clock (RK) */\r
+#define PIN_SSC_RK {PIO_PB19A_RK, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! SSC pin Receiver FrameSync (RF) */\r
+#define PIN_SSC_RF {PIO_PB17A_RF, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+/*! SSC pins definition for codec. */\r
+#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF,\\r
+ PIN_SSC_RD, PIN_SSC_RK, PIN_SSC_RF\r
+\r
+/**\r
+ * \file\r
+ * PCK0\r
+ * - \ref PIN_PCK0\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* PCK */\r
+/* ------------------------------------------------------------------------ */\r
+/*! PCK0 */\r
+#define PIN_PCK0 (PIO_PB22_IDX)\r
+#define PIN_PCK0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+#define PIN_PCK_0_MASK PIO_PB22\r
+#define PIN_PCK_0_PIO PIOB\r
+#define PIN_PCK_0_ID ID_PIOB\r
+#define PIN_PCK_0_TYPE PIO_PERIPH_B\r
+#define PIN_PCK_0_ATTR PIO_DEFAULT\r
+\r
+/**\r
+ * \file\r
+ * HSMCI\r
+ * - \ref PINS_HSMCI\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* HSMCI */\r
+/* ------------------------------------------------------------------------ */\r
+/*! HSMCI pins definition. */\r
+#define PINS_HSMCI\\r
+ { PIO_PA20A_MCCDA | PIO_PA19A_MCCK | PIO_PA21A_MCDA0 | PIO_PA22A_MCDA1\\r
+ | PIO_PA23A_MCDA2 | PIO_PA24A_MCDA3,\\r
+ PIOA, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP },\\r
+ { PIO_PD0B_MCDA4 | PIO_PD1B_MCDA5 | PIO_PD2B_MCDA6 | PIO_PD3B_MCDA7,\\r
+ PIOD, ID_PIOD, PIO_PERIPH_B, PIO_PULLUP},\\r
+ { PIO_PE20B_MCCDB | PIO_PE22B_MCDB0 | PIO_PE24B_MCDB1 | PIO_PE26B_MCDB2\\r
+ | PIO_PE27B_MCDB3,\\r
+ PIOE, ID_PIOE, PIO_PERIPH_B, PIO_PULLUP }\r
+/*! HSMCI pin Card Detect. */\r
+#define PIN_HSMCI_CD {PIO_PE6, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP}\r
+\r
+/**\r
+ * \file\r
+ * UART\r
+ * - \ref PINS_UART\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* UART */\r
+/* ------------------------------------------------------------------------ */\r
+/*! UART pins (UTXD0 and URXD0) definitions, PA8,9. */\r
+#define PINS_UART (PIO_PA8A_URXD | PIO_PA9A_UTXD)\r
+#define PINS_UART_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+#define PINS_UART_MASK (PIO_PA8A_URXD | PIO_PA9A_UTXD)\r
+#define PINS_UART_PIO PIOA\r
+#define PINS_UART_ID ID_PIOA\r
+#define PINS_UART_TYPE PIO_PERIPH_A\r
+#define PINS_UART_ATTR PIO_DEFAULT\r
+\r
+/**\r
+ * \file\r
+ * USART0\r
+ * - \ref PIN_USART0_RXD\r
+ * - \ref PIN_USART0_TXD\r
+ * - \ref PIN_USART0_CTS\r
+ * - \ref PIN_USART0_RTS\r
+ * - \ref PIN_USART0_SCK\r
+ *\r
+ * - \ref PIN_USART0_EN\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* USART0 */\r
+/* ------------------------------------------------------------------------ */\r
+/*! USART0 pin RX */\r
+#define PIN_USART0_RXD\\r
+ {PIO_PA10A_RXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_RXD_IDX (PIO_PA10_IDX)\r
+#define PIN_USART0_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! USART0 pin TX */\r
+#define PIN_USART0_TXD\\r
+ {PIO_PA11A_TXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_TXD_IDX (PIO_PA11_IDX)\r
+#define PIN_USART0_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! USART0 pin CTS */\r
+#define PIN_USART0_CTS\\r
+ {PIO_PB26A_CTS0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_CTS_IDX (PIO_PB26_IDX)\r
+#define PIN_USART0_CTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! USART0 pin RTS */\r
+#define PIN_USART0_RTS\\r
+ {PIO_PB25A_RTS0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_RTS_IDX (PIO_PB25_IDX)\r
+#define PIN_USART0_RTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! USART0 pin SCK */\r
+#define PIN_USART0_SCK\\r
+ {PIO_PA17B_SCK0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_USART0_SCK_IDX (PIO_PA17_IDX)\r
+#define PIN_USART0_SCK_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+/*! USART0 pin ENABLE */\r
+#define PIN_USART0_EN\\r
+ {PIO_PE14, PIOE, ID_PIOE, PIO_OUTPUT_0, PIO_DEFAULT}\r
+#define PIN_USART0_EN_IDX (PIO_PE14_IDX)\r
+#define PIN_USART0_EN_FLAGS (PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+/**\r
+ * \file\r
+ * USART1\r
+ * - \ref PIN_USART1_RXD\r
+ * - \ref PIN_USART1_TXD\r
+ * - \ref PIN_USART1_CTS\r
+ * - \ref PIN_USART1_RTS\r
+ * - \ref PIN_USART1_SCK\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* USART1 */\r
+/* ------------------------------------------------------------------------ */\r
+/*! USART1 pin RX */\r
+#define PIN_USART1_RXD\\r
+ {PIO_PA12A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_RXD_IDX (PIO_PA12_IDX)\r
+#define PIN_USART1_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! USART1 pin TX */\r
+#define PIN_USART1_TXD\\r
+ {PIO_PA13A_TXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_TXD_IDX (PIO_PA13_IDX)\r
+#define PIN_USART1_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! USART1 pin CTS */\r
+#define PIN_USART1_CTS\\r
+ {PIO_PA15A_CTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_CTS_IDX (PIO_PA15_IDX)\r
+#define PIN_USART1_CTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! USART1 pin RTS */\r
+#define PIN_USART1_RTS\\r
+ {PIO_PA14A_RTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_RTS_IDX (PIO_PA14_IDX)\r
+#define PIN_USART1_RTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! USART1 pin SCK */\r
+#define PIN_USART1_SCK\\r
+ {PIO_PA16A_SCK1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_SCK_IDX (PIO_PA16_IDX)\r
+#define PIN_USART1_SCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/**\r
+ * \file\r
+ * USART3\r
+ * - \ref PIN_USART3_RXD\r
+ * - \ref PIN_USART3_TXD\r
+ * - \ref PIN_USART3_CTS\r
+ * - \ref PIN_USART3_RTS\r
+ * - \ref PIN_USART3_SCK\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* USART3 */\r
+/* ------------------------------------------------------------------------ */\r
+/*! USART1 pin RX */\r
+#define PIN_USART3_RXD\\r
+ {PIO_PD5B_RXD3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_USART3_RXD_IDX (PIO_PD5_IDX)\r
+#define PIN_USART3_RXD_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+/*! USART1 pin TX */\r
+#define PIN_USART3_TXD\\r
+ {PIO_PD4B_TXD3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_USART3_TXD_IDX (PIO_PD4_IDX)\r
+#define PIN_USART3_TXD_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+/*! USART1 pin CTS */\r
+#define PIN_USART3_CTS\\r
+ {PIO_PF4A_CTS3, PIOF, ID_PIOF, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART3_CTS_IDX (PIO_PF4_IDX)\r
+#define PIN_USART3_CTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! USART1 pin RTS */\r
+#define PIN_USART3_RTS\\r
+ {PIO_PF5A_RTS3, PIOF, ID_PIOF, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART3_RTS_IDX (PIO_PF5_IDX)\r
+#define PIN_USART3_RTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! USART1 pin SCK */\r
+#define PIN_USART3_SCK\\r
+ {PIO_PE16B_SCK3, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_USART3_SCK_IDX (PIO_PE16_IDX)\r
+#define PIN_USART3_SCK_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+/**\r
+ * \file\r
+ * USB\r
+ * - \ref PIN_USBOTG_VBOF\r
+ * - \ref PIN_USB_FAULT\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* USB */\r
+/* ------------------------------------------------------------------------ */\r
+/*! USB OTG VBus On/Off: Bus Power Control Port. */\r
+#define PIN_UOTGHS_VBOF { PIO_PB10, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP }\r
+/*! USB OTG Identification: Mini Connector Identification Port. */\r
+#define PIN_UOTGHS_ID { PIO_PB11, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP }\r
+/*! USB Fault monitoring pin definition. */\r
+#define PIN_UOTGHS_FAULT { PIO_PE5, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP }\r
+\r
+/*! Multiplexed pin used for USB ID pin: */\r
+#define USB_ID_GPIO (PIO_PB11_IDX)\r
+#define USB_ID_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+/*! Multiplexed pin used for USB_VBOF: */\r
+#define USB_VBOF_GPIO (PIO_PB10_IDX)\r
+#define USB_VBOF_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/*! Active level of the USB_VBOF output pin. */\r
+#define USB_VBOF_ACTIVE_LEVEL LOW\r
+/*! USB overcurrent detection pin. */\r
+#define USB_OVERCURRENT_DETECT_PIN PIO_PE5_IDX\r
+#define USB_OVERCURRENT_DETECT_GPIO (PIO_PE5_IDX)\r
+#define USB_OVERCURRENT_DETECT_FLAGS (PIO_INPUT | PIO_PULLUP)\r
+\r
+/* ------------------------------------------------------------------------ */\r
+\r
+/**\r
+ * \page sam3x_ek_usb "SAM3X-EK - USB device"\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_USB_BMATTRIBUTES\r
+ * - \ref CHIP_USB_UDP\r
+ * - \ref CHIP_USB_PULLUP_INTERNAL\r
+ * - \ref CHIP_USB_NUMENDPOINTS\r
+ * - \ref CHIP_USB_ENDPOINTS_MAXPACKETSIZE\r
+ * - \ref CHIP_USB_ENDPOINTS_BANKS\r
+ */\r
+\r
+/*! USB attributes configuration descriptor (bus or self powered, remote wakeup) */\r
+#define BOARD_USB_BMATTRIBUTES\\r
+ USBConfigurationDescriptor_SELFPOWERED_RWAKEUP\r
+\r
+/*! Indicates chip has an internal pull-up. */\r
+#define CHIP_USB_PULLUP_INTERNAL\r
+\r
+/*! Number of USB endpoints */\r
+#define CHIP_USB_NUMENDPOINTS 10\r
+\r
+/*! Endpoints max packet size */\r
+#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i)\\r
+ ((i == 0) ? 64 : 1024)\r
+\r
+/*! Endpoints Number of Bank */\r
+#define CHIP_USB_ENDPOINTS_BANKS(i)\\r
+ ((i == 0) ? 1 :\\r
+ ((i == 1) ? 3 :\\r
+ ((i == 2) ? 3 : 2)))\r
+\r
+/**\r
+ * \file\r
+ * CAN\r
+ * \ref PIN_CAN0_TRANSCEIVER_RXEN\r
+ * \ref PIN_CAN0_TRANSCEIVER_RS\r
+ * \ref PIN_CAN0_TXD\r
+ * \ref PIN_CAN0_RXD\r
+ * \ref PINS_CAN0\r
+ *\r
+ * \ref PIN_CAN1_TRANSCEIVER_RXEN\r
+ * \ref PIN_CAN1_TRANSCEIVER_RS\r
+ * \ref PIN_CAN1_TXD\r
+ * \ref PIN_CAN1_RXD\r
+ * \ref PINS_CAN1\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* CAN */\r
+/* ------------------------------------------------------------------------ */\r
+\r
+/*! CAN0 RXEN: Select input for high speed mode or ultra low current sleep mode */\r
+#define PIN_CAN0_TRANSCEIVER_RXEN\\r
+ { PIO_PB21, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT }\r
+\r
+/*! CAN0 RS: Select input for high speed mode or low-current standby mode */\r
+#define PIN_CAN0_TRANSCEIVER_RS\\r
+ { PIO_PB20, PIOB, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }\r
+\r
+/*! CAN0 TXD: Transmit data input */\r
+#define PIN_CAN0_TXD\\r
+ { PIO_PA0A_CANTX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }\r
+\r
+/*! CAN0 RXD: Receive data output */\r
+#define PIN_CAN0_RXD\\r
+ { PIO_PA1A_CANRX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }\r
+\r
+/*! List of all CAN0 definitions. */\r
+#define PINS_CAN0 PIN_CAN0_TXD, PIN_CAN0_RXD\r
+\r
+/** CAN0 transceiver PIN RS. */\r
+#define PIN_CAN0_TR_RS_IDX PIO_PB20_IDX\r
+#define PIN_CAN0_TR_RS_FLAGS (PIO_TYPE_PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+/** CAN0 transceiver PIN EN. */\r
+#define PIN_CAN0_TR_EN_IDX PIO_PB21_IDX\r
+#define PIN_CAN0_TR_EN_FLAGS (PIO_TYPE_PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+/** CAN0 PIN RX. */\r
+#define PIN_CAN0_RX_IDX (PIO_PA1_IDX)\r
+#define PIN_CAN0_RX_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/** CAN0 PIN TX. */\r
+#define PIN_CAN0_TX_IDX (PIO_PA0_IDX)\r
+#define PIN_CAN0_TX_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/*! CAN1 RXEN: Select input for high speed mode or ultra low current sleep mode */\r
+#define PIN_CAN1_TRANSCEIVER_RXEN\\r
+ { PIO_PE16, PIOE, ID_PIOE, PIO_OUTPUT_1, PIO_DEFAULT }\r
+\r
+/*! CAN1 RS: Select input for high speed mode or low-current standby mode */\r
+#define PIN_CAN1_TRANSCEIVER_RS\\r
+ { PIO_PE15, PIOE, ID_PIOE, PIO_OUTPUT_0, PIO_DEFAULT }\r
+\r
+/*! CAN1 TXD: Transmit data input */\r
+#define PIN_CAN1_TXD\\r
+ { PIO_PB14A_CANTX1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT }\r
+\r
+/*! CAN1 RXD: Receive data output */\r
+#define PIN_CAN1_RXD\\r
+ { PIO_PB15A_CANRX1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT }\r
+\r
+/*! List of all CAN1 definitions. */\r
+#define PINS_CAN1 PIN_CAN1_TXD, PIN_CAN1_RXD\r
+\r
+/** CAN1 transceiver PIN RS. */\r
+#define PIN_CAN1_TR_RS_IDX PIO_PE15_IDX\r
+#define PIN_CAN1_TR_RS_FLAGS (PIO_TYPE_PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+/** CAN1 transceiver PIN EN. */\r
+#define PIN_CAN1_TR_EN_IDX PIO_PE16_IDX\r
+#define PIN_CAN1_TR_EN_FLAGS (PIO_TYPE_PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+/** CAN1 PIN RX. */\r
+#define PIN_CAN1_RX_IDX (PIO_PB15_IDX)\r
+#define PIN_CAN1_RX_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/** CAN1 PIN TX. */\r
+#define PIN_CAN1_TX_IDX (PIO_PB14_IDX)\r
+#define PIN_CAN1_TX_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/**\r
+ * \file\r
+ * QTouch\r
+ * PIO definitions for Slider\r
+ * \ref SLIDER_IOMASK_SNS\r
+ * \ref SLIDER_IOMASK_SNSK\r
+ * \ref PINS_SLIDER_SNS\r
+ * \ref PINS_SLIDER_SNSK\r
+ *\r
+ * PIO definitions for keys\r
+ * \ref KEY_IOMASK_SNS\r
+ * \ref KEY_IOMASK_SNSK\r
+ * \ref PINS_KEY_SNS\r
+ * \ref PINS_KEY_SNSK\r
+ *\r
+ * PIOS for QTouch\r
+ * \ref PINS_QTOUCH\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* QTOUCH */\r
+/* ------------------------------------------------------------------------ */\r
+/*! PIO definitions for Slider */\r
+#define SLIDER_IOMASK_SNS (uint32_t)(PIO_PF0 | PIO_PF2 | PIO_PF4)\r
+#define SLIDER_IOMASK_SNSK (uint32_t)(PIO_PF1 | PIO_PF3 | PIO_PF5)\r
+#define PINS_SLIDER_SNS\\r
+ {SLIDER_IOMASK_SNS, PIOF, ID_PIOF, PIO_INPUT, PIO_DEFAULT}\r
+#define PINS_SLIDER_SNSK\\r
+ {SLIDER_IOMASK_SNSK, PIOF, ID_PIOF, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/*! PIO definitions for keys */\r
+#define KEY_IOMASK_SNS\\r
+ (uint32_t)(PIO_PE21 | PIO_PE27 | PIO_PE25 | PIO_PE19 | PIO_PE23)\r
+#define KEY_IOMASK_SNSK\\r
+ (uint32_t)(PIO_PE20 | PIO_PE26 | PIO_PE24 | PIO_PE18 | PIO_PE22)\r
+#define PINS_KEY_SNS\\r
+ {KEY_IOMASK_SNS, PIOE, ID_PIOE, PIO_INPUT, PIO_DEFAULT}\r
+#define PINS_KEY_SNSK\\r
+ {KEY_IOMASK_SNSK, PIOE, ID_PIOE, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/*! PIOS for QTouch */\r
+#define PINS_QTOUCH PINS_SLIDER_SNS, PINS_SLIDER_SNSK,\\r
+ PINS_KEY_SNS, PINS_KEY_SNSK\r
+\r
+/**\r
+ * \file\r
+ * TWI\r
+ * - \ref PIN_TWI_TWD0\r
+ * - \ref PIN_TWI_TWCK0\r
+ * - \ref PINS_TWI0\r
+ * - \ref PIN_TWI_TWD1\r
+ * - \ref PIN_TWI_TWCK1\r
+ * - \ref PINS_TWI1\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* TWI */\r
+/* ------------------------------------------------------------------------ */\r
+/*! TWI0 data pin */\r
+#define PIN_TWI_TWD0\\r
+ {PIO_PA17A_TWD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! TWI0 clock pin */\r
+#define PIN_TWI_TWCK0\\r
+ {PIO_PA18A_TWCK0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! TWI0 pins */\r
+#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0\r
+\r
+/*! TWI0 pins definition */\r
+#define TWI0_DATA_GPIO PIO_PA17_IDX\r
+#define TWI0_DATA_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define TWI0_CLK_GPIO PIO_PA18_IDX\r
+#define TWI0_CLK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/*! TWI1 data pin */\r
+#define PIN_TWI_TWD1\\r
+ {PIO_PB12A_TWD1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! TWI1 clock pin */\r
+#define PIN_TWI_TWCK1\\r
+ {PIO_PB13A_TWCK1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! TWI1 pins */\r
+#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1\r
+\r
+/*! TWI1 pins definition */\r
+#define TWI1_DATA_GPIO PIO_PB12_IDX\r
+#define TWI1_DATA_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define TWI1_CLK_GPIO PIO_PB13_IDX\r
+#define TWI1_CLK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/* ------------------------------------------------------------------------ */\r
+\r
+/**\r
+ * \page sam3x_ek_extcomp "SAM3X-EK - External components"\r
+ * This page lists the definitions related to external on-board components\r
+ * located in the board.h file for the SAM3X-EK.\r
+ *\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * LCD\r
+ *\r
+ * - \ref BOARD_LCD_PINS\r
+ * - \ref BOARD_BACKLIGHT_PIN\r
+ * - \ref BOARD_LCD_BASE\r
+ * - \ref BOARD_LCD_RS\r
+ *\r
+ */\r
+\r
+/*! LCD Base Address */\r
+#define BOARD_LCD_BASE 0x62000000\r
+/*! LCD pins definition. */\r
+#define BOARD_LCD_PINS PIN_EBI_DATA_BUS, PIN_EBI_NRD,\\r
+ PIN_EBI_NWE, PIN_EBI_NCS2, PIN_EBI_LCD_RS\r
+/*! Board chip select */\r
+#define BOARD_LCD_NCS 2\r
+/*! Board LCD SMC setup timings */\r
+#define BOARD_TIMING_NS(ns)\\r
+ (((uint32_t)((ns * (BOARD_MCK / 1000000)) / 1000)) + 1)\r
+\r
+#define BOARD_LCD_SETUP\\r
+ SMC_SETUP_NWE_SETUP(BOARD_TIMING_NS(10)) |\\r
+ SMC_SETUP_NCS_WR_SETUP(BOARD_TIMING_NS(10)) |\\r
+ SMC_SETUP_NRD_SETUP(BOARD_TIMING_NS(90)) |\\r
+ SMC_SETUP_NCS_RD_SETUP(BOARD_TIMING_NS(90))\r
+/*! Board LCD SMC pulse timings */\r
+#define BOARD_LCD_PULSE\\r
+ SMC_PULSE_NWE_PULSE(BOARD_TIMING_NS(35)) |\\r
+ SMC_PULSE_NCS_WR_PULSE(BOARD_TIMING_NS(35)) |\\r
+ SMC_PULSE_NRD_PULSE(BOARD_TIMING_NS(355)) |\\r
+ SMC_PULSE_NCS_RD_PULSE(BOARD_TIMING_NS(355))\r
+/*! Board LCD SMC cycle timings */\r
+#define BOARD_LCD_CYCLE\\r
+ SMC_CYCLE_NWE_CYCLE(BOARD_TIMING_NS(100)) |\\r
+ SMC_CYCLE_NRD_CYCLE(BOARD_TIMING_NS(460))\r
+/*! Board LCD SMC mode */\r
+#define BOARD_LCD_MODE\\r
+ SMC_MODE_WRITE_MODE |\\r
+ SMC_MODE_READ_MODE |\\r
+ SMC_MODE_DBW_BIT_16\r
+\r
+/*! Define HX8347A register select signal. */\r
+#define BOARD_LCD_RS (1 << 1)\r
+\r
+/*! Backlight pin definition. */\r
+#define BOARD_BACKLIGHT PIO_PB27_IDX\r
+#define BOARD_BACKLIGHT_FLAG PIO_OUTPUT_0 | PIO_DEFAULT\r
+\r
+/** Definition of MMA7341L x,y,z axis channel number */\r
+#define MMA7341L_ADC_CHANNEL_X 2\r
+#define MMA7341L_ADC_CHANNEL_Y 6\r
+#define MMA7341L_ADC_CHANNEL_Z 7\r
+\r
+/** MMA7341L mode set pin definition. */\r
+#define PIN_MMA7341L_MODE PIO_PC13_IDX\r
+#define PIN_MMA7341L_MODE_FLAG PIO_OUTPUT_1 | PIO_DEFAULT\r
+\r
+/** MMA7341L X,Y,Z axis pin definition. */\r
+#define PIN_MMA7341L_X_AXIS PIO_PB3_IDX\r
+#define PIN_MMA7341L_X_AXIS_FLAG PIO_INPUT | PIO_DEFAULT\r
+#define PIN_MMA7341L_Y_AXIS PIO_PC17_IDX\r
+#define PIN_MMA7341L_Y_AXIS_FLAG PIO_INPUT | PIO_DEFAULT\r
+#define PIN_MMA7341L_Z_AXIS PIO_PC18_IDX\r
+#define PIN_MMA7341L_Z_AXIS_FLAG PIO_INPUT | PIO_DEFAULT\r
+\r
+/**\r
+ * \file\r
+ * TouchScreen\r
+ *\r
+ * - \ref PIN_TSC_IRQ\r
+ * - \ref PIN_TSC_BUSY\r
+ * - \ref BOARD_TSC_SPI_BASE\r
+ * - \ref BOARD_TSC_SPI_ID\r
+ * - \ref BOARD_TSC_SPI_PINS\r
+ * - \ref BOARD_TSC_NPCS\r
+ * - \ref BOARD_TSC_NPCS_PIN\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* Touchscreen */\r
+/* ------------------------------------------------------------------------ */\r
+/*! Touchscreen controller IRQ pin definition. */\r
+#define PIN_TSC_IRQ {PIO_PA31, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+/*! Touchscreen controller Busy pin definition. */\r
+#define PIN_TSC_BUSY {PIO_PA30, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+\r
+/*! Base address of SPI peripheral connected to the touchscreen controller. */\r
+#define BOARD_TSC_SPI_BASE SPI0\r
+/*! Identifier of SPI peripheral connected to the touchscreen controller. */\r
+#define BOARD_TSC_SPI_ID ID_SPI0\r
+/*! Pins of the SPI peripheral connected to the touchscreen controller. */\r
+#define BOARD_TSC_SPI_PINS PINS_SPI0\r
+/*! Chip select connected to the touchscreen controller. */\r
+#define BOARD_TSC_NPCS 0\r
+/*! Chip select pin connected to the touchscreen controller. */\r
+/* We use PIO mode for chip select to meet ADS7843's timing specification */\r
+#define BOARD_TSC_NPCS_PIN\\r
+ {PIO_PA28A_SPI0_NPCS0, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_PULLUP}\r
+\r
+/**\r
+ * \file\r
+ * EMAC\r
+ *\r
+ * - BOARD_EMAC_EREFCK\r
+ * - BOARD_EMAC_ETXEN\r
+ * - BOARD_EMAC_ETX0\r
+ * - BOARD_EMAC_ETX1\r
+ * - BOARD_EMAC_ECRSDV\r
+ * - BOARD_EMAC_ERX0\r
+ * - BOARD_EMAC_ERX1\r
+ * - BOARD_EMAC_ERXER\r
+ * - BOARD_EMAC_EMDC\r
+ * - BOARD_EMAC_EMDIO\r
+ *\r
+ * - BOARD_EMAC_PINS: One single define for all MACB pins\r
+ * - BOARD_EMAC_PHY_ADDR: Phy MAC address\r
+ * - BOARD_EMAC_MODE_RMII: Enable RMII connection with the PHY\r
+ */\r
+\r
+/*! EMAC pin EREFCK */\r
+#define BOARD_EMAC_EREFCK {PIO_PB0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! EMAC pin ETXEN */\r
+#define BOARD_EMAC_ETXEN\\r
+ {PIO_PB1A_ETXEN, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! EMAC pin ETX0 */\r
+#define BOARD_EMAC_ETX0\\r
+ {PIO_PB2A_ETX0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! EMAC pin ETX1 */\r
+#define BOARD_EMAC_ETX1\\r
+ {PIO_PB3A_ETX1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! EMAC pin ECRSDV */\r
+#define BOARD_EMAC_ECRSDV\\r
+ {PIO_PB4A_ECRSDV_ERXDV, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! EMAC pin ERX0 */\r
+#define BOARD_EMAC_ERX0\\r
+ {PIO_PB5A_ERX0, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! EMAC pin ERX1 */\r
+#define BOARD_EMAC_ERX1\\r
+ {PIO_PB6A_ERX1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! EMAC pin ERXER */\r
+#define BOARD_EMAC_ERXER\\r
+ {PIO_PB7A_ERXER, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! EMAC pin EMDC */\r
+#define BOARD_EMAC_EMDC\\r
+ {PIO_PB8A_EMDC, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/*! EMAC pin EMDIO */\r
+#define BOARD_EMAC_EMDIO\\r
+ {PIO_PB9A_EMDIO, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+\r
+/*! EMAC pins */\r
+#define BOARD_EMAC_PINS\\r
+ BOARD_EMAC_EREFCK,\\r
+ BOARD_EMAC_ETX0,\\r
+ BOARD_EMAC_ETX1,\\r
+ BOARD_EMAC_ETXEN,\\r
+ BOARD_EMAC_ECRSDV,\\r
+ BOARD_EMAC_ERX0,\\r
+ BOARD_EMAC_ERX1,\\r
+ BOARD_EMAC_ERXER,\\r
+ BOARD_EMAC_EMDC,\\r
+ BOARD_EMAC_EMDIO\r
+\r
+#define PIN_EEMAC_EREFCK PIO_PB0_IDX\r
+#define PIN_EMAC_ETXEN PIO_PB1_IDX\r
+#define PIN_EMAC_ETX0 PIO_PB2_IDX\r
+#define PIN_EMAC_ETX1 PIO_PB3_IDX\r
+#define PIN_EMAC_ECRSDV PIO_PB4_IDX\r
+#define PIN_EMAC_ERX0 PIO_PB5_IDX\r
+#define PIN_EMAC_ERX1 PIO_PB6_IDX\r
+#define PIN_EMAC_ERXER PIO_PB7_IDX\r
+#define PIN_EMAC_EMDC PIO_PB8_IDX\r
+#define PIN_EMAC_EMDIO PIO_PB9_IDX\r
+#define PIN_EMAC_FLAGS PIO_PERIPH_A | PIO_DEFAULT\r
+\r
+/** EMAC PHY address */\r
+#define BOARD_EMAC_PHY_ADDR 0\r
+/*! EMAC RMII mode */\r
+#define BOARD_EMAC_MODE_RMII 1\r
+\r
+/**\r
+ * \file\r
+ * SD Card\r
+ * - \ref BOARD_SD_PINS\r
+ * - \ref BOARD_SD_PIN_CD\r
+ *\r
+ */\r
+\r
+/*! HSMCI pins that shall be configured to access the SD card. */\r
+#define BOARD_SD_PINS PINS_HSMCI\r
+/*! HSMCI Card Detect pin. */\r
+#define BOARD_SD_PIN_CD PIN_HSMCI_CD\r
+/*! Total number of HSMCI interface */\r
+#define BOARD_NUM_HSMCI 1\r
+\r
+/**\r
+ * \file\r
+ * SmartCard\r
+ * - \ref SMARTCARD_CONNECT_PIN\r
+ * - \ref PIN_ISO7816_RSTMC\r
+ * - \ref PINS_ISO7816\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* SMARTCARD */\r
+/* ------------------------------------------------------------------------ */\r
+/* Smartcard detection pin */\r
+/*#define SMARTCARD_CONNECT_PIN {1 << 13, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} */\r
+\r
+/*/ PIN used for reset the smartcard */\r
+#define PIN_ISO7816_RSTMC {1 << 11, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+/*/ Pins used for connect the smartcard */\r
+#define PINS_ISO7816 PIN_USART1_TXD, PIN_USART1_SCK, PIN_ISO7816_RSTMC\r
+\r
+/* ------------------------------------------------------------------------ */\r
+\r
+/**\r
+ * \page sam3x_ek_mem "SAM3X-EK - Memories"\r
+ * This page lists definitions related to internal & external on-board memories.\r
+ *\r
+ *\r
+ */\r
+\r
+/**\r
+ * \file\r
+ * NandFlash\r
+ * - \ref PIN_EBI_NANDOE\r
+ * - \ref PIN_EBI_NANDWE\r
+ * - \ref PIN_EBI_NANDCLE\r
+ * - \ref PIN_EBI_NANDALE\r
+ * - \ref PIN_EBI_NANDIO\r
+ * - \ref BOARD_NF_CE_PIN\r
+ * - \ref BOARD_NF_RB_PIN\r
+ * - \ref PINS_NANDFLASH\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* NAND FLASH */\r
+/* ------------------------------------------------------------------------ */\r
+/** NandFlash pins definition: OE. */\r
+#define PIN_EBI_NANDOE (PIO_PC19_IDX)\r
+#define PIN_EBI_NANDOE_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+/** NandFlash pins definition: WE. */\r
+#define PIN_EBI_NANDWE (PIO_PC20_IDX)\r
+#define PIN_EBI_NANDWE_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+/** NandFlash pins definition: CLE. */\r
+#define PIN_EBI_NANDCLE (PIO_PD9_IDX)\r
+#define PIN_EBI_NANDCLE_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+/** NandFlash pins definition: ALE. */\r
+#define PIN_EBI_NANDALE (PIO_PD8_IDX)\r
+#define PIN_EBI_NANDALE_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+/** NandFlash pins definition: DATA. */\r
+#define PIN_EBI_NANDIO_0 (PIO_PC2_IDX)\r
+#define PIN_EBI_NANDIO_0_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_1 (PIO_PC3_IDX)\r
+#define PIN_EBI_NANDIO_1_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_2 (PIO_PC4_IDX)\r
+#define PIN_EBI_NANDIO_2_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_3 (PIO_PC5_IDX)\r
+#define PIN_EBI_NANDIO_3_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_4 (PIO_PC6_IDX)\r
+#define PIN_EBI_NANDIO_4_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_5 (PIO_PC7_IDX)\r
+#define PIN_EBI_NANDIO_5_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_6 (PIO_PC8_IDX)\r
+#define PIN_EBI_NANDIO_6_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+#define PIN_EBI_NANDIO_7 (PIO_PC9_IDX)\r
+#define PIN_EBI_NANDIO_7_FLAGS (PIO_PERIPH_A | PIO_PULLUP)\r
+\r
+/** Nandflash chip enable pin definition. */\r
+#define PIN_NF_CE_IDX (PIO_PA6_IDX)\r
+#define PIN_NF_CE_FLAGS (PIO_PERIPH_B | PIO_PULLUP)\r
+\r
+/** Nandflash ready/busy pin definition. */\r
+#define PIN_NF_RB_IDX (PIO_PA2_IDX)\r
+#define PIN_NF_RB_FLAGS (PIO_PERIPH_B | PIO_PULLUP)\r
+\r
+/* Chip select number for nand */\r
+#define BOARD_NAND_CS 0\r
+\r
+/*\r
+ * \addtopage sam3x_ek_mem\r
+ * \section NandFlash\r
+ * - \ref BOARD_NF_COMMAND_ADDR\r
+ * - \ref BOARD_NF_ADDRESS_ADDR\r
+ * - \ref BOARD_NF_DATA_ADDR\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* NAND FLASH */\r
+/* ------------------------------------------------------------------------ */\r
+/*! Address for transferring command bytes to the nandflash. */\r
+#define BOARD_NF_COMMAND_ADDR 0x60400000\r
+/*! Address for transferring address bytes to the nandflash. */\r
+#define BOARD_NF_ADDRESS_ADDR 0x60200000\r
+/*! Address for transferring data bytes to the nandflash. */\r
+#define BOARD_NF_DATA_ADDR 0x60000000\r
+/* Bus width for NAND */\r
+#define CONF_NF_BUSWIDTH 8\r
+/* SMC NFC using five address cycle */\r
+#define CONF_NF_NEED_FIVE_ADDRESS_CYCLES 1\r
+/* Access timing for NAND */\r
+#define CONF_NF_SETUP_TIMING (SMC_SETUP_NWE_SETUP(0) \\r
+ | SMC_SETUP_NCS_WR_SETUP(0) \\r
+ | SMC_SETUP_NRD_SETUP(0) \\r
+ | SMC_SETUP_NCS_RD_SETUP(0))\r
+#define CONF_NF_PULSE_TIMING (SMC_PULSE_NWE_PULSE(2) \\r
+ | SMC_PULSE_NCS_WR_PULSE(3) \\r
+ | SMC_PULSE_NRD_PULSE(2) \\r
+ | SMC_PULSE_NCS_RD_PULSE(3))\r
+#define CONF_NF_CYCLE_TIMING (SMC_CYCLE_NWE_CYCLE(3) \\r
+ | SMC_CYCLE_NRD_CYCLE(3))\r
+#define CONF_NF_TIMING (SMC_TIMINGS_TCLR(1) \\r
+ | SMC_TIMINGS_TADL(6) \\r
+ | SMC_TIMINGS_TAR(4) \\r
+ | SMC_TIMINGS_TRR(2) \\r
+ | SMC_TIMINGS_TWB(9) \\r
+ | SMC_TIMINGS_RBNSEL(7) \\r
+ | (SMC_TIMINGS_NFSEL))\r
+/* Support DMA */\r
+#define CONF_NF_USE_DMA\r
+#ifdef CONF_NF_USE_DMA\r
+/* DMA channel used for NF */\r
+#define CONF_NF_DMA_CHANNEL 0\r
+#endif\r
+\r
+/**\r
+ * \file\r
+ * \section SDRAM\r
+ * - \ref BOARD_SDRAM_SIZE\r
+ * - \ref PIN_SDRAM\r
+ * - \ref BOARD_SDRAM_BUSWIDTH\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* SDRAM */\r
+/* ------------------------------------------------------------------------ */\r
+/*! Board SDRAM size for MT48LC16M16A2 */\r
+#define BOARD_SDRAM_SIZE (32 * 1024 * 1024) /* 32 MB */\r
+\r
+/** Address for transferring command bytes to the SDRAM. */\r
+#define BOARD_SDRAM_ADDR 0x70000000\r
+\r
+/** List of all SDRAM pins definitions */\r
+#define PIO_SDRAM_SDCKE PIO_PD13\r
+#define PIO_SDRAM_SDCS PIO_PD12\r
+#define PIO_SDRAM_RAS PIO_PD15\r
+#define PIO_SDRAM_CAS PIO_PD16\r
+#define PIO_SDRAM_BA0 PIO_PD6\r
+#define PIO_SDRAM_BA1 PIO_PD7\r
+#define PIO_SDRAM_SDWE PIO_PD14\r
+#define PIO_SDRAM_NBS0 PIO_PC21\r
+#define PIO_SDRAM_NBS1 PIO_PD10\r
+#define PIO_SDRAM_DATA (0xffff << 2) //PIO_PC2--PIO_PC17\r
+#define PIO_SDRAM_SDA0_A7 (0xff << 23) //PIO_PC23--PIO_PC30\r
+#define PIO_SDRAM_SDA8 PIO_PD22\r
+#define PIO_SDRAM_SDA9 PIO_PD23\r
+#define PIO_SDRAM_SDA11 PIO_PD25\r
+#define PIO_SDRAM_SDA12 PIO_PD4\r
+#define PIO_SDRAM_SDA10 PIO_PD11\r
+\r
+#define PIN_SDRAM_SDCKE PIO_PD13_IDX\r
+#define PIN_SDRAM_SDCS PIO_PD12_IDX\r
+#define PIN_SDRAM_RAS PIO_PD15_IDX\r
+#define PIN_SDRAM_CAS PIO_PD16_IDX\r
+#define PIN_SDRAM_BA0 PIO_PD6_IDX\r
+#define PIN_SDRAM_BA1 PIO_PD7_IDX\r
+#define PIN_SDRAM_SDWE PIO_PD14_IDX\r
+#define PIN_SDRAM_NBS0 PIO_PC21_IDX\r
+#define PIN_SDRAM_NBS1 PIO_PD10_IDX\r
+#define PIN_SDRAM_DATA0 PIO_PC2_IDX\r
+#define PIN_SDRAM_DATA1 PIO_PC3_IDX\r
+#define PIN_SDRAM_DATA2 PIO_PC4_IDX\r
+#define PIN_SDRAM_DATA3 PIO_PC5_IDX\r
+#define PIN_SDRAM_DATA4 PIO_PC6_IDX\r
+#define PIN_SDRAM_DATA5 PIO_PC7_IDX\r
+#define PIN_SDRAM_DATA6 PIO_PC8_IDX\r
+#define PIN_SDRAM_DATA7 PIO_PC9_IDX\r
+#define PIN_SDRAM_DATA8 PIO_PC10_IDX\r
+#define PIN_SDRAM_DATA9 PIO_PC11_IDX\r
+#define PIN_SDRAM_DATA10 PIO_PC12_IDX\r
+#define PIN_SDRAM_DATA11 PIO_PC13_IDX\r
+#define PIN_SDRAM_DATA12 PIO_PC14_IDX\r
+#define PIN_SDRAM_DATA13 PIO_PC15_IDX\r
+#define PIN_SDRAM_DATA14 PIO_PC16_IDX\r
+#define PIN_SDRAM_DATA15 PIO_PC17_IDX\r
+#define PIN_SDRAM_SDA1 PIO_PC23_IDX\r
+#define PIN_SDRAM_SDA2 PIO_PC24_IDX\r
+#define PIN_SDRAM_SDA3 PIO_PC25_IDX\r
+#define PIN_SDRAM_SDA4 PIO_PC26_IDX\r
+#define PIN_SDRAM_SDA5 PIO_PC27_IDX\r
+#define PIN_SDRAM_SDA6 PIO_PC28_IDX\r
+#define PIN_SDRAM_SDA7 PIO_PC29_IDX\r
+#define PIN_SDRAM_SDA0 PIO_PC30_IDX\r
+#define PIN_SDRAM_SDA8 PIO_PD22_IDX\r
+#define PIN_SDRAM_SDA9 PIO_PD23_IDX\r
+#define PIN_SDRAM_SDA11 PIO_PD25_IDX\r
+#define PIN_SDRAM_SDA12 PIO_PD4_IDX\r
+#define PIN_SDRAM_SDA10 PIO_PD11_IDX\r
+\r
+#define PIN_SDRAM_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+\r
+#define PIN_SDRAM_EN PIO_PD18_IDX\r
+#define PIN_SDRAM_EN_FLAGS PIO_OUTPUT_1 | PIO_DEFAULT\r
+\r
+/** List of all SDRAM pins definitions */\r
+#define PINS_SDRAM_PIOC { PIO_SDRAM_DATA | PIO_SDRAM_NBS0 | PIO_SDRAM_SDA0_A7, \\r
+ PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP }\r
+\r
+#define PINS_SDRAM_PIOD\\r
+ { PIO_SDRAM_SDCKE | PIO_SDRAM_SDCS |\\r
+ PIO_SDRAM_RAS | PIO_SDRAM_CAS |\\r
+ PIO_SDRAM_BA0 | PIO_SDRAM_BA1 |\\r
+ PIO_SDRAM_SDWE | PIO_SDRAM_NBS1 |\\r
+ PIO_SDRAM_SDA10 |\\r
+ PIO_SDRAM_SDA8 | PIO_SDRAM_SDA9 |\\r
+ PIO_SDRAM_SDA11 | PIO_SDRAM_SDA12,\\r
+ PIOD, ID_PIOD, PIO_PERIPH_A, PIO_PULLUP }\r
+\r
+/* PIO18 is used as SDRAM Enable on EK-REVB board */\r
+#define PINS_SDRAM_EN\\r
+ { (1 << 18), PIOD, ID_PIOD, PIO_OUTPUT_1, PIO_DEFAULT }\r
+\r
+#define PINS_SDRAM PINS_SDRAM_PIOC, PINS_SDRAM_PIOD, PINS_SDRAM_EN\r
+\r
+/*! SDRAM bus width */\r
+#define BOARD_SDRAM_BUSWIDTH 16\r
+\r
+/* SDRAMC clock speed */\r
+#define SDRAMC_CLK (BOARD_MCK)\r
+\r
+/**\r
+ * \file\r
+ * \section NorFlash\r
+ * - \ref BOARD_NORFLASH_ADDR\r
+ *\r
+ */\r
+\r
+/* ------------------------------------------------------------------------ */\r
+/* NOR FLASH */\r
+/* ------------------------------------------------------------------------ */\r
+/*! Address for transferring command bytes to the norflash. */\r
+#define BOARD_NORFLASH_ADDR 0x60000000\r
+\r
+/* ------------------------------------------------------------------------ */\r
+\r
+/**\r
+ * \page sam3x_ek_chipdef "SAM3X-EK - Individual chip definition"\r
+ * This page lists the definitions related to different chip's definition\r
+ * located in the board.h file for the SAM3X-EK.\r
+ *\r
+ * \section USART\r
+ * - \ref BOARD_PIN_USART_RXD\r
+ * - \ref BOARD_PIN_USART_TXD\r
+ * - \ref BOARD_PIN_USART_CTS\r
+ * - \ref BOARD_PIN_USART_RTS\r
+ * - \ref BOARD_PIN_USART_EN\r
+ * - \ref BOARD_USART_BASE\r
+ * - \ref BOARD_ID_USART\r
+ */\r
+\r
+/*! Rtc */\r
+#define BOARD_RTC_ID ID_RTC\r
+\r
+/* AT24CXX device address */\r
+#define BOARD_AT24C_ADDRESS 0x50\r
+/** Define MCP980X TWI instance. */\r
+#define BOARD_AT24C_TWI_INSTANCE (TWI0)\r
+\r
+/*! TWI ID for EEPROM application to use */\r
+#define BOARD_ID_TWI_EEPROM ID_TWI0\r
+/*! TWI Base for TWI EEPROM application to use */\r
+#define BOARD_BASE_TWI_EEPROM TWI0\r
+/*! TWI pins for EEPROM application to use */\r
+#define BOARD_PINS_TWI_EEPROM PINS_TWI0\r
+\r
+/*! USART RX pin for application */\r
+#define BOARD_PIN_USART_RXD PIN_USART0_RXD\r
+/*! USART TX pin for application */\r
+#define BOARD_PIN_USART_TXD PIN_USART0_TXD\r
+/*! USART CTS pin for application */\r
+#define BOARD_PIN_USART_CTS PIN_USART0_CTS\r
+/*! USART RTS pin for application */\r
+#define BOARD_PIN_USART_RTS PIN_USART0_RTS\r
+/*! USART ENABLE pin for application */\r
+#define BOARD_PIN_USART_EN PIN_USART0_EN\r
+/*! USART Base for application */\r
+#define BOARD_USART_BASE USART0\r
+/*! USART ID for application */\r
+#define BOARD_ID_USART ID_USART0\r
+/*! USART1 Base for application */\r
+#define BOARD_USART1_BASE USART1\r
+/*! USART1 ID for application */\r
+#define BOARD_ID_USART1 ID_USART1\r
+/*! USART3 Base for application */\r
+#define BOARD_USART3_BASE USART3\r
+/*! USART3 ID for application */\r
+#define BOARD_ID_USART3 ID_USART3\r
+\r
+#define CONSOLE_UART UART\r
+#define CONSOLE_UART_ID ID_UART\r
+\r
+/* RE pin. */\r
+#define PIN_RE_IDX PIN_USART0_CTS_IDX\r
+#define PIN_RE_FLAGS (PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+/* IRDA SD pin. */\r
+#define PIN_IRDA_SD_IDX PIN_USART0_CTS_IDX\r
+#define PIN_IRDA_SD_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+/* TXD pin configuration. */\r
+#define PIN_USART_TXD_IDX PIN_USART0_TXD_IDX\r
+#define PIN_USART_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define PIN_USART_TXD_IO_FLAGS (PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+/* ISO7816 example relate PIN definition. */\r
+#define ISO7816_USART_ID ID_USART0\r
+#define ISO7816_USART USART0\r
+#define PIN_ISO7816_RST_IDX PIO_PA15_IDX\r
+#define PIN_ISO7816_RST_FLAG (PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+#endif /* _SAM3X_EK_H_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) Controller driver for SAM.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "pio.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * The Parallel Input/Output Controller (PIO) manages up to 32 fully\r
+ * programmable input/output lines. Each I/O line may be dedicated as a\r
+ * general-purpose I/O or be assigned to a function of an embedded peripheral.\r
+ * This assures effective optimization of the pins of a product.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef FREQ_SLOW_CLOCK_EXT\r
+/* External slow clock frequency (hz) */\r
+#define FREQ_SLOW_CLOCK_EXT 32768\r
+#endif\r
+\r
+/**\r
+ * \brief Configure PIO internal pull-up.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be\r
+ * configured.\r
+ */\r
+void pio_pull_up(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_up_enable)\r
+{\r
+ /* Enable the pull-up(s) if necessary */\r
+ if (ul_pull_up_enable) {\r
+ p_pio->PIO_PUER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_PUDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure Glitch or Debouncing filter for the specified input(s).\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_cut_off Cuts off frequency for debouncing filter.\r
+ */\r
+void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_cut_off)\r
+{\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ /* Set Debouncing, 0 bit field no effect */\r
+ p_pio->PIO_IFSCER = ul_mask;\r
+#elif (SAM3XA || SAM3U)\r
+ /* Set Debouncing, 0 bit field no effect */\r
+ p_pio->PIO_DIFSR = ul_mask;\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ /* The debouncing filter can filter a pulse of less than 1/2 Period of a\r
+ programmable Divided Slow Clock:\r
+ Tdiv_slclk = ((DIV+1)*2).Tslow_clock */\r
+ p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT /\r
+ (2 * (ul_cut_off))) - 1);\r
+}\r
+\r
+/**\r
+ * \brief Set a high output level on all the PIOs defined in ul_mask.\r
+ * This has no immediate effects on PIOs that are not output, but the PIO\r
+ * controller will save the value if they are changed to outputs.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_SODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Set a low output level on all the PIOs defined in ul_mask.\r
+ * This has no immediate effects on PIOs that are not output, but the PIO\r
+ * controller will save the value if they are changed to outputs.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_clear(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_CODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if one or more PIOs of the given Pin instance currently have\r
+ * a high level; otherwise returns 0. This method returns the actual value that\r
+ * is being read on the pin. To return the supposed output value of a pin, use\r
+ * pio_get_output_data_status() instead.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ *\r
+ * \retval 1 at least one PIO currently has a high level.\r
+ * \retval 0 all PIOs have a low level.\r
+ */\r
+uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask)\r
+{\r
+ uint32_t ul_reg;\r
+\r
+ if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) {\r
+ ul_reg = p_pio->PIO_ODSR;\r
+ } else {\r
+ ul_reg = p_pio->PIO_PDSR;\r
+ }\r
+\r
+ if ((ul_reg & ul_mask) == 0) {\r
+ return 0;\r
+ } else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure IO of a PIO controller as being controlled by a specific\r
+ * peripheral.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask)\r
+{\r
+ uint32_t ul_sr;\r
+\r
+ /* Disable interrupts on the pin(s) */\r
+ p_pio->PIO_IDR = ul_mask;\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_B:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_C:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_D:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);\r
+ break;\r
+\r
+ // other types are invalid in this function\r
+ case PIO_INPUT:\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ case PIO_NOT_A_PIN:\r
+ return;\r
+ }\r
+#elif (SAM3XA|| SAM3U)\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ ul_sr = p_pio->PIO_ABSR;\r
+ p_pio->PIO_ABSR &= (~ul_mask & ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_B:\r
+ ul_sr = p_pio->PIO_ABSR;\r
+ p_pio->PIO_ABSR = (ul_mask | ul_sr);\r
+ break;\r
+\r
+ // other types are invalid in this function\r
+ case PIO_INPUT:\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ case PIO_NOT_A_PIN:\r
+ return;\r
+ }\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ // Remove the pins from under the control of PIO\r
+ p_pio->PIO_PDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Configure one or more pin(s) or a PIO controller as inputs.\r
+ * Optionally, the corresponding internal pull-up(s) and glitch filter(s) can\r
+ * be enabled.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask indicating which pin(s) to configure as input(s).\r
+ * \param ul_attribute PIO attribute(s).\r
+ */\r
+void pio_set_input(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_attribute)\r
+{\r
+ pio_disable_interrupt(p_pio, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP);\r
+\r
+ /* Enable Input Filter if necessary */\r
+ if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) {\r
+ p_pio->PIO_IFER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_IFDR = ul_mask;\r
+ }\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ /* Enable de-glitch or de-bounce if necessary */\r
+ if (ul_attribute & PIO_DEGLITCH) {\r
+ p_pio->PIO_IFSCDR = ul_mask;\r
+ } else {\r
+ if (ul_attribute & PIO_DEBOUNCE) {\r
+ p_pio->PIO_IFSCER = ul_mask;\r
+ }\r
+ }\r
+#elif (SAM3XA|| SAM3U)\r
+ /* Enable de-glitch or de-bounce if necessary */\r
+ if (ul_attribute & PIO_DEGLITCH) {\r
+ p_pio->PIO_SCIFSR = ul_mask;\r
+ } else {\r
+ if (ul_attribute & PIO_DEBOUNCE) {\r
+ p_pio->PIO_SCIFSR = ul_mask;\r
+ }\r
+ }\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ /* Configure pin as input */\r
+ p_pio->PIO_ODR = ul_mask;\r
+ p_pio->PIO_PER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Configure one or more pin(s) of a PIO controller as outputs, with\r
+ * the given default value. Optionally, the multi-drive feature can be enabled\r
+ * on the pin(s).\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask indicating which pin(s) to configure.\r
+ * \param ul_default_level Default level on the pin(s).\r
+ * \param ul_multidrive_enable Indicates if the pin(s) shall be configured as\r
+ * open-drain.\r
+ * \param ul_pull_up_enable Indicates if the pin shall have its pull-up\r
+ * activated.\r
+ */\r
+void pio_set_output(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_default_level,\r
+ const uint32_t ul_multidrive_enable,\r
+ const uint32_t ul_pull_up_enable)\r
+{\r
+ pio_disable_interrupt(p_pio, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, ul_pull_up_enable);\r
+\r
+ /* Enable multi-drive if necessary */\r
+ if (ul_multidrive_enable) {\r
+ p_pio->PIO_MDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_MDDR = ul_mask;\r
+ }\r
+\r
+ /* Set default value */\r
+ if (ul_default_level) {\r
+ p_pio->PIO_SODR = ul_mask;\r
+ } else {\r
+ p_pio->PIO_CODR = ul_mask;\r
+ }\r
+\r
+ /* Configure pin(s) as output(s) */\r
+ p_pio->PIO_OER = ul_mask;\r
+ p_pio->PIO_PER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_attribute Pins attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute)\r
+{\r
+ /* Configure pins */\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ case PIO_PERIPH_B:\r
+# if (SAM3S || SAM3N || SAM4S)\r
+ case PIO_PERIPH_C:\r
+ case PIO_PERIPH_D:\r
+# endif\r
+ pio_set_peripheral(p_pio, ul_type, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP));\r
+ break;\r
+\r
+ case PIO_INPUT:\r
+ pio_set_input(p_pio, ul_mask, ul_attribute);\r
+ break;\r
+\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1),\r
+ (ul_attribute & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if one or more PIOs of the given Pin are configured to\r
+ * output a high level (even if they are not output).\r
+ * To get the actual value of the pin, use PIO_Get() instead.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s).\r
+ *\r
+ * \retval 1 At least one PIO is configured to output a high level.\r
+ * \retval 0 All PIOs are configured to output a low level.\r
+ */\r
+uint32_t pio_get_output_data_status(const Pio *p_pio,\r
+ const uint32_t ul_mask)\r
+{\r
+ if ((p_pio->PIO_ODSR & ul_mask) == 0) {\r
+ return 0;\r
+ } else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure PIO pin multi-driver.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be\r
+ * configured.\r
+ */\r
+void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_multi_driver_enable)\r
+{\r
+ /* Enable the multi-driver if necessary */\r
+ if (ul_multi_driver_enable) {\r
+ p_pio->PIO_MDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_MDDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get multi-driver status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The multi-driver mask value.\r
+ */\r
+uint32_t pio_get_multi_driver_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_MDSR;\r
+}\r
+\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+/**\r
+ * \brief Configure PIO pin internal pull-down.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall\r
+ * be configured.\r
+ */\r
+void pio_pull_down(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_down_enable)\r
+{\r
+ /* Enable the pull-down if necessary */\r
+ if (ul_pull_down_enable) {\r
+ p_pio->PIO_PPDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_PPDDR = ul_mask;\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable PIO output write for synchronous data output.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_OWER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable PIO output write.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_OWDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO output write status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The output write mask value.\r
+ */\r
+uint32_t pio_get_output_write_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_OWSR;\r
+}\r
+\r
+/**\r
+ * \brief Synchronously write on output pins.\r
+ * \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are\r
+ * written.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_ODSR = ul_mask;\r
+}\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+/**\r
+ * \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is\r
+ * active.\r
+ * Disabling the Schmitt Trigger is requested when using the QTouch Library.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_SCHMITT = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Get PIO pin schmitt trigger status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The schmitt trigger mask value.\r
+ */\r
+uint32_t pio_get_schmitt_trigger(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_SCHMITT;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Configure the given interrupt source.\r
+ * Interrupt can be configured to trigger on rising edge, falling edge,\r
+ * high level, low level or simply on level change.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt source bit map.\r
+ * \param ul_attr Interrupt source attributes.\r
+ */\r
+void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_attr)\r
+{\r
+ /* Configure additional interrupt mode registers. */\r
+ if (ul_attr & PIO_IT_AIME) {\r
+ /* Enable additional interrupt mode. */\r
+ p_pio->PIO_AIMER = ul_mask;\r
+\r
+ /* If bit field of the selected pin is 1, set as\r
+ Rising Edge/High level detection event. */\r
+ if (ul_attr & PIO_IT_RE_OR_HL) {\r
+ /* Rising Edge or High Level */\r
+ p_pio->PIO_REHLSR = ul_mask;\r
+ } else {\r
+ /* Falling Edge or Low Level */\r
+ p_pio->PIO_FELLSR = ul_mask;\r
+ }\r
+\r
+ /* If bit field of the selected pin is 1, set as\r
+ edge detection source. */\r
+ if (ul_attr & PIO_IT_EDGE) {\r
+ /* Edge select */\r
+ p_pio->PIO_ESR = ul_mask;\r
+ } else {\r
+ /* Level select */\r
+ p_pio->PIO_LSR = ul_mask;\r
+ }\r
+ } else {\r
+ /* Disable additional interrupt mode. */\r
+ p_pio->PIO_AIMDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable the given interrupt source.\r
+ * The PIO must be configured as an NVIC interrupt source as well.\r
+ * The status register of the corresponding PIO controller is cleared\r
+ * prior to enabling the interrupt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_ISR;\r
+ p_pio->PIO_IER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable a given interrupt source, with no added side effects.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_IDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt status mask value.\r
+ */\r
+uint32_t pio_get_interrupt_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_ISR;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt mask.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pio_get_interrupt_mask(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Set additional interrupt mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ * \param ul_attribute Pin(s) attributes.\r
+ */\r
+void pio_set_additional_interrupt_mode(Pio *p_pio,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute)\r
+{\r
+ /* Enables additional interrupt mode if needed */\r
+ if (ul_attribute & PIO_IT_AIME) {\r
+ /* Enables additional interrupt mode */\r
+ p_pio->PIO_AIMER = ul_mask;\r
+\r
+ /* Configures the Polarity of the event detection */\r
+ /* (Rising/Falling Edge or High/Low Level) */\r
+ if (ul_attribute & PIO_IT_RE_OR_HL) {\r
+ /* Rising Edge or High Level */\r
+ p_pio->PIO_REHLSR = ul_mask;\r
+ } else {\r
+ /* Falling Edge or Low Level */\r
+ p_pio->PIO_FELLSR = ul_mask;\r
+ }\r
+\r
+ /* Configures the type of event detection (Edge or Level) */\r
+ if (ul_attribute & PIO_IT_EDGE) {\r
+ /* Edge select */\r
+ p_pio->PIO_ESR = ul_mask;\r
+ } else {\r
+ /* Level select */\r
+ p_pio->PIO_LSR = ul_mask;\r
+ }\r
+ } else {\r
+ /* Disable additional interrupt mode */\r
+ p_pio->PIO_AIMDR = ul_mask;\r
+ }\r
+}\r
+\r
+#define PIO_WPMR_WPKEY_VALUE PIO_WPMR_WPKEY(0x50494Fu)\r
+\r
+/**\r
+ * \brief Enable or disable write protect of PIO registers.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_enable 1 to enable, 0 to disable.\r
+ */\r
+void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable)\r
+{\r
+ p_pio->PIO_WPMR = PIO_WPMR_WPKEY_VALUE | ul_enable;\r
+}\r
+\r
+/**\r
+ * \brief Read write protect status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return Return write protect status.\r
+ */\r
+uint32_t pio_get_writeprotect_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_WPSR;\r
+}\r
+\r
+#define PIO_DELTA ((uint32_t) PIOB - (uint32_t) PIOA)\r
+\r
+/**\r
+ * \brief Return the value of a pin.\r
+ *\r
+ * \param ul_pin The pin number.\r
+ *\r
+ * \return The pin value.\r
+ *\r
+ * \note If pin is output: a pull-up or pull-down could hide the actual value.\r
+ * The function \ref pio_get can be called to get the actual pin output\r
+ * level.\r
+ * \note If pin is input: PIOx must be clocked to sample the signal.\r
+ * See PMC driver.\r
+ */\r
+uint32_t pio_get_pin_value(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO pin to 1.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called beforehand.\r
+ */\r
+void pio_set_pin_high(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO pin to 0.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called before.\r
+ */\r
+void pio_set_pin_low(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+/**\r
+ * \brief Toggle a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called before.\r
+ */\r
+void pio_toggle_pin(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) {\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);\r
+ } else {\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param ul_pin Bitmask of one or more pin(s) to configure.\r
+ * \param ul_flags Pins attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+\r
+ /* Configure pins */\r
+ switch (ul_flags & PIO_TYPE_Msk) {\r
+ case PIO_TYPE_PIO_PERIPH_A:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_B:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+# if (SAM3S || SAM3N || SAM4S)\r
+ case PIO_TYPE_PIO_PERIPH_C:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_D:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+# endif\r
+\r
+ case PIO_TYPE_PIO_INPUT:\r
+ pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags);\r
+ break;\r
+\r
+ case PIO_TYPE_PIO_OUTPUT_0:\r
+ case PIO_TYPE_PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, (1 << (ul_pin & 0x1F)),\r
+ ((ul_flags & PIO_TYPE_PIO_OUTPUT_1)\r
+ == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,\r
+ (ul_flags & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_flags & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO port to 1.\r
+ *\r
+ * \param p_pio Base address of the PIO port.\r
+ * \param ul_mask Bitmask of one or more pin(s) to toggle.\r
+ */\r
+void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO port to 0.\r
+ *\r
+ * \param p_pio Base address of the PIO port.\r
+ * \param ul_mask Bitmask of one or more pin(s) to toggle.\r
+ */\r
+void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Toggle a GPIO group.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ if (p_pio->PIO_ODSR & ul_mask) {\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = ul_mask;\r
+ } else {\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_flags Pin(s) attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure_pin_group(Pio *p_pio,\r
+ uint32_t ul_mask, const uint32_t ul_flags)\r
+{\r
+ /* Configure pins */\r
+ switch (ul_flags & PIO_TYPE_Msk) {\r
+ case PIO_TYPE_PIO_PERIPH_A:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_B:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+# if (SAM3S || SAM3N || SAM4S)\r
+ case PIO_TYPE_PIO_PERIPH_C:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_D:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+# endif\r
+\r
+ case PIO_TYPE_PIO_INPUT:\r
+ pio_set_input(p_pio, ul_mask, ul_flags);\r
+ break;\r
+\r
+ case PIO_TYPE_PIO_OUTPUT_0:\r
+ case PIO_TYPE_PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, ul_mask,\r
+ ((ul_flags & PIO_TYPE_PIO_OUTPUT_1)\r
+ == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0,\r
+ (ul_flags & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_flags & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Enable interrupt for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref gpio_configure_pin must be called before.\r
+ */\r
+void pio_enable_pin_interrupt(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ p_pio->PIO_IER = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Disable interrupt for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref gpio_configure_pin must be called before.\r
+ */\r
+void pio_disable_pin_interrupt(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ p_pio->PIO_IDR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return GPIO port for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return Pointer to \ref Pio struct for GPIO port.\r
+ */\r
+Pio *pio_get_pin_group(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ return p_pio;\r
+}\r
+\r
+/**\r
+ * \brief Return GPIO port peripheral ID for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return GPIO port peripheral ID.\r
+ */\r
+uint32_t pio_get_pin_group_id(uint32_t ul_pin)\r
+{\r
+ uint32_t ul_id = ID_PIOA + (ul_pin >> 5);\r
+ return ul_id;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return GPIO port pin mask for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return GPIO port pin mask.\r
+ */\r
+uint32_t pio_get_pin_group_mask(uint32_t ul_pin)\r
+{\r
+ uint32_t ul_mask = 1 << (ul_pin & 0x1F);\r
+ return ul_mask;\r
+}\r
+\r
+\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Configure PIO capture mode.\r
+ * \note PIO capture mode will be disabled automatically.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mode Bitmask of one or more modes.\r
+ */\r
+void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode)\r
+{\r
+ ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */\r
+ p_pio->PIO_PCMR = ul_mode;\r
+}\r
+\r
+/**\r
+ * \brief Enable PIO capture mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ */\r
+void pio_capture_enable(Pio *p_pio)\r
+{\r
+ p_pio->PIO_PCMR |= PIO_PCMR_PCEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable PIO capture mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ */\r
+void pio_capture_disable(Pio *p_pio)\r
+{\r
+ p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN);\r
+}\r
+\r
+/**\r
+ * \brief Read from Capture Reception Holding Register.\r
+ * Data presence should be tested before any read attempt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param pul_data Pointer to store the data.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 I/O Failure, Capture data is not ready.\r
+ */\r
+uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data)\r
+{\r
+ /* Check if the data is ready */\r
+ if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) {\r
+ return 1;\r
+ }\r
+\r
+ /* Read data */\r
+ *pul_data = p_pio->PIO_PCRHR;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Enable the given interrupt source of PIO capture. The status\r
+ * register of the corresponding PIO capture controller is cleared prior\r
+ * to enabling the interrupt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_PCISR;\r
+ p_pio->PIO_PCIER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable a given interrupt source of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_PCIDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt status of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt status mask value.\r
+ */\r
+uint32_t pio_capture_get_interrupt_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_PCISR;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt mask of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_PCIMR;\r
+}\r
+\r
+/**\r
+ * \brief Get PDC registers base address.\r
+ *\r
+ * \param p_pio Pointer to an PIO peripheral.\r
+ *\r
+ * \return PIOA PDC register base address.\r
+ */\r
+Pdc *pio_capture_get_pdc_base(const Pio *p_pio)\r
+{\r
+ p_pio = p_pio; /* Stop warning */\r
+ return PDC_PIOA;\r
+}\r
+#endif\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) Controller driver for SAM.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef PIO_H_INCLUDED\r
+#define PIO_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/* GPIO Support */\r
+#define PIO_TYPE_Pos 27\r
+/* PIO Type Mask */\r
+#define PIO_TYPE_Msk (0xFu << PIO_TYPE_Pos)\r
+/* The pin is not a function pin. */\r
+#define PIO_TYPE_NOT_A_PIN (0x0u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral A. */\r
+#define PIO_TYPE_PIO_PERIPH_A (0x1u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral B. */\r
+#define PIO_TYPE_PIO_PERIPH_B (0x2u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral C. */\r
+#define PIO_TYPE_PIO_PERIPH_C (0x3u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral D. */\r
+#define PIO_TYPE_PIO_PERIPH_D (0x4u << PIO_TYPE_Pos)\r
+/* The pin is an input. */\r
+#define PIO_TYPE_PIO_INPUT (0x5u << PIO_TYPE_Pos)\r
+/* The pin is an output and has a default level of 0. */\r
+#define PIO_TYPE_PIO_OUTPUT_0 (0x6u << PIO_TYPE_Pos)\r
+/* The pin is an output and has a default level of 1. */\r
+#define PIO_TYPE_PIO_OUTPUT_1 (0x7u << PIO_TYPE_Pos)\r
+\r
+typedef enum _pio_type {\r
+ PIO_NOT_A_PIN = PIO_TYPE_NOT_A_PIN,\r
+ PIO_PERIPH_A = PIO_TYPE_PIO_PERIPH_A,\r
+ PIO_PERIPH_B = PIO_TYPE_PIO_PERIPH_B,\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ PIO_PERIPH_C = PIO_TYPE_PIO_PERIPH_C,\r
+ PIO_PERIPH_D = PIO_TYPE_PIO_PERIPH_D,\r
+#endif\r
+ PIO_INPUT = PIO_TYPE_PIO_INPUT,\r
+ PIO_OUTPUT_0 = PIO_TYPE_PIO_OUTPUT_0,\r
+ PIO_OUTPUT_1 = PIO_TYPE_PIO_OUTPUT_1\r
+} pio_type_t;\r
+\r
+/* Default pin configuration (no attribute). */\r
+#define PIO_DEFAULT (0u << 0)\r
+/* The internal pin pull-up is active. */\r
+#define PIO_PULLUP (1u << 0)\r
+/* The internal glitch filter is active. */\r
+#define PIO_DEGLITCH (1u << 1)\r
+/* The pin is open-drain. */\r
+#define PIO_OPENDRAIN (1u << 2)\r
+\r
+/* The internal debouncing filter is active. */\r
+#define PIO_DEBOUNCE (1u << 3)\r
+\r
+/* Enable additional interrupt modes. */\r
+#define PIO_IT_AIME (1u << 4)\r
+\r
+/* Interrupt High Level/Rising Edge detection is active. */\r
+#define PIO_IT_RE_OR_HL (1u << 5)\r
+/* Interrupt Edge detection is active. */\r
+#define PIO_IT_EDGE (1u << 6)\r
+\r
+/* Low level interrupt is active */\r
+#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME)\r
+/* High level interrupt is active */\r
+#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME)\r
+/* Falling edge interrupt is active */\r
+#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME)\r
+/* Rising edge interrupt is active */\r
+#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME)\r
+\r
+/*\r
+ * The #attribute# field is a bitmask that can either be set to PIO_DEFAULT,\r
+ * or combine (using bitwise OR '|') any number of the following constants:\r
+ * - PIO_PULLUP\r
+ * - PIO_DEGLITCH\r
+ * - PIO_DEBOUNCE\r
+ * - PIO_OPENDRAIN\r
+ * - PIO_IT_LOW_LEVEL\r
+ * - PIO_IT_HIGH_LEVEL\r
+ * - PIO_IT_FALL_EDGE\r
+ * - PIO_IT_RISE_EDGE\r
+ */\r
+void pio_pull_up(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_up_enable);\r
+void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_cut_off);\r
+void pio_set(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_clear(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask);\r
+void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask);\r
+void pio_set_input(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_attribute);\r
+void pio_set_output(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_default_level,\r
+ const uint32_t ul_multidrive_enable,\r
+ const uint32_t ul_pull_up_enable);\r
+uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute);\r
+uint32_t pio_get_output_data_status(const Pio *p_pio,\r
+ const uint32_t ul_mask);\r
+void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_multi_driver_enable);\r
+uint32_t pio_get_multi_driver_status(const Pio *p_pio);\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+void pio_pull_down(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_down_enable);\r
+#endif\r
+\r
+void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get_output_write_status(const Pio *p_pio);\r
+void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask);\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get_schmitt_trigger(const Pio *p_pio);\r
+#endif\r
+\r
+void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, const uint32_t ul_attr);\r
+void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get_interrupt_status(const Pio *p_pio);\r
+uint32_t pio_get_interrupt_mask(const Pio *p_pio);\r
+void pio_set_additional_interrupt_mode(Pio *p_pio,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute);\r
+void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable);\r
+uint32_t pio_get_writeprotect_status(const Pio *p_pio);\r
+\r
+#if (SAM3S || SAM4S)\r
+void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode);\r
+void pio_capture_enable(Pio *p_pio);\r
+void pio_capture_disable(Pio *p_pio);\r
+uint32_t pio_capture_read(const Pio *p_pio, uint32_t * pul_data);\r
+void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_capture_disable_interrupt(Pio * p_pio, const uint32_t ul_mask);\r
+uint32_t pio_capture_get_interrupt_status(const Pio *p_pio);\r
+uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio);\r
+Pdc *pio_capture_get_pdc_base(const Pio *p_pio);\r
+#endif\r
+\r
+/* GPIO Support */\r
+uint32_t pio_get_pin_value(uint32_t pin);\r
+void pio_set_pin_high(uint32_t pin);\r
+void pio_set_pin_low(uint32_t pin);\r
+void pio_toggle_pin(uint32_t pin);\r
+void pio_enable_pin_interrupt(uint32_t pin);\r
+void pio_disable_pin_interrupt(uint32_t pin);\r
+Pio *pio_get_pin_group(uint32_t pin);\r
+uint32_t pio_get_pin_group_id(uint32_t pin);\r
+uint32_t pio_get_pin_group_mask(uint32_t pin);\r
+uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags);\r
+void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask);\r
+void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask);\r
+void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask);\r
+uint32_t pio_configure_pin_group(Pio *p_pio, uint32_t ul_mask, const uint32_t ul_flags);\r
+\r
+/**\r
+ * \page sam_pio_quickstart Quick Start Guide for the SAM PIO driver\r
+ *\r
+ * This is the quick start guide for the \ref sam_drivers_pio_group "PIO Driver",\r
+ * with step-by-step instructions on how to configure and use the driver for\r
+ * specific use cases.\r
+ *\r
+ * The section described below can be compiled into e.g. the main application\r
+ * loop or any other function that will need to interface with the IO port.\r
+ *\r
+ * \section sam_pio_usecases PIO use cases\r
+ * - \ref sam_pio_quickstart_basic\r
+ * - \ref sam_pio_quickstart_use_case_2\r
+ *\r
+ * \section sam_pio_quickstart_basic Basic usage of the PIO driver\r
+ * This section will present a basic use case for the PIO driver. This use case\r
+ * will configure pin 23 on port A as output and pin 16 as an input with pullup,\r
+ * and then toggle the output pin's value to match that of the input pin.\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_prereq Prerequisites\r
+ * - \ref group_pmc "Power Management Controller driver"\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * pmc_enable_periph_clk(ID_PIOA);\r
+ *\r
+ * pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE);\r
+ * pio_set_input(PIOA, PIO_PA16, PIO_PULLUP);\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_setup_steps_workflow Workflow\r
+ * -# Enable the module clock to the PIOA peripheral:\r
+ * \code pmc_enable_periph_clk(ID_PIOA); \endcode\r
+ * -# Set pin 23 direction on PIOA as output, default low level:\r
+ * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode\r
+ * -# Set pin 16 direction on PIOA as input, with pullup:\r
+ * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_example_code Example code\r
+ * Set the state of output pin 23 to match input pin 16:\r
+ * \code\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_example_workflow Workflow\r
+ * -# We check the value of the pin:\r
+ * \code\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * \endcode\r
+ * -# Then we set the new output value based on the read pin value:\r
+ * \code\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * \endcode\r
+ */\r
+\r
+/**\r
+ * \page sam_pio_quickstart_use_case_2 Advanced use case - Interrupt driven edge detection\r
+ *\r
+ * \section sam_pio_quickstart_use_case_2 Advanced Use Case 1\r
+ * This section will present a more advanced use case for the PIO driver. This use case\r
+ * will configure pin 23 on port A as output and pin 16 as an input with pullup,\r
+ * and then toggle the output pin's value to match that of the input pin using the interrupt\r
+ * controller within the device.\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_prereq Prerequisites\r
+ * - \ref group_pmc "Power Management Controller driver"\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * pmc_enable_periph_clk(ID_PIOA);\r
+ *\r
+ * pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE);\r
+ * pio_set_input(PIOA, PIO_PA16, PIO_PULLUP);\r
+ *\r
+ * pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler);\r
+ * pio_enable_interrupt(PIOA, PIO_PA16);\r
+ *\r
+ * NVIC_EnableIRQ(PIOA_IRQn);\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_setup_steps_workflow Workflow\r
+ * -# Enable the module clock to the PIOA peripheral:\r
+ * \code pmc_enable_periph_clk(ID_PIOA); \endcode\r
+ * -# Set pin 23 direction on PIOA as output, default low level:\r
+ * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode\r
+ * -# Set pin 16 direction on PIOA as input, with pullup:\r
+ * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode\r
+ * -# Configure the input pin 16 interrupt mode and handler:\r
+ * \code pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); \endcode\r
+ * -# Enable the interrupt for the configured input pin:\r
+ * \code pio_enable_interrupt(PIOA, PIO_PA16); \endcode\r
+ * -# Enable interrupt handling from the PIOA module:\r
+ * \code NVIC_EnableIRQ(PIOA_IRQn); \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_example_code Example code\r
+ * Add the following function to your application:\r
+ * \code\r
+ * void pin_edge_handler(void)\r
+ * {\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_example_workflow Workflow\r
+ * -# We check the value of the pin:\r
+ * \code\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * \endcode\r
+ * -# Then we set the new output value based on the read pin value:\r
+ * \code\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * \endcode\r
+ */\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* PIO_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) interrupt handler for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "exceptions.h"\r
+#include "pio.h"\r
+#include "pio_handler.h"\r
+\r
+/** \r
+ * Maximum number of interrupt sources that can be defined. This\r
+ * constant can be increased, but the current value is the smallest possible one\r
+ * that will be compatible with all existing projects.\r
+ */\r
+#define MAX_INTERRUPT_SOURCES 7\r
+\r
+/**\r
+ * Describes a PIO interrupt source, including the PIO instance triggering the\r
+ * interrupt and the associated interrupt handler.\r
+ */\r
+struct s_interrupt_source {\r
+ uint32_t id;\r
+ uint32_t mask;\r
+ uint32_t attr;\r
+\r
+ /* Interrupt handler. */\r
+ void (*handler) (const uint32_t, const uint32_t);\r
+};\r
+\r
+\r
+/* List of interrupt sources. */\r
+static struct s_interrupt_source gs_interrupt_sources[MAX_INTERRUPT_SOURCES];\r
+\r
+/* Number of currently defined interrupt sources. */\r
+static uint32_t gs_ul_nb_sources = 0;\r
+\r
+/**\r
+ * \brief Process an interrupt request on the given PIO controller.\r
+ *\r
+ * \param p_pio PIO controller base address.\r
+ * \param ul_id PIO controller ID.\r
+ */\r
+void pio_handler_process(Pio *p_pio, uint32_t ul_id)\r
+{\r
+ uint32_t status;\r
+ uint32_t i;\r
+\r
+ /* Read PIO controller status */\r
+ status = pio_get_interrupt_status(p_pio);\r
+ status &= pio_get_interrupt_mask(p_pio);\r
+\r
+ /* Check pending events */\r
+ if (status != 0) {\r
+ /* Find triggering source */\r
+ i = 0;\r
+ while (status != 0) {\r
+ /* Source is configured on the same controller */\r
+ if (gs_interrupt_sources[i].id == ul_id) {\r
+ /* Source has PIOs whose statuses have changed */\r
+ if ((status & gs_interrupt_sources[i].mask) != 0) {\r
+ gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id,\r
+ gs_interrupt_sources[i].mask);\r
+ status &= ~(gs_interrupt_sources[i].mask);\r
+ }\r
+ }\r
+ i++;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set an interrupt handler for the provided pins.\r
+ * The provided handler will be called with the triggering pin as its parameter \r
+ * as soon as an interrupt is detected. \r
+ *\r
+ * \param p_pio PIO controller base address.\r
+ * \param ul_id PIO ID.\r
+ * \param ul_mask Pins (bit mask) to configure.\r
+ * \param ul_attr Pins attribute to configure.\r
+ * \param p_handler Interrupt handler function pointer.\r
+ *\r
+ * \return 0 if successful, 1 if the maximum number of sources has been defined.\r
+ */\r
+uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask,\r
+ uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t))\r
+{\r
+ struct s_interrupt_source *pSource;\r
+\r
+ if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES)\r
+ return 1;\r
+\r
+ /* Define new source */\r
+ pSource = &(gs_interrupt_sources[gs_ul_nb_sources]);\r
+ pSource->id = ul_id;\r
+ pSource->mask = ul_mask;\r
+ pSource->attr = ul_attr;\r
+ pSource->handler = p_handler;\r
+ gs_ul_nb_sources++;\r
+\r
+ /* Configure interrupt mode */\r
+ pio_configure_interrupt(p_pio, ul_mask, ul_attr);\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller A interrupt handler.\r
+ * Redefined PIOA interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOA_Handler(void)\r
+{\r
+ pio_handler_process(PIOA, ID_PIOA);\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller B interrupt handler\r
+ * Redefined PIOB interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOB_Handler(void)\r
+{\r
+ pio_handler_process(PIOB, ID_PIOB);\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller C interrupt handler.\r
+ * Redefined PIOC interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOC_Handler(void)\r
+{\r
+ pio_handler_process(PIOC, ID_PIOC);\r
+}\r
+\r
+#if SAM3XA\r
+/**\r
+ * \brief Parallel IO Controller D interrupt handler.\r
+ * Redefined PIOD interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOD_Handler(void)\r
+{\r
+ pio_handler_process(PIOD, ID_PIOD);\r
+}\r
+\r
+#ifdef _SAM3XA_PIOE_INSTANCE_\r
+/**\r
+ * \brief Parallel IO Controller E interrupt handler.\r
+ * Redefined PIOE interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOE_Handler(void)\r
+{\r
+ pio_handler_process(PIOE, ID_PIOE);\r
+}\r
+#endif\r
+\r
+#ifdef _SAM3XA_PIOF_INSTANCE_\r
+/**\r
+ * \brief Parallel IO Controller F interrupt handler.\r
+ * Redefined PIOF interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOF_Handler(void)\r
+{\r
+ pio_handler_process(PIOF, ID_PIOF);\r
+}\r
+#endif\r
+#endif\r
+\r
+/**\r
+ * \brief Initialize PIO interrupt management logic.\r
+ *\r
+ * \note The desired priority of PIO must be provided.\r
+ * Calling this function multiple times result in the reset of currently\r
+ * configured interrupt on the provided PIO.\r
+ *\r
+ * \param p_pio PIO controller base address.\r
+ * \param ul_irqn NVIC line number.\r
+ * \param ul_priority PIO controller interrupts priority.\r
+ */\r
+void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority)\r
+{\r
+ /* Configure PIO interrupt sources */\r
+ pio_get_interrupt_status(p_pio);\r
+ pio_disable_interrupt(p_pio, 0xFFFFFFFF);\r
+ NVIC_DisableIRQ(ul_irqn);\r
+ NVIC_ClearPendingIRQ(ul_irqn);\r
+ NVIC_SetPriority(ul_irqn, ul_priority);\r
+ NVIC_EnableIRQ(ul_irqn);\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) interrupt handler for SAM.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef PIO_HANDLER_H_INCLUDED\r
+#define PIO_HANDLER_H_INCLUDED\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+void pio_handler_process(Pio *p_pio, uint32_t ul_id);\r
+void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority);\r
+uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask,\r
+ uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t));\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* PIO_HANDLER_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Power Management Controller (PMC) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "pmc.h"\r
+\r
+#if (SAM3N)\r
+# define MAX_PERIPH_ID 31\r
+#elif (SAM3XA)\r
+# define MAX_PERIPH_ID 44\r
+#elif (SAM3U)\r
+# define MAX_PERIPH_ID 29\r
+#elif (SAM3S || SAM4S)\r
+# define MAX_PERIPH_ID 34\r
+#endif\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup sam_drivers_pmc_group Power Management Controller (PMC)\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * The Power Management Controller (PMC) optimizes power consumption by controlling\r
+ * all system and user peripheral clocks. The PMC enables/disables the clock inputs\r
+ * to many of the peripherals and the Cortex-M Processor.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Set the prescaler of the MCK.\r
+ *\r
+ * \param ul_pres Prescaler value.\r
+ */\r
+void pmc_mck_set_prescaler(uint32_t ul_pres)\r
+{\r
+ PMC->PMC_MCKR =\r
+ (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+/**\r
+ * \brief Set the source of the MCK.\r
+ *\r
+ * \param ul_source Source selection value.\r
+ */\r
+void pmc_mck_set_source(uint32_t ul_source)\r
+{\r
+ PMC->PMC_MCKR =\r
+ (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to slow clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_SLOW_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to main clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_MAIN_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch master clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_PLLA_CLK;\r
+\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch master clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_PLLB_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Switch master clock source selection to UPLL clock.\r
+ *\r
+ * \param ul_pres Processor clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |\r
+ PMC_MCKR_CSS_UPLL_CLK;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Switch slow clock source selection to external 32k (Xtal or Bypass).\r
+ *\r
+ * \note This function disables the PLLs.\r
+ *\r
+ * \note Switching SCLK back to 32krc is only possible by shutting down the VDDIO\r
+ * power supply.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ */\r
+void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)\r
+{\r
+ /* Set Bypass mode if required */\r
+ if (ul_bypass == 1) {\r
+ SUPC->SUPC_MR |= SUPC_MR_KEY(SUPC_KEY_VALUE) |\r
+ SUPC_MR_OSCBYPASS;\r
+ }\r
+\r
+ SUPC->SUPC_CR |= SUPC_CR_KEY(SUPC_KEY_VALUE) | SUPC_CR_XTALSEL;\r
+}\r
+\r
+/**\r
+ * \brief Check if the external 32k Xtal is ready.\r
+ *\r
+ * \retval 1 External 32k Xtal is ready.\r
+ * \retval 0 External 32k Xtal is not ready.\r
+ */\r
+uint32_t pmc_osc_is_ready_32kxtal(void)\r
+{\r
+ return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)\r
+ && (PMC->PMC_SR & PMC_SR_OSCSELS));\r
+}\r
+\r
+/**\r
+ * \brief Switch main clock source selection to internal fast RC.\r
+ *\r
+ * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ * \retval 2 Invalid frequency.\r
+ */\r
+void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)\r
+{\r
+ uint32_t ul_needXTEN = 0;\r
+\r
+ /* Enable Fast RC oscillator but DO NOT switch to RC now */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN |\r
+ ul_moscrcf;\r
+ } else {\r
+ ul_needXTEN = 1;\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN |\r
+ CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST(PMC_XTAL_STARTUP_TIME) |\r
+ ul_moscrcf;\r
+ }\r
+\r
+ /* Wait the Fast RC to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));\r
+\r
+ /* Switch to Fast RC */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | PMC_CKGR_MOR_KEY_VALUE;\r
+\r
+ /* Disable xtal oscillator */\r
+ if (ul_needXTEN) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable fast RC oscillator.\r
+ *\r
+ * \param ul_rc Fast RC oscillator(4/8/12Mhz).\r
+ */\r
+void pmc_osc_enable_fastrc(uint32_t ul_rc)\r
+{\r
+ /* Enable Fast RC oscillator but DO NOT switch to RC now. Keep MOSCSEL to 1 */\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL |\r
+ CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCRCEN | ul_rc;\r
+ /* Wait the Fast RC to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));\r
+}\r
+\r
+/**\r
+ * \brief Disable the internal fast RC.\r
+ */\r
+void pmc_osc_disable_fastrc(void)\r
+{\r
+ /* Disable Fast RC oscillator */\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & ~CKGR_MOR_MOSCRCF_Msk)\r
+ | PMC_CKGR_MOR_KEY_VALUE;\r
+}\r
+\r
+/**\r
+ * \brief Switch main clock source selection to external Xtal/Bypass.\r
+ * The function may switch MCK to SCLK if MCK source is MAINCK to avoid any\r
+ * system crash.\r
+ *\r
+ * \note If used in Xtal mode, the Xtal is automatically enabled.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+void pmc_switch_mainck_to_xtal(uint32_t ul_bypass)\r
+{\r
+ /* Enable Main Xtal oscillator */\r
+ if (ul_bypass) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTBY |\r
+ CKGR_MOR_MOSCSEL;\r
+ } else {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |\r
+ PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTEN |\r
+ CKGR_MOR_MOSCXTST(PMC_XTAL_STARTUP_TIME);\r
+ /* Wait the Xtal to stabilize */\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));\r
+\r
+ PMC->CKGR_MOR |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Disable the external Xtal.\r
+ *\r
+ * \param ul_bypass 0 for Xtal, 1 for bypass.\r
+ */\r
+void pmc_osc_disable_xtal(uint32_t ul_bypass)\r
+{\r
+ /* Disable xtal oscillator */\r
+ if (ul_bypass) {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ } else {\r
+ PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |\r
+ PMC_CKGR_MOR_KEY_VALUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one\r
+ * of Xtal, bypass or internal RC.\r
+ *\r
+ * \retval 1 Xtal is ready.\r
+ * \retval 0 Xtal is not ready.\r
+ */\r
+uint32_t pmc_osc_is_ready_mainck(void)\r
+{\r
+ return PMC->PMC_SR & PMC_SR_MOSCSELS;\r
+}\r
+\r
+/**\r
+ * \brief Enable PLLA clock.\r
+ *\r
+ * \param mula PLLA multiplier.\r
+ * \param pllacount PLLA counter.\r
+ * \param diva Divider.\r
+ */\r
+void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)\r
+{\r
+ /* first disable the PLL to unlock the lock!*/\r
+ pmc_disable_pllack();\r
+\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |\r
+ CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);\r
+ while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);\r
+}\r
+\r
+/**\r
+ * \brief Disable PLLA clock.\r
+ */\r
+void pmc_disable_pllack(void)\r
+{\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);\r
+}\r
+\r
+/**\r
+ * \brief Is PLLA locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_pllack(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKA);\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Enable PLLB clock.\r
+ *\r
+ * \param mulb PLLB multiplier.\r
+ * \param pllbcount PLLB counter.\r
+ * \param divb Divider.\r
+ */\r
+void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)\r
+{\r
+ /* first disable the PLL to unlock the lock!*/\r
+ pmc_disable_pllbck();\r
+\r
+ PMC->CKGR_PLLBR =\r
+ CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)\r
+ | CKGR_PLLBR_MULB(mulb);\r
+ while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);\r
+}\r
+\r
+/**\r
+ * \brief Disable PLLB clock.\r
+ */\r
+void pmc_disable_pllbck(void)\r
+{\r
+ PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);\r
+}\r
+\r
+/**\r
+ * \brief Is PLLB locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_pllbck(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKB);\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Enable UPLL clock.\r
+ */\r
+void pmc_enable_upll_clock(void)\r
+{\r
+ PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;\r
+\r
+ /* Wait UTMI PLL Lock Status */\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));\r
+}\r
+\r
+/**\r
+ * \brief Disable UPLL clock.\r
+ */\r
+void pmc_disable_upll_clock(void)\r
+{\r
+ PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;\r
+}\r
+\r
+/**\r
+ * \brief Is UPLL locked?\r
+ *\r
+ * \retval 0 Not locked.\r
+ * \retval 1 Locked.\r
+ */\r
+uint32_t pmc_is_locked_upll(void)\r
+{\r
+ return (PMC->PMC_SR & PMC_SR_LOCKU);\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable the specified peripheral clock.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Invalid parameter.\r
+ */\r
+uint32_t pmc_enable_periph_clk(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 1;\r
+ }\r
+\r
+ if (ul_id < 32) {\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {\r
+ PMC->PMC_PCER0 = 1 << ul_id;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {\r
+ PMC->PMC_PCER1 = 1 << ul_id;\r
+ }\r
+#endif\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Disable the specified peripheral clock.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Invalid parameter.\r
+ */\r
+uint32_t pmc_disable_periph_clk(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 1;\r
+ }\r
+\r
+ if (ul_id < 32) {\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {\r
+ PMC->PMC_PCDR0 = 1 << ul_id;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {\r
+ PMC->PMC_PCDR1 = 1 << ul_id;\r
+ }\r
+#endif\r
+ }\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Enable all peripheral clocks.\r
+ */\r
+void pmc_enable_all_periph_clk(void)\r
+{\r
+ PMC->PMC_PCER0 = PMC_MASK_STATUS0;\r
+ while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ PMC->PMC_PCER1 = PMC_MASK_STATUS1;\r
+ while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Disable all peripheral clocks.\r
+ */\r
+void pmc_disable_all_periph_clk(void)\r
+{\r
+ PMC->PMC_PCDR0 = PMC_MASK_STATUS0;\r
+ while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ PMC->PMC_PCDR1 = PMC_MASK_STATUS1;\r
+ while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Check if the specified peripheral clock is enabled.\r
+ *\r
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).\r
+ *\r
+ * \param ul_id Peripheral ID (ID_xxx).\r
+ *\r
+ * \retval 0 Peripheral clock is disabled or unknown.\r
+ * \retval 1 Peripheral clock is enabled.\r
+ */\r
+uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)\r
+{\r
+ if (ul_id > MAX_PERIPH_ID) {\r
+ return 0;\r
+ }\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ if (ul_id < 32) {\r
+#endif\r
+ if ((PMC->PMC_PCSR0 & (1u << ul_id))) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+ } else {\r
+ ul_id -= 32;\r
+ if ((PMC->PMC_PCSR1 & (1u << ul_id))) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+ }\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Set the prescaler for the specified programmable clock.\r
+ *\r
+ * \param ul_id Peripheral ID.\r
+ * \param ul_pres Prescaler value.\r
+ */\r
+void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ PMC->PMC_PCK[ul_id] =\r
+ (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;\r
+ while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))\r
+ && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));\r
+}\r
+\r
+/**\r
+ * \brief Set the source oscillator for the specified programmable clock.\r
+ *\r
+ * \param ul_id Peripheral ID.\r
+ * \param ul_source Source selection value.\r
+ */\r
+void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)\r
+{\r
+ PMC->PMC_PCK[ul_id] =\r
+ (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;\r
+ while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))\r
+ && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to slow clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to main clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Switch programmable clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch programmable clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT;\r
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Switch programmable clock source selection to UPLL clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ * \param ul_pres Programmable clock prescaler.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 Timeout error.\r
+ */\r
+uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)\r
+{\r
+ uint32_t ul_timeout;\r
+\r
+ PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;\r
+ for (ul_timeout = PMC_TIMEOUT;\r
+ !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));\r
+ --ul_timeout) {\r
+ if (ul_timeout == 0) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable the specified programmable clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ */\r
+void pmc_enable_pck(uint32_t ul_id)\r
+{\r
+ PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;\r
+}\r
+\r
+/**\r
+ * \brief Disable the specified programmable clock.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ */\r
+void pmc_disable_pck(uint32_t ul_id)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;\r
+}\r
+\r
+/**\r
+ * \brief Enable all programmable clocks.\r
+ */\r
+void pmc_enable_all_pck(void)\r
+{\r
+ PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;\r
+}\r
+\r
+/**\r
+ * \brief Disable all programmable clocks.\r
+ */\r
+void pmc_disable_all_pck(void)\r
+{\r
+ PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;\r
+}\r
+\r
+/**\r
+ * \brief Check if the specified programmable clock is enabled.\r
+ *\r
+ * \param ul_id Id of the programmable clock.\r
+ *\r
+ * \retval 0 Programmable clock is disabled or unknown.\r
+ * \retval 1 Programmable clock is enabled.\r
+ */\r
+uint32_t pmc_is_pck_enabled(uint32_t ul_id)\r
+{\r
+ if (ul_id > 2) {\r
+ return 0;\r
+ }\r
+\r
+ return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));\r
+}\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to PLLA clock.\r
+ *\r
+ * \param ul_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);\r
+}\r
+#endif\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to PLLB clock.\r
+ *\r
+ * \param ul_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;\r
+}\r
+#endif\r
+\r
+#if (SAM3XA)\r
+/**\r
+ * \brief Switch UDP (USB) clock source selection to UPLL clock.\r
+ *\r
+ * \param dw_usbdiv Clock divisor.\r
+ */\r
+void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)\r
+{\r
+ PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);\r
+}\r
+#endif\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+/**\r
+ * \brief Enable UDP (USB) clock.\r
+ */\r
+void pmc_enable_udpck(void)\r
+{\r
+# if (SAM3S || SAM4S)\r
+ PMC->PMC_SCER = PMC_SCER_UDP;\r
+# else\r
+ PMC->PMC_SCER = PMC_SCER_UOTGCLK;\r
+# endif\r
+}\r
+\r
+/**\r
+ * \brief Disable UDP (USB) clock.\r
+ */\r
+void pmc_disable_udpck(void)\r
+{\r
+# if (SAM3S || SAM4S)\r
+ PMC->PMC_SCDR = PMC_SCDR_UDP;\r
+# else\r
+ PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;\r
+# endif\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable PMC interrupts.\r
+ *\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void pmc_enable_interrupt(uint32_t ul_sources)\r
+{\r
+ PMC->PMC_IER = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Disable PMC interrupts.\r
+ *\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void pmc_disable_interrupt(uint32_t ul_sources)\r
+{\r
+ PMC->PMC_IDR = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Get PMC interrupt mask.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pmc_get_interrupt_mask(void)\r
+{\r
+ return PMC->PMC_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Get current status.\r
+ *\r
+ * \return The current PMC status.\r
+ */\r
+uint32_t pmc_get_status(void)\r
+{\r
+ return PMC->PMC_SR;\r
+}\r
+\r
+/**\r
+ * \brief Set the wake-up inputs for fast startup mode registers (event generation).\r
+ *\r
+ * \param ul_inputs Wake up inputs to enable.\r
+ */\r
+void pmc_set_fast_startup_input(uint32_t ul_inputs)\r
+{\r
+ ul_inputs &= PMC_FAST_STARTUP_Msk;\r
+ PMC->PMC_FSMR |= ul_inputs;\r
+}\r
+\r
+/**\r
+ * \brief Clear the wake-up inputs for fast startup mode registers (remove event generation).\r
+ *\r
+ * \param ul_inputs Wake up inputs to disable.\r
+ */\r
+void pmc_clr_fast_startup_input(uint32_t ul_inputs)\r
+{\r
+ ul_inputs &= PMC_FAST_STARTUP_Msk;\r
+ PMC->PMC_FSMR &= ~ul_inputs;\r
+}\r
+\r
+/**\r
+ * \brief Enable Sleep Mode.\r
+ * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0)\r
+ *\r
+ * \param uc_type 0 for wait for interrupt, 1 for wait for event.\r
+ */\r
+void pmc_enable_sleepmode(uint8_t uc_type)\r
+{\r
+ PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode\r
+ SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep\r
+\r
+ if (uc_type == 0) {\r
+ __WFI();\r
+ } else {\r
+ __WFE();\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable Wait Mode.\r
+ * Enter condition: WFE + (SLEEPDEEP bit = 0) + (LPM bit = 1)\r
+ */\r
+void pmc_enable_waitmode(void)\r
+{\r
+ uint32_t i;\r
+\r
+ PMC->PMC_FSMR |= PMC_FSMR_LPM; // Enter Wait mode\r
+ SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep\r
+ __WFE();\r
+\r
+ /* Waiting for MOSCRCEN bit cleared is strongly recommended\r
+ * to ensure that the core will not execute undesired instructions\r
+ */\r
+ for (i = 0; i < 500; i++) {\r
+ __NOP();\r
+ }\r
+ while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));\r
+}\r
+\r
+/**\r
+ * \brief Enable Backup Mode.\r
+ * Enter condition: WFE + (SLEEPDEEP bit = 1)\r
+ */\r
+void pmc_enable_backupmode(void)\r
+{\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+ __WFE();\r
+}\r
+\r
+/**\r
+ * \brief Enable Clock Failure Detector.\r
+ */\r
+void pmc_enable_clock_failure_detector(void)\r
+{\r
+ uint32_t ul_reg = PMC->CKGR_MOR;\r
+\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_CFDEN | ul_reg;\r
+}\r
+\r
+/**\r
+ * \brief Disable Clock Failure Detector.\r
+ */\r
+void pmc_disable_clock_failure_detector(void)\r
+{\r
+ uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);\r
+\r
+ PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | ul_reg;\r
+}\r
+\r
+/**\r
+ * \brief Enable or disable write protect of PMC registers.\r
+ *\r
+ * \param ul_enable 1 to enable, 0 to disable.\r
+ */\r
+void pmc_set_writeprotect(uint32_t ul_enable)\r
+{\r
+ if (ul_enable) {\r
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE | PMC_WPMR_WPEN;\r
+ } else {\r
+ PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Return write protect status.\r
+ *\r
+ * \retval 0 Protection disabled.\r
+ * \retval 1 Protection enabled.\r
+ */\r
+uint32_t pmc_get_writeprotect_status(void)\r
+{\r
+ return PMC->PMC_WPMR & PMC_WPMR_WPEN;\r
+}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Power Management Controller (PMC) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef PMC_H_INCLUDED\r
+#define PMC_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/** Bit mask for peripheral clocks (PCER0) */\r
+#define PMC_MASK_STATUS0 (0xFFFFFFFC)\r
+\r
+/** Bit mask for peripheral clocks (PCER1) */\r
+#define PMC_MASK_STATUS1 (0xFFFFFFFF)\r
+\r
+/** Loop counter timeout value */\r
+#define PMC_TIMEOUT (2048)\r
+\r
+/** Key to unlock CKGR_MOR register */\r
+#define PMC_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37)\r
+\r
+/** Key used to write SUPC registers */\r
+#define SUPC_KEY_VALUE ((uint32_t) 0xA5)\r
+\r
+/** PMC xtal startup time */\r
+#define PMC_XTAL_STARTUP_TIME (0x3F)\r
+\r
+/** Mask to access fast startup input */\r
+#define PMC_FAST_STARTUP_Msk (0x7FFFFu)\r
+\r
+/** PMC_WPMR Write Protect KEY, unlock it */\r
+#define PMC_WPMR_WPKEY_VALUE PMC_WPMR_WPKEY((uint32_t) 0x504D43)\r
+\r
+/** Using external oscillator */\r
+#define PMC_OSC_XTAL 0\r
+\r
+/** Oscillator in bypass mode */\r
+#define PMC_OSC_BYPASS 1\r
+\r
+#define PMC_PCK_0 0 /* PCK0 ID */\r
+#define PMC_PCK_1 1 /* PCK1 ID */\r
+#define PMC_PCK_2 2 /* PCK2 ID */\r
+\r
+/**\r
+ * \name Master clock (MCK) Source and Prescaler configuration\r
+ *\r
+ * The following functions may be used to select the clock source and\r
+ * prescaler for the master clock.\r
+ */\r
+//@{\r
+\r
+void pmc_mck_set_prescaler(uint32_t ul_pres);\r
+void pmc_mck_set_source(uint32_t ul_source);\r
+uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres);\r
+uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres);\r
+uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres);\r
+#if (SAM3S || SAM4S)\r
+uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres);\r
+#endif\r
+#if (SAM3XA || SAM3U)\r
+uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres);\r
+#endif\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Slow clock (SLCK) oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass);\r
+uint32_t pmc_osc_is_ready_32kxtal(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Main Clock (MAINCK) oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf);\r
+void pmc_osc_enable_fastrc(uint32_t ul_rc);\r
+void pmc_osc_disable_fastrc(void);\r
+void pmc_switch_mainck_to_xtal(uint32_t ul_bypass);\r
+void pmc_osc_disable_xtal(uint32_t ul_bypass);\r
+uint32_t pmc_osc_is_ready_mainck(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name PLL oscillator and configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva);\r
+void pmc_disable_pllack(void);\r
+uint32_t pmc_is_locked_pllack(void);\r
+\r
+#if (SAM3S || SAM4S)\r
+void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb);\r
+void pmc_disable_pllbck(void);\r
+uint32_t pmc_is_locked_pllbck(void);\r
+#endif\r
+\r
+#if (SAM3XA || SAM3U)\r
+void pmc_enable_upll_clock(void);\r
+void pmc_disable_upll_clock(void);\r
+uint32_t pmc_is_locked_upll(void);\r
+#endif\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Peripherals clock configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+uint32_t pmc_enable_periph_clk(uint32_t ul_id);\r
+uint32_t pmc_disable_periph_clk(uint32_t ul_id);\r
+void pmc_enable_all_periph_clk(void);\r
+void pmc_disable_all_periph_clk(void);\r
+uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Programmable clock Source and Prescaler configuration\r
+ *\r
+ * The following functions may be used to select the clock source and\r
+ * prescaler for the specified programmable clock.\r
+ */\r
+//@{\r
+\r
+void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres);\r
+void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source);\r
+uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres);\r
+uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres);\r
+uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres);\r
+#if (SAM3S || SAM4S)\r
+uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres);\r
+#endif\r
+#if (SAM3XA || SAM3U)\r
+uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres);\r
+#endif\r
+void pmc_enable_pck(uint32_t ul_id);\r
+void pmc_disable_pck(uint32_t ul_id);\r
+void pmc_enable_all_pck(void);\r
+void pmc_disable_all_pck(void);\r
+uint32_t pmc_is_pck_enabled(uint32_t ul_id);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name USB clock configuration\r
+ *\r
+ */\r
+//@{\r
+\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3S || SAM4S)\r
+void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3XA)\r
+void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv);\r
+#endif\r
+#if (SAM3S || SAM3XA || SAM4S)\r
+void pmc_enable_udpck(void);\r
+void pmc_disable_udpck(void);\r
+#endif\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Interrupt and status management\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_interrupt(uint32_t ul_sources);\r
+void pmc_disable_interrupt(uint32_t ul_sources);\r
+uint32_t pmc_get_interrupt_mask(void);\r
+uint32_t pmc_get_status(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Power management\r
+ *\r
+ * The following functions are used to configure sleep mode and additional \r
+ * wake up inputs.\r
+ */\r
+//@{\r
+\r
+void pmc_set_fast_startup_input(uint32_t ul_inputs);\r
+void pmc_clr_fast_startup_input(uint32_t ul_inputs);\r
+void pmc_enable_sleepmode(uint8_t uc_type);\r
+void pmc_enable_waitmode(void);\r
+void pmc_enable_backupmode(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Failure detector\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_enable_clock_failure_detector(void);\r
+void pmc_disable_clock_failure_detector(void);\r
+\r
+//@}\r
+\r
+/**\r
+ * \name Write protection\r
+ *\r
+ */\r
+//@{\r
+\r
+void pmc_set_writeprotect(uint32_t ul_enable);\r
+uint32_t pmc_get_writeprotect_status(void);\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+//! @}\r
+\r
+/**\r
+ * \page sam_pmc_quickstart Quick start guide for the SAM PMC module\r
+ *\r
+ * This is the quick start guide for the \ref pmc_group "PMC module", with\r
+ * step-by-step instructions on how to configure and use the driver in a\r
+ * selection of use cases.\r
+ *\r
+ * The use cases contain several code fragments. The code fragments in the\r
+ * steps for setup can be copied into a custom initialization function, while\r
+ * the steps for usage can be copied into, e.g., the main application function.\r
+ *\r
+ * \section pmc_use_cases PMC use cases\r
+ * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources\r
+ * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks\r
+ *\r
+ * \section pmc_basic_use_case Basic use case - Switch Main Clock sources\r
+ * In this use case, the PMC module is configured for a variety of system clock\r
+ * sources and speeds. A LED is used to visually indicate the current clock\r
+ * speed as the source is switched.\r
+ *\r
+ * \section pmc_basic_use_case_setup Setup\r
+ *\r
+ * \subsection pmc_basic_use_case_setup_prereq Prerequisites\r
+ * -# \ref gpio_group "General Purpose I/O Management (gpio)"\r
+ *\r
+ * \subsection pmc_basic_use_case_setup_code Code\r
+ * The following function needs to be added to the user application, to flash a\r
+ * board LED a variable number of times at a rate given in CPU ticks.\r
+ * \r
+ * \code\r
+ * #define FLASH_TICK_COUNT 0x00012345\r
+ *\r
+ * void flash_led(uint32_t tick_count, uint8_t flash_count)\r
+ * {\r
+ * SysTick->CTRL = SysTick_CTRL_ENABLE_Msk;\r
+ * SysTick->LOAD = tick_count;\r
+ * \r
+ * while (flash_count--)\r
+ * {\r
+ * gpio_toggle_pin(LED0_GPIO);\r
+ * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));\r
+ * gpio_toggle_pin(LED0_GPIO);\r
+ * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));\r
+ * }\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \section pmc_basic_use_case_usage Use case\r
+ *\r
+ * \subsection pmc_basic_use_case_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * for (;;)\r
+ * {\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * pmc_switch_mainck_to_xtal(0);\r
+ * flash_led(FLASH_TICK_COUNT, 5);\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_basic_use_case_usage_flow Workflow\r
+ * -# Wrap the code in an infinite loop:\r
+ * \code\r
+ * for (;;)\r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ * -# Switch the Master CPU frequency to the external crystal oscillator, flash\r
+ * a LED on the board several times:\r
+ * \code\r
+ * pmc_switch_mainck_to_xtal(0);\r
+ * flash_led(FLASH_TICK_COUNT, 5); \r
+ * \endcode\r
+ */\r
+\r
+/**\r
+ * \page pmc_use_case_2 Use case #2 - Configure Programmable Clocks\r
+ * In this use case, the PMC module is configured to start the Slow Clock from\r
+ * an attached 32KHz crystal, and start one of the Programmable Clock modules\r
+ * sourced from the Slow Clock divided down with a prescale factor of 64.\r
+ *\r
+ * \section pmc_use_case_2_setup Setup\r
+ *\r
+ * \subsection pmc_use_case_2_setup_prereq Prerequisites\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ *\r
+ * \subsection pmc_use_case_2_setup_code Code\r
+ * The following code must be added to the user application:\r
+ * \code\r
+ * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_use_case_2_setup_code_workflow Workflow\r
+ * -# Configure the PCK1 pin to output on a specific port pin (in this case,\r
+ * PIOA pin 17) of the microcontroller.\r
+ * \code\r
+ * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);\r
+ * \endcode\r
+ * \note The peripheral selection and pin will vary according to your selected\r
+ * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O\r
+ * Lines" of your device's datasheet.\r
+ *\r
+ * \section pmc_use_case_2_usage Use case\r
+ * The generated PCK1 clock output can be viewed on an oscilloscope attached to\r
+ * the correct pin of the microcontroller.\r
+ *\r
+ * \subsection pmc_use_case_2_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);\r
+ * pmc_enable_pck(PMC_PCK_1);\r
+ *\r
+ * for (;;)\r
+ * {\r
+ * // Do Nothing\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection pmc_use_case_2_usage_flow Workflow\r
+ * -# Switch the Slow Clock source input to an external 32KHz crystal:\r
+ * \code\r
+ * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);\r
+ * \endcode\r
+ * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock,\r
+ * with a prescaler of 64:\r
+ * \code\r
+ * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);\r
+ * \endcode\r
+ * -# Enable Programmable Clock module PCK1:\r
+ * \code\r
+ * pmc_enable_pck(PMC_PCK_1);\r
+ * \endcode\r
+ * -# Enter an infinite loop:\r
+ * \code\r
+ * for (;;)\r
+ * {\r
+ * // Do Nothing\r
+ * }\r
+ * \endcode\r
+ */\r
+\r
+#endif /* PMC_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Sleep mode access\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SLEEP_H\r
+#define SLEEP_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <compiler.h>\r
+\r
+/**\r
+ * \defgroup sleep_group Power Manager (PM)\r
+ *\r
+ * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr service.\r
+ *\r
+ * \note To minimize the code overhead, these functions do not feature\r
+ * interrupt-protected access since they are likely to be called inside\r
+ * interrupt handlers or in applications where such protection is not\r
+ * necessary. If such protection is needed, it must be ensured by the calling\r
+ * code.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#if defined(__DOXYGEN__)\r
+/**\r
+ * \brief Sets the MCU in the specified sleep mode\r
+ * \param sleep_mode Sleep mode to set.\r
+ */\r
+#endif\r
+\r
+#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S) // SAM3 and SAM4 series\r
+# include "pmc.h"\r
+\r
+# define SAM_PM_SMODE_ACTIVE 0\r
+# define SAM_PM_SMODE_SLEEP_WFE 1\r
+# define SAM_PM_SMODE_SLEEP_WFI 2\r
+# define SAM_PM_SMODE_WAIT 3\r
+# define SAM_PM_SMODE_BACKUP 4\r
+\r
+/* (SCR) Sleep deep bit */\r
+#define SCR_SLEEPDEEP (0x1 << 2)\r
+\r
+/**\r
+ * Save clock settings and shutdown PLLs\r
+ */\r
+static inline void pmc_save_clock_settings(\r
+ uint32_t *p_osc_setting,\r
+ uint32_t *p_pll0_setting,\r
+ uint32_t *p_pll1_setting,\r
+ uint32_t *p_mck_setting)\r
+{\r
+ if (p_osc_setting) {\r
+ *p_osc_setting = PMC->CKGR_MOR;\r
+ }\r
+ if (p_pll0_setting) {\r
+ *p_pll0_setting = PMC->CKGR_PLLAR;\r
+ }\r
+ if (p_pll1_setting) {\r
+#if SAM3S||SAM4S\r
+ *p_pll1_setting = PMC->CKGR_PLLBR;\r
+#elif SAM3U||SAM3XA\r
+ *p_pll1_setting = PMC->CKGR_UCKR;\r
+#else\r
+ *p_pll1_setting = 0;\r
+#endif\r
+ }\r
+ if (p_mck_setting) {\r
+ *p_mck_setting = PMC->PMC_MCKR;\r
+ }\r
+\r
+ // Switch MCK to Main clock (internal or external 12MHz) for fast wakeup\r
+ // If MAIN_CLK is already the source, just skip\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_MAIN_CLK) {\r
+ return;\r
+ }\r
+ // If we have to enable the MAIN_CLK\r
+ if ((PMC->PMC_SR & PMC_SR_MOSCXTS) == 0) {\r
+ // Intend to use internal RC as source of MAIN_CLK\r
+ pmc_osc_enable_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);\r
+ }\r
+ pmc_switch_mck_to_mainck(PMC_MCKR_PRES_CLK_1);\r
+}\r
+\r
+/**\r
+ * Restore clock settings\r
+ */\r
+static inline void pmc_restore_clock_setting(\r
+ uint32_t osc_setting,\r
+ uint32_t pll0_setting,\r
+ uint32_t pll1_setting,\r
+ uint32_t mck_setting)\r
+{\r
+ uint32_t mckr;\r
+ if ((pll0_setting & CKGR_PLLAR_MULA_Msk) &&\r
+ pll0_setting != PMC->CKGR_PLLAR) {\r
+ PMC->CKGR_PLLAR = 0;\r
+ PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA));\r
+ }\r
+#if SAM3S||SAM4S\r
+ if ((pll1_setting & CKGR_PLLBR_MULB_Msk) &&\r
+ pll1_setting != PMC->CKGR_PLLBR) {\r
+ PMC->CKGR_PLLBR = 0;\r
+ PMC->CKGR_PLLBR = pll1_setting ;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKB));\r
+ }\r
+#elif SAM3U||SAM3XA\r
+ if ((pll1_setting & CKGR_UCKR_UPLLEN) &&\r
+ pll1_setting != PMC->CKGR_UCKR) {\r
+ PMC->CKGR_UCKR = 0;\r
+ PMC->CKGR_UCKR = pll1_setting;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKU));\r
+ }\r
+#else\r
+ UNUSED(pll1_setting);\r
+#endif\r
+ /* Switch to faster clock */\r
+ mckr = PMC->PMC_MCKR;\r
+ // Set PRES\r
+ PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk)\r
+ | (mck_setting & PMC_MCKR_PRES_Msk);\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+ // Set CSS and others\r
+ PMC->PMC_MCKR = mck_setting;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY));\r
+ /* Shutdown fastrc */\r
+ if (0 == (osc_setting & CKGR_MOR_MOSCRCEN)) {\r
+ pmc_osc_disable_fastrc();\r
+ }\r
+}\r
+\r
+static inline void pmc_sleep(int sleep_mode)\r
+{\r
+ switch (sleep_mode) {\r
+ case SAM_PM_SMODE_SLEEP_WFI:\r
+ case SAM_PM_SMODE_SLEEP_WFE:\r
+ PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM;\r
+ SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;\r
+ cpu_irq_enable();\r
+ if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI)\r
+ __WFI();\r
+ else\r
+ __WFE();\r
+ break;\r
+\r
+ case SAM_PM_SMODE_WAIT: {\r
+ uint32_t mor, pllr0, pllr1, mckr;\r
+ pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr);\r
+\r
+ PMC->PMC_FSMR |= PMC_FSMR_LPM;\r
+ SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP ;\r
+ cpu_irq_enable();\r
+ __WFE();\r
+\r
+ cpu_irq_disable();\r
+ pmc_restore_clock_setting(mor, pllr0, pllr1, mckr);\r
+ cpu_irq_enable();\r
+ break;\r
+ }\r
+\r
+ case SAM_PM_SMODE_BACKUP:\r
+ SCB->SCR |= SCR_SLEEPDEEP ;\r
+ cpu_irq_enable();\r
+ __WFE() ;\r
+ break;\r
+ }\r
+}\r
+\r
+#endif\r
+\r
+//! @}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* SLEEP_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+ \r
+#include "usart.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup sam_drivers_usart_group Universal Synchronous Asynchronous Receiver Transmitter (USART)\r
+ *\r
+ * The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex \r
+ * universal synchronous asynchronous serial link. Data frame format is widely programmable\r
+ * (data length, parity, number of stop bits) to support a maximum of standards. The receiver\r
+ * implements parity error, framing error and overrun error detection. The receiver time-out enables\r
+ * handling variable-length frames and the transmitter timeguard facilitates communications with\r
+ * slow remote devices. Multidrop communications are also supported through address bit handling\r
+ * in reception and transmission.\r
+ * The driver supports the following modes: RS232, RS485, SPI, IrDA, ISO7816, MODEM,\r
+ * Hardware handshaking and LIN.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/* The write protect key value. */\r
+#define US_WPKEY_VALUE 0x555341\r
+\r
+/* The CD value scope programmed in MR register. */\r
+#define MIN_CD_VALUE 0x01\r
+#define MIN_CD_VALUE_SPI 0x04\r
+#define MAX_CD_VALUE US_BRGR_CD_Msk\r
+\r
+/* Define the default time-out value for USART. */\r
+#define USART_DEFAULT_TIMEOUT 1000\r
+\r
+/* The receiver sampling divide of baudrate clock. */\r
+#define HIGH_FRQ_SAMPLE_DIV 16\r
+#define LOW_FRQ_SAMPLE_DIV 8\r
+\r
+/* Max transmitter timeguard. */\r
+#define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk\r
+\r
+/* The non-existent parity error number. */\r
+#define USART_PARITY_ERROR 5\r
+\r
+/* ISO7816 protocol type. */\r
+#define ISO7816_T_0 0\r
+#define ISO7816_T_1 1\r
+\r
+/**\r
+ * \brief Calculate a clock divider(CD) and a fractional part (FP) for the \r
+ * USART asynchronous modes to generate a baudrate as close as possible to \r
+ * the baudrate set point.\r
+ *\r
+ * \note Baud rate calculation: Baudrate = ul_mck/(Over * (CD + FP/8))\r
+ * (Over being 16 or 8). The maximal oversampling is selected if it allows to \r
+ * generate a baudrate close to the set point.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param baudrate Baud rate set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 Baud rate is successfully initialized.\r
+ * \retval 1 Baud rate set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_async_baudrate(Usart *p_usart,\r
+ uint32_t baudrate, uint32_t ul_mck)\r
+{\r
+ uint32_t over;\r
+ uint32_t cd_fp;\r
+ uint32_t cd;\r
+ uint32_t fp;\r
+\r
+ /* Calculate the receiver sampling divide of baudrate clock. */\r
+ if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) {\r
+ over = HIGH_FRQ_SAMPLE_DIV;\r
+ } else {\r
+ over = LOW_FRQ_SAMPLE_DIV;\r
+ }\r
+\r
+ /* Calculate the clock divider according to the fraction calculated formula. */\r
+ cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate);\r
+ cd = cd_fp >> 3;\r
+ fp = cd_fp & 0x07;\r
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the OVER bit in MR register. */\r
+ if (over == 8) {\r
+ p_usart->US_MR |= US_MR_OVER;\r
+ }\r
+\r
+ /* Configure the baudrate generate register. */\r
+ p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Calculate a clock divider for the USART synchronous master modes\r
+ * to generate a baudrate as close as possible to the baudrate set point.\r
+ *\r
+ * \note Synchronous baudrate calculation: baudrate = ul_mck / cd\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param baudrate Baud rate set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 Baud rate is successfully initialized.\r
+ * \retval 1 Baud rate set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_sync_master_baudrate(Usart *p_usart,\r
+ uint32_t baudrate, uint32_t ul_mck)\r
+{\r
+ uint32_t cd;\r
+\r
+ /* Calculate the clock divider according to the formula in synchronous mode. */\r
+ cd = (ul_mck + baudrate / 2) / baudrate;\r
+\r
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the baudrate generate register. */\r
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;\r
+\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |\r
+ US_MR_USCLKS_MCK | US_MR_SYNC;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Select the SCK pin as the source of baud rate for the USART\r
+ * synchronous slave modes.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+static void usart_set_sync_slave_baudrate(Usart *p_usart)\r
+{\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) |\r
+ US_MR_USCLKS_SCK | US_MR_SYNC;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Calculate a clock divider (\e CD) for the USART ISO7816 mode to \r
+ * generate an ISO7816 clock as close as possible to the clock set point.\r
+ *\r
+ * \note ISO7816 clock calculation: Clock = ul_mck / cd\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param clock ISO7816 clock set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 ISO7816 clock is successfully initialized.\r
+ * \retval 1 ISO7816 clock set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_iso7816_clock(Usart *p_usart,\r
+ uint32_t clock, uint32_t ul_mck)\r
+{\r
+ uint32_t cd;\r
+\r
+ /* Calculate the clock divider according to the formula in ISO7816 mode. */\r
+ cd = (ul_mck + clock / 2) / clock;\r
+\r
+ if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC |\r
+ US_MR_OVER)) | US_MR_USCLKS_MCK | US_MR_CLKO;\r
+\r
+ /* Configure the baudrate generate register. */\r
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Calculate a clock divider (\e CD) for the USART SPI master mode to\r
+ * generate a baud rate as close as possible to the baud rate set point.\r
+ *\r
+ * \note Baud rate calculation:\r
+ * \f$ Baudrate = \frac{SelectedClock}{CD} \f$.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param baudrate Baud rate set point.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 Baud rate is successfully initialized.\r
+ * \retval 1 Baud rate set point is out of range for the given input clock \r
+ * frequency.\r
+ */\r
+static uint32_t usart_set_spi_master_baudrate(Usart *p_usart,\r
+ uint32_t baudrate, uint32_t ul_mck)\r
+{\r
+ uint32_t cd;\r
+\r
+ /* Calculate the clock divider according to the formula in SPI mode. */\r
+ cd = (ul_mck + baudrate / 2) / baudrate;\r
+\r
+ if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) {\r
+ return 1;\r
+ }\r
+\r
+ p_usart->US_BRGR = cd << US_BRGR_CD_Pos;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Select the SCK pin as the source of baudrate for the USART SPI slave \r
+ * mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+static void usart_set_spi_slave_baudrate(Usart *p_usart)\r
+{\r
+ p_usart->US_MR &= ~US_MR_USCLKS_Msk;\r
+ p_usart->US_MR |= US_MR_USCLKS_SCK;\r
+}\r
+\r
+/**\r
+ * \brief Reset the USART and disable TX and RX.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset(Usart *p_usart)\r
+{\r
+ /* Disable the Write Protect. Some register can't be written if the write protect is enabled. */\r
+ usart_disable_writeprotect(p_usart);\r
+\r
+ /* Reset mode and other registers that could cause unpredictable behavior after reset. */\r
+ p_usart->US_MR = 0;\r
+ p_usart->US_RTOR = 0;\r
+ p_usart->US_TTGR = 0;\r
+\r
+ /* Disable TX and RX, reset status bits and turn off RTS and DTR if exist. */\r
+ usart_reset_tx(p_usart);\r
+ usart_reset_rx(p_usart);\r
+ usart_reset_status(p_usart);\r
+ usart_drive_RTS_pin_high(p_usart);\r
+#if (SAM3S || SAM4S || SAM3U)\r
+ usart_drive_DTR_pin_high(p_usart);\r
+#endif\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in RS232 mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_rs232(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ ul_reg_val = 0;\r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ usart_set_async_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length, parity type, channel mode and stop bit length. */\r
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |\r
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;\r
+ \r
+ /* Configure the USART mode as normal mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_NORMAL;\r
+ \r
+ p_usart->US_MR |= ul_reg_val;\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in hardware handshaking mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_hw_handshaking(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set hardware handshaking mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_HW_HANDSHAKING;\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3S || SAM4S || SAM3U)\r
+/**\r
+ * \brief Configure USART to work in modem mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_modem(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* SAM3S || SAM4S series support MODEM mode only on USART1, and \r
+ SAM3U series support MODEM mode only on USART0. */\r
+#if (SAM3S || SAM4S)\r
+ if (p_usart != USART1) {\r
+ return 1;\r
+ }\r
+#elif (SAM3U)\r
+ if (p_usart != USART0) {\r
+ return 1;\r
+ }\r
+#endif\r
+\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set MODEM mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_MODEM;\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Configure USART to work in SYNC mode and act as a master.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_sync_master(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ ul_reg_val = 0;\r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ usart_set_sync_master_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length, parity type, channel mode and stop bit length. */\r
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |\r
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;\r
+ \r
+ /* Set normal mode and output clock on the SCK pin as synchronous master. */\r
+ ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO;\r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in SYNC mode and act as a slave.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_sync_slave(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt)\r
+{\r
+ static uint32_t ul_reg_val;\r
+ \r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ usart_set_sync_slave_baudrate(p_usart);\r
+ \r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length, parity type, channel mode and stop bit length. */\r
+ ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type |\r
+ p_usart_opt->channel_mode | p_usart_opt->stop_bits;\r
+\r
+ /* Set normal mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_NORMAL;\r
+ p_usart->US_MR |= ul_reg_val; \r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in RS485 mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_rs485(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set RS485 mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_RS485;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in IrDA mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_irda(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Initialize the USART as standard RS232. */\r
+ if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set IrDA filter. */\r
+ p_usart->US_IF = p_usart_opt->irda_filter;\r
+\r
+ /* Set IrDA mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_IRDA;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in ISO7816 mode.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_iso7816(Usart *p_usart,\r
+ const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+ \r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ \r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) &&\r
+ (p_usart_opt->parity_type != US_MR_PAR_ODD))) {\r
+ return 1;\r
+ }\r
+ \r
+ if (p_usart_opt->protocol_type == ISO7816_T_0) {\r
+ ul_reg_val |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT |\r
+ (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos);\r
+\r
+ if (p_usart_opt->bit_order) {\r
+ ul_reg_val |= US_MR_MSBF;\r
+ }\r
+ } else if (p_usart_opt->protocol_type == ISO7816_T_1) {\r
+ /* Only LSBF is used in the T=1 protocol, and max_iterations field is only used in T=0 mode.*/\r
+ if (p_usart_opt->bit_order || p_usart_opt->max_iterations) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */\r
+ ul_reg_val |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT;\r
+ } else {\r
+ return 1;\r
+ }\r
+\r
+ /* Set up the baudrate. */\r
+ if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */\r
+ p_usart->US_FIDI = p_usart_opt->fidi_ratio;\r
+\r
+ /* Set ISO7816 parity type in the MODE register. */\r
+ ul_reg_val |= p_usart_opt->parity_type;\r
+ \r
+ if (p_usart_opt->inhibit_nack) {\r
+ ul_reg_val |= US_MR_INACK;\r
+ }\r
+ if (p_usart_opt->dis_suc_nack) {\r
+ ul_reg_val |= US_MR_DSNACK;\r
+ }\r
+ \r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in SPI mode and act as a master.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_spi_master(Usart *p_usart,\r
+ const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ static uint32_t ul_reg_val;\r
+ \r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ (p_usart_opt->spi_mode > SPI_MODE_3) ||\r
+ usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length bit in MR register. */\r
+ ul_reg_val |= p_usart_opt->char_length;\r
+ \r
+ /* Set SPI master mode and channel mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO |\r
+ p_usart_opt->channel_mode;\r
+ \r
+ switch (p_usart_opt->spi_mode) {\r
+ case SPI_MODE_0:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_1:\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_2:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val |= US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_3:\r
+ ul_reg_val |= US_MR_CPOL;\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ \r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in SPI mode and act as a slave.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_spi_slave(Usart *p_usart,\r
+ const usart_spi_opt_t *p_usart_opt)\r
+{\r
+ static uint32_t ul_reg_val;\r
+\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+ \r
+ ul_reg_val = 0;\r
+ usart_set_spi_slave_baudrate(p_usart);\r
+ \r
+ /* Check whether the input values are legal. */\r
+ if (!p_usart_opt ||\r
+ p_usart_opt->spi_mode > SPI_MODE_3) {\r
+ return 1;\r
+ }\r
+\r
+ /* Configure the character length bit in MR register. */\r
+ ul_reg_val |= p_usart_opt->char_length;\r
+ \r
+ /* Set SPI slave mode and channel mode. */\r
+ ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode;\r
+ \r
+ switch (p_usart_opt->spi_mode) {\r
+ case SPI_MODE_0:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_1:\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ ul_reg_val &= ~US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_2:\r
+ ul_reg_val |= US_MR_CPHA;\r
+ ul_reg_val |= US_MR_CPOL;\r
+ break;\r
+ case SPI_MODE_3:\r
+ ul_reg_val |= US_MR_CPOL;\r
+ ul_reg_val &= ~US_MR_CPHA;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ p_usart->US_MR |= ul_reg_val;\r
+\r
+ return 0;\r
+}\r
+\r
+#if SAM3XA\r
+/**\r
+ * \brief Configure USART to work in LIN mode and act as a LIN master.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_lin_master(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ /* Set up the baudrate. */\r
+ if (usart_set_async_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set LIN master mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_LIN_MASTER; \r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Configure USART to work in LIN mode and act as a LIN slave.\r
+ *\r
+ * \note By default, the transmitter and receiver aren't enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param p_usart_opt Pointer to sam_usart_opt_t instance.\r
+ * \param ul_mck USART module input clock frequency.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_init_lin_slave(Usart *p_usart,\r
+ const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck)\r
+{\r
+ /* Reset the USART and shut down TX and RX. */\r
+ usart_reset(p_usart);\r
+\r
+ /* Set up the baudrate. */\r
+ if (usart_set_async_baudrate(p_usart, p_usart_opt->baudrate, ul_mck)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Set LIN slave mode. */\r
+ p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) |\r
+ US_MR_USART_MODE_LIN_SLAVE;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Abort the current LIN transmission.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_abort_tx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_LINABT;\r
+}\r
+\r
+/**\r
+ * \brief Send a wakeup signal on the LIN bus.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_send_wakeup_signal(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_LINWKUP;\r
+}\r
+\r
+/**\r
+ * \brief Configure the LIN node action, which should be one of PUBLISH,\r
+ * SUBSCRIBE or IGNORE.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE.\r
+ */\r
+void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) |\r
+ (uc_action << US_LINMR_NACT_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Disable the parity check during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_parity(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_PARDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the parity check during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_parity(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_PARDIS;\r
+}\r
+\r
+/**\r
+ * \brief Disable the checksum during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_checksum(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_CHKDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the checksum during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_checksum(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_CHKDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the checksum type during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic checksum.\r
+ */\r
+void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) |\r
+ (uc_type << 4);\r
+}\r
+\r
+/**\r
+ * \brief Configure the data length mode during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_mode Indicate the checksum type: 0 if the data length is defined by the \r
+ * DLC of LIN mode register or 1 if the data length is defined by the bit 5 and 6 of \r
+ * the identifier.\r
+ */\r
+void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) |\r
+ (uc_mode << 5);\r
+}\r
+\r
+/**\r
+ * \brief Disable the frame slot mode during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_frame_slot(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_FSDIS;\r
+}\r
+\r
+/**\r
+ * \brief Enable the frame slot mode during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_frame_slot(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_FSDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the wakeup signal type during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_type Indicate the checksum type: 0 if the wakeup signal is a LIN 2.0 \r
+ * wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal.\r
+ */\r
+void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) |\r
+ (uc_type << 7);\r
+}\r
+\r
+/**\r
+ * \brief Configure the response data length if the data length is defined by\r
+ * the DLC field during the LIN communication.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_len Indicate the response data length.\r
+ */\r
+void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len)\r
+{\r
+ p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) |\r
+ (uc_len << US_LINMR_DLC_Pos);\r
+}\r
+\r
+/**\r
+ * \brief The LIN mode register is not written by the PDC.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_disable_pdc_mode(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR &= ~US_LINMR_PDCM;\r
+}\r
+\r
+/**\r
+ * \brief The LIN mode register (except this flag) is written by the PDC.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_lin_enable_pdc_mode(Usart *p_usart)\r
+{\r
+ p_usart->US_LINMR |= US_LINMR_PDCM;\r
+}\r
+\r
+/**\r
+ * \brief Configure the LIN identifier when USART works in LIN master mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_id The identifier to be transmitted.\r
+ */\r
+void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id)\r
+{\r
+ p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) |\r
+ US_LINIR_IDCHR(uc_id);\r
+}\r
+\r
+/**\r
+ * \brief Read the identifier when USART works in LIN mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return The last identifier received in LIN slave mode or the last identifier \r
+ * transmitted in LIN master mode. \r
+ */\r
+uint8_t usart_lin_read_identifier(Usart *p_usart)\r
+{\r
+ return (p_usart->US_LINMR & US_LINIR_IDCHR_Msk);\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable USART transmitter.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_enable_tx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_TXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable USART transmitter.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_disable_tx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_TXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Immediately stop and disable USART transmitter.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_tx(Usart *p_usart)\r
+{\r
+ /* Reset transmitter */\r
+ p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the transmit timeguard register.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param timeguard The value of transmit timeguard.\r
+ */\r
+void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard)\r
+{\r
+ p_usart->US_TTGR = timeguard;\r
+}\r
+\r
+/**\r
+ * \brief Enable USART receiver.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_enable_rx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RXEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable USART receiver.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_disable_rx(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Immediately stop and disable USART receiver.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_rx(Usart *p_usart)\r
+{\r
+ /* Reset Receiver */\r
+ p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS;\r
+}\r
+\r
+/**\r
+ * \brief Configure the receive timeout register.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param timeout The value of receive timeout.\r
+ */\r
+void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout)\r
+{\r
+ p_usart->US_RTOR = timeout;\r
+}\r
+\r
+/**\r
+ * \brief Enable USART interrupts.\r
+ *\r
+ * \param p_usart Pointer to a USART peripheral.\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources)\r
+{\r
+ p_usart->US_IER = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Disable USART interrupts.\r
+ *\r
+ * \param p_usart Pointer to a USART peripheral.\r
+ * \param ul_sources Interrupt sources bit map.\r
+ */\r
+void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources)\r
+{\r
+ p_usart->US_IDR = ul_sources;\r
+}\r
+\r
+/**\r
+ * \brief Read USART interrupt mask.\r
+ *\r
+ * \param p_usart Pointer to a USART peripheral.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t usart_get_interrupt_mask(Usart *p_usart)\r
+{\r
+ return p_usart->US_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Get current status.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return The current USART status.\r
+ */\r
+uint32_t usart_get_status(Usart *p_usart)\r
+{\r
+ return p_usart->US_CSR;\r
+}\r
+\r
+/**\r
+ * \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_status(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RSTSTA;\r
+}\r
+\r
+/**\r
+ * \brief Start transmission of a break.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_start_tx_break(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_STTBRK;\r
+}\r
+\r
+/**\r
+ * \brief Stop transmission of a break.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_stop_tx_break(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_STPBRK;\r
+}\r
+\r
+/**\r
+ * \brief Start waiting for a character before clocking the timeout count.\r
+ * Reset the status bit TIMEOUT in US_CSR. \r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_start_rx_timeout(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_STTTO;\r
+}\r
+\r
+/**\r
+ * \brief In Multidrop mode only, the next character written to the US_THR\r
+ * is sent with the address bit set. \r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param ul_addr The address to be sent out.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr)\r
+{\r
+ if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) {\r
+ return 1;\r
+ }\r
+ \r
+ p_usart->US_CR = US_CR_SENDA;\r
+ \r
+ if (usart_write(p_usart, ul_addr)) {\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_iterations(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RSTIT;\r
+}\r
+\r
+/**\r
+ * \brief Reset NACK in US_CSR.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_reset_nack(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RSTNACK;\r
+}\r
+\r
+/**\r
+ * \brief Restart the receive timeout.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_restart_rx_timeout(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RETTO;\r
+}\r
+\r
+#if (SAM3S || SAM4S || SAM3U)\r
+/**\r
+ * \brief Drive the pin DTR to 0.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_DTR_pin_low(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_DTREN;\r
+}\r
+\r
+/**\r
+ * \brief Drive the pin DTR to 1.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_DTR_pin_high(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_DTRDIS;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Drive the pin RTS to 0.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_RTS_pin_low(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RTSEN;\r
+}\r
+\r
+/**\r
+ * \brief Drive the pin RTS to 1.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_drive_RTS_pin_high(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RTSDIS;\r
+}\r
+\r
+/**\r
+ * \brief Drive the slave select line NSS (RTS pin) to 0 in SPI master mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_spi_force_chip_select(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_FCS;\r
+}\r
+\r
+/**\r
+ * \brief Drive the slave select line NSS (RTS pin) to 1 in SPI master mode.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_spi_release_chip_select(Usart *p_usart)\r
+{\r
+ p_usart->US_CR = US_CR_RCS;\r
+}\r
+\r
+/**\r
+ * \brief Check if Transmit is Ready.\r
+ * Check if data have been loaded in USART_THR and are waiting to be loaded \r
+ * into the Transmit Shift Register (TSR).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 No data is in the Transmit Holding Register.\r
+ * \retval 0 There is data in the Transmit Holding Register.\r
+ */\r
+uint32_t usart_is_tx_ready(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_TXRDY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if Transmit Holding Register is empty.\r
+ * Check if the last data written in USART_THR have been loaded in TSR and the last\r
+ * data loaded in TSR have been transmitted.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Transmitter is empty.\r
+ * \retval 0 Transmitter is not empty.\r
+ */\r
+uint32_t usart_is_tx_empty(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if the received data are ready.\r
+ * Check if Data have been received and loaded into USART_RHR.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Some data has been received.\r
+ * \retval 0 No data has been received.\r
+ */\r
+uint32_t usart_is_rx_ready(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_RXRDY) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if one receive buffer is filled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Receive is complete.\r
+ * \retval 0 Receive is still pending.\r
+ */\r
+uint32_t usart_is_rx_buf_end(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_ENDRX) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if one transmit buffer is empty.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Transmit is complete.\r
+ * \retval 0 Transmit is still pending.\r
+ */\r
+uint32_t usart_is_tx_buf_end(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_ENDTX) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if both receive buffers are full.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Receive buffers are full.\r
+ * \retval 0 Receive buffers are not full.\r
+ */\r
+uint32_t usart_is_rx_buf_full(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_RXBUFF) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Check if both transmit buffers are empty.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \retval 1 Transmit buffers are empty.\r
+ * \retval 0 Transmit buffers are not empty.\r
+ */\r
+uint32_t usart_is_tx_buf_empty(Usart *p_usart)\r
+{\r
+ return (p_usart->US_CSR & US_CSR_TXBUFE) > 0;\r
+}\r
+\r
+/**\r
+ * \brief Write to USART Transmit Holding Register.\r
+ *\r
+ * \note Before writing user should check if tx is ready (or empty).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Data to be sent.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_write(Usart *p_usart, uint32_t c)\r
+{\r
+ if (!(p_usart->US_CSR & US_CSR_TXRDY)) {\r
+ return 1;\r
+ }\r
+\r
+ p_usart->US_THR = US_THR_TXCHR(c);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Write to USART Transmit Holding Register.\r
+ *\r
+ * \note Before writing user should check if tx is ready (or empty).\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Data to be sent.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_putchar(Usart *p_usart, uint32_t c)\r
+{\r
+ uint32_t timeout = USART_DEFAULT_TIMEOUT;\r
+\r
+ while (!(p_usart->US_CSR & US_CSR_TXRDY)) {\r
+ if (!timeout--) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ p_usart->US_THR = US_THR_TXCHR(c);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Write one-line string through USART.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param string Pointer to one-line string to be sent.\r
+ */\r
+void usart_write_line(Usart *p_usart, const char *string)\r
+{\r
+ while (*string != '\0') {\r
+ usart_putchar(p_usart, *string++);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Read from USART Receive Holding Register.\r
+ *\r
+ * \note Before reading user should check if rx is ready.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Pointer where the one-byte received data will be stored.\r
+ *\r
+ * \retval 0 on success.\r
+ * \retval 1 if no data is available or errors.\r
+ */\r
+uint32_t usart_read(Usart *p_usart, uint32_t *c)\r
+{\r
+ if (!(p_usart->US_CSR & US_CSR_RXRDY)) {\r
+ return 1;\r
+ }\r
+ \r
+ /* Read character */\r
+ *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Read from USART Receive Holding Register.\r
+ * Before reading user should check if rx is ready.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param c Pointer where the one-byte received data will be stored.\r
+ *\r
+ * \retval 0 Data has been received.\r
+ * \retval 1 on failure.\r
+ */\r
+uint32_t usart_getchar(Usart *p_usart, uint32_t *c)\r
+{\r
+ uint32_t timeout = USART_DEFAULT_TIMEOUT;\r
+\r
+ /* If the receiver is empty, wait until it's not empty or timeout has reached. */\r
+ while (!(p_usart->US_CSR & US_CSR_RXRDY)) {\r
+ if (!timeout--) {\r
+ return 1;\r
+ }\r
+ }\r
+\r
+ /* Read character */\r
+ *c = p_usart->US_RHR & US_RHR_RXCHR_Msk;\r
+\r
+ return 0;\r
+}\r
+\r
+#if (SAM3XA || SAM3U)\r
+/**\r
+ * \brief Get Transmit address for DMA operation.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return Transmit address for DMA access.\r
+ */\r
+uint32_t *usart_get_tx_access(Usart *p_usart)\r
+{\r
+ return (uint32_t *)&(p_usart->US_THR);\r
+}\r
+\r
+/**\r
+ * \brief Get Receive address for DMA operation.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return Receive address for DMA access.\r
+ */\r
+uint32_t *usart_get_rx_access(Usart *p_usart)\r
+{\r
+ return (uint32_t *)&(p_usart->US_RHR);\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Get USART PDC base address.\r
+ *\r
+ * \param p_usart Pointer to a UART instance.\r
+ *\r
+ * \return USART PDC registers base for PDC driver to access.\r
+ */\r
+Pdc *usart_get_pdc_base(Usart *p_usart)\r
+{\r
+ Pdc *p_pdc_base;\r
+\r
+ p_pdc_base = (Pdc *) NULL;\r
+\r
+ if (p_usart == USART0) {\r
+ p_pdc_base = PDC_USART0;\r
+ return p_pdc_base;\r
+ }\r
+#if (SAM3S || SAM4S || SAM3XA || SAM3U)\r
+ else if (p_usart == USART1) {\r
+ p_pdc_base = PDC_USART1;\r
+ return p_pdc_base;\r
+ }\r
+#endif\r
+#if (SAM3SD8 || SAM3XA || SAM3U)\r
+ else if (p_usart == USART2) {\r
+ p_pdc_base = PDC_USART2;\r
+ return p_pdc_base;\r
+ }\r
+#endif\r
+#if (SAM3XA || SAM3U)\r
+ else if (p_usart == USART3) {\r
+ p_pdc_base = PDC_USART3;\r
+ return p_pdc_base;\r
+ }\r
+#endif\r
+\r
+ return p_pdc_base;\r
+}\r
+\r
+/**\r
+ * \brief Enable write protect of USART registers.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_enable_writeprotect(Usart *p_usart)\r
+{\r
+ p_usart->US_WPMR = US_WPMR_WPEN | US_WPMR_WPKEY(US_WPKEY_VALUE);\r
+}\r
+\r
+/**\r
+ * \brief Disable write protect of USART registers.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_disable_writeprotect(Usart *p_usart)\r
+{\r
+ p_usart->US_WPMR = US_WPMR_WPKEY(US_WPKEY_VALUE);\r
+}\r
+\r
+/**\r
+ * \brief Get write protect status.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return 0 if the peripheral is not protected. \r
+ * \return 16-bit Write Protect Violation Status otherwise.\r
+ */\r
+uint32_t usart_get_writeprotect_status(Usart *p_usart)\r
+{\r
+ uint32_t reg_value;\r
+\r
+ reg_value = p_usart->US_WPSR;\r
+ if (reg_value & US_WPSR_WPVS) {\r
+ return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get the total number of errors that occur during an ISO7816 transfer.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ *\r
+ * \return The number of errors that occurred.\r
+ */\r
+uint8_t usart_get_error_number(Usart *p_usart)\r
+{\r
+ return (p_usart->US_NER & US_NER_NB_ERRORS_Msk);\r
+}\r
+\r
+#if (SAM3S || SAM4S || SAM3U || SAM3XA)\r
+/**\r
+ * \brief Configure the transmitter preamble length when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_len The transmitter preamble length, which should be 0 ~ 15.\r
+ */\r
+void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) |\r
+ US_MAN_TX_PL(uc_len);\r
+}\r
+\r
+/**\r
+ * \brief Configure the transmitter preamble pattern when the Manchester \r
+ * encode/decode is enabled, which should be 0 ~ 3.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_pattern 0 if the preamble is composed of '1's;\r
+ * 1 if the preamble is composed of '0's;\r
+ * 2 if the preamble is composed of '01's;\r
+ * 3 if the preamble is composed of '10's.\r
+ */\r
+void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) |\r
+ (uc_pattern << US_MAN_TX_PP_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Configure the transmitter Manchester polarity when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_polarity Indicate the transmitter Manchester polarity, which \r
+ * should be 0 or 1.\r
+ */\r
+void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) |\r
+ (uc_polarity << 12);\r
+}\r
+\r
+/**\r
+ * \brief Configure the detected receiver preamble length when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_len The detected receiver preamble length, which should be 0 ~ 15.\r
+ */\r
+void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) |\r
+ US_MAN_RX_PL(uc_len);\r
+}\r
+\r
+/**\r
+ * \brief Configure the detected receiver preamble pattern when the Manchester \r
+ * encode/decode is enabled, which should be 0 ~ 3.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_pattern 0 if the preamble is composed of '1's;\r
+ * 1 if the preamble is composed of '0's;\r
+ * 2 if the preamble is composed of '01's;\r
+ * 3 if the preamble is composed of '10's.\r
+ */\r
+void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) |\r
+ (uc_pattern << US_MAN_RX_PP_Pos);\r
+}\r
+\r
+/**\r
+ * \brief Configure the receiver Manchester polarity when the Manchester \r
+ * encode/decode is enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ * \param uc_polarity Indicate the receiver Manchester polarity, which should \r
+ * be 0 or 1.\r
+ */\r
+void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity)\r
+{\r
+ p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) |\r
+ (uc_polarity << 28);\r
+}\r
+\r
+/**\r
+ * \brief Enable drift compensation.\r
+ *\r
+ * \note The 16X clock mode must be enabled.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_man_enable_drift_compensation(Usart *p_usart)\r
+{\r
+ p_usart->US_MAN |= US_MAN_DRIFT;\r
+}\r
+\r
+/**\r
+ * \brief Disable drift compensation.\r
+ *\r
+ * \param p_usart Pointer to a USART instance.\r
+ */\r
+void usart_man_disable_drift_compensation(Usart *p_usart)\r
+{\r
+ p_usart->US_MAN &= ~US_MAN_DRIFT;\r
+}\r
+#endif\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef USART_H_INCLUDED\r
+#define USART_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/**\r
+ * \defgroup usart_group Universal Synchronous Asynchronous Receiver Transmitter (USART)\r
+ *\r
+ * See \ref sam_usart_quickstart.\r
+ *\r
+ * This is a low-level driver implementation for the SAM Universal\r
+ * Synchronous/Asynchronous Receiver/Transmitter.\r
+ *\r
+ * @{\r
+ */\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/** Clock phase. */\r
+#define SPI_CPHA (1 << 0)\r
+\r
+/** Clock polarity. */\r
+#define SPI_CPOL (1 << 1)\r
+\r
+/** SPI mode definition. */\r
+#define SPI_MODE_0 (SPI_CPHA)\r
+#define SPI_MODE_1 0\r
+#define SPI_MODE_2 (SPI_CPOL | SPI_CPHA)\r
+#define SPI_MODE_3 (SPI_CPOL)\r
+\r
+//! Input parameters when initializing RS232 and similar modes.\r
+typedef struct {\r
+ //! Set baud rate of the USART (unused in slave modes).\r
+ uint32_t baudrate;\r
+ \r
+ //! Number of bits, which should be one of the following: US_MR_CHRL_5_BIT,\r
+ //! US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or US_MR_MODE9.\r
+ uint32_t char_length;\r
+ \r
+ //! Parity type, which should be one of the following: US_MR_PAR_EVEN, US_MR_PAR_ODD,\r
+ //! US_MR_PAR_SPACE, US_MR_PAR_MARK, US_MR_PAR_NO or US_MR_PAR_MULTIDROP.\r
+ uint32_t parity_type;\r
+\r
+ //! Number of stop bits between two characters: US_MR_NBSTOP_1_BIT,\r
+ //! US_MR_NBSTOP_1_5_BIT, US_MR_NBSTOP_2_BIT.\r
+ //! \note US_MR_NBSTOP_1_5_BIT is supported in asynchronous modes only.\r
+ uint32_t stop_bits;\r
+\r
+ //! Run the channel in test mode, which should be one of following: US_MR_CHMODE_NORMAL,\r
+ //! US_MR_CHMODE_AUTOMATIC, US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK\r
+ uint32_t channel_mode;\r
+\r
+ //! Filter of IrDA mode, useless in other modes. \r
+ uint32_t irda_filter;\r
+} sam_usart_opt_t;\r
+\r
+//! Input parameters when initializing ISO7816 mode.\r
+typedef struct {\r
+ //! Set the frequency of the ISO7816 clock.\r
+ uint32_t iso7816_hz;\r
+ \r
+ //! The number of ISO7816 clock ticks in every bit period (1 to 2047, 0 = disable clock).\r
+ //! Baudrate rate = iso7816_hz / fidi_ratio\r
+ uint32_t fidi_ratio;\r
+\r
+ //! How to calculate the parity bit: US_MR_PAR_EVEN for normal mode or\r
+ //! US_MR_PAR_ODD for inverse mode.\r
+ uint32_t parity_type;\r
+\r
+ //! Inhibit Non Acknowledge:\r
+ //! - 0: the NACK is generated;\r
+ //! - 1: the NACK is not generated.\r
+ //!\r
+ //! \note This bit will be used only in ISO7816 mode, protocol T = 0 receiver.\r
+ uint32_t inhibit_nack;\r
+\r
+ //! Disable successive NACKs.\r
+ //! - 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character.\r
+ //! Successive parity errors are counted up to the value in the max_iterations field.\r
+ //! These parity errors generate a NACK on the ISO line. As soon as this value is reached,\r
+ //! No additional NACK is sent on the ISO line. The ITERATION flag is asserted.\r
+ uint32_t dis_suc_nack;\r
+\r
+ //! Max number of repetitions (0 to 7).\r
+ uint32_t max_iterations;\r
+\r
+ //! Bit order in transmitted characters:\r
+ //! - 0: LSB first;\r
+ //! - 1: MSB first.\r
+ uint32_t bit_order;\r
+ \r
+ //! Which protocol is used:\r
+ //! - 0: T = 0;\r
+ //! - 1: T = 1.\r
+ uint32_t protocol_type;\r
+} usart_iso7816_opt_t;\r
+\r
+//! Input parameters when initializing SPI mode.\r
+typedef struct {\r
+ //! Set the frequency of the SPI clock (unused in slave mode).\r
+ uint32_t baudrate;\r
+\r
+ //! Number of bits, which should be one of the following: US_MR_CHRL_5_BIT,\r
+ //! US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or US_MR_MODE9.\r
+ uint32_t char_length;\r
+\r
+ //! Which SPI mode to use, which should be one of the following:\r
+ //! SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3.\r
+ uint32_t spi_mode;\r
+\r
+ //! Run the channel in test mode, which should be one of following: US_MR_CHMODE_NORMAL,\r
+ //! US_MR_CHMODE_AUTOMATIC, US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK\r
+ uint32_t channel_mode;\r
+} usart_spi_opt_t;\r
+\r
+void usart_reset(Usart *p_usart);\r
+uint32_t usart_init_rs232(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_hw_handshaking(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+#if (SAM3S || SAM4S || SAM3U)\r
+uint32_t usart_init_modem(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+#endif\r
+uint32_t usart_init_sync_master(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_sync_slave(Usart *p_usart, const sam_usart_opt_t *p_usart_opt);\r
+uint32_t usart_init_rs485(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_irda(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_iso7816(Usart *p_usart, const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_spi_master(Usart *p_usart, const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_spi_slave(Usart *p_usart, const usart_spi_opt_t *p_usart_opt);\r
+#if SAM3XA\r
+uint32_t usart_init_lin_master(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+uint32_t usart_init_lin_slave(Usart *p_usart, const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);\r
+void usart_lin_abort_tx(Usart *p_usart);\r
+void usart_lin_send_wakeup_signal(Usart *p_usart);\r
+void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action);\r
+void usart_lin_disable_parity(Usart *p_usart);\r
+void usart_lin_enable_parity(Usart *p_usart);\r
+void usart_lin_disable_checksum(Usart *p_usart);\r
+void usart_lin_enable_checksum(Usart *p_usart);\r
+void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type);\r
+void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode);\r
+void usart_lin_disable_frame_slot(Usart *p_usart);\r
+void usart_lin_enable_frame_slot(Usart *p_usart);\r
+void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type);\r
+void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len);\r
+void usart_lin_disable_pdc_mode(Usart *p_usart);\r
+void usart_lin_enable_pdc_mode(Usart *p_usart);\r
+void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id);\r
+uint8_t usart_lin_read_identifier(Usart *p_usart);\r
+#endif\r
+void usart_enable_tx(Usart *p_usart);\r
+void usart_disable_tx(Usart *p_usart);\r
+void usart_reset_tx(Usart *p_usart);\r
+void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard);\r
+void usart_enable_rx(Usart *p_usart);\r
+void usart_disable_rx(Usart *p_usart);\r
+void usart_reset_rx(Usart *p_usart);\r
+void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout);\r
+void usart_enable_interrupt(Usart *p_usart,uint32_t ul_sources);\r
+void usart_disable_interrupt(Usart *p_usart,uint32_t ul_sources);\r
+uint32_t usart_get_interrupt_mask(Usart *p_usart);\r
+uint32_t usart_get_status(Usart *p_usart);\r
+void usart_reset_status(Usart *p_usart);\r
+void usart_start_tx_break(Usart *p_usart);\r
+void usart_stop_tx_break(Usart *p_usart);\r
+void usart_start_rx_timeout(Usart *p_usart);\r
+uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr);\r
+void usart_reset_iterations(Usart *p_usart);\r
+void usart_reset_nack(Usart *p_usart);\r
+void usart_restart_rx_timeout(Usart *p_usart);\r
+#if (SAM3S || SAM4S || SAM3U)\r
+void usart_drive_DTR_pin_low(Usart *p_usart);\r
+void usart_drive_DTR_pin_high(Usart *p_usart);\r
+#endif\r
+void usart_drive_RTS_pin_low(Usart *p_usart);\r
+void usart_drive_RTS_pin_high(Usart *p_usart);\r
+void usart_spi_force_chip_select(Usart *p_usart);\r
+void usart_spi_release_chip_select(Usart *p_usart);\r
+uint32_t usart_is_tx_ready(Usart *p_usart);\r
+uint32_t usart_is_tx_empty(Usart *p_usart);\r
+uint32_t usart_is_rx_ready(Usart *p_usart);\r
+uint32_t usart_is_rx_buf_end(Usart *p_usart);\r
+uint32_t usart_is_tx_buf_end(Usart *p_usart);\r
+uint32_t usart_is_rx_buf_full(Usart *p_usart);\r
+uint32_t usart_is_tx_buf_empty(Usart *p_usart);\r
+uint32_t usart_write(Usart *p_usart, uint32_t c);\r
+uint32_t usart_putchar(Usart *p_usart, uint32_t c);\r
+void usart_write_line(Usart *p_usart, const char *string);\r
+uint32_t usart_read(Usart *p_usart, uint32_t *c);\r
+uint32_t usart_getchar(Usart *p_usart, uint32_t *c);\r
+#if (SAM3XA || SAM3U)\r
+uint32_t * usart_get_tx_access(Usart *p_usart);\r
+uint32_t * usart_get_rx_access(Usart *p_usart);\r
+#endif\r
+Pdc *usart_get_pdc_base(Usart *p_usart);\r
+void usart_enable_writeprotect(Usart *p_usart);\r
+void usart_disable_writeprotect(Usart *p_usart);\r
+uint32_t usart_get_writeprotect_status(Usart *p_usart);\r
+uint8_t usart_get_error_number(Usart *p_usart);\r
+#if (SAM3S || SAM4S || SAM3U || SAM3XA)\r
+void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len);\r
+void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern);\r
+void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity);\r
+void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len);\r
+void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern);\r
+void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity);\r
+void usart_man_enable_drift_compensation(Usart *p_usart);\r
+void usart_man_disable_drift_compensation(Usart *p_usart);\r
+#endif\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+//! @}\r
+\r
+/**\r
+ * \page sam_usart_quickstart Quick start guide for the SAM USART module\r
+ *\r
+ * This is the quick start guide for the \ref usart_group "USART module", with\r
+ * step-by-step instructions on how to configure and use the driver in a\r
+ * selection of use cases.\r
+ *\r
+ * The use cases contain several code fragments. The code fragments in the\r
+ * steps for setup can be copied into a custom initialization function, while\r
+ * the steps for usage can be copied into, e.g., the main application function.\r
+ *\r
+ * \note Some SAM devices contain both USART and UART modules, with the latter\r
+ * being a subset in functionality of the former but physically separate\r
+ * peripherals. UART modules are compatible with the USART driver, but\r
+ * only for the functions and modes supported by the base UART driver.\r
+ *\r
+ * \section usart_basic_use_case Basic use case\r
+ * \section usart_use_cases USART use cases\r
+ * - \ref usart_basic_use_case\r
+ * - \subpage usart_use_case_1\r
+ * - \subpage usart_use_case_2\r
+ *\r
+ * \section usart_basic_use_case Basic use case - transmit a character\r
+ * In this use case, the USART module is configured for:\r
+ * - Using USART0\r
+ * - Baudrate: 9600\r
+ * - Character length: 8 bit\r
+ * - Parity mode: Disabled\r
+ * - Stop bit: None\r
+ * - RS232 mode\r
+ *\r
+ * \section usart_basic_use_case_setup Setup steps\r
+ *\r
+ * \subsection usart_basic_use_case_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclock)"\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ * -# \ref pmc_group "Power Management Controller (pmc)"\r
+ *\r
+ * \subsection usart_basic_use_case_setup_code Example code\r
+ * The following configuration must be added to the project (typically to a \r
+ * conf_usart.h file, but it can also be added to your main application file.)\r
+ * \code\r
+ * #define USART_SERIAL USART0\r
+ * #define USART_SERIAL_ID ID_USART0\r
+ * #define USART_SERIAL_PIO PINS_USART_PIO\r
+ * #define USART_SERIAL_TYPE PINS_USART_TYPE\r
+ * #define USART_SERIAL_PINS PINS_USART_PINS\r
+ * #define USART_SERIAL_MASK PINS_USART_MASK\r
+ * #define USART_SERIAL_BAUDRATE 9600\r
+ * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT\r
+ * #define USART_SERIAL_PARITY US_MR_PAR_NO\r
+ * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT\r
+ * \endcode\r
+ *\r
+ * Add to application initialization:\r
+ * \code\r
+ * sysclk_init();\r
+ *\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_basic_use_case_setup_flow Workflow\r
+ * -# Initialize system clock:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ * -# Configure the USART Tx and Rx pins as Outputs and Inputs respectively:\r
+ * \code\r
+ * pio_configure(PINS_UART_PIO, PINS_UART_TYPE, PINS_UART_MASK,\r
+ * PINS_UART_ATTR);\r
+ * \endcode\r
+ * -# Create USART options struct:\r
+ * \code\r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \endcode\r
+ * -# Enable the clock to the USART module:\r
+ * \code\r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \endcode\r
+ * -# Initialize the USART module in RS232 mode:\r
+ * \code\r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * \endcode\r
+ * -# Enable the Rx and Tx modes of the USART module:\r
+ * \code\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \section usart_basic_use_case_usage Usage steps\r
+ *\r
+ * \subsection usart_basic_use_case_usage_code Example code\r
+ * Add to application C-file:\r
+ * \code\r
+ * usart_putchar(USART_SERIAL, 'a');\r
+ * \endcode\r
+ *\r
+ * \subsection usart_basic_use_case_usage_flow Workflow\r
+ * -# Send an 'a' character via USART\r
+ * \code usart_putchar(USART_SERIAL, 'a'); \endcode\r
+ */\r
+\r
+/**\r
+ * \page usart_use_case_1 USART receive character and echo back\r
+ *\r
+ * In this use case, the USART module is configured for:\r
+ * - Using USART0\r
+ * - Baudrate: 9600\r
+ * - Character length: 8 bit\r
+ * - Parity mode: Disabled\r
+ * - Stop bit: None\r
+ * - RS232 mode\r
+ *\r
+ * The use case waits for a received character on the configured USART and\r
+ * echoes the character back to the same USART.\r
+ *\r
+ * \section usart_use_case_1_setup Setup steps\r
+ *\r
+ * \subsection usart_use_case_1_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclock)"\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ * -# \ref pmc_group "Power Management Controller (pmc)"\r
+ *\r
+ * \subsection usart_use_case_1_setup_code Example code\r
+ * The following configuration must be added to the project (typically to a \r
+ * conf_usart.h file, but it can also be added to your main application file.):\r
+ * \code\r
+ * #define USART_SERIAL USART0\r
+ * #define USART_SERIAL_ID ID_USART0\r
+ * #define USART_SERIAL_PIO PINS_USART_PIO\r
+ * #define USART_SERIAL_TYPE PINS_USART_TYPE\r
+ * #define USART_SERIAL_PINS PINS_USART_PINS\r
+ * #define USART_SERIAL_MASK PINS_USART_MASK\r
+ * #define USART_SERIAL_BAUDRATE 9600\r
+ * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT\r
+ * #define USART_SERIAL_PARITY US_MR_PAR_NO\r
+ * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT\r
+ * \endcode\r
+ *\r
+ * A variable for the received byte must be added:\r
+ * \code\r
+ * uint32_t received_byte;\r
+ * \endcode\r
+ *\r
+ * Add to application initialization:\r
+ * \code\r
+ * sysclk_init();\r
+ *\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_1_setup_flow Workflow\r
+ * -# Initialize system clock:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ * -# Configure the USART Tx and Rx pins as Outputs and Inputs respectively:\r
+ * \code\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \endcode\r
+ * -# Create USART options struct:\r
+ * \code\r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \endcode\r
+ * -# Enable the clock to the USART module:\r
+ * \code pmc_enable_periph_clk(USART_SERIAL_ID); \endcode\r
+ * -# Initialize the USART module in RS232 mode:\r
+ * \code usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz()); \endcode\r
+ * -# Enable the Rx and Tx modes of the USART module:\r
+ * \code\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ *\r
+ * \section usart_use_case_1_usage Usage steps\r
+ *\r
+ * \subsection usart_use_case_1_usage_code Example code\r
+ * Add to, e.g., main loop in application C-file:\r
+ * \code\r
+ * received_byte = usart_getchar(USART_SERIAL);\r
+ * usart_putchar(USART_SERIAL, received_byte);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_1_usage_flow Workflow\r
+ * -# Wait for reception of a character:\r
+ * \code usart_getchar(USART_SERIAL, &received_byte); \endcode\r
+ * -# Echo the character back:\r
+ * \code usart_putchar(USART_SERIAL, received_byte); \endcode\r
+ */\r
+\r
+/**\r
+ * \page usart_use_case_2 USART receive character and echo back via interrupts\r
+ *\r
+ * In this use case, the USART module is configured for:\r
+ * - Using USART0\r
+ * - Baudrate: 9600\r
+ * - Character length: 8 bit\r
+ * - Parity mode: Disabled\r
+ * - Stop bit: None\r
+ * - RS232 mode\r
+ *\r
+ * The use case waits for a received character on the configured USART and\r
+ * echoes the character back to the same USART. The character reception is\r
+ * performed via an interrupt handler, rather than the polling method used\r
+ * in \ref usart_use_case_1.\r
+ *\r
+ * \section usart_use_case_2_setup Setup steps\r
+ *\r
+ * \subsection usart_use_case_2_setup_prereq Prerequisites\r
+ * -# \ref sysclk_group "System Clock Management (sysclock)"\r
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"\r
+ * -# \ref pmc_group "Power Management Controller (pmc)"\r
+ *\r
+ * \subsection usart_use_case_2_setup_code Example code\r
+ * The following configuration must be added to the project (typically to a \r
+ * conf_usart.h file, but it can also be added to your main application file.):\r
+ * \code\r
+ * #define USART_SERIAL USART0\r
+ * #define USART_SERIAL_ID ID_USART0\r
+ * #define USART_SERIAL_ISR_HANDLER USART0_Handler\r
+ * #define USART_SERIAL_PIO PINS_USART_PIO\r
+ * #define USART_SERIAL_TYPE PINS_USART_TYPE\r
+ * #define USART_SERIAL_PINS PINS_USART_PINS\r
+ * #define USART_SERIAL_MASK PINS_USART_MASK\r
+ * #define USART_SERIAL_BAUDRATE 9600\r
+ * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT\r
+ * #define USART_SERIAL_PARITY US_MR_PAR_NO\r
+ * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT\r
+ * \endcode\r
+ *\r
+ * A variable for the received byte must be added:\r
+ * \code\r
+ * uint32_t received_byte;\r
+ * \endcode\r
+ *\r
+ * Add to application initialization:\r
+ * \code\r
+ * sysclk_init();\r
+ *\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \r
+ * pmc_enable_periph_clk(USART_SERIAL_ID);\r
+ * \r
+ * usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz());\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \r
+ * usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY);\r
+ * NVIC_EnableIRQ(USART_SERIAL_IRQ);\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_2_setup_flow Workflow\r
+ * -# Initialize system clock:\r
+ * \code\r
+ * sysclk_init();\r
+ * \endcode\r
+ * -# Configure the USART Tx and Rx pins as Outputs and Inputs respectively:\r
+ * \code\r
+ * pio_configure(USART_SERIAL_PIO, USART_SERIAL_TYPE,\r
+ * USART_SERIAL_MASK, USART_SERIAL_ATTR);\r
+ * \endcode\r
+ * -# Create USART options struct:\r
+ * \code\r
+ * const sam_usart_opt_t usart_console_settings = {\r
+ * USART_SERIAL_BAUDRATE,\r
+ * USART_SERIAL_CHAR_LENGTH,\r
+ * USART_SERIAL_PARITY,\r
+ * USART_SERIAL_STOP_BIT,\r
+ * US_MR_CHMODE_NORMAL\r
+ * };\r
+ * \endcode\r
+ * -# Enable the clock to the USART module:\r
+ * \code pmc_enable_periph_clk(USART_SERIAL_ID); \endcode\r
+ * -# Initialize the USART module in RS232 mode:\r
+ * \code usart_init_rs232(USART_SERIAL, &usart_console_settings, sysclk_get_main_hz()); \endcode\r
+ * -# Enable the Rx and Tx modes of the USART module:\r
+ * \code\r
+ * usart_enable_tx(USART_SERIAL);\r
+ * usart_enable_rx(USART_SERIAL);\r
+ * \endcode\r
+ * -# Enable the USART character reception interrupt, and general interrupts for the USART module.\r
+ * \code\r
+ * usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY);\r
+ * NVIC_EnableIRQ(USART_SERIAL_IRQ);\r
+ * \endcode\r
+ * \section usart_use_case_2_usage Usage steps\r
+ *\r
+ * \subsection usart_use_case_2_usage_code Example code\r
+ * Add to your main application C-file the USART interrupt handler:\r
+ * \code\r
+ * void USART_SERIAL_ISR_HANDLER(void)\r
+ * {\r
+ * uint32_t dw_status = usart_get_status(USART_SERIAL);\r
+ * \r
+ * if (dw_status & US_CSR_RXRDY) {\r
+ * uint32_t received_byte;\r
+ * \r
+ * usart_read(USART_SERIAL, &received_byte);\r
+ * usart_write(USART_SERIAL, received_byte);\r
+ * }\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection usart_use_case_2_usage_flow Workflow\r
+ * -# When the USART ISR fires, retrieve the USART module interrupt flags:\r
+ * \code uint32_t dw_status = usart_get_status(USART_SERIAL); \endcode\r
+ * -# Check if the USART Receive Character interrupt has fired:\r
+ * \code if (dw_status & US_CSR_RXRDY) \endcode\r
+ * -# If a character has been received, fetch it into a temporary variable:\r
+ * \code usart_read(USART_SERIAL, &received_byte); \endcode\r
+ * -# Echo the character back:\r
+ * \code usart_write(USART_SERIAL, received_byte); \endcode\r
+ */\r
+\r
+#endif /* USART_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_ADC_COMPONENT_\r
+#define _SAM3XA_ADC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_ADC Analog-to-digital Converter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Adc hardware registers */\r
+typedef struct {\r
+ WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */\r
+ RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */\r
+ RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */\r
+ RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */\r
+ WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */\r
+ WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */\r
+ RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */\r
+ RoReg Reserved1[1];\r
+ RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */\r
+ WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */\r
+ WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */\r
+ RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */\r
+ RoReg Reserved2[2];\r
+ RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */\r
+ RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */\r
+ RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */\r
+ RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */\r
+ RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */\r
+ RoReg ADC_CDR[16]; /**< \brief (Adc Offset: 0x50) Channel Data Register */\r
+ RoReg Reserved3[1];\r
+ RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */\r
+ RoReg Reserved4[19];\r
+ RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved5[5];\r
+ RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */\r
+ RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */\r
+ RoReg Reserved6[2];\r
+ RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */\r
+ RoReg Reserved7[2];\r
+ WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */\r
+ RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */\r
+} Adc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */\r
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */\r
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */\r
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */\r
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */\r
+#define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */\r
+#define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */\r
+#define ADC_MR_TRGSEL_Pos 1\r
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */\r
+#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External : ADCTRG */\r
+#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 0 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 1 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 2 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */\r
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */\r
+#define ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */\r
+#define ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */\r
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */\r
+#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */\r
+#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */\r
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */\r
+#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */\r
+#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */\r
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */\r
+#define ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */\r
+#define ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */\r
+#define ADC_MR_PRESCAL_Pos 8\r
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */\r
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))\r
+#define ADC_MR_STARTUP_Pos 16\r
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */\r
+#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */\r
+#define ADC_MR_SETTLING_Pos 20\r
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */\r
+#define ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */\r
+#define ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */\r
+#define ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */\r
+#define ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */\r
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */\r
+#define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */\r
+#define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */\r
+#define ADC_MR_TRACKTIM_Pos 24\r
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */\r
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))\r
+#define ADC_MR_TRANSFER_Pos 28\r
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */\r
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))\r
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */\r
+#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */\r
+#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */\r
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */\r
+#define ADC_SEQR1_USCH1_Pos 0\r
+#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */\r
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))\r
+#define ADC_SEQR1_USCH2_Pos 4\r
+#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */\r
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))\r
+#define ADC_SEQR1_USCH3_Pos 8\r
+#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */\r
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))\r
+#define ADC_SEQR1_USCH4_Pos 12\r
+#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */\r
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))\r
+#define ADC_SEQR1_USCH5_Pos 16\r
+#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */\r
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))\r
+#define ADC_SEQR1_USCH6_Pos 20\r
+#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */\r
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))\r
+#define ADC_SEQR1_USCH7_Pos 24\r
+#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */\r
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))\r
+#define ADC_SEQR1_USCH8_Pos 28\r
+#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */\r
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))\r
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */\r
+#define ADC_SEQR2_USCH9_Pos 0\r
+#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */\r
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))\r
+#define ADC_SEQR2_USCH10_Pos 4\r
+#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */\r
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))\r
+#define ADC_SEQR2_USCH11_Pos 8\r
+#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */\r
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))\r
+#define ADC_SEQR2_USCH12_Pos 12\r
+#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */\r
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))\r
+#define ADC_SEQR2_USCH13_Pos 16\r
+#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */\r
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))\r
+#define ADC_SEQR2_USCH14_Pos 20\r
+#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */\r
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))\r
+#define ADC_SEQR2_USCH15_Pos 24\r
+#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */\r
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))\r
+#define ADC_SEQR2_USCH16_Pos 28\r
+#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */\r
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))\r
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */\r
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */\r
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */\r
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */\r
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */\r
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */\r
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */\r
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */\r
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */\r
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */\r
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */\r
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */\r
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */\r
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */\r
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */\r
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */\r
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */\r
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */\r
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */\r
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */\r
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */\r
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */\r
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */\r
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */\r
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */\r
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */\r
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */\r
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */\r
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */\r
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */\r
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */\r
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */\r
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */\r
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */\r
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */\r
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */\r
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */\r
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */\r
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */\r
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */\r
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */\r
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */\r
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */\r
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */\r
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */\r
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */\r
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */\r
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */\r
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */\r
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */\r
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */\r
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */\r
+#define ADC_LCDR_LDATA_Pos 0\r
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */\r
+#define ADC_LCDR_CHNB_Pos 12\r
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */\r
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */\r
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */\r
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */\r
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */\r
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */\r
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */\r
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */\r
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */\r
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */\r
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */\r
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */\r
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */\r
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */\r
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */\r
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */\r
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */\r
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */\r
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */\r
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */\r
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */\r
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */\r
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */\r
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */\r
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */\r
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */\r
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */\r
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */\r
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */\r
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */\r
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */\r
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */\r
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */\r
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */\r
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */\r
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */\r
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */\r
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */\r
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */\r
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */\r
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */\r
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */\r
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */\r
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */\r
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */\r
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */\r
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */\r
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */\r
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */\r
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */\r
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */\r
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */\r
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */\r
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */\r
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */\r
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */\r
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */\r
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */\r
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */\r
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */\r
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */\r
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */\r
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */\r
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */\r
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */\r
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */\r
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */\r
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */\r
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */\r
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */\r
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */\r
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */\r
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */\r
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */\r
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */\r
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */\r
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */\r
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */\r
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */\r
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */\r
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */\r
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */\r
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */\r
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */\r
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */\r
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */\r
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */\r
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */\r
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */\r
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */\r
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */\r
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */\r
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */\r
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */\r
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */\r
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */\r
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */\r
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */\r
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */\r
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */\r
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */\r
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */\r
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */\r
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */\r
+#define ADC_EMR_CMPMODE_Pos 0\r
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */\r
+#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */\r
+#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */\r
+#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */\r
+#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */\r
+#define ADC_EMR_CMPSEL_Pos 4\r
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */\r
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))\r
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */\r
+#define ADC_EMR_CMPFILTER_Pos 12\r
+#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */\r
+#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))\r
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */\r
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */\r
+#define ADC_CWR_LOWTHRES_Pos 0\r
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */\r
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))\r
+#define ADC_CWR_HIGHTHRES_Pos 16\r
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */\r
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))\r
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */\r
+#define ADC_CGR_GAIN0_Pos 0\r
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */\r
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))\r
+#define ADC_CGR_GAIN1_Pos 2\r
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */\r
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))\r
+#define ADC_CGR_GAIN2_Pos 4\r
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */\r
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))\r
+#define ADC_CGR_GAIN3_Pos 6\r
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */\r
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))\r
+#define ADC_CGR_GAIN4_Pos 8\r
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */\r
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))\r
+#define ADC_CGR_GAIN5_Pos 10\r
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */\r
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))\r
+#define ADC_CGR_GAIN6_Pos 12\r
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */\r
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))\r
+#define ADC_CGR_GAIN7_Pos 14\r
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */\r
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))\r
+#define ADC_CGR_GAIN8_Pos 16\r
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */\r
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))\r
+#define ADC_CGR_GAIN9_Pos 18\r
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */\r
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))\r
+#define ADC_CGR_GAIN10_Pos 20\r
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */\r
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))\r
+#define ADC_CGR_GAIN11_Pos 22\r
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */\r
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))\r
+#define ADC_CGR_GAIN12_Pos 24\r
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */\r
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))\r
+#define ADC_CGR_GAIN13_Pos 26\r
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */\r
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))\r
+#define ADC_CGR_GAIN14_Pos 28\r
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */\r
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))\r
+#define ADC_CGR_GAIN15_Pos 30\r
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */\r
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))\r
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */\r
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */\r
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */\r
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */\r
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */\r
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */\r
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */\r
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */\r
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */\r
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */\r
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */\r
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */\r
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */\r
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */\r
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */\r
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */\r
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */\r
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */\r
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */\r
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */\r
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */\r
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */\r
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */\r
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */\r
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */\r
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */\r
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */\r
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */\r
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */\r
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */\r
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */\r
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */\r
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */\r
+/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */\r
+#define ADC_CDR_DATA_Pos 0\r
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */\r
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */\r
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */\r
+#define ADC_ACR_IBCTL_Pos 8\r
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */\r
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))\r
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */\r
+#define ADC_WPMR_WPKEY_Pos 8\r
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */\r
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))\r
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */\r
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */\r
+#define ADC_WPSR_WPVSRC_Pos 8\r
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */\r
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */\r
+#define ADC_RPR_RXPTR_Pos 0\r
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */\r
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))\r
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */\r
+#define ADC_RCR_RXCTR_Pos 0\r
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */\r
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))\r
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define ADC_RNPR_RXNPTR_Pos 0\r
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */\r
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))\r
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */\r
+#define ADC_RNCR_RXNCTR_Pos 0\r
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */\r
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))\r
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */\r
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */\r
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */\r
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */\r
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */\r
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */\r
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */\r
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_ADC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_CAN_COMPONENT_\r
+#define _SAM3XA_CAN_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Controller Area Network */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_CAN Controller Area Network */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief CanMb hardware registers */\r
+typedef struct {\r
+ RwReg CAN_MMR; /**< \brief (CanMb Offset: 0x0) Mailbox Mode Register */\r
+ RwReg CAN_MAM; /**< \brief (CanMb Offset: 0x4) Mailbox Acceptance Mask Register */\r
+ RwReg CAN_MID; /**< \brief (CanMb Offset: 0x8) Mailbox ID Register */\r
+ RwReg CAN_MFID; /**< \brief (CanMb Offset: 0xC) Mailbox Family ID Register */\r
+ RwReg CAN_MSR; /**< \brief (CanMb Offset: 0x10) Mailbox Status Register */\r
+ RwReg CAN_MDL; /**< \brief (CanMb Offset: 0x14) Mailbox Data Low Register */\r
+ RwReg CAN_MDH; /**< \brief (CanMb Offset: 0x18) Mailbox Data High Register */\r
+ RwReg CAN_MCR; /**< \brief (CanMb Offset: 0x1C) Mailbox Control Register */\r
+} CanMb;\r
+/** \brief Can hardware registers */\r
+#define CANMB_NUMBER 8\r
+typedef struct {\r
+ RwReg CAN_MR; /**< \brief (Can Offset: 0x0000) Mode Register */\r
+ WoReg CAN_IER; /**< \brief (Can Offset: 0x0004) Interrupt Enable Register */\r
+ WoReg CAN_IDR; /**< \brief (Can Offset: 0x0008) Interrupt Disable Register */\r
+ RoReg CAN_IMR; /**< \brief (Can Offset: 0x000C) Interrupt Mask Register */\r
+ RoReg CAN_SR; /**< \brief (Can Offset: 0x0010) Status Register */\r
+ RwReg CAN_BR; /**< \brief (Can Offset: 0x0014) Baudrate Register */\r
+ RoReg CAN_TIM; /**< \brief (Can Offset: 0x0018) Timer Register */\r
+ RoReg CAN_TIMESTP; /**< \brief (Can Offset: 0x001C) Timestamp Register */\r
+ RoReg CAN_ECR; /**< \brief (Can Offset: 0x0020) Error Counter Register */\r
+ WoReg CAN_TCR; /**< \brief (Can Offset: 0x0024) Transfer Command Register */\r
+ WoReg CAN_ACR; /**< \brief (Can Offset: 0x0028) Abort Command Register */\r
+ RoReg Reserved1[46];\r
+ RwReg CAN_WPMR; /**< \brief (Can Offset: 0x00E4) Write Protect Mode Register */\r
+ RoReg CAN_WPSR; /**< \brief (Can Offset: 0x00E8) Write Protect Status Register */\r
+ RoReg Reserved2[69];\r
+ CanMb CAN_MB[CANMB_NUMBER]; /**< \brief (Can Offset: 0x200) MB = 0 .. 7 */\r
+} Can;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CAN_MR : (CAN Offset: 0x0000) Mode Register -------- */\r
+#define CAN_MR_CANEN (0x1u << 0) /**< \brief (CAN_MR) CAN Controller Enable */\r
+#define CAN_MR_LPM (0x1u << 1) /**< \brief (CAN_MR) Disable/Enable Low Power Mode */\r
+#define CAN_MR_ABM (0x1u << 2) /**< \brief (CAN_MR) Disable/Enable Autobaud/Listen mode */\r
+#define CAN_MR_OVL (0x1u << 3) /**< \brief (CAN_MR) Disable/Enable Overload Frame */\r
+#define CAN_MR_TEOF (0x1u << 4) /**< \brief (CAN_MR) Timestamp messages at each end of Frame */\r
+#define CAN_MR_TTM (0x1u << 5) /**< \brief (CAN_MR) Disable/Enable Time Triggered Mode */\r
+#define CAN_MR_TIMFRZ (0x1u << 6) /**< \brief (CAN_MR) Enable Timer Freeze */\r
+#define CAN_MR_DRPT (0x1u << 7) /**< \brief (CAN_MR) Disable Repeat */\r
+#define CAN_MR_RXSYNC_Pos 24\r
+#define CAN_MR_RXSYNC_Msk (0x7u << CAN_MR_RXSYNC_Pos) /**< \brief (CAN_MR) Reception Synchronization Stage (not readable) */\r
+#define CAN_MR_RXSYNC_DOUBLE_PP (0x0u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (2 Positive Edges) */\r
+#define CAN_MR_RXSYNC_DOUBLE_PN (0x1u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge) */\r
+#define CAN_MR_RXSYNC_SINGLE_P (0x2u << 24) /**< \brief (CAN_MR) Rx Signal with Single Synchro Stage (Positive Edge) */\r
+#define CAN_MR_RXSYNC_NONE (0x3u << 24) /**< \brief (CAN_MR) Rx Signal with No Synchro Stage */\r
+/* -------- CAN_IER : (CAN Offset: 0x0004) Interrupt Enable Register -------- */\r
+#define CAN_IER_MB0 (0x1u << 0) /**< \brief (CAN_IER) Mailbox 0 Interrupt Enable */\r
+#define CAN_IER_MB1 (0x1u << 1) /**< \brief (CAN_IER) Mailbox 1 Interrupt Enable */\r
+#define CAN_IER_MB2 (0x1u << 2) /**< \brief (CAN_IER) Mailbox 2 Interrupt Enable */\r
+#define CAN_IER_MB3 (0x1u << 3) /**< \brief (CAN_IER) Mailbox 3 Interrupt Enable */\r
+#define CAN_IER_MB4 (0x1u << 4) /**< \brief (CAN_IER) Mailbox 4 Interrupt Enable */\r
+#define CAN_IER_MB5 (0x1u << 5) /**< \brief (CAN_IER) Mailbox 5 Interrupt Enable */\r
+#define CAN_IER_MB6 (0x1u << 6) /**< \brief (CAN_IER) Mailbox 6 Interrupt Enable */\r
+#define CAN_IER_MB7 (0x1u << 7) /**< \brief (CAN_IER) Mailbox 7 Interrupt Enable */\r
+#define CAN_IER_ERRA (0x1u << 16) /**< \brief (CAN_IER) Error Active Mode Interrupt Enable */\r
+#define CAN_IER_WARN (0x1u << 17) /**< \brief (CAN_IER) Warning Limit Interrupt Enable */\r
+#define CAN_IER_ERRP (0x1u << 18) /**< \brief (CAN_IER) Error Passive Mode Interrupt Enable */\r
+#define CAN_IER_BOFF (0x1u << 19) /**< \brief (CAN_IER) Bus Off Mode Interrupt Enable */\r
+#define CAN_IER_SLEEP (0x1u << 20) /**< \brief (CAN_IER) Sleep Interrupt Enable */\r
+#define CAN_IER_WAKEUP (0x1u << 21) /**< \brief (CAN_IER) Wakeup Interrupt Enable */\r
+#define CAN_IER_TOVF (0x1u << 22) /**< \brief (CAN_IER) Timer Overflow Interrupt Enable */\r
+#define CAN_IER_TSTP (0x1u << 23) /**< \brief (CAN_IER) TimeStamp Interrupt Enable */\r
+#define CAN_IER_CERR (0x1u << 24) /**< \brief (CAN_IER) CRC Error Interrupt Enable */\r
+#define CAN_IER_SERR (0x1u << 25) /**< \brief (CAN_IER) Stuffing Error Interrupt Enable */\r
+#define CAN_IER_AERR (0x1u << 26) /**< \brief (CAN_IER) Acknowledgment Error Interrupt Enable */\r
+#define CAN_IER_FERR (0x1u << 27) /**< \brief (CAN_IER) Form Error Interrupt Enable */\r
+#define CAN_IER_BERR (0x1u << 28) /**< \brief (CAN_IER) Bit Error Interrupt Enable */\r
+/* -------- CAN_IDR : (CAN Offset: 0x0008) Interrupt Disable Register -------- */\r
+#define CAN_IDR_MB0 (0x1u << 0) /**< \brief (CAN_IDR) Mailbox 0 Interrupt Disable */\r
+#define CAN_IDR_MB1 (0x1u << 1) /**< \brief (CAN_IDR) Mailbox 1 Interrupt Disable */\r
+#define CAN_IDR_MB2 (0x1u << 2) /**< \brief (CAN_IDR) Mailbox 2 Interrupt Disable */\r
+#define CAN_IDR_MB3 (0x1u << 3) /**< \brief (CAN_IDR) Mailbox 3 Interrupt Disable */\r
+#define CAN_IDR_MB4 (0x1u << 4) /**< \brief (CAN_IDR) Mailbox 4 Interrupt Disable */\r
+#define CAN_IDR_MB5 (0x1u << 5) /**< \brief (CAN_IDR) Mailbox 5 Interrupt Disable */\r
+#define CAN_IDR_MB6 (0x1u << 6) /**< \brief (CAN_IDR) Mailbox 6 Interrupt Disable */\r
+#define CAN_IDR_MB7 (0x1u << 7) /**< \brief (CAN_IDR) Mailbox 7 Interrupt Disable */\r
+#define CAN_IDR_ERRA (0x1u << 16) /**< \brief (CAN_IDR) Error Active Mode Interrupt Disable */\r
+#define CAN_IDR_WARN (0x1u << 17) /**< \brief (CAN_IDR) Warning Limit Interrupt Disable */\r
+#define CAN_IDR_ERRP (0x1u << 18) /**< \brief (CAN_IDR) Error Passive Mode Interrupt Disable */\r
+#define CAN_IDR_BOFF (0x1u << 19) /**< \brief (CAN_IDR) Bus Off Mode Interrupt Disable */\r
+#define CAN_IDR_SLEEP (0x1u << 20) /**< \brief (CAN_IDR) Sleep Interrupt Disable */\r
+#define CAN_IDR_WAKEUP (0x1u << 21) /**< \brief (CAN_IDR) Wakeup Interrupt Disable */\r
+#define CAN_IDR_TOVF (0x1u << 22) /**< \brief (CAN_IDR) Timer Overflow Interrupt */\r
+#define CAN_IDR_TSTP (0x1u << 23) /**< \brief (CAN_IDR) TimeStamp Interrupt Disable */\r
+#define CAN_IDR_CERR (0x1u << 24) /**< \brief (CAN_IDR) CRC Error Interrupt Disable */\r
+#define CAN_IDR_SERR (0x1u << 25) /**< \brief (CAN_IDR) Stuffing Error Interrupt Disable */\r
+#define CAN_IDR_AERR (0x1u << 26) /**< \brief (CAN_IDR) Acknowledgment Error Interrupt Disable */\r
+#define CAN_IDR_FERR (0x1u << 27) /**< \brief (CAN_IDR) Form Error Interrupt Disable */\r
+#define CAN_IDR_BERR (0x1u << 28) /**< \brief (CAN_IDR) Bit Error Interrupt Disable */\r
+/* -------- CAN_IMR : (CAN Offset: 0x000C) Interrupt Mask Register -------- */\r
+#define CAN_IMR_MB0 (0x1u << 0) /**< \brief (CAN_IMR) Mailbox 0 Interrupt Mask */\r
+#define CAN_IMR_MB1 (0x1u << 1) /**< \brief (CAN_IMR) Mailbox 1 Interrupt Mask */\r
+#define CAN_IMR_MB2 (0x1u << 2) /**< \brief (CAN_IMR) Mailbox 2 Interrupt Mask */\r
+#define CAN_IMR_MB3 (0x1u << 3) /**< \brief (CAN_IMR) Mailbox 3 Interrupt Mask */\r
+#define CAN_IMR_MB4 (0x1u << 4) /**< \brief (CAN_IMR) Mailbox 4 Interrupt Mask */\r
+#define CAN_IMR_MB5 (0x1u << 5) /**< \brief (CAN_IMR) Mailbox 5 Interrupt Mask */\r
+#define CAN_IMR_MB6 (0x1u << 6) /**< \brief (CAN_IMR) Mailbox 6 Interrupt Mask */\r
+#define CAN_IMR_MB7 (0x1u << 7) /**< \brief (CAN_IMR) Mailbox 7 Interrupt Mask */\r
+#define CAN_IMR_ERRA (0x1u << 16) /**< \brief (CAN_IMR) Error Active Mode Interrupt Mask */\r
+#define CAN_IMR_WARN (0x1u << 17) /**< \brief (CAN_IMR) Warning Limit Interrupt Mask */\r
+#define CAN_IMR_ERRP (0x1u << 18) /**< \brief (CAN_IMR) Error Passive Mode Interrupt Mask */\r
+#define CAN_IMR_BOFF (0x1u << 19) /**< \brief (CAN_IMR) Bus Off Mode Interrupt Mask */\r
+#define CAN_IMR_SLEEP (0x1u << 20) /**< \brief (CAN_IMR) Sleep Interrupt Mask */\r
+#define CAN_IMR_WAKEUP (0x1u << 21) /**< \brief (CAN_IMR) Wakeup Interrupt Mask */\r
+#define CAN_IMR_TOVF (0x1u << 22) /**< \brief (CAN_IMR) Timer Overflow Interrupt Mask */\r
+#define CAN_IMR_TSTP (0x1u << 23) /**< \brief (CAN_IMR) Timestamp Interrupt Mask */\r
+#define CAN_IMR_CERR (0x1u << 24) /**< \brief (CAN_IMR) CRC Error Interrupt Mask */\r
+#define CAN_IMR_SERR (0x1u << 25) /**< \brief (CAN_IMR) Stuffing Error Interrupt Mask */\r
+#define CAN_IMR_AERR (0x1u << 26) /**< \brief (CAN_IMR) Acknowledgment Error Interrupt Mask */\r
+#define CAN_IMR_FERR (0x1u << 27) /**< \brief (CAN_IMR) Form Error Interrupt Mask */\r
+#define CAN_IMR_BERR (0x1u << 28) /**< \brief (CAN_IMR) Bit Error Interrupt Mask */\r
+/* -------- CAN_SR : (CAN Offset: 0x0010) Status Register -------- */\r
+#define CAN_SR_MB0 (0x1u << 0) /**< \brief (CAN_SR) Mailbox 0 Event */\r
+#define CAN_SR_MB1 (0x1u << 1) /**< \brief (CAN_SR) Mailbox 1 Event */\r
+#define CAN_SR_MB2 (0x1u << 2) /**< \brief (CAN_SR) Mailbox 2 Event */\r
+#define CAN_SR_MB3 (0x1u << 3) /**< \brief (CAN_SR) Mailbox 3 Event */\r
+#define CAN_SR_MB4 (0x1u << 4) /**< \brief (CAN_SR) Mailbox 4 Event */\r
+#define CAN_SR_MB5 (0x1u << 5) /**< \brief (CAN_SR) Mailbox 5 Event */\r
+#define CAN_SR_MB6 (0x1u << 6) /**< \brief (CAN_SR) Mailbox 6 Event */\r
+#define CAN_SR_MB7 (0x1u << 7) /**< \brief (CAN_SR) Mailbox 7 Event */\r
+#define CAN_SR_ERRA (0x1u << 16) /**< \brief (CAN_SR) Error Active Mode */\r
+#define CAN_SR_WARN (0x1u << 17) /**< \brief (CAN_SR) Warning Limit */\r
+#define CAN_SR_ERRP (0x1u << 18) /**< \brief (CAN_SR) Error Passive Mode */\r
+#define CAN_SR_BOFF (0x1u << 19) /**< \brief (CAN_SR) Bus Off Mode */\r
+#define CAN_SR_SLEEP (0x1u << 20) /**< \brief (CAN_SR) CAN controller in Low power Mode */\r
+#define CAN_SR_WAKEUP (0x1u << 21) /**< \brief (CAN_SR) CAN controller is not in Low power Mode */\r
+#define CAN_SR_TOVF (0x1u << 22) /**< \brief (CAN_SR) Timer Overflow */\r
+#define CAN_SR_TSTP (0x1u << 23) /**< \brief (CAN_SR) */\r
+#define CAN_SR_CERR (0x1u << 24) /**< \brief (CAN_SR) Mailbox CRC Error */\r
+#define CAN_SR_SERR (0x1u << 25) /**< \brief (CAN_SR) Mailbox Stuffing Error */\r
+#define CAN_SR_AERR (0x1u << 26) /**< \brief (CAN_SR) Acknowledgment Error */\r
+#define CAN_SR_FERR (0x1u << 27) /**< \brief (CAN_SR) Form Error */\r
+#define CAN_SR_BERR (0x1u << 28) /**< \brief (CAN_SR) Bit Error */\r
+#define CAN_SR_RBSY (0x1u << 29) /**< \brief (CAN_SR) Receiver busy */\r
+#define CAN_SR_TBSY (0x1u << 30) /**< \brief (CAN_SR) Transmitter busy */\r
+#define CAN_SR_OVLSY (0x1u << 31) /**< \brief (CAN_SR) Overload busy */\r
+/* -------- CAN_BR : (CAN Offset: 0x0014) Baudrate Register -------- */\r
+#define CAN_BR_PHASE2_Pos 0\r
+#define CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) /**< \brief (CAN_BR) Phase 2 segment */\r
+#define CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos)))\r
+#define CAN_BR_PHASE1_Pos 4\r
+#define CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) /**< \brief (CAN_BR) Phase 1 segment */\r
+#define CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos)))\r
+#define CAN_BR_PROPAG_Pos 8\r
+#define CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) /**< \brief (CAN_BR) Programming time segment */\r
+#define CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos)))\r
+#define CAN_BR_SJW_Pos 12\r
+#define CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) /**< \brief (CAN_BR) Re-synchronization jump width */\r
+#define CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos)))\r
+#define CAN_BR_BRP_Pos 16\r
+#define CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) /**< \brief (CAN_BR) Baudrate Prescaler. */\r
+#define CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos)))\r
+#define CAN_BR_SMP (0x1u << 24) /**< \brief (CAN_BR) Sampling Mode */\r
+#define CAN_BR_SMP_ONCE (0x0u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled once at sample point. */\r
+#define CAN_BR_SMP_THREE (0x1u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. */\r
+/* -------- CAN_TIM : (CAN Offset: 0x0018) Timer Register -------- */\r
+#define CAN_TIM_TIMER_Pos 0\r
+#define CAN_TIM_TIMER_Msk (0xffffu << CAN_TIM_TIMER_Pos) /**< \brief (CAN_TIM) Timer */\r
+/* -------- CAN_TIMESTP : (CAN Offset: 0x001C) Timestamp Register -------- */\r
+#define CAN_TIMESTP_MTIMESTAMP_Pos 0\r
+#define CAN_TIMESTP_MTIMESTAMP_Msk (0xffffu << CAN_TIMESTP_MTIMESTAMP_Pos) /**< \brief (CAN_TIMESTP) Timestamp */\r
+/* -------- CAN_ECR : (CAN Offset: 0x0020) Error Counter Register -------- */\r
+#define CAN_ECR_REC_Pos 0\r
+#define CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) /**< \brief (CAN_ECR) Receive Error Counter */\r
+#define CAN_ECR_TEC_Pos 16\r
+#define CAN_ECR_TEC_Msk (0xffu << CAN_ECR_TEC_Pos) /**< \brief (CAN_ECR) Transmit Error Counter */\r
+/* -------- CAN_TCR : (CAN Offset: 0x0024) Transfer Command Register -------- */\r
+#define CAN_TCR_MB0 (0x1u << 0) /**< \brief (CAN_TCR) Transfer Request for Mailbox 0 */\r
+#define CAN_TCR_MB1 (0x1u << 1) /**< \brief (CAN_TCR) Transfer Request for Mailbox 1 */\r
+#define CAN_TCR_MB2 (0x1u << 2) /**< \brief (CAN_TCR) Transfer Request for Mailbox 2 */\r
+#define CAN_TCR_MB3 (0x1u << 3) /**< \brief (CAN_TCR) Transfer Request for Mailbox 3 */\r
+#define CAN_TCR_MB4 (0x1u << 4) /**< \brief (CAN_TCR) Transfer Request for Mailbox 4 */\r
+#define CAN_TCR_MB5 (0x1u << 5) /**< \brief (CAN_TCR) Transfer Request for Mailbox 5 */\r
+#define CAN_TCR_MB6 (0x1u << 6) /**< \brief (CAN_TCR) Transfer Request for Mailbox 6 */\r
+#define CAN_TCR_MB7 (0x1u << 7) /**< \brief (CAN_TCR) Transfer Request for Mailbox 7 */\r
+#define CAN_TCR_TIMRST (0x1u << 31) /**< \brief (CAN_TCR) Timer Reset */\r
+/* -------- CAN_ACR : (CAN Offset: 0x0028) Abort Command Register -------- */\r
+#define CAN_ACR_MB0 (0x1u << 0) /**< \brief (CAN_ACR) Abort Request for Mailbox 0 */\r
+#define CAN_ACR_MB1 (0x1u << 1) /**< \brief (CAN_ACR) Abort Request for Mailbox 1 */\r
+#define CAN_ACR_MB2 (0x1u << 2) /**< \brief (CAN_ACR) Abort Request for Mailbox 2 */\r
+#define CAN_ACR_MB3 (0x1u << 3) /**< \brief (CAN_ACR) Abort Request for Mailbox 3 */\r
+#define CAN_ACR_MB4 (0x1u << 4) /**< \brief (CAN_ACR) Abort Request for Mailbox 4 */\r
+#define CAN_ACR_MB5 (0x1u << 5) /**< \brief (CAN_ACR) Abort Request for Mailbox 5 */\r
+#define CAN_ACR_MB6 (0x1u << 6) /**< \brief (CAN_ACR) Abort Request for Mailbox 6 */\r
+#define CAN_ACR_MB7 (0x1u << 7) /**< \brief (CAN_ACR) Abort Request for Mailbox 7 */\r
+/* -------- CAN_WPMR : (CAN Offset: 0x00E4) Write Protect Mode Register -------- */\r
+#define CAN_WPMR_WPEN (0x1u << 0) /**< \brief (CAN_WPMR) Write Protection Enable */\r
+#define CAN_WPMR_WPKEY_Pos 8\r
+#define CAN_WPMR_WPKEY_Msk (0xffffffu << CAN_WPMR_WPKEY_Pos) /**< \brief (CAN_WPMR) SPI Write Protection Key Password */\r
+#define CAN_WPMR_WPKEY(value) ((CAN_WPMR_WPKEY_Msk & ((value) << CAN_WPMR_WPKEY_Pos)))\r
+/* -------- CAN_WPSR : (CAN Offset: 0x00E8) Write Protect Status Register -------- */\r
+#define CAN_WPSR_WPVS (0x1u << 0) /**< \brief (CAN_WPSR) Write Protection Violation Status */\r
+#define CAN_WPSR_WPVSRC_Pos 8\r
+#define CAN_WPSR_WPVSRC_Msk (0xffu << CAN_WPSR_WPVSRC_Pos) /**< \brief (CAN_WPSR) Write Protection Violation Source */\r
+/* -------- CAN_MMR : (CAN Offset: N/A) Mailbox Mode Register -------- */\r
+#define CAN_MMR_MTIMEMARK_Pos 0\r
+#define CAN_MMR_MTIMEMARK_Msk (0xffffu << CAN_MMR_MTIMEMARK_Pos) /**< \brief (CAN_MMR) Mailbox Timemark */\r
+#define CAN_MMR_MTIMEMARK(value) ((CAN_MMR_MTIMEMARK_Msk & ((value) << CAN_MMR_MTIMEMARK_Pos)))\r
+#define CAN_MMR_PRIOR_Pos 16\r
+#define CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) /**< \brief (CAN_MMR) Mailbox Priority */\r
+#define CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos)))\r
+#define CAN_MMR_MOT_Pos 24\r
+#define CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) /**< \brief (CAN_MMR) Mailbox Object Type */\r
+#define CAN_MMR_MOT_MB_DISABLED (0x0u << 24) /**< \brief (CAN_MMR) Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. */\r
+#define CAN_MMR_MOT_MB_RX (0x1u << 24) /**< \brief (CAN_MMR) Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. */\r
+#define CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) /**< \brief (CAN_MMR) Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. */\r
+#define CAN_MMR_MOT_MB_TX (0x3u << 24) /**< \brief (CAN_MMR) Transmit mailbox. Mailbox is configured for transmission. */\r
+#define CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) /**< \brief (CAN_MMR) Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. */\r
+#define CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) /**< \brief (CAN_MMR) Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. */\r
+/* -------- CAN_MAM : (CAN Offset: N/A) Mailbox Acceptance Mask Register -------- */\r
+#define CAN_MAM_MIDvB_Pos 0\r
+#define CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) /**< \brief (CAN_MAM) Complementary bits for identifier in extended frame mode */\r
+#define CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos)))\r
+#define CAN_MAM_MIDvA_Pos 18\r
+#define CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) /**< \brief (CAN_MAM) Identifier for standard frame mode */\r
+#define CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos)))\r
+#define CAN_MAM_MIDE (0x1u << 29) /**< \brief (CAN_MAM) Identifier Version */\r
+/* -------- CAN_MID : (CAN Offset: N/A) Mailbox ID Register -------- */\r
+#define CAN_MID_MIDvB_Pos 0\r
+#define CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) /**< \brief (CAN_MID) Complementary bits for identifier in extended frame mode */\r
+#define CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos)))\r
+#define CAN_MID_MIDvA_Pos 18\r
+#define CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) /**< \brief (CAN_MID) Identifier for standard frame mode */\r
+#define CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos)))\r
+#define CAN_MID_MIDE (0x1u << 29) /**< \brief (CAN_MID) Identifier Version */\r
+/* -------- CAN_MFID : (CAN Offset: N/A) Mailbox Family ID Register -------- */\r
+#define CAN_MFID_MFID_Pos 0\r
+#define CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) /**< \brief (CAN_MFID) Family ID */\r
+/* -------- CAN_MSR : (CAN Offset: N/A) Mailbox Status Register -------- */\r
+#define CAN_MSR_MTIMESTAMP_Pos 0\r
+#define CAN_MSR_MTIMESTAMP_Msk (0xffffu << CAN_MSR_MTIMESTAMP_Pos) /**< \brief (CAN_MSR) Timer value */\r
+#define CAN_MSR_MDLC_Pos 16\r
+#define CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) /**< \brief (CAN_MSR) Mailbox Data Length Code */\r
+#define CAN_MSR_MRTR (0x1u << 20) /**< \brief (CAN_MSR) Mailbox Remote Transmission Request */\r
+#define CAN_MSR_MABT (0x1u << 22) /**< \brief (CAN_MSR) Mailbox Message Abort */\r
+#define CAN_MSR_MRDY (0x1u << 23) /**< \brief (CAN_MSR) Mailbox Ready */\r
+#define CAN_MSR_MMI (0x1u << 24) /**< \brief (CAN_MSR) Mailbox Message Ignored */\r
+/* -------- CAN_MDL : (CAN Offset: N/A) Mailbox Data Low Register -------- */\r
+#define CAN_MDL_MDL_Pos 0\r
+#define CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) /**< \brief (CAN_MDL) Message Data Low Value */\r
+#define CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos)))\r
+/* -------- CAN_MDH : (CAN Offset: N/A) Mailbox Data High Register -------- */\r
+#define CAN_MDH_MDH_Pos 0\r
+#define CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) /**< \brief (CAN_MDH) Message Data High Value */\r
+#define CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos)))\r
+/* -------- CAN_MCR : (CAN Offset: N/A) Mailbox Control Register -------- */\r
+#define CAN_MCR_MDLC_Pos 16\r
+#define CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) /**< \brief (CAN_MCR) Mailbox Data Length Code */\r
+#define CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos)))\r
+#define CAN_MCR_MRTR (0x1u << 20) /**< \brief (CAN_MCR) Mailbox Remote Transmission Request */\r
+#define CAN_MCR_MACR (0x1u << 22) /**< \brief (CAN_MCR) Abort Request for Mailbox x */\r
+#define CAN_MCR_MTCR (0x1u << 23) /**< \brief (CAN_MCR) Mailbox Transfer Command */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_CAN_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_CHIPID_COMPONENT_\r
+#define _SAM3XA_CHIPID_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Chip Identifier */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_CHIPID Chip Identifier */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Chipid hardware registers */\r
+typedef struct {\r
+ RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */\r
+ RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */\r
+} Chipid;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */\r
+#define CHIPID_CIDR_VERSION_Pos 0\r
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */\r
+#define CHIPID_CIDR_EPROC_Pos 5\r
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */\r
+#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */\r
+#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */\r
+#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */\r
+#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */\r
+#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */\r
+#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */\r
+#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */\r
+#define CHIPID_CIDR_NVPSIZ_Pos 8\r
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */\r
+#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_Pos 12\r
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */\r
+#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_Pos 16\r
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */\r
+#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */\r
+#define CHIPID_CIDR_ARCH_Pos 20\r
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */\r
+#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */\r
+#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */\r
+#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */\r
+#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */\r
+#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */\r
+#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */\r
+#define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */\r
+#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */\r
+#define CHIPID_CIDR_NVPTYP_Pos 28\r
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */\r
+#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */\r
+#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */\r
+#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */\r
+#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */\r
+#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */\r
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */\r
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */\r
+#define CHIPID_EXID_EXID_Pos 0\r
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_CHIPID_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_DACC_COMPONENT_\r
+#define _SAM3XA_DACC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_DACC Digital-to-Analog Converter Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Dacc hardware registers */\r
+typedef struct {\r
+ WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */\r
+ RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */\r
+ RoReg Reserved1[2];\r
+ WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */\r
+ WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */\r
+ RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */\r
+ RoReg Reserved2[1];\r
+ WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */\r
+ WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */\r
+ WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */\r
+ RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */\r
+ RoReg Reserved3[24];\r
+ RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */\r
+ RoReg Reserved4[19];\r
+ RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */\r
+ RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */\r
+ RoReg Reserved5[7];\r
+ RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */\r
+ RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */\r
+ RoReg Reserved6[2];\r
+ RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */\r
+ RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */\r
+} Dacc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */\r
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */\r
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */\r
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */\r
+#define DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */\r
+#define DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */\r
+#define DACC_MR_TRGSEL_Pos 1\r
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */\r
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))\r
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */\r
+#define DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */\r
+#define DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */\r
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */\r
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */\r
+#define DACC_MR_REFRESH_Pos 8\r
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */\r
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))\r
+#define DACC_MR_USER_SEL_Pos 16\r
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */\r
+#define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */\r
+#define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */\r
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */\r
+#define DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */\r
+#define DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */\r
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */\r
+#define DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal Mode */\r
+#define DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode enabled */\r
+#define DACC_MR_STARTUP_Pos 24\r
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */\r
+#define DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */\r
+#define DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */\r
+#define DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */\r
+#define DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */\r
+#define DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */\r
+#define DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */\r
+#define DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */\r
+#define DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */\r
+#define DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */\r
+#define DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */\r
+#define DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */\r
+#define DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */\r
+#define DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */\r
+#define DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */\r
+#define DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */\r
+#define DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */\r
+#define DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */\r
+#define DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */\r
+#define DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */\r
+#define DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */\r
+#define DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */\r
+#define DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */\r
+#define DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */\r
+#define DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */\r
+#define DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */\r
+#define DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */\r
+#define DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */\r
+#define DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */\r
+#define DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */\r
+#define DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */\r
+#define DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */\r
+#define DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */\r
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */\r
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */\r
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */\r
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */\r
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */\r
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */\r
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */\r
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */\r
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */\r
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */\r
+#define DACC_CDR_DATA_Pos 0\r
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */\r
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))\r
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */\r
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */\r
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */\r
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */\r
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */\r
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */\r
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */\r
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */\r
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */\r
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */\r
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */\r
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */\r
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */\r
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */\r
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */\r
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */\r
+#define DACC_ACR_IBCTLCH0_Pos 0\r
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */\r
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))\r
+#define DACC_ACR_IBCTLCH1_Pos 2\r
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */\r
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))\r
+#define DACC_ACR_IBCTLDACCORE_Pos 8\r
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */\r
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))\r
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */\r
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */\r
+#define DACC_WPMR_WPKEY_Pos 8\r
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */\r
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))\r
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */\r
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */\r
+#define DACC_WPSR_WPROTADDR_Pos 8\r
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */\r
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */\r
+#define DACC_TPR_TXPTR_Pos 0\r
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */\r
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))\r
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */\r
+#define DACC_TCR_TXCTR_Pos 0\r
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */\r
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))\r
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define DACC_TNPR_TXNPTR_Pos 0\r
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */\r
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))\r
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define DACC_TNCR_TXNCTR_Pos 0\r
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */\r
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))\r
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */\r
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */\r
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */\r
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */\r
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */\r
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */\r
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */\r
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_DACC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_DMAC_COMPONENT_\r
+#define _SAM3XA_DMAC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR DMA Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_DMAC DMA Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief DmacCh_num hardware registers */\r
+typedef struct {\r
+ RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */\r
+ RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */\r
+ RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */\r
+ RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */\r
+ RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */\r
+ RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */\r
+ RoReg Reserved1[4];\r
+} DmacCh_num;\r
+/** \brief Dmac hardware registers */\r
+#define DMACCH_NUM_NUMBER 6\r
+typedef struct {\r
+ RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */\r
+ RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */\r
+ RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */\r
+ RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */\r
+ RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */\r
+ RoReg Reserved1[1];\r
+ WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */\r
+ WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */\r
+ RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */\r
+ RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */\r
+ WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */\r
+ WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */\r
+ RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */\r
+ RoReg Reserved2[2];\r
+ DmacCh_num DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 5 */\r
+ RoReg Reserved3[46];\r
+ RwReg DMAC_WPMR; /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */\r
+ RoReg DMAC_WPSR; /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */\r
+} Dmac;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */\r
+#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */\r
+#define DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */\r
+#define DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */\r
+/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */\r
+#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN) */\r
+/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */\r
+#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */\r
+#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */\r
+#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */\r
+#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */\r
+#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */\r
+#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */\r
+#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */\r
+#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */\r
+#define DMAC_SREQ_SSREQ4 (0x1u << 8) /**< \brief (DMAC_SREQ) Source Request */\r
+#define DMAC_SREQ_DSREQ4 (0x1u << 9) /**< \brief (DMAC_SREQ) Destination Request */\r
+#define DMAC_SREQ_SSREQ5 (0x1u << 10) /**< \brief (DMAC_SREQ) Source Request */\r
+#define DMAC_SREQ_DSREQ5 (0x1u << 11) /**< \brief (DMAC_SREQ) Destination Request */\r
+/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */\r
+#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */\r
+#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */\r
+#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */\r
+#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */\r
+#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */\r
+#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */\r
+#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */\r
+#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */\r
+#define DMAC_CREQ_SCREQ4 (0x1u << 8) /**< \brief (DMAC_CREQ) Source Chunk Request */\r
+#define DMAC_CREQ_DCREQ4 (0x1u << 9) /**< \brief (DMAC_CREQ) Destination Chunk Request */\r
+#define DMAC_CREQ_SCREQ5 (0x1u << 10) /**< \brief (DMAC_CREQ) Source Chunk Request */\r
+#define DMAC_CREQ_DCREQ5 (0x1u << 11) /**< \brief (DMAC_CREQ) Destination Chunk Request */\r
+/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */\r
+#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */\r
+#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */\r
+#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */\r
+#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */\r
+#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */\r
+#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */\r
+#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */\r
+#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */\r
+#define DMAC_LAST_SLAST4 (0x1u << 8) /**< \brief (DMAC_LAST) Source Last */\r
+#define DMAC_LAST_DLAST4 (0x1u << 9) /**< \brief (DMAC_LAST) Destination Last */\r
+#define DMAC_LAST_SLAST5 (0x1u << 10) /**< \brief (DMAC_LAST) Source Last */\r
+#define DMAC_LAST_DLAST5 (0x1u << 11) /**< \brief (DMAC_LAST) Destination Last */\r
+/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */\r
+#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [5:0] */\r
+#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [5:0] */\r
+#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [5:0] */\r
+#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [5:0] */\r
+#define DMAC_EBCIER_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIER) Access Error [5:0] */\r
+#define DMAC_EBCIER_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIER) Access Error [5:0] */\r
+/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */\r
+#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */\r
+#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */\r
+#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */\r
+#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */\r
+#define DMAC_EBCIDR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */\r
+#define DMAC_EBCIDR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */\r
+/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */\r
+#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */\r
+#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */\r
+#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */\r
+#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */\r
+#define DMAC_EBCIMR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */\r
+#define DMAC_EBCIMR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */\r
+/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */\r
+#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */\r
+#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [5:0] */\r
+#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [5:0] */\r
+#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [5:0] */\r
+#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [5:0] */\r
+#define DMAC_EBCISR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCISR) Access Error [5:0] */\r
+#define DMAC_EBCISR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCISR) Access Error [5:0] */\r
+/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */\r
+#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [5:0] */\r
+#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [5:0] */\r
+#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [5:0] */\r
+#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [5:0] */\r
+#define DMAC_CHER_ENA4 (0x1u << 4) /**< \brief (DMAC_CHER) Enable [5:0] */\r
+#define DMAC_CHER_ENA5 (0x1u << 5) /**< \brief (DMAC_CHER) Enable [5:0] */\r
+#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [5:0] */\r
+#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [5:0] */\r
+#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [5:0] */\r
+#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [5:0] */\r
+#define DMAC_CHER_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHER) Suspend [5:0] */\r
+#define DMAC_CHER_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHER) Suspend [5:0] */\r
+#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [5:0] */\r
+#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [5:0] */\r
+#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [5:0] */\r
+#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [5:0] */\r
+#define DMAC_CHER_KEEP4 (0x1u << 28) /**< \brief (DMAC_CHER) Keep on [5:0] */\r
+#define DMAC_CHER_KEEP5 (0x1u << 29) /**< \brief (DMAC_CHER) Keep on [5:0] */\r
+/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */\r
+#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [5:0] */\r
+#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [5:0] */\r
+#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [5:0] */\r
+#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [5:0] */\r
+#define DMAC_CHDR_DIS4 (0x1u << 4) /**< \brief (DMAC_CHDR) Disable [5:0] */\r
+#define DMAC_CHDR_DIS5 (0x1u << 5) /**< \brief (DMAC_CHDR) Disable [5:0] */\r
+#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [5:0] */\r
+#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [5:0] */\r
+#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [5:0] */\r
+#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [5:0] */\r
+#define DMAC_CHDR_RES4 (0x1u << 12) /**< \brief (DMAC_CHDR) Resume [5:0] */\r
+#define DMAC_CHDR_RES5 (0x1u << 13) /**< \brief (DMAC_CHDR) Resume [5:0] */\r
+/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */\r
+#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [5:0] */\r
+#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [5:0] */\r
+#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [5:0] */\r
+#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [5:0] */\r
+#define DMAC_CHSR_ENA4 (0x1u << 4) /**< \brief (DMAC_CHSR) Enable [5:0] */\r
+#define DMAC_CHSR_ENA5 (0x1u << 5) /**< \brief (DMAC_CHSR) Enable [5:0] */\r
+#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [5:0] */\r
+#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [5:0] */\r
+#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [5:0] */\r
+#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [5:0] */\r
+#define DMAC_CHSR_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHSR) Suspend [5:0] */\r
+#define DMAC_CHSR_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHSR) Suspend [5:0] */\r
+#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [5:0] */\r
+#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [5:0] */\r
+#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [5:0] */\r
+#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [5:0] */\r
+#define DMAC_CHSR_EMPT4 (0x1u << 20) /**< \brief (DMAC_CHSR) Empty [5:0] */\r
+#define DMAC_CHSR_EMPT5 (0x1u << 21) /**< \brief (DMAC_CHSR) Empty [5:0] */\r
+#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [5:0] */\r
+#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [5:0] */\r
+#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [5:0] */\r
+#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [5:0] */\r
+#define DMAC_CHSR_STAL4 (0x1u << 28) /**< \brief (DMAC_CHSR) Stalled [5:0] */\r
+#define DMAC_CHSR_STAL5 (0x1u << 29) /**< \brief (DMAC_CHSR) Stalled [5:0] */\r
+/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */\r
+#define DMAC_SADDR_SADDR_Pos 0\r
+#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */\r
+#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos)))\r
+/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */\r
+#define DMAC_DADDR_DADDR_Pos 0\r
+#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */\r
+#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos)))\r
+/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */\r
+#define DMAC_DSCR_DSCR_Pos 2\r
+#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */\r
+#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos)))\r
+/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */\r
+#define DMAC_CTRLA_BTSIZE_Pos 0\r
+#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */\r
+#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))\r
+#define DMAC_CTRLA_SCSIZE_Pos 16\r
+#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) Source Chunk Transfer Size. */\r
+#define DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) /**< \brief (DMAC_CTRLA) 1 data transferred */\r
+#define DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) /**< \brief (DMAC_CTRLA) 4 data transferred */\r
+#define DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) /**< \brief (DMAC_CTRLA) 8 data transferred */\r
+#define DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) /**< \brief (DMAC_CTRLA) 16 data transferred */\r
+#define DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) /**< \brief (DMAC_CTRLA) 32 data transferred */\r
+#define DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) /**< \brief (DMAC_CTRLA) 64 data transferred */\r
+#define DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) /**< \brief (DMAC_CTRLA) 128 data transferred */\r
+#define DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) /**< \brief (DMAC_CTRLA) 256 data transferred */\r
+#define DMAC_CTRLA_DCSIZE_Pos 20\r
+#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) Destination Chunk Transfer Size */\r
+#define DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) /**< \brief (DMAC_CTRLA) 1 data transferred */\r
+#define DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) /**< \brief (DMAC_CTRLA) 4 data transferred */\r
+#define DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) /**< \brief (DMAC_CTRLA) 8 data transferred */\r
+#define DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) /**< \brief (DMAC_CTRLA) 16 data transferred */\r
+#define DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) /**< \brief (DMAC_CTRLA) 32 data transferred */\r
+#define DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) /**< \brief (DMAC_CTRLA) 64 data transferred */\r
+#define DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) /**< \brief (DMAC_CTRLA) 128 data transferred */\r
+#define DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) /**< \brief (DMAC_CTRLA) 256 data transferred */\r
+#define DMAC_CTRLA_SRC_WIDTH_Pos 24\r
+#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */\r
+#define DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */\r
+#define DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */\r
+#define DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */\r
+#define DMAC_CTRLA_DST_WIDTH_Pos 28\r
+#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */\r
+#define DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */\r
+#define DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */\r
+#define DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */\r
+#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA) */\r
+/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */\r
+#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */\r
+#define DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */\r
+#define DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */\r
+#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */\r
+#define DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */\r
+#define DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */\r
+#define DMAC_CTRLB_FC_Pos 21\r
+#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */\r
+#define DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */\r
+#define DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */\r
+#define DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */\r
+#define DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */\r
+#define DMAC_CTRLB_SRC_INCR_Pos 24\r
+#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */\r
+#define DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */\r
+#define DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */\r
+#define DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */\r
+#define DMAC_CTRLB_DST_INCR_Pos 28\r
+#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */\r
+#define DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */\r
+#define DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */\r
+#define DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */\r
+#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB) */\r
+/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */\r
+#define DMAC_CFG_SRC_PER_Pos 0\r
+#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */\r
+#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))\r
+#define DMAC_CFG_DST_PER_Pos 4\r
+#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */\r
+#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))\r
+#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */\r
+#define DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */\r
+#define DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */\r
+#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */\r
+#define DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */\r
+#define DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */\r
+#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */\r
+#define DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */\r
+#define DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */\r
+#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */\r
+#define DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */\r
+#define DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */\r
+#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */\r
+#define DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */\r
+#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */\r
+#define DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */\r
+#define DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */\r
+#define DMAC_CFG_AHB_PROT_Pos 24\r
+#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */\r
+#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))\r
+#define DMAC_CFG_FIFOCFG_Pos 28\r
+#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */\r
+#define DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */\r
+#define DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */\r
+#define DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */\r
+/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */\r
+#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */\r
+#define DMAC_WPMR_WPKEY_Pos 8\r
+#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */\r
+#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos)))\r
+/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */\r
+#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */\r
+#define DMAC_WPSR_WPVSRC_Pos 8\r
+#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_DMAC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_EFC_COMPONENT_\r
+#define _SAM3XA_EFC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_EFC Embedded Flash Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Efc hardware registers */\r
+typedef struct {\r
+ RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */\r
+ WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */\r
+ RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */\r
+ RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */\r
+} Efc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */\r
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */\r
+#define EEFC_FMR_FWS_Pos 8\r
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */\r
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))\r
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */\r
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */\r
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */\r
+#define EEFC_FCR_FCMD_Pos 0\r
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */\r
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))\r
+#define EEFC_FCR_FARG_Pos 8\r
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */\r
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))\r
+#define EEFC_FCR_FKEY_Pos 24\r
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */\r
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))\r
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */\r
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */\r
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */\r
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */\r
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */\r
+#define EEFC_FRR_FVALUE_Pos 0\r
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_EFC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_EMAC_COMPONENT_\r
+#define _SAM3XA_EMAC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_EMAC Ethernet MAC 10/100 */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief EmacSa hardware registers */\r
+typedef struct {\r
+ RwReg EMAC_SAxB; /**< \brief (EmacSa Offset: 0x0) Specific Address 1 Bottom Register */\r
+ RwReg EMAC_SAxT; /**< \brief (EmacSa Offset: 0x4) Specific Address 1 Top Register */\r
+} EmacSa;\r
+/** \brief Emac hardware registers */\r
+#define EMACSA_NUMBER 4\r
+typedef struct {\r
+ RwReg EMAC_NCR; /**< \brief (Emac Offset: 0x00) Network Control Register */\r
+ RwReg EMAC_NCFGR; /**< \brief (Emac Offset: 0x04) Network Configuration Register */\r
+ RoReg EMAC_NSR; /**< \brief (Emac Offset: 0x08) Network Status Register */\r
+ RoReg Reserved1[2];\r
+ RwReg EMAC_TSR; /**< \brief (Emac Offset: 0x14) Transmit Status Register */\r
+ RwReg EMAC_RBQP; /**< \brief (Emac Offset: 0x18) Receive Buffer Queue Pointer Register */\r
+ RwReg EMAC_TBQP; /**< \brief (Emac Offset: 0x1C) Transmit Buffer Queue Pointer Register */\r
+ RwReg EMAC_RSR; /**< \brief (Emac Offset: 0x20) Receive Status Register */\r
+ RwReg EMAC_ISR; /**< \brief (Emac Offset: 0x24) Interrupt Status Register */\r
+ WoReg EMAC_IER; /**< \brief (Emac Offset: 0x28) Interrupt Enable Register */\r
+ WoReg EMAC_IDR; /**< \brief (Emac Offset: 0x2C) Interrupt Disable Register */\r
+ RoReg EMAC_IMR; /**< \brief (Emac Offset: 0x30) Interrupt Mask Register */\r
+ RwReg EMAC_MAN; /**< \brief (Emac Offset: 0x34) Phy Maintenance Register */\r
+ RwReg EMAC_PTR; /**< \brief (Emac Offset: 0x38) Pause Time Register */\r
+ RwReg EMAC_PFR; /**< \brief (Emac Offset: 0x3C) Pause Frames Received Register */\r
+ RwReg EMAC_FTO; /**< \brief (Emac Offset: 0x40) Frames Transmitted Ok Register */\r
+ RwReg EMAC_SCF; /**< \brief (Emac Offset: 0x44) Single Collision Frames Register */\r
+ RwReg EMAC_MCF; /**< \brief (Emac Offset: 0x48) Multiple Collision Frames Register */\r
+ RwReg EMAC_FRO; /**< \brief (Emac Offset: 0x4C) Frames Received Ok Register */\r
+ RwReg EMAC_FCSE; /**< \brief (Emac Offset: 0x50) Frame Check Sequence Errors Register */\r
+ RwReg EMAC_ALE; /**< \brief (Emac Offset: 0x54) Alignment Errors Register */\r
+ RwReg EMAC_DTF; /**< \brief (Emac Offset: 0x58) Deferred Transmission Frames Register */\r
+ RwReg EMAC_LCOL; /**< \brief (Emac Offset: 0x5C) Late Collisions Register */\r
+ RwReg EMAC_ECOL; /**< \brief (Emac Offset: 0x60) Excessive Collisions Register */\r
+ RwReg EMAC_TUND; /**< \brief (Emac Offset: 0x64) Transmit Underrun Errors Register */\r
+ RwReg EMAC_CSE; /**< \brief (Emac Offset: 0x68) Carrier Sense Errors Register */\r
+ RwReg EMAC_RRE; /**< \brief (Emac Offset: 0x6C) Receive Resource Errors Register */\r
+ RwReg EMAC_ROV; /**< \brief (Emac Offset: 0x70) Receive Overrun Errors Register */\r
+ RwReg EMAC_RSE; /**< \brief (Emac Offset: 0x74) Receive Symbol Errors Register */\r
+ RwReg EMAC_ELE; /**< \brief (Emac Offset: 0x78) Excessive Length Errors Register */\r
+ RwReg EMAC_RJA; /**< \brief (Emac Offset: 0x7C) Receive Jabbers Register */\r
+ RwReg EMAC_USF; /**< \brief (Emac Offset: 0x80) Undersize Frames Register */\r
+ RwReg EMAC_STE; /**< \brief (Emac Offset: 0x84) SQE Test Errors Register */\r
+ RwReg EMAC_RLE; /**< \brief (Emac Offset: 0x88) Received Length Field Mismatch Register */\r
+ RoReg Reserved2[1];\r
+ RwReg EMAC_HRB; /**< \brief (Emac Offset: 0x90) Hash Register Bottom [31:0] Register */\r
+ RwReg EMAC_HRT; /**< \brief (Emac Offset: 0x94) Hash Register Top [63:32] Register */\r
+ EmacSa EMAC_SA[EMACSA_NUMBER]; /**< \brief (Emac Offset: 0x98) sa = 1 .. 4 */\r
+ RwReg EMAC_TID; /**< \brief (Emac Offset: 0xB8) Type ID Checking Register */\r
+ RoReg Reserved3[1];\r
+ RwReg EMAC_USRIO; /**< \brief (Emac Offset: 0xC0) User Input/Output Register */\r
+} Emac;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- EMAC_NCR : (EMAC Offset: 0x00) Network Control Register -------- */\r
+#define EMAC_NCR_LB (0x1u << 0) /**< \brief (EMAC_NCR) LoopBack */\r
+#define EMAC_NCR_LLB (0x1u << 1) /**< \brief (EMAC_NCR) Loopback local */\r
+#define EMAC_NCR_RE (0x1u << 2) /**< \brief (EMAC_NCR) Receive enable */\r
+#define EMAC_NCR_TE (0x1u << 3) /**< \brief (EMAC_NCR) Transmit enable */\r
+#define EMAC_NCR_MPE (0x1u << 4) /**< \brief (EMAC_NCR) Management port enable */\r
+#define EMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (EMAC_NCR) Clear statistics registers */\r
+#define EMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (EMAC_NCR) Increment statistics registers */\r
+#define EMAC_NCR_WESTAT (0x1u << 7) /**< \brief (EMAC_NCR) Write enable for statistics registers */\r
+#define EMAC_NCR_BP (0x1u << 8) /**< \brief (EMAC_NCR) Back pressure */\r
+#define EMAC_NCR_TSTART (0x1u << 9) /**< \brief (EMAC_NCR) Start transmission */\r
+#define EMAC_NCR_THALT (0x1u << 10) /**< \brief (EMAC_NCR) Transmit halt */\r
+/* -------- EMAC_NCFGR : (EMAC Offset: 0x04) Network Configuration Register -------- */\r
+#define EMAC_NCFGR_SPD (0x1u << 0) /**< \brief (EMAC_NCFGR) Speed */\r
+#define EMAC_NCFGR_FD (0x1u << 1) /**< \brief (EMAC_NCFGR) Full Duplex */\r
+#define EMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (EMAC_NCFGR) Jumbo Frames */\r
+#define EMAC_NCFGR_CAF (0x1u << 4) /**< \brief (EMAC_NCFGR) Copy All Frames */\r
+#define EMAC_NCFGR_NBC (0x1u << 5) /**< \brief (EMAC_NCFGR) No Broadcast */\r
+#define EMAC_NCFGR_MTI (0x1u << 6) /**< \brief (EMAC_NCFGR) Multicast Hash Enable */\r
+#define EMAC_NCFGR_UNI (0x1u << 7) /**< \brief (EMAC_NCFGR) Unicast Hash Enable */\r
+#define EMAC_NCFGR_BIG (0x1u << 8) /**< \brief (EMAC_NCFGR) Receive 1536 bytes frames */\r
+#define EMAC_NCFGR_CLK_Pos 10\r
+#define EMAC_NCFGR_CLK_Msk (0x3u << EMAC_NCFGR_CLK_Pos) /**< \brief (EMAC_NCFGR) MDC clock divider */\r
+#define EMAC_NCFGR_CLK_MCK_8 (0x0u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz). */\r
+#define EMAC_NCFGR_CLK_MCK_16 (0x1u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz). */\r
+#define EMAC_NCFGR_CLK_MCK_32 (0x2u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz). */\r
+#define EMAC_NCFGR_CLK_MCK_64 (0x3u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz). */\r
+#define EMAC_NCFGR_RTY (0x1u << 12) /**< \brief (EMAC_NCFGR) Retry test */\r
+#define EMAC_NCFGR_PAE (0x1u << 13) /**< \brief (EMAC_NCFGR) Pause Enable */\r
+#define EMAC_NCFGR_RBOF_Pos 14\r
+#define EMAC_NCFGR_RBOF_Msk (0x3u << EMAC_NCFGR_RBOF_Pos) /**< \brief (EMAC_NCFGR) Receive Buffer Offset */\r
+#define EMAC_NCFGR_RBOF_OFFSET_0 (0x0u << 14) /**< \brief (EMAC_NCFGR) No offset from start of receive buffer. */\r
+#define EMAC_NCFGR_RBOF_OFFSET_1 (0x1u << 14) /**< \brief (EMAC_NCFGR) One-byte offset from start of receive buffer. */\r
+#define EMAC_NCFGR_RBOF_OFFSET_2 (0x2u << 14) /**< \brief (EMAC_NCFGR) Two-byte offset from start of receive buffer. */\r
+#define EMAC_NCFGR_RBOF_OFFSET_3 (0x3u << 14) /**< \brief (EMAC_NCFGR) Three-byte offset from start of receive buffer. */\r
+#define EMAC_NCFGR_RLCE (0x1u << 16) /**< \brief (EMAC_NCFGR) Receive Length field Checking Enable */\r
+#define EMAC_NCFGR_DRFCS (0x1u << 17) /**< \brief (EMAC_NCFGR) Discard Receive FCS */\r
+#define EMAC_NCFGR_EFRHD (0x1u << 18) /**< \brief (EMAC_NCFGR) */\r
+#define EMAC_NCFGR_IRXFCS (0x1u << 19) /**< \brief (EMAC_NCFGR) Ignore RX FCS */\r
+/* -------- EMAC_NSR : (EMAC Offset: 0x08) Network Status Register -------- */\r
+#define EMAC_NSR_MDIO (0x1u << 1) /**< \brief (EMAC_NSR) */\r
+#define EMAC_NSR_IDLE (0x1u << 2) /**< \brief (EMAC_NSR) */\r
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */\r
+#define EMAC_TSR_UBR (0x1u << 0) /**< \brief (EMAC_TSR) Used Bit Read */\r
+#define EMAC_TSR_COL (0x1u << 1) /**< \brief (EMAC_TSR) Collision Occurred */\r
+#define EMAC_TSR_RLES (0x1u << 2) /**< \brief (EMAC_TSR) Retry Limit exceeded */\r
+#define EMAC_TSR_TGO (0x1u << 3) /**< \brief (EMAC_TSR) Transmit Go */\r
+#define EMAC_TSR_BEX (0x1u << 4) /**< \brief (EMAC_TSR) Buffers exhausted mid frame */\r
+#define EMAC_TSR_COMP (0x1u << 5) /**< \brief (EMAC_TSR) Transmit Complete */\r
+#define EMAC_TSR_UND (0x1u << 6) /**< \brief (EMAC_TSR) Transmit Underrun */\r
+/* -------- EMAC_RBQP : (EMAC Offset: 0x18) Receive Buffer Queue Pointer Register -------- */\r
+#define EMAC_RBQP_ADDR_Pos 2\r
+#define EMAC_RBQP_ADDR_Msk (0x3fffffffu << EMAC_RBQP_ADDR_Pos) /**< \brief (EMAC_RBQP) Receive buffer queue pointer address */\r
+#define EMAC_RBQP_ADDR(value) ((EMAC_RBQP_ADDR_Msk & ((value) << EMAC_RBQP_ADDR_Pos)))\r
+/* -------- EMAC_TBQP : (EMAC Offset: 0x1C) Transmit Buffer Queue Pointer Register -------- */\r
+#define EMAC_TBQP_ADDR_Pos 2\r
+#define EMAC_TBQP_ADDR_Msk (0x3fffffffu << EMAC_TBQP_ADDR_Pos) /**< \brief (EMAC_TBQP) Transmit buffer queue pointer address */\r
+#define EMAC_TBQP_ADDR(value) ((EMAC_TBQP_ADDR_Msk & ((value) << EMAC_TBQP_ADDR_Pos)))\r
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */\r
+#define EMAC_RSR_BNA (0x1u << 0) /**< \brief (EMAC_RSR) Buffer Not Available */\r
+#define EMAC_RSR_REC (0x1u << 1) /**< \brief (EMAC_RSR) Frame Received */\r
+#define EMAC_RSR_OVR (0x1u << 2) /**< \brief (EMAC_RSR) Receive Overrun */\r
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */\r
+#define EMAC_ISR_MFD (0x1u << 0) /**< \brief (EMAC_ISR) Management Frame Done */\r
+#define EMAC_ISR_RCOMP (0x1u << 1) /**< \brief (EMAC_ISR) Receive Complete */\r
+#define EMAC_ISR_RXUBR (0x1u << 2) /**< \brief (EMAC_ISR) Receive Used Bit Read */\r
+#define EMAC_ISR_TXUBR (0x1u << 3) /**< \brief (EMAC_ISR) Transmit Used Bit Read */\r
+#define EMAC_ISR_TUND (0x1u << 4) /**< \brief (EMAC_ISR) Ethernet Transmit Buffer Underrun */\r
+#define EMAC_ISR_RLEX (0x1u << 5) /**< \brief (EMAC_ISR) Retry Limit Exceeded */\r
+#define EMAC_ISR_TXERR (0x1u << 6) /**< \brief (EMAC_ISR) Transmit Error */\r
+#define EMAC_ISR_TCOMP (0x1u << 7) /**< \brief (EMAC_ISR) Transmit Complete */\r
+#define EMAC_ISR_ROVR (0x1u << 10) /**< \brief (EMAC_ISR) Receive Overrun */\r
+#define EMAC_ISR_HRESP (0x1u << 11) /**< \brief (EMAC_ISR) Hresp not OK */\r
+#define EMAC_ISR_PFRE (0x1u << 12) /**< \brief (EMAC_ISR) Pause Frame Received */\r
+#define EMAC_ISR_PTZ (0x1u << 13) /**< \brief (EMAC_ISR) Pause Time Zero */\r
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */\r
+#define EMAC_IER_MFD (0x1u << 0) /**< \brief (EMAC_IER) Management Frame sent */\r
+#define EMAC_IER_RCOMP (0x1u << 1) /**< \brief (EMAC_IER) Receive Complete */\r
+#define EMAC_IER_RXUBR (0x1u << 2) /**< \brief (EMAC_IER) Receive Used Bit Read */\r
+#define EMAC_IER_TXUBR (0x1u << 3) /**< \brief (EMAC_IER) Transmit Used Bit Read */\r
+#define EMAC_IER_TUND (0x1u << 4) /**< \brief (EMAC_IER) Ethernet Transmit Buffer Underrun */\r
+#define EMAC_IER_RLE (0x1u << 5) /**< \brief (EMAC_IER) Retry Limit Exceeded */\r
+#define EMAC_IER_TXERR (0x1u << 6) /**< \brief (EMAC_IER) */\r
+#define EMAC_IER_TCOMP (0x1u << 7) /**< \brief (EMAC_IER) Transmit Complete */\r
+#define EMAC_IER_ROVR (0x1u << 10) /**< \brief (EMAC_IER) Receive Overrun */\r
+#define EMAC_IER_HRESP (0x1u << 11) /**< \brief (EMAC_IER) Hresp not OK */\r
+#define EMAC_IER_PFR (0x1u << 12) /**< \brief (EMAC_IER) Pause Frame Received */\r
+#define EMAC_IER_PTZ (0x1u << 13) /**< \brief (EMAC_IER) Pause Time Zero */\r
+/* -------- EMAC_IDR : (EMAC Offset: 0x2C) Interrupt Disable Register -------- */\r
+#define EMAC_IDR_MFD (0x1u << 0) /**< \brief (EMAC_IDR) Management Frame sent */\r
+#define EMAC_IDR_RCOMP (0x1u << 1) /**< \brief (EMAC_IDR) Receive Complete */\r
+#define EMAC_IDR_RXUBR (0x1u << 2) /**< \brief (EMAC_IDR) Receive Used Bit Read */\r
+#define EMAC_IDR_TXUBR (0x1u << 3) /**< \brief (EMAC_IDR) Transmit Used Bit Read */\r
+#define EMAC_IDR_TUND (0x1u << 4) /**< \brief (EMAC_IDR) Ethernet Transmit Buffer Underrun */\r
+#define EMAC_IDR_RLE (0x1u << 5) /**< \brief (EMAC_IDR) Retry Limit Exceeded */\r
+#define EMAC_IDR_TXERR (0x1u << 6) /**< \brief (EMAC_IDR) */\r
+#define EMAC_IDR_TCOMP (0x1u << 7) /**< \brief (EMAC_IDR) Transmit Complete */\r
+#define EMAC_IDR_ROVR (0x1u << 10) /**< \brief (EMAC_IDR) Receive Overrun */\r
+#define EMAC_IDR_HRESP (0x1u << 11) /**< \brief (EMAC_IDR) Hresp not OK */\r
+#define EMAC_IDR_PFR (0x1u << 12) /**< \brief (EMAC_IDR) Pause Frame Received */\r
+#define EMAC_IDR_PTZ (0x1u << 13) /**< \brief (EMAC_IDR) Pause Time Zero */\r
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */\r
+#define EMAC_IMR_MFD (0x1u << 0) /**< \brief (EMAC_IMR) Management Frame sent */\r
+#define EMAC_IMR_RCOMP (0x1u << 1) /**< \brief (EMAC_IMR) Receive Complete */\r
+#define EMAC_IMR_RXUBR (0x1u << 2) /**< \brief (EMAC_IMR) Receive Used Bit Read */\r
+#define EMAC_IMR_TXUBR (0x1u << 3) /**< \brief (EMAC_IMR) Transmit Used Bit Read */\r
+#define EMAC_IMR_TUND (0x1u << 4) /**< \brief (EMAC_IMR) Ethernet Transmit Buffer Underrun */\r
+#define EMAC_IMR_RLE (0x1u << 5) /**< \brief (EMAC_IMR) Retry Limit Exceeded */\r
+#define EMAC_IMR_TXERR (0x1u << 6) /**< \brief (EMAC_IMR) */\r
+#define EMAC_IMR_TCOMP (0x1u << 7) /**< \brief (EMAC_IMR) Transmit Complete */\r
+#define EMAC_IMR_ROVR (0x1u << 10) /**< \brief (EMAC_IMR) Receive Overrun */\r
+#define EMAC_IMR_HRESP (0x1u << 11) /**< \brief (EMAC_IMR) Hresp not OK */\r
+#define EMAC_IMR_PFR (0x1u << 12) /**< \brief (EMAC_IMR) Pause Frame Received */\r
+#define EMAC_IMR_PTZ (0x1u << 13) /**< \brief (EMAC_IMR) Pause Time Zero */\r
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) Phy Maintenance Register -------- */\r
+#define EMAC_MAN_DATA_Pos 0\r
+#define EMAC_MAN_DATA_Msk (0xffffu << EMAC_MAN_DATA_Pos) /**< \brief (EMAC_MAN) */\r
+#define EMAC_MAN_DATA(value) ((EMAC_MAN_DATA_Msk & ((value) << EMAC_MAN_DATA_Pos)))\r
+#define EMAC_MAN_CODE_Pos 16\r
+#define EMAC_MAN_CODE_Msk (0x3u << EMAC_MAN_CODE_Pos) /**< \brief (EMAC_MAN) */\r
+#define EMAC_MAN_CODE(value) ((EMAC_MAN_CODE_Msk & ((value) << EMAC_MAN_CODE_Pos)))\r
+#define EMAC_MAN_REGA_Pos 18\r
+#define EMAC_MAN_REGA_Msk (0x1fu << EMAC_MAN_REGA_Pos) /**< \brief (EMAC_MAN) Register Address */\r
+#define EMAC_MAN_REGA(value) ((EMAC_MAN_REGA_Msk & ((value) << EMAC_MAN_REGA_Pos)))\r
+#define EMAC_MAN_PHYA_Pos 23\r
+#define EMAC_MAN_PHYA_Msk (0x1fu << EMAC_MAN_PHYA_Pos) /**< \brief (EMAC_MAN) PHY Address */\r
+#define EMAC_MAN_PHYA(value) ((EMAC_MAN_PHYA_Msk & ((value) << EMAC_MAN_PHYA_Pos)))\r
+#define EMAC_MAN_RW_Pos 28\r
+#define EMAC_MAN_RW_Msk (0x3u << EMAC_MAN_RW_Pos) /**< \brief (EMAC_MAN) Read-write */\r
+#define EMAC_MAN_RW(value) ((EMAC_MAN_RW_Msk & ((value) << EMAC_MAN_RW_Pos)))\r
+#define EMAC_MAN_SOF_Pos 30\r
+#define EMAC_MAN_SOF_Msk (0x3u << EMAC_MAN_SOF_Pos) /**< \brief (EMAC_MAN) Start of frame */\r
+#define EMAC_MAN_SOF(value) ((EMAC_MAN_SOF_Msk & ((value) << EMAC_MAN_SOF_Pos)))\r
+/* -------- EMAC_PTR : (EMAC Offset: 0x38) Pause Time Register -------- */\r
+#define EMAC_PTR_PTIME_Pos 0\r
+#define EMAC_PTR_PTIME_Msk (0xffffu << EMAC_PTR_PTIME_Pos) /**< \brief (EMAC_PTR) Pause Time */\r
+#define EMAC_PTR_PTIME(value) ((EMAC_PTR_PTIME_Msk & ((value) << EMAC_PTR_PTIME_Pos)))\r
+/* -------- EMAC_PFR : (EMAC Offset: 0x3C) Pause Frames Received Register -------- */\r
+#define EMAC_PFR_FROK_Pos 0\r
+#define EMAC_PFR_FROK_Msk (0xffffu << EMAC_PFR_FROK_Pos) /**< \brief (EMAC_PFR) Pause Frames received OK */\r
+#define EMAC_PFR_FROK(value) ((EMAC_PFR_FROK_Msk & ((value) << EMAC_PFR_FROK_Pos)))\r
+/* -------- EMAC_FTO : (EMAC Offset: 0x40) Frames Transmitted Ok Register -------- */\r
+#define EMAC_FTO_FTOK_Pos 0\r
+#define EMAC_FTO_FTOK_Msk (0xffffffu << EMAC_FTO_FTOK_Pos) /**< \brief (EMAC_FTO) Frames Transmitted OK */\r
+#define EMAC_FTO_FTOK(value) ((EMAC_FTO_FTOK_Msk & ((value) << EMAC_FTO_FTOK_Pos)))\r
+/* -------- EMAC_SCF : (EMAC Offset: 0x44) Single Collision Frames Register -------- */\r
+#define EMAC_SCF_SCF_Pos 0\r
+#define EMAC_SCF_SCF_Msk (0xffffu << EMAC_SCF_SCF_Pos) /**< \brief (EMAC_SCF) Single Collision Frames */\r
+#define EMAC_SCF_SCF(value) ((EMAC_SCF_SCF_Msk & ((value) << EMAC_SCF_SCF_Pos)))\r
+/* -------- EMAC_MCF : (EMAC Offset: 0x48) Multiple Collision Frames Register -------- */\r
+#define EMAC_MCF_MCF_Pos 0\r
+#define EMAC_MCF_MCF_Msk (0xffffu << EMAC_MCF_MCF_Pos) /**< \brief (EMAC_MCF) Multicollision Frames */\r
+#define EMAC_MCF_MCF(value) ((EMAC_MCF_MCF_Msk & ((value) << EMAC_MCF_MCF_Pos)))\r
+/* -------- EMAC_FRO : (EMAC Offset: 0x4C) Frames Received Ok Register -------- */\r
+#define EMAC_FRO_FROK_Pos 0\r
+#define EMAC_FRO_FROK_Msk (0xffffffu << EMAC_FRO_FROK_Pos) /**< \brief (EMAC_FRO) Frames Received OK */\r
+#define EMAC_FRO_FROK(value) ((EMAC_FRO_FROK_Msk & ((value) << EMAC_FRO_FROK_Pos)))\r
+/* -------- EMAC_FCSE : (EMAC Offset: 0x50) Frame Check Sequence Errors Register -------- */\r
+#define EMAC_FCSE_FCSE_Pos 0\r
+#define EMAC_FCSE_FCSE_Msk (0xffu << EMAC_FCSE_FCSE_Pos) /**< \brief (EMAC_FCSE) Frame Check Sequence Errors */\r
+#define EMAC_FCSE_FCSE(value) ((EMAC_FCSE_FCSE_Msk & ((value) << EMAC_FCSE_FCSE_Pos)))\r
+/* -------- EMAC_ALE : (EMAC Offset: 0x54) Alignment Errors Register -------- */\r
+#define EMAC_ALE_ALE_Pos 0\r
+#define EMAC_ALE_ALE_Msk (0xffu << EMAC_ALE_ALE_Pos) /**< \brief (EMAC_ALE) Alignment Errors */\r
+#define EMAC_ALE_ALE(value) ((EMAC_ALE_ALE_Msk & ((value) << EMAC_ALE_ALE_Pos)))\r
+/* -------- EMAC_DTF : (EMAC Offset: 0x58) Deferred Transmission Frames Register -------- */\r
+#define EMAC_DTF_DTF_Pos 0\r
+#define EMAC_DTF_DTF_Msk (0xffffu << EMAC_DTF_DTF_Pos) /**< \brief (EMAC_DTF) Deferred Transmission Frames */\r
+#define EMAC_DTF_DTF(value) ((EMAC_DTF_DTF_Msk & ((value) << EMAC_DTF_DTF_Pos)))\r
+/* -------- EMAC_LCOL : (EMAC Offset: 0x5C) Late Collisions Register -------- */\r
+#define EMAC_LCOL_LCOL_Pos 0\r
+#define EMAC_LCOL_LCOL_Msk (0xffu << EMAC_LCOL_LCOL_Pos) /**< \brief (EMAC_LCOL) Late Collisions */\r
+#define EMAC_LCOL_LCOL(value) ((EMAC_LCOL_LCOL_Msk & ((value) << EMAC_LCOL_LCOL_Pos)))\r
+/* -------- EMAC_ECOL : (EMAC Offset: 0x60) Excessive Collisions Register -------- */\r
+#define EMAC_ECOL_EXCOL_Pos 0\r
+#define EMAC_ECOL_EXCOL_Msk (0xffu << EMAC_ECOL_EXCOL_Pos) /**< \brief (EMAC_ECOL) Excessive Collisions */\r
+#define EMAC_ECOL_EXCOL(value) ((EMAC_ECOL_EXCOL_Msk & ((value) << EMAC_ECOL_EXCOL_Pos)))\r
+/* -------- EMAC_TUND : (EMAC Offset: 0x64) Transmit Underrun Errors Register -------- */\r
+#define EMAC_TUND_TUND_Pos 0\r
+#define EMAC_TUND_TUND_Msk (0xffu << EMAC_TUND_TUND_Pos) /**< \brief (EMAC_TUND) Transmit Underruns */\r
+#define EMAC_TUND_TUND(value) ((EMAC_TUND_TUND_Msk & ((value) << EMAC_TUND_TUND_Pos)))\r
+/* -------- EMAC_CSE : (EMAC Offset: 0x68) Carrier Sense Errors Register -------- */\r
+#define EMAC_CSE_CSE_Pos 0\r
+#define EMAC_CSE_CSE_Msk (0xffu << EMAC_CSE_CSE_Pos) /**< \brief (EMAC_CSE) Carrier Sense Errors */\r
+#define EMAC_CSE_CSE(value) ((EMAC_CSE_CSE_Msk & ((value) << EMAC_CSE_CSE_Pos)))\r
+/* -------- EMAC_RRE : (EMAC Offset: 0x6C) Receive Resource Errors Register -------- */\r
+#define EMAC_RRE_RRE_Pos 0\r
+#define EMAC_RRE_RRE_Msk (0xffffu << EMAC_RRE_RRE_Pos) /**< \brief (EMAC_RRE) Receive Resource Errors */\r
+#define EMAC_RRE_RRE(value) ((EMAC_RRE_RRE_Msk & ((value) << EMAC_RRE_RRE_Pos)))\r
+/* -------- EMAC_ROV : (EMAC Offset: 0x70) Receive Overrun Errors Register -------- */\r
+#define EMAC_ROV_ROVR_Pos 0\r
+#define EMAC_ROV_ROVR_Msk (0xffu << EMAC_ROV_ROVR_Pos) /**< \brief (EMAC_ROV) Receive Overrun */\r
+#define EMAC_ROV_ROVR(value) ((EMAC_ROV_ROVR_Msk & ((value) << EMAC_ROV_ROVR_Pos)))\r
+/* -------- EMAC_RSE : (EMAC Offset: 0x74) Receive Symbol Errors Register -------- */\r
+#define EMAC_RSE_RSE_Pos 0\r
+#define EMAC_RSE_RSE_Msk (0xffu << EMAC_RSE_RSE_Pos) /**< \brief (EMAC_RSE) Receive Symbol Errors */\r
+#define EMAC_RSE_RSE(value) ((EMAC_RSE_RSE_Msk & ((value) << EMAC_RSE_RSE_Pos)))\r
+/* -------- EMAC_ELE : (EMAC Offset: 0x78) Excessive Length Errors Register -------- */\r
+#define EMAC_ELE_EXL_Pos 0\r
+#define EMAC_ELE_EXL_Msk (0xffu << EMAC_ELE_EXL_Pos) /**< \brief (EMAC_ELE) Excessive Length Errors */\r
+#define EMAC_ELE_EXL(value) ((EMAC_ELE_EXL_Msk & ((value) << EMAC_ELE_EXL_Pos)))\r
+/* -------- EMAC_RJA : (EMAC Offset: 0x7C) Receive Jabbers Register -------- */\r
+#define EMAC_RJA_RJB_Pos 0\r
+#define EMAC_RJA_RJB_Msk (0xffu << EMAC_RJA_RJB_Pos) /**< \brief (EMAC_RJA) Receive Jabbers */\r
+#define EMAC_RJA_RJB(value) ((EMAC_RJA_RJB_Msk & ((value) << EMAC_RJA_RJB_Pos)))\r
+/* -------- EMAC_USF : (EMAC Offset: 0x80) Undersize Frames Register -------- */\r
+#define EMAC_USF_USF_Pos 0\r
+#define EMAC_USF_USF_Msk (0xffu << EMAC_USF_USF_Pos) /**< \brief (EMAC_USF) Undersize frames */\r
+#define EMAC_USF_USF(value) ((EMAC_USF_USF_Msk & ((value) << EMAC_USF_USF_Pos)))\r
+/* -------- EMAC_STE : (EMAC Offset: 0x84) SQE Test Errors Register -------- */\r
+#define EMAC_STE_SQER_Pos 0\r
+#define EMAC_STE_SQER_Msk (0xffu << EMAC_STE_SQER_Pos) /**< \brief (EMAC_STE) SQE test errors */\r
+#define EMAC_STE_SQER(value) ((EMAC_STE_SQER_Msk & ((value) << EMAC_STE_SQER_Pos)))\r
+/* -------- EMAC_RLE : (EMAC Offset: 0x88) Received Length Field Mismatch Register -------- */\r
+#define EMAC_RLE_RLFM_Pos 0\r
+#define EMAC_RLE_RLFM_Msk (0xffu << EMAC_RLE_RLFM_Pos) /**< \brief (EMAC_RLE) Receive Length Field Mismatch */\r
+#define EMAC_RLE_RLFM(value) ((EMAC_RLE_RLFM_Msk & ((value) << EMAC_RLE_RLFM_Pos)))\r
+/* -------- EMAC_HRB : (EMAC Offset: 0x90) Hash Register Bottom [31:0] Register -------- */\r
+#define EMAC_HRB_ADDR_Pos 0\r
+#define EMAC_HRB_ADDR_Msk (0xffffffffu << EMAC_HRB_ADDR_Pos) /**< \brief (EMAC_HRB) */\r
+#define EMAC_HRB_ADDR(value) ((EMAC_HRB_ADDR_Msk & ((value) << EMAC_HRB_ADDR_Pos)))\r
+/* -------- EMAC_HRT : (EMAC Offset: 0x94) Hash Register Top [63:32] Register -------- */\r
+#define EMAC_HRT_ADDR_Pos 0\r
+#define EMAC_HRT_ADDR_Msk (0xffffffffu << EMAC_HRT_ADDR_Pos) /**< \brief (EMAC_HRT) */\r
+#define EMAC_HRT_ADDR(value) ((EMAC_HRT_ADDR_Msk & ((value) << EMAC_HRT_ADDR_Pos)))\r
+/* -------- EMAC_SAxB : (EMAC Offset: N/A) Specific Address 1 Bottom Register -------- */\r
+#define EMAC_SAxB_ADDR_Pos 0\r
+#define EMAC_SAxB_ADDR_Msk (0xffffffffu << EMAC_SAxB_ADDR_Pos) /**< \brief (EMAC_SAxB) */\r
+#define EMAC_SAxB_ADDR(value) ((EMAC_SAxB_ADDR_Msk & ((value) << EMAC_SAxB_ADDR_Pos)))\r
+/* -------- EMAC_SAxT : (EMAC Offset: N/A) Specific Address 1 Top Register -------- */\r
+#define EMAC_SAxT_ADDR_Pos 0\r
+#define EMAC_SAxT_ADDR_Msk (0xffffu << EMAC_SAxT_ADDR_Pos) /**< \brief (EMAC_SAxT) */\r
+#define EMAC_SAxT_ADDR(value) ((EMAC_SAxT_ADDR_Msk & ((value) << EMAC_SAxT_ADDR_Pos)))\r
+/* -------- EMAC_TID : (EMAC Offset: 0xB8) Type ID Checking Register -------- */\r
+#define EMAC_TID_TID_Pos 0\r
+#define EMAC_TID_TID_Msk (0xffffu << EMAC_TID_TID_Pos) /**< \brief (EMAC_TID) Type ID checking */\r
+#define EMAC_TID_TID(value) ((EMAC_TID_TID_Msk & ((value) << EMAC_TID_TID_Pos)))\r
+/* -------- EMAC_USRIO : (EMAC Offset: 0xC0) User Input/Output Register -------- */\r
+#define EMAC_USRIO_RMII (0x1u << 0) /**< \brief (EMAC_USRIO) Reduce MII */\r
+#define EMAC_USRIO_CLKEN (0x1u << 1) /**< \brief (EMAC_USRIO) Clock Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_EMAC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_GPBR_COMPONENT_\r
+#define _SAM3XA_GPBR_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_GPBR General Purpose Backup Register */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Gpbr hardware registers */\r
+typedef struct {\r
+ RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */\r
+} Gpbr;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */\r
+#define SYS_GPBR_GPBR_VALUE_Pos 0\r
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */\r
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_GPBR_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_HSMCI_COMPONENT_\r
+#define _SAM3XA_HSMCI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_HSMCI High Speed MultiMedia Card Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Hsmci hardware registers */\r
+typedef struct {\r
+ WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */\r
+ RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */\r
+ RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */\r
+ RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */\r
+ RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */\r
+ WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */\r
+ RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */\r
+ RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */\r
+ RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */\r
+ RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */\r
+ WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */\r
+ RoReg Reserved1[2];\r
+ RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */\r
+ WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */\r
+ WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */\r
+ RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */\r
+ RwReg HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */\r
+ RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */\r
+ RoReg Reserved2[35];\r
+ RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */\r
+ RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */\r
+ RoReg Reserved3[69];\r
+ RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */\r
+} Hsmci;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */\r
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */\r
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */\r
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */\r
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */\r
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */\r
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */\r
+#define HSMCI_MR_CLKDIV_Pos 0\r
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */\r
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))\r
+#define HSMCI_MR_PWSDIV_Pos 8\r
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */\r
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))\r
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */\r
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */\r
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */\r
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */\r
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */\r
+#define HSMCI_DTOR_DTOCYC_Pos 0\r
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */\r
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))\r
+#define HSMCI_DTOR_DTOMUL_Pos 4\r
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */\r
+#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */\r
+#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */\r
+#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */\r
+#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */\r
+#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */\r
+#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */\r
+#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */\r
+#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */\r
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */\r
+#define HSMCI_SDCR_SDCSEL_Pos 0\r
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */\r
+#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */\r
+#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) SDCARD/SDIO Slot B selected */\r
+#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */\r
+#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */\r
+#define HSMCI_SDCR_SDCBUS_Pos 6\r
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */\r
+#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */\r
+#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */\r
+#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */\r
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */\r
+#define HSMCI_ARGR_ARG_Pos 0\r
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */\r
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))\r
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */\r
+#define HSMCI_CMDR_CMDNB_Pos 0\r
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */\r
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))\r
+#define HSMCI_CMDR_RSPTYP_Pos 6\r
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */\r
+#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */\r
+#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */\r
+#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */\r
+#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */\r
+#define HSMCI_CMDR_SPCMD_Pos 8\r
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */\r
+#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */\r
+#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */\r
+#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */\r
+#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */\r
+#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */\r
+#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */\r
+#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */\r
+#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */\r
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */\r
+#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */\r
+#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */\r
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */\r
+#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */\r
+#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */\r
+#define HSMCI_CMDR_TRCMD_Pos 16\r
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */\r
+#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */\r
+#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */\r
+#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */\r
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */\r
+#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */\r
+#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */\r
+#define HSMCI_CMDR_TRTYP_Pos 19\r
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */\r
+#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */\r
+#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */\r
+#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */\r
+#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */\r
+#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */\r
+#define HSMCI_CMDR_IOSPCMD_Pos 24\r
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */\r
+#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */\r
+#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */\r
+#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */\r
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */\r
+#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */\r
+#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */\r
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */\r
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */\r
+#define HSMCI_BLKR_BCNT_Pos 0\r
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */\r
+#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */\r
+#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */\r
+#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */\r
+#define HSMCI_BLKR_BLKLEN_Pos 16\r
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */\r
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))\r
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */\r
+#define HSMCI_CSTOR_CSTOCYC_Pos 0\r
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */\r
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))\r
+#define HSMCI_CSTOR_CSTOMUL_Pos 4\r
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */\r
+#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */\r
+#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */\r
+#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */\r
+#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */\r
+#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */\r
+#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */\r
+#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */\r
+#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */\r
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */\r
+#define HSMCI_RSPR_RSP_Pos 0\r
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */\r
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */\r
+#define HSMCI_RDR_DATA_Pos 0\r
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */\r
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */\r
+#define HSMCI_TDR_DATA_Pos 0\r
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */\r
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))\r
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */\r
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */\r
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */\r
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */\r
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */\r
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */\r
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */\r
+#define HSMCI_SR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_SR) */\r
+#define HSMCI_SR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_SR) */\r
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */\r
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */\r
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */\r
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */\r
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */\r
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */\r
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */\r
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */\r
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */\r
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */\r
+#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */\r
+#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */\r
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */\r
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */\r
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */\r
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */\r
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */\r
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */\r
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */\r
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */\r
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */\r
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */\r
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */\r
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */\r
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */\r
+#define HSMCI_IER_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IER) */\r
+#define HSMCI_IER_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IER) */\r
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */\r
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */\r
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */\r
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */\r
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */\r
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */\r
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */\r
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */\r
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */\r
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */\r
+#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */\r
+#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */\r
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */\r
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */\r
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */\r
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */\r
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */\r
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */\r
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */\r
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */\r
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */\r
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */\r
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */\r
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */\r
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */\r
+#define HSMCI_IDR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IDR) */\r
+#define HSMCI_IDR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IDR) */\r
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */\r
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */\r
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */\r
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */\r
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */\r
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */\r
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */\r
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */\r
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */\r
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */\r
+#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */\r
+#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */\r
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */\r
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */\r
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */\r
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */\r
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */\r
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */\r
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */\r
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */\r
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */\r
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */\r
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */\r
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */\r
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */\r
+#define HSMCI_IMR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IMR) */\r
+#define HSMCI_IMR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IMR) */\r
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */\r
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */\r
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */\r
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */\r
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */\r
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */\r
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */\r
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */\r
+#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */\r
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */\r
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */\r
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */\r
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */\r
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */\r
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */\r
+/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */\r
+#define HSMCI_DMA_OFFSET_Pos 0\r
+#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */\r
+#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos)))\r
+#define HSMCI_DMA_CHKSIZE (0x1u << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */\r
+#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */\r
+#define HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */\r
+#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */\r
+#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */\r
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */\r
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */\r
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */\r
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */\r
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */\r
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */\r
+#define HSMCI_WPMR_WP_KEY_Pos 8\r
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */\r
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))\r
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define HSMCI_WPSR_WP_VS_Pos 0\r
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */\r
+#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */\r
+#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */\r
+#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */\r
+#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */\r
+#define HSMCI_WPSR_WP_VSRC_Pos 8\r
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */\r
+/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */\r
+#define HSMCI_FIFO_DATA_Pos 0\r
+#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */\r
+#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_HSMCI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_MATRIX_COMPONENT_\r
+#define _SAM3XA_MATRIX_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_MATRIX AHB Bus Matrix */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Matrix hardware registers */\r
+typedef struct {\r
+ RwReg MATRIX_MCFG[6]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */\r
+ RoReg Reserved1[10];\r
+ RwReg MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */\r
+ RoReg Reserved2[7];\r
+ RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */\r
+ RoReg Reserved3[1];\r
+ RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */\r
+ RoReg Reserved4[1];\r
+ RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */\r
+ RoReg Reserved5[1];\r
+ RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */\r
+ RoReg Reserved6[1];\r
+ RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */\r
+ RoReg Reserved7[1];\r
+ RwReg MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */\r
+ RoReg Reserved8[1];\r
+ RwReg MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */\r
+ RoReg Reserved9[1];\r
+ RwReg MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */\r
+ RoReg Reserved10[1];\r
+ RwReg MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */\r
+ RoReg Reserved11[1];\r
+ RoReg Reserved12[14];\r
+ RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */\r
+ RoReg Reserved13[4];\r
+ RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */\r
+ RoReg Reserved14[51];\r
+ RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */\r
+ RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */\r
+} Matrix;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- MATRIX_MCFG[6] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */\r
+#define MATRIX_MCFG_ULBT_Pos 0\r
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[6]) Undefined Length Burst Type */\r
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))\r
+/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */\r
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Number of Allowed Cycles for a Burst */\r
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */\r
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */\r
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))\r
+#define MATRIX_SCFG_ARBT_Pos 24\r
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[9]) Arbitration Type */\r
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))\r
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */\r
+#define MATRIX_PRAS0_M0PR_Pos 0\r
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */\r
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))\r
+#define MATRIX_PRAS0_M1PR_Pos 4\r
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */\r
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))\r
+#define MATRIX_PRAS0_M2PR_Pos 8\r
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */\r
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))\r
+#define MATRIX_PRAS0_M3PR_Pos 12\r
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */\r
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))\r
+#define MATRIX_PRAS0_M4PR_Pos 16\r
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */\r
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))\r
+#define MATRIX_PRAS0_M5PR_Pos 20\r
+#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */\r
+#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos)))\r
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */\r
+#define MATRIX_PRAS1_M0PR_Pos 0\r
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */\r
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))\r
+#define MATRIX_PRAS1_M1PR_Pos 4\r
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */\r
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))\r
+#define MATRIX_PRAS1_M2PR_Pos 8\r
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */\r
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))\r
+#define MATRIX_PRAS1_M3PR_Pos 12\r
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */\r
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))\r
+#define MATRIX_PRAS1_M4PR_Pos 16\r
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */\r
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))\r
+#define MATRIX_PRAS1_M5PR_Pos 20\r
+#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */\r
+#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos)))\r
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */\r
+#define MATRIX_PRAS2_M0PR_Pos 0\r
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */\r
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))\r
+#define MATRIX_PRAS2_M1PR_Pos 4\r
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */\r
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))\r
+#define MATRIX_PRAS2_M2PR_Pos 8\r
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */\r
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))\r
+#define MATRIX_PRAS2_M3PR_Pos 12\r
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */\r
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))\r
+#define MATRIX_PRAS2_M4PR_Pos 16\r
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */\r
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))\r
+#define MATRIX_PRAS2_M5PR_Pos 20\r
+#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */\r
+#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos)))\r
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */\r
+#define MATRIX_PRAS3_M0PR_Pos 0\r
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */\r
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))\r
+#define MATRIX_PRAS3_M1PR_Pos 4\r
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */\r
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))\r
+#define MATRIX_PRAS3_M2PR_Pos 8\r
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */\r
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))\r
+#define MATRIX_PRAS3_M3PR_Pos 12\r
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */\r
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))\r
+#define MATRIX_PRAS3_M4PR_Pos 16\r
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */\r
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))\r
+#define MATRIX_PRAS3_M5PR_Pos 20\r
+#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */\r
+#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos)))\r
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */\r
+#define MATRIX_PRAS4_M0PR_Pos 0\r
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */\r
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))\r
+#define MATRIX_PRAS4_M1PR_Pos 4\r
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */\r
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))\r
+#define MATRIX_PRAS4_M2PR_Pos 8\r
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */\r
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))\r
+#define MATRIX_PRAS4_M3PR_Pos 12\r
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */\r
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))\r
+#define MATRIX_PRAS4_M4PR_Pos 16\r
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */\r
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))\r
+#define MATRIX_PRAS4_M5PR_Pos 20\r
+#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */\r
+#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos)))\r
+/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */\r
+#define MATRIX_PRAS5_M0PR_Pos 0\r
+#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */\r
+#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))\r
+#define MATRIX_PRAS5_M1PR_Pos 4\r
+#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */\r
+#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))\r
+#define MATRIX_PRAS5_M2PR_Pos 8\r
+#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */\r
+#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))\r
+#define MATRIX_PRAS5_M3PR_Pos 12\r
+#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */\r
+#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))\r
+#define MATRIX_PRAS5_M4PR_Pos 16\r
+#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */\r
+#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))\r
+#define MATRIX_PRAS5_M5PR_Pos 20\r
+#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */\r
+#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos)))\r
+/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */\r
+#define MATRIX_PRAS6_M0PR_Pos 0\r
+#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */\r
+#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))\r
+#define MATRIX_PRAS6_M1PR_Pos 4\r
+#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */\r
+#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))\r
+#define MATRIX_PRAS6_M2PR_Pos 8\r
+#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */\r
+#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))\r
+#define MATRIX_PRAS6_M3PR_Pos 12\r
+#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */\r
+#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))\r
+#define MATRIX_PRAS6_M4PR_Pos 16\r
+#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */\r
+#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))\r
+#define MATRIX_PRAS6_M5PR_Pos 20\r
+#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) /**< \brief (MATRIX_PRAS6) Master 5 Priority */\r
+#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos)))\r
+/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */\r
+#define MATRIX_PRAS7_M0PR_Pos 0\r
+#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */\r
+#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))\r
+#define MATRIX_PRAS7_M1PR_Pos 4\r
+#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */\r
+#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))\r
+#define MATRIX_PRAS7_M2PR_Pos 8\r
+#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */\r
+#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))\r
+#define MATRIX_PRAS7_M3PR_Pos 12\r
+#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */\r
+#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))\r
+#define MATRIX_PRAS7_M4PR_Pos 16\r
+#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */\r
+#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))\r
+#define MATRIX_PRAS7_M5PR_Pos 20\r
+#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) /**< \brief (MATRIX_PRAS7) Master 5 Priority */\r
+#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos)))\r
+/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */\r
+#define MATRIX_PRAS8_M0PR_Pos 0\r
+#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */\r
+#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))\r
+#define MATRIX_PRAS8_M1PR_Pos 4\r
+#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */\r
+#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))\r
+#define MATRIX_PRAS8_M2PR_Pos 8\r
+#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */\r
+#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))\r
+#define MATRIX_PRAS8_M3PR_Pos 12\r
+#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */\r
+#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))\r
+#define MATRIX_PRAS8_M4PR_Pos 16\r
+#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */\r
+#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))\r
+#define MATRIX_PRAS8_M5PR_Pos 20\r
+#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) /**< \brief (MATRIX_PRAS8) Master 5 Priority */\r
+#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos)))\r
+/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */\r
+#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */\r
+#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */\r
+#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */\r
+#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */\r
+#define MATRIX_MRCR_RCB4_Pos 4\r
+#define MATRIX_MRCR_RCB4_Msk (0x3u << MATRIX_MRCR_RCB4_Pos) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */\r
+#define MATRIX_MRCR_RCB4(value) ((MATRIX_MRCR_RCB4_Msk & ((value) << MATRIX_MRCR_RCB4_Pos)))\r
+#define MATRIX_MRCR_RCB5 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 5 */\r
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */\r
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PC0 or ERASE Assignment */\r
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */\r
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */\r
+#define MATRIX_WPMR_WPKEY_Pos 8\r
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */\r
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))\r
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */\r
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */\r
+#define MATRIX_WPSR_WPVSRC_Pos 8\r
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_MATRIX_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PDC_COMPONENT_\r
+#define _SAM3XA_PDC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_PDC Peripheral DMA Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pdc hardware registers */\r
+typedef struct {\r
+ RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */\r
+ RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */\r
+ RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */\r
+ RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */\r
+ RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */\r
+ RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */\r
+ RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */\r
+ RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */\r
+ WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */\r
+ RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */\r
+} Pdc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */\r
+#define PERIPH_RPR_RXPTR_Pos 0\r
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */\r
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))\r
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */\r
+#define PERIPH_RCR_RXCTR_Pos 0\r
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */\r
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))\r
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */\r
+#define PERIPH_TPR_TXPTR_Pos 0\r
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */\r
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))\r
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */\r
+#define PERIPH_TCR_TXCTR_Pos 0\r
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */\r
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))\r
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */\r
+#define PERIPH_RNPR_RXNPTR_Pos 0\r
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */\r
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))\r
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */\r
+#define PERIPH_RNCR_RXNCTR_Pos 0\r
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */\r
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))\r
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */\r
+#define PERIPH_TNPR_TXNPTR_Pos 0\r
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */\r
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))\r
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */\r
+#define PERIPH_TNCR_TXNCTR_Pos 0\r
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */\r
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))\r
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */\r
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */\r
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */\r
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */\r
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */\r
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */\r
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */\r
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_PDC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PIO_COMPONENT_\r
+#define _SAM3XA_PIO_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_PIO Parallel Input/Output Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pio hardware registers */\r
+typedef struct {\r
+ WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */\r
+ WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */\r
+ RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */\r
+ RoReg Reserved1[1];\r
+ WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */\r
+ WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */\r
+ RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */\r
+ RoReg Reserved2[1];\r
+ WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */\r
+ WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */\r
+ RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */\r
+ RoReg Reserved3[1];\r
+ WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */\r
+ WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */\r
+ RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */\r
+ RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */\r
+ WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */\r
+ WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */\r
+ RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */\r
+ RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */\r
+ WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */\r
+ WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */\r
+ RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */\r
+ RoReg Reserved4[1];\r
+ WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */\r
+ WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */\r
+ RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */\r
+ RoReg Reserved5[1];\r
+ RwReg PIO_ABSR; /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */\r
+ RoReg Reserved6[3];\r
+ WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */\r
+ WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */\r
+ RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+ RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */\r
+ RoReg Reserved7[4];\r
+ WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */\r
+ WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */\r
+ RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */\r
+ RoReg Reserved8[1];\r
+ WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */\r
+ WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */\r
+ RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */\r
+ RoReg Reserved9[1];\r
+ WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */\r
+ WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */\r
+ RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */\r
+ RoReg Reserved10[1];\r
+ WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */\r
+ WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */\r
+ RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */\r
+ RoReg Reserved11[1];\r
+ RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */\r
+ RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */\r
+ RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */\r
+} Pio;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */\r
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */\r
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */\r
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */\r
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */\r
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */\r
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */\r
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */\r
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */\r
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */\r
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */\r
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */\r
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */\r
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */\r
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */\r
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */\r
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */\r
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */\r
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */\r
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */\r
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */\r
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */\r
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */\r
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */\r
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */\r
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */\r
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */\r
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */\r
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */\r
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */\r
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */\r
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */\r
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */\r
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */\r
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */\r
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+/* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */\r
+#define PIO_ABSR_P0 (0x1u << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P1 (0x1u << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P2 (0x1u << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P3 (0x1u << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P4 (0x1u << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P5 (0x1u << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P6 (0x1u << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P7 (0x1u << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P8 (0x1u << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P9 (0x1u << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P10 (0x1u << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P11 (0x1u << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P12 (0x1u << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P13 (0x1u << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P14 (0x1u << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P15 (0x1u << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P16 (0x1u << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P17 (0x1u << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P18 (0x1u << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P19 (0x1u << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P20 (0x1u << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P21 (0x1u << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P22 (0x1u << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P23 (0x1u << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P24 (0x1u << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P25 (0x1u << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P26 (0x1u << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P27 (0x1u << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P28 (0x1u << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P29 (0x1u << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P30 (0x1u << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+#define PIO_ABSR_P31 (0x1u << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */\r
+/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */\r
+#define PIO_SCIFSR_P0 (0x1u << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P1 (0x1u << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P2 (0x1u << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P3 (0x1u << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P4 (0x1u << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P5 (0x1u << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P6 (0x1u << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P7 (0x1u << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P8 (0x1u << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P9 (0x1u << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P10 (0x1u << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P11 (0x1u << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P12 (0x1u << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P13 (0x1u << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P14 (0x1u << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P15 (0x1u << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P16 (0x1u << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P17 (0x1u << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P18 (0x1u << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P19 (0x1u << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P20 (0x1u << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P21 (0x1u << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P22 (0x1u << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P23 (0x1u << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P24 (0x1u << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P25 (0x1u << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P26 (0x1u << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P27 (0x1u << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P28 (0x1u << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P29 (0x1u << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P30 (0x1u << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+#define PIO_SCIFSR_P31 (0x1u << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */\r
+/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */\r
+#define PIO_DIFSR_P0 (0x1u << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P1 (0x1u << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P2 (0x1u << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P3 (0x1u << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P4 (0x1u << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P5 (0x1u << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P6 (0x1u << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P7 (0x1u << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P8 (0x1u << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P9 (0x1u << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P10 (0x1u << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P11 (0x1u << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P12 (0x1u << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P13 (0x1u << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P14 (0x1u << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P15 (0x1u << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P16 (0x1u << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P17 (0x1u << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P18 (0x1u << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P19 (0x1u << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P20 (0x1u << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P21 (0x1u << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P22 (0x1u << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P23 (0x1u << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P24 (0x1u << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P25 (0x1u << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P26 (0x1u << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P27 (0x1u << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P28 (0x1u << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P29 (0x1u << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P30 (0x1u << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+#define PIO_DIFSR_P31 (0x1u << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */\r
+/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */\r
+#define PIO_IFDGSR_P0 (0x1u << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P1 (0x1u << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P2 (0x1u << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P3 (0x1u << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P4 (0x1u << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P5 (0x1u << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P6 (0x1u << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P7 (0x1u << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P8 (0x1u << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P9 (0x1u << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P10 (0x1u << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P11 (0x1u << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P12 (0x1u << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P13 (0x1u << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P14 (0x1u << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P15 (0x1u << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P16 (0x1u << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P17 (0x1u << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P18 (0x1u << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P19 (0x1u << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P20 (0x1u << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P21 (0x1u << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P22 (0x1u << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P23 (0x1u << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P24 (0x1u << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P25 (0x1u << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P26 (0x1u << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P27 (0x1u << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P28 (0x1u << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P29 (0x1u << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P30 (0x1u << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFDGSR_P31 (0x1u << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */\r
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */\r
+#define PIO_SCDR_DIV_Pos 0\r
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */\r
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))\r
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */\r
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */\r
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */\r
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */\r
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */\r
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */\r
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */\r
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */\r
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */\r
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */\r
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */\r
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */\r
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */\r
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */\r
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */\r
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */\r
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */\r
+#define PIO_WPMR_WPKEY_Pos 8\r
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */\r
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))\r
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */\r
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */\r
+#define PIO_WPSR_WPVSRC_Pos 8\r
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_PIO_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PMC_COMPONENT_\r
+#define _SAM3XA_PMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Power Management Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_PMC Power Management Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pmc hardware registers */\r
+typedef struct {\r
+ WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */\r
+ WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */\r
+ RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */\r
+ RoReg Reserved1[1];\r
+ WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */\r
+ WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */\r
+ RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */\r
+ RwReg CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */\r
+ RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */\r
+ RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */\r
+ RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */\r
+ RoReg Reserved2[1];\r
+ RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */\r
+ RoReg Reserved3[1];\r
+ RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */\r
+ RoReg Reserved4[1];\r
+ RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */\r
+ RoReg Reserved5[5];\r
+ WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */\r
+ WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */\r
+ RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */\r
+ RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */\r
+ RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */\r
+ RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */\r
+ WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */\r
+ RoReg Reserved6[26];\r
+ RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */\r
+ RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */\r
+ RoReg Reserved7[5];\r
+ WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */\r
+ WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */\r
+ RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */\r
+ RwReg PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */\r
+} Pmc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */\r
+#define PMC_SCER_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB OTG Clock (48 MHz, USB_48M) for UTMI */\r
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */\r
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */\r
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */\r
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */\r
+#define PMC_SCDR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB OTG Clock (48 MHz, USB_48M) for UTMI */\r
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */\r
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */\r
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */\r
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */\r
+#define PMC_SCSR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB OTG Clock (48 MHz, USB_48M) Clock Status */\r
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */\r
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */\r
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */\r
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */\r
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */\r
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */\r
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */\r
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */\r
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */\r
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */\r
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */\r
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */\r
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */\r
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */\r
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */\r
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */\r
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */\r
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */\r
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */\r
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */\r
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */\r
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */\r
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */\r
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */\r
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */\r
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */\r
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */\r
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */\r
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */\r
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */\r
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */\r
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */\r
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */\r
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */\r
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */\r
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */\r
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */\r
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */\r
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */\r
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */\r
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */\r
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */\r
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */\r
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */\r
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */\r
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */\r
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */\r
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */\r
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */\r
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */\r
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */\r
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */\r
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */\r
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */\r
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */\r
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */\r
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */\r
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */\r
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */\r
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */\r
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */\r
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */\r
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */\r
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */\r
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */\r
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */\r
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */\r
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */\r
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */\r
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */\r
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */\r
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */\r
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */\r
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */\r
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */\r
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */\r
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */\r
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */\r
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */\r
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */\r
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */\r
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */\r
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */\r
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */\r
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */\r
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */\r
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */\r
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */\r
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */\r
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */\r
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */\r
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */\r
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */\r
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */\r
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */\r
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */\r
+/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */\r
+#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */\r
+#define CKGR_UCKR_UPLLCOUNT_Pos 20\r
+#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */\r
+#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))\r
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */\r
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */\r
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */\r
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */\r
+#define CKGR_MOR_MOSCRCF_Pos 4\r
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */\r
+#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */\r
+#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */\r
+#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */\r
+#define CKGR_MOR_MOSCXTST_Pos 8\r
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */\r
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))\r
+#define CKGR_MOR_KEY_Pos 16\r
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */\r
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))\r
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */\r
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */\r
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */\r
+#define CKGR_MCFR_MAINF_Pos 0\r
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */\r
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */\r
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */\r
+#define CKGR_PLLAR_DIVA_Pos 0\r
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */\r
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))\r
+#define CKGR_PLLAR_PLLACOUNT_Pos 8\r
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */\r
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))\r
+#define CKGR_PLLAR_MULA_Pos 16\r
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */\r
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))\r
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */\r
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */\r
+#define PMC_MCKR_CSS_Pos 0\r
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */\r
+#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */\r
+#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */\r
+#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */\r
+#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */\r
+#define PMC_MCKR_PRES_Pos 4\r
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */\r
+#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */\r
+#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */\r
+#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */\r
+#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */\r
+#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */\r
+#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */\r
+#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */\r
+#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */\r
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */\r
+#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) */\r
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */\r
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */\r
+#define PMC_USB_USBDIV_Pos 8\r
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */\r
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))\r
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */\r
+#define PMC_PCK_CSS_Pos 0\r
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */\r
+#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */\r
+#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */\r
+#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */\r
+#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */\r
+#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */\r
+#define PMC_PCK_PRES_Pos 4\r
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */\r
+#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */\r
+#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */\r
+#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */\r
+#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */\r
+#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */\r
+#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */\r
+#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */\r
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */\r
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */\r
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */\r
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */\r
+#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */\r
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */\r
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */\r
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */\r
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */\r
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */\r
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */\r
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */\r
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */\r
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */\r
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */\r
+#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */\r
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */\r
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */\r
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */\r
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */\r
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */\r
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */\r
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */\r
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */\r
+#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */\r
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */\r
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */\r
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */\r
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */\r
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */\r
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */\r
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */\r
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */\r
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */\r
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */\r
+#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */\r
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */\r
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */\r
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */\r
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */\r
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */\r
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */\r
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */\r
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */\r
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */\r
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */\r
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */\r
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */\r
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */\r
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */\r
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */\r
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */\r
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */\r
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */\r
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */\r
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */\r
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */\r
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */\r
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */\r
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */\r
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */\r
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */\r
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */\r
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */\r
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */\r
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */\r
+#define PMC_WPMR_WPKEY_Pos 8\r
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */\r
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))\r
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */\r
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */\r
+#define PMC_WPSR_WPVSRC_Pos 8\r
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */\r
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */\r
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */\r
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */\r
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */\r
+#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */\r
+#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */\r
+#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */\r
+#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */\r
+#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */\r
+#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */\r
+#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */\r
+#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */\r
+#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */\r
+#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */\r
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */\r
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */\r
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */\r
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */\r
+#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */\r
+#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */\r
+#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */\r
+#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */\r
+#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */\r
+#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */\r
+#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */\r
+#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */\r
+#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */\r
+#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */\r
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */\r
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */\r
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */\r
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */\r
+#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */\r
+#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */\r
+#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */\r
+#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */\r
+#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */\r
+#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */\r
+#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */\r
+#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */\r
+#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */\r
+#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */\r
+/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */\r
+#define PMC_PCR_PID_Pos 0\r
+#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */\r
+#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))\r
+#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */\r
+#define PMC_PCR_DIV_Pos 16\r
+#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */\r
+#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */\r
+#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */\r
+#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */\r
+#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_PMC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PWM_COMPONENT_\r
+#define _SAM3XA_PWM_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_PWM Pulse Width Modulation Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief PwmCh_num hardware registers */\r
+typedef struct {\r
+ RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */\r
+ RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */\r
+ RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */\r
+ RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */\r
+ RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */\r
+ RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */\r
+ RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */\r
+ RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */\r
+} PwmCh_num;\r
+/** \brief PwmCmp hardware registers */\r
+typedef struct {\r
+ RwReg PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */\r
+ RwReg PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */\r
+ RwReg PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */\r
+ RwReg PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */\r
+} PwmCmp;\r
+/** \brief Pwm hardware registers */\r
+#define PWMCMP_NUMBER 8\r
+#define PWMCH_NUM_NUMBER 8\r
+typedef struct {\r
+ RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */\r
+ WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */\r
+ WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */\r
+ RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */\r
+ WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */\r
+ WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */\r
+ RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */\r
+ RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */\r
+ RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */\r
+ RoReg Reserved1[1];\r
+ RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */\r
+ RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */\r
+ WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */\r
+ WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */\r
+ WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */\r
+ RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */\r
+ RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */\r
+ RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */\r
+ RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */\r
+ WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */\r
+ WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */\r
+ WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */\r
+ WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */\r
+ RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */\r
+ RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */\r
+ WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */\r
+ RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */\r
+ RwReg PWM_FPE1; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register 1 */\r
+ RwReg PWM_FPE2; /**< \brief (Pwm Offset: 0x70) PWM Fault Protection Enable Register 2 */\r
+ RoReg Reserved2[2];\r
+ RwReg PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */\r
+ RoReg Reserved3[11];\r
+ RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */\r
+ RoReg Reserved4[12];\r
+ WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */\r
+ RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */\r
+ RoReg Reserved5[7];\r
+ RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */\r
+ RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */\r
+ RoReg Reserved6[2];\r
+ RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */\r
+ RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */\r
+ RoReg Reserved7[2];\r
+ PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */\r
+ RoReg Reserved8[20];\r
+ PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 7 */\r
+} Pwm;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */\r
+#define PWM_CLK_DIVA_Pos 0\r
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */\r
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))\r
+#define PWM_CLK_PREA_Pos 8\r
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */\r
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))\r
+#define PWM_CLK_DIVB_Pos 16\r
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */\r
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))\r
+#define PWM_CLK_PREB_Pos 24\r
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */\r
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))\r
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */\r
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID4 (0x1u << 4) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID5 (0x1u << 5) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID6 (0x1u << 6) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID7 (0x1u << 7) /**< \brief (PWM_ENA) Channel ID */\r
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */\r
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID4 (0x1u << 4) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID5 (0x1u << 5) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID6 (0x1u << 6) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID7 (0x1u << 7) /**< \brief (PWM_DIS) Channel ID */\r
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */\r
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID4 (0x1u << 4) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID5 (0x1u << 5) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID6 (0x1u << 6) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID7 (0x1u << 7) /**< \brief (PWM_SR) Channel ID */\r
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */\r
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */\r
+#define PWM_IER1_CHID4 (0x1u << 4) /**< \brief (PWM_IER1) Counter Event on Channel 4 Interrupt Enable */\r
+#define PWM_IER1_CHID5 (0x1u << 5) /**< \brief (PWM_IER1) Counter Event on Channel 5 Interrupt Enable */\r
+#define PWM_IER1_CHID6 (0x1u << 6) /**< \brief (PWM_IER1) Counter Event on Channel 6 Interrupt Enable */\r
+#define PWM_IER1_CHID7 (0x1u << 7) /**< \brief (PWM_IER1) Counter Event on Channel 7 Interrupt Enable */\r
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */\r
+#define PWM_IER1_FCHID4 (0x1u << 20) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 4 Interrupt Enable */\r
+#define PWM_IER1_FCHID5 (0x1u << 21) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 5 Interrupt Enable */\r
+#define PWM_IER1_FCHID6 (0x1u << 22) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 6 Interrupt Enable */\r
+#define PWM_IER1_FCHID7 (0x1u << 23) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 7 Interrupt Enable */\r
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */\r
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */\r
+#define PWM_IDR1_CHID4 (0x1u << 4) /**< \brief (PWM_IDR1) Counter Event on Channel 4 Interrupt Disable */\r
+#define PWM_IDR1_CHID5 (0x1u << 5) /**< \brief (PWM_IDR1) Counter Event on Channel 5 Interrupt Disable */\r
+#define PWM_IDR1_CHID6 (0x1u << 6) /**< \brief (PWM_IDR1) Counter Event on Channel 6 Interrupt Disable */\r
+#define PWM_IDR1_CHID7 (0x1u << 7) /**< \brief (PWM_IDR1) Counter Event on Channel 7 Interrupt Disable */\r
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */\r
+#define PWM_IDR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 4 Interrupt Disable */\r
+#define PWM_IDR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 5 Interrupt Disable */\r
+#define PWM_IDR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 6 Interrupt Disable */\r
+#define PWM_IDR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 7 Interrupt Disable */\r
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */\r
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */\r
+#define PWM_IMR1_CHID4 (0x1u << 4) /**< \brief (PWM_IMR1) Counter Event on Channel 4 Interrupt Mask */\r
+#define PWM_IMR1_CHID5 (0x1u << 5) /**< \brief (PWM_IMR1) Counter Event on Channel 5 Interrupt Mask */\r
+#define PWM_IMR1_CHID6 (0x1u << 6) /**< \brief (PWM_IMR1) Counter Event on Channel 6 Interrupt Mask */\r
+#define PWM_IMR1_CHID7 (0x1u << 7) /**< \brief (PWM_IMR1) Counter Event on Channel 7 Interrupt Mask */\r
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */\r
+#define PWM_IMR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 4 Interrupt Mask */\r
+#define PWM_IMR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 5 Interrupt Mask */\r
+#define PWM_IMR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 6 Interrupt Mask */\r
+#define PWM_IMR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 7 Interrupt Mask */\r
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */\r
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */\r
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */\r
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */\r
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */\r
+#define PWM_ISR1_CHID4 (0x1u << 4) /**< \brief (PWM_ISR1) Counter Event on Channel 4 */\r
+#define PWM_ISR1_CHID5 (0x1u << 5) /**< \brief (PWM_ISR1) Counter Event on Channel 5 */\r
+#define PWM_ISR1_CHID6 (0x1u << 6) /**< \brief (PWM_ISR1) Counter Event on Channel 6 */\r
+#define PWM_ISR1_CHID7 (0x1u << 7) /**< \brief (PWM_ISR1) Counter Event on Channel 7 */\r
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */\r
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */\r
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */\r
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */\r
+#define PWM_ISR1_FCHID4 (0x1u << 20) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 4 */\r
+#define PWM_ISR1_FCHID5 (0x1u << 21) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 5 */\r
+#define PWM_ISR1_FCHID6 (0x1u << 22) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 6 */\r
+#define PWM_ISR1_FCHID7 (0x1u << 23) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 7 */\r
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */\r
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */\r
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */\r
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */\r
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */\r
+#define PWM_SCM_SYNC4 (0x1u << 4) /**< \brief (PWM_SCM) Synchronous Channel 4 */\r
+#define PWM_SCM_SYNC5 (0x1u << 5) /**< \brief (PWM_SCM) Synchronous Channel 5 */\r
+#define PWM_SCM_SYNC6 (0x1u << 6) /**< \brief (PWM_SCM) Synchronous Channel 6 */\r
+#define PWM_SCM_SYNC7 (0x1u << 7) /**< \brief (PWM_SCM) Synchronous Channel 7 */\r
+#define PWM_SCM_UPDM_Pos 16\r
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */\r
+#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */\r
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */\r
+#define PWM_SCM_PTRCS_Pos 21\r
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */\r
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))\r
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */\r
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */\r
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */\r
+#define PWM_SCUP_UPR_Pos 0\r
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */\r
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))\r
+#define PWM_SCUP_UPRCNT_Pos 4\r
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */\r
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))\r
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */\r
+#define PWM_SCUPUPD_UPRUPD_Pos 0\r
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */\r
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))\r
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */\r
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */\r
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */\r
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */\r
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */\r
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */\r
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */\r
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */\r
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */\r
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */\r
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */\r
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */\r
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */\r
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */\r
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */\r
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */\r
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */\r
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */\r
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */\r
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */\r
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */\r
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */\r
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */\r
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */\r
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */\r
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */\r
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */\r
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */\r
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */\r
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */\r
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */\r
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */\r
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */\r
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */\r
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */\r
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */\r
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */\r
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */\r
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */\r
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */\r
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */\r
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */\r
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */\r
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */\r
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */\r
+#define PWM_OOV_OOVH4 (0x1u << 4) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 4 */\r
+#define PWM_OOV_OOVH5 (0x1u << 5) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 5 */\r
+#define PWM_OOV_OOVH6 (0x1u << 6) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 6 */\r
+#define PWM_OOV_OOVH7 (0x1u << 7) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 7 */\r
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */\r
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */\r
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */\r
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */\r
+#define PWM_OOV_OOVL4 (0x1u << 20) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 4 */\r
+#define PWM_OOV_OOVL5 (0x1u << 21) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 5 */\r
+#define PWM_OOV_OOVL6 (0x1u << 22) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 6 */\r
+#define PWM_OOV_OOVL7 (0x1u << 23) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 7 */\r
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */\r
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */\r
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */\r
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */\r
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */\r
+#define PWM_OS_OSH4 (0x1u << 4) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 4 */\r
+#define PWM_OS_OSH5 (0x1u << 5) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 5 */\r
+#define PWM_OS_OSH6 (0x1u << 6) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 6 */\r
+#define PWM_OS_OSH7 (0x1u << 7) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 7 */\r
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */\r
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */\r
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */\r
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */\r
+#define PWM_OS_OSL4 (0x1u << 20) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 4 */\r
+#define PWM_OS_OSL5 (0x1u << 21) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 5 */\r
+#define PWM_OS_OSL6 (0x1u << 22) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 6 */\r
+#define PWM_OS_OSL7 (0x1u << 23) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 7 */\r
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */\r
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSS_OSSH4 (0x1u << 4) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 4 */\r
+#define PWM_OSS_OSSH5 (0x1u << 5) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 5 */\r
+#define PWM_OSS_OSSH6 (0x1u << 6) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 6 */\r
+#define PWM_OSS_OSSH7 (0x1u << 7) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 7 */\r
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */\r
+#define PWM_OSS_OSSL4 (0x1u << 20) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 4 */\r
+#define PWM_OSS_OSSL5 (0x1u << 21) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 5 */\r
+#define PWM_OSS_OSSL6 (0x1u << 22) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 6 */\r
+#define PWM_OSS_OSSL7 (0x1u << 23) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 7 */\r
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */\r
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSC_OSCH4 (0x1u << 4) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 4 */\r
+#define PWM_OSC_OSCH5 (0x1u << 5) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 5 */\r
+#define PWM_OSC_OSCH6 (0x1u << 6) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 6 */\r
+#define PWM_OSC_OSCH7 (0x1u << 7) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 7 */\r
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */\r
+#define PWM_OSC_OSCL4 (0x1u << 20) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 4 */\r
+#define PWM_OSC_OSCL5 (0x1u << 21) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 5 */\r
+#define PWM_OSC_OSCL6 (0x1u << 22) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 6 */\r
+#define PWM_OSC_OSCL7 (0x1u << 23) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 7 */\r
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */\r
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSSUPD_OSSUPH4 (0x1u << 4) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 4 */\r
+#define PWM_OSSUPD_OSSUPH5 (0x1u << 5) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 5 */\r
+#define PWM_OSSUPD_OSSUPH6 (0x1u << 6) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 6 */\r
+#define PWM_OSSUPD_OSSUPH7 (0x1u << 7) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 7 */\r
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */\r
+#define PWM_OSSUPD_OSSUPL4 (0x1u << 20) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 4 */\r
+#define PWM_OSSUPD_OSSUPL5 (0x1u << 21) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 5 */\r
+#define PWM_OSSUPD_OSSUPL6 (0x1u << 22) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 6 */\r
+#define PWM_OSSUPD_OSSUPL7 (0x1u << 23) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 7 */\r
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */\r
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSCUPD_OSCUPH4 (0x1u << 4) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 4 */\r
+#define PWM_OSCUPD_OSCUPH5 (0x1u << 5) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 5 */\r
+#define PWM_OSCUPD_OSCUPH6 (0x1u << 6) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 6 */\r
+#define PWM_OSCUPD_OSCUPH7 (0x1u << 7) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 7 */\r
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */\r
+#define PWM_OSCUPD_OSCUPL4 (0x1u << 20) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 4 */\r
+#define PWM_OSCUPD_OSCUPL5 (0x1u << 21) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 5 */\r
+#define PWM_OSCUPD_OSCUPDL6 (0x1u << 22) /**< \brief (PWM_OSCUPD) */\r
+#define PWM_OSCUPD_OSCUPL7 (0x1u << 23) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 7 */\r
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */\r
+#define PWM_FMR_FPOL_Pos 0\r
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */\r
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))\r
+#define PWM_FMR_FMOD_Pos 8\r
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */\r
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))\r
+#define PWM_FMR_FFIL_Pos 16\r
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */\r
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))\r
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */\r
+#define PWM_FSR_FIV_Pos 0\r
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */\r
+#define PWM_FSR_FS_Pos 8\r
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */\r
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */\r
+#define PWM_FCR_FCLR_Pos 0\r
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */\r
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))\r
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */\r
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */\r
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */\r
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */\r
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */\r
+#define PWM_FPV_FPVH4 (0x1u << 4) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 4 */\r
+#define PWM_FPV_FPVH5 (0x1u << 5) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 5 */\r
+#define PWM_FPV_FPVH6 (0x1u << 6) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 6 */\r
+#define PWM_FPV_FPVH7 (0x1u << 7) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 7 */\r
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */\r
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */\r
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */\r
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */\r
+#define PWM_FPV_FPVL4 (0x1u << 20) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 4 */\r
+#define PWM_FPV_FPVL5 (0x1u << 21) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 5 */\r
+#define PWM_FPV_FPVL6 (0x1u << 22) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 6 */\r
+#define PWM_FPV_FPVL7 (0x1u << 23) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 7 */\r
+/* -------- PWM_FPE1 : (PWM Offset: 0x6C) PWM Fault Protection Enable Register 1 -------- */\r
+#define PWM_FPE1_FPE0_Pos 0\r
+#define PWM_FPE1_FPE0_Msk (0xffu << PWM_FPE1_FPE0_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE1_FPE0(value) ((PWM_FPE1_FPE0_Msk & ((value) << PWM_FPE1_FPE0_Pos)))\r
+#define PWM_FPE1_FPE1_Pos 8\r
+#define PWM_FPE1_FPE1_Msk (0xffu << PWM_FPE1_FPE1_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE1_FPE1(value) ((PWM_FPE1_FPE1_Msk & ((value) << PWM_FPE1_FPE1_Pos)))\r
+#define PWM_FPE1_FPE2_Pos 16\r
+#define PWM_FPE1_FPE2_Msk (0xffu << PWM_FPE1_FPE2_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE1_FPE2(value) ((PWM_FPE1_FPE2_Msk & ((value) << PWM_FPE1_FPE2_Pos)))\r
+#define PWM_FPE1_FPE3_Pos 24\r
+#define PWM_FPE1_FPE3_Msk (0xffu << PWM_FPE1_FPE3_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE1_FPE3(value) ((PWM_FPE1_FPE3_Msk & ((value) << PWM_FPE1_FPE3_Pos)))\r
+/* -------- PWM_FPE2 : (PWM Offset: 0x70) PWM Fault Protection Enable Register 2 -------- */\r
+#define PWM_FPE2_FPE4_Pos 0\r
+#define PWM_FPE2_FPE4_Msk (0xffu << PWM_FPE2_FPE4_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE2_FPE4(value) ((PWM_FPE2_FPE4_Msk & ((value) << PWM_FPE2_FPE4_Pos)))\r
+#define PWM_FPE2_FPE5_Pos 8\r
+#define PWM_FPE2_FPE5_Msk (0xffu << PWM_FPE2_FPE5_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE2_FPE5(value) ((PWM_FPE2_FPE5_Msk & ((value) << PWM_FPE2_FPE5_Pos)))\r
+#define PWM_FPE2_FPE6_Pos 16\r
+#define PWM_FPE2_FPE6_Msk (0xffu << PWM_FPE2_FPE6_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE2_FPE6(value) ((PWM_FPE2_FPE6_Msk & ((value) << PWM_FPE2_FPE6_Pos)))\r
+#define PWM_FPE2_FPE7_Pos 24\r
+#define PWM_FPE2_FPE7_Msk (0xffu << PWM_FPE2_FPE7_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE2_FPE7(value) ((PWM_FPE2_FPE7_Msk & ((value) << PWM_FPE2_FPE7_Pos)))\r
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */\r
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */\r
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */\r
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */\r
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */\r
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */\r
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */\r
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */\r
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */\r
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */\r
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_GCEN2 (0x1u << 2) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_GCEN3 (0x1u << 3) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */\r
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */\r
+#define PWM_SMMR_DOWN2 (0x1u << 18) /**< \brief (PWM_SMMR) DOWN Count */\r
+#define PWM_SMMR_DOWN3 (0x1u << 19) /**< \brief (PWM_SMMR) DOWN Count */\r
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */\r
+#define PWM_WPCR_WPCMD_Pos 0\r
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */\r
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))\r
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */\r
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */\r
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */\r
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */\r
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */\r
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */\r
+#define PWM_WPCR_WPKEY_Pos 8\r
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */\r
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))\r
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */\r
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */\r
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPVSRC_Pos 16\r
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */\r
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */\r
+#define PWM_TPR_TXPTR_Pos 0\r
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */\r
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))\r
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */\r
+#define PWM_TCR_TXCTR_Pos 0\r
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */\r
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))\r
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define PWM_TNPR_TXNPTR_Pos 0\r
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */\r
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))\r
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define PWM_TNCR_TXNCTR_Pos 0\r
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */\r
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))\r
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */\r
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */\r
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */\r
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */\r
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */\r
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */\r
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */\r
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */\r
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */\r
+#define PWM_CMPV_CV_Pos 0\r
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */\r
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))\r
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */\r
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */\r
+#define PWM_CMPVUPD_CVUPD_Pos 0\r
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */\r
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))\r
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */\r
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */\r
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */\r
+#define PWM_CMPM_CTR_Pos 4\r
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */\r
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))\r
+#define PWM_CMPM_CPR_Pos 8\r
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */\r
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))\r
+#define PWM_CMPM_CPRCNT_Pos 12\r
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */\r
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))\r
+#define PWM_CMPM_CUPR_Pos 16\r
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */\r
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))\r
+#define PWM_CMPM_CUPRCNT_Pos 20\r
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */\r
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))\r
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */\r
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */\r
+#define PWM_CMPMUPD_CTRUPD_Pos 4\r
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */\r
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))\r
+#define PWM_CMPMUPD_CPRUPD_Pos 8\r
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */\r
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))\r
+#define PWM_CMPMUPD_CUPRUPD_Pos 16\r
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */\r
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))\r
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */\r
+#define PWM_CMR_CPRE_Pos 0\r
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */\r
+#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */\r
+#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */\r
+#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */\r
+#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */\r
+#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */\r
+#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */\r
+#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */\r
+#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */\r
+#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */\r
+#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */\r
+#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */\r
+#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */\r
+#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */\r
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */\r
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */\r
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */\r
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */\r
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */\r
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */\r
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */\r
+#define PWM_CDTY_CDTY_Pos 0\r
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */\r
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))\r
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */\r
+#define PWM_CDTYUPD_CDTYUPD_Pos 0\r
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */\r
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))\r
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */\r
+#define PWM_CPRD_CPRD_Pos 0\r
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */\r
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))\r
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */\r
+#define PWM_CPRDUPD_CPRDUPD_Pos 0\r
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */\r
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))\r
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */\r
+#define PWM_CCNT_CNT_Pos 0\r
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */\r
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */\r
+#define PWM_DT_DTH_Pos 0\r
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */\r
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))\r
+#define PWM_DT_DTL_Pos 16\r
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */\r
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))\r
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */\r
+#define PWM_DTUPD_DTHUPD_Pos 0\r
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */\r
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))\r
+#define PWM_DTUPD_DTLUPD_Pos 16\r
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */\r
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_PWM_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_RSTC_COMPONENT_\r
+#define _SAM3XA_RSTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Reset Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_RSTC Reset Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rstc hardware registers */\r
+typedef struct {\r
+ WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */\r
+ RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */\r
+ RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */\r
+} Rstc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */\r
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */\r
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */\r
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */\r
+#define RSTC_CR_KEY_Pos 24\r
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */\r
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))\r
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */\r
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */\r
+#define RSTC_SR_RSTTYP_Pos 8\r
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */\r
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */\r
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */\r
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */\r
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */\r
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */\r
+#define RSTC_MR_ERSTL_Pos 8\r
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */\r
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))\r
+#define RSTC_MR_KEY_Pos 24\r
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */\r
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_RSTC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_RTC_COMPONENT_\r
+#define _SAM3XA_RTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Real-time Clock */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_RTC Real-time Clock */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rtc hardware registers */\r
+typedef struct {\r
+ RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */\r
+ RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */\r
+ RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */\r
+ RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */\r
+ RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */\r
+ RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */\r
+ RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */\r
+ WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */\r
+ WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */\r
+ WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */\r
+ RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */\r
+ RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */\r
+ RoReg Reserved1[45];\r
+ RwReg RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */\r
+} Rtc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */\r
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */\r
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */\r
+#define RTC_CR_TIMEVSEL_Pos 8\r
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */\r
+#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */\r
+#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */\r
+#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */\r
+#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */\r
+#define RTC_CR_CALEVSEL_Pos 16\r
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */\r
+#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */\r
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */\r
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */\r
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */\r
+#define RTC_TIMR_SEC_Pos 0\r
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */\r
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))\r
+#define RTC_TIMR_MIN_Pos 8\r
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */\r
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))\r
+#define RTC_TIMR_HOUR_Pos 16\r
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */\r
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))\r
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */\r
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */\r
+#define RTC_CALR_CENT_Pos 0\r
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */\r
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))\r
+#define RTC_CALR_YEAR_Pos 8\r
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */\r
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))\r
+#define RTC_CALR_MONTH_Pos 16\r
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */\r
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))\r
+#define RTC_CALR_DAY_Pos 21\r
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */\r
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))\r
+#define RTC_CALR_DATE_Pos 24\r
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */\r
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))\r
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */\r
+#define RTC_TIMALR_SEC_Pos 0\r
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */\r
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))\r
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */\r
+#define RTC_TIMALR_MIN_Pos 8\r
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */\r
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))\r
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */\r
+#define RTC_TIMALR_HOUR_Pos 16\r
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */\r
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))\r
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */\r
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */\r
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */\r
+#define RTC_CALALR_MONTH_Pos 16\r
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */\r
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))\r
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */\r
+#define RTC_CALALR_DATE_Pos 24\r
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */\r
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))\r
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */\r
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */\r
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */\r
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */\r
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */\r
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */\r
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */\r
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */\r
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */\r
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */\r
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */\r
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */\r
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */\r
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */\r
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */\r
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */\r
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */\r
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */\r
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */\r
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */\r
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */\r
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */\r
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */\r
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */\r
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */\r
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */\r
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */\r
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */\r
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */\r
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */\r
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */\r
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */\r
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */\r
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */\r
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */\r
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */\r
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */\r
+#define RTC_WPMR_WPKEY_Pos 8\r
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) */\r
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_RTC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_RTT_COMPONENT_\r
+#define _SAM3XA_RTT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Real-time Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_RTT Real-time Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rtt hardware registers */\r
+typedef struct {\r
+ RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */\r
+ RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */\r
+ RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */\r
+ RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */\r
+} Rtt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */\r
+#define RTT_MR_RTPRES_Pos 0\r
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */\r
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))\r
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */\r
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */\r
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */\r
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */\r
+#define RTT_AR_ALMV_Pos 0\r
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */\r
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))\r
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */\r
+#define RTT_VR_CRTV_Pos 0\r
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */\r
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */\r
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */\r
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_RTT_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_SDRAMC_COMPONENT_\r
+#define _SAM3XA_SDRAMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR SDRAM Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_SDRAMC SDRAM Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Sdramc hardware registers */\r
+typedef struct {\r
+ RwReg SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */\r
+ RwReg SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */\r
+ RwReg SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */\r
+ RoReg Reserved1[1];\r
+ RwReg SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */\r
+ WoReg SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */\r
+ WoReg SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */\r
+ RoReg SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */\r
+ RoReg SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */\r
+ RwReg SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */\r
+ RwReg SDRAMC_CR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */\r
+ RwReg SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register 1 */\r
+} Sdramc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */\r
+#define SDRAMC_MR_MODE_Pos 0\r
+#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */\r
+#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */\r
+#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */\r
+#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */\r
+#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */\r
+#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */\r
+#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */\r
+#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */\r
+/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */\r
+#define SDRAMC_TR_COUNT_Pos 0\r
+#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */\r
+#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)))\r
+/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */\r
+#define SDRAMC_CR_NC_Pos 0\r
+#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */\r
+#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */\r
+#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */\r
+#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */\r
+#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */\r
+#define SDRAMC_CR_NR_Pos 2\r
+#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */\r
+#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */\r
+#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */\r
+#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */\r
+#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */\r
+#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */\r
+#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */\r
+#define SDRAMC_CR_CAS_Pos 5\r
+#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */\r
+#define SDRAMC_CR_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */\r
+#define SDRAMC_CR_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */\r
+#define SDRAMC_CR_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */\r
+#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */\r
+#define SDRAMC_CR_TWR_Pos 8\r
+#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */\r
+#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)))\r
+#define SDRAMC_CR_TRC_TRFC_Pos 12\r
+#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */\r
+#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)))\r
+#define SDRAMC_CR_TRP_Pos 16\r
+#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */\r
+#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)))\r
+#define SDRAMC_CR_TRCD_Pos 20\r
+#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */\r
+#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)))\r
+#define SDRAMC_CR_TRAS_Pos 24\r
+#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */\r
+#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)))\r
+#define SDRAMC_CR_TXSR_Pos 28\r
+#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */\r
+#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)))\r
+/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */\r
+#define SDRAMC_LPR_LPCB_Pos 0\r
+#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */\r
+#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */\r
+#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */\r
+#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */\r
+#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */\r
+#define SDRAMC_LPR_PASR_Pos 4\r
+#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */\r
+#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)))\r
+#define SDRAMC_LPR_TCSR_Pos 8\r
+#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */\r
+#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)))\r
+#define SDRAMC_LPR_DS_Pos 10\r
+#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */\r
+#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)))\r
+#define SDRAMC_LPR_TIMEOUT_Pos 12\r
+#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to define when low-power mode is enable */\r
+#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. */\r
+#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */\r
+#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */\r
+/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */\r
+#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */\r
+/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */\r
+#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */\r
+/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */\r
+#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */\r
+/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */\r
+#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status */\r
+/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */\r
+#define SDRAMC_MDR_MD_Pos 0\r
+#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */\r
+#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */\r
+#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */\r
+/* -------- SDRAMC_CR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */\r
+#define SDRAMC_CR1_NC_Pos 0\r
+#define SDRAMC_CR1_NC_Msk (0x3u << SDRAMC_CR1_NC_Pos) /**< \brief (SDRAMC_CR1) Number of Column Bits */\r
+#define SDRAMC_CR1_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR1) 8 column bits */\r
+#define SDRAMC_CR1_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR1) 9 column bits */\r
+#define SDRAMC_CR1_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR1) 10 column bits */\r
+#define SDRAMC_CR1_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR1) 11 column bits */\r
+#define SDRAMC_CR1_NR_Pos 2\r
+#define SDRAMC_CR1_NR_Msk (0x3u << SDRAMC_CR1_NR_Pos) /**< \brief (SDRAMC_CR1) Number of Row Bits */\r
+#define SDRAMC_CR1_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR1) 11 row bits */\r
+#define SDRAMC_CR1_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR1) 12 row bits */\r
+#define SDRAMC_CR1_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR1) 13 row bits */\r
+#define SDRAMC_CR1_NB (0x1u << 4) /**< \brief (SDRAMC_CR1) Number of Banks */\r
+#define SDRAMC_CR1_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR1) 2 banks */\r
+#define SDRAMC_CR1_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR1) 4 banks */\r
+#define SDRAMC_CR1_CAS_Pos 5\r
+#define SDRAMC_CR1_CAS_Msk (0x3u << SDRAMC_CR1_CAS_Pos) /**< \brief (SDRAMC_CR1) CAS Latency */\r
+#define SDRAMC_CR1_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR1) 1 cycle CAS latency */\r
+#define SDRAMC_CR1_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR1) 2 cycle CAS latency */\r
+#define SDRAMC_CR1_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR1) 3 cycle CAS latency */\r
+#define SDRAMC_CR1_DBW (0x1u << 7) /**< \brief (SDRAMC_CR1) Data Bus Width */\r
+#define SDRAMC_CR1_TWR_Pos 8\r
+#define SDRAMC_CR1_TWR_Msk (0xfu << SDRAMC_CR1_TWR_Pos) /**< \brief (SDRAMC_CR1) Write Recovery Delay */\r
+#define SDRAMC_CR1_TWR(value) ((SDRAMC_CR1_TWR_Msk & ((value) << SDRAMC_CR1_TWR_Pos)))\r
+#define SDRAMC_CR1_TRC_TRFC_Pos 12\r
+#define SDRAMC_CR1_TRC_TRFC_Msk (0xfu << SDRAMC_CR1_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR1) Row Cycle Delay and Row Refresh Cycle */\r
+#define SDRAMC_CR1_TRC_TRFC(value) ((SDRAMC_CR1_TRC_TRFC_Msk & ((value) << SDRAMC_CR1_TRC_TRFC_Pos)))\r
+#define SDRAMC_CR1_TRP_Pos 16\r
+#define SDRAMC_CR1_TRP_Msk (0xfu << SDRAMC_CR1_TRP_Pos) /**< \brief (SDRAMC_CR1) Row Precharge Delay */\r
+#define SDRAMC_CR1_TRP(value) ((SDRAMC_CR1_TRP_Msk & ((value) << SDRAMC_CR1_TRP_Pos)))\r
+#define SDRAMC_CR1_TRCD_Pos 20\r
+#define SDRAMC_CR1_TRCD_Msk (0xfu << SDRAMC_CR1_TRCD_Pos) /**< \brief (SDRAMC_CR1) Row to Column Delay */\r
+#define SDRAMC_CR1_TRCD(value) ((SDRAMC_CR1_TRCD_Msk & ((value) << SDRAMC_CR1_TRCD_Pos)))\r
+#define SDRAMC_CR1_TRAS_Pos 24\r
+#define SDRAMC_CR1_TRAS_Msk (0xfu << SDRAMC_CR1_TRAS_Pos) /**< \brief (SDRAMC_CR1) Active to Precharge Delay */\r
+#define SDRAMC_CR1_TRAS(value) ((SDRAMC_CR1_TRAS_Msk & ((value) << SDRAMC_CR1_TRAS_Pos)))\r
+#define SDRAMC_CR1_TXSR_Pos 28\r
+#define SDRAMC_CR1_TXSR_Msk (0xfu << SDRAMC_CR1_TXSR_Pos) /**< \brief (SDRAMC_CR1) Exit Self Refresh to Active Delay */\r
+#define SDRAMC_CR1_TXSR(value) ((SDRAMC_CR1_TXSR_Msk & ((value) << SDRAMC_CR1_TXSR_Pos)))\r
+/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register 1 -------- */\r
+#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_SDRAMC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_SMC_COMPONENT_\r
+#define _SAM3XA_SMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Static Memory Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_SMC Static Memory Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief SmcCs_number hardware registers */\r
+typedef struct {\r
+ RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */\r
+ RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */\r
+ RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */\r
+ RwReg SMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */\r
+ RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */\r
+} SmcCs_number;\r
+/** \brief Smc hardware registers */\r
+#define SMCCS_NUMBER_NUMBER 8\r
+typedef struct {\r
+ RwReg SMC_CFG; /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */\r
+ WoReg SMC_CTRL; /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */\r
+ RoReg SMC_SR; /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */\r
+ WoReg SMC_IER; /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */\r
+ WoReg SMC_IDR; /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */\r
+ RoReg SMC_IMR; /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */\r
+ RwReg SMC_ADDR; /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */\r
+ RwReg SMC_BANK; /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */\r
+ WoReg SMC_ECC_CTRL; /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */\r
+ RwReg SMC_ECC_MD; /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */\r
+ RoReg SMC_ECC_SR1; /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */\r
+ RoReg SMC_ECC_PR0; /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */\r
+ RoReg SMC_ECC_PR1; /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */\r
+ RoReg SMC_ECC_SR2; /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */\r
+ RoReg SMC_ECC_PR2; /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */\r
+ RoReg SMC_ECC_PR3; /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */\r
+ RoReg SMC_ECC_PR4; /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */\r
+ RoReg SMC_ECC_PR5; /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */\r
+ RoReg SMC_ECC_PR6; /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */\r
+ RoReg SMC_ECC_PR7; /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */\r
+ RoReg SMC_ECC_PR8; /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */\r
+ RoReg SMC_ECC_PR9; /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */\r
+ RoReg SMC_ECC_PR10; /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */\r
+ RoReg SMC_ECC_PR11; /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */\r
+ RoReg SMC_ECC_PR12; /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */\r
+ RoReg SMC_ECC_PR13; /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */\r
+ RoReg SMC_ECC_PR14; /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */\r
+ RoReg SMC_ECC_PR15; /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */\r
+ SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 7 */\r
+ RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x110) SMC OCMS Register */\r
+ WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x114) SMC OCMS KEY1 Register */\r
+ WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x118) SMC OCMS KEY2 Register */\r
+ RoReg Reserved1[50];\r
+ WoReg SMC_WPCR; /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */\r
+ RoReg SMC_WPSR; /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */\r
+} Smc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */\r
+#define SMC_CFG_PAGESIZE_Pos 0\r
+#define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG) */\r
+#define SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */\r
+#define SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */\r
+#define SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */\r
+#define SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */\r
+#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */\r
+#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */\r
+#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */\r
+#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */\r
+#define SMC_CFG_DTOCYC_Pos 16\r
+#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */\r
+#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos)))\r
+#define SMC_CFG_DTOMUL_Pos 20\r
+#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */\r
+#define SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */\r
+#define SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */\r
+#define SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */\r
+#define SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */\r
+#define SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */\r
+#define SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */\r
+#define SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */\r
+#define SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */\r
+/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */\r
+#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */\r
+#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */\r
+/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */\r
+#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */\r
+#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */\r
+#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */\r
+#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */\r
+#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */\r
+#define SMC_SR_NFCSID_Pos 12\r
+#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */\r
+#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */\r
+#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */\r
+#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */\r
+#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */\r
+#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */\r
+#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */\r
+#define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */\r
+/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */\r
+#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */\r
+#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */\r
+#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */\r
+#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */\r
+#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */\r
+#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */\r
+#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */\r
+#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */\r
+#define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */\r
+/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */\r
+#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */\r
+#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */\r
+#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */\r
+#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */\r
+#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */\r
+#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */\r
+#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */\r
+#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */\r
+#define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */\r
+/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */\r
+#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */\r
+#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */\r
+#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */\r
+#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */\r
+#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */\r
+#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */\r
+#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */\r
+#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */\r
+#define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */\r
+/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */\r
+#define SMC_ADDR_ADDR_CYCLE0_Pos 0\r
+#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */\r
+#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos)))\r
+/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */\r
+#define SMC_BANK_BANK_Pos 0\r
+#define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) /**< \brief (SMC_BANK) Bank Identifier */\r
+#define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos)))\r
+/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */\r
+#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */\r
+#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */\r
+/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */\r
+#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0\r
+#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */\r
+#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */\r
+#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */\r
+#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */\r
+#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */\r
+#define SMC_ECC_MD_TYPCORREC_Pos 4\r
+#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */\r
+#define SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash) */\r
+#define SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */\r
+#define SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */\r
+/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */\r
+#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */\r
+#define SMC_ECC_SR1_ECCERR0_Pos 1\r
+#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */\r
+#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */\r
+#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */\r
+#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */\r
+#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */\r
+#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */\r
+#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */\r
+#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */\r
+#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */\r
+#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */\r
+#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */\r
+#define SMC_ECC_SR1_ECCERR4_Pos 17\r
+#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */\r
+#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */\r
+#define SMC_ECC_SR1_ECCERR5_Pos 21\r
+#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */\r
+#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */\r
+#define SMC_ECC_SR1_ECCERR6_Pos 25\r
+#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */\r
+#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */\r
+#define SMC_ECC_SR1_ECCERR7_Pos 29\r
+#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */\r
+/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */\r
+#define SMC_ECC_PR0_BITADDR_Pos 0\r
+#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */\r
+#define SMC_ECC_PR0_WORDADDR_Pos 4\r
+#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */\r
+#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0\r
+#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3\r
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR0_NPARITY_Pos 12\r
+#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */\r
+#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0\r
+#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3\r
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12\r
+#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */\r
+/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */\r
+#define SMC_ECC_PR1_NPARITY_Pos 0\r
+#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */\r
+#define SMC_ECC_PR1_BITADDR_Pos 0\r
+#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR1_WORDADDR_Pos 3\r
+#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12\r
+#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */\r
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3\r
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12\r
+#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */\r
+/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */\r
+#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */\r
+#define SMC_ECC_SR2_ECCERR8_Pos 1\r
+#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */\r
+#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */\r
+#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */\r
+#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */\r
+#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */\r
+#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */\r
+#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */\r
+#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */\r
+#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */\r
+#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */\r
+#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */\r
+#define SMC_ECC_SR2_ECCERR12_Pos 17\r
+#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */\r
+#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */\r
+#define SMC_ECC_SR2_ECCERR13_Pos 21\r
+#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */\r
+#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */\r
+#define SMC_ECC_SR2_ECCERR14_Pos 25\r
+#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */\r
+#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */\r
+#define SMC_ECC_SR2_ECCERR15_Pos 29\r
+#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */\r
+/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */\r
+#define SMC_ECC_PR2_BITADDR_Pos 0\r
+#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR2_WORDADDR_Pos 3\r
+#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR2_NPARITY_Pos 12\r
+#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */\r
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3\r
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12\r
+#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */\r
+/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */\r
+#define SMC_ECC_PR3_BITADDR_Pos 0\r
+#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR3_WORDADDR_Pos 3\r
+#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR3_NPARITY_Pos 12\r
+#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */\r
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3\r
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12\r
+#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */\r
+/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */\r
+#define SMC_ECC_PR4_BITADDR_Pos 0\r
+#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR4_WORDADDR_Pos 3\r
+#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR4_NPARITY_Pos 12\r
+#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */\r
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3\r
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12\r
+#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */\r
+/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */\r
+#define SMC_ECC_PR5_BITADDR_Pos 0\r
+#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR5_WORDADDR_Pos 3\r
+#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR5_NPARITY_Pos 12\r
+#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */\r
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3\r
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12\r
+#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */\r
+/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */\r
+#define SMC_ECC_PR6_BITADDR_Pos 0\r
+#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR6_WORDADDR_Pos 3\r
+#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR6_NPARITY_Pos 12\r
+#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */\r
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3\r
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12\r
+#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */\r
+/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */\r
+#define SMC_ECC_PR7_BITADDR_Pos 0\r
+#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR7_WORDADDR_Pos 3\r
+#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR7_NPARITY_Pos 12\r
+#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */\r
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3\r
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12\r
+#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */\r
+/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */\r
+#define SMC_ECC_PR8_BITADDR_Pos 0\r
+#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR8_WORDADDR_Pos 3\r
+#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR8_NPARITY_Pos 12\r
+#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */\r
+/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */\r
+#define SMC_ECC_PR9_BITADDR_Pos 0\r
+#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR9_WORDADDR_Pos 3\r
+#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR9_NPARITY_Pos 12\r
+#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */\r
+/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */\r
+#define SMC_ECC_PR10_BITADDR_Pos 0\r
+#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR10_WORDADDR_Pos 3\r
+#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR10_NPARITY_Pos 12\r
+#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */\r
+/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */\r
+#define SMC_ECC_PR11_BITADDR_Pos 0\r
+#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR11_WORDADDR_Pos 3\r
+#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR11_NPARITY_Pos 12\r
+#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */\r
+/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */\r
+#define SMC_ECC_PR12_BITADDR_Pos 0\r
+#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR12_WORDADDR_Pos 3\r
+#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR12_NPARITY_Pos 12\r
+#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */\r
+/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */\r
+#define SMC_ECC_PR13_BITADDR_Pos 0\r
+#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR13_WORDADDR_Pos 3\r
+#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR13_NPARITY_Pos 12\r
+#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */\r
+/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */\r
+#define SMC_ECC_PR14_BITADDR_Pos 0\r
+#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR14_WORDADDR_Pos 3\r
+#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR14_NPARITY_Pos 12\r
+#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */\r
+/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */\r
+#define SMC_ECC_PR15_BITADDR_Pos 0\r
+#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR15_WORDADDR_Pos 3\r
+#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */\r
+#define SMC_ECC_PR15_NPARITY_Pos 12\r
+#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */\r
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */\r
+#define SMC_SETUP_NWE_SETUP_Pos 0\r
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */\r
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))\r
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8\r
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */\r
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))\r
+#define SMC_SETUP_NRD_SETUP_Pos 16\r
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */\r
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))\r
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24\r
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */\r
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))\r
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */\r
+#define SMC_PULSE_NWE_PULSE_Pos 0\r
+#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */\r
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))\r
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8\r
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */\r
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))\r
+#define SMC_PULSE_NRD_PULSE_Pos 16\r
+#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */\r
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))\r
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24\r
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */\r
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))\r
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */\r
+#define SMC_CYCLE_NWE_CYCLE_Pos 0\r
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */\r
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))\r
+#define SMC_CYCLE_NRD_CYCLE_Pos 16\r
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */\r
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))\r
+/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */\r
+#define SMC_TIMINGS_TCLR_Pos 0\r
+#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */\r
+#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos)))\r
+#define SMC_TIMINGS_TADL_Pos 4\r
+#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */\r
+#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos)))\r
+#define SMC_TIMINGS_TAR_Pos 8\r
+#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */\r
+#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos)))\r
+#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */\r
+#define SMC_TIMINGS_TRR_Pos 16\r
+#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */\r
+#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos)))\r
+#define SMC_TIMINGS_TWB_Pos 24\r
+#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */\r
+#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos)))\r
+#define SMC_TIMINGS_RBNSEL_Pos 28\r
+#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */\r
+#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos)))\r
+#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */\r
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */\r
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */\r
+#define SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */\r
+#define SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */\r
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */\r
+#define SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */\r
+#define SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */\r
+#define SMC_MODE_EXNW_MODE_Pos 4\r
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */\r
+#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */\r
+#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */\r
+#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */\r
+#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */\r
+#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */\r
+#define SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */\r
+#define SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */\r
+#define SMC_MODE_TDF_CYCLES_Pos 16\r
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */\r
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))\r
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */\r
+/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS Register -------- */\r
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */\r
+#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */\r
+/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC OCMS KEY1 Register -------- */\r
+#define SMC_KEY1_KEY1_Pos 0\r
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */\r
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))\r
+/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC OCMS KEY2 Register -------- */\r
+#define SMC_KEY2_KEY2_Pos 0\r
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */\r
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))\r
+/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */\r
+#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */\r
+#define SMC_WPCR_WP_KEY_Pos 8\r
+#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */\r
+#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos)))\r
+/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */\r
+#define SMC_WPSR_WP_VS_Pos 0\r
+#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */\r
+#define SMC_WPSR_WP_VSRC_Pos 8\r
+#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_SMC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_SPI_COMPONENT_\r
+#define _SAM3XA_SPI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_SPI Serial Peripheral Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Spi hardware registers */\r
+typedef struct {\r
+ WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */\r
+ RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */\r
+ RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */\r
+ WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */\r
+ RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */\r
+ WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */\r
+ WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */\r
+ RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */\r
+ RoReg Reserved1[4];\r
+ RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */\r
+ RoReg Reserved2[41];\r
+ RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */\r
+ RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */\r
+} Spi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */\r
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */\r
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */\r
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */\r
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */\r
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */\r
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */\r
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */\r
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */\r
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */\r
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */\r
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */\r
+#define SPI_MR_PCS_Pos 16\r
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */\r
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))\r
+#define SPI_MR_DLYBCS_Pos 24\r
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */\r
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))\r
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */\r
+#define SPI_RDR_RD_Pos 0\r
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_PCS_Pos 16\r
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */\r
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */\r
+#define SPI_TDR_TD_Pos 0\r
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))\r
+#define SPI_TDR_PCS_Pos 16\r
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */\r
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))\r
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */\r
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */\r
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */\r
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */\r
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */\r
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */\r
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */\r
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */\r
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */\r
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */\r
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */\r
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */\r
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */\r
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */\r
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */\r
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */\r
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */\r
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */\r
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */\r
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */\r
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */\r
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */\r
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */\r
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */\r
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */\r
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */\r
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */\r
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */\r
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */\r
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */\r
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */\r
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */\r
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */\r
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */\r
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */\r
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */\r
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */\r
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */\r
+#define SPI_CSR_BITS_Pos 4\r
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */\r
+#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */\r
+#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */\r
+#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */\r
+#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */\r
+#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */\r
+#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */\r
+#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */\r
+#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */\r
+#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */\r
+#define SPI_CSR_SCBR_Pos 8\r
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */\r
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))\r
+#define SPI_CSR_DLYBS_Pos 16\r
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */\r
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))\r
+#define SPI_CSR_DLYBCT_Pos 24\r
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */\r
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))\r
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */\r
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */\r
+#define SPI_WPMR_WPKEY_Pos 8\r
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */\r
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))\r
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define SPI_WPSR_WPVS (0x7u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */\r
+#define SPI_WPSR_WPVS_Pos 0\r
+#define SPI_WPSR_WPVS_Msk (0x1u << SPI_WPSR_WPVS_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Status */\r
+#define SPI_WPSR_WPVSRC_Pos 8\r
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_SPI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_SSC_COMPONENT_\r
+#define _SAM3XA_SSC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_SSC Synchronous Serial Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Ssc hardware registers */\r
+typedef struct {\r
+ WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */\r
+ RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */\r
+ RoReg Reserved1[2];\r
+ RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */\r
+ RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */\r
+ RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */\r
+ RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */\r
+ RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */\r
+ WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */\r
+ RoReg Reserved2[2];\r
+ RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */\r
+ RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */\r
+ RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */\r
+ RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */\r
+ RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */\r
+ WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */\r
+ WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */\r
+ RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */\r
+ RoReg Reserved3[37];\r
+ RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */\r
+} Ssc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */\r
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */\r
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */\r
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */\r
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */\r
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */\r
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */\r
+#define SSC_CMR_DIV_Pos 0\r
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */\r
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))\r
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */\r
+#define SSC_RCMR_CKS_Pos 0\r
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */\r
+#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */\r
+#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */\r
+#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */\r
+#define SSC_RCMR_CKO_Pos 2\r
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */\r
+#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */\r
+#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */\r
+#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */\r
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */\r
+#define SSC_RCMR_CKG_Pos 6\r
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */\r
+#define SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */\r
+#define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */\r
+#define SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */\r
+#define SSC_RCMR_START_Pos 8\r
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */\r
+#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */\r
+#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */\r
+#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */\r
+#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */\r
+#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */\r
+#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */\r
+#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */\r
+#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */\r
+#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */\r
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */\r
+#define SSC_RCMR_STTDLY_Pos 16\r
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */\r
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))\r
+#define SSC_RCMR_PERIOD_Pos 24\r
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */\r
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))\r
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */\r
+#define SSC_RFMR_DATLEN_Pos 0\r
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */\r
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))\r
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */\r
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */\r
+#define SSC_RFMR_DATNB_Pos 8\r
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */\r
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))\r
+#define SSC_RFMR_FSLEN_Pos 16\r
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */\r
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))\r
+#define SSC_RFMR_FSOS_Pos 20\r
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */\r
+#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */\r
+#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */\r
+#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */\r
+#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */\r
+#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */\r
+#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */\r
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */\r
+#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */\r
+#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */\r
+#define SSC_RFMR_FSLEN_EXT_Pos 28\r
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */\r
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))\r
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */\r
+#define SSC_TCMR_CKS_Pos 0\r
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */\r
+#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */\r
+#define SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */\r
+#define SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */\r
+#define SSC_TCMR_CKO_Pos 2\r
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */\r
+#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */\r
+#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */\r
+#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */\r
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */\r
+#define SSC_TCMR_CKG_Pos 6\r
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */\r
+#define SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */\r
+#define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */\r
+#define SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */\r
+#define SSC_TCMR_START_Pos 8\r
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */\r
+#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */\r
+#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */\r
+#define SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */\r
+#define SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */\r
+#define SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */\r
+#define SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */\r
+#define SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */\r
+#define SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */\r
+#define SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */\r
+#define SSC_TCMR_STTDLY_Pos 16\r
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */\r
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))\r
+#define SSC_TCMR_PERIOD_Pos 24\r
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */\r
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))\r
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */\r
+#define SSC_TFMR_DATLEN_Pos 0\r
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */\r
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))\r
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */\r
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */\r
+#define SSC_TFMR_DATNB_Pos 8\r
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */\r
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))\r
+#define SSC_TFMR_FSLEN_Pos 16\r
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */\r
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))\r
+#define SSC_TFMR_FSOS_Pos 20\r
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */\r
+#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */\r
+#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */\r
+#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */\r
+#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */\r
+#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */\r
+#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */\r
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */\r
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */\r
+#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */\r
+#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */\r
+#define SSC_TFMR_FSLEN_EXT_Pos 28\r
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */\r
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))\r
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */\r
+#define SSC_RHR_RDAT_Pos 0\r
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */\r
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */\r
+#define SSC_THR_TDAT_Pos 0\r
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */\r
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))\r
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */\r
+#define SSC_RSHR_RSDAT_Pos 0\r
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */\r
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */\r
+#define SSC_TSHR_TSDAT_Pos 0\r
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */\r
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))\r
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */\r
+#define SSC_RC0R_CP0_Pos 0\r
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */\r
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))\r
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */\r
+#define SSC_RC1R_CP1_Pos 0\r
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */\r
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))\r
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */\r
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */\r
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */\r
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */\r
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */\r
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */\r
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */\r
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */\r
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */\r
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */\r
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */\r
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */\r
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */\r
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */\r
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */\r
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */\r
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */\r
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */\r
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */\r
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */\r
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */\r
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */\r
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */\r
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */\r
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */\r
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */\r
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */\r
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */\r
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */\r
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */\r
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */\r
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */\r
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */\r
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */\r
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */\r
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */\r
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */\r
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */\r
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */\r
+#define SSC_WPMR_WPKEY_Pos 8\r
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */\r
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))\r
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */\r
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */\r
+#define SSC_WPSR_WPVSRC_Pos 8\r
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_SSC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_SUPC_COMPONENT_\r
+#define _SAM3XA_SUPC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Supply Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_SUPC Supply Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Supc hardware registers */\r
+typedef struct {\r
+ WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */\r
+ RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */\r
+ RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */\r
+ RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */\r
+ RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */\r
+ RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */\r
+} Supc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */\r
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */\r
+#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */\r
+#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */\r
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */\r
+#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */\r
+#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */\r
+#define SUPC_CR_KEY_Pos 24\r
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */\r
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))\r
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */\r
+#define SUPC_SMMR_SMTH_Pos 0\r
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */\r
+#define SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */\r
+#define SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */\r
+#define SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */\r
+#define SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */\r
+#define SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */\r
+#define SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */\r
+#define SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */\r
+#define SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */\r
+#define SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */\r
+#define SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */\r
+#define SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */\r
+#define SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */\r
+#define SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */\r
+#define SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */\r
+#define SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */\r
+#define SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */\r
+#define SUPC_SMMR_SMSMPL_Pos 8\r
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */\r
+#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */\r
+#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */\r
+#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */\r
+#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */\r
+#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */\r
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */\r
+#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */\r
+#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */\r
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */\r
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */\r
+#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */\r
+#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */\r
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */\r
+#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */\r
+#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */\r
+#define SUPC_MR_VDDIORDYONREG (0x1u << 14) /**< \brief (SUPC_MR) */\r
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */\r
+#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */\r
+#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */\r
+#define SUPC_MR_KEY_Pos 24\r
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */\r
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))\r
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */\r
+#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */\r
+#define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */\r
+#define SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */\r
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */\r
+#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */\r
+#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */\r
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */\r
+#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */\r
+#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */\r
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */\r
+#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */\r
+#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */\r
+#define SUPC_WUMR_FWUPDBC_Pos 8\r
+#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer Period */\r
+#define SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */\r
+#define SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */\r
+#define SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */\r
+#define SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */\r
+#define SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */\r
+#define SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_Pos 12\r
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */\r
+#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */\r
+#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */\r
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */\r
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */\r
+#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */\r
+#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */\r
+#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */\r
+#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */\r
+#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */\r
+#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */\r
+#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */\r
+#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */\r
+#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */\r
+#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */\r
+#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */\r
+#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */\r
+#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */\r
+#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */\r
+#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */\r
+#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */\r
+#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */\r
+#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */\r
+#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */\r
+#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */\r
+#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */\r
+#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */\r
+#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */\r
+#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */\r
+#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */\r
+#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */\r
+#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */\r
+#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */\r
+#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */\r
+#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */\r
+#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */\r
+#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */\r
+#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */\r
+#define SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */\r
+#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */\r
+#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */\r
+#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */\r
+#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */\r
+#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */\r
+#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */\r
+#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */\r
+#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */\r
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */\r
+#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */\r
+#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */\r
+#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */\r
+#define SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */\r
+#define SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */\r
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */\r
+#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */\r
+#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */\r
+#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */\r
+#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */\r
+#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */\r
+#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */\r
+#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */\r
+#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */\r
+#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */\r
+#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */\r
+#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */\r
+#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */\r
+#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */\r
+#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */\r
+#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */\r
+#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_SUPC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_TC_COMPONENT_\r
+#define _SAM3XA_TC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Timer Counter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_TC Timer Counter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief TcChannel hardware registers */\r
+typedef struct {\r
+ RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */\r
+ RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */\r
+ RwReg TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */\r
+ RoReg Reserved1[1];\r
+ RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */\r
+ RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */\r
+ RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */\r
+ RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */\r
+ RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */\r
+ RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */\r
+ RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */\r
+ RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg Reserved2[4];\r
+} TcChannel;\r
+/** \brief Tc hardware registers */\r
+#define TCCHANNEL_NUMBER 3\r
+typedef struct {\r
+ TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */\r
+ WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */\r
+ RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */\r
+ WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */\r
+ WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */\r
+ RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */\r
+ RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */\r
+ RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */\r
+ RoReg Reserved1[2];\r
+ RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */\r
+} Tc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */\r
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */\r
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */\r
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */\r
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */\r
+#define TC_CMR_TCCLKS_Pos 0\r
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */\r
+#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */\r
+#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */\r
+#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */\r
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */\r
+#define TC_CMR_BURST_Pos 4\r
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */\r
+#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */\r
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */\r
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */\r
+#define TC_CMR_ETRGEDG_Pos 8\r
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */\r
+#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */\r
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */\r
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */\r
+#define TC_CMR_LDRA_Pos 16\r
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */\r
+#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_LDRB_Pos 18\r
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */\r
+#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */\r
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */\r
+#define TC_CMR_EEVTEDG_Pos 8\r
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */\r
+#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_EEVT_Pos 10\r
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */\r
+#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */\r
+#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */\r
+#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */\r
+#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */\r
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */\r
+#define TC_CMR_WAVSEL_Pos 13\r
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */\r
+#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */\r
+#define TC_CMR_ACPA_Pos 16\r
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */\r
+#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ACPC_Pos 18\r
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */\r
+#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_AEEVT_Pos 20\r
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */\r
+#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ASWTRG_Pos 22\r
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */\r
+#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPB_Pos 24\r
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */\r
+#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPC_Pos 26\r
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */\r
+#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BEEVT_Pos 28\r
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */\r
+#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BSWTRG_Pos 30\r
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */\r
+#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */\r
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */\r
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */\r
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */\r
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */\r
+#define TC_CV_CV_Pos 0\r
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */\r
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */\r
+#define TC_RA_RA_Pos 0\r
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */\r
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))\r
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */\r
+#define TC_RB_RB_Pos 0\r
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */\r
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))\r
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */\r
+#define TC_RC_RC_Pos 0\r
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */\r
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))\r
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */\r
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */\r
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */\r
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */\r
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */\r
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */\r
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */\r
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */\r
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */\r
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */\r
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */\r
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */\r
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */\r
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */\r
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */\r
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */\r
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */\r
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */\r
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */\r
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */\r
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */\r
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */\r
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */\r
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */\r
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */\r
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */\r
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */\r
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */\r
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */\r
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */\r
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */\r
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */\r
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */\r
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */\r
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */\r
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */\r
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */\r
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */\r
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */\r
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */\r
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */\r
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */\r
+#define TC_BMR_TC0XC0S_Pos 0\r
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */\r
+#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */\r
+#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */\r
+#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */\r
+#define TC_BMR_TC1XC1S_Pos 2\r
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */\r
+#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */\r
+#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */\r
+#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */\r
+#define TC_BMR_TC2XC2S_Pos 4\r
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */\r
+#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */\r
+#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */\r
+#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */\r
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */\r
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */\r
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */\r
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */\r
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */\r
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */\r
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */\r
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */\r
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */\r
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */\r
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */\r
+#define TC_BMR_MAXFILT_Pos 20\r
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */\r
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))\r
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */\r
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */\r
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */\r
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */\r
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */\r
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */\r
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */\r
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */\r
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */\r
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */\r
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */\r
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */\r
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */\r
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */\r
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */\r
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */\r
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */\r
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */\r
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */\r
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */\r
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */\r
+#define TC_WPMR_WPKEY_Pos 8\r
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */\r
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_TC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_TRNG_COMPONENT_\r
+#define _SAM3XA_TRNG_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR True Random Number Generator */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_TRNG True Random Number Generator */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Trng hardware registers */\r
+typedef struct {\r
+ WoReg TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */\r
+ RoReg Reserved1[3];\r
+ WoReg TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */\r
+ WoReg TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */\r
+ RoReg TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */\r
+ RoReg TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */\r
+ RoReg Reserved2[12];\r
+ RoReg TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */\r
+} Trng;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */\r
+#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */\r
+#define TRNG_CR_KEY_Pos 8\r
+#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */\r
+#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))\r
+/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */\r
+#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */\r
+/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */\r
+#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */\r
+/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */\r
+#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */\r
+/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */\r
+#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */\r
+/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */\r
+#define TRNG_ODATA_ODATA_Pos 0\r
+#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_TRNG_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_TWI_COMPONENT_\r
+#define _SAM3XA_TWI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Two-wire Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_TWI Two-wire Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Twi hardware registers */\r
+typedef struct {\r
+ WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */\r
+ RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */\r
+ RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */\r
+ RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */\r
+ RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */\r
+ RoReg Reserved1[3];\r
+ RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */\r
+ WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */\r
+ WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */\r
+ RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */\r
+ WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */\r
+ RoReg Reserved2[50];\r
+ RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */\r
+ RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */\r
+ RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */\r
+ RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */\r
+ RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */\r
+ RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */\r
+ RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */\r
+} Twi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */\r
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */\r
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */\r
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */\r
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */\r
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */\r
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */\r
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */\r
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */\r
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */\r
+#define TWI_MMR_IADRSZ_Pos 8\r
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */\r
+#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */\r
+#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */\r
+#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */\r
+#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */\r
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */\r
+#define TWI_MMR_DADR_Pos 16\r
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */\r
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))\r
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */\r
+#define TWI_SMR_SADR_Pos 16\r
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */\r
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))\r
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */\r
+#define TWI_IADR_IADR_Pos 0\r
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */\r
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))\r
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */\r
+#define TWI_CWGR_CLDIV_Pos 0\r
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */\r
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))\r
+#define TWI_CWGR_CHDIV_Pos 8\r
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */\r
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))\r
+#define TWI_CWGR_CKDIV_Pos 16\r
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */\r
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))\r
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */\r
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */\r
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */\r
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */\r
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */\r
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */\r
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */\r
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */\r
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */\r
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */\r
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */\r
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */\r
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */\r
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */\r
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */\r
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */\r
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */\r
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */\r
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */\r
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */\r
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */\r
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */\r
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */\r
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */\r
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */\r
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */\r
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */\r
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */\r
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */\r
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */\r
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */\r
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */\r
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */\r
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */\r
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */\r
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */\r
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */\r
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */\r
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */\r
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */\r
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */\r
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */\r
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */\r
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */\r
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */\r
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */\r
+#define TWI_RHR_RXDATA_Pos 0\r
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */\r
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */\r
+#define TWI_THR_TXDATA_Pos 0\r
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */\r
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))\r
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */\r
+#define TWI_RPR_RXPTR_Pos 0\r
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */\r
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))\r
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */\r
+#define TWI_RCR_RXCTR_Pos 0\r
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */\r
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))\r
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */\r
+#define TWI_TPR_TXPTR_Pos 0\r
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */\r
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))\r
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */\r
+#define TWI_TCR_TXCTR_Pos 0\r
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */\r
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))\r
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define TWI_RNPR_RXNPTR_Pos 0\r
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */\r
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))\r
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */\r
+#define TWI_RNCR_RXNCTR_Pos 0\r
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */\r
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))\r
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define TWI_TNPR_TXNPTR_Pos 0\r
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */\r
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))\r
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define TWI_TNCR_TXNCTR_Pos 0\r
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */\r
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))\r
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */\r
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */\r
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */\r
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */\r
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */\r
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */\r
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */\r
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_TWI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_UART_COMPONENT_\r
+#define _SAM3XA_UART_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_UART Universal Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Uart hardware registers */\r
+typedef struct {\r
+ WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */\r
+ RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */\r
+ WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */\r
+ WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */\r
+ RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */\r
+ RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */\r
+ RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */\r
+ WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */\r
+ RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */\r
+ RoReg Reserved1[55];\r
+ RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */\r
+ RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */\r
+ RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */\r
+ RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */\r
+ RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */\r
+ RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */\r
+ RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */\r
+} Uart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */\r
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */\r
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */\r
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */\r
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */\r
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */\r
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */\r
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */\r
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */\r
+#define UART_MR_PAR_Pos 9\r
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */\r
+#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */\r
+#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */\r
+#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */\r
+#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */\r
+#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */\r
+#define UART_MR_CHMODE_Pos 14\r
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */\r
+#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */\r
+#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */\r
+#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */\r
+#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */\r
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */\r
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */\r
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */\r
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */\r
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */\r
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */\r
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */\r
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */\r
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */\r
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */\r
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */\r
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */\r
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */\r
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */\r
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */\r
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */\r
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */\r
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */\r
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */\r
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */\r
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */\r
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */\r
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */\r
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */\r
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */\r
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */\r
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */\r
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */\r
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */\r
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */\r
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */\r
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */\r
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */\r
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */\r
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */\r
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */\r
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */\r
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */\r
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */\r
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */\r
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */\r
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */\r
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */\r
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */\r
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */\r
+#define UART_RHR_RXCHR_Pos 0\r
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */\r
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */\r
+#define UART_THR_TXCHR_Pos 0\r
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */\r
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))\r
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define UART_BRGR_CD_Pos 0\r
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */\r
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))\r
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */\r
+#define UART_RPR_RXPTR_Pos 0\r
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */\r
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))\r
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */\r
+#define UART_RCR_RXCTR_Pos 0\r
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */\r
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))\r
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */\r
+#define UART_TPR_TXPTR_Pos 0\r
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */\r
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))\r
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */\r
+#define UART_TCR_TXCTR_Pos 0\r
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */\r
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))\r
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define UART_RNPR_RXNPTR_Pos 0\r
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */\r
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))\r
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */\r
+#define UART_RNCR_RXNCTR_Pos 0\r
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */\r
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))\r
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define UART_TNPR_TXNPTR_Pos 0\r
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */\r
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))\r
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define UART_TNCR_TXNCTR_Pos 0\r
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */\r
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))\r
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */\r
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */\r
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */\r
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */\r
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */\r
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */\r
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */\r
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_UART_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_UOTGHS_COMPONENT_\r
+#define _SAM3XA_UOTGHS_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR USB On-The-Go Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_UOTGHS USB On-The-Go Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief UotghsDevdma hardware registers */\r
+typedef struct {\r
+ RwReg UOTGHS_DEVDMANXTDSC; /**< \brief (UotghsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */\r
+ RwReg UOTGHS_DEVDMAADDRESS; /**< \brief (UotghsDevdma Offset: 0x4) Device DMA Channel Address Register */\r
+ RwReg UOTGHS_DEVDMACONTROL; /**< \brief (UotghsDevdma Offset: 0x8) Device DMA Channel Control Register */\r
+ RwReg UOTGHS_DEVDMASTATUS; /**< \brief (UotghsDevdma Offset: 0xC) Device DMA Channel Status Register */\r
+} UotghsDevdma;\r
+/** \brief UotghsHstdma hardware registers */\r
+typedef struct {\r
+ RwReg UOTGHS_HSTDMANXTDSC; /**< \brief (UotghsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */\r
+ RwReg UOTGHS_HSTDMAADDRESS; /**< \brief (UotghsHstdma Offset: 0x4) Host DMA Channel Address Register */\r
+ RwReg UOTGHS_HSTDMACONTROL; /**< \brief (UotghsHstdma Offset: 0x8) Host DMA Channel Control Register */\r
+ RwReg UOTGHS_HSTDMASTATUS; /**< \brief (UotghsHstdma Offset: 0xC) Host DMA Channel Status Register */\r
+} UotghsHstdma;\r
+/** \brief Uotghs hardware registers */\r
+#define UOTGHSDEVDMA_NUMBER 7\r
+#define UOTGHSHSTDMA_NUMBER 7\r
+typedef struct {\r
+ RwReg UOTGHS_DEVCTRL; /**< \brief (Uotghs Offset: 0x0000) Device General Control Register */\r
+ RoReg UOTGHS_DEVISR; /**< \brief (Uotghs Offset: 0x0004) Device Global Interrupt Status Register */\r
+ WoReg UOTGHS_DEVICR; /**< \brief (Uotghs Offset: 0x0008) Device Global Interrupt Clear Register */\r
+ WoReg UOTGHS_DEVIFR; /**< \brief (Uotghs Offset: 0x000C) Device Global Interrupt Set Register */\r
+ RoReg UOTGHS_DEVIMR; /**< \brief (Uotghs Offset: 0x0010) Device Global Interrupt Mask Register */\r
+ WoReg UOTGHS_DEVIDR; /**< \brief (Uotghs Offset: 0x0014) Device Global Interrupt Disable Register */\r
+ WoReg UOTGHS_DEVIER; /**< \brief (Uotghs Offset: 0x0018) Device Global Interrupt Enable Register */\r
+ RwReg UOTGHS_DEVEPT; /**< \brief (Uotghs Offset: 0x001C) Device Endpoint Register */\r
+ RoReg UOTGHS_DEVFNUM; /**< \brief (Uotghs Offset: 0x0020) Device Frame Number Register */\r
+ RoReg Reserved1[55];\r
+ RwReg UOTGHS_DEVEPTCFG[10]; /**< \brief (Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */\r
+ RoReg Reserved2[2];\r
+ RoReg UOTGHS_DEVEPTISR[10]; /**< \brief (Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) */\r
+ RoReg Reserved3[2];\r
+ WoReg UOTGHS_DEVEPTICR[10]; /**< \brief (Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) */\r
+ RoReg Reserved4[2];\r
+ WoReg UOTGHS_DEVEPTIFR[10]; /**< \brief (Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) */\r
+ RoReg Reserved5[2];\r
+ RoReg UOTGHS_DEVEPTIMR[10]; /**< \brief (Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */\r
+ RoReg Reserved6[2];\r
+ WoReg UOTGHS_DEVEPTIER[10]; /**< \brief (Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */\r
+ RoReg Reserved7[2];\r
+ WoReg UOTGHS_DEVEPTIDR[10]; /**< \brief (Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) */\r
+ RoReg Reserved8[50];\r
+ UotghsDevdma UOTGHS_DEVDMA[UOTGHSDEVDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x310) n = 1 .. 7 */\r
+ RoReg Reserved9[32];\r
+ RwReg UOTGHS_HSTCTRL; /**< \brief (Uotghs Offset: 0x0400) Host General Control Register */\r
+ RoReg UOTGHS_HSTISR; /**< \brief (Uotghs Offset: 0x0404) Host Global Interrupt Status Register */\r
+ WoReg UOTGHS_HSTICR; /**< \brief (Uotghs Offset: 0x0408) Host Global Interrupt Clear Register */\r
+ WoReg UOTGHS_HSTIFR; /**< \brief (Uotghs Offset: 0x040C) Host Global Interrupt Set Register */\r
+ RoReg UOTGHS_HSTIMR; /**< \brief (Uotghs Offset: 0x0410) Host Global Interrupt Mask Register */\r
+ WoReg UOTGHS_HSTIDR; /**< \brief (Uotghs Offset: 0x0414) Host Global Interrupt Disable Register */\r
+ WoReg UOTGHS_HSTIER; /**< \brief (Uotghs Offset: 0x0418) Host Global Interrupt Enable Register */\r
+ RwReg UOTGHS_HSTPIP; /**< \brief (Uotghs Offset: 0x0041C) Host Pipe Register */\r
+ RwReg UOTGHS_HSTFNUM; /**< \brief (Uotghs Offset: 0x0420) Host Frame Number Register */\r
+ RwReg UOTGHS_HSTADDR1; /**< \brief (Uotghs Offset: 0x0424) Host Address 1 Register */\r
+ RwReg UOTGHS_HSTADDR2; /**< \brief (Uotghs Offset: 0x0428) Host Address 2 Register */\r
+ RwReg UOTGHS_HSTADDR3; /**< \brief (Uotghs Offset: 0x042C) Host Address 3 Register */\r
+ RoReg Reserved10[52];\r
+ RwReg UOTGHS_HSTPIPCFG[10]; /**< \brief (Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) */\r
+ RoReg Reserved11[2];\r
+ RoReg UOTGHS_HSTPIPISR[10]; /**< \brief (Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) */\r
+ RoReg Reserved12[2];\r
+ WoReg UOTGHS_HSTPIPICR[10]; /**< \brief (Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) */\r
+ RoReg Reserved13[2];\r
+ WoReg UOTGHS_HSTPIPIFR[10]; /**< \brief (Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) */\r
+ RoReg Reserved14[2];\r
+ RoReg UOTGHS_HSTPIPIMR[10]; /**< \brief (Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */\r
+ RoReg Reserved15[2];\r
+ WoReg UOTGHS_HSTPIPIER[10]; /**< \brief (Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */\r
+ RoReg Reserved16[2];\r
+ WoReg UOTGHS_HSTPIPIDR[10]; /**< \brief (Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) */\r
+ RoReg Reserved17[2];\r
+ RwReg UOTGHS_HSTPIPINRQ[10]; /**< \brief (Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) */\r
+ RoReg Reserved18[2];\r
+ RwReg UOTGHS_HSTPIPERR[10]; /**< \brief (Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) */\r
+ RoReg Reserved19[26];\r
+ UotghsHstdma UOTGHS_HSTDMA[UOTGHSHSTDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x710) n = 1 .. 7 */\r
+ RoReg Reserved20[32];\r
+ RwReg UOTGHS_CTRL; /**< \brief (Uotghs Offset: 0x0800) General Control Register */\r
+ RoReg UOTGHS_SR; /**< \brief (Uotghs Offset: 0x0804) General Status Register */\r
+ WoReg UOTGHS_SCR; /**< \brief (Uotghs Offset: 0x0808) General Status Clear Register */\r
+ WoReg UOTGHS_SFR; /**< \brief (Uotghs Offset: 0x080C) General Status Set Register */\r
+ RoReg Reserved21[7];\r
+ RoReg UOTGHS_FSM; /**< \brief (Uotghs Offset: 0x082C) General Finite State Machine Register */\r
+} Uotghs;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UOTGHS_DEVCTRL : (UOTGHS Offset: 0x0000) Device General Control Register -------- */\r
+#define UOTGHS_DEVCTRL_UADD_Pos 0\r
+#define UOTGHS_DEVCTRL_UADD_Msk (0x7fu << UOTGHS_DEVCTRL_UADD_Pos) /**< \brief (UOTGHS_DEVCTRL) USB Address */\r
+#define UOTGHS_DEVCTRL_UADD(value) ((UOTGHS_DEVCTRL_UADD_Msk & ((value) << UOTGHS_DEVCTRL_UADD_Pos)))\r
+#define UOTGHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (UOTGHS_DEVCTRL) Address Enable */\r
+#define UOTGHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (UOTGHS_DEVCTRL) Detach */\r
+#define UOTGHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (UOTGHS_DEVCTRL) Remote Wake-Up */\r
+#define UOTGHS_DEVCTRL_SPDCONF_Pos 10\r
+#define UOTGHS_DEVCTRL_SPDCONF_Msk (0x3u << UOTGHS_DEVCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_DEVCTRL) Mode Configuration */\r
+#define UOTGHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. */\r
+#define UOTGHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (UOTGHS_DEVCTRL) For a better consumption, if high-speed is not needed. */\r
+#define UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (UOTGHS_DEVCTRL) Forced high speed. */\r
+#define UOTGHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral remains in full-speed mode whatever the host speed capability. */\r
+#define UOTGHS_DEVCTRL_LS (0x1u << 12) /**< \brief (UOTGHS_DEVCTRL) Low-Speed Mode Force */\r
+#define UOTGHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (UOTGHS_DEVCTRL) Test mode J */\r
+#define UOTGHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (UOTGHS_DEVCTRL) Test mode K */\r
+#define UOTGHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (UOTGHS_DEVCTRL) Test packet mode */\r
+#define UOTGHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (UOTGHS_DEVCTRL) Specific Operational mode */\r
+/* -------- UOTGHS_DEVISR : (UOTGHS Offset: 0x0004) Device Global Interrupt Status Register -------- */\r
+#define UOTGHS_DEVISR_SUSP (0x1u << 0) /**< \brief (UOTGHS_DEVISR) Suspend Interrupt */\r
+#define UOTGHS_DEVISR_MSOF (0x1u << 1) /**< \brief (UOTGHS_DEVISR) Micro Start of Frame Interrupt */\r
+#define UOTGHS_DEVISR_SOF (0x1u << 2) /**< \brief (UOTGHS_DEVISR) Start of Frame Interrupt */\r
+#define UOTGHS_DEVISR_EORST (0x1u << 3) /**< \brief (UOTGHS_DEVISR) End of Reset Interrupt */\r
+#define UOTGHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (UOTGHS_DEVISR) Wake-Up Interrupt */\r
+#define UOTGHS_DEVISR_EORSM (0x1u << 5) /**< \brief (UOTGHS_DEVISR) End of Resume Interrupt */\r
+#define UOTGHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (UOTGHS_DEVISR) Upstream Resume Interrupt */\r
+#define UOTGHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVISR) Endpoint 0 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVISR) Endpoint 1 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVISR) Endpoint 2 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVISR) Endpoint 3 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVISR) Endpoint 4 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVISR) Endpoint 5 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVISR) Endpoint 6 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVISR) Endpoint 7 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVISR) Endpoint 8 Interrupt */\r
+#define UOTGHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVISR) Endpoint 9 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVISR) DMA Channel 1 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVISR) DMA Channel 2 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVISR) DMA Channel 3 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVISR) DMA Channel 4 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVISR) DMA Channel 5 Interrupt */\r
+#define UOTGHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVISR) DMA Channel 6 Interrupt */\r
+/* -------- UOTGHS_DEVICR : (UOTGHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */\r
+#define UOTGHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (UOTGHS_DEVICR) Suspend Interrupt Clear */\r
+#define UOTGHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (UOTGHS_DEVICR) Micro Start of Frame Interrupt Clear */\r
+#define UOTGHS_DEVICR_SOFC (0x1u << 2) /**< \brief (UOTGHS_DEVICR) Start of Frame Interrupt Clear */\r
+#define UOTGHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (UOTGHS_DEVICR) End of Reset Interrupt Clear */\r
+#define UOTGHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (UOTGHS_DEVICR) Wake-Up Interrupt Clear */\r
+#define UOTGHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (UOTGHS_DEVICR) End of Resume Interrupt Clear */\r
+#define UOTGHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (UOTGHS_DEVICR) Upstream Resume Interrupt Clear */\r
+/* -------- UOTGHS_DEVIFR : (UOTGHS Offset: 0x000C) Device Global Interrupt Set Register -------- */\r
+#define UOTGHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (UOTGHS_DEVIFR) Suspend Interrupt Set */\r
+#define UOTGHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (UOTGHS_DEVIFR) Micro Start of Frame Interrupt Set */\r
+#define UOTGHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (UOTGHS_DEVIFR) Start of Frame Interrupt Set */\r
+#define UOTGHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (UOTGHS_DEVIFR) End of Reset Interrupt Set */\r
+#define UOTGHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (UOTGHS_DEVIFR) Wake-Up Interrupt Set */\r
+#define UOTGHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (UOTGHS_DEVIFR) End of Resume Interrupt Set */\r
+#define UOTGHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (UOTGHS_DEVIFR) Upstream Resume Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIFR) DMA Channel 1 Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIFR) DMA Channel 2 Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIFR) DMA Channel 3 Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIFR) DMA Channel 4 Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIFR) DMA Channel 5 Interrupt Set */\r
+#define UOTGHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIFR) DMA Channel 6 Interrupt Set */\r
+/* -------- UOTGHS_DEVIMR : (UOTGHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */\r
+#define UOTGHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (UOTGHS_DEVIMR) Suspend Interrupt Mask */\r
+#define UOTGHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (UOTGHS_DEVIMR) Micro Start of Frame Interrupt Mask */\r
+#define UOTGHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (UOTGHS_DEVIMR) Start of Frame Interrupt Mask */\r
+#define UOTGHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (UOTGHS_DEVIMR) End of Reset Interrupt Mask */\r
+#define UOTGHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (UOTGHS_DEVIMR) Wake-Up Interrupt Mask */\r
+#define UOTGHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (UOTGHS_DEVIMR) End of Resume Interrupt Mask */\r
+#define UOTGHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (UOTGHS_DEVIMR) Upstream Resume Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIMR) Endpoint 0 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIMR) Endpoint 1 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIMR) Endpoint 2 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIMR) Endpoint 3 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIMR) Endpoint 4 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIMR) Endpoint 5 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIMR) Endpoint 6 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIMR) Endpoint 7 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIMR) Endpoint 8 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIMR) Endpoint 9 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIMR) DMA Channel 1 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIMR) DMA Channel 2 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIMR) DMA Channel 3 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIMR) DMA Channel 4 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIMR) DMA Channel 5 Interrupt Mask */\r
+#define UOTGHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIMR) DMA Channel 6 Interrupt Mask */\r
+/* -------- UOTGHS_DEVIDR : (UOTGHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */\r
+#define UOTGHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (UOTGHS_DEVIDR) Suspend Interrupt Disable */\r
+#define UOTGHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (UOTGHS_DEVIDR) Micro Start of Frame Interrupt Disable */\r
+#define UOTGHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (UOTGHS_DEVIDR) Start of Frame Interrupt Disable */\r
+#define UOTGHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (UOTGHS_DEVIDR) End of Reset Interrupt Disable */\r
+#define UOTGHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (UOTGHS_DEVIDR) Wake-Up Interrupt Disable */\r
+#define UOTGHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (UOTGHS_DEVIDR) End of Resume Interrupt Disable */\r
+#define UOTGHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (UOTGHS_DEVIDR) Upstream Resume Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIDR) Endpoint 0 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIDR) Endpoint 1 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIDR) Endpoint 2 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIDR) Endpoint 3 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIDR) Endpoint 4 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIDR) Endpoint 5 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIDR) Endpoint 6 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIDR) Endpoint 7 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIDR) Endpoint 8 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIDR) Endpoint 9 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIDR) DMA Channel 1 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIDR) DMA Channel 2 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIDR) DMA Channel 3 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIDR) DMA Channel 4 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIDR) DMA Channel 5 Interrupt Disable */\r
+#define UOTGHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIDR) DMA Channel 6 Interrupt Disable */\r
+/* -------- UOTGHS_DEVIER : (UOTGHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */\r
+#define UOTGHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (UOTGHS_DEVIER) Suspend Interrupt Enable */\r
+#define UOTGHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (UOTGHS_DEVIER) Micro Start of Frame Interrupt Enable */\r
+#define UOTGHS_DEVIER_SOFES (0x1u << 2) /**< \brief (UOTGHS_DEVIER) Start of Frame Interrupt Enable */\r
+#define UOTGHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (UOTGHS_DEVIER) End of Reset Interrupt Enable */\r
+#define UOTGHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (UOTGHS_DEVIER) Wake-Up Interrupt Enable */\r
+#define UOTGHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (UOTGHS_DEVIER) End of Resume Interrupt Enable */\r
+#define UOTGHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (UOTGHS_DEVIER) Upstream Resume Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIER) Endpoint 0 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIER) Endpoint 1 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIER) Endpoint 2 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIER) Endpoint 3 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIER) Endpoint 4 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIER) Endpoint 5 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIER) Endpoint 6 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIER) Endpoint 7 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIER) Endpoint 8 Interrupt Enable */\r
+#define UOTGHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIER) Endpoint 9 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIER) DMA Channel 1 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIER) DMA Channel 2 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIER) DMA Channel 3 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIER) DMA Channel 4 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIER) DMA Channel 5 Interrupt Enable */\r
+#define UOTGHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIER) DMA Channel 6 Interrupt Enable */\r
+/* -------- UOTGHS_DEVEPT : (UOTGHS Offset: 0x001C) Device Endpoint Register -------- */\r
+#define UOTGHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Enable */\r
+#define UOTGHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Enable */\r
+#define UOTGHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Enable */\r
+#define UOTGHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Enable */\r
+#define UOTGHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Enable */\r
+#define UOTGHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Enable */\r
+#define UOTGHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Enable */\r
+#define UOTGHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Enable */\r
+#define UOTGHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Enable */\r
+#define UOTGHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Reset */\r
+#define UOTGHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Reset */\r
+#define UOTGHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Reset */\r
+#define UOTGHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Reset */\r
+#define UOTGHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Reset */\r
+#define UOTGHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Reset */\r
+#define UOTGHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Reset */\r
+#define UOTGHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Reset */\r
+#define UOTGHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Reset */\r
+/* -------- UOTGHS_DEVFNUM : (UOTGHS Offset: 0x0020) Device Frame Number Register -------- */\r
+#define UOTGHS_DEVFNUM_MFNUM_Pos 0\r
+#define UOTGHS_DEVFNUM_MFNUM_Msk (0x7u << UOTGHS_DEVFNUM_MFNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Micro Frame Number */\r
+#define UOTGHS_DEVFNUM_FNUM_Pos 3\r
+#define UOTGHS_DEVFNUM_FNUM_Msk (0x7ffu << UOTGHS_DEVFNUM_FNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Frame Number */\r
+#define UOTGHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (UOTGHS_DEVFNUM) Frame Number CRC Error */\r
+/* -------- UOTGHS_DEVEPTCFG[10] : (UOTGHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Memory Allocate */\r
+#define UOTGHS_DEVEPTCFG_EPBK_Pos 2\r
+#define UOTGHS_DEVEPTCFG_EPBK_Msk (0x3u << UOTGHS_DEVEPTCFG_EPBK_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Banks */\r
+#define UOTGHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Single-bank endpoint */\r
+#define UOTGHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Double-bank endpoint */\r
+#define UOTGHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Triple-bank endpoint */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_Pos 4\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_Msk (0x7u << UOTGHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Size */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 8 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 16 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 32 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 64 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 128 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 256 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 512 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 1024 bytes */\r
+#define UOTGHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Direction */\r
+#define UOTGHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is OUT. */\r
+#define UOTGHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */\r
+#define UOTGHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (UOTGHS_DEVEPTCFG[10]) Automatic Switch */\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_Pos 11\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_Msk (0x3u << UOTGHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Type */\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Control */\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Isochronous */\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Bulk */\r
+#define UOTGHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Interrupt */\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_Pos 13\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_Msk (0x3u << UOTGHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Number of transaction per microframe for isochronous endpoint */\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) reserved to endpoint that does not have the high-bandwidth isochronous capability. */\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) default value: one transaction per micro-frame. */\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 2 transactions per micro-frame. This endpoint should be configured as double-bank. */\r
+#define UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 3 transactions per micro-frame. This endpoint should be configured as triple-bank. */\r
+/* -------- UOTGHS_DEVEPTISR[10] : (UOTGHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (UOTGHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */\r
+#define UOTGHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (UOTGHS_DEVEPTISR[10]) Received OUT Data Interrupt */\r
+#define UOTGHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Received SETUP Interrupt */\r
+#define UOTGHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Underflow Interrupt */\r
+#define UOTGHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed OUT Interrupt */\r
+#define UOTGHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) High bandwidth isochronous IN Underflow Error Interrupt */\r
+#define UOTGHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed IN Interrupt */\r
+#define UOTGHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */\r
+#define UOTGHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_DEVEPTISR[10]) Overflow Interrupt */\r
+#define UOTGHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) STALLed Interrupt */\r
+#define UOTGHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) CRC Error Interrupt */\r
+#define UOTGHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (UOTGHS_DEVEPTISR[10]) Short Packet Interrupt */\r
+#define UOTGHS_DEVEPTISR_DTSEQ_Pos 8\r
+#define UOTGHS_DEVEPTISR_DTSEQ_Msk (0x3u << UOTGHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Data Toggle Sequence */\r
+#define UOTGHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data0 toggle sequence */\r
+#define UOTGHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data1 toggle sequence */\r
+#define UOTGHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data2 toggle sequence (for high-bandwidth isochronous endpoint) */\r
+#define UOTGHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) MData toggle sequence (for high-bandwidth isochronous endpoint) */\r
+#define UOTGHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (UOTGHS_DEVEPTISR[10]) High-bandwidth isochronous OUT endpoint transaction error Interrupt */\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_Pos 12\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_Msk (0x3u << UOTGHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Number of Busy Banks */\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 0 busy bank (all banks free) */\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 1 busy bank */\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 2 busy banks */\r
+#define UOTGHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 3 busy banks */\r
+#define UOTGHS_DEVEPTISR_CURRBK_Pos 14\r
+#define UOTGHS_DEVEPTISR_CURRBK_Msk (0x3u << UOTGHS_DEVEPTISR_CURRBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Current Bank */\r
+#define UOTGHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank0 */\r
+#define UOTGHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank1 */\r
+#define UOTGHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank2 */\r
+#define UOTGHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_DEVEPTISR[10]) Read-write Allowed */\r
+#define UOTGHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (UOTGHS_DEVEPTISR[10]) Control Direction */\r
+#define UOTGHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_DEVEPTISR[10]) Configuration OK Status */\r
+#define UOTGHS_DEVEPTISR_BYCT_Pos 20\r
+#define UOTGHS_DEVEPTISR_BYCT_Msk (0x7ffu << UOTGHS_DEVEPTISR_BYCT_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Byte Count */\r
+/* -------- UOTGHS_DEVEPTICR[10] : (UOTGHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Underflow Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) High bandwidth isochronous IN Underflow Error Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTICR[10]) Overflow Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) STALLed Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) CRC Error Interrupt Clear */\r
+#define UOTGHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTICR[10]) Short Packet Interrupt Clear */\r
+/* -------- UOTGHS_DEVEPTIFR[10] : (UOTGHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Underflow Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) High bandwidth isochronous IN Underflow Error Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIFR[10]) Overflow Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) STALLed Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) CRC Error Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIFR[10]) Short Packet Interrupt Set */\r
+#define UOTGHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */\r
+/* -------- UOTGHS_DEVEPTIMR[10] : (UOTGHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */\r
+#define UOTGHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received OUT Data Interrupt */\r
+#define UOTGHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received SETUP Interrupt */\r
+#define UOTGHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Underflow Interrupt */\r
+#define UOTGHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed OUT Interrupt */\r
+#define UOTGHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */\r
+#define UOTGHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed IN Interrupt */\r
+#define UOTGHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */\r
+#define UOTGHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIMR[10]) Overflow Interrupt */\r
+#define UOTGHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALLed Interrupt */\r
+#define UOTGHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) CRC Error Interrupt */\r
+#define UOTGHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIMR[10]) Short Packet Interrupt */\r
+#define UOTGHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIMR[10]) MData Interrupt */\r
+#define UOTGHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIMR[10]) DataX Interrupt */\r
+#define UOTGHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transaction Error Interrupt */\r
+#define UOTGHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */\r
+#define UOTGHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIMR[10]) Kill IN Bank */\r
+#define UOTGHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIMR[10]) FIFO Control */\r
+#define UOTGHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */\r
+#define UOTGHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIMR[10]) NYET Token Disable */\r
+#define UOTGHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIMR[10]) Reset Data Toggle */\r
+#define UOTGHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALL Request */\r
+/* -------- UOTGHS_DEVEPTIER[10] : (UOTGHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Underflow Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIER[10]) Overflow Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) STALLed Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) CRC Error Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIER[10]) Short Packet Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIER[10]) MData Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIER[10]) DataX Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */\r
+#define UOTGHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIER[10]) Kill IN Bank */\r
+#define UOTGHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */\r
+#define UOTGHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIER[10]) NYET Token Disable Enable */\r
+#define UOTGHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIER[10]) Reset Data Toggle Enable */\r
+#define UOTGHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIER[10]) STALL Request Enable */\r
+/* -------- UOTGHS_DEVEPTIDR[10] : (UOTGHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */\r
+#define UOTGHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Underflow Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIDR[10]) Overflow Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALLed Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIDR[10]) MData Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIDR[10]) DataX Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */\r
+#define UOTGHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIDR[10]) FIFO Control Clear */\r
+#define UOTGHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */\r
+#define UOTGHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIDR[10]) NYET Token Disable Clear */\r
+#define UOTGHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALL Request Clear */\r
+/* -------- UOTGHS_DEVDMANXTDSC : (UOTGHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */\r
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0\r
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_DEVDMANXTDSC) Next Descriptor Address */\r
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))\r
+/* -------- UOTGHS_DEVDMAADDRESS : (UOTGHS Offset: N/A) Device DMA Channel Address Register -------- */\r
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos 0\r
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_DEVDMAADDRESS) Buffer Address */\r
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD(value) ((UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos)))\r
+/* -------- UOTGHS_DEVDMACONTROL : (UOTGHS Offset: N/A) Device DMA Channel Control Register -------- */\r
+#define UOTGHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMACONTROL) Channel Enable Command */\r
+#define UOTGHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */\r
+#define UOTGHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Enable Control */\r
+#define UOTGHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Enable Control */\r
+#define UOTGHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Interrupt Enable */\r
+#define UOTGHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Interrupt Enable */\r
+#define UOTGHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */\r
+#define UOTGHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_DEVDMACONTROL) Burst Lock Enable */\r
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16\r
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */\r
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))\r
+/* -------- UOTGHS_DEVDMASTATUS : (UOTGHS Offset: N/A) Device DMA Channel Status Register -------- */\r
+#define UOTGHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Enable Status */\r
+#define UOTGHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Active Status */\r
+#define UOTGHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Transfer Status */\r
+#define UOTGHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Buffer Status */\r
+#define UOTGHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_DEVDMASTATUS) Descriptor Loaded Status */\r
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos 16\r
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_DEVDMASTATUS) Buffer Byte Count */\r
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT(value) ((UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos)))\r
+/* -------- UOTGHS_HSTCTRL : (UOTGHS Offset: 0x0400) Host General Control Register -------- */\r
+#define UOTGHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (UOTGHS_HSTCTRL) Start of Frame Generation Enable */\r
+#define UOTGHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (UOTGHS_HSTCTRL) Send USB Reset */\r
+#define UOTGHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (UOTGHS_HSTCTRL) Send USB Resume */\r
+#define UOTGHS_HSTCTRL_SPDCONF_Pos 12\r
+#define UOTGHS_HSTCTRL_SPDCONF_Msk (0x3u << UOTGHS_HSTCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_HSTCTRL) Mode Configuration */\r
+#define UOTGHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (UOTGHS_HSTCTRL) The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. */\r
+#define UOTGHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (UOTGHS_HSTCTRL) For a better consumption, if high-speed is not needed. */\r
+#define UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (UOTGHS_HSTCTRL) Forced high speed. */\r
+#define UOTGHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (UOTGHS_HSTCTRL) The host remains to full-speed mode whatever the peripheral speed capability. */\r
+/* -------- UOTGHS_HSTISR : (UOTGHS Offset: 0x0404) Host Global Interrupt Status Register -------- */\r
+#define UOTGHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (UOTGHS_HSTISR) Device Connection Interrupt */\r
+#define UOTGHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (UOTGHS_HSTISR) Device Disconnection Interrupt */\r
+#define UOTGHS_HSTISR_RSTI (0x1u << 2) /**< \brief (UOTGHS_HSTISR) USB Reset Sent Interrupt */\r
+#define UOTGHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (UOTGHS_HSTISR) Downstream Resume Sent Interrupt */\r
+#define UOTGHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (UOTGHS_HSTISR) Upstream Resume Received Interrupt */\r
+#define UOTGHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (UOTGHS_HSTISR) Host Start of Frame Interrupt */\r
+#define UOTGHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (UOTGHS_HSTISR) Host Wake-Up Interrupt */\r
+#define UOTGHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTISR) Pipe 0 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTISR) Pipe 1 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTISR) Pipe 2 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTISR) Pipe 3 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTISR) Pipe 4 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTISR) Pipe 5 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTISR) Pipe 6 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTISR) Pipe 7 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTISR) Pipe 8 Interrupt */\r
+#define UOTGHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTISR) Pipe 9 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTISR) DMA Channel 1 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTISR) DMA Channel 2 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTISR) DMA Channel 3 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTISR) DMA Channel 4 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTISR) DMA Channel 5 Interrupt */\r
+#define UOTGHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTISR) DMA Channel 6 Interrupt */\r
+/* -------- UOTGHS_HSTICR : (UOTGHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */\r
+#define UOTGHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (UOTGHS_HSTICR) Device Connection Interrupt Clear */\r
+#define UOTGHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (UOTGHS_HSTICR) Device Disconnection Interrupt Clear */\r
+#define UOTGHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (UOTGHS_HSTICR) USB Reset Sent Interrupt Clear */\r
+#define UOTGHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (UOTGHS_HSTICR) Downstream Resume Sent Interrupt Clear */\r
+#define UOTGHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (UOTGHS_HSTICR) Upstream Resume Received Interrupt Clear */\r
+#define UOTGHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (UOTGHS_HSTICR) Host Start of Frame Interrupt Clear */\r
+#define UOTGHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (UOTGHS_HSTICR) Host Wake-Up Interrupt Clear */\r
+/* -------- UOTGHS_HSTIFR : (UOTGHS Offset: 0x040C) Host Global Interrupt Set Register -------- */\r
+#define UOTGHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (UOTGHS_HSTIFR) Device Connection Interrupt Set */\r
+#define UOTGHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (UOTGHS_HSTIFR) Device Disconnection Interrupt Set */\r
+#define UOTGHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (UOTGHS_HSTIFR) USB Reset Sent Interrupt Set */\r
+#define UOTGHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (UOTGHS_HSTIFR) Downstream Resume Sent Interrupt Set */\r
+#define UOTGHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (UOTGHS_HSTIFR) Upstream Resume Received Interrupt Set */\r
+#define UOTGHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (UOTGHS_HSTIFR) Host Start of Frame Interrupt Set */\r
+#define UOTGHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (UOTGHS_HSTIFR) Host Wake-Up Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIFR) DMA Channel 1 Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIFR) DMA Channel 2 Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIFR) DMA Channel 3 Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIFR) DMA Channel 4 Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIFR) DMA Channel 5 Interrupt Set */\r
+#define UOTGHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIFR) DMA Channel 6 Interrupt Set */\r
+/* -------- UOTGHS_HSTIMR : (UOTGHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */\r
+#define UOTGHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (UOTGHS_HSTIMR) Device Connection Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (UOTGHS_HSTIMR) Device Disconnection Interrupt Enable */\r
+#define UOTGHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (UOTGHS_HSTIMR) USB Reset Sent Interrupt Enable */\r
+#define UOTGHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (UOTGHS_HSTIMR) Downstream Resume Sent Interrupt Enable */\r
+#define UOTGHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (UOTGHS_HSTIMR) Upstream Resume Received Interrupt Enable */\r
+#define UOTGHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (UOTGHS_HSTIMR) Host Start of Frame Interrupt Enable */\r
+#define UOTGHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (UOTGHS_HSTIMR) Host Wake-Up Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIMR) Pipe 0 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIMR) Pipe 1 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIMR) Pipe 2 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIMR) Pipe 3 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIMR) Pipe 4 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIMR) Pipe 5 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIMR) Pipe 6 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIMR) Pipe 7 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIMR) Pipe 8 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIMR) Pipe 9 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIMR) DMA Channel 1 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIMR) DMA Channel 2 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIMR) DMA Channel 3 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIMR) DMA Channel 4 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIMR) DMA Channel 5 Interrupt Enable */\r
+#define UOTGHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIMR) DMA Channel 6 Interrupt Enable */\r
+/* -------- UOTGHS_HSTIDR : (UOTGHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */\r
+#define UOTGHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (UOTGHS_HSTIDR) Device Connection Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (UOTGHS_HSTIDR) Device Disconnection Interrupt Disable */\r
+#define UOTGHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (UOTGHS_HSTIDR) USB Reset Sent Interrupt Disable */\r
+#define UOTGHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (UOTGHS_HSTIDR) Downstream Resume Sent Interrupt Disable */\r
+#define UOTGHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (UOTGHS_HSTIDR) Upstream Resume Received Interrupt Disable */\r
+#define UOTGHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTIDR) Host Start of Frame Interrupt Disable */\r
+#define UOTGHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (UOTGHS_HSTIDR) Host Wake-Up Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIDR) Pipe 0 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIDR) Pipe 1 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIDR) Pipe 2 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIDR) Pipe 3 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIDR) Pipe 4 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIDR) Pipe 5 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIDR) Pipe 6 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIDR) Pipe 7 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIDR) Pipe 8 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIDR) Pipe 9 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIDR) DMA Channel 1 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIDR) DMA Channel 2 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIDR) DMA Channel 3 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIDR) DMA Channel 4 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIDR) DMA Channel 5 Interrupt Disable */\r
+#define UOTGHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIDR) DMA Channel 6 Interrupt Disable */\r
+/* -------- UOTGHS_HSTIER : (UOTGHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */\r
+#define UOTGHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (UOTGHS_HSTIER) Device Connection Interrupt Enable */\r
+#define UOTGHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (UOTGHS_HSTIER) Device Disconnection Interrupt Enable */\r
+#define UOTGHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (UOTGHS_HSTIER) USB Reset Sent Interrupt Enable */\r
+#define UOTGHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (UOTGHS_HSTIER) Downstream Resume Sent Interrupt Enable */\r
+#define UOTGHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (UOTGHS_HSTIER) Upstream Resume Received Interrupt Enable */\r
+#define UOTGHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (UOTGHS_HSTIER) Host Start of Frame Interrupt Enable */\r
+#define UOTGHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (UOTGHS_HSTIER) Host Wake-Up Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIER) Pipe 0 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIER) Pipe 1 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIER) Pipe 2 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIER) Pipe 3 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIER) Pipe 4 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIER) Pipe 5 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIER) Pipe 6 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIER) Pipe 7 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIER) Pipe 8 Interrupt Enable */\r
+#define UOTGHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIER) Pipe 9 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIER) DMA Channel 1 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIER) DMA Channel 2 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIER) DMA Channel 3 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIER) DMA Channel 4 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIER) DMA Channel 5 Interrupt Enable */\r
+#define UOTGHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIER) DMA Channel 6 Interrupt Enable */\r
+/* -------- UOTGHS_HSTPIP : (UOTGHS Offset: 0x0041C) Host Pipe Register -------- */\r
+#define UOTGHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Enable */\r
+#define UOTGHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Enable */\r
+#define UOTGHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Enable */\r
+#define UOTGHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Enable */\r
+#define UOTGHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Enable */\r
+#define UOTGHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Enable */\r
+#define UOTGHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Enable */\r
+#define UOTGHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Enable */\r
+#define UOTGHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Enable */\r
+#define UOTGHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Reset */\r
+#define UOTGHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Reset */\r
+#define UOTGHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Reset */\r
+#define UOTGHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Reset */\r
+#define UOTGHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Reset */\r
+#define UOTGHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Reset */\r
+#define UOTGHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Reset */\r
+#define UOTGHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Reset */\r
+#define UOTGHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Reset */\r
+/* -------- UOTGHS_HSTFNUM : (UOTGHS Offset: 0x0420) Host Frame Number Register -------- */\r
+#define UOTGHS_HSTFNUM_MFNUM_Pos 0\r
+#define UOTGHS_HSTFNUM_MFNUM_Msk (0x7u << UOTGHS_HSTFNUM_MFNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Micro Frame Number */\r
+#define UOTGHS_HSTFNUM_MFNUM(value) ((UOTGHS_HSTFNUM_MFNUM_Msk & ((value) << UOTGHS_HSTFNUM_MFNUM_Pos)))\r
+#define UOTGHS_HSTFNUM_FNUM_Pos 3\r
+#define UOTGHS_HSTFNUM_FNUM_Msk (0x7ffu << UOTGHS_HSTFNUM_FNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Number */\r
+#define UOTGHS_HSTFNUM_FNUM(value) ((UOTGHS_HSTFNUM_FNUM_Msk & ((value) << UOTGHS_HSTFNUM_FNUM_Pos)))\r
+#define UOTGHS_HSTFNUM_FLENHIGH_Pos 16\r
+#define UOTGHS_HSTFNUM_FLENHIGH_Msk (0xffu << UOTGHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Length */\r
+#define UOTGHS_HSTFNUM_FLENHIGH(value) ((UOTGHS_HSTFNUM_FLENHIGH_Msk & ((value) << UOTGHS_HSTFNUM_FLENHIGH_Pos)))\r
+/* -------- UOTGHS_HSTADDR1 : (UOTGHS Offset: 0x0424) Host Address 1 Register -------- */\r
+#define UOTGHS_HSTADDR1_HSTADDRP0_Pos 0\r
+#define UOTGHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */\r
+#define UOTGHS_HSTADDR1_HSTADDRP0(value) ((UOTGHS_HSTADDR1_HSTADDRP0_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP0_Pos)))\r
+#define UOTGHS_HSTADDR1_HSTADDRP1_Pos 8\r
+#define UOTGHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */\r
+#define UOTGHS_HSTADDR1_HSTADDRP1(value) ((UOTGHS_HSTADDR1_HSTADDRP1_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP1_Pos)))\r
+#define UOTGHS_HSTADDR1_HSTADDRP2_Pos 16\r
+#define UOTGHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */\r
+#define UOTGHS_HSTADDR1_HSTADDRP2(value) ((UOTGHS_HSTADDR1_HSTADDRP2_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP2_Pos)))\r
+#define UOTGHS_HSTADDR1_HSTADDRP3_Pos 24\r
+#define UOTGHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */\r
+#define UOTGHS_HSTADDR1_HSTADDRP3(value) ((UOTGHS_HSTADDR1_HSTADDRP3_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP3_Pos)))\r
+/* -------- UOTGHS_HSTADDR2 : (UOTGHS Offset: 0x0428) Host Address 2 Register -------- */\r
+#define UOTGHS_HSTADDR2_HSTADDRP4_Pos 0\r
+#define UOTGHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */\r
+#define UOTGHS_HSTADDR2_HSTADDRP4(value) ((UOTGHS_HSTADDR2_HSTADDRP4_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP4_Pos)))\r
+#define UOTGHS_HSTADDR2_HSTADDRP5_Pos 8\r
+#define UOTGHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */\r
+#define UOTGHS_HSTADDR2_HSTADDRP5(value) ((UOTGHS_HSTADDR2_HSTADDRP5_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP5_Pos)))\r
+#define UOTGHS_HSTADDR2_HSTADDRP6_Pos 16\r
+#define UOTGHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */\r
+#define UOTGHS_HSTADDR2_HSTADDRP6(value) ((UOTGHS_HSTADDR2_HSTADDRP6_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP6_Pos)))\r
+#define UOTGHS_HSTADDR2_HSTADDRP7_Pos 24\r
+#define UOTGHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */\r
+#define UOTGHS_HSTADDR2_HSTADDRP7(value) ((UOTGHS_HSTADDR2_HSTADDRP7_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP7_Pos)))\r
+/* -------- UOTGHS_HSTADDR3 : (UOTGHS Offset: 0x042C) Host Address 3 Register -------- */\r
+#define UOTGHS_HSTADDR3_HSTADDRP8_Pos 0\r
+#define UOTGHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */\r
+#define UOTGHS_HSTADDR3_HSTADDRP8(value) ((UOTGHS_HSTADDR3_HSTADDRP8_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP8_Pos)))\r
+#define UOTGHS_HSTADDR3_HSTADDRP9_Pos 8\r
+#define UOTGHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */\r
+#define UOTGHS_HSTADDR3_HSTADDRP9(value) ((UOTGHS_HSTADDR3_HSTADDRP9_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP9_Pos)))\r
+/* -------- UOTGHS_HSTPIPCFG[10] : (UOTGHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Memory Allocate */\r
+#define UOTGHS_HSTPIPCFG_PBK_Pos 2\r
+#define UOTGHS_HSTPIPCFG_PBK_Msk (0x3u << UOTGHS_HSTPIPCFG_PBK_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Banks */\r
+#define UOTGHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Single-bank pipe */\r
+#define UOTGHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Double-bank pipe */\r
+#define UOTGHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Triple-bank pipe */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_Pos 4\r
+#define UOTGHS_HSTPIPCFG_PSIZE_Msk (0x7u << UOTGHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Size */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 8 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 16 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 32 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 64 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 128 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 256 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 512 bytes */\r
+#define UOTGHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 1024 bytes */\r
+#define UOTGHS_HSTPIPCFG_PTOKEN_Pos 8\r
+#define UOTGHS_HSTPIPCFG_PTOKEN_Msk (0x3u << UOTGHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Token */\r
+#define UOTGHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) SETUP */\r
+#define UOTGHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) IN */\r
+#define UOTGHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) OUT */\r
+#define UOTGHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (UOTGHS_HSTPIPCFG[10]) Automatic Switch */\r
+#define UOTGHS_HSTPIPCFG_PTYPE_Pos 12\r
+#define UOTGHS_HSTPIPCFG_PTYPE_Msk (0x3u << UOTGHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Type */\r
+#define UOTGHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Control */\r
+#define UOTGHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Isochronous */\r
+#define UOTGHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Bulk */\r
+#define UOTGHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Interrupt */\r
+#define UOTGHS_HSTPIPCFG_PEPNUM_Pos 16\r
+#define UOTGHS_HSTPIPCFG_PEPNUM_Msk (0xfu << UOTGHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Endpoint Number */\r
+#define UOTGHS_HSTPIPCFG_PEPNUM(value) ((UOTGHS_HSTPIPCFG_PEPNUM_Msk & ((value) << UOTGHS_HSTPIPCFG_PEPNUM_Pos)))\r
+#define UOTGHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (UOTGHS_HSTPIPCFG[10]) Ping Enable */\r
+#define UOTGHS_HSTPIPCFG_INTFRQ_Pos 24\r
+#define UOTGHS_HSTPIPCFG_INTFRQ_Msk (0xffu << UOTGHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */\r
+#define UOTGHS_HSTPIPCFG_INTFRQ(value) ((UOTGHS_HSTPIPCFG_INTFRQ_Msk & ((value) << UOTGHS_HSTPIPCFG_INTFRQ_Pos)))\r
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Pos 24\r
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << UOTGHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) bInterval parameter for the Bulk-Out/Ping transaction */\r
+#define UOTGHS_HSTPIPCFG_BINTERVAL(value) ((UOTGHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << UOTGHS_HSTPIPCFG_BINTERVAL_Pos)))\r
+/* -------- UOTGHS_HSTPIPISR[10] : (UOTGHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (UOTGHS_HSTPIPISR[10]) Received IN Data Interrupt */\r
+#define UOTGHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */\r
+#define UOTGHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */\r
+#define UOTGHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Underflow Interrupt */\r
+#define UOTGHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Error Interrupt */\r
+#define UOTGHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (UOTGHS_HSTPIPISR[10]) NAKed Interrupt */\r
+#define UOTGHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_HSTPIPISR[10]) Overflow Interrupt */\r
+#define UOTGHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) Received STALLed Interrupt */\r
+#define UOTGHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) CRC Error Interrupt */\r
+#define UOTGHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (UOTGHS_HSTPIPISR[10]) Short Packet Interrupt */\r
+#define UOTGHS_HSTPIPISR_DTSEQ_Pos 8\r
+#define UOTGHS_HSTPIPISR_DTSEQ_Msk (0x3u << UOTGHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Data Toggle Sequence */\r
+#define UOTGHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data0 toggle sequence */\r
+#define UOTGHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data1 toggle sequence */\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_Pos 12\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_Msk (0x3u << UOTGHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Number of Busy Banks */\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 0 busy bank (all banks free) */\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 1 busy bank */\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 2 busy banks */\r
+#define UOTGHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 3 busy banks */\r
+#define UOTGHS_HSTPIPISR_CURRBK_Pos 14\r
+#define UOTGHS_HSTPIPISR_CURRBK_Msk (0x3u << UOTGHS_HSTPIPISR_CURRBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Current Bank */\r
+#define UOTGHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank0 */\r
+#define UOTGHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank1 */\r
+#define UOTGHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank2 */\r
+#define UOTGHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_HSTPIPISR[10]) Read-write Allowed */\r
+#define UOTGHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_HSTPIPISR[10]) Configuration OK Status */\r
+#define UOTGHS_HSTPIPISR_PBYCT_Pos 20\r
+#define UOTGHS_HSTPIPISR_PBYCT_Msk (0x7ffu << UOTGHS_HSTPIPISR_PBYCT_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Byte Count */\r
+/* -------- UOTGHS_HSTPIPICR[10] : (UOTGHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Underflow Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPICR[10]) NAKed Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPICR[10]) Overflow Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) CRC Error Interrupt Clear */\r
+#define UOTGHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPICR[10]) Short Packet Interrupt Clear */\r
+/* -------- UOTGHS_HSTPIPIFR[10] : (UOTGHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Underflow Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIFR[10]) NAKed Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIFR[10]) Overflow Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) CRC Error Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIFR[10]) Short Packet Interrupt Set */\r
+#define UOTGHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIFR[10]) Number of Busy Banks Set */\r
+/* -------- UOTGHS_HSTPIPIMR[10] : (UOTGHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Underflow Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIMR[10]) NAKed Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIMR[10]) Overflow Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */\r
+#define UOTGHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIMR[10]) FIFO Control */\r
+#define UOTGHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */\r
+#define UOTGHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Freeze */\r
+#define UOTGHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIMR[10]) Reset Data Toggle */\r
+/* -------- UOTGHS_HSTPIPIER[10] : (UOTGHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Underflow Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIER[10]) NAKed Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIER[10]) Overflow Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) CRC Error Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIER[10]) Short Packet Interrupt Enable */\r
+#define UOTGHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIER[10]) Number of Busy Banks Enable */\r
+#define UOTGHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */\r
+#define UOTGHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Freeze Enable */\r
+#define UOTGHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIER[10]) Reset Data Toggle Enable */\r
+/* -------- UOTGHS_HSTPIPIDR[10] : (UOTGHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Underflow Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIDR[10]) NAKed Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIDR[10]) Overflow Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */\r
+#define UOTGHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIDR[10]) Number of Busy Banks Disable */\r
+#define UOTGHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIDR[10]) FIFO Control Disable */\r
+#define UOTGHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */\r
+#define UOTGHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Freeze Disable */\r
+/* -------- UOTGHS_HSTPIPINRQ[10] : (UOTGHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPINRQ_INRQ_Pos 0\r
+#define UOTGHS_HSTPIPINRQ_INRQ_Msk (0xffu << UOTGHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Number before Freeze */\r
+#define UOTGHS_HSTPIPINRQ_INRQ(value) ((UOTGHS_HSTPIPINRQ_INRQ_Msk & ((value) << UOTGHS_HSTPIPINRQ_INRQ_Pos)))\r
+#define UOTGHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Mode */\r
+/* -------- UOTGHS_HSTPIPERR[10] : (UOTGHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */\r
+#define UOTGHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (UOTGHS_HSTPIPERR[10]) Data Toggle Error */\r
+#define UOTGHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (UOTGHS_HSTPIPERR[10]) Data PID Error */\r
+#define UOTGHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (UOTGHS_HSTPIPERR[10]) PID Error */\r
+#define UOTGHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (UOTGHS_HSTPIPERR[10]) Time-Out Error */\r
+#define UOTGHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (UOTGHS_HSTPIPERR[10]) CRC16 Error */\r
+#define UOTGHS_HSTPIPERR_COUNTER_Pos 5\r
+#define UOTGHS_HSTPIPERR_COUNTER_Msk (0x3u << UOTGHS_HSTPIPERR_COUNTER_Pos) /**< \brief (UOTGHS_HSTPIPERR[10]) Error Counter */\r
+#define UOTGHS_HSTPIPERR_COUNTER(value) ((UOTGHS_HSTPIPERR_COUNTER_Msk & ((value) << UOTGHS_HSTPIPERR_COUNTER_Pos)))\r
+/* -------- UOTGHS_HSTDMANXTDSC : (UOTGHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */\r
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0\r
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_HSTDMANXTDSC) Next Descriptor Address */\r
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))\r
+/* -------- UOTGHS_HSTDMAADDRESS : (UOTGHS Offset: N/A) Host DMA Channel Address Register -------- */\r
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos 0\r
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_HSTDMAADDRESS) Buffer Address */\r
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD(value) ((UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos)))\r
+/* -------- UOTGHS_HSTDMACONTROL : (UOTGHS Offset: N/A) Host DMA Channel Control Register -------- */\r
+#define UOTGHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMACONTROL) Channel Enable Command */\r
+#define UOTGHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */\r
+#define UOTGHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Enable (Control) */\r
+#define UOTGHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Enable Control */\r
+#define UOTGHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Interrupt Enable */\r
+#define UOTGHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Interrupt Enable */\r
+#define UOTGHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */\r
+#define UOTGHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_HSTDMACONTROL) Burst Lock Enable */\r
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16\r
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */\r
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))\r
+/* -------- UOTGHS_HSTDMASTATUS : (UOTGHS Offset: N/A) Host DMA Channel Status Register -------- */\r
+#define UOTGHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Enable Status */\r
+#define UOTGHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Active Status */\r
+#define UOTGHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Transfer Status */\r
+#define UOTGHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Buffer Status */\r
+#define UOTGHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_HSTDMASTATUS) Descriptor Loaded Status */\r
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos 16\r
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_HSTDMASTATUS) Buffer Byte Count */\r
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT(value) ((UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos)))\r
+/* -------- UOTGHS_CTRL : (UOTGHS Offset: 0x0800) General Control Register -------- */\r
+#define UOTGHS_CTRL_IDTE (0x1u << 0) /**< \brief (UOTGHS_CTRL) ID Transition Interrupt Enable */\r
+#define UOTGHS_CTRL_VBUSTE (0x1u << 1) /**< \brief (UOTGHS_CTRL) VBus Transition Interrupt Enable */\r
+#define UOTGHS_CTRL_SRPE (0x1u << 2) /**< \brief (UOTGHS_CTRL) SRP Interrupt Enable */\r
+#define UOTGHS_CTRL_VBERRE (0x1u << 3) /**< \brief (UOTGHS_CTRL) VBus Error Interrupt Enable */\r
+#define UOTGHS_CTRL_BCERRE (0x1u << 4) /**< \brief (UOTGHS_CTRL) B-Connection Error Interrupt Enable */\r
+#define UOTGHS_CTRL_ROLEEXE (0x1u << 5) /**< \brief (UOTGHS_CTRL) Role Exchange Interrupt Enable */\r
+#define UOTGHS_CTRL_HNPERRE (0x1u << 6) /**< \brief (UOTGHS_CTRL) HNP Error Interrupt Enable */\r
+#define UOTGHS_CTRL_STOE (0x1u << 7) /**< \brief (UOTGHS_CTRL) Suspend Time-Out Interrupt Enable */\r
+#define UOTGHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (UOTGHS_CTRL) VBus Hardware Control */\r
+#define UOTGHS_CTRL_SRPSEL (0x1u << 9) /**< \brief (UOTGHS_CTRL) SRP Selection */\r
+#define UOTGHS_CTRL_SRPREQ (0x1u << 10) /**< \brief (UOTGHS_CTRL) SRP Request */\r
+#define UOTGHS_CTRL_HNPREQ (0x1u << 11) /**< \brief (UOTGHS_CTRL) HNP Request */\r
+#define UOTGHS_CTRL_OTGPADE (0x1u << 12) /**< \brief (UOTGHS_CTRL) OTG Pad Enable */\r
+#define UOTGHS_CTRL_VBUSPO (0x1u << 13) /**< \brief (UOTGHS_CTRL) VBus Polarity Off */\r
+#define UOTGHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (UOTGHS_CTRL) Freeze USB Clock */\r
+#define UOTGHS_CTRL_USBE (0x1u << 15) /**< \brief (UOTGHS_CTRL) UOTGHS Enable */\r
+#define UOTGHS_CTRL_TIMVALUE_Pos 16\r
+#define UOTGHS_CTRL_TIMVALUE_Msk (0x3u << UOTGHS_CTRL_TIMVALUE_Pos) /**< \brief (UOTGHS_CTRL) Timer Value */\r
+#define UOTGHS_CTRL_TIMVALUE(value) ((UOTGHS_CTRL_TIMVALUE_Msk & ((value) << UOTGHS_CTRL_TIMVALUE_Pos)))\r
+#define UOTGHS_CTRL_TIMPAGE_Pos 20\r
+#define UOTGHS_CTRL_TIMPAGE_Msk (0x3u << UOTGHS_CTRL_TIMPAGE_Pos) /**< \brief (UOTGHS_CTRL) Timer Page */\r
+#define UOTGHS_CTRL_TIMPAGE(value) ((UOTGHS_CTRL_TIMPAGE_Msk & ((value) << UOTGHS_CTRL_TIMPAGE_Pos)))\r
+#define UOTGHS_CTRL_UNLOCK (0x1u << 22) /**< \brief (UOTGHS_CTRL) Timer Access Unlock */\r
+#define UOTGHS_CTRL_UIDE (0x1u << 24) /**< \brief (UOTGHS_CTRL) UOTGID Pin Enable */\r
+#define UOTGHS_CTRL_UIDE_UIMOD (0x0u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UIMOD bit. */\r
+#define UOTGHS_CTRL_UIDE_UOTGID (0x1u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UOTGID input pin. */\r
+#define UOTGHS_CTRL_UIMOD (0x1u << 25) /**< \brief (UOTGHS_CTRL) UOTGHS Mode */\r
+#define UOTGHS_CTRL_UIMOD_Host (0x0u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB host mode. */\r
+#define UOTGHS_CTRL_UIMOD_Device (0x1u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB device mode. */\r
+/* -------- UOTGHS_SR : (UOTGHS Offset: 0x0804) General Status Register -------- */\r
+#define UOTGHS_SR_IDTI (0x1u << 0) /**< \brief (UOTGHS_SR) ID Transition Interrupt */\r
+#define UOTGHS_SR_VBUSTI (0x1u << 1) /**< \brief (UOTGHS_SR) VBus Transition Interrupt */\r
+#define UOTGHS_SR_SRPI (0x1u << 2) /**< \brief (UOTGHS_SR) SRP Interrupt */\r
+#define UOTGHS_SR_VBERRI (0x1u << 3) /**< \brief (UOTGHS_SR) VBus Error Interrupt */\r
+#define UOTGHS_SR_BCERRI (0x1u << 4) /**< \brief (UOTGHS_SR) B-Connection Error Interrupt */\r
+#define UOTGHS_SR_ROLEEXI (0x1u << 5) /**< \brief (UOTGHS_SR) Role Exchange Interrupt */\r
+#define UOTGHS_SR_HNPERRI (0x1u << 6) /**< \brief (UOTGHS_SR) HNP Error Interrupt */\r
+#define UOTGHS_SR_STOI (0x1u << 7) /**< \brief (UOTGHS_SR) Suspend Time-Out Interrupt */\r
+#define UOTGHS_SR_VBUSRQ (0x1u << 9) /**< \brief (UOTGHS_SR) VBus Request */\r
+#define UOTGHS_SR_ID (0x1u << 10) /**< \brief (UOTGHS_SR) UOTGID Pin State */\r
+#define UOTGHS_SR_VBUS (0x1u << 11) /**< \brief (UOTGHS_SR) VBus Level */\r
+#define UOTGHS_SR_SPEED_Pos 12\r
+#define UOTGHS_SR_SPEED_Msk (0x3u << UOTGHS_SR_SPEED_Pos) /**< \brief (UOTGHS_SR) Speed Status */\r
+#define UOTGHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (UOTGHS_SR) Full-Speed mode */\r
+#define UOTGHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (UOTGHS_SR) High-Speed mode */\r
+#define UOTGHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (UOTGHS_SR) Low-Speed mode */\r
+#define UOTGHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (UOTGHS_SR) UTMI Clock Usable */\r
+/* -------- UOTGHS_SCR : (UOTGHS Offset: 0x0808) General Status Clear Register -------- */\r
+#define UOTGHS_SCR_IDTIC (0x1u << 0) /**< \brief (UOTGHS_SCR) ID Transition Interrupt Clear */\r
+#define UOTGHS_SCR_VBUSTIC (0x1u << 1) /**< \brief (UOTGHS_SCR) VBus Transition Interrupt Clear */\r
+#define UOTGHS_SCR_SRPIC (0x1u << 2) /**< \brief (UOTGHS_SCR) SRP Interrupt Clear */\r
+#define UOTGHS_SCR_VBERRIC (0x1u << 3) /**< \brief (UOTGHS_SCR) VBus Error Interrupt Clear */\r
+#define UOTGHS_SCR_BCERRIC (0x1u << 4) /**< \brief (UOTGHS_SCR) B-Connection Error Interrupt Clear */\r
+#define UOTGHS_SCR_ROLEEXIC (0x1u << 5) /**< \brief (UOTGHS_SCR) Role Exchange Interrupt Clear */\r
+#define UOTGHS_SCR_HNPERRIC (0x1u << 6) /**< \brief (UOTGHS_SCR) HNP Error Interrupt Clear */\r
+#define UOTGHS_SCR_STOIC (0x1u << 7) /**< \brief (UOTGHS_SCR) Suspend Time-Out Interrupt Clear */\r
+#define UOTGHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (UOTGHS_SCR) VBus Request Clear */\r
+/* -------- UOTGHS_SFR : (UOTGHS Offset: 0x080C) General Status Set Register -------- */\r
+#define UOTGHS_SFR_IDTIS (0x1u << 0) /**< \brief (UOTGHS_SFR) ID Transition Interrupt Set */\r
+#define UOTGHS_SFR_VBUSTIS (0x1u << 1) /**< \brief (UOTGHS_SFR) VBus Transition Interrupt Set */\r
+#define UOTGHS_SFR_SRPIS (0x1u << 2) /**< \brief (UOTGHS_SFR) SRP Interrupt Set */\r
+#define UOTGHS_SFR_VBERRIS (0x1u << 3) /**< \brief (UOTGHS_SFR) VBus Error Interrupt Set */\r
+#define UOTGHS_SFR_BCERRIS (0x1u << 4) /**< \brief (UOTGHS_SFR) B-Connection Error Interrupt Set */\r
+#define UOTGHS_SFR_ROLEEXIS (0x1u << 5) /**< \brief (UOTGHS_SFR) Role Exchange Interrupt Set */\r
+#define UOTGHS_SFR_HNPERRIS (0x1u << 6) /**< \brief (UOTGHS_SFR) HNP Error Interrupt Set */\r
+#define UOTGHS_SFR_STOIS (0x1u << 7) /**< \brief (UOTGHS_SFR) Suspend Time-Out Interrupt Set */\r
+#define UOTGHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (UOTGHS_SFR) VBus Request Set */\r
+/* -------- UOTGHS_FSM : (UOTGHS Offset: 0x082C) General Finite State Machine Register -------- */\r
+#define UOTGHS_FSM_DRDSTATE_Pos 0\r
+#define UOTGHS_FSM_DRDSTATE_Msk (0xfu << UOTGHS_FSM_DRDSTATE_Pos) /**< \brief (UOTGHS_FSM) */\r
+#define UOTGHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (UOTGHS_FSM) This is the start state for A-devices (when the ID pin is 0) */\r
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */\r
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */\r
+#define UOTGHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device that operates in Host mode is operational. */\r
+#define UOTGHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (UOTGHS_FSM) The A-device operating as a host is in the suspend mode. */\r
+#define UOTGHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (UOTGHS_FSM) The A-device operates as a peripheral. */\r
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */\r
+#define UOTGHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */\r
+#define UOTGHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */\r
+#define UOTGHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (UOTGHS_FSM) This is the start state for B-device (when the ID pin is 1). */\r
+#define UOTGHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the peripheral. */\r
+#define UOTGHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */\r
+#define UOTGHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. */\r
+#define UOTGHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */\r
+#define UOTGHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the Host. */\r
+#define UOTGHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_UOTGHS_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_USART_COMPONENT_\r
+#define _SAM3XA_USART_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_USART Universal Synchronous Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Usart hardware registers */\r
+typedef struct {\r
+ WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */\r
+ RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */\r
+ WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */\r
+ WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */\r
+ RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */\r
+ RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */\r
+ RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */\r
+ WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */\r
+ RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */\r
+ RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */\r
+ RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */\r
+ RoReg Reserved1[5];\r
+ RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */\r
+ RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */\r
+ RoReg Reserved2[1];\r
+ RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */\r
+ RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */\r
+ RwReg US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */\r
+ RwReg US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */\r
+ RoReg Reserved3[34];\r
+ RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved4[5];\r
+ RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */\r
+ RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */\r
+ RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */\r
+ RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */\r
+ RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */\r
+ RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */\r
+ RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */\r
+} Usart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */\r
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */\r
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */\r
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */\r
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */\r
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */\r
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */\r
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */\r
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */\r
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */\r
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */\r
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */\r
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */\r
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */\r
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */\r
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */\r
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */\r
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */\r
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */\r
+#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */\r
+#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */\r
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */\r
+#define US_MR_USART_MODE_Pos 0\r
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) */\r
+#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */\r
+#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */\r
+#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */\r
+#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */\r
+#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */\r
+#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */\r
+#define US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN Master */\r
+#define US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave */\r
+#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */\r
+#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */\r
+#define US_MR_USCLKS_Pos 4\r
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */\r
+#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */\r
+#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */\r
+#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */\r
+#define US_MR_CHRL_Pos 6\r
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */\r
+#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */\r
+#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */\r
+#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */\r
+#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */\r
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */\r
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */\r
+#define US_MR_PAR_Pos 9\r
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */\r
+#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */\r
+#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */\r
+#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */\r
+#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */\r
+#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */\r
+#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */\r
+#define US_MR_NBSTOP_Pos 12\r
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */\r
+#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */\r
+#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */\r
+#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */\r
+#define US_MR_CHMODE_Pos 14\r
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */\r
+#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */\r
+#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */\r
+#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */\r
+#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */\r
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */\r
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */\r
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */\r
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */\r
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */\r
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */\r
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */\r
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */\r
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */\r
+#define US_MR_MAX_ITERATION_Pos 24\r
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) */\r
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))\r
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */\r
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */\r
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */\r
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */\r
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */\r
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */\r
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */\r
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */\r
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */\r
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */\r
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */\r
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */\r
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */\r
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */\r
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */\r
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */\r
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */\r
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */\r
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */\r
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */\r
+#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */\r
+#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */\r
+#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */\r
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */\r
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */\r
+#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */\r
+#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */\r
+#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */\r
+#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */\r
+#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */\r
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */\r
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */\r
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */\r
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */\r
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */\r
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */\r
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */\r
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */\r
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */\r
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */\r
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */\r
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */\r
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */\r
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */\r
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */\r
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */\r
+#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */\r
+#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */\r
+#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */\r
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */\r
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */\r
+#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */\r
+#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */\r
+#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */\r
+#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */\r
+#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */\r
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */\r
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */\r
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */\r
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */\r
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */\r
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */\r
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */\r
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */\r
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */\r
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */\r
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */\r
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */\r
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */\r
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */\r
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */\r
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */\r
+#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */\r
+#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */\r
+#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */\r
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */\r
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */\r
+#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */\r
+#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */\r
+#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */\r
+#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */\r
+#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */\r
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */\r
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */\r
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */\r
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */\r
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */\r
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */\r
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */\r
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */\r
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */\r
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */\r
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */\r
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */\r
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */\r
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */\r
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */\r
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt */\r
+#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received */\r
+#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */\r
+#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed */\r
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */\r
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */\r
+#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */\r
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */\r
+#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */\r
+#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */\r
+#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */\r
+#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */\r
+#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */\r
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */\r
+#define US_RHR_RXCHR_Pos 0\r
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */\r
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */\r
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */\r
+#define US_THR_TXCHR_Pos 0\r
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */\r
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))\r
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */\r
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define US_BRGR_CD_Pos 0\r
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */\r
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))\r
+#define US_BRGR_FP_Pos 16\r
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */\r
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))\r
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */\r
+#define US_RTOR_TO_Pos 0\r
+#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */\r
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))\r
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */\r
+#define US_TTGR_TG_Pos 0\r
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */\r
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))\r
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */\r
+#define US_FIDI_FI_DI_RATIO_Pos 0\r
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */\r
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))\r
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */\r
+#define US_NER_NB_ERRORS_Pos 0\r
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */\r
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */\r
+#define US_IF_IRDA_FILTER_Pos 0\r
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */\r
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))\r
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */\r
+#define US_MAN_TX_PL_Pos 0\r
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */\r
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))\r
+#define US_MAN_TX_PP_Pos 8\r
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */\r
+#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */\r
+#define US_MAN_RX_PL_Pos 16\r
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */\r
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))\r
+#define US_MAN_RX_PP_Pos 24\r
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */\r
+#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */\r
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN) */\r
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */\r
+/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */\r
+#define US_LINMR_NACT_Pos 0\r
+#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */\r
+#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */\r
+#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */\r
+#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */\r
+#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */\r
+#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */\r
+#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */\r
+#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */\r
+#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */\r
+#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */\r
+#define US_LINMR_DLC_Pos 8\r
+#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */\r
+#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))\r
+#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) PDC Mode */\r
+/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */\r
+#define US_LINIR_IDCHR_Pos 0\r
+#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */\r
+#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))\r
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */\r
+#define US_WPMR_WPKEY_Pos 8\r
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */\r
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))\r
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */\r
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */\r
+#define US_WPSR_WPVSRC_Pos 8\r
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */\r
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */\r
+#define US_RPR_RXPTR_Pos 0\r
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */\r
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))\r
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */\r
+#define US_RCR_RXCTR_Pos 0\r
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */\r
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))\r
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */\r
+#define US_TPR_TXPTR_Pos 0\r
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */\r
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))\r
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */\r
+#define US_TCR_TXCTR_Pos 0\r
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */\r
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))\r
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define US_RNPR_RXNPTR_Pos 0\r
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */\r
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))\r
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */\r
+#define US_RNCR_RXNCTR_Pos 0\r
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */\r
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))\r
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define US_TNPR_TXNPTR_Pos 0\r
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */\r
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))\r
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define US_TNCR_TXNCTR_Pos 0\r
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */\r
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))\r
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */\r
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */\r
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */\r
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */\r
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */\r
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */\r
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */\r
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_USART_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_WDT_COMPONENT_\r
+#define _SAM3XA_WDT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Watchdog Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM3XA_WDT Watchdog Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Wdt hardware registers */\r
+typedef struct {\r
+ WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */\r
+ RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */\r
+ RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */\r
+} Wdt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */\r
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */\r
+#define WDT_CR_KEY_Pos 24\r
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */\r
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))\r
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */\r
+#define WDT_MR_WDV_Pos 0\r
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */\r
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))\r
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */\r
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */\r
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */\r
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */\r
+#define WDT_MR_WDD_Pos 16\r
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */\r
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))\r
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */\r
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */\r
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */\r
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */\r
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM3XA_WDT_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_ADC_INSTANCE_\r
+#define _SAM3XA_ADC_INSTANCE_\r
+\r
+/* ========== Register definition for ADC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_ADC_CR (0x400C0000U) /**< \brief (ADC) Control Register */\r
+#define REG_ADC_MR (0x400C0004U) /**< \brief (ADC) Mode Register */\r
+#define REG_ADC_SEQR1 (0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */\r
+#define REG_ADC_SEQR2 (0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */\r
+#define REG_ADC_CHER (0x400C0010U) /**< \brief (ADC) Channel Enable Register */\r
+#define REG_ADC_CHDR (0x400C0014U) /**< \brief (ADC) Channel Disable Register */\r
+#define REG_ADC_CHSR (0x400C0018U) /**< \brief (ADC) Channel Status Register */\r
+#define REG_ADC_LCDR (0x400C0020U) /**< \brief (ADC) Last Converted Data Register */\r
+#define REG_ADC_IER (0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */\r
+#define REG_ADC_IDR (0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */\r
+#define REG_ADC_IMR (0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */\r
+#define REG_ADC_ISR (0x400C0030U) /**< \brief (ADC) Interrupt Status Register */\r
+#define REG_ADC_OVER (0x400C003CU) /**< \brief (ADC) Overrun Status Register */\r
+#define REG_ADC_EMR (0x400C0040U) /**< \brief (ADC) Extended Mode Register */\r
+#define REG_ADC_CWR (0x400C0044U) /**< \brief (ADC) Compare Window Register */\r
+#define REG_ADC_CGR (0x400C0048U) /**< \brief (ADC) Channel Gain Register */\r
+#define REG_ADC_COR (0x400C004CU) /**< \brief (ADC) Channel Offset Register */\r
+#define REG_ADC_CDR (0x400C0050U) /**< \brief (ADC) Channel Data Register */\r
+#define REG_ADC_ACR (0x400C0094U) /**< \brief (ADC) Analog Control Register */\r
+#define REG_ADC_WPMR (0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */\r
+#define REG_ADC_WPSR (0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */\r
+#define REG_ADC_RPR (0x400C0100U) /**< \brief (ADC) Receive Pointer Register */\r
+#define REG_ADC_RCR (0x400C0104U) /**< \brief (ADC) Receive Counter Register */\r
+#define REG_ADC_RNPR (0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */\r
+#define REG_ADC_RNCR (0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */\r
+#define REG_ADC_PTCR (0x400C0120U) /**< \brief (ADC) Transfer Control Register */\r
+#define REG_ADC_PTSR (0x400C0124U) /**< \brief (ADC) Transfer Status Register */\r
+#else\r
+#define REG_ADC_CR (*(WoReg*)0x400C0000U) /**< \brief (ADC) Control Register */\r
+#define REG_ADC_MR (*(RwReg*)0x400C0004U) /**< \brief (ADC) Mode Register */\r
+#define REG_ADC_SEQR1 (*(RwReg*)0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */\r
+#define REG_ADC_SEQR2 (*(RwReg*)0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */\r
+#define REG_ADC_CHER (*(WoReg*)0x400C0010U) /**< \brief (ADC) Channel Enable Register */\r
+#define REG_ADC_CHDR (*(WoReg*)0x400C0014U) /**< \brief (ADC) Channel Disable Register */\r
+#define REG_ADC_CHSR (*(RoReg*)0x400C0018U) /**< \brief (ADC) Channel Status Register */\r
+#define REG_ADC_LCDR (*(RoReg*)0x400C0020U) /**< \brief (ADC) Last Converted Data Register */\r
+#define REG_ADC_IER (*(WoReg*)0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */\r
+#define REG_ADC_IDR (*(WoReg*)0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */\r
+#define REG_ADC_IMR (*(RoReg*)0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */\r
+#define REG_ADC_ISR (*(RoReg*)0x400C0030U) /**< \brief (ADC) Interrupt Status Register */\r
+#define REG_ADC_OVER (*(RoReg*)0x400C003CU) /**< \brief (ADC) Overrun Status Register */\r
+#define REG_ADC_EMR (*(RwReg*)0x400C0040U) /**< \brief (ADC) Extended Mode Register */\r
+#define REG_ADC_CWR (*(RwReg*)0x400C0044U) /**< \brief (ADC) Compare Window Register */\r
+#define REG_ADC_CGR (*(RwReg*)0x400C0048U) /**< \brief (ADC) Channel Gain Register */\r
+#define REG_ADC_COR (*(RwReg*)0x400C004CU) /**< \brief (ADC) Channel Offset Register */\r
+#define REG_ADC_CDR (*(RoReg*)0x400C0050U) /**< \brief (ADC) Channel Data Register */\r
+#define REG_ADC_ACR (*(RwReg*)0x400C0094U) /**< \brief (ADC) Analog Control Register */\r
+#define REG_ADC_WPMR (*(RwReg*)0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */\r
+#define REG_ADC_WPSR (*(RoReg*)0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */\r
+#define REG_ADC_RPR (*(RwReg*)0x400C0100U) /**< \brief (ADC) Receive Pointer Register */\r
+#define REG_ADC_RCR (*(RwReg*)0x400C0104U) /**< \brief (ADC) Receive Counter Register */\r
+#define REG_ADC_RNPR (*(RwReg*)0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */\r
+#define REG_ADC_RNCR (*(RwReg*)0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */\r
+#define REG_ADC_PTCR (*(WoReg*)0x400C0120U) /**< \brief (ADC) Transfer Control Register */\r
+#define REG_ADC_PTSR (*(RoReg*)0x400C0124U) /**< \brief (ADC) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_ADC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_CAN0_INSTANCE_\r
+#define _SAM3XA_CAN0_INSTANCE_\r
+\r
+/* ========== Register definition for CAN0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CAN0_MR (0x400B4000U) /**< \brief (CAN0) Mode Register */\r
+#define REG_CAN0_IER (0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */\r
+#define REG_CAN0_IDR (0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */\r
+#define REG_CAN0_IMR (0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */\r
+#define REG_CAN0_SR (0x400B4010U) /**< \brief (CAN0) Status Register */\r
+#define REG_CAN0_BR (0x400B4014U) /**< \brief (CAN0) Baudrate Register */\r
+#define REG_CAN0_TIM (0x400B4018U) /**< \brief (CAN0) Timer Register */\r
+#define REG_CAN0_TIMESTP (0x400B401CU) /**< \brief (CAN0) Timestamp Register */\r
+#define REG_CAN0_ECR (0x400B4020U) /**< \brief (CAN0) Error Counter Register */\r
+#define REG_CAN0_TCR (0x400B4024U) /**< \brief (CAN0) Transfer Command Register */\r
+#define REG_CAN0_ACR (0x400B4028U) /**< \brief (CAN0) Abort Command Register */\r
+#define REG_CAN0_WPMR (0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */\r
+#define REG_CAN0_WPSR (0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */\r
+#define REG_CAN0_MMR0 (0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */\r
+#define REG_CAN0_MAM0 (0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */\r
+#define REG_CAN0_MID0 (0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */\r
+#define REG_CAN0_MFID0 (0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */\r
+#define REG_CAN0_MSR0 (0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */\r
+#define REG_CAN0_MDL0 (0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */\r
+#define REG_CAN0_MDH0 (0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */\r
+#define REG_CAN0_MCR0 (0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */\r
+#define REG_CAN0_MMR1 (0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */\r
+#define REG_CAN0_MAM1 (0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */\r
+#define REG_CAN0_MID1 (0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */\r
+#define REG_CAN0_MFID1 (0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */\r
+#define REG_CAN0_MSR1 (0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */\r
+#define REG_CAN0_MDL1 (0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */\r
+#define REG_CAN0_MDH1 (0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */\r
+#define REG_CAN0_MCR1 (0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */\r
+#define REG_CAN0_MMR2 (0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */\r
+#define REG_CAN0_MAM2 (0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */\r
+#define REG_CAN0_MID2 (0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */\r
+#define REG_CAN0_MFID2 (0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */\r
+#define REG_CAN0_MSR2 (0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */\r
+#define REG_CAN0_MDL2 (0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */\r
+#define REG_CAN0_MDH2 (0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */\r
+#define REG_CAN0_MCR2 (0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */\r
+#define REG_CAN0_MMR3 (0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */\r
+#define REG_CAN0_MAM3 (0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */\r
+#define REG_CAN0_MID3 (0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */\r
+#define REG_CAN0_MFID3 (0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */\r
+#define REG_CAN0_MSR3 (0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */\r
+#define REG_CAN0_MDL3 (0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */\r
+#define REG_CAN0_MDH3 (0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */\r
+#define REG_CAN0_MCR3 (0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */\r
+#define REG_CAN0_MMR4 (0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */\r
+#define REG_CAN0_MAM4 (0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */\r
+#define REG_CAN0_MID4 (0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */\r
+#define REG_CAN0_MFID4 (0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */\r
+#define REG_CAN0_MSR4 (0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */\r
+#define REG_CAN0_MDL4 (0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */\r
+#define REG_CAN0_MDH4 (0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */\r
+#define REG_CAN0_MCR4 (0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */\r
+#define REG_CAN0_MMR5 (0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */\r
+#define REG_CAN0_MAM5 (0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */\r
+#define REG_CAN0_MID5 (0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */\r
+#define REG_CAN0_MFID5 (0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */\r
+#define REG_CAN0_MSR5 (0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */\r
+#define REG_CAN0_MDL5 (0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */\r
+#define REG_CAN0_MDH5 (0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */\r
+#define REG_CAN0_MCR5 (0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */\r
+#define REG_CAN0_MMR6 (0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */\r
+#define REG_CAN0_MAM6 (0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */\r
+#define REG_CAN0_MID6 (0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */\r
+#define REG_CAN0_MFID6 (0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */\r
+#define REG_CAN0_MSR6 (0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */\r
+#define REG_CAN0_MDL6 (0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */\r
+#define REG_CAN0_MDH6 (0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */\r
+#define REG_CAN0_MCR6 (0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */\r
+#define REG_CAN0_MMR7 (0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */\r
+#define REG_CAN0_MAM7 (0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */\r
+#define REG_CAN0_MID7 (0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */\r
+#define REG_CAN0_MFID7 (0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */\r
+#define REG_CAN0_MSR7 (0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */\r
+#define REG_CAN0_MDL7 (0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */\r
+#define REG_CAN0_MDH7 (0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */\r
+#define REG_CAN0_MCR7 (0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */\r
+#else\r
+#define REG_CAN0_MR (*(RwReg*)0x400B4000U) /**< \brief (CAN0) Mode Register */\r
+#define REG_CAN0_IER (*(WoReg*)0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */\r
+#define REG_CAN0_IDR (*(WoReg*)0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */\r
+#define REG_CAN0_IMR (*(RoReg*)0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */\r
+#define REG_CAN0_SR (*(RoReg*)0x400B4010U) /**< \brief (CAN0) Status Register */\r
+#define REG_CAN0_BR (*(RwReg*)0x400B4014U) /**< \brief (CAN0) Baudrate Register */\r
+#define REG_CAN0_TIM (*(RoReg*)0x400B4018U) /**< \brief (CAN0) Timer Register */\r
+#define REG_CAN0_TIMESTP (*(RoReg*)0x400B401CU) /**< \brief (CAN0) Timestamp Register */\r
+#define REG_CAN0_ECR (*(RoReg*)0x400B4020U) /**< \brief (CAN0) Error Counter Register */\r
+#define REG_CAN0_TCR (*(WoReg*)0x400B4024U) /**< \brief (CAN0) Transfer Command Register */\r
+#define REG_CAN0_ACR (*(WoReg*)0x400B4028U) /**< \brief (CAN0) Abort Command Register */\r
+#define REG_CAN0_WPMR (*(RwReg*)0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */\r
+#define REG_CAN0_WPSR (*(RoReg*)0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */\r
+#define REG_CAN0_MMR0 (*(RwReg*)0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */\r
+#define REG_CAN0_MAM0 (*(RwReg*)0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */\r
+#define REG_CAN0_MID0 (*(RwReg*)0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */\r
+#define REG_CAN0_MFID0 (*(RoReg*)0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */\r
+#define REG_CAN0_MSR0 (*(RoReg*)0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */\r
+#define REG_CAN0_MDL0 (*(RwReg*)0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */\r
+#define REG_CAN0_MDH0 (*(RwReg*)0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */\r
+#define REG_CAN0_MCR0 (*(WoReg*)0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */\r
+#define REG_CAN0_MMR1 (*(RwReg*)0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */\r
+#define REG_CAN0_MAM1 (*(RwReg*)0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */\r
+#define REG_CAN0_MID1 (*(RwReg*)0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */\r
+#define REG_CAN0_MFID1 (*(RoReg*)0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */\r
+#define REG_CAN0_MSR1 (*(RoReg*)0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */\r
+#define REG_CAN0_MDL1 (*(RwReg*)0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */\r
+#define REG_CAN0_MDH1 (*(RwReg*)0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */\r
+#define REG_CAN0_MCR1 (*(WoReg*)0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */\r
+#define REG_CAN0_MMR2 (*(RwReg*)0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */\r
+#define REG_CAN0_MAM2 (*(RwReg*)0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */\r
+#define REG_CAN0_MID2 (*(RwReg*)0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */\r
+#define REG_CAN0_MFID2 (*(RoReg*)0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */\r
+#define REG_CAN0_MSR2 (*(RoReg*)0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */\r
+#define REG_CAN0_MDL2 (*(RwReg*)0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */\r
+#define REG_CAN0_MDH2 (*(RwReg*)0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */\r
+#define REG_CAN0_MCR2 (*(WoReg*)0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */\r
+#define REG_CAN0_MMR3 (*(RwReg*)0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */\r
+#define REG_CAN0_MAM3 (*(RwReg*)0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */\r
+#define REG_CAN0_MID3 (*(RwReg*)0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */\r
+#define REG_CAN0_MFID3 (*(RoReg*)0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */\r
+#define REG_CAN0_MSR3 (*(RoReg*)0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */\r
+#define REG_CAN0_MDL3 (*(RwReg*)0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */\r
+#define REG_CAN0_MDH3 (*(RwReg*)0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */\r
+#define REG_CAN0_MCR3 (*(WoReg*)0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */\r
+#define REG_CAN0_MMR4 (*(RwReg*)0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */\r
+#define REG_CAN0_MAM4 (*(RwReg*)0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */\r
+#define REG_CAN0_MID4 (*(RwReg*)0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */\r
+#define REG_CAN0_MFID4 (*(RoReg*)0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */\r
+#define REG_CAN0_MSR4 (*(RoReg*)0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */\r
+#define REG_CAN0_MDL4 (*(RwReg*)0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */\r
+#define REG_CAN0_MDH4 (*(RwReg*)0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */\r
+#define REG_CAN0_MCR4 (*(WoReg*)0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */\r
+#define REG_CAN0_MMR5 (*(RwReg*)0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */\r
+#define REG_CAN0_MAM5 (*(RwReg*)0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */\r
+#define REG_CAN0_MID5 (*(RwReg*)0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */\r
+#define REG_CAN0_MFID5 (*(RoReg*)0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */\r
+#define REG_CAN0_MSR5 (*(RoReg*)0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */\r
+#define REG_CAN0_MDL5 (*(RwReg*)0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */\r
+#define REG_CAN0_MDH5 (*(RwReg*)0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */\r
+#define REG_CAN0_MCR5 (*(WoReg*)0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */\r
+#define REG_CAN0_MMR6 (*(RwReg*)0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */\r
+#define REG_CAN0_MAM6 (*(RwReg*)0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */\r
+#define REG_CAN0_MID6 (*(RwReg*)0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */\r
+#define REG_CAN0_MFID6 (*(RoReg*)0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */\r
+#define REG_CAN0_MSR6 (*(RoReg*)0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */\r
+#define REG_CAN0_MDL6 (*(RwReg*)0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */\r
+#define REG_CAN0_MDH6 (*(RwReg*)0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */\r
+#define REG_CAN0_MCR6 (*(WoReg*)0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */\r
+#define REG_CAN0_MMR7 (*(RwReg*)0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */\r
+#define REG_CAN0_MAM7 (*(RwReg*)0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */\r
+#define REG_CAN0_MID7 (*(RwReg*)0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */\r
+#define REG_CAN0_MFID7 (*(RoReg*)0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */\r
+#define REG_CAN0_MSR7 (*(RoReg*)0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */\r
+#define REG_CAN0_MDL7 (*(RwReg*)0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */\r
+#define REG_CAN0_MDH7 (*(RwReg*)0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */\r
+#define REG_CAN0_MCR7 (*(WoReg*)0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_CAN0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_CAN1_INSTANCE_\r
+#define _SAM3XA_CAN1_INSTANCE_\r
+\r
+/* ========== Register definition for CAN1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CAN1_MR (0x400B8000U) /**< \brief (CAN1) Mode Register */\r
+#define REG_CAN1_IER (0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */\r
+#define REG_CAN1_IDR (0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */\r
+#define REG_CAN1_IMR (0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */\r
+#define REG_CAN1_SR (0x400B8010U) /**< \brief (CAN1) Status Register */\r
+#define REG_CAN1_BR (0x400B8014U) /**< \brief (CAN1) Baudrate Register */\r
+#define REG_CAN1_TIM (0x400B8018U) /**< \brief (CAN1) Timer Register */\r
+#define REG_CAN1_TIMESTP (0x400B801CU) /**< \brief (CAN1) Timestamp Register */\r
+#define REG_CAN1_ECR (0x400B8020U) /**< \brief (CAN1) Error Counter Register */\r
+#define REG_CAN1_TCR (0x400B8024U) /**< \brief (CAN1) Transfer Command Register */\r
+#define REG_CAN1_ACR (0x400B8028U) /**< \brief (CAN1) Abort Command Register */\r
+#define REG_CAN1_WPMR (0x400B80E4U) /**< \brief (CAN1) Write Protect Mode Register */\r
+#define REG_CAN1_WPSR (0x400B80E8U) /**< \brief (CAN1) Write Protect Status Register */\r
+#define REG_CAN1_MMR0 (0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */\r
+#define REG_CAN1_MAM0 (0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */\r
+#define REG_CAN1_MID0 (0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */\r
+#define REG_CAN1_MFID0 (0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */\r
+#define REG_CAN1_MSR0 (0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */\r
+#define REG_CAN1_MDL0 (0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */\r
+#define REG_CAN1_MDH0 (0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */\r
+#define REG_CAN1_MCR0 (0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */\r
+#define REG_CAN1_MMR1 (0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */\r
+#define REG_CAN1_MAM1 (0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */\r
+#define REG_CAN1_MID1 (0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */\r
+#define REG_CAN1_MFID1 (0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */\r
+#define REG_CAN1_MSR1 (0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */\r
+#define REG_CAN1_MDL1 (0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */\r
+#define REG_CAN1_MDH1 (0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */\r
+#define REG_CAN1_MCR1 (0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */\r
+#define REG_CAN1_MMR2 (0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */\r
+#define REG_CAN1_MAM2 (0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */\r
+#define REG_CAN1_MID2 (0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */\r
+#define REG_CAN1_MFID2 (0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */\r
+#define REG_CAN1_MSR2 (0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */\r
+#define REG_CAN1_MDL2 (0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */\r
+#define REG_CAN1_MDH2 (0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */\r
+#define REG_CAN1_MCR2 (0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */\r
+#define REG_CAN1_MMR3 (0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */\r
+#define REG_CAN1_MAM3 (0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */\r
+#define REG_CAN1_MID3 (0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */\r
+#define REG_CAN1_MFID3 (0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */\r
+#define REG_CAN1_MSR3 (0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */\r
+#define REG_CAN1_MDL3 (0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */\r
+#define REG_CAN1_MDH3 (0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */\r
+#define REG_CAN1_MCR3 (0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */\r
+#define REG_CAN1_MMR4 (0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */\r
+#define REG_CAN1_MAM4 (0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */\r
+#define REG_CAN1_MID4 (0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */\r
+#define REG_CAN1_MFID4 (0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */\r
+#define REG_CAN1_MSR4 (0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */\r
+#define REG_CAN1_MDL4 (0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */\r
+#define REG_CAN1_MDH4 (0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */\r
+#define REG_CAN1_MCR4 (0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */\r
+#define REG_CAN1_MMR5 (0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */\r
+#define REG_CAN1_MAM5 (0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */\r
+#define REG_CAN1_MID5 (0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */\r
+#define REG_CAN1_MFID5 (0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */\r
+#define REG_CAN1_MSR5 (0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */\r
+#define REG_CAN1_MDL5 (0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */\r
+#define REG_CAN1_MDH5 (0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */\r
+#define REG_CAN1_MCR5 (0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */\r
+#define REG_CAN1_MMR6 (0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */\r
+#define REG_CAN1_MAM6 (0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */\r
+#define REG_CAN1_MID6 (0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */\r
+#define REG_CAN1_MFID6 (0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */\r
+#define REG_CAN1_MSR6 (0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */\r
+#define REG_CAN1_MDL6 (0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */\r
+#define REG_CAN1_MDH6 (0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */\r
+#define REG_CAN1_MCR6 (0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */\r
+#define REG_CAN1_MMR7 (0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */\r
+#define REG_CAN1_MAM7 (0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */\r
+#define REG_CAN1_MID7 (0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */\r
+#define REG_CAN1_MFID7 (0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */\r
+#define REG_CAN1_MSR7 (0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */\r
+#define REG_CAN1_MDL7 (0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */\r
+#define REG_CAN1_MDH7 (0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */\r
+#define REG_CAN1_MCR7 (0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */\r
+#else\r
+#define REG_CAN1_MR (*(RwReg*)0x400B8000U) /**< \brief (CAN1) Mode Register */\r
+#define REG_CAN1_IER (*(WoReg*)0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */\r
+#define REG_CAN1_IDR (*(WoReg*)0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */\r
+#define REG_CAN1_IMR (*(RoReg*)0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */\r
+#define REG_CAN1_SR (*(RoReg*)0x400B8010U) /**< \brief (CAN1) Status Register */\r
+#define REG_CAN1_BR (*(RwReg*)0x400B8014U) /**< \brief (CAN1) Baudrate Register */\r
+#define REG_CAN1_TIM (*(RoReg*)0x400B8018U) /**< \brief (CAN1) Timer Register */\r
+#define REG_CAN1_TIMESTP (*(RoReg*)0x400B801CU) /**< \brief (CAN1) Timestamp Register */\r
+#define REG_CAN1_ECR (*(RoReg*)0x400B8020U) /**< \brief (CAN1) Error Counter Register */\r
+#define REG_CAN1_TCR (*(WoReg*)0x400B8024U) /**< \brief (CAN1) Transfer Command Register */\r
+#define REG_CAN1_ACR (*(WoReg*)0x400B8028U) /**< \brief (CAN1) Abort Command Register */\r
+#define REG_CAN1_WPMR (*(RwReg*)0x400B80E4U) /**< \brief (CAN1) Write Protect Mode Register */\r
+#define REG_CAN1_WPSR (*(RoReg*)0x400B80E8U) /**< \brief (CAN1) Write Protect Status Register */\r
+#define REG_CAN1_MMR0 (*(RwReg*)0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */\r
+#define REG_CAN1_MAM0 (*(RwReg*)0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */\r
+#define REG_CAN1_MID0 (*(RwReg*)0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */\r
+#define REG_CAN1_MFID0 (*(RoReg*)0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */\r
+#define REG_CAN1_MSR0 (*(RoReg*)0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */\r
+#define REG_CAN1_MDL0 (*(RwReg*)0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */\r
+#define REG_CAN1_MDH0 (*(RwReg*)0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */\r
+#define REG_CAN1_MCR0 (*(WoReg*)0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */\r
+#define REG_CAN1_MMR1 (*(RwReg*)0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */\r
+#define REG_CAN1_MAM1 (*(RwReg*)0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */\r
+#define REG_CAN1_MID1 (*(RwReg*)0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */\r
+#define REG_CAN1_MFID1 (*(RoReg*)0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */\r
+#define REG_CAN1_MSR1 (*(RoReg*)0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */\r
+#define REG_CAN1_MDL1 (*(RwReg*)0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */\r
+#define REG_CAN1_MDH1 (*(RwReg*)0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */\r
+#define REG_CAN1_MCR1 (*(WoReg*)0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */\r
+#define REG_CAN1_MMR2 (*(RwReg*)0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */\r
+#define REG_CAN1_MAM2 (*(RwReg*)0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */\r
+#define REG_CAN1_MID2 (*(RwReg*)0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */\r
+#define REG_CAN1_MFID2 (*(RoReg*)0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */\r
+#define REG_CAN1_MSR2 (*(RoReg*)0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */\r
+#define REG_CAN1_MDL2 (*(RwReg*)0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */\r
+#define REG_CAN1_MDH2 (*(RwReg*)0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */\r
+#define REG_CAN1_MCR2 (*(WoReg*)0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */\r
+#define REG_CAN1_MMR3 (*(RwReg*)0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */\r
+#define REG_CAN1_MAM3 (*(RwReg*)0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */\r
+#define REG_CAN1_MID3 (*(RwReg*)0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */\r
+#define REG_CAN1_MFID3 (*(RoReg*)0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */\r
+#define REG_CAN1_MSR3 (*(RoReg*)0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */\r
+#define REG_CAN1_MDL3 (*(RwReg*)0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */\r
+#define REG_CAN1_MDH3 (*(RwReg*)0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */\r
+#define REG_CAN1_MCR3 (*(WoReg*)0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */\r
+#define REG_CAN1_MMR4 (*(RwReg*)0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */\r
+#define REG_CAN1_MAM4 (*(RwReg*)0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */\r
+#define REG_CAN1_MID4 (*(RwReg*)0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */\r
+#define REG_CAN1_MFID4 (*(RoReg*)0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */\r
+#define REG_CAN1_MSR4 (*(RoReg*)0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */\r
+#define REG_CAN1_MDL4 (*(RwReg*)0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */\r
+#define REG_CAN1_MDH4 (*(RwReg*)0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */\r
+#define REG_CAN1_MCR4 (*(WoReg*)0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */\r
+#define REG_CAN1_MMR5 (*(RwReg*)0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */\r
+#define REG_CAN1_MAM5 (*(RwReg*)0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */\r
+#define REG_CAN1_MID5 (*(RwReg*)0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */\r
+#define REG_CAN1_MFID5 (*(RoReg*)0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */\r
+#define REG_CAN1_MSR5 (*(RoReg*)0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */\r
+#define REG_CAN1_MDL5 (*(RwReg*)0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */\r
+#define REG_CAN1_MDH5 (*(RwReg*)0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */\r
+#define REG_CAN1_MCR5 (*(WoReg*)0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */\r
+#define REG_CAN1_MMR6 (*(RwReg*)0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */\r
+#define REG_CAN1_MAM6 (*(RwReg*)0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */\r
+#define REG_CAN1_MID6 (*(RwReg*)0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */\r
+#define REG_CAN1_MFID6 (*(RoReg*)0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */\r
+#define REG_CAN1_MSR6 (*(RoReg*)0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */\r
+#define REG_CAN1_MDL6 (*(RwReg*)0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */\r
+#define REG_CAN1_MDH6 (*(RwReg*)0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */\r
+#define REG_CAN1_MCR6 (*(WoReg*)0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */\r
+#define REG_CAN1_MMR7 (*(RwReg*)0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */\r
+#define REG_CAN1_MAM7 (*(RwReg*)0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */\r
+#define REG_CAN1_MID7 (*(RwReg*)0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */\r
+#define REG_CAN1_MFID7 (*(RoReg*)0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */\r
+#define REG_CAN1_MSR7 (*(RoReg*)0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */\r
+#define REG_CAN1_MDL7 (*(RwReg*)0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */\r
+#define REG_CAN1_MDH7 (*(RwReg*)0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */\r
+#define REG_CAN1_MCR7 (*(WoReg*)0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_CAN1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_CHIPID_INSTANCE_\r
+#define _SAM3XA_CHIPID_INSTANCE_\r
+\r
+/* ========== Register definition for CHIPID peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CHIPID_CIDR (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */\r
+#define REG_CHIPID_EXID (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */\r
+#else\r
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */\r
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_CHIPID_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_DACC_INSTANCE_\r
+#define _SAM3XA_DACC_INSTANCE_\r
+\r
+/* ========== Register definition for DACC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_DACC_CR (0x400C8000U) /**< \brief (DACC) Control Register */\r
+#define REG_DACC_MR (0x400C8004U) /**< \brief (DACC) Mode Register */\r
+#define REG_DACC_CHER (0x400C8010U) /**< \brief (DACC) Channel Enable Register */\r
+#define REG_DACC_CHDR (0x400C8014U) /**< \brief (DACC) Channel Disable Register */\r
+#define REG_DACC_CHSR (0x400C8018U) /**< \brief (DACC) Channel Status Register */\r
+#define REG_DACC_CDR (0x400C8020U) /**< \brief (DACC) Conversion Data Register */\r
+#define REG_DACC_IER (0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */\r
+#define REG_DACC_IDR (0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */\r
+#define REG_DACC_IMR (0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */\r
+#define REG_DACC_ISR (0x400C8030U) /**< \brief (DACC) Interrupt Status Register */\r
+#define REG_DACC_ACR (0x400C8094U) /**< \brief (DACC) Analog Current Register */\r
+#define REG_DACC_WPMR (0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */\r
+#define REG_DACC_WPSR (0x400C80E8U) /**< \brief (DACC) Write Protect Status register */\r
+#define REG_DACC_TPR (0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */\r
+#define REG_DACC_TCR (0x400C810CU) /**< \brief (DACC) Transmit Counter Register */\r
+#define REG_DACC_TNPR (0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */\r
+#define REG_DACC_TNCR (0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */\r
+#define REG_DACC_PTCR (0x400C8120U) /**< \brief (DACC) Transfer Control Register */\r
+#define REG_DACC_PTSR (0x400C8124U) /**< \brief (DACC) Transfer Status Register */\r
+#else\r
+#define REG_DACC_CR (*(WoReg*)0x400C8000U) /**< \brief (DACC) Control Register */\r
+#define REG_DACC_MR (*(RwReg*)0x400C8004U) /**< \brief (DACC) Mode Register */\r
+#define REG_DACC_CHER (*(WoReg*)0x400C8010U) /**< \brief (DACC) Channel Enable Register */\r
+#define REG_DACC_CHDR (*(WoReg*)0x400C8014U) /**< \brief (DACC) Channel Disable Register */\r
+#define REG_DACC_CHSR (*(RoReg*)0x400C8018U) /**< \brief (DACC) Channel Status Register */\r
+#define REG_DACC_CDR (*(WoReg*)0x400C8020U) /**< \brief (DACC) Conversion Data Register */\r
+#define REG_DACC_IER (*(WoReg*)0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */\r
+#define REG_DACC_IDR (*(WoReg*)0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */\r
+#define REG_DACC_IMR (*(RoReg*)0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */\r
+#define REG_DACC_ISR (*(RoReg*)0x400C8030U) /**< \brief (DACC) Interrupt Status Register */\r
+#define REG_DACC_ACR (*(RwReg*)0x400C8094U) /**< \brief (DACC) Analog Current Register */\r
+#define REG_DACC_WPMR (*(RwReg*)0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */\r
+#define REG_DACC_WPSR (*(RoReg*)0x400C80E8U) /**< \brief (DACC) Write Protect Status register */\r
+#define REG_DACC_TPR (*(RwReg*)0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */\r
+#define REG_DACC_TCR (*(RwReg*)0x400C810CU) /**< \brief (DACC) Transmit Counter Register */\r
+#define REG_DACC_TNPR (*(RwReg*)0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */\r
+#define REG_DACC_TNCR (*(RwReg*)0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */\r
+#define REG_DACC_PTCR (*(WoReg*)0x400C8120U) /**< \brief (DACC) Transfer Control Register */\r
+#define REG_DACC_PTSR (*(RoReg*)0x400C8124U) /**< \brief (DACC) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_DACC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_DMAC_INSTANCE_\r
+#define _SAM3XA_DMAC_INSTANCE_\r
+\r
+/* ========== Register definition for DMAC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_DMAC_GCFG (0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */\r
+#define REG_DMAC_EN (0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */\r
+#define REG_DMAC_SREQ (0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */\r
+#define REG_DMAC_CREQ (0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */\r
+#define REG_DMAC_LAST (0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */\r
+#define REG_DMAC_EBCIER (0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */\r
+#define REG_DMAC_EBCIDR (0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */\r
+#define REG_DMAC_EBCIMR (0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */\r
+#define REG_DMAC_EBCISR (0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */\r
+#define REG_DMAC_CHER (0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */\r
+#define REG_DMAC_CHDR (0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */\r
+#define REG_DMAC_CHSR (0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */\r
+#define REG_DMAC_SADDR0 (0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */\r
+#define REG_DMAC_DADDR0 (0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */\r
+#define REG_DMAC_DSCR0 (0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */\r
+#define REG_DMAC_CTRLA0 (0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */\r
+#define REG_DMAC_CTRLB0 (0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */\r
+#define REG_DMAC_CFG0 (0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */\r
+#define REG_DMAC_SADDR1 (0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */\r
+#define REG_DMAC_DADDR1 (0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */\r
+#define REG_DMAC_DSCR1 (0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */\r
+#define REG_DMAC_CTRLA1 (0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */\r
+#define REG_DMAC_CTRLB1 (0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */\r
+#define REG_DMAC_CFG1 (0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */\r
+#define REG_DMAC_SADDR2 (0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */\r
+#define REG_DMAC_DADDR2 (0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */\r
+#define REG_DMAC_DSCR2 (0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */\r
+#define REG_DMAC_CTRLA2 (0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */\r
+#define REG_DMAC_CTRLB2 (0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */\r
+#define REG_DMAC_CFG2 (0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */\r
+#define REG_DMAC_SADDR3 (0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */\r
+#define REG_DMAC_DADDR3 (0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */\r
+#define REG_DMAC_DSCR3 (0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */\r
+#define REG_DMAC_CTRLA3 (0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */\r
+#define REG_DMAC_CTRLB3 (0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */\r
+#define REG_DMAC_CFG3 (0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */\r
+#define REG_DMAC_SADDR4 (0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */\r
+#define REG_DMAC_DADDR4 (0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */\r
+#define REG_DMAC_DSCR4 (0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */\r
+#define REG_DMAC_CTRLA4 (0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */\r
+#define REG_DMAC_CTRLB4 (0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */\r
+#define REG_DMAC_CFG4 (0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */\r
+#define REG_DMAC_SADDR5 (0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */\r
+#define REG_DMAC_DADDR5 (0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */\r
+#define REG_DMAC_DSCR5 (0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */\r
+#define REG_DMAC_CTRLA5 (0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */\r
+#define REG_DMAC_CTRLB5 (0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */\r
+#define REG_DMAC_CFG5 (0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */\r
+#define REG_DMAC_WPMR (0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */\r
+#define REG_DMAC_WPSR (0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */\r
+#else\r
+#define REG_DMAC_GCFG (*(RwReg*)0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */\r
+#define REG_DMAC_EN (*(RwReg*)0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */\r
+#define REG_DMAC_SREQ (*(RwReg*)0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */\r
+#define REG_DMAC_CREQ (*(RwReg*)0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */\r
+#define REG_DMAC_LAST (*(RwReg*)0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */\r
+#define REG_DMAC_EBCIER (*(WoReg*)0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */\r
+#define REG_DMAC_EBCIDR (*(WoReg*)0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */\r
+#define REG_DMAC_EBCIMR (*(RoReg*)0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */\r
+#define REG_DMAC_EBCISR (*(RoReg*)0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */\r
+#define REG_DMAC_CHER (*(WoReg*)0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */\r
+#define REG_DMAC_CHDR (*(WoReg*)0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */\r
+#define REG_DMAC_CHSR (*(RoReg*)0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */\r
+#define REG_DMAC_SADDR0 (*(RwReg*)0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */\r
+#define REG_DMAC_DADDR0 (*(RwReg*)0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */\r
+#define REG_DMAC_DSCR0 (*(RwReg*)0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */\r
+#define REG_DMAC_CTRLA0 (*(RwReg*)0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */\r
+#define REG_DMAC_CTRLB0 (*(RwReg*)0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */\r
+#define REG_DMAC_CFG0 (*(RwReg*)0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */\r
+#define REG_DMAC_SADDR1 (*(RwReg*)0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */\r
+#define REG_DMAC_DADDR1 (*(RwReg*)0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */\r
+#define REG_DMAC_DSCR1 (*(RwReg*)0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */\r
+#define REG_DMAC_CTRLA1 (*(RwReg*)0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */\r
+#define REG_DMAC_CTRLB1 (*(RwReg*)0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */\r
+#define REG_DMAC_CFG1 (*(RwReg*)0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */\r
+#define REG_DMAC_SADDR2 (*(RwReg*)0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */\r
+#define REG_DMAC_DADDR2 (*(RwReg*)0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */\r
+#define REG_DMAC_DSCR2 (*(RwReg*)0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */\r
+#define REG_DMAC_CTRLA2 (*(RwReg*)0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */\r
+#define REG_DMAC_CTRLB2 (*(RwReg*)0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */\r
+#define REG_DMAC_CFG2 (*(RwReg*)0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */\r
+#define REG_DMAC_SADDR3 (*(RwReg*)0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */\r
+#define REG_DMAC_DADDR3 (*(RwReg*)0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */\r
+#define REG_DMAC_DSCR3 (*(RwReg*)0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */\r
+#define REG_DMAC_CTRLA3 (*(RwReg*)0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */\r
+#define REG_DMAC_CTRLB3 (*(RwReg*)0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */\r
+#define REG_DMAC_CFG3 (*(RwReg*)0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */\r
+#define REG_DMAC_SADDR4 (*(RwReg*)0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */\r
+#define REG_DMAC_DADDR4 (*(RwReg*)0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */\r
+#define REG_DMAC_DSCR4 (*(RwReg*)0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */\r
+#define REG_DMAC_CTRLA4 (*(RwReg*)0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */\r
+#define REG_DMAC_CTRLB4 (*(RwReg*)0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */\r
+#define REG_DMAC_CFG4 (*(RwReg*)0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */\r
+#define REG_DMAC_SADDR5 (*(RwReg*)0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */\r
+#define REG_DMAC_DADDR5 (*(RwReg*)0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */\r
+#define REG_DMAC_DSCR5 (*(RwReg*)0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */\r
+#define REG_DMAC_CTRLA5 (*(RwReg*)0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */\r
+#define REG_DMAC_CTRLB5 (*(RwReg*)0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */\r
+#define REG_DMAC_CFG5 (*(RwReg*)0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */\r
+#define REG_DMAC_WPMR (*(RwReg*)0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */\r
+#define REG_DMAC_WPSR (*(RoReg*)0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_DMAC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_EFC0_INSTANCE_\r
+#define _SAM3XA_EFC0_INSTANCE_\r
+\r
+/* ========== Register definition for EFC0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_EFC0_FMR (0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */\r
+#define REG_EFC0_FCR (0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */\r
+#define REG_EFC0_FSR (0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */\r
+#define REG_EFC0_FRR (0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */\r
+#else\r
+#define REG_EFC0_FMR (*(RwReg*)0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */\r
+#define REG_EFC0_FCR (*(WoReg*)0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */\r
+#define REG_EFC0_FSR (*(RoReg*)0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */\r
+#define REG_EFC0_FRR (*(RoReg*)0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_EFC0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_EFC1_INSTANCE_\r
+#define _SAM3XA_EFC1_INSTANCE_\r
+\r
+/* ========== Register definition for EFC1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_EFC1_FMR (0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */\r
+#define REG_EFC1_FCR (0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */\r
+#define REG_EFC1_FSR (0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */\r
+#define REG_EFC1_FRR (0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */\r
+#else\r
+#define REG_EFC1_FMR (*(RwReg*)0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */\r
+#define REG_EFC1_FCR (*(WoReg*)0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */\r
+#define REG_EFC1_FSR (*(RoReg*)0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */\r
+#define REG_EFC1_FRR (*(RoReg*)0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_EFC1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_EMAC_INSTANCE_\r
+#define _SAM3XA_EMAC_INSTANCE_\r
+\r
+/* ========== Register definition for EMAC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_EMAC_NCR (0x400B0000U) /**< \brief (EMAC) Network Control Register */\r
+#define REG_EMAC_NCFGR (0x400B0004U) /**< \brief (EMAC) Network Configuration Register */\r
+#define REG_EMAC_NSR (0x400B0008U) /**< \brief (EMAC) Network Status Register */\r
+#define REG_EMAC_TSR (0x400B0014U) /**< \brief (EMAC) Transmit Status Register */\r
+#define REG_EMAC_RBQP (0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */\r
+#define REG_EMAC_TBQP (0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */\r
+#define REG_EMAC_RSR (0x400B0020U) /**< \brief (EMAC) Receive Status Register */\r
+#define REG_EMAC_ISR (0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */\r
+#define REG_EMAC_IER (0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */\r
+#define REG_EMAC_IDR (0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */\r
+#define REG_EMAC_IMR (0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */\r
+#define REG_EMAC_MAN (0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */\r
+#define REG_EMAC_PTR (0x400B0038U) /**< \brief (EMAC) Pause Time Register */\r
+#define REG_EMAC_PFR (0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */\r
+#define REG_EMAC_FTO (0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */\r
+#define REG_EMAC_SCF (0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */\r
+#define REG_EMAC_MCF (0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */\r
+#define REG_EMAC_FRO (0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */\r
+#define REG_EMAC_FCSE (0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */\r
+#define REG_EMAC_ALE (0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */\r
+#define REG_EMAC_DTF (0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */\r
+#define REG_EMAC_LCOL (0x400B005CU) /**< \brief (EMAC) Late Collisions Register */\r
+#define REG_EMAC_ECOL (0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */\r
+#define REG_EMAC_TUND (0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */\r
+#define REG_EMAC_CSE (0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */\r
+#define REG_EMAC_RRE (0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */\r
+#define REG_EMAC_ROV (0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */\r
+#define REG_EMAC_RSE (0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */\r
+#define REG_EMAC_ELE (0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */\r
+#define REG_EMAC_RJA (0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */\r
+#define REG_EMAC_USF (0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */\r
+#define REG_EMAC_STE (0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */\r
+#define REG_EMAC_RLE (0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */\r
+#define REG_EMAC_HRB (0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */\r
+#define REG_EMAC_HRT (0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */\r
+#define REG_EMAC_SA1B (0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */\r
+#define REG_EMAC_SA1T (0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */\r
+#define REG_EMAC_SA2B (0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */\r
+#define REG_EMAC_SA2T (0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */\r
+#define REG_EMAC_SA3B (0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */\r
+#define REG_EMAC_SA3T (0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */\r
+#define REG_EMAC_SA4B (0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */\r
+#define REG_EMAC_SA4T (0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */\r
+#define REG_EMAC_TID (0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */\r
+#define REG_EMAC_USRIO (0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */\r
+#else\r
+#define REG_EMAC_NCR (*(RwReg*)0x400B0000U) /**< \brief (EMAC) Network Control Register */\r
+#define REG_EMAC_NCFGR (*(RwReg*)0x400B0004U) /**< \brief (EMAC) Network Configuration Register */\r
+#define REG_EMAC_NSR (*(RoReg*)0x400B0008U) /**< \brief (EMAC) Network Status Register */\r
+#define REG_EMAC_TSR (*(RwReg*)0x400B0014U) /**< \brief (EMAC) Transmit Status Register */\r
+#define REG_EMAC_RBQP (*(RwReg*)0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */\r
+#define REG_EMAC_TBQP (*(RwReg*)0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */\r
+#define REG_EMAC_RSR (*(RwReg*)0x400B0020U) /**< \brief (EMAC) Receive Status Register */\r
+#define REG_EMAC_ISR (*(RwReg*)0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */\r
+#define REG_EMAC_IER (*(WoReg*)0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */\r
+#define REG_EMAC_IDR (*(WoReg*)0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */\r
+#define REG_EMAC_IMR (*(RoReg*)0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */\r
+#define REG_EMAC_MAN (*(RwReg*)0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */\r
+#define REG_EMAC_PTR (*(RwReg*)0x400B0038U) /**< \brief (EMAC) Pause Time Register */\r
+#define REG_EMAC_PFR (*(RwReg*)0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */\r
+#define REG_EMAC_FTO (*(RwReg*)0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */\r
+#define REG_EMAC_SCF (*(RwReg*)0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */\r
+#define REG_EMAC_MCF (*(RwReg*)0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */\r
+#define REG_EMAC_FRO (*(RwReg*)0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */\r
+#define REG_EMAC_FCSE (*(RwReg*)0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */\r
+#define REG_EMAC_ALE (*(RwReg*)0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */\r
+#define REG_EMAC_DTF (*(RwReg*)0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */\r
+#define REG_EMAC_LCOL (*(RwReg*)0x400B005CU) /**< \brief (EMAC) Late Collisions Register */\r
+#define REG_EMAC_ECOL (*(RwReg*)0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */\r
+#define REG_EMAC_TUND (*(RwReg*)0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */\r
+#define REG_EMAC_CSE (*(RwReg*)0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */\r
+#define REG_EMAC_RRE (*(RwReg*)0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */\r
+#define REG_EMAC_ROV (*(RwReg*)0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */\r
+#define REG_EMAC_RSE (*(RwReg*)0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */\r
+#define REG_EMAC_ELE (*(RwReg*)0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */\r
+#define REG_EMAC_RJA (*(RwReg*)0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */\r
+#define REG_EMAC_USF (*(RwReg*)0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */\r
+#define REG_EMAC_STE (*(RwReg*)0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */\r
+#define REG_EMAC_RLE (*(RwReg*)0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */\r
+#define REG_EMAC_HRB (*(RwReg*)0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */\r
+#define REG_EMAC_HRT (*(RwReg*)0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */\r
+#define REG_EMAC_SA1B (*(RwReg*)0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */\r
+#define REG_EMAC_SA1T (*(RwReg*)0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */\r
+#define REG_EMAC_SA2B (*(RwReg*)0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */\r
+#define REG_EMAC_SA2T (*(RwReg*)0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */\r
+#define REG_EMAC_SA3B (*(RwReg*)0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */\r
+#define REG_EMAC_SA3T (*(RwReg*)0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */\r
+#define REG_EMAC_SA4B (*(RwReg*)0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */\r
+#define REG_EMAC_SA4T (*(RwReg*)0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */\r
+#define REG_EMAC_TID (*(RwReg*)0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */\r
+#define REG_EMAC_USRIO (*(RwReg*)0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_EMAC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_GPBR_INSTANCE_\r
+#define _SAM3XA_GPBR_INSTANCE_\r
+\r
+/* ========== Register definition for GPBR peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_GPBR_GPBR (0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */\r
+#else\r
+#define REG_GPBR_GPBR (*(RwReg*)0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_GPBR_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_HSMCI_INSTANCE_\r
+#define _SAM3XA_HSMCI_INSTANCE_\r
+\r
+/* ========== Register definition for HSMCI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */\r
+#define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */\r
+#define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */\r
+#define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */\r
+#define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */\r
+#define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */\r
+#define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */\r
+#define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */\r
+#define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */\r
+#define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */\r
+#define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */\r
+#define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */\r
+#define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */\r
+#define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */\r
+#define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */\r
+#define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */\r
+#define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */\r
+#define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */\r
+#define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */\r
+#define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */\r
+#else\r
+#define REG_HSMCI_CR (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */\r
+#define REG_HSMCI_MR (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */\r
+#define REG_HSMCI_DTOR (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */\r
+#define REG_HSMCI_SDCR (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */\r
+#define REG_HSMCI_ARGR (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */\r
+#define REG_HSMCI_CMDR (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */\r
+#define REG_HSMCI_BLKR (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */\r
+#define REG_HSMCI_CSTOR (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */\r
+#define REG_HSMCI_RSPR (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */\r
+#define REG_HSMCI_RDR (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */\r
+#define REG_HSMCI_TDR (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */\r
+#define REG_HSMCI_SR (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */\r
+#define REG_HSMCI_IER (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */\r
+#define REG_HSMCI_IDR (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */\r
+#define REG_HSMCI_IMR (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */\r
+#define REG_HSMCI_DMA (*(RwReg*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */\r
+#define REG_HSMCI_CFG (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */\r
+#define REG_HSMCI_WPMR (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */\r
+#define REG_HSMCI_WPSR (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */\r
+#define REG_HSMCI_FIFO (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_HSMCI_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_MATRIX_INSTANCE_\r
+#define _SAM3XA_MATRIX_INSTANCE_\r
+\r
+/* ========== Register definition for MATRIX peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_MATRIX_MCFG (0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */\r
+#define REG_MATRIX_SCFG (0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */\r
+#define REG_MATRIX_PRAS0 (0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */\r
+#define REG_MATRIX_PRAS1 (0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */\r
+#define REG_MATRIX_PRAS2 (0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */\r
+#define REG_MATRIX_PRAS3 (0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */\r
+#define REG_MATRIX_PRAS4 (0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */\r
+#define REG_MATRIX_PRAS5 (0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */\r
+#define REG_MATRIX_PRAS6 (0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */\r
+#define REG_MATRIX_PRAS7 (0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */\r
+#define REG_MATRIX_PRAS8 (0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */\r
+#define REG_MATRIX_MRCR (0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */\r
+#define REG_CCFG_SYSIO (0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */\r
+#define REG_MATRIX_WPMR (0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */\r
+#define REG_MATRIX_WPSR (0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */\r
+#else\r
+#define REG_MATRIX_MCFG (*(RwReg*)0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */\r
+#define REG_MATRIX_SCFG (*(RwReg*)0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */\r
+#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */\r
+#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */\r
+#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */\r
+#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */\r
+#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */\r
+#define REG_MATRIX_PRAS5 (*(RwReg*)0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */\r
+#define REG_MATRIX_PRAS6 (*(RwReg*)0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */\r
+#define REG_MATRIX_PRAS7 (*(RwReg*)0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */\r
+#define REG_MATRIX_PRAS8 (*(RwReg*)0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */\r
+#define REG_MATRIX_MRCR (*(RwReg*)0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */\r
+#define REG_CCFG_SYSIO (*(RwReg*)0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */\r
+#define REG_MATRIX_WPMR (*(RwReg*)0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */\r
+#define REG_MATRIX_WPSR (*(RoReg*)0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_MATRIX_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PIOA_INSTANCE_\r
+#define _SAM3XA_PIOA_INSTANCE_\r
+\r
+/* ========== Register definition for PIOA peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */\r
+#define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */\r
+#define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */\r
+#define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */\r
+#define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */\r
+#define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */\r
+#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */\r
+#define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */\r
+#define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */\r
+#define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */\r
+#define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */\r
+#define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */\r
+#define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */\r
+#define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */\r
+#define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */\r
+#define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */\r
+#define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */\r
+#define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */\r
+#define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */\r
+#define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */\r
+#define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */\r
+#define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */\r
+#define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */\r
+#define REG_PIOA_ABSR (0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */\r
+#define REG_PIOA_SCIFSR (0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOA_DIFSR (0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */\r
+#define REG_PIOA_IFDGSR (0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */\r
+#define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */\r
+#define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */\r
+#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */\r
+#define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */\r
+#define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */\r
+#define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */\r
+#define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */\r
+#define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */\r
+#define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */\r
+#define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */\r
+#else\r
+#define REG_PIOA_PER (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */\r
+#define REG_PIOA_PDR (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */\r
+#define REG_PIOA_PSR (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */\r
+#define REG_PIOA_OER (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */\r
+#define REG_PIOA_ODR (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */\r
+#define REG_PIOA_OSR (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */\r
+#define REG_PIOA_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */\r
+#define REG_PIOA_IFDR (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */\r
+#define REG_PIOA_IFSR (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */\r
+#define REG_PIOA_SODR (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */\r
+#define REG_PIOA_CODR (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */\r
+#define REG_PIOA_ODSR (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */\r
+#define REG_PIOA_PDSR (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */\r
+#define REG_PIOA_IER (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */\r
+#define REG_PIOA_IDR (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */\r
+#define REG_PIOA_IMR (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */\r
+#define REG_PIOA_ISR (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */\r
+#define REG_PIOA_MDER (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */\r
+#define REG_PIOA_MDDR (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */\r
+#define REG_PIOA_MDSR (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */\r
+#define REG_PIOA_PUDR (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */\r
+#define REG_PIOA_PUER (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */\r
+#define REG_PIOA_PUSR (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */\r
+#define REG_PIOA_ABSR (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */\r
+#define REG_PIOA_SCIFSR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOA_DIFSR (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */\r
+#define REG_PIOA_IFDGSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOA_SCDR (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOA_OWER (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */\r
+#define REG_PIOA_OWDR (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */\r
+#define REG_PIOA_OWSR (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */\r
+#define REG_PIOA_AIMER (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOA_AIMDR (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOA_AIMMR (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOA_ESR (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */\r
+#define REG_PIOA_LSR (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */\r
+#define REG_PIOA_ELSR (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */\r
+#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */\r
+#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */\r
+#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */\r
+#define REG_PIOA_WPMR (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */\r
+#define REG_PIOA_WPSR (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_PIOA_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PIOB_INSTANCE_\r
+#define _SAM3XA_PIOB_INSTANCE_\r
+\r
+/* ========== Register definition for PIOB peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */\r
+#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */\r
+#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */\r
+#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */\r
+#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */\r
+#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */\r
+#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */\r
+#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */\r
+#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */\r
+#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */\r
+#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */\r
+#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */\r
+#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */\r
+#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */\r
+#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */\r
+#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */\r
+#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */\r
+#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */\r
+#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */\r
+#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */\r
+#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */\r
+#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */\r
+#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */\r
+#define REG_PIOB_ABSR (0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */\r
+#define REG_PIOB_SCIFSR (0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOB_DIFSR (0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */\r
+#define REG_PIOB_IFDGSR (0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */\r
+#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */\r
+#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */\r
+#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */\r
+#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */\r
+#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */\r
+#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */\r
+#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */\r
+#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */\r
+#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */\r
+#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */\r
+#else\r
+#define REG_PIOB_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */\r
+#define REG_PIOB_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */\r
+#define REG_PIOB_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */\r
+#define REG_PIOB_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */\r
+#define REG_PIOB_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */\r
+#define REG_PIOB_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */\r
+#define REG_PIOB_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */\r
+#define REG_PIOB_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */\r
+#define REG_PIOB_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */\r
+#define REG_PIOB_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */\r
+#define REG_PIOB_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */\r
+#define REG_PIOB_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */\r
+#define REG_PIOB_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */\r
+#define REG_PIOB_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */\r
+#define REG_PIOB_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */\r
+#define REG_PIOB_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */\r
+#define REG_PIOB_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */\r
+#define REG_PIOB_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */\r
+#define REG_PIOB_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */\r
+#define REG_PIOB_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */\r
+#define REG_PIOB_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */\r
+#define REG_PIOB_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */\r
+#define REG_PIOB_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */\r
+#define REG_PIOB_ABSR (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */\r
+#define REG_PIOB_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOB_DIFSR (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */\r
+#define REG_PIOB_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOB_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOB_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */\r
+#define REG_PIOB_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */\r
+#define REG_PIOB_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */\r
+#define REG_PIOB_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOB_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOB_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOB_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */\r
+#define REG_PIOB_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */\r
+#define REG_PIOB_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */\r
+#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */\r
+#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */\r
+#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */\r
+#define REG_PIOB_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */\r
+#define REG_PIOB_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_PIOB_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PIOC_INSTANCE_\r
+#define _SAM3XA_PIOC_INSTANCE_\r
+\r
+/* ========== Register definition for PIOC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */\r
+#define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */\r
+#define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */\r
+#define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */\r
+#define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */\r
+#define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */\r
+#define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */\r
+#define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */\r
+#define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */\r
+#define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */\r
+#define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */\r
+#define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */\r
+#define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */\r
+#define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */\r
+#define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */\r
+#define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */\r
+#define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */\r
+#define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */\r
+#define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */\r
+#define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */\r
+#define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */\r
+#define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */\r
+#define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */\r
+#define REG_PIOC_ABSR (0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */\r
+#define REG_PIOC_SCIFSR (0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOC_DIFSR (0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */\r
+#define REG_PIOC_IFDGSR (0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */\r
+#define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */\r
+#define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */\r
+#define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */\r
+#define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */\r
+#define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */\r
+#define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */\r
+#define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */\r
+#define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */\r
+#define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */\r
+#define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */\r
+#else\r
+#define REG_PIOC_PER (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */\r
+#define REG_PIOC_PDR (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */\r
+#define REG_PIOC_PSR (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */\r
+#define REG_PIOC_OER (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */\r
+#define REG_PIOC_ODR (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */\r
+#define REG_PIOC_OSR (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */\r
+#define REG_PIOC_IFER (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */\r
+#define REG_PIOC_IFDR (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */\r
+#define REG_PIOC_IFSR (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */\r
+#define REG_PIOC_SODR (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */\r
+#define REG_PIOC_CODR (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */\r
+#define REG_PIOC_ODSR (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */\r
+#define REG_PIOC_PDSR (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */\r
+#define REG_PIOC_IER (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */\r
+#define REG_PIOC_IDR (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */\r
+#define REG_PIOC_IMR (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */\r
+#define REG_PIOC_ISR (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */\r
+#define REG_PIOC_MDER (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */\r
+#define REG_PIOC_MDDR (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */\r
+#define REG_PIOC_MDSR (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */\r
+#define REG_PIOC_PUDR (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */\r
+#define REG_PIOC_PUER (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */\r
+#define REG_PIOC_PUSR (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */\r
+#define REG_PIOC_ABSR (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */\r
+#define REG_PIOC_SCIFSR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOC_DIFSR (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */\r
+#define REG_PIOC_IFDGSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOC_SCDR (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOC_OWER (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */\r
+#define REG_PIOC_OWDR (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */\r
+#define REG_PIOC_OWSR (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */\r
+#define REG_PIOC_AIMER (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOC_AIMDR (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOC_AIMMR (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOC_ESR (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */\r
+#define REG_PIOC_LSR (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */\r
+#define REG_PIOC_ELSR (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */\r
+#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */\r
+#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */\r
+#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */\r
+#define REG_PIOC_WPMR (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */\r
+#define REG_PIOC_WPSR (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_PIOC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PIOD_INSTANCE_\r
+#define _SAM3XA_PIOD_INSTANCE_\r
+\r
+/* ========== Register definition for PIOD peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */\r
+#define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */\r
+#define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */\r
+#define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */\r
+#define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */\r
+#define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */\r
+#define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */\r
+#define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */\r
+#define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */\r
+#define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */\r
+#define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */\r
+#define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */\r
+#define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */\r
+#define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */\r
+#define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */\r
+#define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */\r
+#define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */\r
+#define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */\r
+#define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */\r
+#define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */\r
+#define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */\r
+#define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */\r
+#define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */\r
+#define REG_PIOD_ABSR (0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */\r
+#define REG_PIOD_SCIFSR (0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOD_DIFSR (0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */\r
+#define REG_PIOD_IFDGSR (0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */\r
+#define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */\r
+#define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */\r
+#define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */\r
+#define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */\r
+#define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */\r
+#define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */\r
+#define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */\r
+#define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */\r
+#define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */\r
+#define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */\r
+#else\r
+#define REG_PIOD_PER (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */\r
+#define REG_PIOD_PDR (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */\r
+#define REG_PIOD_PSR (*(RoReg*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */\r
+#define REG_PIOD_OER (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */\r
+#define REG_PIOD_ODR (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */\r
+#define REG_PIOD_OSR (*(RoReg*)0x400E1418U) /**< \brief (PIOD) Output Status Register */\r
+#define REG_PIOD_IFER (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */\r
+#define REG_PIOD_IFDR (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */\r
+#define REG_PIOD_IFSR (*(RoReg*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */\r
+#define REG_PIOD_SODR (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */\r
+#define REG_PIOD_CODR (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */\r
+#define REG_PIOD_ODSR (*(RwReg*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */\r
+#define REG_PIOD_PDSR (*(RoReg*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */\r
+#define REG_PIOD_IER (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */\r
+#define REG_PIOD_IDR (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */\r
+#define REG_PIOD_IMR (*(RoReg*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */\r
+#define REG_PIOD_ISR (*(RoReg*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */\r
+#define REG_PIOD_MDER (*(WoReg*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */\r
+#define REG_PIOD_MDDR (*(WoReg*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */\r
+#define REG_PIOD_MDSR (*(RoReg*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */\r
+#define REG_PIOD_PUDR (*(WoReg*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */\r
+#define REG_PIOD_PUER (*(WoReg*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */\r
+#define REG_PIOD_PUSR (*(RoReg*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */\r
+#define REG_PIOD_ABSR (*(RwReg*)0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */\r
+#define REG_PIOD_SCIFSR (*(WoReg*)0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOD_DIFSR (*(WoReg*)0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */\r
+#define REG_PIOD_IFDGSR (*(RoReg*)0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOD_SCDR (*(RwReg*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOD_OWER (*(WoReg*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */\r
+#define REG_PIOD_OWDR (*(WoReg*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */\r
+#define REG_PIOD_OWSR (*(RoReg*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */\r
+#define REG_PIOD_AIMER (*(WoReg*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOD_AIMDR (*(WoReg*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOD_AIMMR (*(RoReg*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOD_ESR (*(WoReg*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */\r
+#define REG_PIOD_LSR (*(WoReg*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */\r
+#define REG_PIOD_ELSR (*(RoReg*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */\r
+#define REG_PIOD_FELLSR (*(WoReg*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */\r
+#define REG_PIOD_REHLSR (*(WoReg*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */\r
+#define REG_PIOD_FRLHSR (*(RoReg*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOD_LOCKSR (*(RoReg*)0x400E14E0U) /**< \brief (PIOD) Lock Status */\r
+#define REG_PIOD_WPMR (*(RwReg*)0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */\r
+#define REG_PIOD_WPSR (*(RoReg*)0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_PIOD_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PIOE_INSTANCE_\r
+#define _SAM3XA_PIOE_INSTANCE_\r
+\r
+/* ========== Register definition for PIOE peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */\r
+#define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */\r
+#define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */\r
+#define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */\r
+#define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */\r
+#define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */\r
+#define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */\r
+#define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */\r
+#define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */\r
+#define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */\r
+#define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */\r
+#define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */\r
+#define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */\r
+#define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */\r
+#define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */\r
+#define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */\r
+#define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */\r
+#define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */\r
+#define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */\r
+#define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */\r
+#define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */\r
+#define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */\r
+#define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */\r
+#define REG_PIOE_ABSR (0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */\r
+#define REG_PIOE_SCIFSR (0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOE_DIFSR (0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */\r
+#define REG_PIOE_IFDGSR (0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */\r
+#define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */\r
+#define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */\r
+#define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */\r
+#define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */\r
+#define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */\r
+#define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */\r
+#define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */\r
+#define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */\r
+#define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */\r
+#define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */\r
+#else\r
+#define REG_PIOE_PER (*(WoReg*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */\r
+#define REG_PIOE_PDR (*(WoReg*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */\r
+#define REG_PIOE_PSR (*(RoReg*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */\r
+#define REG_PIOE_OER (*(WoReg*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */\r
+#define REG_PIOE_ODR (*(WoReg*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */\r
+#define REG_PIOE_OSR (*(RoReg*)0x400E1618U) /**< \brief (PIOE) Output Status Register */\r
+#define REG_PIOE_IFER (*(WoReg*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */\r
+#define REG_PIOE_IFDR (*(WoReg*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */\r
+#define REG_PIOE_IFSR (*(RoReg*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */\r
+#define REG_PIOE_SODR (*(WoReg*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */\r
+#define REG_PIOE_CODR (*(WoReg*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */\r
+#define REG_PIOE_ODSR (*(RwReg*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */\r
+#define REG_PIOE_PDSR (*(RoReg*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */\r
+#define REG_PIOE_IER (*(WoReg*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */\r
+#define REG_PIOE_IDR (*(WoReg*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */\r
+#define REG_PIOE_IMR (*(RoReg*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */\r
+#define REG_PIOE_ISR (*(RoReg*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */\r
+#define REG_PIOE_MDER (*(WoReg*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */\r
+#define REG_PIOE_MDDR (*(WoReg*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */\r
+#define REG_PIOE_MDSR (*(RoReg*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */\r
+#define REG_PIOE_PUDR (*(WoReg*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */\r
+#define REG_PIOE_PUER (*(WoReg*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */\r
+#define REG_PIOE_PUSR (*(RoReg*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */\r
+#define REG_PIOE_ABSR (*(RwReg*)0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */\r
+#define REG_PIOE_SCIFSR (*(WoReg*)0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOE_DIFSR (*(WoReg*)0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */\r
+#define REG_PIOE_IFDGSR (*(RoReg*)0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOE_SCDR (*(RwReg*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOE_OWER (*(WoReg*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */\r
+#define REG_PIOE_OWDR (*(WoReg*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */\r
+#define REG_PIOE_OWSR (*(RoReg*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */\r
+#define REG_PIOE_AIMER (*(WoReg*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOE_AIMDR (*(WoReg*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOE_AIMMR (*(RoReg*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOE_ESR (*(WoReg*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */\r
+#define REG_PIOE_LSR (*(WoReg*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */\r
+#define REG_PIOE_ELSR (*(RoReg*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */\r
+#define REG_PIOE_FELLSR (*(WoReg*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */\r
+#define REG_PIOE_REHLSR (*(WoReg*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */\r
+#define REG_PIOE_FRLHSR (*(RoReg*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOE_LOCKSR (*(RoReg*)0x400E16E0U) /**< \brief (PIOE) Lock Status */\r
+#define REG_PIOE_WPMR (*(RwReg*)0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */\r
+#define REG_PIOE_WPSR (*(RoReg*)0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_PIOE_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PIOF_INSTANCE_\r
+#define _SAM3XA_PIOF_INSTANCE_\r
+\r
+/* ========== Register definition for PIOF peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOF_PER (0x400E1800U) /**< \brief (PIOF) PIO Enable Register */\r
+#define REG_PIOF_PDR (0x400E1804U) /**< \brief (PIOF) PIO Disable Register */\r
+#define REG_PIOF_PSR (0x400E1808U) /**< \brief (PIOF) PIO Status Register */\r
+#define REG_PIOF_OER (0x400E1810U) /**< \brief (PIOF) Output Enable Register */\r
+#define REG_PIOF_ODR (0x400E1814U) /**< \brief (PIOF) Output Disable Register */\r
+#define REG_PIOF_OSR (0x400E1818U) /**< \brief (PIOF) Output Status Register */\r
+#define REG_PIOF_IFER (0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */\r
+#define REG_PIOF_IFDR (0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */\r
+#define REG_PIOF_IFSR (0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */\r
+#define REG_PIOF_SODR (0x400E1830U) /**< \brief (PIOF) Set Output Data Register */\r
+#define REG_PIOF_CODR (0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */\r
+#define REG_PIOF_ODSR (0x400E1838U) /**< \brief (PIOF) Output Data Status Register */\r
+#define REG_PIOF_PDSR (0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */\r
+#define REG_PIOF_IER (0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */\r
+#define REG_PIOF_IDR (0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */\r
+#define REG_PIOF_IMR (0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */\r
+#define REG_PIOF_ISR (0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */\r
+#define REG_PIOF_MDER (0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */\r
+#define REG_PIOF_MDDR (0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */\r
+#define REG_PIOF_MDSR (0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */\r
+#define REG_PIOF_PUDR (0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */\r
+#define REG_PIOF_PUER (0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */\r
+#define REG_PIOF_PUSR (0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */\r
+#define REG_PIOF_ABSR (0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */\r
+#define REG_PIOF_SCIFSR (0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOF_DIFSR (0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */\r
+#define REG_PIOF_IFDGSR (0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOF_SCDR (0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOF_OWER (0x400E18A0U) /**< \brief (PIOF) Output Write Enable */\r
+#define REG_PIOF_OWDR (0x400E18A4U) /**< \brief (PIOF) Output Write Disable */\r
+#define REG_PIOF_OWSR (0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */\r
+#define REG_PIOF_AIMER (0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOF_AIMDR (0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOF_AIMMR (0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOF_ESR (0x400E18C0U) /**< \brief (PIOF) Edge Select Register */\r
+#define REG_PIOF_LSR (0x400E18C4U) /**< \brief (PIOF) Level Select Register */\r
+#define REG_PIOF_ELSR (0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */\r
+#define REG_PIOF_FELLSR (0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */\r
+#define REG_PIOF_REHLSR (0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */\r
+#define REG_PIOF_FRLHSR (0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOF_LOCKSR (0x400E18E0U) /**< \brief (PIOF) Lock Status */\r
+#define REG_PIOF_WPMR (0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */\r
+#define REG_PIOF_WPSR (0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */\r
+#else\r
+#define REG_PIOF_PER (*(WoReg*)0x400E1800U) /**< \brief (PIOF) PIO Enable Register */\r
+#define REG_PIOF_PDR (*(WoReg*)0x400E1804U) /**< \brief (PIOF) PIO Disable Register */\r
+#define REG_PIOF_PSR (*(RoReg*)0x400E1808U) /**< \brief (PIOF) PIO Status Register */\r
+#define REG_PIOF_OER (*(WoReg*)0x400E1810U) /**< \brief (PIOF) Output Enable Register */\r
+#define REG_PIOF_ODR (*(WoReg*)0x400E1814U) /**< \brief (PIOF) Output Disable Register */\r
+#define REG_PIOF_OSR (*(RoReg*)0x400E1818U) /**< \brief (PIOF) Output Status Register */\r
+#define REG_PIOF_IFER (*(WoReg*)0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */\r
+#define REG_PIOF_IFDR (*(WoReg*)0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */\r
+#define REG_PIOF_IFSR (*(RoReg*)0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */\r
+#define REG_PIOF_SODR (*(WoReg*)0x400E1830U) /**< \brief (PIOF) Set Output Data Register */\r
+#define REG_PIOF_CODR (*(WoReg*)0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */\r
+#define REG_PIOF_ODSR (*(RwReg*)0x400E1838U) /**< \brief (PIOF) Output Data Status Register */\r
+#define REG_PIOF_PDSR (*(RoReg*)0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */\r
+#define REG_PIOF_IER (*(WoReg*)0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */\r
+#define REG_PIOF_IDR (*(WoReg*)0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */\r
+#define REG_PIOF_IMR (*(RoReg*)0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */\r
+#define REG_PIOF_ISR (*(RoReg*)0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */\r
+#define REG_PIOF_MDER (*(WoReg*)0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */\r
+#define REG_PIOF_MDDR (*(WoReg*)0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */\r
+#define REG_PIOF_MDSR (*(RoReg*)0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */\r
+#define REG_PIOF_PUDR (*(WoReg*)0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */\r
+#define REG_PIOF_PUER (*(WoReg*)0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */\r
+#define REG_PIOF_PUSR (*(RoReg*)0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */\r
+#define REG_PIOF_ABSR (*(RwReg*)0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */\r
+#define REG_PIOF_SCIFSR (*(WoReg*)0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */\r
+#define REG_PIOF_DIFSR (*(WoReg*)0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */\r
+#define REG_PIOF_IFDGSR (*(RoReg*)0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */\r
+#define REG_PIOF_SCDR (*(RwReg*)0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOF_OWER (*(WoReg*)0x400E18A0U) /**< \brief (PIOF) Output Write Enable */\r
+#define REG_PIOF_OWDR (*(WoReg*)0x400E18A4U) /**< \brief (PIOF) Output Write Disable */\r
+#define REG_PIOF_OWSR (*(RoReg*)0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */\r
+#define REG_PIOF_AIMER (*(WoReg*)0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOF_AIMDR (*(WoReg*)0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOF_AIMMR (*(RoReg*)0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOF_ESR (*(WoReg*)0x400E18C0U) /**< \brief (PIOF) Edge Select Register */\r
+#define REG_PIOF_LSR (*(WoReg*)0x400E18C4U) /**< \brief (PIOF) Level Select Register */\r
+#define REG_PIOF_ELSR (*(RoReg*)0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */\r
+#define REG_PIOF_FELLSR (*(WoReg*)0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */\r
+#define REG_PIOF_REHLSR (*(WoReg*)0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */\r
+#define REG_PIOF_FRLHSR (*(RoReg*)0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOF_LOCKSR (*(RoReg*)0x400E18E0U) /**< \brief (PIOF) Lock Status */\r
+#define REG_PIOF_WPMR (*(RwReg*)0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */\r
+#define REG_PIOF_WPSR (*(RoReg*)0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_PIOF_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PMC_INSTANCE_\r
+#define _SAM3XA_PMC_INSTANCE_\r
+\r
+/* ========== Register definition for PMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */\r
+#define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */\r
+#define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */\r
+#define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */\r
+#define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */\r
+#define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */\r
+#define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */\r
+#define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */\r
+#define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */\r
+#define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */\r
+#define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */\r
+#define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */\r
+#define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */\r
+#define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */\r
+#define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */\r
+#define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */\r
+#define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */\r
+#define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */\r
+#define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */\r
+#define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */\r
+#define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */\r
+#define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */\r
+#define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */\r
+#define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */\r
+#define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */\r
+#define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */\r
+#else\r
+#define REG_PMC_SCER (*(WoReg*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */\r
+#define REG_PMC_SCDR (*(WoReg*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */\r
+#define REG_PMC_SCSR (*(RoReg*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */\r
+#define REG_PMC_PCER0 (*(WoReg*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */\r
+#define REG_PMC_PCDR0 (*(WoReg*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */\r
+#define REG_PMC_PCSR0 (*(RoReg*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */\r
+#define REG_CKGR_UCKR (*(RwReg*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */\r
+#define REG_CKGR_MOR (*(RwReg*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */\r
+#define REG_CKGR_MCFR (*(RoReg*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */\r
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0628U) /**< \brief (PMC) PLLA Register */\r
+#define REG_PMC_MCKR (*(RwReg*)0x400E0630U) /**< \brief (PMC) Master Clock Register */\r
+#define REG_PMC_USB (*(RwReg*)0x400E0638U) /**< \brief (PMC) USB Clock Register */\r
+#define REG_PMC_PCK (*(RwReg*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */\r
+#define REG_PMC_IER (*(WoReg*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */\r
+#define REG_PMC_IDR (*(WoReg*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */\r
+#define REG_PMC_SR (*(RoReg*)0x400E0668U) /**< \brief (PMC) Status Register */\r
+#define REG_PMC_IMR (*(RoReg*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */\r
+#define REG_PMC_FSMR (*(RwReg*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */\r
+#define REG_PMC_FSPR (*(RwReg*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */\r
+#define REG_PMC_FOCR (*(WoReg*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */\r
+#define REG_PMC_WPMR (*(RwReg*)0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */\r
+#define REG_PMC_WPSR (*(RoReg*)0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */\r
+#define REG_PMC_PCER1 (*(WoReg*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */\r
+#define REG_PMC_PCDR1 (*(WoReg*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */\r
+#define REG_PMC_PCSR1 (*(RoReg*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */\r
+#define REG_PMC_PCR (*(RwReg*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_PMC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_PWM_INSTANCE_\r
+#define _SAM3XA_PWM_INSTANCE_\r
+\r
+/* ========== Register definition for PWM peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PWM_CLK (0x40094000U) /**< \brief (PWM) PWM Clock Register */\r
+#define REG_PWM_ENA (0x40094004U) /**< \brief (PWM) PWM Enable Register */\r
+#define REG_PWM_DIS (0x40094008U) /**< \brief (PWM) PWM Disable Register */\r
+#define REG_PWM_SR (0x4009400CU) /**< \brief (PWM) PWM Status Register */\r
+#define REG_PWM_IER1 (0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */\r
+#define REG_PWM_IDR1 (0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */\r
+#define REG_PWM_IMR1 (0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */\r
+#define REG_PWM_ISR1 (0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */\r
+#define REG_PWM_SCM (0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */\r
+#define REG_PWM_SCUC (0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */\r
+#define REG_PWM_SCUP (0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */\r
+#define REG_PWM_SCUPUPD (0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */\r
+#define REG_PWM_IER2 (0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */\r
+#define REG_PWM_IDR2 (0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */\r
+#define REG_PWM_IMR2 (0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */\r
+#define REG_PWM_ISR2 (0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */\r
+#define REG_PWM_OOV (0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */\r
+#define REG_PWM_OS (0x40094048U) /**< \brief (PWM) PWM Output Selection Register */\r
+#define REG_PWM_OSS (0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */\r
+#define REG_PWM_OSC (0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */\r
+#define REG_PWM_OSSUPD (0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */\r
+#define REG_PWM_OSCUPD (0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */\r
+#define REG_PWM_FMR (0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */\r
+#define REG_PWM_FSR (0x40094060U) /**< \brief (PWM) PWM Fault Status Register */\r
+#define REG_PWM_FCR (0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */\r
+#define REG_PWM_FPV (0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */\r
+#define REG_PWM_FPE1 (0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */\r
+#define REG_PWM_FPE2 (0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */\r
+#define REG_PWM_ELMR (0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */\r
+#define REG_PWM_SMMR (0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */\r
+#define REG_PWM_WPCR (0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */\r
+#define REG_PWM_WPSR (0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */\r
+#define REG_PWM_TPR (0x40094108U) /**< \brief (PWM) Transmit Pointer Register */\r
+#define REG_PWM_TCR (0x4009410CU) /**< \brief (PWM) Transmit Counter Register */\r
+#define REG_PWM_TNPR (0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */\r
+#define REG_PWM_TNCR (0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */\r
+#define REG_PWM_PTCR (0x40094120U) /**< \brief (PWM) Transfer Control Register */\r
+#define REG_PWM_PTSR (0x40094124U) /**< \brief (PWM) Transfer Status Register */\r
+#define REG_PWM_CMPV0 (0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */\r
+#define REG_PWM_CMPVUPD0 (0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */\r
+#define REG_PWM_CMPM0 (0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */\r
+#define REG_PWM_CMPMUPD0 (0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */\r
+#define REG_PWM_CMPV1 (0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */\r
+#define REG_PWM_CMPVUPD1 (0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */\r
+#define REG_PWM_CMPM1 (0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */\r
+#define REG_PWM_CMPMUPD1 (0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */\r
+#define REG_PWM_CMPV2 (0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */\r
+#define REG_PWM_CMPVUPD2 (0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */\r
+#define REG_PWM_CMPM2 (0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */\r
+#define REG_PWM_CMPMUPD2 (0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */\r
+#define REG_PWM_CMPV3 (0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */\r
+#define REG_PWM_CMPVUPD3 (0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */\r
+#define REG_PWM_CMPM3 (0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */\r
+#define REG_PWM_CMPMUPD3 (0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */\r
+#define REG_PWM_CMPV4 (0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */\r
+#define REG_PWM_CMPVUPD4 (0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */\r
+#define REG_PWM_CMPM4 (0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */\r
+#define REG_PWM_CMPMUPD4 (0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */\r
+#define REG_PWM_CMPV5 (0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */\r
+#define REG_PWM_CMPVUPD5 (0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */\r
+#define REG_PWM_CMPM5 (0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */\r
+#define REG_PWM_CMPMUPD5 (0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */\r
+#define REG_PWM_CMPV6 (0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */\r
+#define REG_PWM_CMPVUPD6 (0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */\r
+#define REG_PWM_CMPM6 (0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */\r
+#define REG_PWM_CMPMUPD6 (0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */\r
+#define REG_PWM_CMPV7 (0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */\r
+#define REG_PWM_CMPVUPD7 (0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */\r
+#define REG_PWM_CMPM7 (0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */\r
+#define REG_PWM_CMPMUPD7 (0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */\r
+#define REG_PWM_CMR0 (0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */\r
+#define REG_PWM_CDTY0 (0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+#define REG_PWM_CDTYUPD0 (0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+#define REG_PWM_CPRD0 (0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */\r
+#define REG_PWM_CPRDUPD0 (0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */\r
+#define REG_PWM_CCNT0 (0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */\r
+#define REG_PWM_DT0 (0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */\r
+#define REG_PWM_DTUPD0 (0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+#define REG_PWM_CMR1 (0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */\r
+#define REG_PWM_CDTY1 (0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+#define REG_PWM_CDTYUPD1 (0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+#define REG_PWM_CPRD1 (0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */\r
+#define REG_PWM_CPRDUPD1 (0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */\r
+#define REG_PWM_CCNT1 (0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */\r
+#define REG_PWM_DT1 (0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */\r
+#define REG_PWM_DTUPD1 (0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+#define REG_PWM_CMR2 (0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */\r
+#define REG_PWM_CDTY2 (0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+#define REG_PWM_CDTYUPD2 (0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+#define REG_PWM_CPRD2 (0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */\r
+#define REG_PWM_CPRDUPD2 (0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */\r
+#define REG_PWM_CCNT2 (0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */\r
+#define REG_PWM_DT2 (0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */\r
+#define REG_PWM_DTUPD2 (0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+#define REG_PWM_CMR3 (0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */\r
+#define REG_PWM_CDTY3 (0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+#define REG_PWM_CDTYUPD3 (0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+#define REG_PWM_CPRD3 (0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */\r
+#define REG_PWM_CPRDUPD3 (0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */\r
+#define REG_PWM_CCNT3 (0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */\r
+#define REG_PWM_DT3 (0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */\r
+#define REG_PWM_DTUPD3 (0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+#define REG_PWM_CMR4 (0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */\r
+#define REG_PWM_CDTY4 (0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */\r
+#define REG_PWM_CDTYUPD4 (0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */\r
+#define REG_PWM_CPRD4 (0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */\r
+#define REG_PWM_CPRDUPD4 (0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */\r
+#define REG_PWM_CCNT4 (0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */\r
+#define REG_PWM_DT4 (0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */\r
+#define REG_PWM_DTUPD4 (0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */\r
+#define REG_PWM_CMR5 (0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */\r
+#define REG_PWM_CDTY5 (0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */\r
+#define REG_PWM_CDTYUPD5 (0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */\r
+#define REG_PWM_CPRD5 (0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */\r
+#define REG_PWM_CPRDUPD5 (0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */\r
+#define REG_PWM_CCNT5 (0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */\r
+#define REG_PWM_DT5 (0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */\r
+#define REG_PWM_DTUPD5 (0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */\r
+#define REG_PWM_CMR6 (0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */\r
+#define REG_PWM_CDTY6 (0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */\r
+#define REG_PWM_CDTYUPD6 (0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */\r
+#define REG_PWM_CPRD6 (0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */\r
+#define REG_PWM_CPRDUPD6 (0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */\r
+#define REG_PWM_CCNT6 (0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */\r
+#define REG_PWM_DT6 (0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */\r
+#define REG_PWM_DTUPD6 (0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */\r
+#define REG_PWM_CMR7 (0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */\r
+#define REG_PWM_CDTY7 (0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */\r
+#define REG_PWM_CDTYUPD7 (0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */\r
+#define REG_PWM_CPRD7 (0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */\r
+#define REG_PWM_CPRDUPD7 (0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */\r
+#define REG_PWM_CCNT7 (0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */\r
+#define REG_PWM_DT7 (0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */\r
+#define REG_PWM_DTUPD7 (0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */\r
+#else\r
+#define REG_PWM_CLK (*(RwReg*)0x40094000U) /**< \brief (PWM) PWM Clock Register */\r
+#define REG_PWM_ENA (*(WoReg*)0x40094004U) /**< \brief (PWM) PWM Enable Register */\r
+#define REG_PWM_DIS (*(WoReg*)0x40094008U) /**< \brief (PWM) PWM Disable Register */\r
+#define REG_PWM_SR (*(RoReg*)0x4009400CU) /**< \brief (PWM) PWM Status Register */\r
+#define REG_PWM_IER1 (*(WoReg*)0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */\r
+#define REG_PWM_IDR1 (*(WoReg*)0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */\r
+#define REG_PWM_IMR1 (*(RoReg*)0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */\r
+#define REG_PWM_ISR1 (*(RoReg*)0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */\r
+#define REG_PWM_SCM (*(RwReg*)0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */\r
+#define REG_PWM_SCUC (*(RwReg*)0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */\r
+#define REG_PWM_SCUP (*(RwReg*)0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */\r
+#define REG_PWM_SCUPUPD (*(WoReg*)0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */\r
+#define REG_PWM_IER2 (*(WoReg*)0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */\r
+#define REG_PWM_IDR2 (*(WoReg*)0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */\r
+#define REG_PWM_IMR2 (*(RoReg*)0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */\r
+#define REG_PWM_ISR2 (*(RoReg*)0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */\r
+#define REG_PWM_OOV (*(RwReg*)0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */\r
+#define REG_PWM_OS (*(RwReg*)0x40094048U) /**< \brief (PWM) PWM Output Selection Register */\r
+#define REG_PWM_OSS (*(WoReg*)0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */\r
+#define REG_PWM_OSC (*(WoReg*)0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */\r
+#define REG_PWM_OSSUPD (*(WoReg*)0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */\r
+#define REG_PWM_OSCUPD (*(WoReg*)0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */\r
+#define REG_PWM_FMR (*(RwReg*)0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */\r
+#define REG_PWM_FSR (*(RoReg*)0x40094060U) /**< \brief (PWM) PWM Fault Status Register */\r
+#define REG_PWM_FCR (*(WoReg*)0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */\r
+#define REG_PWM_FPV (*(RwReg*)0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */\r
+#define REG_PWM_FPE1 (*(RwReg*)0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */\r
+#define REG_PWM_FPE2 (*(RwReg*)0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */\r
+#define REG_PWM_ELMR (*(RwReg*)0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */\r
+#define REG_PWM_SMMR (*(RwReg*)0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */\r
+#define REG_PWM_WPCR (*(WoReg*)0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */\r
+#define REG_PWM_WPSR (*(RoReg*)0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */\r
+#define REG_PWM_TPR (*(RwReg*)0x40094108U) /**< \brief (PWM) Transmit Pointer Register */\r
+#define REG_PWM_TCR (*(RwReg*)0x4009410CU) /**< \brief (PWM) Transmit Counter Register */\r
+#define REG_PWM_TNPR (*(RwReg*)0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */\r
+#define REG_PWM_TNCR (*(RwReg*)0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */\r
+#define REG_PWM_PTCR (*(WoReg*)0x40094120U) /**< \brief (PWM) Transfer Control Register */\r
+#define REG_PWM_PTSR (*(RoReg*)0x40094124U) /**< \brief (PWM) Transfer Status Register */\r
+#define REG_PWM_CMPV0 (*(RwReg*)0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */\r
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */\r
+#define REG_PWM_CMPM0 (*(RwReg*)0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */\r
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */\r
+#define REG_PWM_CMPV1 (*(RwReg*)0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */\r
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */\r
+#define REG_PWM_CMPM1 (*(RwReg*)0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */\r
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */\r
+#define REG_PWM_CMPV2 (*(RwReg*)0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */\r
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */\r
+#define REG_PWM_CMPM2 (*(RwReg*)0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */\r
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */\r
+#define REG_PWM_CMPV3 (*(RwReg*)0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */\r
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */\r
+#define REG_PWM_CMPM3 (*(RwReg*)0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */\r
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */\r
+#define REG_PWM_CMPV4 (*(RwReg*)0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */\r
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */\r
+#define REG_PWM_CMPM4 (*(RwReg*)0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */\r
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */\r
+#define REG_PWM_CMPV5 (*(RwReg*)0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */\r
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */\r
+#define REG_PWM_CMPM5 (*(RwReg*)0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */\r
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */\r
+#define REG_PWM_CMPV6 (*(RwReg*)0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */\r
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */\r
+#define REG_PWM_CMPM6 (*(RwReg*)0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */\r
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */\r
+#define REG_PWM_CMPV7 (*(RwReg*)0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */\r
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */\r
+#define REG_PWM_CMPM7 (*(RwReg*)0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */\r
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */\r
+#define REG_PWM_CMR0 (*(RwReg*)0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */\r
+#define REG_PWM_CDTY0 (*(RwReg*)0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+#define REG_PWM_CPRD0 (*(RwReg*)0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */\r
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */\r
+#define REG_PWM_CCNT0 (*(RoReg*)0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */\r
+#define REG_PWM_DT0 (*(RwReg*)0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */\r
+#define REG_PWM_DTUPD0 (*(WoReg*)0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+#define REG_PWM_CMR1 (*(RwReg*)0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */\r
+#define REG_PWM_CDTY1 (*(RwReg*)0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+#define REG_PWM_CPRD1 (*(RwReg*)0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */\r
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */\r
+#define REG_PWM_CCNT1 (*(RoReg*)0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */\r
+#define REG_PWM_DT1 (*(RwReg*)0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */\r
+#define REG_PWM_DTUPD1 (*(WoReg*)0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+#define REG_PWM_CMR2 (*(RwReg*)0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */\r
+#define REG_PWM_CDTY2 (*(RwReg*)0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+#define REG_PWM_CPRD2 (*(RwReg*)0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */\r
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */\r
+#define REG_PWM_CCNT2 (*(RoReg*)0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */\r
+#define REG_PWM_DT2 (*(RwReg*)0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */\r
+#define REG_PWM_DTUPD2 (*(WoReg*)0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+#define REG_PWM_CMR3 (*(RwReg*)0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */\r
+#define REG_PWM_CDTY3 (*(RwReg*)0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+#define REG_PWM_CPRD3 (*(RwReg*)0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */\r
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */\r
+#define REG_PWM_CCNT3 (*(RoReg*)0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */\r
+#define REG_PWM_DT3 (*(RwReg*)0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */\r
+#define REG_PWM_DTUPD3 (*(WoReg*)0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+#define REG_PWM_CMR4 (*(RwReg*)0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */\r
+#define REG_PWM_CDTY4 (*(RwReg*)0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */\r
+#define REG_PWM_CDTYUPD4 (*(WoReg*)0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */\r
+#define REG_PWM_CPRD4 (*(RwReg*)0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */\r
+#define REG_PWM_CPRDUPD4 (*(WoReg*)0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */\r
+#define REG_PWM_CCNT4 (*(RoReg*)0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */\r
+#define REG_PWM_DT4 (*(RwReg*)0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */\r
+#define REG_PWM_DTUPD4 (*(WoReg*)0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */\r
+#define REG_PWM_CMR5 (*(RwReg*)0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */\r
+#define REG_PWM_CDTY5 (*(RwReg*)0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */\r
+#define REG_PWM_CDTYUPD5 (*(WoReg*)0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */\r
+#define REG_PWM_CPRD5 (*(RwReg*)0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */\r
+#define REG_PWM_CPRDUPD5 (*(WoReg*)0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */\r
+#define REG_PWM_CCNT5 (*(RoReg*)0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */\r
+#define REG_PWM_DT5 (*(RwReg*)0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */\r
+#define REG_PWM_DTUPD5 (*(WoReg*)0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */\r
+#define REG_PWM_CMR6 (*(RwReg*)0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */\r
+#define REG_PWM_CDTY6 (*(RwReg*)0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */\r
+#define REG_PWM_CDTYUPD6 (*(WoReg*)0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */\r
+#define REG_PWM_CPRD6 (*(RwReg*)0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */\r
+#define REG_PWM_CPRDUPD6 (*(WoReg*)0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */\r
+#define REG_PWM_CCNT6 (*(RoReg*)0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */\r
+#define REG_PWM_DT6 (*(RwReg*)0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */\r
+#define REG_PWM_DTUPD6 (*(WoReg*)0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */\r
+#define REG_PWM_CMR7 (*(RwReg*)0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */\r
+#define REG_PWM_CDTY7 (*(RwReg*)0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */\r
+#define REG_PWM_CDTYUPD7 (*(WoReg*)0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */\r
+#define REG_PWM_CPRD7 (*(RwReg*)0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */\r
+#define REG_PWM_CPRDUPD7 (*(WoReg*)0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */\r
+#define REG_PWM_CCNT7 (*(RoReg*)0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */\r
+#define REG_PWM_DT7 (*(RwReg*)0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */\r
+#define REG_PWM_DTUPD7 (*(WoReg*)0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_PWM_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_RSTC_INSTANCE_\r
+#define _SAM3XA_RSTC_INSTANCE_\r
+\r
+/* ========== Register definition for RSTC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RSTC_CR (0x400E1A00U) /**< \brief (RSTC) Control Register */\r
+#define REG_RSTC_SR (0x400E1A04U) /**< \brief (RSTC) Status Register */\r
+#define REG_RSTC_MR (0x400E1A08U) /**< \brief (RSTC) Mode Register */\r
+#else\r
+#define REG_RSTC_CR (*(WoReg*)0x400E1A00U) /**< \brief (RSTC) Control Register */\r
+#define REG_RSTC_SR (*(RoReg*)0x400E1A04U) /**< \brief (RSTC) Status Register */\r
+#define REG_RSTC_MR (*(RwReg*)0x400E1A08U) /**< \brief (RSTC) Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_RSTC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_RTC_INSTANCE_\r
+#define _SAM3XA_RTC_INSTANCE_\r
+\r
+/* ========== Register definition for RTC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RTC_CR (0x400E1A60U) /**< \brief (RTC) Control Register */\r
+#define REG_RTC_MR (0x400E1A64U) /**< \brief (RTC) Mode Register */\r
+#define REG_RTC_TIMR (0x400E1A68U) /**< \brief (RTC) Time Register */\r
+#define REG_RTC_CALR (0x400E1A6CU) /**< \brief (RTC) Calendar Register */\r
+#define REG_RTC_TIMALR (0x400E1A70U) /**< \brief (RTC) Time Alarm Register */\r
+#define REG_RTC_CALALR (0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */\r
+#define REG_RTC_SR (0x400E1A78U) /**< \brief (RTC) Status Register */\r
+#define REG_RTC_SCCR (0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */\r
+#define REG_RTC_IER (0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */\r
+#define REG_RTC_IDR (0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */\r
+#define REG_RTC_IMR (0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */\r
+#define REG_RTC_VER (0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */\r
+#define REG_RTC_WPMR (0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */\r
+#else\r
+#define REG_RTC_CR (*(RwReg*)0x400E1A60U) /**< \brief (RTC) Control Register */\r
+#define REG_RTC_MR (*(RwReg*)0x400E1A64U) /**< \brief (RTC) Mode Register */\r
+#define REG_RTC_TIMR (*(RwReg*)0x400E1A68U) /**< \brief (RTC) Time Register */\r
+#define REG_RTC_CALR (*(RwReg*)0x400E1A6CU) /**< \brief (RTC) Calendar Register */\r
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1A70U) /**< \brief (RTC) Time Alarm Register */\r
+#define REG_RTC_CALALR (*(RwReg*)0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */\r
+#define REG_RTC_SR (*(RoReg*)0x400E1A78U) /**< \brief (RTC) Status Register */\r
+#define REG_RTC_SCCR (*(WoReg*)0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */\r
+#define REG_RTC_IER (*(WoReg*)0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */\r
+#define REG_RTC_IDR (*(WoReg*)0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */\r
+#define REG_RTC_IMR (*(RoReg*)0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */\r
+#define REG_RTC_VER (*(RoReg*)0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */\r
+#define REG_RTC_WPMR (*(RwReg*)0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_RTC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_RTT_INSTANCE_\r
+#define _SAM3XA_RTT_INSTANCE_\r
+\r
+/* ========== Register definition for RTT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RTT_MR (0x400E1A30U) /**< \brief (RTT) Mode Register */\r
+#define REG_RTT_AR (0x400E1A34U) /**< \brief (RTT) Alarm Register */\r
+#define REG_RTT_VR (0x400E1A38U) /**< \brief (RTT) Value Register */\r
+#define REG_RTT_SR (0x400E1A3CU) /**< \brief (RTT) Status Register */\r
+#else\r
+#define REG_RTT_MR (*(RwReg*)0x400E1A30U) /**< \brief (RTT) Mode Register */\r
+#define REG_RTT_AR (*(RwReg*)0x400E1A34U) /**< \brief (RTT) Alarm Register */\r
+#define REG_RTT_VR (*(RoReg*)0x400E1A38U) /**< \brief (RTT) Value Register */\r
+#define REG_RTT_SR (*(RoReg*)0x400E1A3CU) /**< \brief (RTT) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_RTT_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_SDRAMC_INSTANCE_\r
+#define _SAM3XA_SDRAMC_INSTANCE_\r
+\r
+/* ========== Register definition for SDRAMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SDRAMC_MR (0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */\r
+#define REG_SDRAMC_TR (0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */\r
+#define REG_SDRAMC_CR (0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */\r
+#define REG_SDRAMC_LPR (0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */\r
+#define REG_SDRAMC_IER (0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */\r
+#define REG_SDRAMC_IDR (0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */\r
+#define REG_SDRAMC_IMR (0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */\r
+#define REG_SDRAMC_ISR (0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */\r
+#define REG_SDRAMC_MDR (0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */\r
+#define REG_SDRAMC_CR1 (0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */\r
+#define REG_SDRAMC_OCMS (0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */\r
+#else\r
+#define REG_SDRAMC_MR (*(RwReg*)0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */\r
+#define REG_SDRAMC_TR (*(RwReg*)0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */\r
+#define REG_SDRAMC_CR (*(RwReg*)0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */\r
+#define REG_SDRAMC_LPR (*(RwReg*)0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */\r
+#define REG_SDRAMC_IER (*(WoReg*)0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */\r
+#define REG_SDRAMC_IDR (*(WoReg*)0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */\r
+#define REG_SDRAMC_IMR (*(RoReg*)0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */\r
+#define REG_SDRAMC_ISR (*(RoReg*)0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */\r
+#define REG_SDRAMC_MDR (*(RwReg*)0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */\r
+#define REG_SDRAMC_CR1 (*(RwReg*)0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */\r
+#define REG_SDRAMC_OCMS (*(RwReg*)0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_SMC_INSTANCE_\r
+#define _SAM3XA_SMC_INSTANCE_\r
+\r
+/* ========== Register definition for SMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SMC_CFG (0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */\r
+#define REG_SMC_CTRL (0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */\r
+#define REG_SMC_SR (0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */\r
+#define REG_SMC_IER (0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */\r
+#define REG_SMC_IDR (0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */\r
+#define REG_SMC_IMR (0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */\r
+#define REG_SMC_ADDR (0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */\r
+#define REG_SMC_BANK (0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */\r
+#define REG_SMC_ECC_CTRL (0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */\r
+#define REG_SMC_ECC_MD (0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */\r
+#define REG_SMC_ECC_SR1 (0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */\r
+#define REG_SMC_ECC_PR0 (0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */\r
+#define REG_SMC_ECC_PR1 (0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */\r
+#define REG_SMC_ECC_SR2 (0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */\r
+#define REG_SMC_ECC_PR2 (0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */\r
+#define REG_SMC_ECC_PR3 (0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */\r
+#define REG_SMC_ECC_PR4 (0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */\r
+#define REG_SMC_ECC_PR5 (0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */\r
+#define REG_SMC_ECC_PR6 (0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */\r
+#define REG_SMC_ECC_PR7 (0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */\r
+#define REG_SMC_ECC_PR8 (0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */\r
+#define REG_SMC_ECC_PR9 (0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */\r
+#define REG_SMC_ECC_PR10 (0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */\r
+#define REG_SMC_ECC_PR11 (0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */\r
+#define REG_SMC_ECC_PR12 (0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */\r
+#define REG_SMC_ECC_PR13 (0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */\r
+#define REG_SMC_ECC_PR14 (0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */\r
+#define REG_SMC_ECC_PR15 (0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */\r
+#define REG_SMC_SETUP0 (0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+#define REG_SMC_PULSE0 (0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+#define REG_SMC_CYCLE0 (0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+#define REG_SMC_TIMINGS0 (0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */\r
+#define REG_SMC_MODE0 (0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */\r
+#define REG_SMC_SETUP1 (0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+#define REG_SMC_PULSE1 (0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+#define REG_SMC_CYCLE1 (0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+#define REG_SMC_TIMINGS1 (0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */\r
+#define REG_SMC_MODE1 (0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */\r
+#define REG_SMC_SETUP2 (0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+#define REG_SMC_PULSE2 (0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+#define REG_SMC_CYCLE2 (0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+#define REG_SMC_TIMINGS2 (0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */\r
+#define REG_SMC_MODE2 (0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */\r
+#define REG_SMC_SETUP3 (0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+#define REG_SMC_PULSE3 (0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+#define REG_SMC_CYCLE3 (0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+#define REG_SMC_TIMINGS3 (0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */\r
+#define REG_SMC_MODE3 (0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */\r
+#define REG_SMC_SETUP4 (0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */\r
+#define REG_SMC_PULSE4 (0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */\r
+#define REG_SMC_CYCLE4 (0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */\r
+#define REG_SMC_TIMINGS4 (0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */\r
+#define REG_SMC_MODE4 (0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */\r
+#define REG_SMC_SETUP5 (0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */\r
+#define REG_SMC_PULSE5 (0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */\r
+#define REG_SMC_CYCLE5 (0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */\r
+#define REG_SMC_TIMINGS5 (0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */\r
+#define REG_SMC_MODE5 (0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */\r
+#define REG_SMC_SETUP6 (0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */\r
+#define REG_SMC_PULSE6 (0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */\r
+#define REG_SMC_CYCLE6 (0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */\r
+#define REG_SMC_TIMINGS6 (0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */\r
+#define REG_SMC_MODE6 (0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */\r
+#define REG_SMC_SETUP7 (0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */\r
+#define REG_SMC_PULSE7 (0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */\r
+#define REG_SMC_CYCLE7 (0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */\r
+#define REG_SMC_TIMINGS7 (0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */\r
+#define REG_SMC_MODE7 (0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */\r
+#define REG_SMC_OCMS (0x400E0110U) /**< \brief (SMC) SMC OCMS Register */\r
+#define REG_SMC_KEY1 (0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+#define REG_SMC_KEY2 (0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+#define REG_SMC_WPCR (0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */\r
+#define REG_SMC_WPSR (0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */\r
+#else\r
+#define REG_SMC_CFG (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */\r
+#define REG_SMC_CTRL (*(WoReg*)0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */\r
+#define REG_SMC_SR (*(RoReg*)0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */\r
+#define REG_SMC_IER (*(WoReg*)0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */\r
+#define REG_SMC_IDR (*(WoReg*)0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */\r
+#define REG_SMC_IMR (*(RoReg*)0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */\r
+#define REG_SMC_ADDR (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */\r
+#define REG_SMC_BANK (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */\r
+#define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */\r
+#define REG_SMC_ECC_MD (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */\r
+#define REG_SMC_ECC_SR1 (*(RoReg*)0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */\r
+#define REG_SMC_ECC_PR0 (*(RoReg*)0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */\r
+#define REG_SMC_ECC_PR1 (*(RoReg*)0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */\r
+#define REG_SMC_ECC_SR2 (*(RoReg*)0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */\r
+#define REG_SMC_ECC_PR2 (*(RoReg*)0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */\r
+#define REG_SMC_ECC_PR3 (*(RoReg*)0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */\r
+#define REG_SMC_ECC_PR4 (*(RoReg*)0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */\r
+#define REG_SMC_ECC_PR5 (*(RoReg*)0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */\r
+#define REG_SMC_ECC_PR6 (*(RoReg*)0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */\r
+#define REG_SMC_ECC_PR7 (*(RoReg*)0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */\r
+#define REG_SMC_ECC_PR8 (*(RoReg*)0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */\r
+#define REG_SMC_ECC_PR9 (*(RoReg*)0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */\r
+#define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */\r
+#define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */\r
+#define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */\r
+#define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */\r
+#define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */\r
+#define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */\r
+#define REG_SMC_SETUP0 (*(RwReg*)0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+#define REG_SMC_PULSE0 (*(RwReg*)0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+#define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */\r
+#define REG_SMC_MODE0 (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */\r
+#define REG_SMC_SETUP1 (*(RwReg*)0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+#define REG_SMC_PULSE1 (*(RwReg*)0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+#define REG_SMC_CYCLE1 (*(RwReg*)0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+#define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */\r
+#define REG_SMC_MODE1 (*(RwReg*)0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */\r
+#define REG_SMC_SETUP2 (*(RwReg*)0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+#define REG_SMC_PULSE2 (*(RwReg*)0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+#define REG_SMC_CYCLE2 (*(RwReg*)0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+#define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */\r
+#define REG_SMC_MODE2 (*(RwReg*)0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */\r
+#define REG_SMC_SETUP3 (*(RwReg*)0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+#define REG_SMC_PULSE3 (*(RwReg*)0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+#define REG_SMC_CYCLE3 (*(RwReg*)0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+#define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */\r
+#define REG_SMC_MODE3 (*(RwReg*)0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */\r
+#define REG_SMC_SETUP4 (*(RwReg*)0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */\r
+#define REG_SMC_PULSE4 (*(RwReg*)0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */\r
+#define REG_SMC_CYCLE4 (*(RwReg*)0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */\r
+#define REG_SMC_TIMINGS4 (*(RwReg*)0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */\r
+#define REG_SMC_MODE4 (*(RwReg*)0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */\r
+#define REG_SMC_SETUP5 (*(RwReg*)0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */\r
+#define REG_SMC_PULSE5 (*(RwReg*)0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */\r
+#define REG_SMC_CYCLE5 (*(RwReg*)0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */\r
+#define REG_SMC_TIMINGS5 (*(RwReg*)0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */\r
+#define REG_SMC_MODE5 (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */\r
+#define REG_SMC_SETUP6 (*(RwReg*)0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */\r
+#define REG_SMC_PULSE6 (*(RwReg*)0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */\r
+#define REG_SMC_CYCLE6 (*(RwReg*)0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */\r
+#define REG_SMC_TIMINGS6 (*(RwReg*)0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */\r
+#define REG_SMC_MODE6 (*(RwReg*)0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */\r
+#define REG_SMC_SETUP7 (*(RwReg*)0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */\r
+#define REG_SMC_PULSE7 (*(RwReg*)0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */\r
+#define REG_SMC_CYCLE7 (*(RwReg*)0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */\r
+#define REG_SMC_TIMINGS7 (*(RwReg*)0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */\r
+#define REG_SMC_MODE7 (*(RwReg*)0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */\r
+#define REG_SMC_OCMS (*(RwReg*)0x400E0110U) /**< \brief (SMC) SMC OCMS Register */\r
+#define REG_SMC_KEY1 (*(WoReg*)0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+#define REG_SMC_KEY2 (*(WoReg*)0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+#define REG_SMC_WPCR (*(WoReg*)0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */\r
+#define REG_SMC_WPSR (*(RoReg*)0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_SMC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_SPI0_INSTANCE_\r
+#define _SAM3XA_SPI0_INSTANCE_\r
+\r
+/* ========== Register definition for SPI0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SPI0_CR (0x40008000U) /**< \brief (SPI0) Control Register */\r
+#define REG_SPI0_MR (0x40008004U) /**< \brief (SPI0) Mode Register */\r
+#define REG_SPI0_RDR (0x40008008U) /**< \brief (SPI0) Receive Data Register */\r
+#define REG_SPI0_TDR (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */\r
+#define REG_SPI0_SR (0x40008010U) /**< \brief (SPI0) Status Register */\r
+#define REG_SPI0_IER (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */\r
+#define REG_SPI0_IDR (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */\r
+#define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */\r
+#define REG_SPI0_CSR (0x40008030U) /**< \brief (SPI0) Chip Select Register */\r
+#define REG_SPI0_WPMR (0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */\r
+#define REG_SPI0_WPSR (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */\r
+#else\r
+#define REG_SPI0_CR (*(WoReg*)0x40008000U) /**< \brief (SPI0) Control Register */\r
+#define REG_SPI0_MR (*(RwReg*)0x40008004U) /**< \brief (SPI0) Mode Register */\r
+#define REG_SPI0_RDR (*(RoReg*)0x40008008U) /**< \brief (SPI0) Receive Data Register */\r
+#define REG_SPI0_TDR (*(WoReg*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */\r
+#define REG_SPI0_SR (*(RoReg*)0x40008010U) /**< \brief (SPI0) Status Register */\r
+#define REG_SPI0_IER (*(WoReg*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */\r
+#define REG_SPI0_IDR (*(WoReg*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */\r
+#define REG_SPI0_IMR (*(RoReg*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */\r
+#define REG_SPI0_CSR (*(RwReg*)0x40008030U) /**< \brief (SPI0) Chip Select Register */\r
+#define REG_SPI0_WPMR (*(RwReg*)0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */\r
+#define REG_SPI0_WPSR (*(RoReg*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_SPI0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_SPI1_INSTANCE_\r
+#define _SAM3XA_SPI1_INSTANCE_\r
+\r
+/* ========== Register definition for SPI1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SPI1_CR (0x4000C000U) /**< \brief (SPI1) Control Register */\r
+#define REG_SPI1_MR (0x4000C004U) /**< \brief (SPI1) Mode Register */\r
+#define REG_SPI1_RDR (0x4000C008U) /**< \brief (SPI1) Receive Data Register */\r
+#define REG_SPI1_TDR (0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */\r
+#define REG_SPI1_SR (0x4000C010U) /**< \brief (SPI1) Status Register */\r
+#define REG_SPI1_IER (0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */\r
+#define REG_SPI1_IDR (0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */\r
+#define REG_SPI1_IMR (0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */\r
+#define REG_SPI1_CSR (0x4000C030U) /**< \brief (SPI1) Chip Select Register */\r
+#define REG_SPI1_WPMR (0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */\r
+#define REG_SPI1_WPSR (0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */\r
+#else\r
+#define REG_SPI1_CR (*(WoReg*)0x4000C000U) /**< \brief (SPI1) Control Register */\r
+#define REG_SPI1_MR (*(RwReg*)0x4000C004U) /**< \brief (SPI1) Mode Register */\r
+#define REG_SPI1_RDR (*(RoReg*)0x4000C008U) /**< \brief (SPI1) Receive Data Register */\r
+#define REG_SPI1_TDR (*(WoReg*)0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */\r
+#define REG_SPI1_SR (*(RoReg*)0x4000C010U) /**< \brief (SPI1) Status Register */\r
+#define REG_SPI1_IER (*(WoReg*)0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */\r
+#define REG_SPI1_IDR (*(WoReg*)0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */\r
+#define REG_SPI1_IMR (*(RoReg*)0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */\r
+#define REG_SPI1_CSR (*(RwReg*)0x4000C030U) /**< \brief (SPI1) Chip Select Register */\r
+#define REG_SPI1_WPMR (*(RwReg*)0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */\r
+#define REG_SPI1_WPSR (*(RoReg*)0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_SPI1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_SSC_INSTANCE_\r
+#define _SAM3XA_SSC_INSTANCE_\r
+\r
+/* ========== Register definition for SSC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */\r
+#define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */\r
+#define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */\r
+#define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */\r
+#define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */\r
+#define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */\r
+#define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */\r
+#define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */\r
+#define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */\r
+#define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */\r
+#define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */\r
+#define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */\r
+#define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */\r
+#define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */\r
+#define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */\r
+#define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */\r
+#define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */\r
+#define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */\r
+#else\r
+#define REG_SSC_CR (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */\r
+#define REG_SSC_CMR (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */\r
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */\r
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */\r
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */\r
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */\r
+#define REG_SSC_RHR (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */\r
+#define REG_SSC_THR (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */\r
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */\r
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */\r
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */\r
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */\r
+#define REG_SSC_SR (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */\r
+#define REG_SSC_IER (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */\r
+#define REG_SSC_IDR (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */\r
+#define REG_SSC_IMR (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */\r
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */\r
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_SSC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_SUPC_INSTANCE_\r
+#define _SAM3XA_SUPC_INSTANCE_\r
+\r
+/* ========== Register definition for SUPC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SUPC_CR (0x400E1A10U) /**< \brief (SUPC) Supply Controller Control Register */\r
+#define REG_SUPC_SMMR (0x400E1A14U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */\r
+#define REG_SUPC_MR (0x400E1A18U) /**< \brief (SUPC) Supply Controller Mode Register */\r
+#define REG_SUPC_WUMR (0x400E1A1CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */\r
+#define REG_SUPC_WUIR (0x400E1A20U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */\r
+#define REG_SUPC_SR (0x400E1A24U) /**< \brief (SUPC) Supply Controller Status Register */\r
+#else\r
+#define REG_SUPC_CR (*(WoReg*)0x400E1A10U) /**< \brief (SUPC) Supply Controller Control Register */\r
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1A14U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */\r
+#define REG_SUPC_MR (*(RwReg*)0x400E1A18U) /**< \brief (SUPC) Supply Controller Mode Register */\r
+#define REG_SUPC_WUMR (*(RwReg*)0x400E1A1CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */\r
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1A20U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */\r
+#define REG_SUPC_SR (*(RoReg*)0x400E1A24U) /**< \brief (SUPC) Supply Controller Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_SUPC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_TC0_INSTANCE_\r
+#define _SAM3XA_TC0_INSTANCE_\r
+\r
+/* ========== Register definition for TC0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC0_CCR0 (0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */\r
+#define REG_TC0_CMR0 (0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */\r
+#define REG_TC0_SMMR0 (0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC0_CV0 (0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */\r
+#define REG_TC0_RA0 (0x40080014U) /**< \brief (TC0) Register A (channel = 0) */\r
+#define REG_TC0_RB0 (0x40080018U) /**< \brief (TC0) Register B (channel = 0) */\r
+#define REG_TC0_RC0 (0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */\r
+#define REG_TC0_SR0 (0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */\r
+#define REG_TC0_IER0 (0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC0_IDR0 (0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC0_IMR0 (0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC0_CCR1 (0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */\r
+#define REG_TC0_CMR1 (0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */\r
+#define REG_TC0_SMMR1 (0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC0_CV1 (0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */\r
+#define REG_TC0_RA1 (0x40080054U) /**< \brief (TC0) Register A (channel = 1) */\r
+#define REG_TC0_RB1 (0x40080058U) /**< \brief (TC0) Register B (channel = 1) */\r
+#define REG_TC0_RC1 (0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */\r
+#define REG_TC0_SR1 (0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */\r
+#define REG_TC0_IER1 (0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC0_IDR1 (0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC0_IMR1 (0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC0_CCR2 (0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */\r
+#define REG_TC0_CMR2 (0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */\r
+#define REG_TC0_SMMR2 (0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC0_CV2 (0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */\r
+#define REG_TC0_RA2 (0x40080094U) /**< \brief (TC0) Register A (channel = 2) */\r
+#define REG_TC0_RB2 (0x40080098U) /**< \brief (TC0) Register B (channel = 2) */\r
+#define REG_TC0_RC2 (0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */\r
+#define REG_TC0_SR2 (0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */\r
+#define REG_TC0_IER2 (0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC0_IDR2 (0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC0_IMR2 (0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC0_BCR (0x400800C0U) /**< \brief (TC0) Block Control Register */\r
+#define REG_TC0_BMR (0x400800C4U) /**< \brief (TC0) Block Mode Register */\r
+#define REG_TC0_QIER (0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */\r
+#define REG_TC0_QIDR (0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */\r
+#define REG_TC0_QIMR (0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */\r
+#define REG_TC0_QISR (0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */\r
+#define REG_TC0_FMR (0x400800D8U) /**< \brief (TC0) Fault Mode Register */\r
+#define REG_TC0_WPMR (0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */\r
+#else\r
+#define REG_TC0_CCR0 (*(WoReg*)0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */\r
+#define REG_TC0_CMR0 (*(RwReg*)0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */\r
+#define REG_TC0_SMMR0 (*(RwReg*)0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC0_CV0 (*(RoReg*)0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */\r
+#define REG_TC0_RA0 (*(RwReg*)0x40080014U) /**< \brief (TC0) Register A (channel = 0) */\r
+#define REG_TC0_RB0 (*(RwReg*)0x40080018U) /**< \brief (TC0) Register B (channel = 0) */\r
+#define REG_TC0_RC0 (*(RwReg*)0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */\r
+#define REG_TC0_SR0 (*(RoReg*)0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */\r
+#define REG_TC0_IER0 (*(WoReg*)0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC0_IDR0 (*(WoReg*)0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC0_IMR0 (*(RoReg*)0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC0_CCR1 (*(WoReg*)0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */\r
+#define REG_TC0_CMR1 (*(RwReg*)0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */\r
+#define REG_TC0_SMMR1 (*(RwReg*)0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC0_CV1 (*(RoReg*)0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */\r
+#define REG_TC0_RA1 (*(RwReg*)0x40080054U) /**< \brief (TC0) Register A (channel = 1) */\r
+#define REG_TC0_RB1 (*(RwReg*)0x40080058U) /**< \brief (TC0) Register B (channel = 1) */\r
+#define REG_TC0_RC1 (*(RwReg*)0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */\r
+#define REG_TC0_SR1 (*(RoReg*)0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */\r
+#define REG_TC0_IER1 (*(WoReg*)0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC0_IDR1 (*(WoReg*)0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC0_IMR1 (*(RoReg*)0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC0_CCR2 (*(WoReg*)0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */\r
+#define REG_TC0_CMR2 (*(RwReg*)0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */\r
+#define REG_TC0_SMMR2 (*(RwReg*)0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC0_CV2 (*(RoReg*)0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */\r
+#define REG_TC0_RA2 (*(RwReg*)0x40080094U) /**< \brief (TC0) Register A (channel = 2) */\r
+#define REG_TC0_RB2 (*(RwReg*)0x40080098U) /**< \brief (TC0) Register B (channel = 2) */\r
+#define REG_TC0_RC2 (*(RwReg*)0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */\r
+#define REG_TC0_SR2 (*(RoReg*)0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */\r
+#define REG_TC0_IER2 (*(WoReg*)0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC0_IDR2 (*(WoReg*)0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC0_IMR2 (*(RoReg*)0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC0_BCR (*(WoReg*)0x400800C0U) /**< \brief (TC0) Block Control Register */\r
+#define REG_TC0_BMR (*(RwReg*)0x400800C4U) /**< \brief (TC0) Block Mode Register */\r
+#define REG_TC0_QIER (*(WoReg*)0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */\r
+#define REG_TC0_QIDR (*(WoReg*)0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */\r
+#define REG_TC0_QIMR (*(RoReg*)0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */\r
+#define REG_TC0_QISR (*(RoReg*)0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */\r
+#define REG_TC0_FMR (*(RwReg*)0x400800D8U) /**< \brief (TC0) Fault Mode Register */\r
+#define REG_TC0_WPMR (*(RwReg*)0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_TC0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_TC1_INSTANCE_\r
+#define _SAM3XA_TC1_INSTANCE_\r
+\r
+/* ========== Register definition for TC1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC1_CCR0 (0x40084000U) /**< \brief (TC1) Channel Control Register (channel = 0) */\r
+#define REG_TC1_CMR0 (0x40084004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */\r
+#define REG_TC1_SMMR0 (0x40084008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC1_CV0 (0x40084010U) /**< \brief (TC1) Counter Value (channel = 0) */\r
+#define REG_TC1_RA0 (0x40084014U) /**< \brief (TC1) Register A (channel = 0) */\r
+#define REG_TC1_RB0 (0x40084018U) /**< \brief (TC1) Register B (channel = 0) */\r
+#define REG_TC1_RC0 (0x4008401CU) /**< \brief (TC1) Register C (channel = 0) */\r
+#define REG_TC1_SR0 (0x40084020U) /**< \brief (TC1) Status Register (channel = 0) */\r
+#define REG_TC1_IER0 (0x40084024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC1_IDR0 (0x40084028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC1_IMR0 (0x4008402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC1_CCR1 (0x40084040U) /**< \brief (TC1) Channel Control Register (channel = 1) */\r
+#define REG_TC1_CMR1 (0x40084044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */\r
+#define REG_TC1_SMMR1 (0x40084048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC1_CV1 (0x40084050U) /**< \brief (TC1) Counter Value (channel = 1) */\r
+#define REG_TC1_RA1 (0x40084054U) /**< \brief (TC1) Register A (channel = 1) */\r
+#define REG_TC1_RB1 (0x40084058U) /**< \brief (TC1) Register B (channel = 1) */\r
+#define REG_TC1_RC1 (0x4008405CU) /**< \brief (TC1) Register C (channel = 1) */\r
+#define REG_TC1_SR1 (0x40084060U) /**< \brief (TC1) Status Register (channel = 1) */\r
+#define REG_TC1_IER1 (0x40084064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC1_IDR1 (0x40084068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC1_IMR1 (0x4008406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC1_CCR2 (0x40084080U) /**< \brief (TC1) Channel Control Register (channel = 2) */\r
+#define REG_TC1_CMR2 (0x40084084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */\r
+#define REG_TC1_SMMR2 (0x40084088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC1_CV2 (0x40084090U) /**< \brief (TC1) Counter Value (channel = 2) */\r
+#define REG_TC1_RA2 (0x40084094U) /**< \brief (TC1) Register A (channel = 2) */\r
+#define REG_TC1_RB2 (0x40084098U) /**< \brief (TC1) Register B (channel = 2) */\r
+#define REG_TC1_RC2 (0x4008409CU) /**< \brief (TC1) Register C (channel = 2) */\r
+#define REG_TC1_SR2 (0x400840A0U) /**< \brief (TC1) Status Register (channel = 2) */\r
+#define REG_TC1_IER2 (0x400840A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC1_IDR2 (0x400840A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC1_IMR2 (0x400840ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC1_BCR (0x400840C0U) /**< \brief (TC1) Block Control Register */\r
+#define REG_TC1_BMR (0x400840C4U) /**< \brief (TC1) Block Mode Register */\r
+#define REG_TC1_QIER (0x400840C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */\r
+#define REG_TC1_QIDR (0x400840CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */\r
+#define REG_TC1_QIMR (0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */\r
+#define REG_TC1_QISR (0x400840D4U) /**< \brief (TC1) QDEC Interrupt Status Register */\r
+#define REG_TC1_FMR (0x400840D8U) /**< \brief (TC1) Fault Mode Register */\r
+#define REG_TC1_WPMR (0x400840E4U) /**< \brief (TC1) Write Protect Mode Register */\r
+#else\r
+#define REG_TC1_CCR0 (*(WoReg*)0x40084000U) /**< \brief (TC1) Channel Control Register (channel = 0) */\r
+#define REG_TC1_CMR0 (*(RwReg*)0x40084004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */\r
+#define REG_TC1_SMMR0 (*(RwReg*)0x40084008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC1_CV0 (*(RoReg*)0x40084010U) /**< \brief (TC1) Counter Value (channel = 0) */\r
+#define REG_TC1_RA0 (*(RwReg*)0x40084014U) /**< \brief (TC1) Register A (channel = 0) */\r
+#define REG_TC1_RB0 (*(RwReg*)0x40084018U) /**< \brief (TC1) Register B (channel = 0) */\r
+#define REG_TC1_RC0 (*(RwReg*)0x4008401CU) /**< \brief (TC1) Register C (channel = 0) */\r
+#define REG_TC1_SR0 (*(RoReg*)0x40084020U) /**< \brief (TC1) Status Register (channel = 0) */\r
+#define REG_TC1_IER0 (*(WoReg*)0x40084024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC1_IDR0 (*(WoReg*)0x40084028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC1_IMR0 (*(RoReg*)0x4008402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC1_CCR1 (*(WoReg*)0x40084040U) /**< \brief (TC1) Channel Control Register (channel = 1) */\r
+#define REG_TC1_CMR1 (*(RwReg*)0x40084044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */\r
+#define REG_TC1_SMMR1 (*(RwReg*)0x40084048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC1_CV1 (*(RoReg*)0x40084050U) /**< \brief (TC1) Counter Value (channel = 1) */\r
+#define REG_TC1_RA1 (*(RwReg*)0x40084054U) /**< \brief (TC1) Register A (channel = 1) */\r
+#define REG_TC1_RB1 (*(RwReg*)0x40084058U) /**< \brief (TC1) Register B (channel = 1) */\r
+#define REG_TC1_RC1 (*(RwReg*)0x4008405CU) /**< \brief (TC1) Register C (channel = 1) */\r
+#define REG_TC1_SR1 (*(RoReg*)0x40084060U) /**< \brief (TC1) Status Register (channel = 1) */\r
+#define REG_TC1_IER1 (*(WoReg*)0x40084064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC1_IDR1 (*(WoReg*)0x40084068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC1_IMR1 (*(RoReg*)0x4008406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC1_CCR2 (*(WoReg*)0x40084080U) /**< \brief (TC1) Channel Control Register (channel = 2) */\r
+#define REG_TC1_CMR2 (*(RwReg*)0x40084084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */\r
+#define REG_TC1_SMMR2 (*(RwReg*)0x40084088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC1_CV2 (*(RoReg*)0x40084090U) /**< \brief (TC1) Counter Value (channel = 2) */\r
+#define REG_TC1_RA2 (*(RwReg*)0x40084094U) /**< \brief (TC1) Register A (channel = 2) */\r
+#define REG_TC1_RB2 (*(RwReg*)0x40084098U) /**< \brief (TC1) Register B (channel = 2) */\r
+#define REG_TC1_RC2 (*(RwReg*)0x4008409CU) /**< \brief (TC1) Register C (channel = 2) */\r
+#define REG_TC1_SR2 (*(RoReg*)0x400840A0U) /**< \brief (TC1) Status Register (channel = 2) */\r
+#define REG_TC1_IER2 (*(WoReg*)0x400840A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC1_IDR2 (*(WoReg*)0x400840A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC1_IMR2 (*(RoReg*)0x400840ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC1_BCR (*(WoReg*)0x400840C0U) /**< \brief (TC1) Block Control Register */\r
+#define REG_TC1_BMR (*(RwReg*)0x400840C4U) /**< \brief (TC1) Block Mode Register */\r
+#define REG_TC1_QIER (*(WoReg*)0x400840C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */\r
+#define REG_TC1_QIDR (*(WoReg*)0x400840CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */\r
+#define REG_TC1_QIMR (*(RoReg*)0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */\r
+#define REG_TC1_QISR (*(RoReg*)0x400840D4U) /**< \brief (TC1) QDEC Interrupt Status Register */\r
+#define REG_TC1_FMR (*(RwReg*)0x400840D8U) /**< \brief (TC1) Fault Mode Register */\r
+#define REG_TC1_WPMR (*(RwReg*)0x400840E4U) /**< \brief (TC1) Write Protect Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_TC1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_TC2_INSTANCE_\r
+#define _SAM3XA_TC2_INSTANCE_\r
+\r
+/* ========== Register definition for TC2 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC2_CCR0 (0x40088000U) /**< \brief (TC2) Channel Control Register (channel = 0) */\r
+#define REG_TC2_CMR0 (0x40088004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */\r
+#define REG_TC2_SMMR0 (0x40088008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC2_CV0 (0x40088010U) /**< \brief (TC2) Counter Value (channel = 0) */\r
+#define REG_TC2_RA0 (0x40088014U) /**< \brief (TC2) Register A (channel = 0) */\r
+#define REG_TC2_RB0 (0x40088018U) /**< \brief (TC2) Register B (channel = 0) */\r
+#define REG_TC2_RC0 (0x4008801CU) /**< \brief (TC2) Register C (channel = 0) */\r
+#define REG_TC2_SR0 (0x40088020U) /**< \brief (TC2) Status Register (channel = 0) */\r
+#define REG_TC2_IER0 (0x40088024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC2_IDR0 (0x40088028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC2_IMR0 (0x4008802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC2_CCR1 (0x40088040U) /**< \brief (TC2) Channel Control Register (channel = 1) */\r
+#define REG_TC2_CMR1 (0x40088044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */\r
+#define REG_TC2_SMMR1 (0x40088048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC2_CV1 (0x40088050U) /**< \brief (TC2) Counter Value (channel = 1) */\r
+#define REG_TC2_RA1 (0x40088054U) /**< \brief (TC2) Register A (channel = 1) */\r
+#define REG_TC2_RB1 (0x40088058U) /**< \brief (TC2) Register B (channel = 1) */\r
+#define REG_TC2_RC1 (0x4008805CU) /**< \brief (TC2) Register C (channel = 1) */\r
+#define REG_TC2_SR1 (0x40088060U) /**< \brief (TC2) Status Register (channel = 1) */\r
+#define REG_TC2_IER1 (0x40088064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC2_IDR1 (0x40088068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC2_IMR1 (0x4008806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC2_CCR2 (0x40088080U) /**< \brief (TC2) Channel Control Register (channel = 2) */\r
+#define REG_TC2_CMR2 (0x40088084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */\r
+#define REG_TC2_SMMR2 (0x40088088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC2_CV2 (0x40088090U) /**< \brief (TC2) Counter Value (channel = 2) */\r
+#define REG_TC2_RA2 (0x40088094U) /**< \brief (TC2) Register A (channel = 2) */\r
+#define REG_TC2_RB2 (0x40088098U) /**< \brief (TC2) Register B (channel = 2) */\r
+#define REG_TC2_RC2 (0x4008809CU) /**< \brief (TC2) Register C (channel = 2) */\r
+#define REG_TC2_SR2 (0x400880A0U) /**< \brief (TC2) Status Register (channel = 2) */\r
+#define REG_TC2_IER2 (0x400880A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC2_IDR2 (0x400880A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC2_IMR2 (0x400880ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC2_BCR (0x400880C0U) /**< \brief (TC2) Block Control Register */\r
+#define REG_TC2_BMR (0x400880C4U) /**< \brief (TC2) Block Mode Register */\r
+#define REG_TC2_QIER (0x400880C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */\r
+#define REG_TC2_QIDR (0x400880CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */\r
+#define REG_TC2_QIMR (0x400880D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */\r
+#define REG_TC2_QISR (0x400880D4U) /**< \brief (TC2) QDEC Interrupt Status Register */\r
+#define REG_TC2_FMR (0x400880D8U) /**< \brief (TC2) Fault Mode Register */\r
+#define REG_TC2_WPMR (0x400880E4U) /**< \brief (TC2) Write Protect Mode Register */\r
+#else\r
+#define REG_TC2_CCR0 (*(WoReg*)0x40088000U) /**< \brief (TC2) Channel Control Register (channel = 0) */\r
+#define REG_TC2_CMR0 (*(RwReg*)0x40088004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */\r
+#define REG_TC2_SMMR0 (*(RwReg*)0x40088008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC2_CV0 (*(RoReg*)0x40088010U) /**< \brief (TC2) Counter Value (channel = 0) */\r
+#define REG_TC2_RA0 (*(RwReg*)0x40088014U) /**< \brief (TC2) Register A (channel = 0) */\r
+#define REG_TC2_RB0 (*(RwReg*)0x40088018U) /**< \brief (TC2) Register B (channel = 0) */\r
+#define REG_TC2_RC0 (*(RwReg*)0x4008801CU) /**< \brief (TC2) Register C (channel = 0) */\r
+#define REG_TC2_SR0 (*(RoReg*)0x40088020U) /**< \brief (TC2) Status Register (channel = 0) */\r
+#define REG_TC2_IER0 (*(WoReg*)0x40088024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC2_IDR0 (*(WoReg*)0x40088028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC2_IMR0 (*(RoReg*)0x4008802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC2_CCR1 (*(WoReg*)0x40088040U) /**< \brief (TC2) Channel Control Register (channel = 1) */\r
+#define REG_TC2_CMR1 (*(RwReg*)0x40088044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */\r
+#define REG_TC2_SMMR1 (*(RwReg*)0x40088048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC2_CV1 (*(RoReg*)0x40088050U) /**< \brief (TC2) Counter Value (channel = 1) */\r
+#define REG_TC2_RA1 (*(RwReg*)0x40088054U) /**< \brief (TC2) Register A (channel = 1) */\r
+#define REG_TC2_RB1 (*(RwReg*)0x40088058U) /**< \brief (TC2) Register B (channel = 1) */\r
+#define REG_TC2_RC1 (*(RwReg*)0x4008805CU) /**< \brief (TC2) Register C (channel = 1) */\r
+#define REG_TC2_SR1 (*(RoReg*)0x40088060U) /**< \brief (TC2) Status Register (channel = 1) */\r
+#define REG_TC2_IER1 (*(WoReg*)0x40088064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC2_IDR1 (*(WoReg*)0x40088068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC2_IMR1 (*(RoReg*)0x4008806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC2_CCR2 (*(WoReg*)0x40088080U) /**< \brief (TC2) Channel Control Register (channel = 2) */\r
+#define REG_TC2_CMR2 (*(RwReg*)0x40088084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */\r
+#define REG_TC2_SMMR2 (*(RwReg*)0x40088088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC2_CV2 (*(RoReg*)0x40088090U) /**< \brief (TC2) Counter Value (channel = 2) */\r
+#define REG_TC2_RA2 (*(RwReg*)0x40088094U) /**< \brief (TC2) Register A (channel = 2) */\r
+#define REG_TC2_RB2 (*(RwReg*)0x40088098U) /**< \brief (TC2) Register B (channel = 2) */\r
+#define REG_TC2_RC2 (*(RwReg*)0x4008809CU) /**< \brief (TC2) Register C (channel = 2) */\r
+#define REG_TC2_SR2 (*(RoReg*)0x400880A0U) /**< \brief (TC2) Status Register (channel = 2) */\r
+#define REG_TC2_IER2 (*(WoReg*)0x400880A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC2_IDR2 (*(WoReg*)0x400880A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC2_IMR2 (*(RoReg*)0x400880ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC2_BCR (*(WoReg*)0x400880C0U) /**< \brief (TC2) Block Control Register */\r
+#define REG_TC2_BMR (*(RwReg*)0x400880C4U) /**< \brief (TC2) Block Mode Register */\r
+#define REG_TC2_QIER (*(WoReg*)0x400880C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */\r
+#define REG_TC2_QIDR (*(WoReg*)0x400880CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */\r
+#define REG_TC2_QIMR (*(RoReg*)0x400880D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */\r
+#define REG_TC2_QISR (*(RoReg*)0x400880D4U) /**< \brief (TC2) QDEC Interrupt Status Register */\r
+#define REG_TC2_FMR (*(RwReg*)0x400880D8U) /**< \brief (TC2) Fault Mode Register */\r
+#define REG_TC2_WPMR (*(RwReg*)0x400880E4U) /**< \brief (TC2) Write Protect Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_TC2_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_TRNG_INSTANCE_\r
+#define _SAM3XA_TRNG_INSTANCE_\r
+\r
+/* ========== Register definition for TRNG peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TRNG_CR (0x400BC000U) /**< \brief (TRNG) Control Register */\r
+#define REG_TRNG_IER (0x400BC010U) /**< \brief (TRNG) Interrupt Enable Register */\r
+#define REG_TRNG_IDR (0x400BC014U) /**< \brief (TRNG) Interrupt Disable Register */\r
+#define REG_TRNG_IMR (0x400BC018U) /**< \brief (TRNG) Interrupt Mask Register */\r
+#define REG_TRNG_ISR (0x400BC01CU) /**< \brief (TRNG) Interrupt Status Register */\r
+#define REG_TRNG_ODATA (0x400BC050U) /**< \brief (TRNG) Output Data Register */\r
+#else\r
+#define REG_TRNG_CR (*(WoReg*)0x400BC000U) /**< \brief (TRNG) Control Register */\r
+#define REG_TRNG_IER (*(WoReg*)0x400BC010U) /**< \brief (TRNG) Interrupt Enable Register */\r
+#define REG_TRNG_IDR (*(WoReg*)0x400BC014U) /**< \brief (TRNG) Interrupt Disable Register */\r
+#define REG_TRNG_IMR (*(RoReg*)0x400BC018U) /**< \brief (TRNG) Interrupt Mask Register */\r
+#define REG_TRNG_ISR (*(RoReg*)0x400BC01CU) /**< \brief (TRNG) Interrupt Status Register */\r
+#define REG_TRNG_ODATA (*(RoReg*)0x400BC050U) /**< \brief (TRNG) Output Data Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_TRNG_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_TWI0_INSTANCE_\r
+#define _SAM3XA_TWI0_INSTANCE_\r
+\r
+/* ========== Register definition for TWI0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TWI0_CR (0x4008C000U) /**< \brief (TWI0) Control Register */\r
+#define REG_TWI0_MMR (0x4008C004U) /**< \brief (TWI0) Master Mode Register */\r
+#define REG_TWI0_SMR (0x4008C008U) /**< \brief (TWI0) Slave Mode Register */\r
+#define REG_TWI0_IADR (0x4008C00CU) /**< \brief (TWI0) Internal Address Register */\r
+#define REG_TWI0_CWGR (0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */\r
+#define REG_TWI0_SR (0x4008C020U) /**< \brief (TWI0) Status Register */\r
+#define REG_TWI0_IER (0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */\r
+#define REG_TWI0_IDR (0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */\r
+#define REG_TWI0_IMR (0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */\r
+#define REG_TWI0_RHR (0x4008C030U) /**< \brief (TWI0) Receive Holding Register */\r
+#define REG_TWI0_THR (0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */\r
+#define REG_TWI0_RPR (0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */\r
+#define REG_TWI0_RCR (0x4008C104U) /**< \brief (TWI0) Receive Counter Register */\r
+#define REG_TWI0_TPR (0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */\r
+#define REG_TWI0_TCR (0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */\r
+#define REG_TWI0_RNPR (0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */\r
+#define REG_TWI0_RNCR (0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */\r
+#define REG_TWI0_TNPR (0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */\r
+#define REG_TWI0_TNCR (0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */\r
+#define REG_TWI0_PTCR (0x4008C120U) /**< \brief (TWI0) Transfer Control Register */\r
+#define REG_TWI0_PTSR (0x4008C124U) /**< \brief (TWI0) Transfer Status Register */\r
+#else\r
+#define REG_TWI0_CR (*(WoReg*)0x4008C000U) /**< \brief (TWI0) Control Register */\r
+#define REG_TWI0_MMR (*(RwReg*)0x4008C004U) /**< \brief (TWI0) Master Mode Register */\r
+#define REG_TWI0_SMR (*(RwReg*)0x4008C008U) /**< \brief (TWI0) Slave Mode Register */\r
+#define REG_TWI0_IADR (*(RwReg*)0x4008C00CU) /**< \brief (TWI0) Internal Address Register */\r
+#define REG_TWI0_CWGR (*(RwReg*)0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */\r
+#define REG_TWI0_SR (*(RoReg*)0x4008C020U) /**< \brief (TWI0) Status Register */\r
+#define REG_TWI0_IER (*(WoReg*)0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */\r
+#define REG_TWI0_IDR (*(WoReg*)0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */\r
+#define REG_TWI0_IMR (*(RoReg*)0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */\r
+#define REG_TWI0_RHR (*(RoReg*)0x4008C030U) /**< \brief (TWI0) Receive Holding Register */\r
+#define REG_TWI0_THR (*(WoReg*)0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */\r
+#define REG_TWI0_RPR (*(RwReg*)0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */\r
+#define REG_TWI0_RCR (*(RwReg*)0x4008C104U) /**< \brief (TWI0) Receive Counter Register */\r
+#define REG_TWI0_TPR (*(RwReg*)0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */\r
+#define REG_TWI0_TCR (*(RwReg*)0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */\r
+#define REG_TWI0_RNPR (*(RwReg*)0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */\r
+#define REG_TWI0_RNCR (*(RwReg*)0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */\r
+#define REG_TWI0_TNPR (*(RwReg*)0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */\r
+#define REG_TWI0_TNCR (*(RwReg*)0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */\r
+#define REG_TWI0_PTCR (*(WoReg*)0x4008C120U) /**< \brief (TWI0) Transfer Control Register */\r
+#define REG_TWI0_PTSR (*(RoReg*)0x4008C124U) /**< \brief (TWI0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_TWI0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_TWI1_INSTANCE_\r
+#define _SAM3XA_TWI1_INSTANCE_\r
+\r
+/* ========== Register definition for TWI1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TWI1_CR (0x40090000U) /**< \brief (TWI1) Control Register */\r
+#define REG_TWI1_MMR (0x40090004U) /**< \brief (TWI1) Master Mode Register */\r
+#define REG_TWI1_SMR (0x40090008U) /**< \brief (TWI1) Slave Mode Register */\r
+#define REG_TWI1_IADR (0x4009000CU) /**< \brief (TWI1) Internal Address Register */\r
+#define REG_TWI1_CWGR (0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */\r
+#define REG_TWI1_SR (0x40090020U) /**< \brief (TWI1) Status Register */\r
+#define REG_TWI1_IER (0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */\r
+#define REG_TWI1_IDR (0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */\r
+#define REG_TWI1_IMR (0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */\r
+#define REG_TWI1_RHR (0x40090030U) /**< \brief (TWI1) Receive Holding Register */\r
+#define REG_TWI1_THR (0x40090034U) /**< \brief (TWI1) Transmit Holding Register */\r
+#define REG_TWI1_RPR (0x40090100U) /**< \brief (TWI1) Receive Pointer Register */\r
+#define REG_TWI1_RCR (0x40090104U) /**< \brief (TWI1) Receive Counter Register */\r
+#define REG_TWI1_TPR (0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */\r
+#define REG_TWI1_TCR (0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */\r
+#define REG_TWI1_RNPR (0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */\r
+#define REG_TWI1_RNCR (0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */\r
+#define REG_TWI1_TNPR (0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */\r
+#define REG_TWI1_TNCR (0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */\r
+#define REG_TWI1_PTCR (0x40090120U) /**< \brief (TWI1) Transfer Control Register */\r
+#define REG_TWI1_PTSR (0x40090124U) /**< \brief (TWI1) Transfer Status Register */\r
+#else\r
+#define REG_TWI1_CR (*(WoReg*)0x40090000U) /**< \brief (TWI1) Control Register */\r
+#define REG_TWI1_MMR (*(RwReg*)0x40090004U) /**< \brief (TWI1) Master Mode Register */\r
+#define REG_TWI1_SMR (*(RwReg*)0x40090008U) /**< \brief (TWI1) Slave Mode Register */\r
+#define REG_TWI1_IADR (*(RwReg*)0x4009000CU) /**< \brief (TWI1) Internal Address Register */\r
+#define REG_TWI1_CWGR (*(RwReg*)0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */\r
+#define REG_TWI1_SR (*(RoReg*)0x40090020U) /**< \brief (TWI1) Status Register */\r
+#define REG_TWI1_IER (*(WoReg*)0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */\r
+#define REG_TWI1_IDR (*(WoReg*)0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */\r
+#define REG_TWI1_IMR (*(RoReg*)0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */\r
+#define REG_TWI1_RHR (*(RoReg*)0x40090030U) /**< \brief (TWI1) Receive Holding Register */\r
+#define REG_TWI1_THR (*(WoReg*)0x40090034U) /**< \brief (TWI1) Transmit Holding Register */\r
+#define REG_TWI1_RPR (*(RwReg*)0x40090100U) /**< \brief (TWI1) Receive Pointer Register */\r
+#define REG_TWI1_RCR (*(RwReg*)0x40090104U) /**< \brief (TWI1) Receive Counter Register */\r
+#define REG_TWI1_TPR (*(RwReg*)0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */\r
+#define REG_TWI1_TCR (*(RwReg*)0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */\r
+#define REG_TWI1_RNPR (*(RwReg*)0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */\r
+#define REG_TWI1_RNCR (*(RwReg*)0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */\r
+#define REG_TWI1_TNPR (*(RwReg*)0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */\r
+#define REG_TWI1_TNCR (*(RwReg*)0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */\r
+#define REG_TWI1_PTCR (*(WoReg*)0x40090120U) /**< \brief (TWI1) Transfer Control Register */\r
+#define REG_TWI1_PTSR (*(RoReg*)0x40090124U) /**< \brief (TWI1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_TWI1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_UART_INSTANCE_\r
+#define _SAM3XA_UART_INSTANCE_\r
+\r
+/* ========== Register definition for UART peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_UART_CR (0x400E0800U) /**< \brief (UART) Control Register */\r
+#define REG_UART_MR (0x400E0804U) /**< \brief (UART) Mode Register */\r
+#define REG_UART_IER (0x400E0808U) /**< \brief (UART) Interrupt Enable Register */\r
+#define REG_UART_IDR (0x400E080CU) /**< \brief (UART) Interrupt Disable Register */\r
+#define REG_UART_IMR (0x400E0810U) /**< \brief (UART) Interrupt Mask Register */\r
+#define REG_UART_SR (0x400E0814U) /**< \brief (UART) Status Register */\r
+#define REG_UART_RHR (0x400E0818U) /**< \brief (UART) Receive Holding Register */\r
+#define REG_UART_THR (0x400E081CU) /**< \brief (UART) Transmit Holding Register */\r
+#define REG_UART_BRGR (0x400E0820U) /**< \brief (UART) Baud Rate Generator Register */\r
+#define REG_UART_RPR (0x400E0900U) /**< \brief (UART) Receive Pointer Register */\r
+#define REG_UART_RCR (0x400E0904U) /**< \brief (UART) Receive Counter Register */\r
+#define REG_UART_TPR (0x400E0908U) /**< \brief (UART) Transmit Pointer Register */\r
+#define REG_UART_TCR (0x400E090CU) /**< \brief (UART) Transmit Counter Register */\r
+#define REG_UART_RNPR (0x400E0910U) /**< \brief (UART) Receive Next Pointer Register */\r
+#define REG_UART_RNCR (0x400E0914U) /**< \brief (UART) Receive Next Counter Register */\r
+#define REG_UART_TNPR (0x400E0918U) /**< \brief (UART) Transmit Next Pointer Register */\r
+#define REG_UART_TNCR (0x400E091CU) /**< \brief (UART) Transmit Next Counter Register */\r
+#define REG_UART_PTCR (0x400E0920U) /**< \brief (UART) Transfer Control Register */\r
+#define REG_UART_PTSR (0x400E0924U) /**< \brief (UART) Transfer Status Register */\r
+#else\r
+#define REG_UART_CR (*(WoReg*)0x400E0800U) /**< \brief (UART) Control Register */\r
+#define REG_UART_MR (*(RwReg*)0x400E0804U) /**< \brief (UART) Mode Register */\r
+#define REG_UART_IER (*(WoReg*)0x400E0808U) /**< \brief (UART) Interrupt Enable Register */\r
+#define REG_UART_IDR (*(WoReg*)0x400E080CU) /**< \brief (UART) Interrupt Disable Register */\r
+#define REG_UART_IMR (*(RoReg*)0x400E0810U) /**< \brief (UART) Interrupt Mask Register */\r
+#define REG_UART_SR (*(RoReg*)0x400E0814U) /**< \brief (UART) Status Register */\r
+#define REG_UART_RHR (*(RoReg*)0x400E0818U) /**< \brief (UART) Receive Holding Register */\r
+#define REG_UART_THR (*(WoReg*)0x400E081CU) /**< \brief (UART) Transmit Holding Register */\r
+#define REG_UART_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART) Baud Rate Generator Register */\r
+#define REG_UART_RPR (*(RwReg*)0x400E0900U) /**< \brief (UART) Receive Pointer Register */\r
+#define REG_UART_RCR (*(RwReg*)0x400E0904U) /**< \brief (UART) Receive Counter Register */\r
+#define REG_UART_TPR (*(RwReg*)0x400E0908U) /**< \brief (UART) Transmit Pointer Register */\r
+#define REG_UART_TCR (*(RwReg*)0x400E090CU) /**< \brief (UART) Transmit Counter Register */\r
+#define REG_UART_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART) Receive Next Pointer Register */\r
+#define REG_UART_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART) Receive Next Counter Register */\r
+#define REG_UART_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART) Transmit Next Pointer Register */\r
+#define REG_UART_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART) Transmit Next Counter Register */\r
+#define REG_UART_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART) Transfer Control Register */\r
+#define REG_UART_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_UART_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_UOTGHS_INSTANCE_\r
+#define _SAM3XA_UOTGHS_INSTANCE_\r
+\r
+/* ========== Register definition for UOTGHS peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_UOTGHS_DEVCTRL (0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */\r
+#define REG_UOTGHS_DEVISR (0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */\r
+#define REG_UOTGHS_DEVICR (0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */\r
+#define REG_UOTGHS_DEVIFR (0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */\r
+#define REG_UOTGHS_DEVIMR (0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */\r
+#define REG_UOTGHS_DEVIDR (0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */\r
+#define REG_UOTGHS_DEVIER (0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */\r
+#define REG_UOTGHS_DEVEPT (0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */\r
+#define REG_UOTGHS_DEVFNUM (0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */\r
+#define REG_UOTGHS_DEVEPTCFG (0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTISR (0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTICR (0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTIFR (0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTIMR (0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTIER (0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTIDR (0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */\r
+#define REG_UOTGHS_DEVDMANXTDSC1 (0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */\r
+#define REG_UOTGHS_DEVDMAADDRESS1 (0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */\r
+#define REG_UOTGHS_DEVDMACONTROL1 (0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */\r
+#define REG_UOTGHS_DEVDMASTATUS1 (0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */\r
+#define REG_UOTGHS_DEVDMANXTDSC2 (0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */\r
+#define REG_UOTGHS_DEVDMAADDRESS2 (0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */\r
+#define REG_UOTGHS_DEVDMACONTROL2 (0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */\r
+#define REG_UOTGHS_DEVDMASTATUS2 (0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */\r
+#define REG_UOTGHS_DEVDMANXTDSC3 (0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */\r
+#define REG_UOTGHS_DEVDMAADDRESS3 (0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */\r
+#define REG_UOTGHS_DEVDMACONTROL3 (0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */\r
+#define REG_UOTGHS_DEVDMASTATUS3 (0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */\r
+#define REG_UOTGHS_DEVDMANXTDSC4 (0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */\r
+#define REG_UOTGHS_DEVDMAADDRESS4 (0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */\r
+#define REG_UOTGHS_DEVDMACONTROL4 (0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */\r
+#define REG_UOTGHS_DEVDMASTATUS4 (0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */\r
+#define REG_UOTGHS_DEVDMANXTDSC5 (0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */\r
+#define REG_UOTGHS_DEVDMAADDRESS5 (0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */\r
+#define REG_UOTGHS_DEVDMACONTROL5 (0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */\r
+#define REG_UOTGHS_DEVDMASTATUS5 (0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */\r
+#define REG_UOTGHS_DEVDMANXTDSC6 (0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */\r
+#define REG_UOTGHS_DEVDMAADDRESS6 (0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */\r
+#define REG_UOTGHS_DEVDMACONTROL6 (0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */\r
+#define REG_UOTGHS_DEVDMASTATUS6 (0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */\r
+#define REG_UOTGHS_DEVDMANXTDSC7 (0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */\r
+#define REG_UOTGHS_DEVDMAADDRESS7 (0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */\r
+#define REG_UOTGHS_DEVDMACONTROL7 (0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */\r
+#define REG_UOTGHS_DEVDMASTATUS7 (0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */\r
+#define REG_UOTGHS_HSTCTRL (0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */\r
+#define REG_UOTGHS_HSTISR (0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */\r
+#define REG_UOTGHS_HSTICR (0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */\r
+#define REG_UOTGHS_HSTIFR (0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */\r
+#define REG_UOTGHS_HSTIMR (0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */\r
+#define REG_UOTGHS_HSTIDR (0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */\r
+#define REG_UOTGHS_HSTIER (0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */\r
+#define REG_UOTGHS_HSTPIP (0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */\r
+#define REG_UOTGHS_HSTFNUM (0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */\r
+#define REG_UOTGHS_HSTADDR1 (0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */\r
+#define REG_UOTGHS_HSTADDR2 (0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */\r
+#define REG_UOTGHS_HSTADDR3 (0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */\r
+#define REG_UOTGHS_HSTPIPCFG (0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPISR (0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPICR (0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPIFR (0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPIMR (0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPIER (0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPIDR (0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPINRQ (0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPERR (0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */\r
+#define REG_UOTGHS_HSTDMANXTDSC1 (0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */\r
+#define REG_UOTGHS_HSTDMAADDRESS1 (0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */\r
+#define REG_UOTGHS_HSTDMACONTROL1 (0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */\r
+#define REG_UOTGHS_HSTDMASTATUS1 (0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */\r
+#define REG_UOTGHS_HSTDMANXTDSC2 (0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */\r
+#define REG_UOTGHS_HSTDMAADDRESS2 (0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */\r
+#define REG_UOTGHS_HSTDMACONTROL2 (0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */\r
+#define REG_UOTGHS_HSTDMASTATUS2 (0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */\r
+#define REG_UOTGHS_HSTDMANXTDSC3 (0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */\r
+#define REG_UOTGHS_HSTDMAADDRESS3 (0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */\r
+#define REG_UOTGHS_HSTDMACONTROL3 (0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */\r
+#define REG_UOTGHS_HSTDMASTATUS3 (0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */\r
+#define REG_UOTGHS_HSTDMANXTDSC4 (0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */\r
+#define REG_UOTGHS_HSTDMAADDRESS4 (0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */\r
+#define REG_UOTGHS_HSTDMACONTROL4 (0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */\r
+#define REG_UOTGHS_HSTDMASTATUS4 (0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */\r
+#define REG_UOTGHS_HSTDMANXTDSC5 (0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */\r
+#define REG_UOTGHS_HSTDMAADDRESS5 (0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */\r
+#define REG_UOTGHS_HSTDMACONTROL5 (0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */\r
+#define REG_UOTGHS_HSTDMASTATUS5 (0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */\r
+#define REG_UOTGHS_HSTDMANXTDSC6 (0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */\r
+#define REG_UOTGHS_HSTDMAADDRESS6 (0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */\r
+#define REG_UOTGHS_HSTDMACONTROL6 (0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */\r
+#define REG_UOTGHS_HSTDMASTATUS6 (0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */\r
+#define REG_UOTGHS_HSTDMANXTDSC7 (0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */\r
+#define REG_UOTGHS_HSTDMAADDRESS7 (0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */\r
+#define REG_UOTGHS_HSTDMACONTROL7 (0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */\r
+#define REG_UOTGHS_HSTDMASTATUS7 (0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */\r
+#define REG_UOTGHS_CTRL (0x400AC800U) /**< \brief (UOTGHS) General Control Register */\r
+#define REG_UOTGHS_SR (0x400AC804U) /**< \brief (UOTGHS) General Status Register */\r
+#define REG_UOTGHS_SCR (0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */\r
+#define REG_UOTGHS_SFR (0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */\r
+#define REG_UOTGHS_FSM (0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */\r
+#else\r
+#define REG_UOTGHS_DEVCTRL (*(RwReg*)0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */\r
+#define REG_UOTGHS_DEVISR (*(RoReg*)0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */\r
+#define REG_UOTGHS_DEVICR (*(WoReg*)0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */\r
+#define REG_UOTGHS_DEVIFR (*(WoReg*)0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */\r
+#define REG_UOTGHS_DEVIMR (*(RoReg*)0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */\r
+#define REG_UOTGHS_DEVIDR (*(WoReg*)0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */\r
+#define REG_UOTGHS_DEVIER (*(WoReg*)0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */\r
+#define REG_UOTGHS_DEVEPT (*(RwReg*)0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */\r
+#define REG_UOTGHS_DEVFNUM (*(RoReg*)0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */\r
+#define REG_UOTGHS_DEVEPTCFG (*(RwReg*)0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTISR (*(RoReg*)0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTICR (*(WoReg*)0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTIFR (*(WoReg*)0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTIMR (*(RoReg*)0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTIER (*(WoReg*)0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */\r
+#define REG_UOTGHS_DEVEPTIDR (*(WoReg*)0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */\r
+#define REG_UOTGHS_DEVDMANXTDSC1 (*(RwReg*)0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */\r
+#define REG_UOTGHS_DEVDMAADDRESS1 (*(RwReg*)0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */\r
+#define REG_UOTGHS_DEVDMACONTROL1 (*(RwReg*)0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */\r
+#define REG_UOTGHS_DEVDMASTATUS1 (*(RwReg*)0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */\r
+#define REG_UOTGHS_DEVDMANXTDSC2 (*(RwReg*)0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */\r
+#define REG_UOTGHS_DEVDMAADDRESS2 (*(RwReg*)0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */\r
+#define REG_UOTGHS_DEVDMACONTROL2 (*(RwReg*)0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */\r
+#define REG_UOTGHS_DEVDMASTATUS2 (*(RwReg*)0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */\r
+#define REG_UOTGHS_DEVDMANXTDSC3 (*(RwReg*)0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */\r
+#define REG_UOTGHS_DEVDMAADDRESS3 (*(RwReg*)0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */\r
+#define REG_UOTGHS_DEVDMACONTROL3 (*(RwReg*)0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */\r
+#define REG_UOTGHS_DEVDMASTATUS3 (*(RwReg*)0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */\r
+#define REG_UOTGHS_DEVDMANXTDSC4 (*(RwReg*)0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */\r
+#define REG_UOTGHS_DEVDMAADDRESS4 (*(RwReg*)0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */\r
+#define REG_UOTGHS_DEVDMACONTROL4 (*(RwReg*)0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */\r
+#define REG_UOTGHS_DEVDMASTATUS4 (*(RwReg*)0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */\r
+#define REG_UOTGHS_DEVDMANXTDSC5 (*(RwReg*)0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */\r
+#define REG_UOTGHS_DEVDMAADDRESS5 (*(RwReg*)0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */\r
+#define REG_UOTGHS_DEVDMACONTROL5 (*(RwReg*)0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */\r
+#define REG_UOTGHS_DEVDMASTATUS5 (*(RwReg*)0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */\r
+#define REG_UOTGHS_DEVDMANXTDSC6 (*(RwReg*)0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */\r
+#define REG_UOTGHS_DEVDMAADDRESS6 (*(RwReg*)0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */\r
+#define REG_UOTGHS_DEVDMACONTROL6 (*(RwReg*)0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */\r
+#define REG_UOTGHS_DEVDMASTATUS6 (*(RwReg*)0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */\r
+#define REG_UOTGHS_DEVDMANXTDSC7 (*(RwReg*)0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */\r
+#define REG_UOTGHS_DEVDMAADDRESS7 (*(RwReg*)0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */\r
+#define REG_UOTGHS_DEVDMACONTROL7 (*(RwReg*)0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */\r
+#define REG_UOTGHS_DEVDMASTATUS7 (*(RwReg*)0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */\r
+#define REG_UOTGHS_HSTCTRL (*(RwReg*)0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */\r
+#define REG_UOTGHS_HSTISR (*(RoReg*)0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */\r
+#define REG_UOTGHS_HSTICR (*(WoReg*)0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */\r
+#define REG_UOTGHS_HSTIFR (*(WoReg*)0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */\r
+#define REG_UOTGHS_HSTIMR (*(RoReg*)0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */\r
+#define REG_UOTGHS_HSTIDR (*(WoReg*)0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */\r
+#define REG_UOTGHS_HSTIER (*(WoReg*)0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */\r
+#define REG_UOTGHS_HSTPIP (*(RwReg*)0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */\r
+#define REG_UOTGHS_HSTFNUM (*(RwReg*)0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */\r
+#define REG_UOTGHS_HSTADDR1 (*(RwReg*)0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */\r
+#define REG_UOTGHS_HSTADDR2 (*(RwReg*)0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */\r
+#define REG_UOTGHS_HSTADDR3 (*(RwReg*)0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */\r
+#define REG_UOTGHS_HSTPIPCFG (*(RwReg*)0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPISR (*(RoReg*)0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPICR (*(WoReg*)0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPIFR (*(WoReg*)0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPIMR (*(RoReg*)0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPIER (*(WoReg*)0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPIDR (*(WoReg*)0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPINRQ (*(RwReg*)0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */\r
+#define REG_UOTGHS_HSTPIPERR (*(RwReg*)0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */\r
+#define REG_UOTGHS_HSTDMANXTDSC1 (*(RwReg*)0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */\r
+#define REG_UOTGHS_HSTDMAADDRESS1 (*(RwReg*)0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */\r
+#define REG_UOTGHS_HSTDMACONTROL1 (*(RwReg*)0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */\r
+#define REG_UOTGHS_HSTDMASTATUS1 (*(RwReg*)0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */\r
+#define REG_UOTGHS_HSTDMANXTDSC2 (*(RwReg*)0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */\r
+#define REG_UOTGHS_HSTDMAADDRESS2 (*(RwReg*)0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */\r
+#define REG_UOTGHS_HSTDMACONTROL2 (*(RwReg*)0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */\r
+#define REG_UOTGHS_HSTDMASTATUS2 (*(RwReg*)0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */\r
+#define REG_UOTGHS_HSTDMANXTDSC3 (*(RwReg*)0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */\r
+#define REG_UOTGHS_HSTDMAADDRESS3 (*(RwReg*)0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */\r
+#define REG_UOTGHS_HSTDMACONTROL3 (*(RwReg*)0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */\r
+#define REG_UOTGHS_HSTDMASTATUS3 (*(RwReg*)0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */\r
+#define REG_UOTGHS_HSTDMANXTDSC4 (*(RwReg*)0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */\r
+#define REG_UOTGHS_HSTDMAADDRESS4 (*(RwReg*)0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */\r
+#define REG_UOTGHS_HSTDMACONTROL4 (*(RwReg*)0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */\r
+#define REG_UOTGHS_HSTDMASTATUS4 (*(RwReg*)0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */\r
+#define REG_UOTGHS_HSTDMANXTDSC5 (*(RwReg*)0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */\r
+#define REG_UOTGHS_HSTDMAADDRESS5 (*(RwReg*)0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */\r
+#define REG_UOTGHS_HSTDMACONTROL5 (*(RwReg*)0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */\r
+#define REG_UOTGHS_HSTDMASTATUS5 (*(RwReg*)0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */\r
+#define REG_UOTGHS_HSTDMANXTDSC6 (*(RwReg*)0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */\r
+#define REG_UOTGHS_HSTDMAADDRESS6 (*(RwReg*)0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */\r
+#define REG_UOTGHS_HSTDMACONTROL6 (*(RwReg*)0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */\r
+#define REG_UOTGHS_HSTDMASTATUS6 (*(RwReg*)0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */\r
+#define REG_UOTGHS_HSTDMANXTDSC7 (*(RwReg*)0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */\r
+#define REG_UOTGHS_HSTDMAADDRESS7 (*(RwReg*)0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */\r
+#define REG_UOTGHS_HSTDMACONTROL7 (*(RwReg*)0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */\r
+#define REG_UOTGHS_HSTDMASTATUS7 (*(RwReg*)0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */\r
+#define REG_UOTGHS_CTRL (*(RwReg*)0x400AC800U) /**< \brief (UOTGHS) General Control Register */\r
+#define REG_UOTGHS_SR (*(RoReg*)0x400AC804U) /**< \brief (UOTGHS) General Status Register */\r
+#define REG_UOTGHS_SCR (*(WoReg*)0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */\r
+#define REG_UOTGHS_SFR (*(WoReg*)0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */\r
+#define REG_UOTGHS_FSM (*(RoReg*)0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_UOTGHS_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_USART0_INSTANCE_\r
+#define _SAM3XA_USART0_INSTANCE_\r
+\r
+/* ========== Register definition for USART0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART0_CR (0x40098000U) /**< \brief (USART0) Control Register */\r
+#define REG_USART0_MR (0x40098004U) /**< \brief (USART0) Mode Register */\r
+#define REG_USART0_IER (0x40098008U) /**< \brief (USART0) Interrupt Enable Register */\r
+#define REG_USART0_IDR (0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */\r
+#define REG_USART0_IMR (0x40098010U) /**< \brief (USART0) Interrupt Mask Register */\r
+#define REG_USART0_CSR (0x40098014U) /**< \brief (USART0) Channel Status Register */\r
+#define REG_USART0_RHR (0x40098018U) /**< \brief (USART0) Receiver Holding Register */\r
+#define REG_USART0_THR (0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */\r
+#define REG_USART0_BRGR (0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+#define REG_USART0_RTOR (0x40098024U) /**< \brief (USART0) Receiver Time-out Register */\r
+#define REG_USART0_TTGR (0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+#define REG_USART0_FIDI (0x40098040U) /**< \brief (USART0) FI DI Ratio Register */\r
+#define REG_USART0_NER (0x40098044U) /**< \brief (USART0) Number of Errors Register */\r
+#define REG_USART0_IF (0x4009804CU) /**< \brief (USART0) IrDA Filter Register */\r
+#define REG_USART0_MAN (0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */\r
+#define REG_USART0_LINMR (0x40098054U) /**< \brief (USART0) LIN Mode Register */\r
+#define REG_USART0_LINIR (0x40098058U) /**< \brief (USART0) LIN Identifier Register */\r
+#define REG_USART0_WPMR (0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */\r
+#define REG_USART0_WPSR (0x400980E8U) /**< \brief (USART0) Write Protect Status Register */\r
+#define REG_USART0_RPR (0x40098100U) /**< \brief (USART0) Receive Pointer Register */\r
+#define REG_USART0_RCR (0x40098104U) /**< \brief (USART0) Receive Counter Register */\r
+#define REG_USART0_TPR (0x40098108U) /**< \brief (USART0) Transmit Pointer Register */\r
+#define REG_USART0_TCR (0x4009810CU) /**< \brief (USART0) Transmit Counter Register */\r
+#define REG_USART0_RNPR (0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */\r
+#define REG_USART0_RNCR (0x40098114U) /**< \brief (USART0) Receive Next Counter Register */\r
+#define REG_USART0_TNPR (0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */\r
+#define REG_USART0_TNCR (0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */\r
+#define REG_USART0_PTCR (0x40098120U) /**< \brief (USART0) Transfer Control Register */\r
+#define REG_USART0_PTSR (0x40098124U) /**< \brief (USART0) Transfer Status Register */\r
+#else\r
+#define REG_USART0_CR (*(WoReg*)0x40098000U) /**< \brief (USART0) Control Register */\r
+#define REG_USART0_MR (*(RwReg*)0x40098004U) /**< \brief (USART0) Mode Register */\r
+#define REG_USART0_IER (*(WoReg*)0x40098008U) /**< \brief (USART0) Interrupt Enable Register */\r
+#define REG_USART0_IDR (*(WoReg*)0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */\r
+#define REG_USART0_IMR (*(RoReg*)0x40098010U) /**< \brief (USART0) Interrupt Mask Register */\r
+#define REG_USART0_CSR (*(RoReg*)0x40098014U) /**< \brief (USART0) Channel Status Register */\r
+#define REG_USART0_RHR (*(RoReg*)0x40098018U) /**< \brief (USART0) Receiver Holding Register */\r
+#define REG_USART0_THR (*(WoReg*)0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */\r
+#define REG_USART0_BRGR (*(RwReg*)0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+#define REG_USART0_RTOR (*(RwReg*)0x40098024U) /**< \brief (USART0) Receiver Time-out Register */\r
+#define REG_USART0_TTGR (*(RwReg*)0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+#define REG_USART0_FIDI (*(RwReg*)0x40098040U) /**< \brief (USART0) FI DI Ratio Register */\r
+#define REG_USART0_NER (*(RoReg*)0x40098044U) /**< \brief (USART0) Number of Errors Register */\r
+#define REG_USART0_IF (*(RwReg*)0x4009804CU) /**< \brief (USART0) IrDA Filter Register */\r
+#define REG_USART0_MAN (*(RwReg*)0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */\r
+#define REG_USART0_LINMR (*(RwReg*)0x40098054U) /**< \brief (USART0) LIN Mode Register */\r
+#define REG_USART0_LINIR (*(RwReg*)0x40098058U) /**< \brief (USART0) LIN Identifier Register */\r
+#define REG_USART0_WPMR (*(RwReg*)0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */\r
+#define REG_USART0_WPSR (*(RoReg*)0x400980E8U) /**< \brief (USART0) Write Protect Status Register */\r
+#define REG_USART0_RPR (*(RwReg*)0x40098100U) /**< \brief (USART0) Receive Pointer Register */\r
+#define REG_USART0_RCR (*(RwReg*)0x40098104U) /**< \brief (USART0) Receive Counter Register */\r
+#define REG_USART0_TPR (*(RwReg*)0x40098108U) /**< \brief (USART0) Transmit Pointer Register */\r
+#define REG_USART0_TCR (*(RwReg*)0x4009810CU) /**< \brief (USART0) Transmit Counter Register */\r
+#define REG_USART0_RNPR (*(RwReg*)0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */\r
+#define REG_USART0_RNCR (*(RwReg*)0x40098114U) /**< \brief (USART0) Receive Next Counter Register */\r
+#define REG_USART0_TNPR (*(RwReg*)0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */\r
+#define REG_USART0_TNCR (*(RwReg*)0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */\r
+#define REG_USART0_PTCR (*(WoReg*)0x40098120U) /**< \brief (USART0) Transfer Control Register */\r
+#define REG_USART0_PTSR (*(RoReg*)0x40098124U) /**< \brief (USART0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_USART0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_USART1_INSTANCE_\r
+#define _SAM3XA_USART1_INSTANCE_\r
+\r
+/* ========== Register definition for USART1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART1_CR (0x4009C000U) /**< \brief (USART1) Control Register */\r
+#define REG_USART1_MR (0x4009C004U) /**< \brief (USART1) Mode Register */\r
+#define REG_USART1_IER (0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */\r
+#define REG_USART1_IDR (0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */\r
+#define REG_USART1_IMR (0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */\r
+#define REG_USART1_CSR (0x4009C014U) /**< \brief (USART1) Channel Status Register */\r
+#define REG_USART1_RHR (0x4009C018U) /**< \brief (USART1) Receiver Holding Register */\r
+#define REG_USART1_THR (0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */\r
+#define REG_USART1_BRGR (0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+#define REG_USART1_RTOR (0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */\r
+#define REG_USART1_TTGR (0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+#define REG_USART1_FIDI (0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */\r
+#define REG_USART1_NER (0x4009C044U) /**< \brief (USART1) Number of Errors Register */\r
+#define REG_USART1_IF (0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */\r
+#define REG_USART1_MAN (0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */\r
+#define REG_USART1_LINMR (0x4009C054U) /**< \brief (USART1) LIN Mode Register */\r
+#define REG_USART1_LINIR (0x4009C058U) /**< \brief (USART1) LIN Identifier Register */\r
+#define REG_USART1_WPMR (0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */\r
+#define REG_USART1_WPSR (0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */\r
+#define REG_USART1_RPR (0x4009C100U) /**< \brief (USART1) Receive Pointer Register */\r
+#define REG_USART1_RCR (0x4009C104U) /**< \brief (USART1) Receive Counter Register */\r
+#define REG_USART1_TPR (0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */\r
+#define REG_USART1_TCR (0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */\r
+#define REG_USART1_RNPR (0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */\r
+#define REG_USART1_RNCR (0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */\r
+#define REG_USART1_TNPR (0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */\r
+#define REG_USART1_TNCR (0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */\r
+#define REG_USART1_PTCR (0x4009C120U) /**< \brief (USART1) Transfer Control Register */\r
+#define REG_USART1_PTSR (0x4009C124U) /**< \brief (USART1) Transfer Status Register */\r
+#else\r
+#define REG_USART1_CR (*(WoReg*)0x4009C000U) /**< \brief (USART1) Control Register */\r
+#define REG_USART1_MR (*(RwReg*)0x4009C004U) /**< \brief (USART1) Mode Register */\r
+#define REG_USART1_IER (*(WoReg*)0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */\r
+#define REG_USART1_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */\r
+#define REG_USART1_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */\r
+#define REG_USART1_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART1) Channel Status Register */\r
+#define REG_USART1_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART1) Receiver Holding Register */\r
+#define REG_USART1_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */\r
+#define REG_USART1_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+#define REG_USART1_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */\r
+#define REG_USART1_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+#define REG_USART1_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */\r
+#define REG_USART1_NER (*(RoReg*)0x4009C044U) /**< \brief (USART1) Number of Errors Register */\r
+#define REG_USART1_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */\r
+#define REG_USART1_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */\r
+#define REG_USART1_LINMR (*(RwReg*)0x4009C054U) /**< \brief (USART1) LIN Mode Register */\r
+#define REG_USART1_LINIR (*(RwReg*)0x4009C058U) /**< \brief (USART1) LIN Identifier Register */\r
+#define REG_USART1_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */\r
+#define REG_USART1_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */\r
+#define REG_USART1_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART1) Receive Pointer Register */\r
+#define REG_USART1_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART1) Receive Counter Register */\r
+#define REG_USART1_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */\r
+#define REG_USART1_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */\r
+#define REG_USART1_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */\r
+#define REG_USART1_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */\r
+#define REG_USART1_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */\r
+#define REG_USART1_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */\r
+#define REG_USART1_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART1) Transfer Control Register */\r
+#define REG_USART1_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_USART1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_USART2_INSTANCE_\r
+#define _SAM3XA_USART2_INSTANCE_\r
+\r
+/* ========== Register definition for USART2 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART2_CR (0x400A0000U) /**< \brief (USART2) Control Register */\r
+#define REG_USART2_MR (0x400A0004U) /**< \brief (USART2) Mode Register */\r
+#define REG_USART2_IER (0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */\r
+#define REG_USART2_IDR (0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */\r
+#define REG_USART2_IMR (0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */\r
+#define REG_USART2_CSR (0x400A0014U) /**< \brief (USART2) Channel Status Register */\r
+#define REG_USART2_RHR (0x400A0018U) /**< \brief (USART2) Receiver Holding Register */\r
+#define REG_USART2_THR (0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */\r
+#define REG_USART2_BRGR (0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */\r
+#define REG_USART2_RTOR (0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */\r
+#define REG_USART2_TTGR (0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */\r
+#define REG_USART2_FIDI (0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */\r
+#define REG_USART2_NER (0x400A0044U) /**< \brief (USART2) Number of Errors Register */\r
+#define REG_USART2_IF (0x400A004CU) /**< \brief (USART2) IrDA Filter Register */\r
+#define REG_USART2_MAN (0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */\r
+#define REG_USART2_LINMR (0x400A0054U) /**< \brief (USART2) LIN Mode Register */\r
+#define REG_USART2_LINIR (0x400A0058U) /**< \brief (USART2) LIN Identifier Register */\r
+#define REG_USART2_WPMR (0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */\r
+#define REG_USART2_WPSR (0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */\r
+#define REG_USART2_RPR (0x400A0100U) /**< \brief (USART2) Receive Pointer Register */\r
+#define REG_USART2_RCR (0x400A0104U) /**< \brief (USART2) Receive Counter Register */\r
+#define REG_USART2_TPR (0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */\r
+#define REG_USART2_TCR (0x400A010CU) /**< \brief (USART2) Transmit Counter Register */\r
+#define REG_USART2_RNPR (0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */\r
+#define REG_USART2_RNCR (0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */\r
+#define REG_USART2_TNPR (0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */\r
+#define REG_USART2_TNCR (0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */\r
+#define REG_USART2_PTCR (0x400A0120U) /**< \brief (USART2) Transfer Control Register */\r
+#define REG_USART2_PTSR (0x400A0124U) /**< \brief (USART2) Transfer Status Register */\r
+#else\r
+#define REG_USART2_CR (*(WoReg*)0x400A0000U) /**< \brief (USART2) Control Register */\r
+#define REG_USART2_MR (*(RwReg*)0x400A0004U) /**< \brief (USART2) Mode Register */\r
+#define REG_USART2_IER (*(WoReg*)0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */\r
+#define REG_USART2_IDR (*(WoReg*)0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */\r
+#define REG_USART2_IMR (*(RoReg*)0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */\r
+#define REG_USART2_CSR (*(RoReg*)0x400A0014U) /**< \brief (USART2) Channel Status Register */\r
+#define REG_USART2_RHR (*(RoReg*)0x400A0018U) /**< \brief (USART2) Receiver Holding Register */\r
+#define REG_USART2_THR (*(WoReg*)0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */\r
+#define REG_USART2_BRGR (*(RwReg*)0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */\r
+#define REG_USART2_RTOR (*(RwReg*)0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */\r
+#define REG_USART2_TTGR (*(RwReg*)0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */\r
+#define REG_USART2_FIDI (*(RwReg*)0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */\r
+#define REG_USART2_NER (*(RoReg*)0x400A0044U) /**< \brief (USART2) Number of Errors Register */\r
+#define REG_USART2_IF (*(RwReg*)0x400A004CU) /**< \brief (USART2) IrDA Filter Register */\r
+#define REG_USART2_MAN (*(RwReg*)0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */\r
+#define REG_USART2_LINMR (*(RwReg*)0x400A0054U) /**< \brief (USART2) LIN Mode Register */\r
+#define REG_USART2_LINIR (*(RwReg*)0x400A0058U) /**< \brief (USART2) LIN Identifier Register */\r
+#define REG_USART2_WPMR (*(RwReg*)0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */\r
+#define REG_USART2_WPSR (*(RoReg*)0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */\r
+#define REG_USART2_RPR (*(RwReg*)0x400A0100U) /**< \brief (USART2) Receive Pointer Register */\r
+#define REG_USART2_RCR (*(RwReg*)0x400A0104U) /**< \brief (USART2) Receive Counter Register */\r
+#define REG_USART2_TPR (*(RwReg*)0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */\r
+#define REG_USART2_TCR (*(RwReg*)0x400A010CU) /**< \brief (USART2) Transmit Counter Register */\r
+#define REG_USART2_RNPR (*(RwReg*)0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */\r
+#define REG_USART2_RNCR (*(RwReg*)0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */\r
+#define REG_USART2_TNPR (*(RwReg*)0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */\r
+#define REG_USART2_TNCR (*(RwReg*)0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */\r
+#define REG_USART2_PTCR (*(WoReg*)0x400A0120U) /**< \brief (USART2) Transfer Control Register */\r
+#define REG_USART2_PTSR (*(RoReg*)0x400A0124U) /**< \brief (USART2) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_USART2_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_USART3_INSTANCE_\r
+#define _SAM3XA_USART3_INSTANCE_\r
+\r
+/* ========== Register definition for USART3 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART3_CR (0x400A4000U) /**< \brief (USART3) Control Register */\r
+#define REG_USART3_MR (0x400A4004U) /**< \brief (USART3) Mode Register */\r
+#define REG_USART3_IER (0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */\r
+#define REG_USART3_IDR (0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */\r
+#define REG_USART3_IMR (0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */\r
+#define REG_USART3_CSR (0x400A4014U) /**< \brief (USART3) Channel Status Register */\r
+#define REG_USART3_RHR (0x400A4018U) /**< \brief (USART3) Receiver Holding Register */\r
+#define REG_USART3_THR (0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */\r
+#define REG_USART3_BRGR (0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */\r
+#define REG_USART3_RTOR (0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */\r
+#define REG_USART3_TTGR (0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */\r
+#define REG_USART3_FIDI (0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */\r
+#define REG_USART3_NER (0x400A4044U) /**< \brief (USART3) Number of Errors Register */\r
+#define REG_USART3_IF (0x400A404CU) /**< \brief (USART3) IrDA Filter Register */\r
+#define REG_USART3_MAN (0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */\r
+#define REG_USART3_LINMR (0x400A4054U) /**< \brief (USART3) LIN Mode Register */\r
+#define REG_USART3_LINIR (0x400A4058U) /**< \brief (USART3) LIN Identifier Register */\r
+#define REG_USART3_WPMR (0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */\r
+#define REG_USART3_WPSR (0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */\r
+#define REG_USART3_RPR (0x400A4100U) /**< \brief (USART3) Receive Pointer Register */\r
+#define REG_USART3_RCR (0x400A4104U) /**< \brief (USART3) Receive Counter Register */\r
+#define REG_USART3_TPR (0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */\r
+#define REG_USART3_TCR (0x400A410CU) /**< \brief (USART3) Transmit Counter Register */\r
+#define REG_USART3_RNPR (0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */\r
+#define REG_USART3_RNCR (0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */\r
+#define REG_USART3_TNPR (0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */\r
+#define REG_USART3_TNCR (0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */\r
+#define REG_USART3_PTCR (0x400A4120U) /**< \brief (USART3) Transfer Control Register */\r
+#define REG_USART3_PTSR (0x400A4124U) /**< \brief (USART3) Transfer Status Register */\r
+#else\r
+#define REG_USART3_CR (*(WoReg*)0x400A4000U) /**< \brief (USART3) Control Register */\r
+#define REG_USART3_MR (*(RwReg*)0x400A4004U) /**< \brief (USART3) Mode Register */\r
+#define REG_USART3_IER (*(WoReg*)0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */\r
+#define REG_USART3_IDR (*(WoReg*)0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */\r
+#define REG_USART3_IMR (*(RoReg*)0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */\r
+#define REG_USART3_CSR (*(RoReg*)0x400A4014U) /**< \brief (USART3) Channel Status Register */\r
+#define REG_USART3_RHR (*(RoReg*)0x400A4018U) /**< \brief (USART3) Receiver Holding Register */\r
+#define REG_USART3_THR (*(WoReg*)0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */\r
+#define REG_USART3_BRGR (*(RwReg*)0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */\r
+#define REG_USART3_RTOR (*(RwReg*)0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */\r
+#define REG_USART3_TTGR (*(RwReg*)0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */\r
+#define REG_USART3_FIDI (*(RwReg*)0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */\r
+#define REG_USART3_NER (*(RoReg*)0x400A4044U) /**< \brief (USART3) Number of Errors Register */\r
+#define REG_USART3_IF (*(RwReg*)0x400A404CU) /**< \brief (USART3) IrDA Filter Register */\r
+#define REG_USART3_MAN (*(RwReg*)0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */\r
+#define REG_USART3_LINMR (*(RwReg*)0x400A4054U) /**< \brief (USART3) LIN Mode Register */\r
+#define REG_USART3_LINIR (*(RwReg*)0x400A4058U) /**< \brief (USART3) LIN Identifier Register */\r
+#define REG_USART3_WPMR (*(RwReg*)0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */\r
+#define REG_USART3_WPSR (*(RoReg*)0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */\r
+#define REG_USART3_RPR (*(RwReg*)0x400A4100U) /**< \brief (USART3) Receive Pointer Register */\r
+#define REG_USART3_RCR (*(RwReg*)0x400A4104U) /**< \brief (USART3) Receive Counter Register */\r
+#define REG_USART3_TPR (*(RwReg*)0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */\r
+#define REG_USART3_TCR (*(RwReg*)0x400A410CU) /**< \brief (USART3) Transmit Counter Register */\r
+#define REG_USART3_RNPR (*(RwReg*)0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */\r
+#define REG_USART3_RNCR (*(RwReg*)0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */\r
+#define REG_USART3_TNPR (*(RwReg*)0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */\r
+#define REG_USART3_TNCR (*(RwReg*)0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */\r
+#define REG_USART3_PTCR (*(WoReg*)0x400A4120U) /**< \brief (USART3) Transfer Control Register */\r
+#define REG_USART3_PTSR (*(RoReg*)0x400A4124U) /**< \brief (USART3) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_USART3_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_WDT_INSTANCE_\r
+#define _SAM3XA_WDT_INSTANCE_\r
+\r
+/* ========== Register definition for WDT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_WDT_CR (0x400E1A50U) /**< \brief (WDT) Control Register */\r
+#define REG_WDT_MR (0x400E1A54U) /**< \brief (WDT) Mode Register */\r
+#define REG_WDT_SR (0x400E1A58U) /**< \brief (WDT) Status Register */\r
+#else\r
+#define REG_WDT_CR (*(WoReg*)0x400E1A50U) /**< \brief (WDT) Control Register */\r
+#define REG_WDT_MR (*(RwReg*)0x400E1A54U) /**< \brief (WDT) Mode Register */\r
+#define REG_WDT_SR (*(RoReg*)0x400E1A58U) /**< \brief (WDT) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM3XA_WDT_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3A4C_PIO_\r
+#define _SAM3A4C_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */\r
+#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */\r
+#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */\r
+#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */\r
+#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */\r
+#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */\r
+#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */\r
+#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */\r
+#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */\r
+#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */\r
+#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */\r
+#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */\r
+#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */\r
+#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for CAN0 peripheral ========== */\r
+#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */\r
+#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */\r
+/* ========== Pio definition for CAN1 peripheral ========== */\r
+#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */\r
+#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */\r
+#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */\r
+#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */\r
+#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */\r
+#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */\r
+#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */\r
+#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */\r
+#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */\r
+#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */\r
+#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */\r
+#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */\r
+#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */\r
+#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */\r
+#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */\r
+#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */\r
+#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */\r
+#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART peripheral ========== */\r
+#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */\r
+#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */\r
+/* ========== Pio definition for UOTGHS peripheral ========== */\r
+#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */\r
+#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+\r
+#endif /* _SAM3A4C_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3A8C_PIO_\r
+#define _SAM3A8C_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */\r
+#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */\r
+#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */\r
+#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */\r
+#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */\r
+#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */\r
+#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */\r
+#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */\r
+#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */\r
+#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */\r
+#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */\r
+#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */\r
+#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */\r
+#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for CAN0 peripheral ========== */\r
+#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */\r
+#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */\r
+/* ========== Pio definition for CAN1 peripheral ========== */\r
+#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */\r
+#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */\r
+#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */\r
+#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */\r
+#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */\r
+#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */\r
+#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */\r
+#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */\r
+#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */\r
+#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */\r
+#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */\r
+#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */\r
+#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */\r
+#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */\r
+#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */\r
+#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */\r
+#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */\r
+#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART peripheral ========== */\r
+#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */\r
+#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */\r
+/* ========== Pio definition for UOTGHS peripheral ========== */\r
+#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */\r
+#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+\r
+#endif /* _SAM3A8C_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X4C_PIO_\r
+#define _SAM3X4C_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */\r
+#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */\r
+#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */\r
+#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */\r
+#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */\r
+#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */\r
+#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */\r
+#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */\r
+#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */\r
+#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */\r
+#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */\r
+#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */\r
+#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */\r
+#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for CAN0 peripheral ========== */\r
+#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */\r
+#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */\r
+/* ========== Pio definition for CAN1 peripheral ========== */\r
+#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */\r
+#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EMAC peripheral ========== */\r
+#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */\r
+#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */\r
+#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */\r
+#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */\r
+#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */\r
+#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */\r
+#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */\r
+#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */\r
+#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */\r
+#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */\r
+#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */\r
+#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */\r
+#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */\r
+#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */\r
+#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */\r
+#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */\r
+#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */\r
+#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */\r
+#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */\r
+#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */\r
+#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */\r
+#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */\r
+#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */\r
+#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */\r
+#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */\r
+#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */\r
+#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */\r
+#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */\r
+#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */\r
+#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */\r
+#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */\r
+#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */\r
+#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */\r
+#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */\r
+#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART peripheral ========== */\r
+#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */\r
+#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */\r
+/* ========== Pio definition for UOTGHS peripheral ========== */\r
+#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */\r
+#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+\r
+#endif /* _SAM3X4C_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X4E_PIO_\r
+#define _SAM3X4E_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */\r
+#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */\r
+#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */\r
+#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */\r
+#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */\r
+#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */\r
+#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */\r
+#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */\r
+#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */\r
+#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */\r
+#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */\r
+#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */\r
+#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */\r
+#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for CAN0 peripheral ========== */\r
+#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */\r
+#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */\r
+/* ========== Pio definition for CAN1 peripheral ========== */\r
+#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */\r
+#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */\r
+#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */\r
+#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */\r
+#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */\r
+#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */\r
+#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */\r
+#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */\r
+#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */\r
+#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */\r
+#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */\r
+#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */\r
+#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */\r
+#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */\r
+#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */\r
+#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */\r
+#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */\r
+#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */\r
+#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */\r
+#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */\r
+#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */\r
+#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */\r
+#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */\r
+#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */\r
+#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */\r
+#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */\r
+#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */\r
+#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */\r
+#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */\r
+#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */\r
+#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */\r
+#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */\r
+#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */\r
+#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */\r
+#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */\r
+#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */\r
+#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */\r
+#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */\r
+#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */\r
+#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */\r
+#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */\r
+#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */\r
+#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */\r
+#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */\r
+#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */\r
+#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */\r
+#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */\r
+/* ========== Pio definition for EMAC peripheral ========== */\r
+#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */\r
+#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */\r
+#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */\r
+#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */\r
+#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */\r
+#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */\r
+#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */\r
+#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */\r
+#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */\r
+#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */\r
+#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */\r
+#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */\r
+#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */\r
+#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */\r
+#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */\r
+#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */\r
+#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */\r
+#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */\r
+#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */\r
+#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */\r
+#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */\r
+#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */\r
+#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */\r
+#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */\r
+#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */\r
+#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */\r
+#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */\r
+#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */\r
+#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */\r
+#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */\r
+#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */\r
+#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */\r
+#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */\r
+#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */\r
+#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART peripheral ========== */\r
+#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */\r
+#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */\r
+/* ========== Pio definition for UOTGHS peripheral ========== */\r
+#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */\r
+#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio definition for USART3 peripheral ========== */\r
+#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */\r
+#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */\r
+#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */\r
+#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */\r
+#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD1_IDX 97\r
+#define PIO_PD2_IDX 98\r
+#define PIO_PD3_IDX 99\r
+#define PIO_PD4_IDX 100\r
+#define PIO_PD5_IDX 101\r
+#define PIO_PD6_IDX 102\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+\r
+#endif /* _SAM3X4E_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X8C_PIO_\r
+#define _SAM3X8C_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */\r
+#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */\r
+#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */\r
+#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */\r
+#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */\r
+#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */\r
+#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */\r
+#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */\r
+#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */\r
+#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */\r
+#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */\r
+#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */\r
+#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */\r
+#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for CAN0 peripheral ========== */\r
+#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */\r
+#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */\r
+/* ========== Pio definition for CAN1 peripheral ========== */\r
+#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */\r
+#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EMAC peripheral ========== */\r
+#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */\r
+#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */\r
+#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */\r
+#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */\r
+#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */\r
+#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */\r
+#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */\r
+#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */\r
+#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */\r
+#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */\r
+#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */\r
+#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */\r
+#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */\r
+#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */\r
+#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */\r
+#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */\r
+#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */\r
+#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */\r
+#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */\r
+#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */\r
+#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */\r
+#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */\r
+#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */\r
+#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */\r
+#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */\r
+#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */\r
+#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */\r
+#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */\r
+#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */\r
+#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */\r
+#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */\r
+#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */\r
+#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */\r
+#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */\r
+#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART peripheral ========== */\r
+#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */\r
+#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */\r
+/* ========== Pio definition for UOTGHS peripheral ========== */\r
+#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */\r
+#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+\r
+#endif /* _SAM3X8C_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X8E_PIO_\r
+#define _SAM3X8E_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */\r
+#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */\r
+#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */\r
+#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */\r
+#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */\r
+#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */\r
+#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */\r
+#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */\r
+#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */\r
+#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */\r
+#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */\r
+#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */\r
+#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */\r
+#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for CAN0 peripheral ========== */\r
+#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */\r
+#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */\r
+/* ========== Pio definition for CAN1 peripheral ========== */\r
+#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */\r
+#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */\r
+#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */\r
+#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */\r
+#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */\r
+#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */\r
+#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */\r
+#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */\r
+#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */\r
+#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */\r
+#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */\r
+#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */\r
+#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */\r
+#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */\r
+#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */\r
+#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */\r
+#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */\r
+#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */\r
+#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */\r
+#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */\r
+#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */\r
+#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */\r
+#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */\r
+#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */\r
+#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */\r
+#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */\r
+#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */\r
+#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */\r
+#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */\r
+#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */\r
+#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */\r
+#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */\r
+#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */\r
+#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */\r
+#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */\r
+#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */\r
+#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */\r
+#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */\r
+#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */\r
+#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */\r
+#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */\r
+#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */\r
+#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */\r
+#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */\r
+#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */\r
+#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */\r
+#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */\r
+/* ========== Pio definition for EMAC peripheral ========== */\r
+#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */\r
+#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */\r
+#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */\r
+#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */\r
+#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */\r
+#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */\r
+#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */\r
+#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */\r
+#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */\r
+#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */\r
+#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */\r
+#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */\r
+#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */\r
+#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */\r
+#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */\r
+#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */\r
+#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */\r
+#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */\r
+#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */\r
+#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */\r
+#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */\r
+#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */\r
+#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */\r
+#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */\r
+#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */\r
+#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */\r
+#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */\r
+#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */\r
+#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */\r
+#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */\r
+#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */\r
+#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */\r
+#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */\r
+#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */\r
+#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART peripheral ========== */\r
+#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */\r
+#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */\r
+/* ========== Pio definition for UOTGHS peripheral ========== */\r
+#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */\r
+#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio definition for USART3 peripheral ========== */\r
+#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */\r
+#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */\r
+#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */\r
+#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */\r
+#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD1_IDX 97\r
+#define PIO_PD2_IDX 98\r
+#define PIO_PD3_IDX 99\r
+#define PIO_PD4_IDX 100\r
+#define PIO_PD5_IDX 101\r
+#define PIO_PD6_IDX 102\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+\r
+#endif /* _SAM3X8E_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X8H_PIO_\r
+#define _SAM3X8H_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */\r
+#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */\r
+#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */\r
+#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */\r
+#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */\r
+#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */\r
+#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */\r
+#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */\r
+#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */\r
+#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */\r
+#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */\r
+#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */\r
+#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */\r
+#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */\r
+#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */\r
+#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */\r
+#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */\r
+#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */\r
+#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */\r
+#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */\r
+#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */\r
+#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */\r
+#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */\r
+#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */\r
+#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */\r
+#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */\r
+#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */\r
+#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */\r
+#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */\r
+#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */\r
+#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */\r
+#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */\r
+#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */\r
+#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */\r
+#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */\r
+#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */\r
+#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */\r
+#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */\r
+#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */\r
+#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */\r
+#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */\r
+#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */\r
+#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */\r
+#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */\r
+#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */\r
+#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */\r
+#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */\r
+#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */\r
+#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */\r
+#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */\r
+#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */\r
+#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */\r
+#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */\r
+#define PIO_PE6 (1u << 6) /**< \brief Pin Controlled by PE6 */\r
+#define PIO_PE7 (1u << 7) /**< \brief Pin Controlled by PE7 */\r
+#define PIO_PE8 (1u << 8) /**< \brief Pin Controlled by PE8 */\r
+#define PIO_PE9 (1u << 9) /**< \brief Pin Controlled by PE9 */\r
+#define PIO_PE10 (1u << 10) /**< \brief Pin Controlled by PE10 */\r
+#define PIO_PE11 (1u << 11) /**< \brief Pin Controlled by PE11 */\r
+#define PIO_PE12 (1u << 12) /**< \brief Pin Controlled by PE12 */\r
+#define PIO_PE13 (1u << 13) /**< \brief Pin Controlled by PE13 */\r
+#define PIO_PE14 (1u << 14) /**< \brief Pin Controlled by PE14 */\r
+#define PIO_PE15 (1u << 15) /**< \brief Pin Controlled by PE15 */\r
+#define PIO_PE16 (1u << 16) /**< \brief Pin Controlled by PE16 */\r
+#define PIO_PE17 (1u << 17) /**< \brief Pin Controlled by PE17 */\r
+#define PIO_PE18 (1u << 18) /**< \brief Pin Controlled by PE18 */\r
+#define PIO_PE19 (1u << 19) /**< \brief Pin Controlled by PE19 */\r
+#define PIO_PE20 (1u << 20) /**< \brief Pin Controlled by PE20 */\r
+#define PIO_PE21 (1u << 21) /**< \brief Pin Controlled by PE21 */\r
+#define PIO_PE22 (1u << 22) /**< \brief Pin Controlled by PE22 */\r
+#define PIO_PE23 (1u << 23) /**< \brief Pin Controlled by PE23 */\r
+#define PIO_PE24 (1u << 24) /**< \brief Pin Controlled by PE24 */\r
+#define PIO_PE25 (1u << 25) /**< \brief Pin Controlled by PE25 */\r
+#define PIO_PE26 (1u << 26) /**< \brief Pin Controlled by PE26 */\r
+#define PIO_PE27 (1u << 27) /**< \brief Pin Controlled by PE27 */\r
+#define PIO_PE28 (1u << 28) /**< \brief Pin Controlled by PE28 */\r
+#define PIO_PE29 (1u << 29) /**< \brief Pin Controlled by PE29 */\r
+#define PIO_PE30 (1u << 30) /**< \brief Pin Controlled by PE30 */\r
+#define PIO_PE31 (1u << 31) /**< \brief Pin Controlled by PE31 */\r
+#define PIO_PF0 (1u << 0) /**< \brief Pin Controlled by PF0 */\r
+#define PIO_PF1 (1u << 1) /**< \brief Pin Controlled by PF1 */\r
+#define PIO_PF2 (1u << 2) /**< \brief Pin Controlled by PF2 */\r
+#define PIO_PF3 (1u << 3) /**< \brief Pin Controlled by PF3 */\r
+#define PIO_PF4 (1u << 4) /**< \brief Pin Controlled by PF4 */\r
+#define PIO_PF5 (1u << 5) /**< \brief Pin Controlled by PF5 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */\r
+#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */\r
+#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */\r
+#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */\r
+#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */\r
+#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */\r
+#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */\r
+#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */\r
+#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */\r
+#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */\r
+#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */\r
+#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */\r
+#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */\r
+#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */\r
+#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */\r
+#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for CAN0 peripheral ========== */\r
+#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */\r
+#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */\r
+/* ========== Pio definition for CAN1 peripheral ========== */\r
+#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */\r
+#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */\r
+#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */\r
+#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */\r
+#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */\r
+#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */\r
+#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */\r
+#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */\r
+#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */\r
+#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */\r
+#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */\r
+#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */\r
+#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */\r
+#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */\r
+#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */\r
+#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */\r
+#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */\r
+#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */\r
+#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */\r
+#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */\r
+#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */\r
+#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */\r
+#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */\r
+#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */\r
+#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */\r
+#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */\r
+#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */\r
+#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */\r
+#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */\r
+#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */\r
+#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */\r
+#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */\r
+#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */\r
+#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */\r
+#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */\r
+#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */\r
+#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */\r
+#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */\r
+#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */\r
+#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */\r
+#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */\r
+#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */\r
+#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */\r
+#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */\r
+#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */\r
+#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */\r
+#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */\r
+#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */\r
+#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */\r
+#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */\r
+#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */\r
+#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */\r
+#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */\r
+#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */\r
+#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */\r
+/* ========== Pio definition for EMAC peripheral ========== */\r
+#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */\r
+#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */\r
+#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */\r
+#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */\r
+#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */\r
+#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */\r
+#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */\r
+#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */\r
+#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */\r
+#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */\r
+#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */\r
+#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */\r
+#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */\r
+#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */\r
+#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */\r
+#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */\r
+#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */\r
+#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */\r
+#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */\r
+#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */\r
+#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */\r
+#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */\r
+#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */\r
+#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */\r
+#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */\r
+#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */\r
+#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */\r
+#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */\r
+#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */\r
+#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */\r
+#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */\r
+#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */\r
+#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */\r
+#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */\r
+#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */\r
+#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */\r
+#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */\r
+#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */\r
+/* ========== Pio definition for SPI0 peripheral ========== */\r
+#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */\r
+#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */\r
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */\r
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */\r
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */\r
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */\r
+#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */\r
+/* ========== Pio definition for SPI1 peripheral ========== */\r
+#define PIO_PE28A_SPI1_MISO (1u << 28) /**< \brief Spi1 signal: SPI1_MISO */\r
+#define PIO_PE29A_SPI1_MOSI (1u << 29) /**< \brief Spi1 signal: SPI1_MOSI */\r
+#define PIO_PE31A_SPI1_NPCS0 (1u << 31) /**< \brief Spi1 signal: SPI1_NPCS0 */\r
+#define PIO_PF0A_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */\r
+#define PIO_PF1A_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */\r
+#define PIO_PF2A_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */\r
+#define PIO_PE30A_SPI1_SPCK (1u << 30) /**< \brief Spi1 signal: SPI1_SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */\r
+#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */\r
+#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */\r
+#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */\r
+#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */\r
+#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */\r
+#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TC2 peripheral ========== */\r
+#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */\r
+#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */\r
+#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */\r
+#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */\r
+#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */\r
+#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */\r
+#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */\r
+#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */\r
+#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART peripheral ========== */\r
+#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */\r
+#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */\r
+/* ========== Pio definition for UOTGHS peripheral ========== */\r
+#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */\r
+#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio definition for USART2 peripheral ========== */\r
+#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */\r
+#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */\r
+#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */\r
+#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */\r
+#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */\r
+/* ========== Pio definition for USART3 peripheral ========== */\r
+#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */\r
+#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */\r
+#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */\r
+#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */\r
+#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PB15_IDX 47\r
+#define PIO_PB16_IDX 48\r
+#define PIO_PB17_IDX 49\r
+#define PIO_PB18_IDX 50\r
+#define PIO_PB19_IDX 51\r
+#define PIO_PB20_IDX 52\r
+#define PIO_PB21_IDX 53\r
+#define PIO_PB22_IDX 54\r
+#define PIO_PB23_IDX 55\r
+#define PIO_PB24_IDX 56\r
+#define PIO_PB25_IDX 57\r
+#define PIO_PB26_IDX 58\r
+#define PIO_PB27_IDX 59\r
+#define PIO_PB28_IDX 60\r
+#define PIO_PB29_IDX 61\r
+#define PIO_PB30_IDX 62\r
+#define PIO_PB31_IDX 63\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PD0_IDX 96\r
+#define PIO_PD1_IDX 97\r
+#define PIO_PD2_IDX 98\r
+#define PIO_PD3_IDX 99\r
+#define PIO_PD4_IDX 100\r
+#define PIO_PD5_IDX 101\r
+#define PIO_PD6_IDX 102\r
+#define PIO_PD7_IDX 103\r
+#define PIO_PD8_IDX 104\r
+#define PIO_PD9_IDX 105\r
+#define PIO_PD10_IDX 106\r
+#define PIO_PD11_IDX 107\r
+#define PIO_PD12_IDX 108\r
+#define PIO_PD13_IDX 109\r
+#define PIO_PD14_IDX 110\r
+#define PIO_PD15_IDX 111\r
+#define PIO_PD16_IDX 112\r
+#define PIO_PD17_IDX 113\r
+#define PIO_PD18_IDX 114\r
+#define PIO_PD19_IDX 115\r
+#define PIO_PD20_IDX 116\r
+#define PIO_PD21_IDX 117\r
+#define PIO_PD22_IDX 118\r
+#define PIO_PD23_IDX 119\r
+#define PIO_PD24_IDX 120\r
+#define PIO_PD25_IDX 121\r
+#define PIO_PD26_IDX 122\r
+#define PIO_PD27_IDX 123\r
+#define PIO_PD28_IDX 124\r
+#define PIO_PD29_IDX 125\r
+#define PIO_PD30_IDX 126\r
+#define PIO_PE0_IDX 128\r
+#define PIO_PE1_IDX 129\r
+#define PIO_PE2_IDX 130\r
+#define PIO_PE3_IDX 131\r
+#define PIO_PE4_IDX 132\r
+#define PIO_PE5_IDX 133\r
+#define PIO_PE6_IDX 134\r
+#define PIO_PE7_IDX 135\r
+#define PIO_PE8_IDX 136\r
+#define PIO_PE9_IDX 137\r
+#define PIO_PE10_IDX 138\r
+#define PIO_PE11_IDX 139\r
+#define PIO_PE12_IDX 140\r
+#define PIO_PE13_IDX 141\r
+#define PIO_PE14_IDX 142\r
+#define PIO_PE15_IDX 143\r
+#define PIO_PE16_IDX 144\r
+#define PIO_PE17_IDX 145\r
+#define PIO_PE18_IDX 146\r
+#define PIO_PE19_IDX 147\r
+#define PIO_PE20_IDX 148\r
+#define PIO_PE21_IDX 149\r
+#define PIO_PE22_IDX 150\r
+#define PIO_PE23_IDX 151\r
+#define PIO_PE24_IDX 152\r
+#define PIO_PE25_IDX 153\r
+#define PIO_PE26_IDX 154\r
+#define PIO_PE27_IDX 155\r
+#define PIO_PE28_IDX 156\r
+#define PIO_PE29_IDX 157\r
+#define PIO_PE30_IDX 158\r
+#define PIO_PE31_IDX 159\r
+#define PIO_PF0_IDX 160\r
+#define PIO_PF1_IDX 161\r
+#define PIO_PF2_IDX 162\r
+#define PIO_PF3_IDX 163\r
+#define PIO_PF4_IDX 164\r
+#define PIO_PF5_IDX 165\r
+\r
+#endif /* _SAM3X8H_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3A4C_\r
+#define _SAM3A4C_\r
+\r
+/** \addtogroup SAM3A4C_definitions SAM3A4C definitions\r
+ This file defines all structures and symbols for SAM3A4C:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM3A4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A4C_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */\r
+/****** SAM3A4C specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM3A4C Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM3A4C Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM3A4C Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM3A4C Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM3A4C Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM3A4C Power Management Controller (PMC) */\r
+ EFC0_IRQn = 6, /**< 6 SAM3A4C Enhanced Flash Controller 0 (EFC0) */\r
+ EFC1_IRQn = 7, /**< 7 SAM3A4C Enhanced Flash Controller 1 (EFC1) */\r
+ UART_IRQn = 8, /**< 8 SAM3A4C Universal Asynchronous Receiver Transceiver (UART) */\r
+ PIOA_IRQn = 11, /**< 11 SAM3A4C Parallel I/O Controller A, (PIOA) */\r
+ PIOB_IRQn = 12, /**< 12 SAM3A4C Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 17, /**< 17 SAM3A4C USART 0 (USART0) */\r
+ USART1_IRQn = 18, /**< 18 SAM3A4C USART 1 (USART1) */\r
+ USART2_IRQn = 19, /**< 19 SAM3A4C USART 2 (USART2) */\r
+ HSMCI_IRQn = 21, /**< 21 SAM3A4C Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 22, /**< 22 SAM3A4C Two-Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 23, /**< 23 SAM3A4C Two-Wire Interface 1 (TWI1) */\r
+ SPI0_IRQn = 24, /**< 24 SAM3A4C Serial Peripheral Interface (SPI0) */\r
+ SSC_IRQn = 26, /**< 26 SAM3A4C Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 27, /**< 27 SAM3A4C Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 28, /**< 28 SAM3A4C Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 29, /**< 29 SAM3A4C Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 30, /**< 30 SAM3A4C Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 31, /**< 31 SAM3A4C Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 32, /**< 32 SAM3A4C Timer Counter 5 (TC5) */\r
+ PWM_IRQn = 36, /**< 36 SAM3A4C Pulse Width Modulation Controller (PWM) */\r
+ ADC_IRQn = 37, /**< 37 SAM3A4C ADC Controller (ADC) */\r
+ DACC_IRQn = 38, /**< 38 SAM3A4C DAC Controller (DACC) */\r
+ DMAC_IRQn = 39, /**< 39 SAM3A4C DMA Controller (DMAC) */\r
+ UOTGHS_IRQn = 40, /**< 40 SAM3A4C USB OTG High Speed (UOTGHS) */\r
+ TRNG_IRQn = 41, /**< 41 SAM3A4C True Random Number Generator (TRNG) */\r
+ CAN0_IRQn = 43, /**< 43 SAM3A4C CAN Controller 0 (CAN0) */\r
+ CAN1_IRQn = 44 /**< 44 SAM3A4C CAN Controller 1 (CAN1) */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */\r
+ void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */\r
+ void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */\r
+ void* pvReserved9;\r
+ void* pvReserved10;\r
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */\r
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */\r
+ void* pvReserved13;\r
+ void* pvReserved14;\r
+ void* pvReserved15;\r
+ void* pvReserved16;\r
+ void* pfnUSART0_Handler; /* 17 USART 0 */\r
+ void* pfnUSART1_Handler; /* 18 USART 1 */\r
+ void* pfnUSART2_Handler; /* 19 USART 2 */\r
+ void* pvReserved20;\r
+ void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */\r
+ void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */\r
+ void* pvReserved25;\r
+ void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 27 Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 28 Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 29 Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 30 Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 31 Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 32 Timer Counter 5 */\r
+ void* pvReserved33;\r
+ void* pvReserved34;\r
+ void* pvReserved35;\r
+ void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */\r
+ void* pfnADC_Handler; /* 37 ADC Controller */\r
+ void* pfnDACC_Handler; /* 38 DAC Controller */\r
+ void* pfnDMAC_Handler; /* 39 DMA Controller */\r
+ void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */\r
+ void* pfnTRNG_Handler; /* 41 True Random Number Generator */\r
+ void* pvReserved42;\r
+ void* pfnCAN0_Handler; /* 43 CAN Controller 0 */\r
+ void* pfnCAN1_Handler; /* 44 CAN Controller 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M3 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ADC_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC0_Handler ( void );\r
+void EFC1_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART_Handler ( void );\r
+void UOTGHS_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM3_REV 0x0200 /**< SAM3A4C core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAM3A4C does provide a MPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM3A4C uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm3.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam3x.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3A4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A4C_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_adc.h"\r
+#include "component/component_can.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_dmac.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pdc.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM3A4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A4C_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_uotghs.h"\r
+#include "instance/instance_can0.h"\r
+#include "instance/instance_can1.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dmac.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_efc0.h"\r
+#include "instance/instance_efc1.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM3A4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A4C_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */\r
+#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */\r
+#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */\r
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */\r
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */\r
+#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */\r
+#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */\r
+#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */\r
+#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */\r
+#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */\r
+#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */\r
+#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */\r
+#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */\r
+#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */\r
+#define ID_ADC (37) /**< \brief ADC Controller (ADC) */\r
+#define ID_DACC (38) /**< \brief DAC Controller (DACC) */\r
+#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */\r
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */\r
+#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */\r
+#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */\r
+#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM3A4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A4C_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART (0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM3A4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A4C_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sam3a4c.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM3A4C */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH0_SIZE (0x20000u)\r
+#define IFLASH0_PAGE_SIZE (256u)\r
+#define IFLASH0_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH0_NB_OF_PAGES (512u)\r
+#define IFLASH1_SIZE (0x20000u)\r
+#define IFLASH1_PAGE_SIZE (256u)\r
+#define IFLASH1_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH1_NB_OF_PAGES (512u)\r
+#define IRAM0_SIZE (0x8000u)\r
+#define IRAM1_SIZE (0x8000u)\r
+#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)\r
+#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)\r
+\r
+#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */\r
+#if defined IFLASH0_SIZE\r
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */\r
+#endif\r
+#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */\r
+#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */\r
+#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */\r
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */\r
+#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */\r
+#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */\r
+#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM3A4C */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (84000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */\r
+#define CHIP_FREQ_FWS_0 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM3A4C_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3A8C_\r
+#define _SAM3A8C_\r
+\r
+/** \addtogroup SAM3A8C_definitions SAM3A8C definitions\r
+ This file defines all structures and symbols for SAM3A8C:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM3A8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A8C_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */\r
+/****** SAM3A8C specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM3A8C Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM3A8C Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM3A8C Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM3A8C Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM3A8C Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM3A8C Power Management Controller (PMC) */\r
+ EFC0_IRQn = 6, /**< 6 SAM3A8C Enhanced Flash Controller 0 (EFC0) */\r
+ EFC1_IRQn = 7, /**< 7 SAM3A8C Enhanced Flash Controller 1 (EFC1) */\r
+ UART_IRQn = 8, /**< 8 SAM3A8C Universal Asynchronous Receiver Transceiver (UART) */\r
+ PIOA_IRQn = 11, /**< 11 SAM3A8C Parallel I/O Controller A, (PIOA) */\r
+ PIOB_IRQn = 12, /**< 12 SAM3A8C Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 17, /**< 17 SAM3A8C USART 0 (USART0) */\r
+ USART1_IRQn = 18, /**< 18 SAM3A8C USART 1 (USART1) */\r
+ USART2_IRQn = 19, /**< 19 SAM3A8C USART 2 (USART2) */\r
+ HSMCI_IRQn = 21, /**< 21 SAM3A8C Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 22, /**< 22 SAM3A8C Two-Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 23, /**< 23 SAM3A8C Two-Wire Interface 1 (TWI1) */\r
+ SPI0_IRQn = 24, /**< 24 SAM3A8C Serial Peripheral Interface (SPI0) */\r
+ SSC_IRQn = 26, /**< 26 SAM3A8C Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 27, /**< 27 SAM3A8C Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 28, /**< 28 SAM3A8C Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 29, /**< 29 SAM3A8C Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 30, /**< 30 SAM3A8C Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 31, /**< 31 SAM3A8C Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 32, /**< 32 SAM3A8C Timer Counter 5 (TC5) */\r
+ PWM_IRQn = 36, /**< 36 SAM3A8C Pulse Width Modulation Controller (PWM) */\r
+ ADC_IRQn = 37, /**< 37 SAM3A8C ADC Controller (ADC) */\r
+ DACC_IRQn = 38, /**< 38 SAM3A8C DAC Controller (DACC) */\r
+ DMAC_IRQn = 39, /**< 39 SAM3A8C DMA Controller (DMAC) */\r
+ UOTGHS_IRQn = 40, /**< 40 SAM3A8C USB OTG High Speed (UOTGHS) */\r
+ TRNG_IRQn = 41, /**< 41 SAM3A8C True Random Number Generator (TRNG) */\r
+ CAN0_IRQn = 43, /**< 43 SAM3A8C CAN Controller 0 (CAN0) */\r
+ CAN1_IRQn = 44 /**< 44 SAM3A8C CAN Controller 1 (CAN1) */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */\r
+ void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */\r
+ void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */\r
+ void* pvReserved9;\r
+ void* pvReserved10;\r
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */\r
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */\r
+ void* pvReserved13;\r
+ void* pvReserved14;\r
+ void* pvReserved15;\r
+ void* pvReserved16;\r
+ void* pfnUSART0_Handler; /* 17 USART 0 */\r
+ void* pfnUSART1_Handler; /* 18 USART 1 */\r
+ void* pfnUSART2_Handler; /* 19 USART 2 */\r
+ void* pvReserved20;\r
+ void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */\r
+ void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */\r
+ void* pvReserved25;\r
+ void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 27 Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 28 Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 29 Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 30 Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 31 Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 32 Timer Counter 5 */\r
+ void* pvReserved33;\r
+ void* pvReserved34;\r
+ void* pvReserved35;\r
+ void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */\r
+ void* pfnADC_Handler; /* 37 ADC Controller */\r
+ void* pfnDACC_Handler; /* 38 DAC Controller */\r
+ void* pfnDMAC_Handler; /* 39 DMA Controller */\r
+ void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */\r
+ void* pfnTRNG_Handler; /* 41 True Random Number Generator */\r
+ void* pvReserved42;\r
+ void* pfnCAN0_Handler; /* 43 CAN Controller 0 */\r
+ void* pfnCAN1_Handler; /* 44 CAN Controller 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M3 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ADC_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC0_Handler ( void );\r
+void EFC1_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART_Handler ( void );\r
+void UOTGHS_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM3_REV 0x0200 /**< SAM3A8C core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAM3A8C does provide a MPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM3A8C uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm3.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam3x.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3A8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A8C_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_adc.h"\r
+#include "component/component_can.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_dmac.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pdc.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM3A8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A8C_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_uotghs.h"\r
+#include "instance/instance_can0.h"\r
+#include "instance/instance_can1.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dmac.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_efc0.h"\r
+#include "instance/instance_efc1.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM3A8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A8C_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */\r
+#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */\r
+#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */\r
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */\r
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */\r
+#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */\r
+#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */\r
+#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */\r
+#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */\r
+#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */\r
+#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */\r
+#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */\r
+#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */\r
+#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */\r
+#define ID_ADC (37) /**< \brief ADC Controller (ADC) */\r
+#define ID_DACC (38) /**< \brief DAC Controller (DACC) */\r
+#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */\r
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */\r
+#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */\r
+#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */\r
+#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM3A8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A8C_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART (0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM3A8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3A8C_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sam3a8c.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM3A8C */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH0_SIZE (0x40000u)\r
+#define IFLASH0_PAGE_SIZE (256u)\r
+#define IFLASH0_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH0_NB_OF_PAGES (1024u)\r
+#define IFLASH1_SIZE (0x40000u)\r
+#define IFLASH1_PAGE_SIZE (256u)\r
+#define IFLASH1_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH1_NB_OF_PAGES (1024u)\r
+#define IRAM0_SIZE (0x10000u)\r
+#define IRAM1_SIZE (0x8000u)\r
+#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)\r
+#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)\r
+\r
+#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */\r
+#if defined IFLASH0_SIZE\r
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */\r
+#endif\r
+#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */\r
+#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */\r
+#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */\r
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */\r
+#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */\r
+#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */\r
+#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM3A8C */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (84000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */\r
+#define CHIP_FREQ_FWS_0 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM3A8C_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X4C_\r
+#define _SAM3X4C_\r
+\r
+/** \addtogroup SAM3X4C_definitions SAM3X4C definitions\r
+ This file defines all structures and symbols for SAM3X4C:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM3X4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4C_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */\r
+/****** SAM3X4C specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM3X4C Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM3X4C Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM3X4C Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM3X4C Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM3X4C Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM3X4C Power Management Controller (PMC) */\r
+ EFC0_IRQn = 6, /**< 6 SAM3X4C Enhanced Flash Controller 0 (EFC0) */\r
+ EFC1_IRQn = 7, /**< 7 SAM3X4C Enhanced Flash Controller 1 (EFC1) */\r
+ UART_IRQn = 8, /**< 8 SAM3X4C Universal Asynchronous Receiver Transceiver (UART) */\r
+ PIOA_IRQn = 11, /**< 11 SAM3X4C Parallel I/O Controller A, (PIOA) */\r
+ PIOB_IRQn = 12, /**< 12 SAM3X4C Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 17, /**< 17 SAM3X4C USART 0 (USART0) */\r
+ USART1_IRQn = 18, /**< 18 SAM3X4C USART 1 (USART1) */\r
+ USART2_IRQn = 19, /**< 19 SAM3X4C USART 2 (USART2) */\r
+ HSMCI_IRQn = 21, /**< 21 SAM3X4C Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 22, /**< 22 SAM3X4C Two-Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 23, /**< 23 SAM3X4C Two-Wire Interface 1 (TWI1) */\r
+ SPI0_IRQn = 24, /**< 24 SAM3X4C Serial Peripheral Interface (SPI0) */\r
+ SSC_IRQn = 26, /**< 26 SAM3X4C Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 27, /**< 27 SAM3X4C Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 28, /**< 28 SAM3X4C Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 29, /**< 29 SAM3X4C Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 30, /**< 30 SAM3X4C Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 31, /**< 31 SAM3X4C Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 32, /**< 32 SAM3X4C Timer Counter 5 (TC5) */\r
+ PWM_IRQn = 36, /**< 36 SAM3X4C Pulse Width Modulation Controller (PWM) */\r
+ ADC_IRQn = 37, /**< 37 SAM3X4C ADC Controller (ADC) */\r
+ DACC_IRQn = 38, /**< 38 SAM3X4C DAC Controller (DACC) */\r
+ DMAC_IRQn = 39, /**< 39 SAM3X4C DMA Controller (DMAC) */\r
+ UOTGHS_IRQn = 40, /**< 40 SAM3X4C USB OTG High Speed (UOTGHS) */\r
+ TRNG_IRQn = 41, /**< 41 SAM3X4C True Random Number Generator (TRNG) */\r
+ EMAC_IRQn = 42, /**< 42 SAM3X4C Ethernet MAC (EMAC) */\r
+ CAN0_IRQn = 43, /**< 43 SAM3X4C CAN Controller 0 (CAN0) */\r
+ CAN1_IRQn = 44 /**< 44 SAM3X4C CAN Controller 1 (CAN1) */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */\r
+ void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */\r
+ void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */\r
+ void* pvReserved9;\r
+ void* pvReserved10;\r
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */\r
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */\r
+ void* pvReserved13;\r
+ void* pvReserved14;\r
+ void* pvReserved15;\r
+ void* pvReserved16;\r
+ void* pfnUSART0_Handler; /* 17 USART 0 */\r
+ void* pfnUSART1_Handler; /* 18 USART 1 */\r
+ void* pfnUSART2_Handler; /* 19 USART 2 */\r
+ void* pvReserved20;\r
+ void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */\r
+ void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */\r
+ void* pvReserved25;\r
+ void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 27 Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 28 Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 29 Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 30 Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 31 Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 32 Timer Counter 5 */\r
+ void* pvReserved33;\r
+ void* pvReserved34;\r
+ void* pvReserved35;\r
+ void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */\r
+ void* pfnADC_Handler; /* 37 ADC Controller */\r
+ void* pfnDACC_Handler; /* 38 DAC Controller */\r
+ void* pfnDMAC_Handler; /* 39 DMA Controller */\r
+ void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */\r
+ void* pfnTRNG_Handler; /* 41 True Random Number Generator */\r
+ void* pfnEMAC_Handler; /* 42 Ethernet MAC */\r
+ void* pfnCAN0_Handler; /* 43 CAN Controller 0 */\r
+ void* pfnCAN1_Handler; /* 44 CAN Controller 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M3 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ADC_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC0_Handler ( void );\r
+void EFC1_Handler ( void );\r
+void EMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART_Handler ( void );\r
+void UOTGHS_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM3_REV 0x0200 /**< SAM3X4C core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAM3X4C does provide a MPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM3X4C uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm3.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam3x.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4C_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_adc.h"\r
+#include "component/component_can.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_dmac.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_emac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pdc.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM3X4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4C_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_uotghs.h"\r
+#include "instance/instance_emac.h"\r
+#include "instance/instance_can0.h"\r
+#include "instance/instance_can1.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dmac.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_efc0.h"\r
+#include "instance/instance_efc1.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM3X4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4C_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */\r
+#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */\r
+#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */\r
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */\r
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */\r
+#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */\r
+#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */\r
+#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */\r
+#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */\r
+#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */\r
+#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */\r
+#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */\r
+#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */\r
+#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */\r
+#define ID_ADC (37) /**< \brief ADC Controller (ADC) */\r
+#define ID_DACC (38) /**< \brief DAC Controller (DACC) */\r
+#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */\r
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */\r
+#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */\r
+#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */\r
+#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */\r
+#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM3X4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4C_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART (0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM3X4C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4C_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sam3x4c.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM3X4C */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH0_SIZE (0x20000u)\r
+#define IFLASH0_PAGE_SIZE (256u)\r
+#define IFLASH0_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH0_NB_OF_PAGES (512u)\r
+#define IFLASH1_SIZE (0x20000u)\r
+#define IFLASH1_PAGE_SIZE (256u)\r
+#define IFLASH1_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH1_NB_OF_PAGES (512u)\r
+#define IRAM0_SIZE (0x8000u)\r
+#define IRAM1_SIZE (0x8000u)\r
+#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)\r
+#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)\r
+\r
+#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */\r
+#if defined IFLASH0_SIZE\r
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */\r
+#endif\r
+#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */\r
+#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */\r
+#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */\r
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */\r
+#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */\r
+#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */\r
+#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM3X4C */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (84000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */\r
+#define CHIP_FREQ_FWS_0 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM3X4C_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X4E_\r
+#define _SAM3X4E_\r
+\r
+/** \addtogroup SAM3X4E_definitions SAM3X4E definitions\r
+ This file defines all structures and symbols for SAM3X4E:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */\r
+/****** SAM3X4E specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM3X4E Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM3X4E Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM3X4E Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM3X4E Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM3X4E Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM3X4E Power Management Controller (PMC) */\r
+ EFC0_IRQn = 6, /**< 6 SAM3X4E Enhanced Flash Controller 0 (EFC0) */\r
+ EFC1_IRQn = 7, /**< 7 SAM3X4E Enhanced Flash Controller 1 (EFC1) */\r
+ UART_IRQn = 8, /**< 8 SAM3X4E Universal Asynchronous Receiver Transceiver (UART) */\r
+ SMC_IRQn = 9, /**< 9 SAM3X4E Static Memory Controller (SMC) */\r
+ PIOA_IRQn = 11, /**< 11 SAM3X4E Parallel I/O Controller A, (PIOA) */\r
+ PIOB_IRQn = 12, /**< 12 SAM3X4E Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 13, /**< 13 SAM3X4E Parallel I/O Controller C (PIOC) */\r
+ PIOD_IRQn = 14, /**< 14 SAM3X4E Parallel I/O Controller D (PIOD) */\r
+ USART0_IRQn = 17, /**< 17 SAM3X4E USART 0 (USART0) */\r
+ USART1_IRQn = 18, /**< 18 SAM3X4E USART 1 (USART1) */\r
+ USART2_IRQn = 19, /**< 19 SAM3X4E USART 2 (USART2) */\r
+ USART3_IRQn = 20, /**< 20 SAM3X4E USART 3 (USART3) */\r
+ HSMCI_IRQn = 21, /**< 21 SAM3X4E Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 22, /**< 22 SAM3X4E Two-Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 23, /**< 23 SAM3X4E Two-Wire Interface 1 (TWI1) */\r
+ SPI0_IRQn = 24, /**< 24 SAM3X4E Serial Peripheral Interface (SPI0) */\r
+ SSC_IRQn = 26, /**< 26 SAM3X4E Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 27, /**< 27 SAM3X4E Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 28, /**< 28 SAM3X4E Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 29, /**< 29 SAM3X4E Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 30, /**< 30 SAM3X4E Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 31, /**< 31 SAM3X4E Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 32, /**< 32 SAM3X4E Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 33, /**< 33 SAM3X4E Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 34, /**< 34 SAM3X4E Timer Counter 7 (TC7) */\r
+ TC8_IRQn = 35, /**< 35 SAM3X4E Timer Counter 8 (TC8) */\r
+ PWM_IRQn = 36, /**< 36 SAM3X4E Pulse Width Modulation Controller (PWM) */\r
+ ADC_IRQn = 37, /**< 37 SAM3X4E ADC Controller (ADC) */\r
+ DACC_IRQn = 38, /**< 38 SAM3X4E DAC Controller (DACC) */\r
+ DMAC_IRQn = 39, /**< 39 SAM3X4E DMA Controller (DMAC) */\r
+ UOTGHS_IRQn = 40, /**< 40 SAM3X4E USB OTG High Speed (UOTGHS) */\r
+ TRNG_IRQn = 41, /**< 41 SAM3X4E True Random Number Generator (TRNG) */\r
+ EMAC_IRQn = 42, /**< 42 SAM3X4E Ethernet MAC (EMAC) */\r
+ CAN0_IRQn = 43, /**< 43 SAM3X4E CAN Controller 0 (CAN0) */\r
+ CAN1_IRQn = 44 /**< 44 SAM3X4E CAN Controller 1 (CAN1) */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */\r
+ void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */\r
+ void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */\r
+ void* pfnSMC_Handler; /* 9 Static Memory Controller */\r
+ void* pvReserved10;\r
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */\r
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */\r
+ void* pfnPIOD_Handler; /* 14 Parallel I/O Controller D */\r
+ void* pvReserved15;\r
+ void* pvReserved16;\r
+ void* pfnUSART0_Handler; /* 17 USART 0 */\r
+ void* pfnUSART1_Handler; /* 18 USART 1 */\r
+ void* pfnUSART2_Handler; /* 19 USART 2 */\r
+ void* pfnUSART3_Handler; /* 20 USART 3 */\r
+ void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */\r
+ void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */\r
+ void* pvReserved25;\r
+ void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 27 Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 28 Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 29 Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 30 Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 31 Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 32 Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 33 Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 34 Timer Counter 7 */\r
+ void* pfnTC8_Handler; /* 35 Timer Counter 8 */\r
+ void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */\r
+ void* pfnADC_Handler; /* 37 ADC Controller */\r
+ void* pfnDACC_Handler; /* 38 DAC Controller */\r
+ void* pfnDMAC_Handler; /* 39 DMA Controller */\r
+ void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */\r
+ void* pfnTRNG_Handler; /* 41 True Random Number Generator */\r
+ void* pfnEMAC_Handler; /* 42 Ethernet MAC */\r
+ void* pfnCAN0_Handler; /* 43 CAN Controller 0 */\r
+ void* pfnCAN1_Handler; /* 44 CAN Controller 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M3 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ADC_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC0_Handler ( void );\r
+void EFC1_Handler ( void );\r
+void EMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SMC_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART_Handler ( void );\r
+void UOTGHS_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USART3_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM3_REV 0x0200 /**< SAM3X4E core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAM3X4E does provide a MPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM3X4E uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm3.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam3x.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_adc.h"\r
+#include "component/component_can.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_dmac.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_emac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pdc.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usart3.h"\r
+#include "instance/instance_uotghs.h"\r
+#include "instance/instance_emac.h"\r
+#include "instance/instance_can0.h"\r
+#include "instance/instance_can1.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dmac.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_smc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_efc0.h"\r
+#include "instance/instance_efc1.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_pioc.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */\r
+#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */\r
+#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */\r
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */\r
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */\r
+#define ID_USART3 (20) /**< \brief USART 3 (USART3) */\r
+#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */\r
+#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */\r
+#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */\r
+#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */\r
+#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */\r
+#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */\r
+#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */\r
+#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */\r
+#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */\r
+#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */\r
+#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */\r
+#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */\r
+#define ID_ADC (37) /**< \brief ADC Controller (ADC) */\r
+#define ID_DACC (38) /**< \brief DAC Controller (DACC) */\r
+#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */\r
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */\r
+#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */\r
+#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */\r
+#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */\r
+#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */\r
+#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */\r
+#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART (0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */\r
+#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */\r
+#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X4E_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sam3x4e.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH0_SIZE (0x20000u)\r
+#define IFLASH0_PAGE_SIZE (256u)\r
+#define IFLASH0_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH0_NB_OF_PAGES (512u)\r
+#define IFLASH1_SIZE (0x20000u)\r
+#define IFLASH1_PAGE_SIZE (256u)\r
+#define IFLASH1_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH1_NB_OF_PAGES (512u)\r
+#define IRAM0_SIZE (0x8000u)\r
+#define IRAM1_SIZE (0x8000u)\r
+#define NFCRAM_SIZE (0x1000u)\r
+#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)\r
+#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)\r
+\r
+#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */\r
+#if defined IFLASH0_SIZE\r
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */\r
+#endif\r
+#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */\r
+#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */\r
+#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */\r
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */\r
+#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */\r
+#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */\r
+#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM3X4E */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (84000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */\r
+#define CHIP_FREQ_FWS_0 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM3X4E_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X8C_\r
+#define _SAM3X8C_\r
+\r
+/** \addtogroup SAM3X8C_definitions SAM3X8C definitions\r
+ This file defines all structures and symbols for SAM3X8C:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM3X8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8C_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */\r
+/****** SAM3X8C specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM3X8C Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM3X8C Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM3X8C Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM3X8C Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM3X8C Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM3X8C Power Management Controller (PMC) */\r
+ EFC0_IRQn = 6, /**< 6 SAM3X8C Enhanced Flash Controller 0 (EFC0) */\r
+ EFC1_IRQn = 7, /**< 7 SAM3X8C Enhanced Flash Controller 1 (EFC1) */\r
+ UART_IRQn = 8, /**< 8 SAM3X8C Universal Asynchronous Receiver Transceiver (UART) */\r
+ PIOA_IRQn = 11, /**< 11 SAM3X8C Parallel I/O Controller A, (PIOA) */\r
+ PIOB_IRQn = 12, /**< 12 SAM3X8C Parallel I/O Controller B (PIOB) */\r
+ USART0_IRQn = 17, /**< 17 SAM3X8C USART 0 (USART0) */\r
+ USART1_IRQn = 18, /**< 18 SAM3X8C USART 1 (USART1) */\r
+ USART2_IRQn = 19, /**< 19 SAM3X8C USART 2 (USART2) */\r
+ HSMCI_IRQn = 21, /**< 21 SAM3X8C Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 22, /**< 22 SAM3X8C Two-Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 23, /**< 23 SAM3X8C Two-Wire Interface 1 (TWI1) */\r
+ SPI0_IRQn = 24, /**< 24 SAM3X8C Serial Peripheral Interface (SPI0) */\r
+ SSC_IRQn = 26, /**< 26 SAM3X8C Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 27, /**< 27 SAM3X8C Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 28, /**< 28 SAM3X8C Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 29, /**< 29 SAM3X8C Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 30, /**< 30 SAM3X8C Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 31, /**< 31 SAM3X8C Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 32, /**< 32 SAM3X8C Timer Counter 5 (TC5) */\r
+ PWM_IRQn = 36, /**< 36 SAM3X8C Pulse Width Modulation Controller (PWM) */\r
+ ADC_IRQn = 37, /**< 37 SAM3X8C ADC Controller (ADC) */\r
+ DACC_IRQn = 38, /**< 38 SAM3X8C DAC Controller (DACC) */\r
+ DMAC_IRQn = 39, /**< 39 SAM3X8C DMA Controller (DMAC) */\r
+ UOTGHS_IRQn = 40, /**< 40 SAM3X8C USB OTG High Speed (UOTGHS) */\r
+ TRNG_IRQn = 41, /**< 41 SAM3X8C True Random Number Generator (TRNG) */\r
+ EMAC_IRQn = 42, /**< 42 SAM3X8C Ethernet MAC (EMAC) */\r
+ CAN0_IRQn = 43, /**< 43 SAM3X8C CAN Controller 0 (CAN0) */\r
+ CAN1_IRQn = 44 /**< 44 SAM3X8C CAN Controller 1 (CAN1) */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */\r
+ void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */\r
+ void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */\r
+ void* pvReserved9;\r
+ void* pvReserved10;\r
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */\r
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */\r
+ void* pvReserved13;\r
+ void* pvReserved14;\r
+ void* pvReserved15;\r
+ void* pvReserved16;\r
+ void* pfnUSART0_Handler; /* 17 USART 0 */\r
+ void* pfnUSART1_Handler; /* 18 USART 1 */\r
+ void* pfnUSART2_Handler; /* 19 USART 2 */\r
+ void* pvReserved20;\r
+ void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */\r
+ void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */\r
+ void* pvReserved25;\r
+ void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 27 Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 28 Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 29 Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 30 Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 31 Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 32 Timer Counter 5 */\r
+ void* pvReserved33;\r
+ void* pvReserved34;\r
+ void* pvReserved35;\r
+ void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */\r
+ void* pfnADC_Handler; /* 37 ADC Controller */\r
+ void* pfnDACC_Handler; /* 38 DAC Controller */\r
+ void* pfnDMAC_Handler; /* 39 DMA Controller */\r
+ void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */\r
+ void* pfnTRNG_Handler; /* 41 True Random Number Generator */\r
+ void* pfnEMAC_Handler; /* 42 Ethernet MAC */\r
+ void* pfnCAN0_Handler; /* 43 CAN Controller 0 */\r
+ void* pfnCAN1_Handler; /* 44 CAN Controller 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M3 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ADC_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC0_Handler ( void );\r
+void EFC1_Handler ( void );\r
+void EMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART_Handler ( void );\r
+void UOTGHS_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM3_REV 0x0200 /**< SAM3X8C core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAM3X8C does provide a MPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM3X8C uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm3.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam3x.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8C_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_adc.h"\r
+#include "component/component_can.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_dmac.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_emac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pdc.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM3X8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8C_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_uotghs.h"\r
+#include "instance/instance_emac.h"\r
+#include "instance/instance_can0.h"\r
+#include "instance/instance_can1.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dmac.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_efc0.h"\r
+#include "instance/instance_efc1.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM3X8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8C_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */\r
+#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */\r
+#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */\r
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */\r
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */\r
+#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */\r
+#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */\r
+#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */\r
+#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */\r
+#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */\r
+#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */\r
+#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */\r
+#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */\r
+#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */\r
+#define ID_ADC (37) /**< \brief ADC Controller (ADC) */\r
+#define ID_DACC (38) /**< \brief DAC Controller (DACC) */\r
+#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */\r
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */\r
+#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */\r
+#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */\r
+#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */\r
+#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM3X8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8C_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART (0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM3X8C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8C_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sam3x8c.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM3X8C */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH0_SIZE (0x40000u)\r
+#define IFLASH0_PAGE_SIZE (256u)\r
+#define IFLASH0_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH0_NB_OF_PAGES (1024u)\r
+#define IFLASH1_SIZE (0x40000u)\r
+#define IFLASH1_PAGE_SIZE (256u)\r
+#define IFLASH1_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH1_NB_OF_PAGES (1024u)\r
+#define IRAM0_SIZE (0x10000u)\r
+#define IRAM1_SIZE (0x8000u)\r
+#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)\r
+#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)\r
+\r
+#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */\r
+#if defined IFLASH0_SIZE\r
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */\r
+#endif\r
+#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */\r
+#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */\r
+#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */\r
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */\r
+#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */\r
+#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */\r
+#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM3X8C */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (84000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */\r
+#define CHIP_FREQ_FWS_0 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM3X8C_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X8E_\r
+#define _SAM3X8E_\r
+\r
+/** \addtogroup SAM3X8E_definitions SAM3X8E definitions\r
+ This file defines all structures and symbols for SAM3X8E:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM3X8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8E_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */\r
+/****** SAM3X8E specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM3X8E Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM3X8E Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM3X8E Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM3X8E Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM3X8E Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM3X8E Power Management Controller (PMC) */\r
+ EFC0_IRQn = 6, /**< 6 SAM3X8E Enhanced Flash Controller 0 (EFC0) */\r
+ EFC1_IRQn = 7, /**< 7 SAM3X8E Enhanced Flash Controller 1 (EFC1) */\r
+ UART_IRQn = 8, /**< 8 SAM3X8E Universal Asynchronous Receiver Transceiver (UART) */\r
+ SMC_IRQn = 9, /**< 9 SAM3X8E Static Memory Controller (SMC) */\r
+ PIOA_IRQn = 11, /**< 11 SAM3X8E Parallel I/O Controller A, (PIOA) */\r
+ PIOB_IRQn = 12, /**< 12 SAM3X8E Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 13, /**< 13 SAM3X8E Parallel I/O Controller C (PIOC) */\r
+ PIOD_IRQn = 14, /**< 14 SAM3X8E Parallel I/O Controller D (PIOD) */\r
+ USART0_IRQn = 17, /**< 17 SAM3X8E USART 0 (USART0) */\r
+ USART1_IRQn = 18, /**< 18 SAM3X8E USART 1 (USART1) */\r
+ USART2_IRQn = 19, /**< 19 SAM3X8E USART 2 (USART2) */\r
+ USART3_IRQn = 20, /**< 20 SAM3X8E USART 3 (USART3) */\r
+ HSMCI_IRQn = 21, /**< 21 SAM3X8E Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 22, /**< 22 SAM3X8E Two-Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 23, /**< 23 SAM3X8E Two-Wire Interface 1 (TWI1) */\r
+ SPI0_IRQn = 24, /**< 24 SAM3X8E Serial Peripheral Interface (SPI0) */\r
+ SSC_IRQn = 26, /**< 26 SAM3X8E Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 27, /**< 27 SAM3X8E Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 28, /**< 28 SAM3X8E Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 29, /**< 29 SAM3X8E Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 30, /**< 30 SAM3X8E Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 31, /**< 31 SAM3X8E Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 32, /**< 32 SAM3X8E Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 33, /**< 33 SAM3X8E Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 34, /**< 34 SAM3X8E Timer Counter 7 (TC7) */\r
+ TC8_IRQn = 35, /**< 35 SAM3X8E Timer Counter 8 (TC8) */\r
+ PWM_IRQn = 36, /**< 36 SAM3X8E Pulse Width Modulation Controller (PWM) */\r
+ ADC_IRQn = 37, /**< 37 SAM3X8E ADC Controller (ADC) */\r
+ DACC_IRQn = 38, /**< 38 SAM3X8E DAC Controller (DACC) */\r
+ DMAC_IRQn = 39, /**< 39 SAM3X8E DMA Controller (DMAC) */\r
+ UOTGHS_IRQn = 40, /**< 40 SAM3X8E USB OTG High Speed (UOTGHS) */\r
+ TRNG_IRQn = 41, /**< 41 SAM3X8E True Random Number Generator (TRNG) */\r
+ EMAC_IRQn = 42, /**< 42 SAM3X8E Ethernet MAC (EMAC) */\r
+ CAN0_IRQn = 43, /**< 43 SAM3X8E CAN Controller 0 (CAN0) */\r
+ CAN1_IRQn = 44 /**< 44 SAM3X8E CAN Controller 1 (CAN1) */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */\r
+ void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */\r
+ void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */\r
+ void* pfnSMC_Handler; /* 9 Static Memory Controller */\r
+ void* pvReserved10;\r
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */\r
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */\r
+ void* pfnPIOD_Handler; /* 14 Parallel I/O Controller D */\r
+ void* pvReserved15;\r
+ void* pvReserved16;\r
+ void* pfnUSART0_Handler; /* 17 USART 0 */\r
+ void* pfnUSART1_Handler; /* 18 USART 1 */\r
+ void* pfnUSART2_Handler; /* 19 USART 2 */\r
+ void* pfnUSART3_Handler; /* 20 USART 3 */\r
+ void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */\r
+ void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */\r
+ void* pvReserved25;\r
+ void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 27 Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 28 Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 29 Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 30 Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 31 Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 32 Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 33 Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 34 Timer Counter 7 */\r
+ void* pfnTC8_Handler; /* 35 Timer Counter 8 */\r
+ void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */\r
+ void* pfnADC_Handler; /* 37 ADC Controller */\r
+ void* pfnDACC_Handler; /* 38 DAC Controller */\r
+ void* pfnDMAC_Handler; /* 39 DMA Controller */\r
+ void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */\r
+ void* pfnTRNG_Handler; /* 41 True Random Number Generator */\r
+ void* pfnEMAC_Handler; /* 42 Ethernet MAC */\r
+ void* pfnCAN0_Handler; /* 43 CAN Controller 0 */\r
+ void* pfnCAN1_Handler; /* 44 CAN Controller 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M3 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ADC_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC0_Handler ( void );\r
+void EFC1_Handler ( void );\r
+void EMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SMC_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART_Handler ( void );\r
+void UOTGHS_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USART3_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM3_REV 0x0200 /**< SAM3X8E core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAM3X8E does provide a MPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM3X8E uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm3.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam3x.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8E_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_adc.h"\r
+#include "component/component_can.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_dmac.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_emac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pdc.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM3X8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8E_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usart3.h"\r
+#include "instance/instance_uotghs.h"\r
+#include "instance/instance_emac.h"\r
+#include "instance/instance_can0.h"\r
+#include "instance/instance_can1.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dmac.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_smc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_efc0.h"\r
+#include "instance/instance_efc1.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_pioc.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM3X8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8E_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */\r
+#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */\r
+#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */\r
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */\r
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */\r
+#define ID_USART3 (20) /**< \brief USART 3 (USART3) */\r
+#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */\r
+#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */\r
+#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */\r
+#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */\r
+#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */\r
+#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */\r
+#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */\r
+#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */\r
+#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */\r
+#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */\r
+#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */\r
+#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */\r
+#define ID_ADC (37) /**< \brief ADC Controller (ADC) */\r
+#define ID_DACC (38) /**< \brief DAC Controller (DACC) */\r
+#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */\r
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */\r
+#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */\r
+#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */\r
+#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */\r
+#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM3X8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8E_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */\r
+#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */\r
+#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART (0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */\r
+#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */\r
+#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM3X8E */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8E_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sam3x8e.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM3X8E */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH0_SIZE (0x40000u)\r
+#define IFLASH0_PAGE_SIZE (256u)\r
+#define IFLASH0_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH0_NB_OF_PAGES (1024u)\r
+#define IFLASH1_SIZE (0x40000u)\r
+#define IFLASH1_PAGE_SIZE (256u)\r
+#define IFLASH1_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH1_NB_OF_PAGES (1024u)\r
+#define IRAM0_SIZE (0x10000u)\r
+#define IRAM1_SIZE (0x8000u)\r
+#define NFCRAM_SIZE (0x1000u)\r
+#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)\r
+#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)\r
+\r
+#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */\r
+#if defined IFLASH0_SIZE\r
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */\r
+#endif\r
+#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */\r
+#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */\r
+#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */\r
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */\r
+#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */\r
+#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */\r
+#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM3X8E */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (84000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */\r
+#define CHIP_FREQ_FWS_0 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM3X8E_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3X8H_\r
+#define _SAM3X8H_\r
+\r
+/** \addtogroup SAM3X8H_definitions SAM3X8H definitions\r
+ This file defines all structures and symbols for SAM3X8H:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM3X8H */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8H_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */\r
+/****** SAM3X8H specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM3X8H Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM3X8H Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM3X8H Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM3X8H Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM3X8H Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM3X8H Power Management Controller (PMC) */\r
+ EFC0_IRQn = 6, /**< 6 SAM3X8H Enhanced Flash Controller 0 (EFC0) */\r
+ EFC1_IRQn = 7, /**< 7 SAM3X8H Enhanced Flash Controller 1 (EFC1) */\r
+ UART_IRQn = 8, /**< 8 SAM3X8H Universal Asynchronous Receiver Transceiver (UART) */\r
+ SMC_IRQn = 9, /**< 9 SAM3X8H Static Memory Controller (SMC) */\r
+ SDRAMC_IRQn = 10, /**< 10 SAM3X8H Synchronous Dynamic RAM Controller (SDRAMC) */\r
+ PIOA_IRQn = 11, /**< 11 SAM3X8H Parallel I/O Controller A, (PIOA) */\r
+ PIOB_IRQn = 12, /**< 12 SAM3X8H Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 13, /**< 13 SAM3X8H Parallel I/O Controller C (PIOC) */\r
+ PIOD_IRQn = 14, /**< 14 SAM3X8H Parallel I/O Controller D (PIOD) */\r
+ PIOE_IRQn = 15, /**< 15 SAM3X8H Parallel I/O Controller E (PIOE) */\r
+ PIOF_IRQn = 16, /**< 16 SAM3X8H Parallel I/O Controller F (PIOF) */\r
+ USART0_IRQn = 17, /**< 17 SAM3X8H USART 0 (USART0) */\r
+ USART1_IRQn = 18, /**< 18 SAM3X8H USART 1 (USART1) */\r
+ USART2_IRQn = 19, /**< 19 SAM3X8H USART 2 (USART2) */\r
+ USART3_IRQn = 20, /**< 20 SAM3X8H USART 3 (USART3) */\r
+ HSMCI_IRQn = 21, /**< 21 SAM3X8H Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 22, /**< 22 SAM3X8H Two-Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 23, /**< 23 SAM3X8H Two-Wire Interface 1 (TWI1) */\r
+ SPI0_IRQn = 24, /**< 24 SAM3X8H Serial Peripheral Interface (SPI0) */\r
+ SPI1_IRQn = 25, /**< 25 SAM3X8H Serial Peripheral Interface (SPI1) */\r
+ SSC_IRQn = 26, /**< 26 SAM3X8H Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 27, /**< 27 SAM3X8H Timer Counter 0 (TC0) */\r
+ TC1_IRQn = 28, /**< 28 SAM3X8H Timer Counter 1 (TC1) */\r
+ TC2_IRQn = 29, /**< 29 SAM3X8H Timer Counter 2 (TC2) */\r
+ TC3_IRQn = 30, /**< 30 SAM3X8H Timer Counter 3 (TC3) */\r
+ TC4_IRQn = 31, /**< 31 SAM3X8H Timer Counter 4 (TC4) */\r
+ TC5_IRQn = 32, /**< 32 SAM3X8H Timer Counter 5 (TC5) */\r
+ TC6_IRQn = 33, /**< 33 SAM3X8H Timer Counter 6 (TC6) */\r
+ TC7_IRQn = 34, /**< 34 SAM3X8H Timer Counter 7 (TC7) */\r
+ TC8_IRQn = 35, /**< 35 SAM3X8H Timer Counter 8 (TC8) */\r
+ PWM_IRQn = 36, /**< 36 SAM3X8H Pulse Width Modulation Controller (PWM) */\r
+ ADC_IRQn = 37, /**< 37 SAM3X8H ADC Controller (ADC) */\r
+ DACC_IRQn = 38, /**< 38 SAM3X8H DAC Controller (DACC) */\r
+ DMAC_IRQn = 39, /**< 39 SAM3X8H DMA Controller (DMAC) */\r
+ UOTGHS_IRQn = 40, /**< 40 SAM3X8H USB OTG High Speed (UOTGHS) */\r
+ TRNG_IRQn = 41, /**< 41 SAM3X8H True Random Number Generator (TRNG) */\r
+ EMAC_IRQn = 42, /**< 42 SAM3X8H Ethernet MAC (EMAC) */\r
+ CAN0_IRQn = 43, /**< 43 SAM3X8H CAN Controller 0 (CAN0) */\r
+ CAN1_IRQn = 44 /**< 44 SAM3X8H CAN Controller 1 (CAN1) */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */\r
+ void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */\r
+ void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */\r
+ void* pfnSMC_Handler; /* 9 Static Memory Controller */\r
+ void* pfnSDRAMC_Handler; /* 10 Synchronous Dynamic RAM Controller */\r
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */\r
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */\r
+ void* pfnPIOD_Handler; /* 14 Parallel I/O Controller D */\r
+ void* pfnPIOE_Handler; /* 15 Parallel I/O Controller E */\r
+ void* pfnPIOF_Handler; /* 16 Parallel I/O Controller F */\r
+ void* pfnUSART0_Handler; /* 17 USART 0 */\r
+ void* pfnUSART1_Handler; /* 18 USART 1 */\r
+ void* pfnUSART2_Handler; /* 19 USART 2 */\r
+ void* pfnUSART3_Handler; /* 20 USART 3 */\r
+ void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */\r
+ void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */\r
+ void* pfnSPI1_Handler; /* 25 Serial Peripheral Interface */\r
+ void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 27 Timer Counter 0 */\r
+ void* pfnTC1_Handler; /* 28 Timer Counter 1 */\r
+ void* pfnTC2_Handler; /* 29 Timer Counter 2 */\r
+ void* pfnTC3_Handler; /* 30 Timer Counter 3 */\r
+ void* pfnTC4_Handler; /* 31 Timer Counter 4 */\r
+ void* pfnTC5_Handler; /* 32 Timer Counter 5 */\r
+ void* pfnTC6_Handler; /* 33 Timer Counter 6 */\r
+ void* pfnTC7_Handler; /* 34 Timer Counter 7 */\r
+ void* pfnTC8_Handler; /* 35 Timer Counter 8 */\r
+ void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */\r
+ void* pfnADC_Handler; /* 37 ADC Controller */\r
+ void* pfnDACC_Handler; /* 38 DAC Controller */\r
+ void* pfnDMAC_Handler; /* 39 DMA Controller */\r
+ void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */\r
+ void* pfnTRNG_Handler; /* 41 True Random Number Generator */\r
+ void* pfnEMAC_Handler; /* 42 Ethernet MAC */\r
+ void* pfnCAN0_Handler; /* 43 CAN Controller 0 */\r
+ void* pfnCAN1_Handler; /* 44 CAN Controller 1 */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M3 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ADC_Handler ( void );\r
+void CAN0_Handler ( void );\r
+void CAN1_Handler ( void );\r
+void DACC_Handler ( void );\r
+void DMAC_Handler ( void );\r
+void EFC0_Handler ( void );\r
+void EFC1_Handler ( void );\r
+void EMAC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PIOD_Handler ( void );\r
+void PIOE_Handler ( void );\r
+void PIOF_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SDRAMC_Handler ( void );\r
+void SMC_Handler ( void );\r
+void SPI0_Handler ( void );\r
+void SPI1_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TC6_Handler ( void );\r
+void TC7_Handler ( void );\r
+void TC8_Handler ( void );\r
+void TRNG_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART_Handler ( void );\r
+void UOTGHS_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void USART2_Handler ( void );\r
+void USART3_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM3_REV 0x0200 /**< SAM3X8H core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAM3X8H does provide a MPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM3X8H uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm3.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam3x.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8H */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8H_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_adc.h"\r
+#include "component/component_can.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_dmac.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_emac.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pdc.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_sdramc.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_trng.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_uotghs.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM3X8H */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8H_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi0.h"\r
+#include "instance/instance_spi1.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_tc2.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_usart2.h"\r
+#include "instance/instance_usart3.h"\r
+#include "instance/instance_uotghs.h"\r
+#include "instance/instance_emac.h"\r
+#include "instance/instance_can0.h"\r
+#include "instance/instance_can1.h"\r
+#include "instance/instance_trng.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dmac.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_smc.h"\r
+#include "instance/instance_sdramc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_efc0.h"\r
+#include "instance/instance_efc1.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_pioc.h"\r
+#include "instance/instance_piod.h"\r
+#include "instance/instance_pioe.h"\r
+#include "instance/instance_piof.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM3X8H */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8H_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */\r
+#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */\r
+#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */\r
+#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_SDRAMC (10) /**< \brief Synchronous Dynamic RAM Controller (SDRAMC) */\r
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */\r
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */\r
+#define ID_PIOE (15) /**< \brief Parallel I/O Controller E (PIOE) */\r
+#define ID_PIOF (16) /**< \brief Parallel I/O Controller F (PIOF) */\r
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */\r
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */\r
+#define ID_USART3 (20) /**< \brief USART 3 (USART3) */\r
+#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */\r
+#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */\r
+#define ID_SPI1 (25) /**< \brief Serial Peripheral Interface (SPI1) */\r
+#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */\r
+#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */\r
+#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */\r
+#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */\r
+#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */\r
+#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */\r
+#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */\r
+#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */\r
+#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */\r
+#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */\r
+#define ID_ADC (37) /**< \brief ADC Controller (ADC) */\r
+#define ID_DACC (38) /**< \brief DAC Controller (DACC) */\r
+#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */\r
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */\r
+#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */\r
+#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */\r
+#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */\r
+#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM3X8H */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8H_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define SPI1 (0x4000C000U) /**< \brief (SPI1 ) Base Address */\r
+#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */\r
+#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */\r
+#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC (0x400E0200U) /**< \brief (SDRAMC ) Base Address */\r
+#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART (0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define PIOF (0x400E1800U) /**< \brief (PIOF ) Base Address */\r
+#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */\r
+#define SPI1 ((Spi *)0x4000C000U) /**< \brief (SPI1 ) Base Address */\r
+#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */\r
+#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */\r
+#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */\r
+#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */\r
+#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */\r
+#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */\r
+#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */\r
+#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */\r
+#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */\r
+#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */\r
+#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */\r
+#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */\r
+#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */\r
+#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define SDRAMC ((Sdramc *)0x400E0200U) /**< \brief (SDRAMC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */\r
+#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */\r
+#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */\r
+#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */\r
+#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */\r
+#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */\r
+#define PIOF ((Pio *)0x400E1800U) /**< \brief (PIOF ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM3X8H */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM3X8H_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sam3x8h.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM3X8H */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH0_SIZE (0x40000u)\r
+#define IFLASH0_PAGE_SIZE (256u)\r
+#define IFLASH0_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH0_NB_OF_PAGES (1024u)\r
+#define IFLASH1_SIZE (0x40000u)\r
+#define IFLASH1_PAGE_SIZE (256u)\r
+#define IFLASH1_LOCK_REGION_SIZE (16384u)\r
+#define IFLASH1_NB_OF_PAGES (1024u)\r
+#define IRAM0_SIZE (0x10000u)\r
+#define IRAM1_SIZE (0x8000u)\r
+#define NFCRAM_SIZE (0x1000u)\r
+#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)\r
+#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE)\r
+\r
+#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */\r
+#if defined IFLASH0_SIZE\r
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */\r
+#endif\r
+#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */\r
+#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */\r
+#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */\r
+#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */\r
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */\r
+#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */\r
+#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */\r
+#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM3X8H */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (84000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */\r
+#define CHIP_FREQ_FWS_0 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM3X8H_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM3XA_\r
+#define _SAM3XA_\r
+\r
+#if defined __SAM3A4C__\r
+ #include "sam3a4c.h"\r
+#elif defined __SAM3A8C__\r
+ #include "sam3a8c.h"\r
+#elif defined __SAM3X4C__\r
+ #include "sam3x4c.h"\r
+#elif defined __SAM3X4E__\r
+ #include "sam3x4e.h"\r
+#elif defined __SAM3X8C__\r
+ #include "sam3x8c.h"\r
+#elif defined __SAM3X8E__\r
+ #include "sam3x8e.h"\r
+#elif defined __SAM3X8H__\r
+ #include "sam3x8h.h"\r
+#else\r
+ #error Library does not support the specified device.\r
+#endif\r
+\r
+#endif /* _SAM3XA_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief This file contains the default exception handlers.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * This file provides basic support for Cortex-M processor based\r
+ * microcontrollers.\r
+ *\r
+ * \note\r
+ * The exception handler has weak aliases.\r
+ * As they are weak aliases, any function with the same name will override\r
+ * this definition.\r
+ *\r
+ */\r
+\r
+#include "exceptions.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#ifdef __GNUC__\r
+/* Cortex-M3 core handlers */\r
+void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+\r
+/* Peripherals handlers */\r
+void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void EFC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void EFC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UART_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#ifdef _SAM3XA_SMC_INSTANCE_\r
+void SMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* _SAM3XA_SMC_INSTANCE_ */\r
+#ifdef _SAM3XA_SDRAMC_INSTANCE_\r
+void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */\r
+void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#ifdef _SAM3XA_PIOC_INSTANCE_\r
+void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* _SAM3XA_PIOC_INSTANCE_ */\r
+#ifdef _SAM3XA_PIOD_INSTANCE_\r
+void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* _SAM3XA_PIOD_INSTANCE_ */\r
+#ifdef _SAM3XA_PIOE_INSTANCE_\r
+void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* _SAM3XA_PIOE_INSTANCE_ */\r
+#ifdef _SAM3XA_PIOF_INSTANCE_\r
+void PIOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* _SAM3XA_PIOF_INSTANCE_ */\r
+void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#ifdef _SAM3XA_USART3_INSTANCE_\r
+void USART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* _SAM3XA_USART3_INSTANCE_ */\r
+void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TWI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TWI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#ifdef _SAM3XA_SPI1_INSTANCE_\r
+void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* _SAM3XA_SPI1_INSTANCE_ */\r
+void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#ifdef _SAM3XA_TC2_INSTANCE_\r
+void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* _SAM3XA_TC2_INSTANCE_ */\r
+void PWM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UOTGHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#ifdef _SAM3XA_EMAC_INSTANCE_\r
+void EMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* _SAM3XA_EMAC_INSTANCE_ */\r
+void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* __GNUC__ */\r
+\r
+#ifdef __ICCARM__\r
+/* Cortex-M3 core handlers */\r
+#pragma weak NMI_Handler=Dummy_Handler\r
+#pragma weak HardFault_Handler=Dummy_Handler\r
+#pragma weak MemManage_Handler=Dummy_Handler\r
+#pragma weak BusFault_Handler=Dummy_Handler\r
+#pragma weak UsageFault_Handler=Dummy_Handler\r
+#pragma weak SVC_Handler=Dummy_Handler\r
+#pragma weak DebugMon_Handler=Dummy_Handler\r
+#pragma weak PendSV_Handler=Dummy_Handler\r
+#pragma weak SysTick_Handler=Dummy_Handler\r
+\r
+/* Peripherals handlers */\r
+#pragma weak SUPC_Handler=Dummy_Handler\r
+#pragma weak RSTC_Handler=Dummy_Handler\r
+#pragma weak RTC_Handler=Dummy_Handler\r
+#pragma weak RTT_Handler=Dummy_Handler\r
+#pragma weak WDT_Handler=Dummy_Handler\r
+#pragma weak PMC_Handler=Dummy_Handler\r
+#pragma weak EFC0_Handler=Dummy_Handler\r
+#pragma weak EFC1_Handler=Dummy_Handler\r
+#pragma weak UART_Handler=Dummy_Handler\r
+#ifdef _SAM3XA_SMC_INSTANCE_\r
+#pragma weak SMC_Handler=Dummy_Handler\r
+#endif /* _SAM3XA_SMC_INSTANCE_ */\r
+#ifdef _SAM3XA_SDRAMC_INSTANCE_\r
+#pragma weak SDRAMC_Handler=Dummy_Handler\r
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */\r
+#pragma weak PIOA_Handler=Dummy_Handler\r
+#pragma weak PIOB_Handler=Dummy_Handler\r
+#ifdef _SAM3XA_PIOC_INSTANCE_\r
+#pragma weak PIOC_Handler=Dummy_Handler\r
+#endif /* _SAM3XA_PIOC_INSTANCE_ */\r
+#ifdef _SAM3XA_PIOD_INSTANCE_\r
+#pragma weak PIOD_Handler=Dummy_Handler\r
+#endif /* _SAM3XA_PIOD_INSTANCE_ */\r
+#ifdef _SAM3XA_PIOE_INSTANCE_\r
+#pragma weak PIOE_Handler=Dummy_Handler\r
+#endif /* _SAM3XA_PIOE_INSTANCE_ */\r
+#ifdef _SAM3XA_PIOF_INSTANCE_\r
+#pragma weak PIOF_Handler=Dummy_Handler\r
+#endif /* _SAM3XA_PIOF_INSTANCE_ */\r
+#pragma weak USART0_Handler=Dummy_Handler\r
+#pragma weak USART1_Handler=Dummy_Handler\r
+#pragma weak USART2_Handler=Dummy_Handler\r
+#ifdef _SAM3XA_USART3_INSTANCE_\r
+#pragma weak USART3_Handler=Dummy_Handler\r
+#endif /* _SAM3XA_USART3_INSTANCE_ */\r
+#pragma weak HSMCI_Handler=Dummy_Handler\r
+#pragma weak TWI0_Handler=Dummy_Handler\r
+#pragma weak TWI1_Handler=Dummy_Handler\r
+#pragma weak SPI0_Handler=Dummy_Handler\r
+#ifdef _SAM3XA_SPI1_INSTANCE_\r
+#pragma weak SPI1_Handler=Dummy_Handler\r
+#endif /* _SAM3XA_SPI1_INSTANCE_ */\r
+#pragma weak SSC_Handler=Dummy_Handler\r
+#pragma weak TC0_Handler=Dummy_Handler\r
+#pragma weak TC1_Handler=Dummy_Handler\r
+#pragma weak TC2_Handler=Dummy_Handler\r
+#pragma weak TC3_Handler=Dummy_Handler\r
+#pragma weak TC4_Handler=Dummy_Handler\r
+#pragma weak TC5_Handler=Dummy_Handler\r
+#ifdef _SAM3XA_TC2_INSTANCE_\r
+#pragma weak TC6_Handler=Dummy_Handler\r
+#pragma weak TC7_Handler=Dummy_Handler\r
+#pragma weak TC8_Handler=Dummy_Handler\r
+#endif /* _SAM3XA_TC2_INSTANCE_ */\r
+#pragma weak PWM_Handler=Dummy_Handler\r
+#pragma weak ADC_Handler=Dummy_Handler\r
+#pragma weak DACC_Handler=Dummy_Handler\r
+#pragma weak DMAC_Handler=Dummy_Handler\r
+#pragma weak UOTGHS_Handler=Dummy_Handler\r
+#pragma weak TRNG_Handler=Dummy_Handler\r
+#ifdef _SAM3XA_EMAC_INSTANCE_\r
+#pragma weak EMAC_Handler=Dummy_Handler\r
+#endif /* _SAM3XA_EMAC_INSTANCE_ */\r
+#pragma weak CAN0_Handler=Dummy_Handler\r
+#pragma weak CAN1_Handler=Dummy_Handler\r
+#endif /* __ICCARM__ */\r
+\r
+/**\r
+ * \brief Default interrupt handler for unused IRQs.\r
+ */\r
+void Dummy_Handler(void)\r
+{\r
+ while (1) {\r
+ }\r
+}\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief This file contains the interface for default exception handlers.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef EXCEPTIONS_H_INCLUDED\r
+#define EXCEPTIONS_H_INCLUDED\r
+\r
+#include "sam3xa.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+/* Function prototype for exception table items (interrupt handler). */\r
+typedef void (*IntFunc) (void);\r
+\r
+/* Default empty handler */\r
+void Dummy_Handler(void);\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#endif /* EXCEPTIONS_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Startup file for SAM3X.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "exceptions.h"\r
+#include "sam3xa.h"\r
+#include "system_sam3x.h"\r
+\r
+/* Initialize segments */\r
+extern uint32_t _sfixed;\r
+extern uint32_t _efixed;\r
+extern uint32_t _etext;\r
+extern uint32_t _srelocate;\r
+extern uint32_t _erelocate;\r
+extern uint32_t _szero;\r
+extern uint32_t _ezero;\r
+extern uint32_t _sstack;\r
+extern uint32_t _estack;\r
+\r
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */\r
+int main(void);\r
+/** \endcond */\r
+\r
+void __libc_init_array(void);\r
+\r
+/* Exception Table */\r
+__attribute__ ((section(".vectors")))\r
+IntFunc exception_table[] = {\r
+\r
+ /* Configure Initial Stack Pointer, using linker-generated symbols */\r
+ (IntFunc) (&_estack),\r
+ (void*) Reset_Handler,\r
+\r
+ (void*) NMI_Handler,\r
+ (void*) HardFault_Handler,\r
+ (void*) MemManage_Handler,\r
+ (void*) BusFault_Handler,\r
+ (void*) UsageFault_Handler,\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) SVC_Handler,\r
+ (void*) DebugMon_Handler,\r
+ (void*) (0UL), /* Reserved */\r
+ (void*) PendSV_Handler,\r
+ (void*) SysTick_Handler,\r
+\r
+ /* Configurable interrupts */\r
+ (void*) SUPC_Handler, /* 0 Supply Controller */\r
+ (void*) RSTC_Handler, /* 1 Reset Controller */\r
+ (void*) RTC_Handler, /* 2 Real Time Clock */\r
+ (void*) RTT_Handler, /* 3 Real Time Timer */\r
+ (void*) WDT_Handler, /* 4 Watchdog Timer */\r
+ (void*) PMC_Handler, /* 5 PMC */\r
+ (void*) EFC0_Handler, /* 6 EFC 0 */\r
+ (void*) EFC1_Handler, /* 7 EFC 1 */\r
+ (void*) UART_Handler, /* 8 UART */\r
+#ifdef _SAM3XA_SMC_INSTANCE_\r
+ (void*) SMC_Handler, /* 9 SMC */\r
+#else\r
+ (void*) (0UL), /* 9 Reserved */\r
+#endif /* _SAM3XA_SMC_INSTANCE_ */\r
+#ifdef _SAM3XA_SDRAMC_INSTANCE_\r
+ (void*) SDRAMC_Handler, /* 10 SDRAMC */\r
+#else\r
+ (void*) (0UL), /* 10 Reserved */\r
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */\r
+ (void*) PIOA_Handler, /* 11 Parallel IO Controller A */\r
+ (void*) PIOB_Handler, /* 12 Parallel IO Controller B */\r
+#ifdef _SAM3XA_PIOC_INSTANCE_\r
+ (void*) PIOC_Handler, /* 13 Parallel IO Controller C */\r
+#else\r
+ (void*) (0UL), /* 13 Reserved */\r
+#endif /* _SAM3XA_PIOC_INSTANCE_ */\r
+#ifdef _SAM3XA_PIOD_INSTANCE_\r
+ (void*) PIOD_Handler, /* 14 Parallel IO Controller D */\r
+#else\r
+ (void*) (0UL), /* 14 Reserved */\r
+#endif /* _SAM3XA_PIOD_INSTANCE_ */\r
+#ifdef _SAM3XA_PIOE_INSTANCE_\r
+ (void*) PIOE_Handler, /* 15 Parallel IO Controller E */\r
+#else\r
+ (void*) (0UL), /* 15 Reserved */\r
+#endif /* _SAM3XA_PIOE_INSTANCE_ */\r
+#ifdef _SAM3XA_PIOF_INSTANCE_\r
+ (void*) PIOF_Handler, /* 16 Parallel IO Controller F */\r
+#else\r
+ (void*) (0UL), /* 16 Reserved */\r
+#endif /* _SAM3XA_PIOF_INSTANCE_ */\r
+ (void*) USART0_Handler, /* 17 USART 0 */\r
+ (void*) USART1_Handler, /* 18 USART 1 */\r
+ (void*) USART2_Handler, /* 19 USART 2 */\r
+#ifdef _SAM3XA_USART3_INSTANCE_\r
+ (void*) USART3_Handler, /* 20 USART 3 */\r
+#else\r
+ (void*) (0UL), /* 20 Reserved */\r
+#endif /* _SAM3XA_USART3_INSTANCE_ */\r
+ (void*) HSMCI_Handler, /* 21 MCI */\r
+ (void*) TWI0_Handler, /* 22 TWI 0 */\r
+ (void*) TWI1_Handler, /* 23 TWI 1 */\r
+ (void*) SPI0_Handler, /* 24 SPI 0 */\r
+#ifdef _SAM3XA_SPI1_INSTANCE_\r
+ (void*) SPI1_Handler, /* 25 SPI 1 */\r
+#else\r
+ (void*) (0UL), /* 25 Reserved */\r
+#endif /* _SAM3XA_SPI1_INSTANCE_ */\r
+ (void*) SSC_Handler, /* 26 SSC */\r
+ (void*) TC0_Handler, /* 27 Timer Counter 0 */\r
+ (void*) TC1_Handler, /* 28 Timer Counter 1 */\r
+ (void*) TC2_Handler, /* 29 Timer Counter 2 */\r
+ (void*) TC3_Handler, /* 30 Timer Counter 3 */\r
+ (void*) TC4_Handler, /* 31 Timer Counter 4 */\r
+ (void*) TC5_Handler, /* 32 Timer Counter 5 */\r
+#ifdef _SAM3XA_TC2_INSTANCE_\r
+ (void*) TC6_Handler, /* 33 Timer Counter 6 */\r
+ (void*) TC7_Handler, /* 34 Timer Counter 7 */\r
+ (void*) TC8_Handler, /* 35 Timer Counter 8 */\r
+#else\r
+ (void*) (0UL), /* 33 Reserved */\r
+ (void*) (0UL), /* 34 Reserved */\r
+ (void*) (0UL), /* 35 Reserved */\r
+#endif /* _SAM3XA_TC2_INSTANCE_ */\r
+ (void*) PWM_Handler, /* 36 PWM */\r
+ (void*) ADC_Handler, /* 37 ADC controller */\r
+ (void*) DACC_Handler, /* 38 DAC controller */\r
+ (void*) DMAC_Handler, /* 39 DMA Controller */\r
+ (void*) UOTGHS_Handler, /* 40 USB OTG High Speed */\r
+ (void*) TRNG_Handler, /* 41 True Random Number Generator */\r
+#ifdef _SAM3XA_EMAC_INSTANCE_\r
+ (void*) EMAC_Handler, /* 42 Ethernet MAC */\r
+#else\r
+ (void*) (0UL), /* 42 Reserved */\r
+#endif /* _SAM3XA_EMAC_INSTANCE_ */\r
+ (void*) CAN0_Handler, /* 43 CAN Controller 0 */\r
+ (void*) CAN1_Handler /* 44 CAN Controller 1 */\r
+};\r
+\r
+/* TEMPORARY PATCH FOR SCB */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+/**\r
+ * \brief This is the code that gets called on processor reset.\r
+ * To initialize the device, and call the main() routine.\r
+ */\r
+void Reset_Handler(void)\r
+{\r
+ uint32_t *pSrc, *pDest;\r
+\r
+ /* Initialize the relocate segment */\r
+ pSrc = &_etext;\r
+ pDest = &_srelocate;\r
+\r
+ if (pSrc != pDest) {\r
+ for (; pDest < &_erelocate;) {\r
+ *pDest++ = *pSrc++;\r
+ }\r
+ }\r
+\r
+ /* Clear the zero segment */\r
+ for (pDest = &_szero; pDest < &_ezero;) {\r
+ *pDest++ = 0;\r
+ }\r
+\r
+ /* Set the vector table base address */\r
+ pSrc = (uint32_t *) & _sfixed;\r
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);\r
+\r
+ if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) {\r
+ SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;\r
+ }\r
+\r
+ /* Initialize the C library */\r
+ __libc_init_array();\r
+\r
+ /* Branch to main function */\r
+ main();\r
+\r
+ /* Infinite loop */\r
+ while (1);\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Provides the low-level initialization functions that called \r
+ * on chip startup.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "system_sam3x.h"\r
+#include "sam3xa.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+/* Clock settings (84MHz) */\r
+#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))\r
+#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \\r
+ | CKGR_PLLAR_MULA(0xdUL) \\r
+ | CKGR_PLLAR_PLLACOUNT(0x3fUL) \\r
+ | CKGR_PLLAR_DIVA(0x1UL))\r
+#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)\r
+\r
+/* Clock Definitions */\r
+#define SYS_UTMIPLL (480000000UL) /* UTMI PLL frequency */\r
+\r
+#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */\r
+\r
+/* FIXME: should be generated by sock */\r
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+/**\r
+ * \brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemFrequency variable.\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* Set FWS according to SYS_BOARD_MCKR configuration */\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(4);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(4);\r
+\r
+ /* Initialize main oscillator */\r
+ if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | \r
+ CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {\r
+ }\r
+ }\r
+\r
+ /* Switch to 3-20MHz Xtal oscillator */\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | \r
+ CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;\r
+\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {\r
+ }\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | \r
+ PMC_MCKR_CSS_MAIN_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ /* Initialize PLLA */\r
+ PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {\r
+ }\r
+\r
+ /* Switch to main clock */\r
+ PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ /* Switch to PLLA */\r
+ PMC->PMC_MCKR = SYS_BOARD_MCKR;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ SystemCoreClock = CHIP_FREQ_CPU_MAX;\r
+}\r
+\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ /* Determine clock frequency according to clock register values */\r
+ switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {\r
+ case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */\r
+ if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_32K;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_SLCK_RC;\r
+ }\r
+ break;\r
+ case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */\r
+ case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {\r
+ SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> \r
+ CKGR_PLLAR_MULA_Pos) + 1U);\r
+ SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> \r
+ CKGR_PLLAR_DIVA_Pos));\r
+ } else {\r
+ SystemCoreClock = SYS_UTMIPLL / 2U;\r
+ }\r
+ break;\r
+ }\r
+\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {\r
+ SystemCoreClock /= 3U;\r
+ } else {\r
+ SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> \r
+ PMC_MCKR_PRES_Pos);\r
+ }\r
+}\r
+\r
+/** \r
+ * Initialize flash.\r
+ */\r
+void system_init_flash(uint32_t ul_clk)\r
+{\r
+ /* Set FWS for embedded Flash access according to operating frequency */\r
+ if (ul_clk < CHIP_FREQ_FWS_0) {\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(0);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(0);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_1) {\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(1);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(1);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_2) {\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(2);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(2);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_3) {\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(3);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(3);\r
+ } else {\r
+ EFC0->EEFC_FMR = EEFC_FMR_FWS(4);\r
+ EFC1->EEFC_FMR = EEFC_FMR_FWS(4);\r
+ }\r
+}\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Provides the low-level initialization functions that called \r
+ * on chip startup.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SYSTEM_SAM3X_H_INCLUDED\r
+#define SYSTEM_SAM3X_H_INCLUDED\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemCoreClock variable.\r
+ */\r
+void SystemInit(void);\r
+\r
+/**\r
+ * @brief Updates the SystemCoreClock with current core Clock \r
+ * retrieved from cpu registers.\r
+ */\r
+void SystemCoreClockUpdate(void);\r
+\r
+/** \r
+ * Initialize flash.\r
+ */\r
+void system_init_flash(uint32_t ul_clk);\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#endif /* SYSTEM_SAM3X_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Commonly used includes, types and macros.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef UTILS_COMPILER_H\r
+#define UTILS_COMPILER_H\r
+\r
+/**\r
+ * \defgroup group_sam_utils Compiler abstraction layer and code utilities\r
+ *\r
+ * Compiler abstraction layer and code utilities for AT91SAM.\r
+ * This module provides various abstraction layers and utilities to make code compatible between different compilers.\r
+ *\r
+ * \{\r
+ */\r
+#include <stddef.h>\r
+\r
+#if (defined __ICCARM__)\r
+# include <intrinsics.h>\r
+#endif\r
+\r
+#include <parts.h>\r
+#include "preprocessor.h"\r
+\r
+#include <io.h>\r
+\r
+//_____ D E C L A R A T I O N S ____________________________________________\r
+\r
+#ifndef __ASSEMBLY__ // Not defined for assembling.\r
+\r
+#include <stdio.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <stdlib.h>\r
+\r
+#ifdef __ICCARM__\r
+/*! \name Compiler Keywords\r
+ *\r
+ * Port of some keywords from GCC to IAR Embedded Workbench.\r
+ */\r
+//! @{\r
+#define __asm__ asm\r
+#define __inline__ inline\r
+#define __volatile__\r
+//! @}\r
+\r
+#endif\r
+\r
+/**\r
+ * \def UNUSED\r
+ * \brief Marking \a v as a unused parameter or value.\r
+ */\r
+#define UNUSED(v) (void)(v)\r
+\r
+/**\r
+ * \def unused\r
+ * \brief Marking \a v as a unused parameter or value.\r
+ */\r
+#define unused(v) do { (void)(v); } while(0)\r
+\r
+/**\r
+ * \def barrier\r
+ * \brief Memory barrier\r
+ */\r
+#define barrier() __DMB()\r
+\r
+/**\r
+ * \brief Emit the compiler pragma \a arg.\r
+ *\r
+ * \param arg The pragma directive as it would appear after \e \#pragma\r
+ * (i.e. not stringified).\r
+ */\r
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)\r
+\r
+/**\r
+ * \def COMPILER_PACK_SET(alignment)\r
+ * \brief Set maximum alignment for subsequent struct and union\r
+ * definitions to \a alignment.\r
+ */\r
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))\r
+\r
+/**\r
+ * \def COMPILER_PACK_RESET()\r
+ * \brief Set default alignment for subsequent struct and union\r
+ * definitions.\r
+ */\r
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())\r
+\r
+\r
+/**\r
+ * \brief Set aligned boundary.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))\r
+#elif (defined __ICCARM__)\r
+# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)\r
+#endif\r
+\r
+/**\r
+ * \brief Set word-aligned boundary.\r
+ */\r
+#if (defined __GNUC__) || defined(__CC_ARM)\r
+#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))\r
+#elif (defined __ICCARM__)\r
+#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)\r
+#endif\r
+\r
+/**\r
+ * \def __always_inline\r
+ * \brief The function should always be inlined.\r
+ *\r
+ * This annotation instructs the compiler to ignore its inlining\r
+ * heuristics and inline the function no matter how big it thinks it\r
+ * becomes.\r
+ */\r
+#if defined(__CC_ARM)\r
+# define __always_inline __forceinline\r
+#elif (defined __GNUC__)\r
+# define __always_inline __attribute__((__always_inline__)) inline\r
+#elif (defined __ICCARM__)\r
+# define __always_inline _Pragma("inline=forced")\r
+#endif\r
+\r
+/*! \brief This macro is used to test fatal errors.\r
+ *\r
+ * The macro tests if the expression is false. If it is, a fatal error is\r
+ * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO\r
+ * is defined, a unit test version of the macro is used, to allow execution\r
+ * of further tests after a false expression.\r
+ *\r
+ * \param expr Expression to evaluate and supposed to be nonzero.\r
+ */\r
+#if defined(_ASSERT_ENABLE_)\r
+# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)\r
+ // Assert() is defined in unit_test/suite.h\r
+# include "unit_test/suite.h"\r
+# else\r
+#undef TEST_SUITE_DEFINE_ASSERT_MACRO\r
+# define Assert(expr) \\r
+ {\\r
+ if (!(expr)) while (true);\\r
+ }\r
+# endif\r
+#else\r
+# define Assert(expr) ((void) 0)\r
+#endif\r
+\r
+/* Define attribute */\r
+#if defined ( __CC_ARM ) /* Keil µVision 4 */\r
+# define WEAK __attribute__ ((weak))\r
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */\r
+# define WEAK __weak\r
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */\r
+# define WEAK __attribute__ ((weak))\r
+#endif\r
+\r
+/* Define NO_INIT attribute */\r
+#if defined ( __CC_ARM )\r
+# define NO_INIT __attribute__((zero_init))\r
+#elif defined ( __ICCARM__ )\r
+# define NO_INIT __no_init\r
+#elif defined ( __GNUC__ )\r
+# define NO_INIT __attribute__((section(".no_init")))\r
+#endif\r
+\r
+#include "interrupt.h"\r
+\r
+/*! \name Usual Types\r
+ */\r
+//! @{\r
+typedef unsigned char Bool; //!< Boolean.\r
+#ifndef __cplusplus\r
+#if !defined(__bool_true_false_are_defined)\r
+typedef unsigned char bool; //!< Boolean.\r
+#endif\r
+#endif\r
+typedef int8_t S8 ; //!< 8-bit signed integer.\r
+typedef uint8_t U8 ; //!< 8-bit unsigned integer.\r
+typedef int16_t S16; //!< 16-bit signed integer.\r
+typedef uint16_t U16; //!< 16-bit unsigned integer.\r
+typedef uint16_t le16_t;\r
+typedef uint16_t be16_t;\r
+typedef int32_t S32; //!< 32-bit signed integer.\r
+typedef uint32_t U32; //!< 32-bit unsigned integer.\r
+typedef uint32_t le32_t;\r
+typedef uint32_t be32_t;\r
+typedef int64_t S64; //!< 64-bit signed integer.\r
+typedef uint64_t U64; //!< 64-bit unsigned integer.\r
+typedef float F32; //!< 32-bit floating-point number.\r
+typedef double F64; //!< 64-bit floating-point number.\r
+typedef uint32_t iram_size_t;\r
+//! @}\r
+\r
+\r
+/*! \name Status Types\r
+ */\r
+//! @{\r
+typedef bool Status_bool_t; //!< Boolean status.\r
+typedef U8 Status_t; //!< 8-bit-coded status.\r
+//! @}\r
+\r
+\r
+/*! \name Aliasing Aggregate Types\r
+ */\r
+//! @{\r
+\r
+//! 16-bit union.\r
+typedef union\r
+{\r
+ S16 s16 ;\r
+ U16 u16 ;\r
+ S8 s8 [2];\r
+ U8 u8 [2];\r
+} Union16;\r
+\r
+//! 32-bit union.\r
+typedef union\r
+{\r
+ S32 s32 ;\r
+ U32 u32 ;\r
+ S16 s16[2];\r
+ U16 u16[2];\r
+ S8 s8 [4];\r
+ U8 u8 [4];\r
+} Union32;\r
+\r
+//! 64-bit union.\r
+typedef union\r
+{\r
+ S64 s64 ;\r
+ U64 u64 ;\r
+ S32 s32[2];\r
+ U32 u32[2];\r
+ S16 s16[4];\r
+ U16 u16[4];\r
+ S8 s8 [8];\r
+ U8 u8 [8];\r
+} Union64;\r
+\r
+//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ S64 *s64ptr;\r
+ U64 *u64ptr;\r
+ S32 *s32ptr;\r
+ U32 *u32ptr;\r
+ S16 *s16ptr;\r
+ U16 *u16ptr;\r
+ S8 *s8ptr ;\r
+ U8 *u8ptr ;\r
+} UnionPtr;\r
+\r
+//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ volatile S64 *s64ptr;\r
+ volatile U64 *u64ptr;\r
+ volatile S32 *s32ptr;\r
+ volatile U32 *u32ptr;\r
+ volatile S16 *s16ptr;\r
+ volatile U16 *u16ptr;\r
+ volatile S8 *s8ptr ;\r
+ volatile U8 *u8ptr ;\r
+} UnionVPtr;\r
+\r
+//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ const S64 *s64ptr;\r
+ const U64 *u64ptr;\r
+ const S32 *s32ptr;\r
+ const U32 *u32ptr;\r
+ const S16 *s16ptr;\r
+ const U16 *u16ptr;\r
+ const S8 *s8ptr ;\r
+ const U8 *u8ptr ;\r
+} UnionCPtr;\r
+\r
+//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ const volatile S64 *s64ptr;\r
+ const volatile U64 *u64ptr;\r
+ const volatile S32 *s32ptr;\r
+ const volatile U32 *u32ptr;\r
+ const volatile S16 *s16ptr;\r
+ const volatile U16 *u16ptr;\r
+ const volatile S8 *s8ptr ;\r
+ const volatile U8 *u8ptr ;\r
+} UnionCVPtr;\r
+\r
+//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ S64 *s64ptr;\r
+ U64 *u64ptr;\r
+ S32 *s32ptr;\r
+ U32 *u32ptr;\r
+ S16 *s16ptr;\r
+ U16 *u16ptr;\r
+ S8 *s8ptr ;\r
+ U8 *u8ptr ;\r
+} StructPtr;\r
+\r
+//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ volatile S64 *s64ptr;\r
+ volatile U64 *u64ptr;\r
+ volatile S32 *s32ptr;\r
+ volatile U32 *u32ptr;\r
+ volatile S16 *s16ptr;\r
+ volatile U16 *u16ptr;\r
+ volatile S8 *s8ptr ;\r
+ volatile U8 *u8ptr ;\r
+} StructVPtr;\r
+\r
+//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ const S64 *s64ptr;\r
+ const U64 *u64ptr;\r
+ const S32 *s32ptr;\r
+ const U32 *u32ptr;\r
+ const S16 *s16ptr;\r
+ const U16 *u16ptr;\r
+ const S8 *s8ptr ;\r
+ const U8 *u8ptr ;\r
+} StructCPtr;\r
+\r
+//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ const volatile S64 *s64ptr;\r
+ const volatile U64 *u64ptr;\r
+ const volatile S32 *s32ptr;\r
+ const volatile U32 *u32ptr;\r
+ const volatile S16 *s16ptr;\r
+ const volatile U16 *u16ptr;\r
+ const volatile S8 *s8ptr ;\r
+ const volatile U8 *u8ptr ;\r
+} StructCVPtr;\r
+\r
+//! @}\r
+\r
+#endif // #ifndef __ASSEMBLY__\r
+\r
+/*! \name Usual Constants\r
+ */\r
+//! @{\r
+#define DISABLE 0\r
+#define ENABLE 1\r
+#ifndef __cplusplus\r
+#if !defined(__bool_true_false_are_defined)\r
+#define false 0\r
+#define true 1\r
+#endif\r
+#endif\r
+#define PASS 0\r
+#define FAIL 1\r
+#define LOW 0\r
+#define HIGH 1\r
+//! @}\r
+\r
+\r
+#ifndef __ASSEMBLY__ // not for assembling.\r
+\r
+//! \name Optimization Control\r
+//@{\r
+\r
+/**\r
+ * \def likely(exp)\r
+ * \brief The expression \a exp is likely to be true\r
+ */\r
+#ifndef likely\r
+# define likely(exp) (exp)\r
+#endif\r
+\r
+/**\r
+ * \def unlikely(exp)\r
+ * \brief The expression \a exp is unlikely to be true\r
+ */\r
+#ifndef unlikely\r
+# define unlikely(exp) (exp)\r
+#endif\r
+\r
+/**\r
+ * \def is_constant(exp)\r
+ * \brief Determine if an expression evaluates to a constant value.\r
+ *\r
+ * \param exp Any expression\r
+ *\r
+ * \return true if \a exp is constant, false otherwise.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define is_constant(exp) __builtin_constant_p(exp)\r
+#else\r
+# define is_constant(exp) (0)\r
+#endif\r
+\r
+//! @}\r
+\r
+/*! \name Bit-Field Handling\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reads the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read bits from.\r
+ * \param mask Bit-mask indicating bits to read.\r
+ *\r
+ * \return Read bits.\r
+ */\r
+#define Rd_bits( value, mask) ((value) & (mask))\r
+\r
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue to write bits to.\r
+ * \param mask Bit-mask indicating bits to write.\r
+ * \param bits Bits to write.\r
+ *\r
+ * \return Resulting value with written bits.\r
+ */\r
+#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\\r
+ ((bits ) & (mask)))\r
+\r
+/*! \brief Tests the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value of which to test bits.\r
+ * \param mask Bit-mask indicating bits to test.\r
+ *\r
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.\r
+ */\r
+#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)\r
+\r
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to clear bits.\r
+ * \param mask Bit-mask indicating bits to clear.\r
+ *\r
+ * \return Resulting value with cleared bits.\r
+ */\r
+#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))\r
+\r
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to set bits.\r
+ * \param mask Bit-mask indicating bits to set.\r
+ *\r
+ * \return Resulting value with set bits.\r
+ */\r
+#define Set_bits(lvalue, mask) ((lvalue) |= (mask))\r
+\r
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to toggle bits.\r
+ * \param mask Bit-mask indicating bits to toggle.\r
+ *\r
+ * \return Resulting value with toggled bits.\r
+ */\r
+#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))\r
+\r
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read a bit-field from.\r
+ * \param mask Bit-mask indicating the bit-field to read.\r
+ *\r
+ * \return Read bit-field.\r
+ */\r
+#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))\r
+\r
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue to write a bit-field to.\r
+ * \param mask Bit-mask indicating the bit-field to write.\r
+ * \param bitfield Bit-field to write.\r
+ *\r
+ * \return Resulting value with written bit-field.\r
+ */\r
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Zero-Bit Counting\r
+ *\r
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when\r
+ * applied to constant expressions (values known at compile time), so they are\r
+ * more optimized than the use of the corresponding assembly instructions and\r
+ * they can be used as constant expressions e.g. to initialize objects having\r
+ * static storage duration, and like the corresponding assembly instructions\r
+ * when applied to non-constant expressions (values unknown at compile time), so\r
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz\r
+ * ensure a possible and optimized behavior for both constant and non-constant\r
+ * expressions.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the leading zero bits.\r
+ *\r
+ * \return The count of leading zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define clz(u) __builtin_clz(u)\r
+#elif (defined __ICCARM__)\r
+# define clz(u) __CLZ(u)\r
+#else\r
+# define clz(u) (((u) == 0) ? 32 : \\r
+ ((u) & (1ul << 31)) ? 0 : \\r
+ ((u) & (1ul << 30)) ? 1 : \\r
+ ((u) & (1ul << 29)) ? 2 : \\r
+ ((u) & (1ul << 28)) ? 3 : \\r
+ ((u) & (1ul << 27)) ? 4 : \\r
+ ((u) & (1ul << 26)) ? 5 : \\r
+ ((u) & (1ul << 25)) ? 6 : \\r
+ ((u) & (1ul << 24)) ? 7 : \\r
+ ((u) & (1ul << 23)) ? 8 : \\r
+ ((u) & (1ul << 22)) ? 9 : \\r
+ ((u) & (1ul << 21)) ? 10 : \\r
+ ((u) & (1ul << 20)) ? 11 : \\r
+ ((u) & (1ul << 19)) ? 12 : \\r
+ ((u) & (1ul << 18)) ? 13 : \\r
+ ((u) & (1ul << 17)) ? 14 : \\r
+ ((u) & (1ul << 16)) ? 15 : \\r
+ ((u) & (1ul << 15)) ? 16 : \\r
+ ((u) & (1ul << 14)) ? 17 : \\r
+ ((u) & (1ul << 13)) ? 18 : \\r
+ ((u) & (1ul << 12)) ? 19 : \\r
+ ((u) & (1ul << 11)) ? 20 : \\r
+ ((u) & (1ul << 10)) ? 21 : \\r
+ ((u) & (1ul << 9)) ? 22 : \\r
+ ((u) & (1ul << 8)) ? 23 : \\r
+ ((u) & (1ul << 7)) ? 24 : \\r
+ ((u) & (1ul << 6)) ? 25 : \\r
+ ((u) & (1ul << 5)) ? 26 : \\r
+ ((u) & (1ul << 4)) ? 27 : \\r
+ ((u) & (1ul << 3)) ? 28 : \\r
+ ((u) & (1ul << 2)) ? 29 : \\r
+ ((u) & (1ul << 1)) ? 30 : \\r
+ 31)\r
+#endif\r
+\r
+/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the trailing zero bits.\r
+ *\r
+ * \return The count of trailing zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define ctz(u) __builtin_ctz(u)\r
+#else\r
+# define ctz(u) ((u) & (1ul << 0) ? 0 : \\r
+ (u) & (1ul << 1) ? 1 : \\r
+ (u) & (1ul << 2) ? 2 : \\r
+ (u) & (1ul << 3) ? 3 : \\r
+ (u) & (1ul << 4) ? 4 : \\r
+ (u) & (1ul << 5) ? 5 : \\r
+ (u) & (1ul << 6) ? 6 : \\r
+ (u) & (1ul << 7) ? 7 : \\r
+ (u) & (1ul << 8) ? 8 : \\r
+ (u) & (1ul << 9) ? 9 : \\r
+ (u) & (1ul << 10) ? 10 : \\r
+ (u) & (1ul << 11) ? 11 : \\r
+ (u) & (1ul << 12) ? 12 : \\r
+ (u) & (1ul << 13) ? 13 : \\r
+ (u) & (1ul << 14) ? 14 : \\r
+ (u) & (1ul << 15) ? 15 : \\r
+ (u) & (1ul << 16) ? 16 : \\r
+ (u) & (1ul << 17) ? 17 : \\r
+ (u) & (1ul << 18) ? 18 : \\r
+ (u) & (1ul << 19) ? 19 : \\r
+ (u) & (1ul << 20) ? 20 : \\r
+ (u) & (1ul << 21) ? 21 : \\r
+ (u) & (1ul << 22) ? 22 : \\r
+ (u) & (1ul << 23) ? 23 : \\r
+ (u) & (1ul << 24) ? 24 : \\r
+ (u) & (1ul << 25) ? 25 : \\r
+ (u) & (1ul << 26) ? 26 : \\r
+ (u) & (1ul << 27) ? 27 : \\r
+ (u) & (1ul << 28) ? 28 : \\r
+ (u) & (1ul << 29) ? 29 : \\r
+ (u) & (1ul << 30) ? 30 : \\r
+ (u) & (1ul << 31) ? 31 : \\r
+ 32)\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Bit Reversing\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reverses the bits of \a u8.\r
+ *\r
+ * \param u8 U8 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u8 with reversed bits.\r
+ */\r
+#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))\r
+\r
+/*! \brief Reverses the bits of \a u16.\r
+ *\r
+ * \param u16 U16 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u16 with reversed bits.\r
+ */\r
+#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16))\r
+\r
+/*! \brief Reverses the bits of \a u32.\r
+ *\r
+ * \param u32 U32 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u32 with reversed bits.\r
+ */\r
+#define bit_reverse32(u32) __RBIT(u32)\r
+\r
+/*! \brief Reverses the bits of \a u64.\r
+ *\r
+ * \param u64 U64 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u64 with reversed bits.\r
+ */\r
+#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\\r
+ ((U64)bit_reverse32((U64)(u64)) << 32)))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Alignment\r
+ */\r
+//! @{\r
+\r
+/*! \brief Tests alignment of the number \a val with the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.\r
+ */\r
+#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) )\r
+\r
+/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Alignment of the number \a val with respect to the \a n boundary.\r
+ */\r
+#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) )\r
+\r
+/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.\r
+ *\r
+ * \param lval Input/output lvalue.\r
+ * \param n Boundary.\r
+ * \param alg Alignment.\r
+ *\r
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.\r
+ */\r
+#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )\r
+\r
+/*! \brief Aligns the number \a val with the upper \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.\r
+ */\r
+#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1))\r
+\r
+/*! \brief Aligns the number \a val with the lower \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.\r
+ */\r
+#define Align_down(val, n ) ( (val) & ~((n) - 1))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Mathematics\r
+ *\r
+ * The same considerations as for clz and ctz apply here but GCC does not\r
+ * provide built-in functions to access the assembly instructions abs, min and\r
+ * max and it does not produce them by itself in most cases, so two sets of\r
+ * macros are defined here:\r
+ * - Abs, Min and Max to apply to constant expressions (values known at\r
+ * compile time);\r
+ * - abs, min and max to apply to non-constant expressions (values unknown at\r
+ * compile time), abs is found in stdlib.h.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Takes the absolute value of \a a.\r
+ *\r
+ * \param a Input value.\r
+ *\r
+ * \return Absolute value of \a a.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Abs(a) (((a) < 0 ) ? -(a) : (a))\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Min(a, b) (((a) < (b)) ? (a) : (b))\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Max(a, b) (((a) > (b)) ? (a) : (b))\r
+\r
+// abs() is already defined by stdlib.h\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define min(a, b) Min(a, b)\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define max(a, b) Max(a, b)\r
+\r
+//! @}\r
+\r
+\r
+/*! \brief Calls the routine at address \a addr.\r
+ *\r
+ * It generates a long call opcode.\r
+ *\r
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if\r
+ * it is invoked from the CPU supervisor mode.\r
+ *\r
+ * \param addr Address of the routine to call.\r
+ *\r
+ * \note It may be used as a long jump opcode in some special cases.\r
+ */\r
+#define Long_call(addr) ((*(void (*)(void))(addr))())\r
+\r
+\r
+/*! \name MCU Endianism Handling\r
+ * ARM is MCU little endianism.\r
+ */\r
+//! @{\r
+#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.\r
+#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.\r
+\r
+#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.\r
+#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.\r
+#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.\r
+#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.\r
+#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+ \r
+#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.\r
+#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.\r
+#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.\r
+#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.\r
+#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.\r
+#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.\r
+#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.\r
+#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.\r
+#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.\r
+#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.\r
+#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.\r
+#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.\r
+#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.\r
+#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.\r
+#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.\r
+#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.\r
+#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.\r
+#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.\r
+#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.\r
+#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.\r
+#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.\r
+#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.\r
+#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.\r
+#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.\r
+#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.\r
+#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.\r
+\r
+#define BE16(x) Swap16(x)\r
+#define LE16(x) (x)\r
+\r
+#define le16_to_cpu(x) (x)\r
+#define cpu_to_le16(x) (x)\r
+#define LE16_TO_CPU(x) (x)\r
+#define CPU_TO_LE16(x) (x)\r
+\r
+#define be16_to_cpu(x) Swap16(x)\r
+#define cpu_to_be16(x) Swap16(x)\r
+#define BE16_TO_CPU(x) Swap16(x)\r
+#define CPU_TO_BE16(x) Swap16(x)\r
+\r
+#define le32_to_cpu(x) (x)\r
+#define cpu_to_le32(x) (x)\r
+#define LE32_TO_CPU(x) (x)\r
+#define CPU_TO_LE32(x) (x)\r
+\r
+#define be32_to_cpu(x) swap32(x)\r
+#define cpu_to_be32(x) swap32(x)\r
+#define BE32_TO_CPU(x) swap32(x)\r
+#define CPU_TO_BE32(x) swap32(x)\r
+//! @}\r
+\r
+\r
+/*! \name Endianism Conversion\r
+ *\r
+ * The same considerations as for clz and ctz apply here but GCC's\r
+ * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when\r
+ * applied to constant expressions, so two sets of macros are defined here:\r
+ * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known\r
+ * at compile time);\r
+ * - swap16, swap32 and swap64 to apply to non-constant expressions (values\r
+ * unknown at compile time).\r
+ */\r
+//! @{\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\\r
+ ((U16)(u16) << 8)))\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\\r
+ ((U32)Swap16((U32)(u32)) << 16)))\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\\r
+ ((U64)Swap32((U64)(u64)) << 32)))\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define swap16(u16) Swap16(u16)\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32)))\r
+#else\r
+# define swap32(u32) Swap32(u32)\r
+#endif\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64)))\r
+#else\r
+# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\\r
+ ((U64)swap32((U64)(u64)) << 32)))\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Target Abstraction\r
+ */\r
+//! @{\r
+\r
+#define _GLOBEXT_ extern //!< extern storage-class specifier.\r
+#define _CONST_TYPE_ const //!< const type qualifier.\r
+#define _MEM_TYPE_SLOW_ //!< Slow memory type.\r
+#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.\r
+#define _MEM_TYPE_FAST_ //!< Fast memory type.\r
+\r
+typedef U8 Byte; //!< 8-bit unsigned integer.\r
+\r
+#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.\r
+#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.\r
+#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.\r
+#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.\r
+\r
+#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.\r
+\r
+//! @}\r
+\r
+/**\r
+ * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using\r
+ * integer arithmetic.\r
+ *\r
+ * \param a An integer\r
+ * \param b Another integer\r
+ *\r
+ * \return (\a a / \a b) rounded up to the nearest integer.\r
+ */\r
+#define div_ceil(a, b) (((a) + (b) - 1) / (b))\r
+\r
+#endif // #ifndef __ASSEMBLY__\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif /* UTILS_COMPILER_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Arch file for SAM.\r
+ *\r
+ * This file defines common SAM series.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM_IO_\r
+#define _SAM_IO_\r
+\r
+/* SAM3 family */\r
+\r
+/* SAM3S series */\r
+#if (SAM3S)\r
+# if (SAM3S8 || SAM3SD8)\r
+# include "sam3s8.h"\r
+# else\r
+# include "sam3s.h"\r
+# endif\r
+#endif\r
+\r
+/* SAM3U series */\r
+#if (SAM3U)\r
+# include "sam3u.h"\r
+#endif\r
+\r
+/* SAM3N series */\r
+#if (SAM3N)\r
+# include "sam3n.h"\r
+#endif\r
+\r
+/* SAM3XA series */\r
+#if (SAM3XA)\r
+# include "sam3xa.h"\r
+#endif\r
+\r
+/* SAM4S series */\r
+#if (SAM4S)\r
+# include "sam4s.h"\r
+#endif\r
+\r
+#endif /* _SAM_IO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Flash Linker script for SAM.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ * \r
+ * 1. Redistributions of source code must retain the above copyright notice, \r
+ * this list of conditions and the following disclaimer.\r
+ * \r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * \r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ * \r
+ * 4. This software may only be redistributed and used in connection with an \r
+ * Atmel microcontroller product.\r
+ * \r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")\r
+OUTPUT_ARCH(arm)\r
+SEARCH_DIR(.)\r
+\r
+/* Memory Spaces Definitions */\r
+MEMORY\r
+{\r
+ rom (rx) : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */\r
+ sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */\r
+ sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */\r
+ ram (rwx) : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */\r
+/* ram (rwx) : ORIGIN = ORIGIN( sram1 )-LENGTH( sram0 ), LENGTH = LENGTH( sram0 )+LENGTH( sram1 ) */ /* sram, 96K */\r
+}\r
+\r
+/* The stack size used by the application. NOTE: you need to adjust */\r
+STACK_SIZE = 0x2000;\r
+\r
+/* Section Definitions */ \r
+SECTIONS \r
+{ \r
+ .text : \r
+ { \r
+ . = ALIGN(4);\r
+ _sfixed = .;\r
+ KEEP(*(.vectors .vectors.*))\r
+ *(.text .text.* .gnu.linkonce.t.*) \r
+ *(.glue_7t) *(.glue_7) \r
+ *(.rodata .rodata* .gnu.linkonce.r.*) \r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+\r
+ /* Support C constructors, and C destructors in both user code\r
+ and the C library. This also provides support for C++ code. */\r
+ . = ALIGN(4);\r
+ KEEP(*(.init))\r
+ . = ALIGN(4);\r
+ __preinit_array_start = .;\r
+ KEEP (*(.preinit_array))\r
+ __preinit_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ __init_array_start = .;\r
+ KEEP (*(SORT(.init_array.*)))\r
+ KEEP (*(.init_array))\r
+ __init_array_end = .;\r
+\r
+ . = ALIGN(0x4);\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*crtend.o(.ctors))\r
+\r
+ . = ALIGN(4);\r
+ KEEP(*(.fini))\r
+\r
+ . = ALIGN(4);\r
+ __fini_array_start = .;\r
+ KEEP (*(.fini_array))\r
+ KEEP (*(SORT(.fini_array.*)))\r
+ __fini_array_end = .;\r
+\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*crtend.o(.dtors))\r
+\r
+ . = ALIGN(4);\r
+ _efixed = .; /* End of text section */\r
+ } > rom\r
+\r
+ /* .ARM.exidx is sorted, so has to go in its own output section. */\r
+ PROVIDE_HIDDEN (__exidx_start = .);\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > rom\r
+ PROVIDE_HIDDEN (__exidx_end = .);\r
+\r
+ . = ALIGN(4); \r
+ _etext = .;\r
+\r
+ .relocate : AT (_etext)\r
+ {\r
+ . = ALIGN(4);\r
+ _srelocate = .;\r
+ *(.ramfunc .ramfunc.*);\r
+ *(.data .data.*);\r
+ . = ALIGN(4);\r
+ _erelocate = .;\r
+ } > ram\r
+\r
+ /* .bss section which is used for uninitialized data */ \r
+ .bss (NOLOAD) :\r
+ { \r
+ . = ALIGN(4);\r
+ _sbss = . ;\r
+ _szero = .;\r
+ *(.bss .bss.*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ _ebss = . ;\r
+ _ezero = .;\r
+ } > ram\r
+\r
+ /* stack section */\r
+ .stack (NOLOAD):\r
+ {\r
+ . = ALIGN(8);\r
+ _sstack = .;\r
+ . = . + STACK_SIZE;\r
+ . = ALIGN(8);\r
+ _estack = .;\r
+ } > ram\r
+\r
+ . = ALIGN(4); \r
+ _end = . ; \r
+}\r
--- /dev/null
+# List of available make goals:\r
+#\r
+# all Default target, builds the project\r
+# clean Clean up the project\r
+# rebuild Rebuild the project\r
+# debug_flash Builds the project and debug in flash\r
+# debug_sram Builds the project and debug in sram\r
+#\r
+# doc Build the documentation\r
+# cleandoc Clean up the documentation\r
+# rebuilddoc Rebuild the documentation\r
+#\r
+# \file\r
+#\r
+# Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+#\r
+# \asf_license_start\r
+#\r
+# \page License\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# 1. Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the following disclaimer.\r
+#\r
+# 2. Redistributions in binary form must reproduce the above copyright notice,\r
+# this list of conditions and the following disclaimer in the documentation\r
+# and/or other materials provided with the distribution.\r
+#\r
+# 3. The name of Atmel may not be used to endorse or promote products derived\r
+# from this software without specific prior written permission.\r
+#\r
+# 4. This software may only be redistributed and used in connection with an\r
+# Atmel microcontroller product.\r
+#\r
+# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+# POSSIBILITY OF SUCH DAMAGE.\r
+#\r
+# \asf_license_stop\r
+#\r
+\r
+# Include the config.mk file from the current working path, e.g., where the\r
+# user called make.\r
+include config.mk\r
+\r
+# Tool to use to generate documentation from the source code\r
+DOCGEN ?= doxygen\r
+\r
+# Look for source files relative to the top-level source directory\r
+VPATH := $(PRJ_PATH)\r
+\r
+# Output target file\r
+project_type := $(PROJECT_TYPE)\r
+\r
+# Output target file\r
+ifeq ($(project_type),flash)\r
+target := $(TARGET_FLASH)\r
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH)\r
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)\r
+else\r
+target := $(TARGET_SRAM)\r
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM)\r
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)\r
+endif\r
+\r
+# Output project name (target name minus suffix)\r
+project := $(basename $(target))\r
+\r
+# Output target file (typically ELF or static library)\r
+ifeq ($(suffix $(target)),.a)\r
+target_type := lib\r
+else\r
+ifeq ($(suffix $(target)),.elf)\r
+target_type := elf\r
+else\r
+$(error "Target type $(target_type) is not supported")\r
+endif\r
+endif\r
+\r
+# Allow override of operating system detection. The user can add OS=Linux or\r
+# OS=Windows on the command line to explicit set the host OS.\r
+#\r
+# This allows to work around broken uname utility on certain systems.\r
+ifdef OS\r
+ ifeq ($(strip $(OS)), Linux)\r
+ os_type := Linux\r
+ endif\r
+ ifeq (Windows,$(findstring Windows,$(OS)))\r
+ os_type := windows32_64\r
+ endif\r
+endif\r
+\r
+#os_type ?= $(strip $(shell uname))\r
+\r
+#ifeq ($(os_type),windows32)\r
+#os := Windows\r
+#else\r
+#ifeq ($(os_type),windows64)\r
+#os := Windows\r
+#else\r
+#ifeq ($(os_type),)\r
+#os := Windows\r
+#else\r
+## Default to Linux style operating system. Both Cygwin and mingw are fully\r
+## compatible (for this Makefile) with Linux.\r
+#os := Linux\r
+#endif\r
+#endif\r
+#endif\r
+\r
+ifeq ($(os_type),windows32_64)\r
+os := Windows\r
+else\r
+ifeq ($(os_type),Linux)\r
+os := Linux\r
+else\r
+os := Linux\r
+endif\r
+endif\r
+\r
+# Output documentation directory and configuration file.\r
+docdir := ../doxygen/html\r
+doccfg := ../doxygen/doxyfile.doxygen\r
+\r
+CROSS ?= arm-none-eabi-\r
+AR := $(CROSS)ar\r
+AS := $(CROSS)as\r
+CC := $(CROSS)gcc\r
+CPP := $(CROSS)gcc -E\r
+CXX := $(CROSS)g++\r
+LD := $(CROSS)g++\r
+NM := $(CROSS)nm\r
+OBJCOPY := $(CROSS)objcopy\r
+OBJDUMP := $(CROSS)objdump\r
+SIZE := $(CROSS)size\r
+GDB := $(CROSS)gdb\r
+\r
+RM := cs-rm -f\r
+ifeq ($(os),Windows)\r
+#RMDIR := rmdir /S /Q\r
+RMDIR := cs-rm -rf\r
+else\r
+RMDIR := rmdir -p --ignore-fail-on-non-empty\r
+endif\r
+\r
+# Strings for beautifying output\r
+MSG_CLEAN_FILES = "RM *.o *.d"\r
+MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))"\r
+MSG_CLEAN_DOC = "RMDIR $(docdir)"\r
+MSG_MKDIR = "MKDIR $(dir $@)"\r
+\r
+MSG_INFO = "INFO "\r
+\r
+MSG_ARCHIVING = "AR $@"\r
+MSG_ASSEMBLING = "AS $@"\r
+MSG_BINARY_IMAGE = "OBJCOPY $@"\r
+MSG_COMPILING = "CC $@"\r
+MSG_COMPILING_CXX = "CXX $@"\r
+MSG_EXTENDED_LISTING = "OBJDUMP $@"\r
+MSG_IHEX_IMAGE = "OBJCOPY $@"\r
+MSG_LINKING = "LN $@"\r
+MSG_PREPROCESSING = "CPP $@"\r
+MSG_SIZE = "SIZE $@"\r
+MSG_SYMBOL_TABLE = "NM $@"\r
+\r
+MSG_GENERATING_DOC = "DOXYGEN $(docdir)"\r
+\r
+# Don't use make's built-in rules and variables\r
+MAKEFLAGS += -rR\r
+\r
+# Don't print 'Entering directory ...'\r
+MAKEFLAGS += --no-print-directory\r
+\r
+# Function for reversing the order of a list\r
+reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))\r
+\r
+# Hide command output by default, but allow the user to override this\r
+# by adding V=1 on the command line.\r
+#\r
+# This is inspired by the Kbuild system used by the Linux kernel.\r
+ifdef V\r
+ ifeq ("$(origin V)", "command line")\r
+ VERBOSE = $(V)\r
+ endif\r
+endif\r
+ifndef VERBOSE\r
+ VERBOSE = 0\r
+endif\r
+\r
+ifeq ($(VERBOSE), 1)\r
+ Q =\r
+else\r
+# Q = @\r
+ Q =\r
+endif\r
+\r
+arflags-gnu-y := $(ARFLAGS)\r
+asflags-gnu-y := $(ASFLAGS)\r
+cflags-gnu-y := $(CFLAGS)\r
+cxxflags-gnu-y := $(CXXFLAGS)\r
+cppflags-gnu-y := $(CPPFLAGS)\r
+cpuflags-gnu-y :=\r
+dbgflags-gnu-y := $(DBGFLAGS)\r
+libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB))\r
+ldflags-gnu-y := $(LDFLAGS)\r
+flashflags-gnu-y :=\r
+clean-files :=\r
+clean-dirs :=\r
+\r
+clean-files += $(wildcard $(target) $(project).map)\r
+clean-files += $(wildcard $(project).hex $(project).bin)\r
+clean-files += $(wildcard $(project).lss $(project).sym)\r
+clean-files += $(wildcard $(build))\r
+\r
+# Use pipes instead of temporary files for communication between processes\r
+cflags-gnu-y += -pipe\r
+asflags-gnu-y += -pipe\r
+ldflags-gnu-y += -pipe\r
+\r
+# Archiver flags.\r
+arflags-gnu-y += rcs\r
+\r
+# Always enable warnings. And be very careful about implicit\r
+# declarations.\r
+cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes\r
+cflags-gnu-y += -Werror-implicit-function-declaration\r
+cxxflags-gnu-y += -Wall\r
+# IAR doesn't allow arithmetic on void pointers, so warn about that.\r
+cflags-gnu-y += -Wpointer-arith\r
+cxxflags-gnu-y += -Wpointer-arith\r
+\r
+# Preprocessor flags.\r
+cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))\r
+asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')\r
+\r
+# CPU specific flags.\r
+cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__\r
+\r
+# Dependency file flags.\r
+depflags = -MD -MP -MQ $@\r
+\r
+# Debug specific flags.\r
+ifdef BUILD_DEBUG_LEVEL\r
+dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL)\r
+else\r
+dbgflags-gnu-y += -g3\r
+endif\r
+\r
+# Optimization specific flags.\r
+ifdef BUILD_OPTIMIZATION\r
+optflags-gnu-y = -O$(BUILD_OPTIMIZATION)\r
+else\r
+optflags-gnu-y = $(OPTIMIZATION)\r
+endif\r
+\r
+# Always preprocess assembler files.\r
+asflags-gnu-y += -x assembler-with-cpp\r
+# Compile C files using the GNU99 standard.\r
+cflags-gnu-y += -std=gnu99\r
+# Compile C++ files using the GNU++98 standard.\r
+cxxflags-gnu-y += -std=gnu++98\r
+\r
+\r
+# Separate each function and data into its own separate section to allow\r
+# garbage collection of unused sections.\r
+cflags-gnu-y += -ffunction-sections -fdata-sections\r
+cxxflags-gnu-y += -ffunction-sections -fdata-sections\r
+\r
+# Various cflags.\r
+cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int\r
+cflags-gnu-y += -Wmain -Wparentheses\r
+cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused\r
+cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef\r
+cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings\r
+cflags-gnu-y += -Wsign-compare -Waggregate-return \r
+cflags-gnu-y += -Wmissing-declarations\r
+cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations\r
+cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long\r
+cflags-gnu-y += -Wunreachable-code\r
+cflags-gnu-y += -Wcast-align\r
+cflags-gnu-y += --param max-inline-insns-single=500\r
+\r
+# To reduce application size use only integer printf function.\r
+cflags-gnu-y += -Dprintf=iprintf\r
+\r
+# Garbage collect unreferred sections when linking.\r
+ldflags-gnu-y += -Wl,--gc-sections\r
+\r
+# Use the linker script if provided by the project.\r
+ifneq ($(strip $(linker_script)),)\r
+ldflags-gnu-y += -Wl,-T $(linker_script)\r
+endif\r
+\r
+# Output a link map file and a cross reference table\r
+ldflags-gnu-y += -Wl,-Map=$(project).map,--cref\r
+\r
+# Add library search paths relative to the top level directory.\r
+ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))\r
+\r
+a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__\r
+c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)\r
+cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)\r
+l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)\r
+ar_flags = $(arflags-gnu-y)\r
+\r
+# Source files list and part informations must already be included before\r
+# running this makefile\r
+\r
+# If a custom build directory is specified, use it -- force trailing / in directory name.\r
+ifdef BUILD_DIR\r
+ build-dir := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)\r
+else\r
+ build-dir =\r
+endif\r
+\r
+# Create object files list from source files list.\r
+obj-y := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))\r
+# Create dependency files list from source files list.\r
+dep-files := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))\r
+\r
+clean-files += $(wildcard $(obj-y))\r
+clean-files += $(dep-files)\r
+\r
+clean-dirs += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))\r
+\r
+.PHONY: all\r
+\r
+# Default target.\r
+.PHONY: all\r
+ifeq ($(project_type),all)\r
+all:\r
+ $(MAKE) all PROJECT_TYPE=flash\r
+ $(MAKE) all PROJECT_TYPE=sram\r
+else\r
+ifeq ($(target_type),lib)\r
+all: $(target) $(project).lss $(project).sym\r
+else\r
+ifeq ($(target_type),elf)\r
+all: $(target) $(project).lss $(project).sym $(project).hex $(project).bin\r
+endif\r
+endif\r
+endif\r
+\r
+# Default target.\r
+.PHONY: os\r
+os:\r
+ @echo OS '$(OS)'\r
+ @echo os type '$(os_type)'\r
+ @echo os '$(os)'\r
+ @echo '$(findstring Windows,$(OS))'\r
+\r
+# Clean up the project.\r
+.PHONY: clean\r
+clean:\r
+ @$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))\r
+ $(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)\r
+ @$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))\r
+# Remove created directories, and make sure we only remove existing\r
+# directories, since recursive rmdir might help us a bit on the way.\r
+ifeq ($(os),Windows)\r
+ $(Q)$(if $(strip $(clean-dirs)), \\r
+ $(RMDIR) $(strip $(subst /,\,$(clean-dirs))))\r
+else\r
+ $(Q)$(if $(strip $(clean-dirs)), \\r
+ for directory in $(strip $(clean-dirs)); do \\r
+ if [ -d "$$directory" ]; then \\r
+ $(RMDIR) $$directory; \\r
+ fi \\r
+ done \\r
+ )\r
+endif\r
+\r
+# Rebuild the project.\r
+.PHONY: rebuild\r
+rebuild: clean all\r
+\r
+# Debug the project in flash.\r
+.PHONY: debug_flash\r
+debug_flash: all\r
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH)\r
+\r
+# Debug the project in sram.\r
+.PHONY: debug_sram\r
+debug_sram: all\r
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM)\r
+\r
+.PHONY: objfiles\r
+objfiles: $(obj-y)\r
+\r
+# Create object files from C source files.\r
+$(build-dir)%.o: %.c $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk\r
+ @echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ -mkdir $(subst /,\,$(dir $@))\r
+else\r
+ -mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_COMPILING)\r
+ $(Q)$(CC) $(c_flags) -c $< -o $@\r
+\r
+# Create object files from C++ source files.\r
+$(build-dir)%.o: %.cpp $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk\r
+ @echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ -mkdir $(subst /,\,$(dir $@))\r
+else\r
+ -mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_COMPILING_CXX)\r
+ $(Q)$(CXX) $(cxx_flags) -c $< -o $@\r
+\r
+# Preprocess and assemble: create object files from assembler source files.\r
+$(build-dir)%.o: %.S $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk\r
+ @echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ -mkdir $(subst /,\,$(dir $@))\r
+else\r
+ -mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_ASSEMBLING)\r
+ $(Q)$(CC) $(a_flags) -c $< -o $@\r
+\r
+# Include all dependency files to add depedency to all header files in use.\r
+include $(dep-files)\r
+\r
+ifeq ($(target_type),lib)\r
+# Archive object files into an archive\r
+$(target): $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk $(obj-y)\r
+ @echo $(MSG_ARCHIVING)\r
+ $(Q)$(AR) $(ar_flags) $@ $(obj-y)\r
+ @echo $(MSG_SIZE)\r
+ $(Q)$(SIZE) -Bxt $@\r
+else\r
+ifeq ($(target_type),elf)\r
+# Link the object files into an ELF file. Also make sure the target is rebuilt\r
+# if the common Makefile.in or project config.mk is changed.\r
+$(target): $(linker_script) $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk $(obj-y)\r
+ @echo $(MSG_LINKING)\r
+ @echo $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@\r
+ $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@\r
+ @echo $(MSG_SIZE)\r
+ $(Q)$(SIZE) -Ax $@\r
+ $(Q)$(SIZE) -Bx $@\r
+endif\r
+endif\r
+\r
+# Create extended function listing from target output file.\r
+%.lss: $(target)\r
+ @echo $(MSG_EXTENDED_LISTING)\r
+ $(Q)$(OBJDUMP) -h -S $< > $@\r
+\r
+# Create symbol table from target output file.\r
+%.sym: $(target)\r
+ @echo $(MSG_SYMBOL_TABLE)\r
+ $(Q)$(NM) -n $< > $@\r
+\r
+# Create Intel HEX image from ELF output file.\r
+%.hex: $(target)\r
+ @echo $(MSG_IHEX_IMAGE)\r
+ $(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y) $< $@\r
+\r
+# Create binary image from ELF output file.\r
+%.bin: $(target)\r
+ @echo $(MSG_BINARY_IMAGE)\r
+ $(Q)$(OBJCOPY) -O binary $< $@\r
+\r
+# Provide information about the detected host operating system.\r
+.SECONDARY: info-os\r
+info-os:\r
+ @echo $(MSG_INFO)$(os) build host detected\r
+\r
+# Build Doxygen generated documentation.\r
+.PHONY: doc\r
+doc:\r
+ @echo $(MSG_GENERATING_DOC)\r
+ $(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))\r
+\r
+# Clean Doxygen generated documentation.\r
+.PHONY: cleandoc\r
+cleandoc:\r
+ @$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))\r
+ $(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))\r
+\r
+# Rebuild the Doxygen generated documentation.\r
+.PHONY: rebuilddoc\r
+rebuilddoc: cleandoc doc\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor macro repeating utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _MREPEAT_H_\r
+#define _MREPEAT_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+#include "preprocessor.h"\r
+\r
+\r
+//! Maximal number of repetitions supported by MREPEAT.\r
+#define MREPEAT_LIMIT 256\r
+\r
+/*! \brief Macro repeat.\r
+ *\r
+ * This macro represents a horizontal repetition construct.\r
+ *\r
+ * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.\r
+ * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with\r
+ * the current repetition number and the auxiliary data argument.\r
+ * \param data Auxiliary data passed to macro.\r
+ *\r
+ * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>\r
+ */\r
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data)\r
+\r
+#define MREPEAT0( macro, data)\r
+#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)\r
+#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)\r
+#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)\r
+#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)\r
+#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)\r
+#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)\r
+#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)\r
+#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)\r
+#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)\r
+#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)\r
+#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)\r
+#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)\r
+#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)\r
+#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)\r
+#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)\r
+#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)\r
+#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)\r
+#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)\r
+#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)\r
+#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)\r
+#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)\r
+#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)\r
+#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)\r
+#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)\r
+#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)\r
+#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)\r
+#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)\r
+#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)\r
+#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)\r
+#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)\r
+#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)\r
+#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)\r
+#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)\r
+#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)\r
+#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)\r
+#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)\r
+#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)\r
+#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)\r
+#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)\r
+#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)\r
+#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)\r
+#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)\r
+#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)\r
+#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)\r
+#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)\r
+#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)\r
+#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)\r
+#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)\r
+#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)\r
+#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)\r
+#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)\r
+#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)\r
+#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)\r
+#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)\r
+#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)\r
+#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)\r
+#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)\r
+#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)\r
+#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)\r
+#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)\r
+#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)\r
+#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)\r
+#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)\r
+#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)\r
+#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)\r
+#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)\r
+#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)\r
+#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)\r
+#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)\r
+#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)\r
+#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)\r
+#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)\r
+#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)\r
+#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)\r
+#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)\r
+#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)\r
+#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)\r
+#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)\r
+#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)\r
+#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)\r
+#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)\r
+#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)\r
+#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)\r
+#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)\r
+#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)\r
+#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)\r
+#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)\r
+#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)\r
+#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)\r
+#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)\r
+#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)\r
+#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)\r
+#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)\r
+#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)\r
+#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)\r
+#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)\r
+#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)\r
+#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)\r
+#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)\r
+#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)\r
+#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)\r
+#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)\r
+#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)\r
+#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)\r
+#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)\r
+#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)\r
+#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)\r
+#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)\r
+#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)\r
+#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)\r
+#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)\r
+#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)\r
+#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)\r
+#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)\r
+#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)\r
+#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)\r
+#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)\r
+#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)\r
+#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)\r
+#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)\r
+#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)\r
+#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)\r
+#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)\r
+#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)\r
+#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)\r
+#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)\r
+#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)\r
+#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)\r
+#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)\r
+#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)\r
+#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)\r
+#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)\r
+#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)\r
+#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)\r
+#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)\r
+#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)\r
+#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)\r
+#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)\r
+#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)\r
+#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)\r
+#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)\r
+#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)\r
+#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)\r
+#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)\r
+#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)\r
+#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)\r
+#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)\r
+#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)\r
+#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)\r
+#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)\r
+#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)\r
+#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)\r
+#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)\r
+#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)\r
+#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)\r
+#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)\r
+#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)\r
+#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)\r
+#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)\r
+#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)\r
+#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)\r
+#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)\r
+#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)\r
+#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)\r
+#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)\r
+#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)\r
+#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)\r
+#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)\r
+#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)\r
+#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)\r
+#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)\r
+#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)\r
+#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)\r
+#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)\r
+#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)\r
+#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)\r
+#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)\r
+#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)\r
+#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)\r
+#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)\r
+#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)\r
+#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)\r
+#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)\r
+#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)\r
+#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)\r
+#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)\r
+#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)\r
+#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)\r
+#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)\r
+#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)\r
+#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)\r
+#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)\r
+#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)\r
+#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)\r
+#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)\r
+#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)\r
+#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)\r
+#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)\r
+#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)\r
+#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)\r
+#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)\r
+#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)\r
+#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)\r
+#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)\r
+#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)\r
+#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)\r
+#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)\r
+#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)\r
+#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)\r
+#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)\r
+#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)\r
+#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)\r
+#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)\r
+#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)\r
+#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)\r
+#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)\r
+#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)\r
+#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)\r
+#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)\r
+#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)\r
+#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)\r
+#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)\r
+#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)\r
+#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)\r
+#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)\r
+#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)\r
+#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)\r
+#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)\r
+#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)\r
+#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)\r
+#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)\r
+#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)\r
+#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)\r
+#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)\r
+#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)\r
+#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)\r
+#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)\r
+#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)\r
+#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)\r
+#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)\r
+#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)\r
+#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)\r
+#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)\r
+#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)\r
+#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)\r
+#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)\r
+#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)\r
+#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)\r
+#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)\r
+#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)\r
+#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)\r
+#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)\r
+#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)\r
+#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)\r
+#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)\r
+#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _MREPEAT_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _PREPROCESSOR_H_\r
+#define _PREPROCESSOR_H_\r
+\r
+#include "tpaste.h"\r
+#include "stringz.h"\r
+#include "mrepeat.h"\r
+\r
+\r
+#endif // _PREPROCESSOR_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor stringizing utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _STRINGZ_H_\r
+#define _STRINGZ_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_stringz Preprocessor - Stringize\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+/*! \brief Stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the token passed as an argument if the token is \#defined.\r
+ *\r
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)\r
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to\r
+ * writing "A0".\r
+ */\r
+#define STRINGZ(x) #x\r
+\r
+/*! \brief Absolute stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the token is \#defined.\r
+ *\r
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is\r
+ * equivalent to writing "A0".\r
+ */\r
+#define ASTRINGZ(x) STRINGZ(x)\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _STRINGZ_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor token pasting utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _TPASTE_H_\r
+#define _TPASTE_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+/*! \name Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.\r
+ *\r
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by\r
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is\r
+ * equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define TPASTE2( a, b) a##b\r
+#define TPASTE3( a, b, c) a##b##c\r
+#define TPASTE4( a, b, c, d) a##b##c##d\r
+#define TPASTE5( a, b, c, d, e) a##b##c##d##e\r
+#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f\r
+#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g\r
+#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h\r
+#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i\r
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j\r
+//! @}\r
+\r
+/*! \name Absolute Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the tokens are \#defined.\r
+ *\r
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined\r
+ * as 32 is equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define ATPASTE2( a, b) TPASTE2( a, b)\r
+#define ATPASTE3( a, b, c) TPASTE3( a, b, c)\r
+#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)\r
+#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)\r
+#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)\r
+#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)\r
+#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)\r
+#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)\r
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)\r
+//! @}\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _TPASTE_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Status code definitions.\r
+ *\r
+ * This file defines various status codes returned by functions,\r
+ * indicating success or failure as well as what kind of failure.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef STATUS_CODES_H_INCLUDED\r
+#define STATUS_CODES_H_INCLUDED\r
+\r
+/**\r
+ * Status code that may be returned by shell commands and protocol\r
+ * implementations.\r
+ *\r
+ * \note Any change to these status codes and the corresponding\r
+ * message strings is strictly forbidden. New codes can be added,\r
+ * however, but make sure that any message string tables are updated\r
+ * at the same time.\r
+ */\r
+enum status_code {\r
+ STATUS_OK = 0, //!< Success\r
+ ERR_IO_ERROR = -1, //!< I/O error\r
+ ERR_FLUSHED = -2, //!< Request flushed from queue\r
+ ERR_TIMEOUT = -3, //!< Operation timed out\r
+ ERR_BAD_DATA = -4, //!< Data integrity check failed\r
+ ERR_PROTOCOL = -5, //!< Protocol error\r
+ ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device\r
+ ERR_NO_MEMORY = -7, //!< Insufficient memory\r
+ ERR_INVALID_ARG = -8, //!< Invalid argument\r
+ ERR_BAD_ADDRESS = -9, //!< Bad address\r
+ ERR_BUSY = -10, //!< Resource is busy\r
+ ERR_BAD_FORMAT = -11, //!< Data format not recognized\r
+\r
+ /**\r
+ * \brief Operation in progress\r
+ *\r
+ * This status code is for driver-internal use when an operation\r
+ * is currently being performed.\r
+ *\r
+ * \note Drivers should never return this status code to any\r
+ * callers. It is strictly for internal use.\r
+ */\r
+ OPERATION_IN_PROGRESS = -128,\r
+};\r
+\r
+typedef enum status_code status_code_t;\r
+\r
+#endif /* STATUS_CODES_H_INCLUDED */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V2.11\r
+ * @date 08. September 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+\r
+/** \mainpage CMSIS Cortex-M3\r
+\r
+ This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.\r
+ It consists of:\r
+\r
+ - Cortex-M Core Register Definitions\r
+ - Cortex-M functions\r
+ - Cortex-M instructions\r
+\r
+ The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease\r
+ access to the Cortex-M Core\r
+ */\r
+\r
+/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates following MISRA-C2004 Rules:\r
+ \r
+ - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'. \r
+\r
+ - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+ \r
+ - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code. \r
+\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core\r
+ - Cortex-M core Revision Number\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM3 definitions */\r
+#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+#define __FPU_USED 0 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ /* add preprocessor checks */\r
+#endif\r
+\r
+#include <stdint.h> /*!< standard types definitions */\r
+#include "core_cmInstr.h" /*!< Core Instruction Access */\r
+#include "core_cmFunc.h" /*!< Core Function Access */\r
+\r
+#endif /* __CORE_CM3_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM3_H_DEPENDANT\r
+#define __CORE_CM3_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM3_REV\r
+ #define __CM3_REV 0x0200\r
+ #warning "__CM3_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+/*@} end of group CMSIS_core_definitions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register CMSIS Core Register\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE CMSIS Core\r
+ Type definitions for the Cortex-M Core Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC CMSIS NVIC\r
+ Type definitions for the Cortex-M NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB CMSIS SCB\r
+ Type definitions for the Cortex-M System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#if (__CM3_REV < 0x0201) /* core r2p1 */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#else\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB\r
+ Type definitions for the Cortex-M System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1[1];\r
+#endif\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick CMSIS SysTick\r
+ Type definitions for the Cortex-M System Timer Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM CMSIS ITM\r
+ Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */\r
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU CMSIS MPU\r
+ Type definitions for the Cortex-M Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug CMSIS Core Debug\r
+ Type definitions for the Cortex-M Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ This function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ This function gets the priority grouping from NVIC Interrupt Controller.\r
+ Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+\r
+ \return Priority grouping field\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ This function enables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to enable\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ This function disables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to disable\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ This function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for get pending\r
+ \return 0 Interrupt status is not pending\r
+ \return 1 Interrupt status is pending\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ This function sets the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for set pending\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ This function clears the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for clear pending\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ This function reads the active register in NVIC and returns the active bit.\r
+ \param [in] IRQn Number of the interrupt for get active\r
+ \return 0 Interrupt status is not active\r
+ \return 1 Interrupt status is active\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ This function sets the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ Note: The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for set priority\r
+ \param [in] priority Priority to set\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ This function reads the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ The returned priority value is automatically aligned to the implemented\r
+ priority bits of the microcontroller.\r
+\r
+ \param [in] IRQn Number of the interrupt for get priority\r
+ \return Interrupt Priority\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ This function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ The returned priority value can be used for NVIC_SetPriority(...) function\r
+\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0)\r
+ \param [in] SubPriority Sub priority value (starting from 0)\r
+ \return Encoded priority for the interrupt\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ This function decodes an interrupt priority value with the given priority group to\r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ The priority value can be retrieved with NVIC_GetPriority(...) function\r
+\r
+ \param [in] Priority Priority value\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0)\r
+ \param [out] pSubPriority Sub priority value (starting from 0)\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ This function initiate a system reset request to reset the MCU.\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ This function initialises the system tick timer and its interrupt and start the system tick timer.\r
+ Counter is in free running mode to generate periodical interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ This function transmits a character via the ITM channel 0.\r
+ It just returns when no debugger is connected that has booked the output.\r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+\r
+ \param [in] ch Character to transmit\r
+ \return Character to transmit\r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ This function inputs a character via external variable ITM_RxBuffer.\r
+ It just returns when no debugger is connected that has booked the output.\r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+\r
+ \return Received character\r
+ \return -1 No character received\r
+ */\r
+static __INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ This function checks external variable ITM_RxBuffer whether a character is available or not.\r
+ It returns '1' if a character is available and '0' if no character is available.\r
+\r
+ \return 0 No character available\r
+ \return 1 Character available\r
+ */\r
+static __INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V2.10\r
+ * @date 26. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface \r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get ISPR Register\r
+\r
+ This function returns the content of the ISPR Register.\r
+\r
+ \return ISPR Register value\r
+ */\r
+static __INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+static __INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+static __INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+static __INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+static __INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+ \r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+static __INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+static __INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/** \brief Get ISPR Register\r
+\r
+ This function returns the content of the ISPR Register.\r
+\r
+ \return ISPR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V2.10\r
+ * @date 19. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor, \r
+ so that all instructions following the ISB are fetched from cache or \r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier. \r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before \r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+static __INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+static __INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz \r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor, \r
+ so that all instructions following the ISB are fetched from cache or \r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier. \r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before \r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint8_t result;\r
+ \r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint16_t result;\r
+ \r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint8_t result;\r
+ \r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+* -------------------------------------------------------------------\r
+* Copyright (C) 2011 ARM Limited. All rights reserved. \r
+* \r
+* Date: 25 July 2011 \r
+* Revision: V2.10 \r
+* \r
+* Project: Cortex Microcontroller Software Interface Standard (CMSIS)\r
+* Title: Release Note for CMSIS\r
+*\r
+* -------------------------------------------------------------------\r
+\r
+\r
+NOTE - Open the index.html file to access CMSIS documentation\r
+\r
+\r
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all \r
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects \r
+and reduces time-to-market for new embedded applications.\r
+\r
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").\r
+Any user of the software package is bound to the terms and conditions of the end user license agreement.\r
+\r
+\r
+You will find the following sub-directories:\r
+\r
+Documentation - Contains CMSIS documentation.\r
+ \r
+DSP_Lib - MDK project files, Examples and source files etc.. to build the \r
+ CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.\r
+\r
+Include - CMSIS Core Support and CMSIS DSP Include Files.\r
+\r
+Lib - CMSIS DSP Binaries \r
+---\r
--- /dev/null
+END USER LICENCE AGREEMENT FOR THE CORTEX MICROCONTROLLER SOFTWARE INTERFACE\r
+STANDARD (CMSIS) SPECIFICATION AND SOFTWARE\r
+\r
+THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A\r
+SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE\r
+CMSIS SPECIFICATION, EXAMPLE CODE, DSP LIBRARY SPECIFICATION AND DSP LIBRARY\r
+IMPLEMENTATION AS SUCH TERMS ARE DEFINED BELOW (COLLECTIVELY, THE "ARM\r
+DELIVERABLES"). ARM IS ONLY WILLING TO LICENSE THE ARM DELIVERABLES TO YOU ON CONDITION\r
+THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING\r
+OR OTHERWISE USING OR COPYING THE ARM DELIVERABLES YOU INDICATE THAT YOU AGREE TO\r
+BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS\r
+LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE THE ARM DELIVERABLES AND YOU MAY NOT\r
+INSTALL, USE OR COPY THE ARM DELIVERABLES.\r
+\r
+"CMSIS Specification" means any documentation and C programming language files defining the application\r
+programming interface, naming and coding conventions of the Cortex Microcontroller Software Interface\r
+Standard (CMSIS) as well as the System View Description (SVD) documentation and associated XML schema\r
+file. Notwithstanding the foregoing, "CMSIS Specification" shall not include (i) the implementation of other\r
+published specifications referenced in the CMSIS Specification; (ii) any enabling technologies that may be\r
+necessary to make or use any product or portion thereof that complies with the CMSIS Specification, but are not\r
+themselves expressly set forth in the CMSIS Specification (e.g. compiler front ends, code generators, back ends,\r
+libraries or other compiler, assembler or linker technologies; validation or debug software or hardware;\r
+applications, operating system or driver software; RISC architecture; processor microarchitecture); (iii)\r
+maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high level representations of\r
+integrated circuit designs.\r
+\r
+"DSP Library Implementation" means any C programming language source code implementing the functionality\r
+of the digital signal processor (DSP) algorithms and the application programming interface as defined in the DSP\r
+Library Specification. The DSP Library Implementation makes use of CMSIS application programming interface\r
+and therefore is targeted at Cortex-M class processors.\r
+\r
+"DSP Library Specification" means the DSP library documentation and C programming language file defining the\r
+application programming interface of the DSP Library Implementation. Notwithstanding the foregoing, "DSP\r
+Library Specification" shall not include (i) the implementation of other published specifications referenced in the\r
+DSP Library Specification; (ii) any enabling technologies that may be necessary to make or use any product or\r
+portion thereof that complies with the DSP Library Specification, but are not themselves expressly set forth in the\r
+DSP Library Specification (e.g. compiler front ends, code generators, back ends, libraries or other compiler,\r
+assembler or linker technologies; validation or debug software or hardware; applications, operating system or\r
+driver software; RISC architecture; processor microarchitecture); (iii) maskworks and physical layouts of\r
+integrated circuit designs; or (iv) RTL or other high level representations of integrated circuit designs.\r
+\r
+"Example Code" means any files in C, C++ or ARM assembly programming languages, associated project and\r
+configuration files that demonstrate the usage of the CMSIS Specification, the DSP Library Specification and the\r
+DSP Library Implementation, for microprocessors or device specific software applications that are for use with\r
+microprocessors.\r
+\r
+1. LICENCE GRANTS.\r
+\r
+1.1 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, nontransferable\r
+licence, to;\r
+\r
+(i) use and copy the CMSIS Specification for the purpose of developing, having developed, manufacturing,\r
+having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the\r
+CMSIS Specification, provided that you preserve any copyright notices which are included with, or in, the CMSIS\r
+Specification and provided that you do not use ARM's name, logo or trademarks to market such products;\r
+\r
+(ii) use, copy, and modify (solely to the extent necessary to incorporate the whole or any part of the DSP Library\r
+Specification into your documentation), the DSP Library Specification, for the purpose of developing, having\r
+developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing\r
+products that comply with the DSP Library Specification, and distribute and have distributed any documentation\r
+created by or for you that has been derived from the DSP Library Specification with such products, provided that\r
+you preserve any copyright notices which are included with, or in, the DSP Library Specification and provided that\r
+you do not use ARM's name, logo or trademarks to market such products;\r
+\r
+(iii) use, copy, modify and sublicense the Example Code solely for the purpose of developing, having developed,\r
+manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that\r
+comply with either or both the CMSIS Specification and the DSP Library Specification, provided that you preserve\r
+any copyright notices which are included with, or in, the Example Code and that you do not use ARM's name,\r
+logo or trademarks to market such products;\r
+\r
+(iv) use, copy and modify (provided that the logical functionality and the application programming interface of the\r
+DSP Library Implementation are maintained) the DSP Library Implementation, solely for the purposes of\r
+developing; (a) software applications for use with microprocessors manufactured or simulated under licence from\r
+ARM ("Software Applications"); and (b) tools that are designed to develop software programs for use with\r
+microprocessors manufactured or simulated under licence from ARM ("Tools"); and\r
+\r
+(v) subject to clause 1.1(vi) below; (a) distribute and sublicense the use of the DSP Library Implementation\r
+(including any modified forms thereof created under Clause 1.1(iv) above) in binary or source format, solely as\r
+incorporated into Software Library Applications and Tools to third parties; and (b) sublicense to such third parties\r
+the right to use and copy the Tools for the purposes of developing and distribute software programs for use with\r
+microprocessors manufactured or simulated under licence from ARM.\r
+\r
+(vi) CONDITIONS ON REDISTRIBUTION: If you choose to redistribute the whole or any part of the DSP Library\r
+Implementation as incorporated into Software Library Applications or Tools, you agree to; (a) ensure that the\r
+DSP Library Implementation is licensed for use only as part of Software Library Applications and Tools and only\r
+for use with microprocessors manufactured or simulated under licence from ARM; (b) not to use ARM's name,\r
+logo or trademarks to market Software Applications and Tools; and (c) include valid copyright notices on\r
+Software Applications and Tools, and preserve any copyright notices which are included with, or in, the DSP\r
+Library Implementation.\r
+\r
+2. RESTRICTIONS ON USE OF THE ARM DELIVERABLES.\r
+\r
+PERMITTED USERS: The ARM Deliverables shall be used only by you (either a single individual, or single legal\r
+entity) your employees, or by your on-site bona fide sub-contractors for whose acts and omissions you hereby\r
+agree to be responsible to ARM for to the same extent as you are for your employees, and provided always that\r
+such sub-contractors; (i) are contractually obligated to use the ARM Deliverables only for your benefit, and (ii)\r
+agree to assign all their work product and any rights they create therein in the supply of such work to you.\r
+COPYRIGHT AND RESERVATION OF RIGHTS: The ARM Deliverables are owned by ARM or its licensors and\r
+are protected by copyright and other intellectual property laws and international treaties. The ARM Deliverables\r
+are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the ARM\r
+Deliverables or any intellectual property therein. In no event shall the licences granted herein be construed as\r
+granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except\r
+the ARM Deliverables.\r
+\r
+3. SUPPORT.\r
+\r
+ARM is not obligated to support the ARM Deliverables but may do so entirely at ARM's discretion.\r
+\r
+4. NO WARRANTY\r
+\r
+YOU AGREE THAT THE ARM DELIVERABLES ARE LICENSED "AS IS", AND THAT ARM EXPRESSLY\r
+DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS,\r
+IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF NONINFRINGEMENT,\r
+SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE. THE ARM\r
+DELIVERABLES MAY CONTAIN ERRORS. ARM RESERVES THE RIGHT TO INCORPORATE\r
+MODIFICATIONS TO THE ARM DELIVERABLES IN LATER REVISIONS OF THEM, AND TO MAKE\r
+IMPROVEMENTS OR CHANGES IN THE ARM DELIVERABLES AT ANY TIME.\r
+\r
+5. LIMITATION OF LIABILITY.\r
+\r
+THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN\r
+CONTRACT, TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS\r
+LICENCE SHALL NOT EXCEED THE GREATER OF (I) THE TOTAL OF SUMS PAID BY YOU TO ARM (IF\r
+ANY) FOR THIS LICENCE AND (II) US$10.00. THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN\r
+THIS LICENCE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW.\r
+\r
+6. U.S. GOVERNMENT END USERS.\r
+US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this\r
+commercial product and accompanying documentation is restricted in accordance with the terms of this Licence.\r
+\r
+7. TERM AND TERMINATION.\r
+\r
+7.1 This Licence shall remain in force until terminated in accordance with the terms of Clause 7.2 or Clause 7.3\r
+below.\r
+\r
+7.2 Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this\r
+Licence then ARM may terminate this Licence immediately upon giving written notice to you. You may terminate\r
+this Licence at any time.\r
+\r
+7.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you\r
+asserts any patents against ARM, ARM affiliates, third parties who have a valid licence from ARM for the ARM\r
+Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate)\r
+patent is Necessary to implement the CMSIS Specification or DSP Library Specification. In this Licence; (i)\r
+"affiliate" means any entity controlling, controlled by or under common control with a party (in fact or in law, via\r
+voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert"\r
+means to allege infringement in legal or administrative proceedings, or proceedings before any other competent\r
+trade, arbitral or international authority; (iii) "Necessary" means with respect to any claims of any patent, those\r
+claims which, without the appropriate permission of the patent owner, will be infringed when implementing the\r
+CMSIS Specification or DSP Library Specification because no alternative, commercially reasonable, noninfringing\r
+way of implementing the CMSIS Specification or DSP Library Specification is known.\r
+\r
+7.4 Upon termination of this Licence, you shall stop using the ARM Deliverables and destroy all copies of the\r
+ARM Deliverables in your possession. The provisions of clauses 5, 6, 7, and 8 shall survive termination of this\r
+Licence.\r
+\r
+8. GENERAL.\r
+\r
+This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by\r
+you and ARM, this is the only agreement between you and ARM relating to the ARM Deliverables and it may only\r
+be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence\r
+may not be modified by purchase orders, advertising or other representation by any person. If any clause or\r
+sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisions of this\r
+Licence shall not be affected thereby. The failure by ARM to enforce any of the provisions of this Licence, unless\r
+waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of\r
+this Licence in the future. This Licence may not be assigned without the prior written consent of ARM.\r
+\r
+ARM contract reference LEC-PRE-00489\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Board configuration.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CONF_BOARD_H_INCLUDED\r
+#define CONF_BOARD_H_INCLUDED\r
+\r
+/* Configure UART pins */\r
+//#define CONF_BOARD_UART_CONSOLE\r
+\r
+/* Configure ADC example pins */\r
+//#define CONF_BOARD_ADC\r
+\r
+/* Enable USB interface (USB) for host mode */\r
+//#define CONF_BOARD_USB_PORT\r
+\r
+/*\r
+ * LED pins are not configured for PWM function here.\r
+ * Because those LED pins are enabled for PIO function by default.\r
+ * You can enable them according to application.\r
+ */\r
+/* Configure PWM LED0 pin */\r
+//#define CONF_BOARD_PWM_LED0\r
+\r
+/* Configure PWM LED1 pin */\r
+//#define CONF_BOARD_PWM_LED1\r
+\r
+/* Configure PWM LED2 pin */\r
+//#define CONF_BOARD_PWM_LED2\r
+\r
+/* Configure SPI0 pins */\r
+//#define CONF_BOARD_SPI0\r
+//#define CONF_BOARD_SPI0_NPCS0\r
+//#define CONF_BOARD_SPI0_NPCS1\r
+//#define CONF_BOARD_SPI0_NPCS2\r
+//#define CONF_BOARD_SPI0_NPCS3\r
+\r
+/* Configure SPI1 pins */\r
+//#define CONF_BOARD_SPI1\r
+//#define CONF_BOARD_SPI1_NPCS0\r
+//#define CONF_BOARD_SPI1_NPCS1\r
+//#define CONF_BOARD_SPI1_NPCS2\r
+//#define CONF_BOARD_SPI1_NPCS3\r
+\r
+//#define CONF_BOARD_TWI0\r
+\r
+//#define CONF_BOARD_TWI1\r
+\r
+/*\r
+ * USART pins are configured as basic serial port by default.\r
+ * You can enable other pins according application.\r
+ */\r
+/* Configure USART RXD pin */\r
+#define CONF_BOARD_USART_RXD\r
+\r
+/* Configure USART TXD pin */\r
+#define CONF_BOARD_USART_TXD\r
+\r
+/* Configure USART CTS pin */\r
+//#define CONF_BOARD_USART_CTS\r
+\r
+/* Configure USART RTS pin */\r
+//#define CONF_BOARD_USART_RTS\r
+\r
+/* Configure USART synchronous communication SCK pin */\r
+//#define CONF_BOARD_USART_SCK\r
+\r
+/* Configure ADM3312 enable pin */\r
+#define CONF_BOARD_ADM3312_EN\r
+\r
+/* Configure IrDA transceiver shutdown pin */\r
+//#define CONF_BOARD_TFDU4300_SD\r
+\r
+/* Configure RS485 transceiver ADM3485 RE pin */\r
+//#define CONF_BOARD_ADM3485_RE\r
+\r
+//#define CONF_BOARD_SMC_PSRAM\r
+\r
+/* Configure LCD EBI pins */\r
+//#define CONF_BOARD_HX8347A\r
+\r
+/* Configure Backlight control pin */\r
+//#define CONF_BOARD_AAT3194\r
+\r
+#endif /* CONF_BOARD_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM3X clock configuration.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * \page License\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CONF_CLOCK_H_INCLUDED\r
+#define CONF_CLOCK_H_INCLUDED\r
+\r
+// ===== System Clock (MCK) Source Options\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS\r
+#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK\r
+//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK\r
+\r
+// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES))\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1\r
+#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64\r
+//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3\r
+\r
+// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)\r
+// Use mul and div effective values here.\r
+#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL\r
+#define CONFIG_PLL0_MUL 14\r
+#define CONFIG_PLL0_DIV 1\r
+\r
+// ===== UPLL (UTMI) Hardware fixed at 480 MHz.\r
+\r
+// ===== USB Clock Source Options (Fusb = FpllX / USB_div)\r
+// Use div effective value here.\r
+//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0\r
+//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL\r
+//#define CONFIG_USBCLK_DIV 1\r
+\r
+// ===== Target frequency (System clock)\r
+// - XTAL frequency: 12MHz\r
+// - System clock source: PLLA\r
+// - System clock prescaler: 2 (divided by 2)\r
+// - PLLA source: XTAL\r
+// - PLLA output: XTAL * 14 / 1\r
+// - System clock is: 12 * 14 / 1 /2 = 84MHz\r
+// ===== Target frequency (USB Clock)\r
+// - USB clock source: UPLL\r
+// - USB clock divider: 1 (not divided)\r
+// - UPLL frequency: 480MHz\r
+// - USB clock: 480 / 1 = 480MHz\r
+\r
+\r
+#endif /* CONF_CLOCK_H_INCLUDED */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, training, latest information,\r
+ license and contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
+ the code with commercial support, indemnification, and middleware, under\r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under\r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard demo includes - just needed for the LED (ParTest) initialisation\r
+function. */\r
+#include "partest.h"\r
+\r
+/* Atmel library includes. */\r
+#include <asf.h>\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Set up the hardware ready to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+extern void main_blinky( void );\r
+extern void main_full( void );\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the documentation page for this demo on the FreeRTOS.org web site for\r
+full information - including hardware setup requirements. */\r
+\r
+int main( void )\r
+{\r
+ /* Prepare the hardware to run this demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+extern void SystemCoreClockUpdate( void );\r
+\r
+ /* ASF function to setup clocking. */\r
+ sysclk_init();\r
+\r
+ /* Ensure all priority bits are assigned as preemption priority bits. */\r
+ NVIC_SetPriorityGrouping( 0 );\r
+\r
+ /* Atmel library function to setup for the evaluation kit being used. */\r
+ board_init();\r
+\r
+ /* Perform any configuration necessary to use the ParTest LED output\r
+ functions. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if\r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles the LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Atmel library includes. */\r
+#include "asf.h"\r
+\r
+/* Common demo includes. */\r
+#include "partest.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* Values passed to the two tasks just to check the task parameter \r
+functionality. */\r
+#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
+#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Called by main() to create the simply blinky style application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was insufficient FreeRTOS heap memory available for the idle and/or\r
+ timer tasks to be created. See the memory management section on the\r
+ FreeRTOS web site for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again.\r
+ The block time is specified in ticks, the constant used converts ticks\r
+ to ms. While in the Blocked state this task will not consume any CPU\r
+ time. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == 100UL )\r
+ {\r
+ vParTestToggleLED( 0 );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and a software timer, then\r
+ * starts the scheduler. The web documentation provides more details of the \r
+ * standard demo application tasks, which provide no particular functionality, \r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Check" timer - The check software timer period is initially set to three\r
+ * seconds. The callback function associated with the check software timer\r
+ * checks that all the standard demo tasks are not only still executing, but \r
+ * are executing without reporting any errors. If the check software timer \r
+ * discovers that a task has either stalled, or reported an error, then it \r
+ * changes its own execution period from the initial three seconds, to just \r
+ * 200ms. The check software timer callback function also toggles the green \r
+ * LED each time it is called. This provides a visual indication of the system \r
+ * status: If the green LED toggles every three seconds, then no issues have \r
+ * been discovered. If the green LED toggles every 200ms, then an issue has \r
+ * been discovered with at least one task.\r
+ *\r
+ * See the documentation page for this demo on the FreeRTOS.org web site for\r
+ * full information, including hardware setup requirements. \r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+#include "flash_timer.h"\r
+#include "partest.h"\r
+#include "comtest2.h"\r
+\r
+\r
+/* Atmel library includes. */\r
+#include "asf.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/* The standard demo flash timers can be used to flash any number of LEDs. In\r
+this case, because only three LEDs are available, and one is in use by the\r
+check timer, only two are used by the flash timers. */\r
+#define mainNUMBER_OF_FLASH_TIMERS_LEDS ( 2 )\r
+\r
+/* The LED toggled by the check timer. The first two LEDs are toggle by the\r
+standard demo flash timers. */\r
+#define mainCHECK_LED ( 2 )\r
+\r
+/* Baud rate used by the comtest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( 115200 )\r
+\r
+/* The LED used by the comtest tasks. In this case, there are no LEDs available\r
+for the comtest, so the LED number is deliberately out of range. */\r
+#define mainCOM_TEST_LED ( 3 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+xTimerHandle xCheckTimer = NULL;\r
+\r
+ /* Start all the other standard demo/test tasks. The have not particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartLEDFlashTimers( mainNUMBER_OF_FLASH_TIMERS_LEDS );\r
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );\r
+ \r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ ); \r
+ \r
+ if( xCheckTimer != NULL )\r
+ {\r
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
+ }\r
+\r
+ /* The set of tasks created by the following function call have to be \r
+ created last as they keep account of the number of tasks they expect to see \r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+ \r
+ /* If all is well, the scheduler will now be running, and the following line\r
+ will never be reached. If the following line does execute, then there was\r
+ insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+ to be created. See the memory management section on the FreeRTOS web site\r
+ for more details. */\r
+ for( ;; ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ they are all still running, and that none have detected an error. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ \r
+ if( xAreComTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ \r
+ /* Have any errors been latch in ulErrorFound? If so, shorten the\r
+ period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
+ This will result in an increase in the rate at which mainCHECK_LED\r
+ toggles. */\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+ \r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, training, latest information,\r
+ license and contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
+ the code with commercial support, indemnification, and middleware, under\r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under\r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART1.\r
+\r
+ ***Note*** This example uses queues to send each character into an interrupt\r
+ service routine and out of an interrupt service routine individually. This\r
+ is done to demonstrate queues being used in an interrupt, and to deliberately\r
+ load the system to test the FreeRTOS port. It is *NOT* meant to be an\r
+ example of an efficient implementation. An efficient implementation should\r
+ use FIFO's or DMA if available, and only use FreeRTOS API functions when\r
+ enough has been received to warrant a task being unblocked to process the\r
+ data.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+#include "comtest2.h"\r
+\r
+/* Library includes. */\r
+#include "asf.h"\r
+\r
+/* Demo application includes. */\r
+#include "demo_serial.h"\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Misc defines. */\r
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )\r
+#define serNO_BLOCK ( ( portTickType ) 0 )\r
+#define serPMC_USART_ID ( BOARD_ID_USART )\r
+\r
+/* The USART supported by this file. */\r
+#define serUSART_PORT ( USART0 )\r
+#define serUSART_IRQ ( USART0_IRQn )\r
+\r
+/* Every bit in the interrupt mask. */\r
+#define serMASK_ALL_INTERRUPTS ( 0xffffffffUL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used to hold received characters. */\r
+static xQueueHandle xRxedChars;\r
+static xQueueHandle xCharsForTx;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * See the serial.h header file.\r
+ */\r
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
+{\r
+uint32_t ulChar;\r
+xComPortHandle xReturn;\r
+const sam_usart_opt_t xUSARTSettings =\r
+{\r
+ ulWantedBaud,\r
+ US_MR_CHRL_8_BIT,\r
+ US_MR_PAR_NO,\r
+ US_MR_NBSTOP_1_BIT,\r
+ US_MR_CHMODE_NORMAL,\r
+ 0 /* Only used in IrDA mode. */\r
+};\r
+\r
+ /* Create the queues used to hold Rx/Tx characters. */\r
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );\r
+\r
+ /* If the queues were created correctly then setup the serial port\r
+ hardware. */\r
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )\r
+ {\r
+ /* Enable the peripheral clock in the PMC. */\r
+ pmc_enable_periph_clk( serPMC_USART_ID );\r
+\r
+ /* Configure USART in serial mode. */\r
+ usart_init_rs232( serUSART_PORT, &xUSARTSettings, sysclk_get_cpu_hz() );\r
+\r
+ /* Disable all the interrupts. */\r
+ usart_disable_interrupt( serUSART_PORT, serMASK_ALL_INTERRUPTS );\r
+\r
+ /* Enable the receiver and transmitter. */\r
+ usart_enable_tx( serUSART_PORT );\r
+ usart_enable_rx( serUSART_PORT );\r
+\r
+ /* Clear any characters before enabling interrupt. */\r
+ usart_getchar( serUSART_PORT, &ulChar );\r
+\r
+ /* Enable Rx end interrupt. */\r
+ usart_enable_interrupt( serUSART_PORT, US_IER_RXRDY );\r
+\r
+ /* Configure and enable interrupt of USART. */\r
+ NVIC_SetPriority( serUSART_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+ NVIC_EnableIRQ( serUSART_IRQ );\r
+ }\r
+ else\r
+ {\r
+ xReturn = ( xComPortHandle ) 0;\r
+ }\r
+\r
+ /* This demo file only supports a single port but we have to return\r
+ something to comply with the standard demo header file. */\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )\r
+{\r
+ /* The port handle is not required as this driver only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+ /* Get the next character from the buffer. Return false if no characters\r
+ are available, or arrive before xBlockTime expires. */\r
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ return pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )\r
+{\r
+signed char *pxNext;\r
+\r
+ /* A couple of parameters that this port does not use. */\r
+ ( void ) usStringLength;\r
+ ( void ) pxPort;\r
+\r
+ /* NOTE: This implementation does not handle the queue being full as no\r
+ block time is used! */\r
+\r
+ /* The port handle is not required as this driver only supports USART1. */\r
+ ( void ) pxPort;\r
+\r
+ /* Send each character in the string, one at a time. */\r
+ pxNext = ( signed char * ) pcString;\r
+ while( *pxNext )\r
+ {\r
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );\r
+ pxNext++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* This simple example only supports one port. */\r
+ ( void ) pxPort;\r
+\r
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )\r
+ {\r
+ xReturn = pdPASS;\r
+ usart_enable_interrupt( serUSART_PORT, US_IER_TXRDY );\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialClose( xComPortHandle xPort )\r
+{\r
+ /* Not supported as not required by the demo application. */\r
+ ( void ) xPort;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * It should be noted that the com test tasks (which use make use of this file)\r
+ * are included to demonstrate queues being used to communicate between tasks\r
+ * and interrupts, and to demonstrate a context switch being performed from\r
+ * inside an interrupt service routine. The serial driver used here is *not*\r
+ * intended to represent an efficient implementation. Real applications should\r
+ * make use of the USARTS peripheral DMA channel (PDC).\r
+ */\r
+void USART0_Handler( void )\r
+{\r
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+uint8_t ucChar;\r
+uint32_t ulChar;\r
+uint32_t ulUSARTStatus, ulUSARTMask;\r
+\r
+ ulUSARTStatus = usart_get_status( serUSART_PORT );\r
+ ulUSARTMask = usart_get_interrupt_mask( serUSART_PORT );\r
+ ulUSARTStatus &= ulUSARTMask;\r
+\r
+ if( ( ulUSARTStatus & US_CSR_TXRDY ) != 0UL )\r
+ {\r
+ /* The interrupt was caused by the TX register becoming empty. Are\r
+ there any more characters to transmit? */\r
+ if( xQueueReceiveFromISR( xCharsForTx, &ucChar, &xHigherPriorityTaskWoken ) == pdTRUE )\r
+ {\r
+ /* A character was retrieved from the queue so can be sent to the\r
+ USART now. */\r
+ usart_putchar( serUSART_PORT, ( uint32_t ) ucChar );\r
+ }\r
+ else\r
+ {\r
+ usart_disable_interrupt( serUSART_PORT, US_IER_TXRDY );\r
+ }\r
+ }\r
+\r
+ if( ( ulUSARTStatus & US_CSR_RXRDY ) != 0UL )\r
+ {\r
+ /* A character has been received on the USART, send it to the Rx\r
+ handler task. */\r
+ usart_getchar( serUSART_PORT, &ulChar );\r
+ ucChar = ( uint8_t ) ( ulChar & 0xffUL );\r
+ xQueueSendFromISR( xRxedChars, &ucChar, &xHigherPriorityTaskWoken );\r
+ }\r
+\r
+ /* If sending or receiving from a queue has caused a task to unblock, and\r
+ the unblocked task has a priority equal to or higher than the currently\r
+ running task (the task this ISR interrupted), then xHigherPriorityTaskWoken\r
+ will have automatically been set to pdTRUE within the queue send or receive\r
+ function. portEND_SWITCHING_ISR() will then ensure that this ISR returns\r
+ directly to the higher priority unblocked task. */\r
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
projects / freertos / commitdiff