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u-boot
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Thu, 22 Sep 2016 15:36:45 +0000 (11:36 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

8 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Thu, 22 Sep 2016 15:36:23 +0000 (11:36 -0400)]
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

8 years agoMakefile: rm u-boot.cfg dependencies are missing
Stephen Warren [Mon, 19 Sep 2016 18:20:26 +0000 (12:20 -0600)]
Makefile: rm u-boot.cfg dependencies are missing

Prior to the previous patch, a freshly created .u-boot.cfg.cmd may not
correctly represent all dependencies for u-boot.cfg. The previous change
only solved this issue for fresh builds; when performing an incremental
build, the deficient .u-boot.cfg.cmd is already present, so u-boot.cfg
is not rebuilt, and hence .u-boot.cfg.cmd is not rebuilt with the correct
content.

Solve this by explicitly detecting when the dependency file .u-boot.cfg.d
has not been integrated into .u-boot.cfg.cmd, and force u-boot.cfg to be
rebuilt in this case by deleting it first. This is possible since
if_changed_dep will always delete .u-boot.cfg.d when it executes
successfully, so its presence means either that the previous build was
made by a source tree that contained a Makefile that didn't include the
previous patch, or that the build failed part way through executing
if_changed_dep for u-boot.cfg. Forcing a rebuild of u-boot.cfg is required
in the former case, and will cause no additional work in the latter case,
since the file would be rebuilt anyway for the same reason it was being
rebuilt by the previous build.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
8 years agoMakefile: use if_change_dep for u-boot.cfg
Stephen Warren [Mon, 19 Sep 2016 18:20:25 +0000 (12:20 -0600)]
Makefile: use if_change_dep for u-boot.cfg

cmd_cpp_cfg generates a dependency output, but because it's invoked using
if_changed rather than if_changed_dep, that dependency file is ignored.
This results in Kbuild not knowing about which files u-boot.cfg depends
on, so it may not be rebuilt when required.

A practical result of this is that u-boot.cfg may continue to reference
CONFIG_ options that no longer exist in the source tree, and this can
cause the adhoc config options check to fail.

This change modifies Makefile to use if_changed_dep, which in turn causes
all dependencies to be known to the next make invocation.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
8 years agotest/py/tests/test_vboot.py: Add check that we boot the image
Tom Rini [Sun, 18 Sep 2016 13:46:58 +0000 (09:46 -0400)]
test/py/tests/test_vboot.py: Add check that we boot the image

Make sure that when we're telling bootm to boot an image, and we expect
the image to boot we get the output from sandbox that we attempted to
run Linux and that U-Boot completed its job.

Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
8 years agoimage-fit: Fix fit_get_node_from_config semantics
Paul Burton [Tue, 20 Sep 2016 17:17:12 +0000 (18:17 +0100)]
image-fit: Fix fit_get_node_from_config semantics

Commit bac17b78dace ("image-fit: switch ENOLINK to ENOENT") changed
fit_get_node_from_config to return -ENOENT when a property doesn't
exist, but didn't change any of its callers which check return values.
Notably it didn't change boot_get_ramdisk, which leads to U-Boot failing
to boot FIT images which don't include ramdisks with the following
message:

  Ramdisk image is corrupt or invalid

It also didn't take into account that by returning -ENOENT to denote the
lack of a property we lost the ability to determine from the return
value of fit_get_node_from_config whether it was the property or the
configuration node that was missing, which may potentially lead callers
to accept invalid FIT images.

Fix this by having fit_get_node_from_config return -EINVAL when the
configuration node isn't found and -ENOENT when the property isn't
found, which seems to make semantic sense. Callers that previously
checked for -ENOLINK are adjusted to check for -ENOENT, which fixes the
breakage introduced by commit bac17b78dace ("image-fit: switch ENOLINK
to ENOENT").

The only other user of the return fit_get_node_from_config return value,
indirectly, is bootm_find_os which already checked for -ENOENT. From a
read-through of the code I suspect it ought to have been checking for
-ENOLINK prior to bac17b78dace ("image-fit: switch ENOLINK to ENOENT")
anyway, which would make it right after this patch, but this would be
good to get verified by someone who knows this x86 code or is able to
test it.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Jonathan Gray <jsg@jsg.id.au>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
8 years agoconfigs: fsl: Move SPI/SPI-FLASH configs to defconfig
Jagan Teki [Wed, 21 Sep 2016 19:55:48 +0000 (01:25 +0530)]
configs: fsl: Move SPI/SPI-FLASH configs to defconfig

Moved FSL_QSPI/SPI/SPI-FLASH configs from include/configs
into respective used defconfigs.
- CONFIG_FSL_QSPI
- CONFIG_SPI_FLASH
- CONFIG_SPI_FLASH_BAR
- CONFIG_SPI_FLASH_STMICRO

Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
8 years agospi: Kconfig: Move FSL_QSPI entry to non-dm place
Jagan Teki [Sat, 3 Sep 2016 07:28:33 +0000 (12:58 +0530)]
spi: Kconfig: Move FSL_QSPI entry to non-dm place

Since FSL_QSPI driver still supporting non-dm code
better to move the Kconfig from DM undefined place.

Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
8 years agozynqmp: Remove unnnecessary board config file for dc4
Siva Durga Prasad Paladugu [Mon, 1 Aug 2016 04:49:38 +0000 (10:19 +0530)]
zynqmp: Remove unnnecessary board config file for dc4

Remove unnecessary board specific config file for DC4
board.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Use the same name for atf image everywhere
Michal Simek [Wed, 21 Sep 2016 09:42:58 +0000 (11:42 +0200)]
ARM64: zynqmp: Use the same name for atf image everywhere

Use atf-uboot.ub image instead of atf.ub.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Enable CONFIG_AHCI via Kconfig
Michal Simek [Wed, 7 Sep 2016 11:16:31 +0000 (13:16 +0200)]
ARM64: zynqmp: Enable CONFIG_AHCI via Kconfig

Move CONFIG_AHCI to defconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Add support for chip ID detection
Michal Simek [Mon, 1 Feb 2016 14:05:58 +0000 (15:05 +0100)]
ARM64: zynqmp: Add support for chip ID detection

Chip ID needs to be known for loading bitstream because
U-Boot checks ID from bitstream header in BIT format.
BIN format is completely unchecked.

The chipid is get from ATF via SMC.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agofpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP
Siva Durga Prasad Paladugu [Wed, 13 Jan 2016 10:55:37 +0000 (16:25 +0530)]
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP

Add PL bitstream dowload support for ZynqMP
Bitstream will be validated by uboot and loaded
to PL by invoking an smc instruction to ATF which route this request to
PMU FW which will take care of loading it to PL

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Fix USB ulpi phy sequence
Michal Simek [Tue, 16 Aug 2016 13:40:05 +0000 (15:40 +0200)]
ARM64: zynqmp: Fix USB ulpi phy sequence

It should be enough to call low(5us)->high pulse for all cases
to provide proper reset. There is no need to call high->low->high.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Add support for USB ulpi phy reset via mode pins
Michal Simek [Mon, 15 Aug 2016 07:41:36 +0000 (09:41 +0200)]
ARM64: zynqmp: Add support for USB ulpi phy reset via mode pins

Mode pins can be used as output for reset. Xilinx boards are using
this feature as additional way how to reset USB phys and also others
chips on the boards.
Mode1 is used on all these boards for this feature.
Let SPL toggle reset on this pin by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Add support for DFU from SPL
Michal Simek [Fri, 19 Aug 2016 12:14:52 +0000 (14:14 +0200)]
ARM64: zynqmp: Add support for DFU from SPL

SPL needs to have bigger stack size because of USB.
Simple malloc needs to be disabled because dfu code requires different
allocation functions. There is no space in OCM that's why random place
in DDR is used.

BOOTD must be disabled because it is causing compilation error.

All variables are disabled and used only variables valid for DFU because
they are simple huge. Including automatic variables added by
CONFIG_ENV_VARS_UBOOT_CONFIG.
Hardcode addresses for u-boot, atf, kernel and dtb
just for SPL DFU code.

Enable SPL DFU for zcu100.
Create new usb_dfu_spl variable just to run Linux kernel loaded in SPL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM: Add new BOOT_DEVICE_DFU boot mode
Michal Simek [Tue, 30 Aug 2016 13:38:57 +0000 (15:38 +0200)]
ARM: Add new BOOT_DEVICE_DFU boot mode

This enum is needed when SPL_DFU is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Add USB boot mode
Michal Simek [Fri, 29 Apr 2016 11:00:10 +0000 (13:00 +0200)]
ARM64: zynqmp: Add USB boot mode

Add USB boot mode.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Move BSS location to the beginning of ram
Michal Simek [Tue, 30 Aug 2016 12:58:46 +0000 (14:58 +0200)]
ARM64: zynqmp: Move BSS location to the beginning of ram

With SPL_DFU support memory layout needs to be cleanup
that's why move bss to the start of memory.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agospi: zynq: Use variable to remove u32 to u64 conversions
Michal Simek [Thu, 1 Sep 2016 10:51:27 +0000 (12:51 +0200)]
spi: zynq: Use variable to remove u32 to u64 conversions

Current code generates warning when it is compiled for arm64:
Warnings:
In file included from drivers/spi/zynq_spi.c:14:0:
drivers/spi/zynq_spi.c: In function ‘zynq_spi_init_hw’:
drivers/spi/zynq_spi.c:95:9: warning: large integer implicitly truncated
to unsigned type [-Woverflow]
  writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
         ^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
                                  ^
drivers/spi/zynq_spi.c: In function ‘zynq_spi_release_bus’:
drivers/spi/zynq_spi.c:177:9: warning: large integer implicitly
truncated to unsigned type [-Woverflow]
  writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
         ^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
                                  ^
This patch is using one variable to do conversion via u32 variable.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoARM64: zynqmp: Fix usb_gadget_handle_interrupt routine
Michal Simek [Thu, 1 Sep 2016 09:16:40 +0000 (11:16 +0200)]
ARM64: zynqmp: Fix usb_gadget_handle_interrupt routine

Function is defined in g_dnl.h and have different parameter
then it is used. This patch fixes it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Force certain bootmode for SPL
Michal Simek [Tue, 30 Aug 2016 14:17:27 +0000 (16:17 +0200)]
ARM64: zynqmp: Force certain bootmode for SPL

ZynqMP provides an option to overwrite bootmode setting which
can change SPL behavior.
For example: boot SPL via JTAG and then SPL loads images from SD.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoARM64: zynqmp: Wire up both USBs available on ZynqMP
Michal Simek [Mon, 8 Aug 2016 08:11:26 +0000 (10:11 +0200)]
ARM64: zynqmp: Wire up both USBs available on ZynqMP

The second USB wasn't enabled. This patch fixes it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agofpga: Add Kconfig to fpga subsystem
Michal Simek [Mon, 19 Sep 2016 08:41:55 +0000 (10:41 +0200)]
fpga: Add Kconfig to fpga subsystem

Add missing Kconfig to fpga subsystem to be able
to add new options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
8 years agoomap4_panda: Disable ext2/3/4 support in SPL
Tom Rini [Wed, 21 Sep 2016 22:38:41 +0000 (18:38 -0400)]
omap4_panda: Disable ext2/3/4 support in SPL

Pandaboard is growing again, disable EXT2/3/4 support in SPL save more
space.

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoclk.h: Add <asm/errno.h>
Tom Rini [Wed, 21 Sep 2016 21:56:01 +0000 (17:56 -0400)]
clk.h: Add <asm/errno.h>

Since we return -ENOSYS in some cases we must have <asm/errno.>
available.

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agosf: Move flags macro's to spi_flash_params{} members
Jagan Teki [Mon, 8 Aug 2016 13:55:55 +0000 (19:25 +0530)]
sf: Move flags macro's to spi_flash_params{} members

This patch moves flags macro's to respective member position on
spi_flash_params{}, for better readabilty and finding the
respective member macro's easily.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
8 years agosf: Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash
Jagan Teki [Mon, 8 Aug 2016 11:53:56 +0000 (17:23 +0530)]
sf: Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash

Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash code from header file.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
8 years agosf: Remove SECT_32K
Jagan Teki [Mon, 8 Aug 2016 11:49:08 +0000 (17:19 +0530)]
sf: Remove SECT_32K

SECT_32K never used anywhere in the code.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
8 years agospi: Remove SPI_RX_FAST
Jagan Teki [Wed, 10 Aug 2016 15:18:14 +0000 (20:48 +0530)]
spi: Remove SPI_RX_FAST

Removed SPI_RX_FAST since default read for spi slaves
are always 1-wire fast read.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
8 years agospi: Use mode for rx mode flags
Jagan Teki [Mon, 8 Aug 2016 11:42:12 +0000 (17:12 +0530)]
spi: Use mode for rx mode flags

Make rx mode flags as generic to spi, earlier mode_rx is
maintained separately because of some flash specific code.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
8 years agosf: Remove e_rd_cmd from param table
Jagan Teki [Mon, 8 Aug 2016 11:32:18 +0000 (17:02 +0530)]
sf: Remove e_rd_cmd from param table

e_rd_cmd is maintained separately for fastest read command code,
since the read commands are computed normally this e_rd_cmd
is not required in spi_flash_params table.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
8 years agosf: Simplify fastest read cmd code
Jagan Teki [Mon, 8 Aug 2016 11:20:45 +0000 (16:50 +0530)]
sf: Simplify fastest read cmd code

Fastest read command code look for fastest read command
taking inputs from spi->mode_rx and flags from param table
and controller mode_rx is always been a priority.

Since mode_rx is always set from controller side this optimized
code doesn't require much and this code required exctra overhead like
1) Maintain e_rx_cmd in param table
2) Maintain mode_rx in spi_slave {}

Hence removed this code, and look for read command from normal
spi->mode from spi_slave{} and params->flags

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
8 years agospi: ti_qspi: Remove unnecessary udelay for AM437x
Vignesh R [Wed, 7 Sep 2016 09:48:23 +0000 (15:18 +0530)]
spi: ti_qspi: Remove unnecessary udelay for AM437x

This udelay() was added as an HACK and is no longer required. All
read/write/erase operations work fine even without this delay. Hence,
remove the udelay() call.

Tested read/write/erase operation on AM437x SK. Also tested QSPI Boot.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agospi: ti_qspi: use 128 bit transfer mode when writing to flash
Vignesh R [Wed, 7 Sep 2016 09:48:22 +0000 (15:18 +0530)]
spi: ti_qspi: use 128 bit transfer mode when writing to flash

TI QSPI has four 32 bit data registers which can be used to transfer 16
bytes of data at once. The register group QSPI_SPI_DATA_REG_3,
QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is
treated as a single 128-bit word for shifting data in and out. The bit
at QSPI_SPI_DATA_REG_3[31] position is the first bit to be shifted out
in case of 128 bit transfer mode. Therefore the first byte to be written
to flash should be at QSPI_SPI_DATA_REG_3[31-25] position.
Instead of writing 1 byte at a time when interacting with SPI NOR flash,
make use of all the four registers so that 16 bytes can be transferred
in one go.

With this patch, the flash write speed increases from ~250KBs/ to
~650KB/s on DRA74 EVM.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agospi: zynq_spi: Fix infinite looping while xfer
Lad, Prabhakar [Sat, 30 Jul 2016 21:28:24 +0000 (22:28 +0100)]
spi: zynq_spi: Fix infinite looping while xfer

During spi transfer, for example:
sspi 1:1.0 8 ff

the rx_len values will  be:
rx_len = 0
rx_len = 4294967295

This caused a busy looping during xfer, this patch fixes it
by adding a check while reading the rx fifo

Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Wed, 21 Sep 2016 18:50:18 +0000 (14:50 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

8 years agoMerge branch 'master' of http://git.denx.de/u-boot-mmc
Tom Rini [Wed, 21 Sep 2016 15:48:02 +0000 (11:48 -0400)]
Merge branch 'master' of http://git.denx.de/u-boot-mmc

8 years agoMIPS: Hang if run on a secondary CPU
Paul Burton [Wed, 21 Sep 2016 13:59:54 +0000 (14:59 +0100)]
MIPS: Hang if run on a secondary CPU

Some systems are configured such that multiple CPUs begin running from
their reset vector following a system reset. If this occurs then U-Boot
will be run on multiple CPUs simultaneously, which causes all sorts of
issues as the multiple instances of U-Boot clobber each other.

Prevent this from happening by simply hanging with an infinite loop if
we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum
as appropriate, is non-zero.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Fix cache maintenance in relocate_code & simplify
Paul Burton [Wed, 21 Sep 2016 10:11:06 +0000 (11:11 +0100)]
MIPS: Fix cache maintenance in relocate_code & simplify

The relocate_code function was handling cache maintenance incorrectly.
It copied U-Boot to its new location, flushed the caches & then
proceeded to apply relocations & jump to the new code without flushing
the caches again. This is problematic as the instruction cache could
potentially have already fetched instructions that hadn't had relocs
applied.

Rework this to perform the flush_cache call using the code in the
original copy of U-Boot, after having applied relocations to the new
copy of U-Boot. The new U-Boot can then be jumped to safely once that
cache flush has been performed.

As part of this, since the old U-Boot is used up until after that cache
flush, complexity around loading values from the GOT using a jump & link
instruction & loads from a table is removed. Instead we can simply load
the needed values with PTR_LA fromt the original GOT.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoboston: Introduce support for the MIPS Boston development board
Paul Burton [Thu, 8 Sep 2016 06:47:39 +0000 (07:47 +0100)]
boston: Introduce support for the MIPS Boston development board

This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA & an
Intel EG20T Platform Controller Hub, used largely as part of the
development of new CPUs and their software support. It is essentially
the successor to the older MIPS Malta board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoclk: boston: Providea simple driver for Boston board clocks
Paul Burton [Thu, 8 Sep 2016 06:47:38 +0000 (07:47 +0100)]
clk: boston: Providea simple driver for Boston board clocks

Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agodm: syscon: Provide a generic syscon driver
Paul Burton [Thu, 8 Sep 2016 06:47:37 +0000 (07:47 +0100)]
dm: syscon: Provide a generic syscon driver

Provide a trivial syscon driver matching the generic "syscon" compatible
string, allowing for simple system controllers to be used without a
custom driver just as in Linux.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agodm: core: Match compatible strings in order of priority
Paul Burton [Thu, 8 Sep 2016 06:47:36 +0000 (07:47 +0100)]
dm: core: Match compatible strings in order of priority

Device model drivers have previously been matched to FDT nodes by virtue
of being the first driver in the driver list to be compatible with the
node. This ignores the fact that compatible strings in the device tree
are listed in order of priority - that is, if we have a node with 2
compatible strings & a driver that matches each then we should always
probe the driver that matches the first compatible string.

Fix this by looping through the compatible strings for a node when
attempting to bind it in lists_bind_fdt and checking each driver for
a match of the first string, then each driver for a match of the second
string etc. Effectively this inverts the loops over compatible strings &
drivers.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agodm: regmap: Implement simple regmap_read & regmap_write
Paul Burton [Thu, 8 Sep 2016 06:47:35 +0000 (07:47 +0100)]
dm: regmap: Implement simple regmap_read & regmap_write

The regmap_read & regmap_write functions were previously declared in
regmap.h but not implemented anywhere. The regmap implementation &
commit message of 6f98b7504f70 ("dm: Add support for register maps
(regmap)") indicate that only memory mapped accesses are supported for
now, so providing simple implementations of regmap_read & regmap_write
is trivial. The access size is presumed to be 4 bytes & endianness is
presumed native, which are the defaults for the regmap code in Linux.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agonet: pch_gbe: Make 64 bit safe
Paul Burton [Thu, 8 Sep 2016 06:47:34 +0000 (07:47 +0100)]
net: pch_gbe: Make 64 bit safe

The pch_gbe driver previously casted pointers to & from unsigned 32 bit
integers in many locations. This breaks the driver on 64 bit systems,
producing streams of compiler warnings about mismatched pointer &
integer sizes and then failing to keep track of addresses correctly at
runtime.

Fix the driver for 64 bit systems by using unsigned longs in place of
the previously used 32 bit integers.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: pch_gbe: Use dm_pci_map_bar to discover MMIO base
Paul Burton [Thu, 8 Sep 2016 06:47:33 +0000 (07:47 +0100)]
net: pch_gbe: Use dm_pci_map_bar to discover MMIO base

Reading the PCI BAR & converting the result to a physical address is not
safe across all architectures. For example on MIPS the virtual:physical
mapping is not 1:1, so we cannot directly make use of the physical
address.

Use the more generic BAR-mapping function dm_pci_map_bar to discover the
MMIO base address, which should work across architectures.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agopci: Flip condition for detecting non-PCI parent devices
Paul Burton [Thu, 8 Sep 2016 06:47:32 +0000 (07:47 +0100)]
pci: Flip condition for detecting non-PCI parent devices

In pci_uclass_pre_probe an attempt is made to detect whether the parent
of a device is a PCI device and that the device is thus a bridge. This
was being done by checking whether the parent of the device is of the
UCLASS_ROOT class. This causes problems if the PCI controller is a child
of some other non-PCI node, for example a simple-bus node.

For example, if the device tree contains something like the following
then pci_uclass_pre_probe would incorrectly believe that the PCI
controller is a bridge, with a PCI parent:

  / {
    some_child {
      compatible = "simple-bus";
      #address-cells = <1>;
      #size-cells = <1>;
      ranges = <>;

      pci_controller: pci@10000000 {
        compatible = "my-pci-controller";
        device_type = "pci";
        reg = <0x10000000 0x2000000>;
      };
    };
  };

Avoid this incorrect detection of bridges by instead checking whether
the parent devices class is UCLASS_PCI and treating a device as a bridge
when this is true, making use of device_is_on_pci_bus to perform this
test.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agopci: xilinx: Add a driver for Xilinx AXI to PCIe bridge
Paul Burton [Thu, 8 Sep 2016 06:47:31 +0000 (07:47 +0100)]
pci: xilinx: Add a driver for Xilinx AXI to PCIe bridge

This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe ECAM specification, but with some
quirks about what devices are valid to access.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agodt-bindings: Add interrupt-controller/mips-gic.h header
Paul Burton [Thu, 8 Sep 2016 06:47:30 +0000 (07:47 +0100)]
dt-bindings: Add interrupt-controller/mips-gic.h header

Import a copy of the dt-bindings/interrupt-controller/mips-gic.h header
from Linux, such that we can use device trees which include it without
modification.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoserial: ns16550: Support clocks via phandle
Paul Burton [Thu, 8 Sep 2016 06:47:29 +0000 (07:47 +0100)]
serial: ns16550: Support clocks via phandle

Previously ns16550 compatible UARTs probed via device tree have needed
their device tree nodes to contain a clock-frequency property. An
alternative to this commonly used with Linux is to reference a clock via
a phandle. This patch allows U-Boot to support that, retrieving the
clock frequency by probing the appropriate clock device.

For example, a system might choose to provide the UART base clock as a
reference to a clock common to multiple devices:

  sys_clk: clock {
    compatible = "fixed-clock";
    #clock-cells = <0>;
    clock-frequency = <10000000>;
  };

  uart0: uart@10000000 {
    compatible = "ns16550a";
    reg = <0x10000000 0x1000>;
    clocks = <&sys_clk>;
  };

  uart1: uart@10000000 {
    compatible = "ns16550a";
    reg = <0x10001000 0x1000>;
    clocks = <&sys_clk>;
  };

This removes the need for the frequency information to be duplicated in
multiple nodes and allows the device tree to be more descriptive of the
system.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoclk: Use dummy clk_get_by_* functions when CONFIG_CLK is disabled
Paul Burton [Thu, 8 Sep 2016 06:47:28 +0000 (07:47 +0100)]
clk: Use dummy clk_get_by_* functions when CONFIG_CLK is disabled

The implementations of clk_get_by_index & clk_get_by_name are only
available when CONFIG_CLK is enabled. Provide the dummies when this is
not the case in order to avoid build failures.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoMIPS: Ensure cache ops complete in mips_cache_reset
Paul Burton [Wed, 21 Sep 2016 10:18:59 +0000 (11:18 +0100)]
MIPS: Ensure cache ops complete in mips_cache_reset

Ensure that cache operations complete before returning from
mips_cache_reset by placing a completion barrier (sync instruction)
before the return. Without this there is no guarantee that the cache ops
will complete before any subsequent memory accesses, since they are
indexed cache ops & thus not implicitly ordered with memory accesses.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Clear hazard between TagLo writes & cache ops
Paul Burton [Wed, 21 Sep 2016 10:18:58 +0000 (11:18 +0100)]
MIPS: Clear hazard between TagLo writes & cache ops

Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Ensure Config.K0=2 applies before any memory accesses
Paul Burton [Wed, 21 Sep 2016 10:18:57 +0000 (11:18 +0100)]
MIPS: Ensure Config.K0=2 applies before any memory accesses

During boot we set Config.K0=2 (uncached) such that any accesses to the
kseg0 memory region are performed uncached before the caches are
initialised. This write to the Config register introduces an execution
hazard between it & any following memory accesses (such as the load of
_gp), which we need to clear in order to ensure those memory accesses
are actually performed uncached. Clear this execution hazard with the
insertion of an ehb execution hazard barrier instruction.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Malta: Enable CM & L2 support
Paul Burton [Wed, 21 Sep 2016 10:18:56 +0000 (11:18 +0100)]
MIPS: Malta: Enable CM & L2 support

Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Join the coherent domain when a CM is present
Paul Burton [Wed, 21 Sep 2016 10:18:55 +0000 (11:18 +0100)]
MIPS: Join the coherent domain when a CM is present

MIPS Linux expects the bootloader to leave the boot CPU a member of the
coherent domain when running on a system with a CM, and we will need to
do so if we wish to make use of IOCUs to have cache-coherent DMA in
U-Boot (and on some systems there is no choice in that matter). When a
CM is present, join the coherent domain after completing cache
initialisation.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: L2 cache support
Paul Burton [Wed, 21 Sep 2016 10:18:54 +0000 (11:18 +0100)]
MIPS: L2 cache support

This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.

If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Map CM Global Control Registers
Paul Burton [Wed, 21 Sep 2016 10:18:53 +0000 (11:18 +0100)]
MIPS: Map CM Global Control Registers

Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Define register names for cache init
Paul Burton [Wed, 21 Sep 2016 10:18:52 +0000 (11:18 +0100)]
MIPS: Define register names for cache init

Define names for registers holding cache sizes throughout
mips_cache_reset, in order to make the code easier to read & allow for
changing register assignments more easily.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: If we don't need DDR for cache init, init cache first
Paul Burton [Wed, 21 Sep 2016 10:18:51 +0000 (11:18 +0100)]
MIPS: If we don't need DDR for cache init, init cache first

On systems where cache initialisation doesn't require zeroed memory (ie.
systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined)
perform cache initialisation prior to lowlevel_init & DDR
initialisation. This allows for DDR initialisation code to run cached &
thus significantly faster.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Preserve Config implementation-defined bits
Paul Burton [Wed, 21 Sep 2016 10:18:50 +0000 (11:18 +0100)]
MIPS: Preserve Config implementation-defined bits

The coprocessor 0 Config register includes 9 implementation defined
bits, which in some processors do things like enable write combining or
other functionality. We ought not to wipe them to 0 during boot. Rather
than doing so, preserve their value & only clear the bits standardised
by the MIPS architecture.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Enable use of the instruction cache earlier
Paul Burton [Wed, 21 Sep 2016 10:18:49 +0000 (11:18 +0100)]
MIPS: Enable use of the instruction cache earlier

Enable use of the instruction cache immediately after it has been
initialised. This will only take effect if U-Boot was linked to run from
kseg0 rather than kseg1, but when this is the case the data cache
initialisation code will run cached & thus significantly faster.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: Probe cache line sizes once during boot
Paul Burton [Wed, 21 Sep 2016 10:18:48 +0000 (11:18 +0100)]
MIPS: Probe cache line sizes once during boot

Rather than probing the cache line sizes on every call of any cache
maintenance function, probe them once during boot & store the values in
the global data structure for later use. This will reduce the overhead
of the cache maintenance functions, which isn't a big deal yet but
becomes more important once L2 caches which may expose their properties
via coprocessor 2 or the CM are supported.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoMIPS: ath79: Use mach_cpu_init instead of arch_cpu_init
Paul Burton [Wed, 21 Sep 2016 10:18:47 +0000 (11:18 +0100)]
MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init

In order to prepare for MIPS arch code making use of arch_cpu_init in a
later patch, stop using it from ath79 SoC code & instead use the new
mach_cpu_init which is provided for this purpose.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
8 years agoboard_f: Add a mach_cpu_init callback
Paul Burton [Wed, 21 Sep 2016 10:18:46 +0000 (11:18 +0100)]
board_f: Add a mach_cpu_init callback

Currently we have a mismash of architectures which use arch_cpu_init
from architecture-wide code (arc, avr32, blackfin, mips, nios2, xtensa)
and architectures which use arch_cpu_init from machine/SoC level code
(arm, x86).

In order to clean this mess up & allow for both use cases, introduce a
new mach_cpu_init callback which is run immediately after arch_cpu_init.
This will allow for architectures to have arch-wide code without needing
individual machines to all implement their own arch_cpu_init with a call
to some common function.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agomips: Add MIPSfpga platform support
Zubair Lutfullah Kakakhel [Fri, 29 Jul 2016 14:11:20 +0000 (15:11 +0100)]
mips: Add MIPSfpga platform support

MIPSfpga is an FPGA based dev platform.

In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks

The FPGA dev board used is the Nexys4DDR board by Digilent.

For more information, check the Readme file in board/imgtec/xilfpga

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agomips: xilfpga: Add device tree files
Zubair Lutfullah Kakakhel [Fri, 29 Jul 2016 14:11:19 +0000 (15:11 +0100)]
mips: xilfpga: Add device tree files

Mostly the same as the Kernel upstream device tree file except for

- alias for the serial console node
- ethernet node as the ethernet stuff isn't upstream on kernel.org yet
- uart clock-frequency passed directly in the node

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agonet: emaclite: Enable driver for MIPS
Zubair Lutfullah Kakakhel [Wed, 27 Jul 2016 11:25:09 +0000 (12:25 +0100)]
net: emaclite: Enable driver for MIPS

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: emaclite: use __raw_readl/writel instead of weird define
Zubair Lutfullah Kakakhel [Wed, 27 Jul 2016 11:25:08 +0000 (12:25 +0100)]
net: emaclite: use __raw_readl/writel instead of weird define

out_be32 and in_be32 are actually #defined to little endian
writel/readl in arch/microblaze.

Just use __raw_writel/readl instead. That is also what is used
in the Linux kernel driver for this IP block

Tested on MIPSfpga. Can tftp a kernel.

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agonet: emaclite: Use ioremap_nocache
Zubair Lutfullah Kakakhel [Wed, 27 Jul 2016 11:25:07 +0000 (12:25 +0100)]
net: emaclite: Use ioremap_nocache

Virtual to physical mapping isn't necessarily 1:1 for all architectures

Using ioremap_nocache allows for the arch code to translate the
physical address to a virtual address.

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agommc: dw_mmc: push/pop all FIFO data if any data request
Jacob Chen [Mon, 19 Sep 2016 02:16:50 +0000 (10:16 +0800)]
mmc: dw_mmc: push/pop all FIFO data if any data request

When DTO interrupt occurred, there are any remaining data still in FIFO
due to RX FIFO threshold is larger than remaining data. It also
causes that dwmmc didn't trigger RXDR interrupt, so is TX.

It's responsibility of driver to read remaining bytes on seeing DTO
interrupt.

Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
8 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Tue, 20 Sep 2016 13:34:53 +0000 (09:34 -0400)]
Merge git://git.denx.de/u-boot-dm

8 years agoPowerPC: Update last users of CONFIG_ISO_STRING to Kconfig
Tom Rini [Tue, 20 Sep 2016 02:02:46 +0000 (22:02 -0400)]
PowerPC: Update last users of CONFIG_ISO_STRING to Kconfig

There are a few boards that use CONFIG_ISO_STRING as part of a sanity
check during firmware update at run time.  Move this string to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoPowerPC: Update MIP405/MIP405T to use Kconfig better
Tom Rini [Tue, 20 Sep 2016 01:55:34 +0000 (21:55 -0400)]
PowerPC: Update MIP405/MIP405T to use Kconfig better

Convert CONFIG_MIP405T from SYS_EXTRA_OPTIONS to a real config

There are two boards, MIP405 and MIP405T that have a few differences.
Start by checking for CONFIG_TARGET_MIP405.  Then introduce
CONFIG_TARGET_MIP405T and use that not CONFIG_MIP405T.  Next, convert
also convert the usage of CONFIG_ISO_STRING to be based on Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoKconfig: Move config IDENT_STRING to Kconfig
Siva Durga Prasad Paladugu [Fri, 29 Jul 2016 10:01:47 +0000 (15:31 +0530)]
Kconfig: Move config IDENT_STRING to Kconfig

Move the config IDENT_STRING to Kconfig and migrate all boards

[sivadur: Migrate zynq boards]
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[trini: Update configs, add some default to sunxi Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoconfigs: Re-sync
Tom Rini [Mon, 19 Sep 2016 21:00:58 +0000 (17:00 -0400)]
configs: Re-sync

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agommc: sdhci: Add the programmable clock mode support
Wenyou Yang [Sun, 18 Sep 2016 01:01:22 +0000 (09:01 +0800)]
mmc: sdhci: Add the programmable clock mode support

Add the programmable clock mode for the clock generator.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
8 years agommc: sd: optimize erase
Peng Fan [Thu, 1 Sep 2016 03:13:39 +0000 (11:13 +0800)]
mmc: sd: optimize erase

To SD, there is no erase group, then the value erase_grp_size
will be default 1. When erasing SD blocks, the blocks will be
erased one by one, which is time consuming.

We use AU_SIZE as a group to speed up the erasing.

Erasing 4MB with a SD2.0 Card with AU_SIZE 4MB.
`time mmc erase 0x100000 0x2000`
time: 44.856 seconds (before optimization)
time: 0.335 seconds  (after optimization)

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Stephen Warren <swarren@nvidia.com>
8 years agommc: sd: extracting erase related information from sd status
Peng Fan [Thu, 1 Sep 2016 03:13:38 +0000 (11:13 +0800)]
mmc: sd: extracting erase related information from sd status

Add function to read SD_STATUS information.
According to the information, get erase_timeout/erase_size/erase_offset.
Add a structure sd_ssr to include the erase related information.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Clemens Gruber <clemens.gruber@pqgruber.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Stephen Warren <swarren@nvidia.com>
8 years agommc: sdhci: drop CONFIG_ from CONFIG_SDHCI_CMD_MAX_TIMEOUT
Masahiro Yamada [Thu, 25 Aug 2016 07:07:39 +0000 (16:07 +0900)]
mmc: sdhci: drop CONFIG_ from CONFIG_SDHCI_CMD_MAX_TIMEOUT

No need for per-SoC adjustment for this parameter.  It should be
determined by the slowest hardware.  Currently, no board overrides
this CONFIG, so 3.2 sec is large enough.  (If not, we can make it
even larger.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agommc: sdhci: drop CONFIG_ from CONFIG_SDHCI_CMD_DEFAULT_TIME
Masahiro Yamada [Thu, 25 Aug 2016 07:07:38 +0000 (16:07 +0900)]
mmc: sdhci: drop CONFIG_ from CONFIG_SDHCI_CMD_DEFAULT_TIME

This CONFIG is not configurable since it is not guarded by #ifndef.
Nobody has complained about that, so there is no need to keep it as
a CONFIG option.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agommc: sdhci: move SDMA capability check to sdhci_setup_cfg()
Masahiro Yamada [Thu, 25 Aug 2016 07:07:37 +0000 (16:07 +0900)]
mmc: sdhci: move SDMA capability check to sdhci_setup_cfg()

If CONFIG_BLK is enabled, add_sdhci() is never called.  Move this
quirk handling to sdhci_setup_cfg(), which is now the central place
for hardware capability checks.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agommc: sdhci: move broken voltage quirk handling to sdhci_setup_cfg()
Masahiro Yamada [Thu, 25 Aug 2016 07:07:36 +0000 (16:07 +0900)]
mmc: sdhci: move broken voltage quirk handling to sdhci_setup_cfg()

If CONFIG_BLK is enabled, add_sdhci() is never called.  Move this
quirk handling to sdhci_setup_cfg(), which is now the central place
for hardware capability checks.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agommc: sdhci: move error message to more relevant place
Masahiro Yamada [Thu, 25 Aug 2016 07:07:35 +0000 (16:07 +0900)]
mmc: sdhci: move error message to more relevant place

"Hardware doesn't specify base clock frequency" may not be only the
error case of sdhci_setup_cfg().  It is better to print this where
the corresponding error is triggered.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agommc: sdhci: move sdhci_reset() call to sdhci_init()
Masahiro Yamada [Thu, 25 Aug 2016 07:07:34 +0000 (16:07 +0900)]
mmc: sdhci: move sdhci_reset() call to sdhci_init()

If CONFIG_BLK is enabled, add_sdhci() is never called.
So, sdhci_reset() is not called, either.  This is a problem for
my board as it needs the reset to start from a sane state.

Move the add_sdhci() call to sdhci_init(), which is visited
by both of the with/without CONFIG_BLK cases.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
8 years agoRevert "Increase default of CONFIG_SYS_MALLOC_F_LEN for SPL_OF_CONTROL"
Masahiro Yamada [Mon, 19 Sep 2016 12:40:26 +0000 (21:40 +0900)]
Revert "Increase default of CONFIG_SYS_MALLOC_F_LEN for SPL_OF_CONTROL"

This reverts commit 90c08d9e08c7a108ab904f3bbdeb558081757892.

I took a closer look at this after the commit was applied, and found
CONFIG_SYS_MALLOC_F_LEN=0x2000 was too much.  8KB memory for SPL is
actually too big for some boards.  Perhaps 0x800 is enough, but the
situation varies board by board.

Let's postpone our decision until we come up with a better idea.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoA20-OLinuXino-Lime2: Enable USB gadget support
Tom Rini [Mon, 19 Sep 2016 14:03:32 +0000 (10:03 -0400)]
A20-OLinuXino-Lime2: Enable USB gadget support

Based on A13-OLinuXino, enable DFU and UMS support.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
8 years agodtoc: Add methods for reading data from properties
Simon Glass [Tue, 26 Jul 2016 00:59:18 +0000 (18:59 -0600)]
dtoc: Add methods for reading data from properties

Provide easy helpers for reading integer, string and boolean values from
device-tree properties.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodtoc: Correct quotes in fdt_util
Simon Glass [Tue, 26 Jul 2016 00:59:17 +0000 (18:59 -0600)]
dtoc: Correct quotes in fdt_util

The style is to use single quotes for strings where possible. Adjust this
function.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodtoc: Support finding the offset of a property
Simon Glass [Tue, 26 Jul 2016 00:59:16 +0000 (18:59 -0600)]
dtoc: Support finding the offset of a property

Add a way to find the byte offset of a property within the device tree. This
is only supported with the normal libfdt implementation since fdtget does
not provide this information.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodtoc: Support packing the device tree
Simon Glass [Tue, 26 Jul 2016 00:59:15 +0000 (18:59 -0600)]
dtoc: Support packing the device tree

After any node/property deletion the device tree can be packed to remove
spare space. Add a way to perform this operation.

Note that for fdt_fallback, fdtput automatically packs the device tree after
deletion, so no action is required here.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodtoc: Support deleting device tree properties
Simon Glass [Tue, 26 Jul 2016 00:59:14 +0000 (18:59 -0600)]
dtoc: Support deleting device tree properties

Add support for deleting a device tree property. With the fallback
implementation this uses fdtput. With libfdt it uses the API call and
updates the offsets afterwards.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodtoc: Move to using bytearray
Simon Glass [Tue, 26 Jul 2016 00:59:13 +0000 (18:59 -0600)]
dtoc: Move to using bytearray

Since we want to be able to change the in-memory device tree using libfdt,
use a bytearray instead of a string. This makes interfacing from Python
easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodtoc: Prepare for supporting changing of device trees
Simon Glass [Tue, 26 Jul 2016 00:59:12 +0000 (18:59 -0600)]
dtoc: Prepare for supporting changing of device trees

For binman we need to support deleting properties in the device tree. This
will change the offsets of nodes after the deletion. In preparation, add
code to keep track of when the offsets are invalid, and regenerate them.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodtoc: Drop the convert_dash parameter to GetProps()
Simon Glass [Tue, 26 Jul 2016 00:59:11 +0000 (18:59 -0600)]
dtoc: Drop the convert_dash parameter to GetProps()

This is not used anywhere in dtoc, so drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodtoc: Allow the device tree to be compiled from source
Simon Glass [Tue, 26 Jul 2016 00:59:10 +0000 (18:59 -0600)]
dtoc: Allow the device tree to be compiled from source

If a source device tree is provide to the Fdt() constructors, compile it
automatically. This will be used in tests, where we want to build a
particular test .dts file and check that it works correctly in binman.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agopatman: Add a library to handle logging and progress
Simon Glass [Tue, 26 Jul 2016 00:59:09 +0000 (18:59 -0600)]
patman: Add a library to handle logging and progress

When tools want to display information of varying levels of importance, it
helps to provide the user with control over the verbosity of these messages.
Progress messages work best if they are displayed and then removed from the
display when no-longer relevant.

Add a new tout library (terminal out) to handle these tasks.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agopatman: Add a tools library for using temporary files
Simon Glass [Tue, 26 Jul 2016 00:59:08 +0000 (18:59 -0600)]
patman: Add a tools library for using temporary files

For tools which want to use input files and temporary output, it is useful
to have the handling of these dealt with in one place. Add a new library
which allows input files to be read, and output files to be written, all
based on a common directory structure.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodtoc: Move a few more common functions into fdt.py
Simon Glass [Tue, 26 Jul 2016 00:59:07 +0000 (18:59 -0600)]
dtoc: Move a few more common functions into fdt.py

Some functions have the same code in the subclasses. Move these into the
superclass to avoid duplication.

Signed-off-by: Simon Glass <sjg@chromium.org>