Ley Foon Tan [Thu, 14 Jun 2018 10:45:23 +0000 (18:45 +0800)]
net: designware: Add reset ctrl to driver
Add code to reset all reset signals as in Ethernet DT node. A reset
property is an optional feature, so only print out a warning and do not
fail if a reset property is not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Ley Foon Tan [Thu, 14 Jun 2018 10:45:21 +0000 (18:45 +0800)]
mmc: dwmmc: socfpga: Add reset ctrl to driver
Add code to reset all reset signals as in mmc DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Peter Robinson [Sun, 10 Jun 2018 05:17:46 +0000 (06:17 +0100)]
tegra: nyan-big: Update CONFIG_SYS_TEXT to the default in README.chromium
To build U-Boot on a Nyan Big Chromebook the docs outline adjusting the Tegra124
defined CONFIG_SYS_TEXT_BASE but this has since been moved to individual config
files. We should have the default required for U-Boot chain loading on the
chromebook as the default CONFIG_SYS_TEXT_BASE and update the docs to remove
this now non required step.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Andre Przywara [Wed, 4 Jul 2018 23:57:48 +0000 (00:57 +0100)]
sunxi: A64: OHCI: prevent turning off shared USB clock
On the A64 the clock for the first USB controller is actually the parent
of the clock for the second controller, so turning them off in that order
makes the system hang.
Fix this by only turning off *both* clocks when the *last* OHCI controller
is brought down. This covers the case when only one controller is used.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
When using CONFIG_OF_BOARD on rpi to use the dtb provided by the
RaspberryPi Fundation, the compatible string isn't the same, resulting
in not-functional usb from u-boot.
The Allwinner A64 SoCs suffers from an arch timer implementation erratum,
where sometimes the lower 11 bits of the counter value erroneously
become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and
backwards, with the latter one often showing weird behaviour.
Port the workaround proposed for Linux to U-Boot and activate it for all
A64 boards.
This fixes crashes when accessing MMC devices (SD cards), caused by a
recent change to actually use the counter value for timeout checks.
Fixes: 5ff8e54888e4d26a352453564f7f599d29696dc9 ("sunxi: improve throughput
in the sunxi_mmc driver")
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Andreas Färber <afaerber@suse.de> Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
Andre Przywara [Wed, 27 Jun 2018 00:42:52 +0000 (01:42 +0100)]
arm: timer: factor out FSL arch timer erratum workaround
At the moment we have the workaround for the Freescale arch timer
erratum A-008585 merged into the generic timer_read_counter() routine.
Split those two up, so that we can add other errata workaround more
easily. Also add an explaining comment on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Andreas Färber <afaerber@suse.de> Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
Alexander Graf [Fri, 15 Jun 2018 08:29:29 +0000 (10:29 +0200)]
ax25: Switch to CONFIG_BOOTP_PREFER_SERVERIP
The ax25-ae350 target currently uses CONFIG_BOOTP_SERVERIP which means we
ignore the DHCP provided TFTP ip address. This breaks every case where we
do now provide a serverip environment variable.
Instead, let's use the new CONFIG_BOOT_PREFER_SERVERIP option to fall back
to the DHCP provided TFTP IP if no serverip environment variable is set.
Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Rick Chen <rick@andestech.com>
Alexander Graf [Fri, 15 Jun 2018 08:29:28 +0000 (10:29 +0200)]
net: Add option to prefer bootp/dhcp serverip
Currently we can choose between 2 different types of behavior for the
serverip variable:
1) Always overwrite it with the DHCP server IP address (default)
2) Ignore what the DHCP server says (CONFIG_BOOTP_SERVERIP)
This patch adds a 3rd option:
3) Use serverip from DHCP if no serverip is given
(CONFIG_BOOTP_PREFER_SERVERIP)
With this new option, we can have the default case that a boot file gets
loaded from the DHCP provided TFTP server work while allowing users to
specify their own serverip variable to explicitly use a different tftp
server.
Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Alexander Graf [Fri, 15 Jun 2018 08:29:27 +0000 (10:29 +0200)]
net: Prefer command line arguments
We can call commands like dhcp and bootp without arguments or with
explicit command line arguments that really should tell the code where
to look for files instead.
Unfortunately, the current code simply overwrites command line arguments
in the dhcp case with dhcp values.
This patch allows the code to preserve the command line values if they
were set on the command line. That way the semantics are slightly more
intuitive.
The reason this patch does that by introducing a new variable is that we
can not rely on net_boot_file_name[0] being unset, as today it's
completely legal to call "dhcp" and afterwards run "tftp" and expect the
latter to repeat the same query as before. I would prefer not to break
that behavior in case anyone relies on it.
Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Lothar Felten [Fri, 22 Jun 2018 20:29:54 +0000 (22:29 +0200)]
net: Add new wol command - Wake on LAN
Add a new command 'wol': Wait for an incoming Wake-on-LAN packet or
time out if no WoL packed is received.
If the WoL packet contains a password, it is saved in the environment
variable 'wolpassword' using the etherwake format (dot or colon
separated decimals).
Intended use case: a networked device should boot an alternate image.
It's attached to a network on a client site, modifying the DHCP server
configuration or setup of a tftp server is not allowed.
After power on the device waits a few seconds for a WoL packet. If a
packet is received, the device boots the alternate image. Otherwise
it boots the default image.
This method is a simple way to interact with a system via network even
if only the MAC address is known. Tools to send WoL packets are
available on all common platforms.
Some Ethernet drivers seem to pad the incoming packet. The additional
padding bytes might be recognized as Wake-on-LAN password bytes.
By default enabled in pengwyn_defconfig.
Signed-off-by: Lothar Felten <lothar.felten@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Alex Kiernan [Fri, 15 Jun 2018 05:06:00 +0000 (05:06 +0000)]
net: fastboot: Fix build when FASTBOOT_FLASH is disabled
When building without FASTBOOT_FLASH we don't include the intermediate
update callback to keep the client alive, so ensure we don't try setting
it here.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When using CONFIG_OF_BOARD on rpi to use the dtb provided by the
RaspberryPi Fundation, the compatible string isn't the same, resulting
in not-functional video in u-boot.
Tom Rini [Mon, 2 Jul 2018 02:10:33 +0000 (22:10 -0400)]
Revert "fw_printenv: Don't bail out directly after one env read error"
As pointed out by Wolfgang Denk, the problem with this fix is that while
interactive users will see that we have found one part of the
environment failed and are using the other, progmatic use will not see
this and can lead to problems.
Bin Meng [Thu, 28 Jun 2018 03:38:02 +0000 (20:38 -0700)]
efi_loader: Increase number of configuration tables to 16
At present the number of configuration tables is set to 2. By
looking at which tables the Linux EFI stub or iPXE can process,
it looks 16 is a reasonable number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Ivan Gorinov [Fri, 22 Jun 2018 04:16:16 +0000 (21:16 -0700)]
x86: Use microcode update from device tree for all processors
Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies
the microcode update data block encoded in Device Tree to the bootstrap
processor but not passed to the other CPUs when multiprocessing is enabled.
If the bootstrap processor successfully performs a microcode update
from Device Tree, use the same data block for the other processors.
Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed build errors on edison and qemu-x86] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Sat, 23 Jun 2018 10:03:47 +0000 (03:03 -0700)]
x86: timer: tsc: Allow specifying clock rate from device tree again
With the introduction of early timer support in the TSC driver,
the capability of getting clock rate from device tree was lost
unfortunately. Now we bring such functionality back, but with a
limitation that when TSC is used as early timer, specifying clock
rate from device tree does not work.
This fixes random boot failures seen on QEMU targets: printing "TSC
frequency is ZERO" and reset forever.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Nishanth Menon [Tue, 12 Jun 2018 20:24:11 +0000 (15:24 -0500)]
ARM: mach-omap2: omap3/am335x: Enable ACR::IBE on Cortex-A8 SoCs for CVE-2017-5715
Enable CVE-2017-5715 option to set the IBE bit. This enables kernel
workarounds necessary for the said CVE.
With this enabled, Linux reports:
CPU0: Spectre v2: using BPIALL workaround
This workaround may need to be re-applied in OS environment around low
power transition resume states where context of ACR would be lost (off-mode
etc).
Nishanth Menon [Tue, 12 Jun 2018 20:24:09 +0000 (15:24 -0500)]
ARM: Introduce ability to enable invalidate of BTB with ICIALLU on Cortex-A15 for CVE-2017-5715
As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB)
needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to
be done unconditionally for Cortex-A15 processors. Provide a config
option for platforms to enable this option based on impact analysis
for products.
NOTE: This patch in itself is NOT the final solution, this requires:
a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
provide direct access to ACR register.
b) Operating Systems such as Linux to provide adequate workaround in the
right locations.
c) This workaround applies to only the boot processor. It is important
to apply workaround as necessary (context-save-restore) around low
power context loss OR additional processors as necessary in either
firmware support OR elsewhere in OS.
Nishanth Menon [Tue, 12 Jun 2018 20:24:08 +0000 (15:24 -0500)]
ARM: Introduce ability to enable ACR::IBE on Cortex-A8 for CVE-2017-5715
As recommended by Arm in [1], IBE[2] has to be enabled unconditionally
for BPIALL to be functional on Cortex-A8 processors. Provide a config
option for platforms to enable this option based on impact analysis
for products.
NOTE: This patch in itself is NOT the final solution, this requires:
a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
provide direct access to ACR register.
b) Operating Systems such as Linux to provide adequate workaround in the right
locations.
c) This workaround applies to only the boot processor. It is important
to apply workaround as necessary (context-save-restore) around low
power context loss OR additional processors as necessary in either
firmware support OR elsewhere in OS.
Jagan Teki [Thu, 28 Jun 2018 14:10:46 +0000 (19:40 +0530)]
usb: sunxi: Use proper reg_mask for clock gate, reset
Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.
unfortunately these are fixed due to lack of separate
clock, reset drivers.
Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.
This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.
We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Zeng Tao [Thu, 28 Jun 2018 17:54:19 +0000 (01:54 +0800)]
usb: ohci: change the NUM_EDs from 8 to 32
For ohci, the maximam supported endpoint number is 32(in and out), and
now we have used (usb_pipeendpoint(pipe) << 1) to index the specified
endpoint descritor, usb_pipeendpoint(pipe) can reach 0xf, so we need
change the NUM_EDs from 8 to 32.
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Marek Vasut [Thu, 24 May 2018 19:58:45 +0000 (21:58 +0200)]
sf: Enable FSR polling on N25Q256(A)
The N25Q256(A) datasheet clearly states that this device does have
a Flag Status Register and does update FSR PEC bit 7 during Program
and Erase cycles to indicate the cycle is in progress. Enable the
FSR PEC bit polling on this device to prevent data corruption.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@openedev.com> Cc: Tom Rini <trini@konsulko.com>
Hannes Schmelzer [Tue, 26 Jun 2018 14:08:39 +0000 (16:08 +0200)]
spi: omap3: fix claim/release bus within DM
The claim/release bus function must not reset the whole SPI core because
settings regarding wordlen, clock-frequency and so on made by
set_wordlen, set_mode, set_speed get lost with this action. Resulting in
a non-functional SPI.
Without DM the failure didn't came up since after the spi_reset within
claim bus all the setup (wordlen, mode, ...) was called, in DM they are
called by the spi uclass.
We change now the things as following for having a working SPI instance
in DM:
- move the spi_reset(...) to the probe call in DM for having a known
hardware state after probe. Without DM we don't have a probe call, so we
issue the reset as before during the claim_bus call.
- in release bus we just reset the modulctrl to the reset-value (spi-
slave)
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Jagan Teki <jagan@openedev.com>
Andrew Thomas [Mon, 18 Jun 2018 18:56:06 +0000 (11:56 -0700)]
dwc2 USB controller hangs with lan78xx
This bug is the combination of dwc2 USB controller and lan78xx
USB ethernet controller, which is the combination in use on
the Raspberry Pi Model 3 B+.
When the host attempts to receive a packet, but a packet has not
arrived, the lan78xx controller responds by setting BIR
(Bulk-In Empty Response) to NAK. Unfortunately, this hangs
the USB controller and requires the USB controller to
be reset.
The fix proposed is to have the lan78xx controller respond
by setting BIR to ZLP.
Signed-off-by: Andrew Thomas <andrew.thomas@oracle.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Alexander Graf <agraf@suse.de>
Joe Hershberger [Tue, 26 Jun 2018 09:37:59 +0000 (12:37 +0300)]
fw_printenv: Don't bail out directly after one env read error
When using a redundant environment a read error should simply mean to
not use that copy instead of giving up completely. The other copy may
be just fine.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Ioan-Adrian Ratiu <adrian.ratiu@ni.com>
Jörg Krause [Sun, 14 Jan 2018 18:26:40 +0000 (19:26 +0100)]
mtd: nand: mxs_nand_spl: add mxs_flash_full_ident
For now, the existing SPL MXS NAND driver only supports to identify
ONFi-compliant NAND chips. In order to allow identifying
non-ONFi-compliant chips add `mxs_flash_full_ident()` which uses the
`nand_get_flash_type()` functionality from `nand_base.c` to lookup
for supported NAND chips in the chip ID list.
For compatibility reason the full identification support is only
available if the config option `CONFIG_SPL_NAND_IDENT` is enabled.
The lookup was tested on a custom i.MX6ULL board with a Toshiba
TC58NVG1S3HTAI0 NAND chip.
Jörg Krause [Sun, 14 Jan 2018 18:26:39 +0000 (19:26 +0100)]
mtd: nand: mxs_nand_spl: refactor mxs_flash_ident
The existing `mxs_flash_ident()` is limited to identify ONFi compliant
NAND chips only. In order to support non-ONFi NAND chips refactor the
function and rename it to `mxs_flash_onfi_ident()`.
A follow-up patch will add `mxs_flash_full_ident()` which allows to use
the chip ID list to lookup for supported NAND flashs.
Jörg Krause [Sun, 14 Jan 2018 18:26:37 +0000 (19:26 +0100)]
mtd: nand: export nand_get_flash_type function
`nand_get_flash_type()` allows identification of supported NAND flashs.
The function is useful in SPL (like mxs_nand_spl.c) to lookup for a NAND
flash (which does not support ONFi) instead of using nand_simple.c and
hard-coding all required NAND parameters.
Since commit 1da1938d57b3 ("spl: Add default values for ARCH_MX7")
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is selected by default on
i.MX7 platforms, so remove it from the board defconfig.
Jagan Teki [Mon, 18 Jun 2018 05:42:19 +0000 (11:12 +0530)]
imx6ul: geam: Fix fdt_file mismatch
fdt_file is looking for imx6ul-geam-kit.dtb but Linux
has imx6ul-geam.dtb, since Linux skipped -kit on file name
by below commit.
"ARM: dts: imx6ul-geam: Skip suffix -kit from dts name"
(sha1: 182de5ebce71e469cfa686fcdf08c9cbe11ece97)
So, due to this mismatch U-Boot failed to pick the
proper dtb which eventually break the Linux boot.
This patch fixed this mismatch by
- renaming dts files
- update config option to use new dtb file
- update fdt_file to new dtb file name
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
The PFUZE3000 uses registers addresses up to 0xff.
The DM pfuze100 driver supports both pfuze100 and pfuze3000. Allow it
to use the device type to return the correct number of registers.
Also rename the too generic PMIC_NUM_OF_REGS enumeration value for
pfuze3000 to match the other "PFUZE3000_" prefixed enumerations and the
pfuze100 enumeration value PFUZE100_NUM_OF_REGS.
Stefan Agner [Fri, 22 Jun 2018 16:06:18 +0000 (18:06 +0200)]
mtd: nand: mxs_nand: add support for specific ECC strength
Add support for specified ECC strength/size using device tree
properties nand-ecc-strength/nand-ecc-step-size.
This aligns behavior with the mainline driver, such that:
- If fsl,use-minimal-ecc is requested it will use data from
data sheet/ONFI. If this is not available the driver will fail.
- If nand-ecc-strength/nand-ecc-step-size are specified those
value will be used.
- By default maximum possible ECC strength is used
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Stefan Agner [Fri, 22 Jun 2018 15:19:51 +0000 (17:19 +0200)]
mtd: nand: mxs_nand: add minimal ECC support
Add support for minimum ECC strength supported by the NAND chip.
This aligns with the behavior when using the fsl,use-minimum-ecc
device tree property in Linux.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Report correct ECC parameters back to the stack. Do not report
bytes as we have it not immeaditly available and the Linux version
also does not report it. It seems to have no aversive effect.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Stefan Agner [Fri, 22 Jun 2018 15:19:49 +0000 (17:19 +0200)]
mtd: nand: mxs_nand: use structure for BCH geometry
Calculate BCH geometry at start and store the information in
a structure. This avoids recalculation on every page access
and allows to calculate ECC relevant information in one place.
This patch does not change ECC layout or driver behavior in
any way.
The patch aligns the driver somewhat with the Linux GPMI NAND
driver which drives the same IP.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Stefan Agner [Fri, 22 Jun 2018 15:19:48 +0000 (17:19 +0200)]
mtd: nand: mxs_nand: allow to enable BBT support
Add config option which allows to enable on flash bad block table
support. This has the same effect as when using the device tree
property "nand-on-flash-bbt" in Linux.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Stefan Agner [Fri, 22 Jun 2018 15:19:46 +0000 (17:19 +0200)]
mtd: nand: mxs_nand: introduce SPL specific init
In preparation to convert the driver to use NAND self init
provide a new minimal init for SPL builds. As a side effect
this also reduces size of SPL by about 4KiB.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
- ignored the responsible arguments (speed, mode)
The set speed/mode function must use the supplied function arguments to
work properly. With this commit we take those arguments and transfer
them to the priv-data.
- used wrong udevice pointer for getting priv data
the udevice-pointer within function argument is already the spi-bus
device, so it is wrong looking here for some parent (ocp-bus in this
case) and getting priv-pointer from there.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Jagan Teki <jagan@openedev.com>
Bin Meng [Fri, 22 Jun 2018 08:38:30 +0000 (01:38 -0700)]
x86: efi: payload: Count in conventional memory above 4GB in DRAM bank
At present in dram_init_banksize() it ignores conventional memory
above 4GB. This leads to wrong DRAM size is printed during boot.
Remove such limitation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
projects / u-boot / log