Antonio Borneo [Mon, 2 Jul 2018 16:47:34 +0000 (18:47 +0200)]
gdb_server: set current_target from connection's one
In a multi-target environment we are supposed to have a single
gdb server for each target (or for each group of targets within
a SMP node).
By default, the gdb attached to a server sends its command to
the target (or to the SMP node targets) linked to that server.
This is working fine for the normal gdb commands, but it is
broken for the native OpenOCD commands executed through gdb
"monitor" command. In the latter case, gdb "monitor" commands
will be executed on the current target of OpenOCD configuration
script (that is either the last target created or the target
specified in a "targets" command).
Fixed in gdb_new_connection() by replacing the current target
in the connection's copy of command context.
Change-Id: If7c8f2dce4a3138f0907d3000dd0b15e670cfa80 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4586 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Christopher Head <chead@zaber.com>
Antonio Borneo [Mon, 25 Jun 2018 13:09:31 +0000 (15:09 +0200)]
gdb_server: only trigger once the event gdb-detach at gdb quit
When GDB quits (e.g. with "quit" command) we first execute
gdb_detach() to reply "OK" then, at GDB disconnect (either TCP
or pipe connection type), we execute gdb_connection_closed().
In case GDB is killed or it crashes, OpenOCD only executes the
latter when detects the disconnection.
Both gdb_detach() and gdb_connection_closed() trigger the event
TARGET_EVENT_GDB_DETACH thus getting it triggered twice on clean
GDB quit.
Do not trigger the event TARGET_EVENT_GDB_DETACH in gdb_detach()
and let only gdb_connection_closed() to handle it.
Change-Id: Iacf035c855b8b3e2239c1c0e259c279688b418ee Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4585 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Omair Javaid [Wed, 23 May 2018 12:43:47 +0000 (17:43 +0500)]
Add ARM v8 AArch64 semihosting support
This patch implements semihosting support for AArch64. This picks
code from previously submitted AArch64 semihosting support patch
and rebases on top of reworked semihosting code. Tested in AArch64
mode on a Lemaker Hikey Board with NewLib and GDB.
Antonio Borneo [Thu, 22 Jan 2015 15:12:46 +0000 (23:12 +0800)]
target: fix 'bp' command help message
"asid" and "length" are separate arguments of the command.
Put space between them.
Change-Id: I36cfc1e3a01caafef4fc3b26972a0cc192b0b963 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4511 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Christopher Head [Mon, 14 May 2018 20:08:24 +0000 (13:08 -0700)]
flash/nor/stm32h7: Fix incorrect comment
The name of the bit according to the reference manual is inconsistency
error, not increment error.
Change-Id: Ie3b73c0312db586e35519e03fd1a5cb225673d97 Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4521 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Christopher Head [Mon, 14 May 2018 20:06:39 +0000 (13:06 -0700)]
flash/nor/stm32: Eliminate working area leak
On a specific early-return path, an allocated working area was not
freed. Free it.
Change-Id: I7c8fe51ff475f191624086996be1c77251780b77 Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4520 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Christopher Head [Mon, 14 May 2018 18:56:56 +0000 (11:56 -0700)]
flash/nor/stm32: Report errors in wait_status_busy
Flash operation errors that occur during algorithm programming are
reported via the algorithm return value. However, Flash operation
errors that occur during non-algorithm work (erasing, programming
without a work area, programming the last non-multiple-of-32-bytes on
an H7, etc.) generally end with a call to stm32x_wait_status_busy,
which reads the status register and clears the error flags but fails
to actually report that something went wrong should an error flag
(other than WRPERR) be set. Return an error status from
stm32x_wait_status_busy in those cases. Correct a log message
accordingly.
Change-Id: I09369ea5f924fe58833aec1f45e52320ab4aaf43 Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4519 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Antonio Borneo [Tue, 29 May 2018 21:40:36 +0000 (23:40 +0200)]
target/cortex_m: return error if breakpoint address is out of range
If the "Flash Patch and Breakpoint" unit is rev.1 then it can only
accept breakpoint addresses below 0x1FFFFFFF.
Detailed info in "ARM v7-M Architecture Reference Manual", DDI0403E
at chapter "C1.11 Flash Patch and Breakpoint unit".
Print a message and return error if the address of hardware
breakpoint cannot be handled by the breakpoint unit.
Change-Id: I95c92b1f058f0dfc568bf03015f99e439b27c59b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4535 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Christopher Head <chead@zaber.com>
Antonio Borneo [Sat, 23 Jun 2018 13:12:46 +0000 (15:12 +0200)]
jtag/drivers/cmsis-dap: fix connect in cmsis_dap_swd_switch_seq()
The proc cmsis_dap_swd_switch_seq() is part of the SWD API for
this interface driver. It is valid only when the interface is
used in SWD mode.
In this proc there is the need to call, in sequence, first
cmsis_dap_cmd_DAP_Disconnect() then cmsis_dap_cmd_DAP_Connect().
The latter call requires the connection mode as parameter, that
inside cmsis_dap_swd_switch_seq() can only be CONNECT_SWD.
The current implementation is not correct and in some cases can
pass mode CONNECT_JTAG. Moreover, JTAG is optional in CMSIS-DAP
and passing mode CONNECT_JTAG triggers an error with SWD-only
interfaces.
Use mode CONNECT_SWD in SWD specific cmsis_dap_swd_switch_seq().
Change-Id: Ib455bf5b69cb2a2d146a6c8875387b00c27a5690 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4571 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add configuration for the Renesas R-Car R8A7794 E2
based Silk evaluation board.
Change-Id: I504b5630b1a2791ed6967c6c2af8851ceef9723f Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
---
NOTE: This requires SW7[1] in position 1 (default is 0)
Reviewed-on: http://openocd.zylin.com/4532 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Antonio Borneo [Fri, 15 Jun 2018 14:30:41 +0000 (16:30 +0200)]
target/arm_adi_v5: sync CSW and TAR cache on apreg write
When using apreg to change AP registers CSW or TAR we get internal
cached value not valid anymore.
Reuse the setup functions for CSW and TAR to write them.
Invalidate the cached value before the call to force the write, thus
keeping original apreg behaviour.
Change-Id: Ib14fafd5e584345de94f2e983de55406c588ac1c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4565 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
James Marshall [Wed, 17 Jan 2018 02:08:16 +0000 (21:08 -0500)]
target/arm: Add PLD command to ARM disassembler.
Updates the ARM disassembler to handle PLD (PreLoad Data) commands.
Previously handled by printing a TODO message. There are three forms of
the command: literal, register, and immediate. Simply decode based off
of the A1 encoding for the instructions in the ARM ARM. Also fixes mask
to handle PLDW commands.
Change-Id: I63bf97f16af254e838462c7cfac80f6c4681c556 Signed-off-by: James Marshall <jcmarsh@gwmail.gwu.edu>
Reviewed-on: http://openocd.zylin.com/4348 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Antonio Borneo [Mon, 11 Jun 2018 08:29:52 +0000 (10:29 +0200)]
flash/nor/psoc5lp: fix compile issue on GCC 8.1.0
Issue already identified by Alex https://sourceforge.net/u/alexbour/
in ticket #191 https://sourceforge.net/p/openocd/tickets/191/
src/flash/nor/psoc5lp.c:237:2: error: ‘strncpy’ output
truncated before terminating nul copying 2 bytes from a
string of the same length [-Werror=stringop-truncation]
Fix it by assigning the value to the array elements.
Change-Id: I22468e5700efa64ea48ae8cdec930c48b4a7d8fb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4563 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tomas Vanek [Mon, 12 Mar 2018 22:42:23 +0000 (23:42 +0100)]
tcl/target/stm32f7x: configure faster system clock in reset-init
STM32F7xx devices need faster clock for flash programming
over JTAG transport. Using reset default 16 MHz clock
resulted in lot of DAP WAITs and substantial decrease
of flashing performance.
Change-Id: Ida6915331dd924c9c0d08822fd94c04ad408cdc5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4464 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com>
Edward Fewell [Fri, 19 Jan 2018 02:48:11 +0000 (20:48 -0600)]
flash/nor: Add support for TI CC26xx/CC13xx flash
Added cc26xx flash driver to support the TI CC26xx and CC13xx
microcontrollers. Driver is capable of determining which MCU
is connected and configures itself accordingly. Added config
files for four specific variants: CC26x0, CC13x0, CC26x2, and
CC13x2.
Note that the flash loader code is based on the sources used
to support flash in Code Composer Studio and Uniflash from TI.
Removed cc26xx.cfg file made obsolete by this patch.
Change-Id: Ie2b0f74f8af7517a9184704b839677d1c9787862 Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4358 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
Change #3432 was merged into git master without adapting it
to #4297 "prepare infrastructure for multi-block blank check".
This is a fast fix of PSoC5LP specific blank check.
Not tested on real PSoC5LP device.
Change-Id: I7dc13ee7bd1f07b2bfe5a93a5030c0c482d30f00 Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4557 Tested-by: jenkins
Edward Fewell [Tue, 5 Jun 2018 16:17:40 +0000 (11:17 -0500)]
drivers: xds110: Remove unnecessary and deprecated libusb function.
libusb-1.0.22 has deprecated the libusb_set_debug function. This
function was present in the XDS110 driver as an artifact left over
from early debugging. It isn't required because logging is disabled
by default. Removing it to simplify the code and no longer need to
have libusb version specific #if's in the code.
Change-Id: I9c3f16c039da3f3fad9c4a1169978b0d85a1b45c Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4553 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
Andreas Färber [Sat, 30 Apr 2016 13:10:05 +0000 (15:10 +0200)]
flash/nor: Add PSoC 5LP flash driver
Always probe for ECC mode and display ECC sectors if disabled.
Non-ECC write is implemented as zeroing the ECC/config bytes.
Erasing ECC sectors is ignored, erase-checking takes them into account.
Tested with CY8CKIT-059 (CY8C5888), except ECC mode.
Change-Id: If63b9ffca7ad8de038be3c086c49712b629ec554 Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-on: http://openocd.zylin.com/3432 Tested-by: jenkins
Edward Fewell [Thu, 28 Dec 2017 23:38:21 +0000 (17:38 -0600)]
flash/nor: Add support for TI CC3220SF internal flash
Added cc3220sf flash driver to support the TI CC3220SF
microcontrollers. Implemented flash driver to support the
internal flash of the CC3220SF. The implementation does not
support the serial flash of the CC32xx family that requires
connection over UART, and not via JTAG/SWD debug. Added config
files for both CC32xx devices (no flash) and CC3220SF (with
flash).
Updated to implement comments from code review.
Additional updates to handle remaining comments from review.
Additional updates per review.
Added code to only request aligned writes and full 32-bit
words down to flash helper algorithm. Updated for recent
changes in OpenOCD flash code.
Removed cc32xx.cfg file made obsolete by this patch.
Change-Id: I58fc1478d07238d39c7ef02339f1097a91668c47 Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4319 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Omair Javaid [Thu, 31 May 2018 00:36:53 +0000 (05:36 +0500)]
Fix Semihosting FileIO for targets using vcont packet
This patch fixes a bug where target fails to resume after completing GDB FileIO.
We need to update target last run control information to decide resumption. This
was not being done for vcont packets.
Christopher Head [Fri, 27 Apr 2018 01:09:36 +0000 (18:09 -0700)]
target/cortex_m: constify some variables
Change-Id: I1f3fddd89597333fc1bb9535c0cd76ca3e008324 Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4503 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
flash/nor/core: fix double-free crash with 'virtual' flash banks
flash_bank structure of 'virtual' flash driver is a full copy of
the master flash_bank structure including bank->sectors and
bank->prot_blocks pointers. These pointers point to memory
locations allocated by the master driver and thus master driver
is responsible for deallocating them.
Do not free bank->sectors and bank->prot_blocks of 'virtual'
driver since they were already released by master flash driver.
Antonio Borneo [Sun, 27 May 2018 15:37:38 +0000 (17:37 +0200)]
target: fix syntax in help message
The name of the command is already printed before the string
in ->usage, thus it appears twice.
E.g.
> help examine
stm32f4x.cpu arp_examine arp_examine ['allow-defer']
used internally for reset processing
stm32f4x.cpu examine_deferred examine_deferred
used internally for reset processing
stm32f4x.cpu was_examined was_examined
used internally for reset processing
Remove the command name from the string in ->usage.
Liviu Ionescu [Sun, 13 May 2018 15:39:06 +0000 (18:39 +0300)]
Rework/update ARM semihosting
In 2016, ARM released the second edition of the semihosting specs
("Semihosting for AArch32 and AArch64"), adding support for 64-bits.
To ease the reuse of the semihosting logic for other platforms
(like RISC-V), the semihosting code was isolated from the ARM
target and updated to the latest specs.
The new code is already in use since January (in GNU MCU Eclipse
OpenOCD) and no problems were reported, neither for ARM nor for
RISC-V targets, after more than 7K downloads.
Edward Fewell [Tue, 2 Jan 2018 21:27:51 +0000 (15:27 -0600)]
jtag/drivers: Add support for TI XDS110 debug probe
Add support for the XDS110 debug probe using the APIs in the
probe's firmware. Includes support for older versions of the
firmware (with reduced performance) and support for a newer
version that includes OpenOCD specific APIs. Tested on various
TI LauchPads including MSP432P4, MSP432E4, CC2650, CC2652, and
CC3220SF.
Updated to add better support for swd switch. Removed issues found with
clang static analysis.
Updated to add rules entry for the XDS110 probe and Tiva DFU mode (which
affects both XDS110 and ICDI probes).
Philipp Tomsich [Fri, 27 Apr 2018 17:59:56 +0000 (19:59 +0200)]
arm_dpm: flush both scratch registers (R0 and R1)
Neither the initial loop to clear dirty registers (which visits all
registers starting at R2 and counting upwards) nor the final explicit
flushes ensure a write-back in arm_dpm_write_dirty_registers.
This change makes sure that both our scratch registers (i.e. R0 and
R1) are written back to the target.
Faisal Shah [Tue, 10 Apr 2018 03:46:45 +0000 (22:46 -0500)]
ChibiOS thread states: Update thread state to label mapping
Fixed style issue.
Removed #define with list of strings, and just put the
strings in the array initialization directly.
Removed empty space at the start of line.
Change-Id: I76580be203d7d69b8c5b5440f820156543e0d5cc Signed-off-by: Faisal Shah <faisal.shah@gmail.com>
Reviewed-on: http://openocd.zylin.com/4488 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Bohdan Tymkiv [Wed, 21 Mar 2018 14:13:28 +0000 (16:13 +0200)]
psoc6: Run flash algorithm asynchronously to improve performance
Existing psoc6 driver starts flash algorithm for each Flash row. This is
suboptimal from performance point of view, starting/stopping flash
algorithm for each row adds significant overhead. This change starts
flash algorithm and leaves it running asynchronously while driver
performs flash operations.
Performance gain is 170...250% depending on probe:
board: add configuration for stm32f103c8 "Blue Pill"
The "Blue Pill" is a popular development board with an STM32F103C8
micro controller. According to sources, it has a 128kB Flash on board
even though the option bytes only report 64kB. This patch therefore also
modifies target/stm32f1x.cfg to take an optional FLASH_SIZE variable into
account which the board file sets to 0x20000.
Marek Vasut [Wed, 11 Apr 2018 15:15:01 +0000 (17:15 +0200)]
tcl/target: Add Renesas R-Car R8A7790 H2 target
Add configuration for the Renesas R-Car R8A7790 H2 target.
This is an SoC with four Cortex A15 and four Cortex A7
ARMv7a cores, only the four A15 cores are supported.
Tomas Vanek [Thu, 22 Feb 2018 23:12:50 +0000 (00:12 +0100)]
target/cortex_m: allow setting the type of a breakpoint
Cortex-M target used 'auto_bp_type' mode. The requested type
of breakpoint was ignored and hard (FPB) breakpoints were set in
'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above
0x20000000.
The code memory area of Cortex-M does not mean the memory is flash and
vice versa. External flash (parallel or QSPI) is usually mapped above
code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis
has a RAM block under 0x20000000 boundary.
Remove 'auto_bp_type' mode, set breakpoints to requested type.
Change 'cortex_m maskisr auto' handling to use a hard temporary
breakpoint everywhere: it can also workaround not working soft breakpoints
on Cortex-M7 with ICache enabled.
tcl/board: add board configuration for NXP IMX7SABRE
configuration also contains a reset-init procedure that disables the
watchdog and initilizes the boards DDR memory so that you can upload
baremetal (e.g. boot loader) code into DDR and start it from there.
Tomas Vanek [Thu, 15 Feb 2018 09:18:37 +0000 (10:18 +0100)]
flash/nor/at91sam: implement flash bank deallocation for SAM series
Microchip (former Atmel) SAM drivers allocate a struct per chip.
at91sam3, at91sam34:
Deallocate all chip structs from the list at once, on the first bank
deallocation.
at91samd and at91sam4l drivers do not handle more than one bank.
Convert them to simple driver_priv allocation and use
default_flash_free_driver_priv().
Change-Id: I49d7200f38a4568c7e12f306c27d1b1b72646736 Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4416 Tested-by: jenkins
Tomas Vanek [Sat, 10 Feb 2018 12:07:56 +0000 (13:07 +0100)]
flash/nor: handle flash write alignment/padding in the infrastructure
Most of flash drivers have to ensure proper flash write block alignment
and padding. As there was no support for it in the flash infrastructure,
each driver does it its own way. Sometimes this part of code is not properly
tested and contains bugs.
flash_write(_unlock) joins all image sections targeted to one flash bank
using padded areas as a glue. This solves alignment problems on section
boundaries but imposes other problems.
Introduce new flash bank parameters write_start_alignment,
write_end_alignment and minimal_write_gap.
New flash drivers can just properly set these values instead of handling
alignment by its own.
Adapt infrastructure (namely flash_write_unlock(), handle_flash_fill_command()
and handle_flash_write_bank_command()) to prepare write data padded
to an alignment required by the flash bank.
Rework flash_write_unlock() to discontinue write block when the gap
between sections is bigger than minimum specified in minimal_write_gap.
minimal_write_gap is set to one sector by default.
Change-Id: I4368dd402dfaf51c193bcbf1332cffff092b239b Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4399 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Tomas Vanek [Thu, 23 Nov 2017 08:18:24 +0000 (09:18 +0100)]
target, flash: prepare infrastructure for multi-block blank check
'flash erase_check' command runs a check algorithm on a target
if possible. The algorithm is run repeatedly for each flash sector.
Unfortunately every start and stop of the algorithm impose not negligible
overhead.
In practice it means checking is faster than plain read only for
sectors of size approx 4 kByte or bigger. And checking sectors
as short as 512 bytes runs approx 4 times slower than plain read.
The patch changes API call target_blank_check_memory() and related
to take an array of sectors (or arbitrary memory blocks).
Changes in target-specific checking routines are kept minimal.
They use only the first block from the array and process it by
the unchanged algorithm.
default_flash_blank_check() routine repeats target_blank_check_memory()
until all blocks are checked, so it works with both multi-block
and single-block based checkers.
Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4297 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Structures rtos_standard_Cortex_M4F_stacking and
rtos_standard_Cortex_M4F_FPU_stacking in rtos_standard_stackings.c
where using rtos_standard_Cortex_M3_stack_align for the stack-align
function. This function calls rtos_Cortex_M_stack_align with
XPSR_OFFSET = 0x3c. This offset is correct for cortex-M3 but not for
cortex-M4F and cortex-M4F with fpu. This patch adds stack_align
functions for M4F an M4F_FPU
Change-Id: If6a90b1898fccbb85619a10f3aef5277dd88ce47 Signed-off-by: Armin van der Togt <armin@otheruse.nl>
Reviewed-on: http://openocd.zylin.com/4037 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
On SMP targets, the "target smp" command creates a list of targets
that belong to the SMP cluster. Free this list when a target gets
destroyed on shutdown. For simplicity, the complete list is free'd as
soon as the first target of the SMP cluster is destroyed instead of
individually removing targets from the list.
Tim Newsome [Tue, 6 Mar 2018 22:10:04 +0000 (14:10 -0800)]
Add gdb_report_register_access_error command
With this option enabled (it's disabled by default) errors accessing
registers are returned to gdb. Otherwise they are ignored and success is
reported to gdb. (This is the current behavior.)
We want this for RISC-V, but there's still some cleanup that needs to be
done before that can be upstreamed.
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I7e56109ea52d18b780c14a07fb35f9e6e8979da4
Reviewed-on: http://openocd.zylin.com/4452 Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
arm_adi_v5: Add ability to ignore the CSYSPWRUPACK bit
The CTRL/STAT register in the ARM DAP DP has a debug power up
ack bit and a system power up ack bit. Some devices do not set
the system power up ack bit until sometime later. To avoid having
the initial target examination fail due to this or to have a
sticky bit error report claim power failure due to this a user
can now specify that this bit should be ignored.
Stefan Arnold [Tue, 17 Oct 2017 08:50:13 +0000 (10:50 +0200)]
flash/nor/at91samd: Add "nvmuserrow" command.
Add option "nvmuserrow" to "at91samd" for changing and reading the register at 0x804000 which represents various fuses.
Change-Id: I6382cc4ac15e6b9681e2f30b0ae60397a6289c3b Signed-off-by: Stefan Arnold <sarnold@sh-sw.de>
Reviewed-on: http://openocd.zylin.com/4260 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tomas Vanek [Wed, 21 Feb 2018 21:19:58 +0000 (22:19 +0100)]
drivers/kitprog: workaround KitProg firmware bug of missing ZLP
KitProg firmware does not send a zero length packet at the end of the bulk-in
transmission of a length divisible by a bulk packet size. This is inconsistent
with the USB specification and results in jtag_libusb_bulk_read()
waits forever when a transmission of specific size is received.
Limit bulk read size to expected number of bytes for problematic tranfer sizes.
Use 1 second timeout as the last resort.
Cody P Schafer [Wed, 7 Mar 2018 16:31:35 +0000 (11:31 -0500)]
target/cortex_m: avoid dwt comparator overflow
Avoid ever overflowing the DWT_COMPARATOR array by allocating space for
16 comparators (the field is masked by 0xf).
On a stm32f767zi chip (on a nucleo-767zi board) I've been seeing crashes
with address sanitizer enabled due to its (apparent) 10 present
comparators. This appears to be due to
https://sourceforge.net/p/openocd/tickets/178/.
In non-address sanitizer builds, this would likely cause some random
memory to be written to in some cases. (see above bug for observations).
Change-Id: I2b7d599eb326236dbc93f74b350c442c9a502c4b Signed-off-by: Cody P Schafer <openocd@codyps.com>
Reviewed-on: http://openocd.zylin.com/4458 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Robert Jordens [Mon, 5 Feb 2018 11:54:29 +0000 (11:54 +0000)]
xilinx-dna.cfg: generic tools for reading Xilinx Device DNA
Most Xilinx FPGA devices contain an embedded, unique device identifier.
The identifier is nonvolatile, permanently programmed into the FPGA, and is
unchangeable providing a great serial / tracking number.
This commit adds generic support for reading the Xilinx Spartan 6 and 7
Series (Kintex, Artix, Ultrascale) Device DNA. The code is similar to
the function in fpga/xilinx-xc6s.cfg for Spartan 6 but the register
addresses are different and the logic has been simplified.
The code was not placed in xilinx-xc7.cfg. The approach of defining taps
in the same file as library code to use them is fundamentally broken on
boards that have more than one FPGA or other chips. This commit (like
the addition of support for Xilinx XADC) starts to remedy that by
splitting library code from board-specific fixed definitions.
The support code is sourced in the Kasli and KC705 board support files
as it was tested on these boards.
Robert Jordens [Mon, 29 Jan 2018 20:12:37 +0000 (21:12 +0100)]
tcl/fpga/xilinx-xadc.cfg: add support for XADC
The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
temperature, internal power supply rail voltages as well as external
voltages. The XADC is available both from fabric as well as through the
JTAG TAP.
This code implements access throught the JTAG TAP.
Robert Jordens [Mon, 15 Jan 2018 10:53:48 +0000 (10:53 +0000)]
tcl/board: add support for Kasli
Kasli is an open hardware FPGA board. It is part of the Sinara family of
devices designed to control quantum physics experiments (see Sayma_AMC
for other boards already suppported by openocd).
Kasli was developed as part of the opticlock project. It features a
Xilinx Artix 7 100T FPGA, DDR3 RAM, a clock reconstruction and
distribution network, four 6 Gb/s transceiver links (three SFP and
one SATA) as well as interfaces to up to 12 Eurocard Extension Modules
(EEMs).
Robert Jordens [Thu, 3 Aug 2017 10:25:07 +0000 (12:25 +0200)]
xilinx-xcu: add Xilinx Ultrascale tap data
The Ultrascale series is a bit more complicated to handle since with the
stacked and interconnected dies the IR gets longer. This adds support
for all currently known chips from the Ultrascale family.
- add 'dap create' command to create dap instances
- move all dap subcmmand into the dap instance commands
- keep 'dap info' for convenience
- change all armv7 and armv8 targets to take a dap
instance instead of a jtag chain position
- restructure tap/dap/target relations, jtag tap no
longer references the dap, daps are now independently
created and initialized.
- clean up swd connect
- re-initialize DAP also on JTAG errors (e.g. after reset,
power cycle)
- update documentation
- update target files
Extend the CTI abstraction to be accessible from TCL and
change the 'target' command to accept a cti 'object' instead of a
base address. This also allows accessing CTI instances that are not
related to a configured target.
If we enter debug state from EL0, some registers are not accessible.
Temporarily move to EL1H and back to gain access. Also, fix
armv8_dpm_modeswitch() to not immediately restore the previous state
on elevating the privilege level.
gdb_server: fake step if thread is not current rtos thread
gdb assumes that a rtos can make any thread active at will in response
to a 'Hg' packet. It further assumes that it needs to step-over after
setting a breakpoint on frame #0 of any non-current thread. Both
assumptions are not valid for an actual rtos. We fake the step-over to
not trigger an internal error in gdb. See
https://sourceware.org/bugzilla/show_bug.cgi?id=22925 for details.
projects / openocd / log