On live hardware, interrupts will happen while the core is
held for stepping. The next step will most of the time execute an
interrupt service instead of the next line of code, which is not
what you expect. Disable interrupts through DSCR before resuming
for a step, and re-enable them again after the step happened.
This should be made configurable, like on cortex_a target.
According to gdb documentation, a register "cpsr" is expected if
aarch64 features are announced. Also, the value buffer must be
capable of holding a 64bit value (8 byte, not 4)
Reduce complexity of memory access functions, anyway there are no ARMv8
platforms that actually contain an AHB-AP at all. while at it, fix
virt-to-phys function signatures to expect target_addr_t.
- armv8 EDSCR has no ITR_EN bit, ITR is always enabled. Writes to this
bit are ignored but we should not do them anyway
- use dpmv8 function to report the reason for debug entry
- WFAR is a 64bit register
Use configured CTI base address instead of hardcoded value, if
available.
Use symbolic constants instead of raw hex offsets.
Trim halt and resume code to what is actually necessary.
aarch64: fix context and hybrid hardware breakpoints
Fix 64bit address setting
Fix register spacing (16 instead of 4)
Set HMC bit for all but linked context match breakpoints,
where the bit is ignored anyway
target: add -ctibase config option in addition to -dbgbase
Some vendors don't fully populate the ROM table, e.g. BCM2357 (used in
Raspberry Pi 3) doesn't list CTI, however it is mandatory for halting
an ARMv8 core and therefore it's always present (and required),
regardless of the ROM table listing it or not.
David Ung [Mon, 20 Apr 2015 20:14:43 +0000 (13:14 -0700)]
aarch64: Correct target state for hardware step
When using hardware step for doing stepping, the existing DSCR records
the event as external debug request. This will generate a SIGINT event
to GDB and causes it to stop the stepping process.
For aarch64, read DESR to check if the event is a hardware step and set
state to DBG_REASON_SINGLESTEP.
With this patch, GDB can now do source level stepping.
Change-Id: I1d06f819578c74b3ac17376c67f882adddea1f52 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
pierre Kuo [Thu, 23 Apr 2015 21:44:27 +0000 (14:44 -0700)]
aarch64: Add instruction stepping support using hardware step
Use AARCH64's hardware step event to do stepping.
Change-Id: I2d029ceeadd381913d0c3355c8787b11dacff7f7 Signed-off-by: pierre Kuo <vichy.kuo@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
pierre Kuo [Tue, 17 Mar 2015 19:44:04 +0000 (12:44 -0700)]
aarch64: Add hardware breakpoint support
Enable the use of hardware breakpoint on AARCH64.
Change-Id: I59caaa6d92ac60278af8938625b1790a1787372f Signed-off-by: pierre Kuo <vichy.kuo@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
David Ung [Fri, 16 Jan 2015 01:22:20 +0000 (17:22 -0800)]
aarch64: Add ARMv8 AARCH64 support files
Add new AARCH64 target and ARMv8 support files.
This is an instantiation from the cortex_a files but modified to support
64bit ARMv8. Not all features are complete, notably breakpts and single
stepping are not yet implemented.
Currently it lets you halt of the processors, resume, dump cpu
registers,
read/write memory and getting a stack trace with gdb.
> halt
invalid mode value encountered 5
target state: halted
unrecognized psr mode: 0x5
target halted in ARM state due to debug-request, current mode:
UNRECOGNIZED
cpsr: 0x600001c5 pc: 0x00093528
MMU: disabled, D-Cache: disabled, I-Cache: disabled
> targets
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* cpu0 aarch64 little cpu.dap halted
(gdb) bt
#0 cpu_do_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/mm/proc.S:87
#1 0xffffffc000085114 in arch_cpu_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/kernel/process.c:107
#2 0x0000000000000000 in ?? ()
Change-Id: Iccb1d15c7d8ace7b9e811dac3c9757ced4d0f618 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Define a target_addr_t type to support 32-bit and 64-bit addresses at
the same time. Also define matching TARGET_PRI*ADDR format macros as
well as a convenient TARGET_ADDR_FMT.
In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000)
be least invasive by leaving the formatting unchanged apart from the
type;
for generic code adopt TARGET_ADDR_FMT as unified address format.
Don't silently change gdb formatting here, leave that to later.
Add COMMAND_PARSE_ADDRESS() macro to abstract the address type.
Implement it using its own parse_target_addr() function, in the hopes
of catching pointer type mismatches better.
Add '--disable-target64' configure option to revert to previous 32-bit
target address behavior.
Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com>
[AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This bug was already attempted to fix in an earlier patch but
merging the "defer-examine" feature caused a regression, which this patch
tries to fix again.
Paul Fertser [Sat, 7 Jan 2017 18:51:32 +0000 (21:51 +0300)]
jtag: core: report TRST and SRST as asserted only when they really are
When SRST is never enabled, the global jtag_srst variable is left at its
initial state, that is, -1, and it does _not_ mean SRST is currently
asserted. Same about TRST.
Fixes "reset halt" in cases when srst_pulls_trst but srst usage is not
enabled.
Change-Id: I8d2e9120479de4cfbf5561033926c9ef945eecc9 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3943 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tomas Vanek [Thu, 22 Dec 2016 20:47:20 +0000 (21:47 +0100)]
flash/nor: fix doc/help and range test for flash protect
Commit 77a1c01ccbb1150ffe749a7373cf6c4dc15ecad0 introduced infrastructure
for utilizing protection blocks of different size than erase sector.
Parts of doc/help kept reading 'sector' instead of 'protection block'.
flash_driver_protect() parameter range testing did not switched
to bank->num_prot_blocks.
This change fixes it.
Change-Id: Iec301761190a1a1bcc4cb005a519b9e5e4fede51 Reported-by: Mark Odell <mark@odell.ws> Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3917 Tested-by: jenkins Reviewed-by: Mark Odell <mrfirmware@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
These libraries override the used CFLAGS without adding the
defaults. This didn't have any effect until change
http://openocd.zylin.com/3870 (ef4c139). Restore by adding
AM_CLAGS to the per-target CFLAGS.
Interestingly, automake seems to clear the CFLAGS for the target
even if the override variable is only mentioned within a non-active
conditional branch, such as the IS_MINGW for the affected libraries.
Change-Id: I805206865e59e3fa33a7ea3c0d3472e51219351c Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3927 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This seems to be a leftover from borrowing from omap3* configs. Since
SJC is not enabling or disabling the DAP tap, and the tap is always
available, the extra tapenable command causes warnings on startup
(can't enable what's already enabled).
Change-Id: I7514436d565aa5b91876dbdab547956f36dcab77 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3892 Tested-by: jenkins
Paul Fertser [Mon, 12 Dec 2016 08:50:17 +0000 (11:50 +0300)]
target: cortex_a: fix segfault when SPSR is not properly handled
OpenOCD doesn't (yet) know how to handle HYP mode properly so spsr
register is not getting initialised when OpenOCD connects to a target
stopped in this mode.
Search for scripts relative to the executable on all(?) platforms
Add a helper to hide the platform-dependent method to get a
canonical, absolute, /-separated path to the executable.
Use this and the relative path from BINDIR to PKGDATADIR to
construct a search path that finds the scripts even if the
installation dir is moved, as long as the structure below $prefix
is maintained.
This method should fully support all the tricks you can to with
autotools to customize the installed layout such as overriding the
default directories at configure-time and overriding the configured
directories at build-time.
The exe path detection methods are combined from
http://openocd.zylin.com/3388 by Rick Foos and
http://openocd.zylin.com/3537 by Steven Stallion, as well as tips
found all over internet.
Change-Id: Ifc9cc9dd0bf52fbd67b1b0f2383318cda0c422c4 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Signed-off-by: Steven Stallion <sstallion@gmail.com>
Reviewed-on: http://openocd.zylin.com/3889 Tested-by: jenkins Reviewed-by: Rick Foos <rfoos@solengtech.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Paul Fertser [Tue, 16 Aug 2016 06:52:28 +0000 (09:52 +0300)]
jimtcl: update to 0.77, the current version, enable only specific modules
This is needed to fix build on aarch64 to get updated config.guess.
Because some newer JimTcl modules that get enabled are failing to
build on some of the platforms OpenOCD supports, enable only a
fixed set that shouldn't cause any issues.
We also disable running Jim Tcl tests on distcheck because they never
worked (before 85358e479e5bbf295a5aaf743f3c29a5e1a4fd1c Jim commit)
but didn't break Jenkins build; with newer version they're getting run
and fail due to limited permissions for filesystem and networking
operations.
Change-Id: I0b6c6a00bf2cf0902bbb01c9c0224fe93c74ac94 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3700 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
board: add configuration for freescale twr-vf65gs10 system module
This patch contains configuration for the twr-vf65gs10 system module
of the Freescale (NXP) tower system. It provides support for both the
CMSIS-DAP available via USB and the Cortex+ETM connector
on J5. The configuration also contains DDR and clock init code
hooked into the reset-init event handler.
Change-Id: I68303e0038e137dcadc57525e662428769fb69f2 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3564 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
CFLAGS is a user variable and shouldn't be set in either
configure.ac or Makefile.am because that makes it impossible to
override compiler flags at configure or make time.
AC_SUBST the default warning flags into AM_CFLAGS instead, which
is emitted before CFLAGS on the compiler command line.
Do the same thing with a mingw-specific flag as well.
Change-Id: I6ac3a3c8b7e0abf6f0e60ea239b549d68ea6d370 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3870 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Marc Schink [Wed, 30 Sep 2015 16:58:19 +0000 (18:58 +0200)]
jlink: Add EMUCOM support
EMUCOM is a way to communicate with a J-Link device via so called
channels. A channel can either be read or written in a single
operation.
Beside the reserved channels for SEGGER, there are channels available to
implement vendor and/or device specific functionalities. For example,
EMUCOM is used on many starter and development kits from Silicon Labs to
access power measurements and various other information and settings.
Change-Id: I6094109c043b34aed4a40ceabe71f30ff896bf1d Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3794 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
kevin [Mon, 17 Oct 2016 11:46:26 +0000 (12:46 +0100)]
flash/nor/efm32: Support flash size smaller than 32k
The current implementation fails on devices with less than 32k of
flash (such as several devices in the Zero Gecko family) because
the 'assert' assumes (incorrectly) that the number of flash banks
will always be >= 32.
This change ensures that at least one word of lock bits is always read
in order to support devices with less than 32k of flash.
Signed-off-by: Kevlar Harness <software@klystron.com>
Change-Id: I59febe2cb690c893a5057a5f72918e146cf2afe4
Reviewed-on: http://openocd.zylin.com/3806 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Change b0698501b0e789091e9f9f1427b32af304888769 fixed
reset for i.MX6 and TI Sitara SoCs but broke reset for
cortex-a targets that use SWD. This patch is a work-
around that forces asserting SRST when SWD is used.
This patch adds a Cortex-M private configuration option
that allows setting the acess point during target
creation. This circumvents situations in hybrid systems
when the correct access point can not be automatically
detected.
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