]> git.sur5r.net Git - u-boot/log
u-boot
6 years agosunxi: imply CONFIG_OF_LIBFDT_OVERLAY
Andre Heider [Tue, 16 Jan 2018 08:44:22 +0000 (09:44 +0100)]
sunxi: imply CONFIG_OF_LIBFDT_OVERLAY

fdt overlay support is useful for all sunxi boards, enable per default
and remove it from sunxi defconfigs.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agonet: regex: Disable by default on sunXi
Maxime Ripard [Tue, 16 Jan 2018 08:44:21 +0000 (09:44 +0100)]
net: regex: Disable by default on sunXi

The sunXi arm64 build has overflown, leading to the main U-boot binary
overwriting the environment when flashing the new image, or even worse,
overwriting itself when we're calling saveenv.

Disable this option that is not critical until we can adress the issue
properly.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agovideo: bpp16: Disable by default on sunXi
Maxime Ripard [Tue, 16 Jan 2018 08:44:20 +0000 (09:44 +0100)]
video: bpp16: Disable by default on sunXi

The sunXi arm64 build has overflown, leading to the main U-boot binary
overwriting the environment when flashing the new image, or even worse,
overwriting itself when we're calling saveenv.

Disable this command that is not critical until we can adress the issue
properly.

Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agovideo: bpp8: Disable by default on sunXi
Maxime Ripard [Tue, 16 Jan 2018 08:44:19 +0000 (09:44 +0100)]
video: bpp8: Disable by default on sunXi

The sunXi arm64 build has overflown, leading to the main U-boot binary
overwriting the environment when flashing the new image, or even worse,
overwriting itself when we're calling saveenv.

Disable this command that is not critical until we can adress the issue
properly.

Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agocmd: misc: Disable by default on sunXi
Maxime Ripard [Tue, 16 Jan 2018 08:44:18 +0000 (09:44 +0100)]
cmd: misc: Disable by default on sunXi

The sunXi arm64 build has overflown, leading to the main U-boot binary
overwriting the environment when flashing the new image, or even worse,
overwriting itself when we're calling saveenv.

Disable this command that is not critical until we can adress the issue
properly.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agocmd: loads: Disable by default on sunXi
Maxime Ripard [Tue, 16 Jan 2018 08:44:17 +0000 (09:44 +0100)]
cmd: loads: Disable by default on sunXi

The sunXi arm64 build has overflown, leading to the main U-boot binary
overwriting the environment when flashing the new image, or even worse,
overwriting itself when we're calling saveenv.

Disable this command that is not critical until we can adress the issue
properly.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agocmd: loadb: Disable by default on sunXi
Maxime Ripard [Tue, 16 Jan 2018 08:44:16 +0000 (09:44 +0100)]
cmd: loadb: Disable by default on sunXi

The sunXi arm64 build has overflown, leading to the main U-boot binary
overwriting the environment when flashing the new image, or even worse,
overwriting itself when we're calling saveenv.

Disable this command that is not critical until we can adress the issue
properly.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agocmd: unzip: Disable by default on sunXi
Maxime Ripard [Tue, 16 Jan 2018 08:44:15 +0000 (09:44 +0100)]
cmd: unzip: Disable by default on sunXi

The sunXi arm64 build has overflown, leading to the main U-boot binary
overwriting the environment when flashing the new image, or even worse,
overwriting itself when we're calling saveenv.

Disable this command that is not critical until we can adress the issue
properly.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agocmd: crc32: Disable by default on sunXi
Maxime Ripard [Tue, 16 Jan 2018 08:44:14 +0000 (09:44 +0100)]
cmd: crc32: Disable by default on sunXi

The sunXi arm64 build has overflown, leading to the main U-boot binary
overwriting the environment when flashing the new image, or even worse,
overwriting itself when we're calling saveenv.

Disable this command that is not critical until we can adress the issue
properly.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agodfu: select HASH
Maxime Ripard [Tue, 16 Jan 2018 08:44:13 +0000 (09:44 +0100)]
dfu: select HASH

The DFU code relies on the HASH config option. Make sure it is always there
by selecting it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agoMerge git://git.denx.de/u-boot-mips
Tom Rini [Fri, 26 Jan 2018 12:46:47 +0000 (07:46 -0500)]
Merge git://git.denx.de/u-boot-mips

6 years agoMerge git://git.denx.de/u-boot-spi
Tom Rini [Fri, 26 Jan 2018 12:46:34 +0000 (07:46 -0500)]
Merge git://git.denx.de/u-boot-spi

6 years agoMIPS: add BMIPS Comtrend AR-5315u board
Álvaro Fernández Rojas [Sat, 20 Jan 2018 18:16:05 +0000 (19:16 +0100)]
MIPS: add BMIPS Comtrend AR-5315u board

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
6 years agoMIPS: add support for Broadcom MIPS BCM6318 SoC family
Álvaro Fernández Rojas [Sat, 20 Jan 2018 18:16:04 +0000 (19:16 +0100)]
MIPS: add support for Broadcom MIPS BCM6318 SoC family

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
6 years agodm: ram: bmips: add BCM6318 support
Álvaro Fernández Rojas [Sat, 20 Jan 2018 18:16:03 +0000 (19:16 +0100)]
dm: ram: bmips: add BCM6318 support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
6 years agodm: cpu: bmips: add BCM6318 support
Álvaro Fernández Rojas [Sat, 20 Jan 2018 18:16:02 +0000 (19:16 +0100)]
dm: cpu: bmips: add BCM6318 support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
6 years agoMIPS: add BMIPS Comtrend WAP-5813n board
Álvaro Fernández Rojas [Sat, 20 Jan 2018 13:16:56 +0000 (14:16 +0100)]
MIPS: add BMIPS Comtrend WAP-5813n board

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
6 years agoMIPS: add support for Broadcom MIPS BCM6368 SoC family
Álvaro Fernández Rojas [Sat, 20 Jan 2018 13:16:55 +0000 (14:16 +0100)]
MIPS: add support for Broadcom MIPS BCM6368 SoC family

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
6 years agodm: cpu: bmips: add BCM6368 support
Álvaro Fernández Rojas [Sat, 20 Jan 2018 13:16:54 +0000 (14:16 +0100)]
dm: cpu: bmips: add BCM6368 support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
6 years agoDW SPI: Get clock value from Device Tree
Eugeniy Paltsev [Thu, 28 Dec 2017 12:09:03 +0000 (15:09 +0300)]
DW SPI: Get clock value from Device Tree

Add option to set spi controller clock frequency via device tree
using standard clock bindings.

Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.

Get rid of clock_manager.h include as we don't use
cm_get_spi_controller_clk_hz function anymore. (we use redefined
dw_spi_get_clk in SOCFPGA clock managers instead)

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agoSOCFPGA: clock manager: implement dw_spi_get_clk function
Eugeniy Paltsev [Thu, 28 Dec 2017 12:09:02 +0000 (15:09 +0300)]
SOCFPGA: clock manager: implement dw_spi_get_clk function

Implement dw_spi_get_clk function to override its weak
implementation in designware_spi.c driver.

We need this change to get rid of cm_get_spi_controller_clk_hz
function and clock_manager.h include in designware_spi.c driver.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agousb: ehci: mxs: fix swapped argument in ehci_writel()
Daniel Schwierzeck [Thu, 25 Jan 2018 19:43:58 +0000 (20:43 +0100)]
usb: ehci: mxs: fix swapped argument in ehci_writel()

ehci_writel() swaps the arguments for address and value. One call
in ehci-mxs ignores that.

This fixes the warning:

drivers/usb/host/ehci-mxs.c: In function ?ehci_hcd_stop?:
drivers/usb/host/ehci-mxs.c:159:19: error: initialization makes integer from pointer without a cast [-Werror=int-conversion]
  ehci_writel(tmp, &hcor->or_usbcmd);
                   ^
arch/arm/include/asm/io.h:117:34: note: in definition of macro ?writel?
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
                                  ^
drivers/usb/host/ehci-mxs.c:159:2: note: in expansion of macro ?ehci_writel?
  ^~~~~~~~~~~

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
6 years agousb: xhci: Fix bool initialization in xhci_bulk_tx
Gustavo A. R. Silva [Sat, 20 Jan 2018 08:37:31 +0000 (02:37 -0600)]
usb: xhci: Fix bool initialization in xhci_bulk_tx

Bool initializations should use true and false.

This issue was detected with the help of Coccinelle.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
6 years agomips: bmips: increment SYS_MALLOC_F_LEN
Álvaro Fernández Rojas [Sat, 20 Jan 2018 10:45:39 +0000 (11:45 +0100)]
mips: bmips: increment SYS_MALLOC_F_LEN

This prevents the following ENOMEM:
Error binding driver 'bmips_cpu': -12

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
6 years agoboston: Pad binary in .mcs to a multiple of 16 bytes
Paul Burton [Thu, 18 Jan 2018 22:36:41 +0000 (14:36 -0800)]
boston: Pad binary in .mcs to a multiple of 16 bytes

When flashing U-Boot on a Boston board using Xilinx Vivado tools, the
final 0x00 byte which ends the .relocs section seems to be skipped &
left in flash as 0xff unless the data contained in the .mcs is padded
out to a 16 byte boundary. Without our final zero byte relocation will
fail with an error about a spurious reloc:

Avoid this problem by padding out the data in the .mcs file to a 16 byte
boundary using srec_cat's -range-pad functionality.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
6 years agoddr: altera: silence PHY calibration unless in debug mode
Goldschmidt Simon [Thu, 25 Jan 2018 06:04:44 +0000 (06:04 +0000)]
ddr: altera: silence PHY calibration unless in debug mode

This driver has been using printf() including filename since it was
added. Convert to using debug() instead.

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
6 years agoarm: socfpga: allow configs without network support
Simon Goldschmidt [Thu, 25 Jan 2018 06:18:27 +0000 (07:18 +0100)]
arm: socfpga: allow configs without network support

Currently, socfpga_common.h does not allow configurations without
network support. This is because CONFIG_CMD_PXE is defined in this
file and distro mode has DHCP hard-coded as available.

Fix this by moving CONFIG_CMD_PXE and CONFIG_MENU to the defconfigs
and by making DHCP optional in BOOT_TARGET_DEVICES(func).

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
6 years agoMerge branch 'master' of git://git.denx.de/u-boot-coldfire
Tom Rini [Thu, 25 Jan 2018 03:08:00 +0000 (22:08 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-coldfire

6 years agopinctrl: rmobile: Import R8A7794 E2 PFC tables
Marek Vasut [Wed, 17 Jan 2018 21:33:59 +0000 (22:33 +0100)]
pinctrl: rmobile: Import R8A7794 E2 PFC tables

Import PFC tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agopinctrl: rmobile: Import R8A7792 V2H PFC tables
Marek Vasut [Wed, 17 Jan 2018 21:29:50 +0000 (22:29 +0100)]
pinctrl: rmobile: Import R8A7792 V2H PFC tables

Import PFC tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agopinctrl: rmobile: Import R8A7791/R8A7793 M2 PFC tables
Marek Vasut [Wed, 17 Jan 2018 16:14:45 +0000 (17:14 +0100)]
pinctrl: rmobile: Import R8A7791/R8A7793 M2 PFC tables

Import PFC tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux
kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agopinctrl: rmobile: Import R8A7790 H2 PFC tables
Marek Vasut [Wed, 17 Jan 2018 21:18:59 +0000 (22:18 +0100)]
pinctrl: rmobile: Import R8A7790 H2 PFC tables

Import PFC tables for R8A7790 H2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Import R8A7794 E2 clock tables
Marek Vasut [Wed, 17 Jan 2018 22:39:57 +0000 (23:39 +0100)]
clk: renesas: Import R8A7794 E2 clock tables

Import clock tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Import R8A7792 V2H clock tables
Marek Vasut [Wed, 17 Jan 2018 22:39:10 +0000 (23:39 +0100)]
clk: renesas: Import R8A7792 V2H clock tables

Import clock tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Import R8A7791/R8A7793 M2 clock tables
Marek Vasut [Mon, 8 Jan 2018 15:38:51 +0000 (16:38 +0100)]
clk: renesas: Import R8A7791/R8A7793 M2 clock tables

Import clock tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux
kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Import R8A7790 H2 clock tables
Marek Vasut [Wed, 17 Jan 2018 22:14:25 +0000 (23:14 +0100)]
clk: renesas: Import R8A7790 H2 clock tables

Import clock tables for R8A7790 H2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Add Gen2 clock core
Marek Vasut [Mon, 8 Jan 2018 15:38:51 +0000 (16:38 +0100)]
clk: renesas: Add Gen2 clock core

Add common clock code for Renesas RCar Gen2 platforms.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Add DIV6P1 clock type
Marek Vasut [Wed, 17 Jan 2018 23:05:28 +0000 (00:05 +0100)]
clk: renesas: Add DIV6P1 clock type

Add macros for the DIV6P1 clock type, which is used on Gen2
and optionally also on Gen3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Split out code shared between Gen2 and Gen3
Marek Vasut [Mon, 15 Jan 2018 15:44:39 +0000 (16:44 +0100)]
clk: renesas: Split out code shared between Gen2 and Gen3

Pull code which is common for RCar Gen2 and RCar Gen3 into
separate source file. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Make clock tables Kconfig configurable
Marek Vasut [Mon, 8 Jan 2018 15:32:38 +0000 (16:32 +0100)]
clk: renesas: Make clock tables Kconfig configurable

Add Kconfig entries for each SoC clock table, so they can be
compiled in or out at build time. This can reduce the size of
the binary if desired.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Split SMSTPCR and RMSTPCR tables
Marek Vasut [Sun, 14 Jan 2018 23:58:35 +0000 (00:58 +0100)]
clk: renesas: Split SMSTPCR and RMSTPCR tables

The Gen2 requires setting RMSTPCR before booting, while on Gen3 this
is thus far always zero. Split the tables so the RMSTPCR can be set
too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Pull Gen3 specific bits into separate header
Marek Vasut [Mon, 8 Jan 2018 16:09:45 +0000 (17:09 +0100)]
clk: renesas: Pull Gen3 specific bits into separate header

Extract the macros specific to Gen3 clock into a separate header.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Make PLL configurations per-SoC
Marek Vasut [Tue, 16 Jan 2018 18:23:17 +0000 (19:23 +0100)]
clk: renesas: Make PLL configurations per-SoC

Not all SoCs have the same PLL configuration options,
so make those PLL configuraion tables per-SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Make clk_ids per-driver
Marek Vasut [Mon, 8 Jan 2018 15:05:28 +0000 (16:05 +0100)]
clk: renesas: Make clk_ids per-driver

Not all drivers use the same IDs, so make those IDs per-driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: renesas: Split RCar Gen3 driver
Marek Vasut [Mon, 8 Jan 2018 13:01:40 +0000 (14:01 +0100)]
clk: renesas: Split RCar Gen3 driver

Split the massive driver into smaller per-SoC drivers and pull the
common code into a separate file. This would allow configuring out
unnecessary clock drivers once the Kconfig changes are in and also
allow adding more clock tables easily.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoserial: sh: Add support for R7S72100 (RZ/A1)
Chris Brandt [Wed, 17 Jan 2018 01:52:18 +0000 (20:52 -0500)]
serial: sh: Add support for R7S72100 (RZ/A1)

Add support for RZ/A1 series SoCs.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
6 years agoserial: sh: Unify CONFIG_R8A779[01234] as CONFIG_RCAR_GEN2
Marek Vasut [Mon, 22 Jan 2018 00:43:25 +0000 (01:43 +0100)]
serial: sh: Unify CONFIG_R8A779[01234] as CONFIG_RCAR_GEN2

Use the common RCAR_GEN2 config option instead of enumerating
each SoC and having a lengthy ifdef clause. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoserial: sh: Replace fdtdec_get_addr() with devfdt_get_addr()
Marek Vasut [Wed, 17 Jan 2018 21:36:37 +0000 (22:36 +0100)]
serial: sh: Replace fdtdec_get_addr() with devfdt_get_addr()

Replace fdtdec_get_addr() with devfdt_get_addr() as the later one is
the current recommended practice.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Convert CONFIG_R8A77xx to Kconfig
Marek Vasut [Sun, 7 Jan 2018 18:37:06 +0000 (19:37 +0100)]
ARM: rmobile: Convert CONFIG_R8A77xx to Kconfig

Convert these configuration options to Kconfig, update board defconfigs
and drop them from whitelist.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: dts: rmobile: Factor out U-Boot extras
Marek Vasut [Wed, 10 Jan 2018 10:47:03 +0000 (11:47 +0100)]
ARM: dts: rmobile: Factor out U-Boot extras

Pull out u-boot extras into dtsi files to make synchronization of DTS
from Linux kernel as easy as a simple copy. All the U-Boot extras are
now in *-u-boot.dts* files instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: dts: rmobile: Update DTS to match Linux 4.14
Marek Vasut [Wed, 29 Nov 2017 03:27:36 +0000 (04:27 +0100)]
ARM: dts: rmobile: Update DTS to match Linux 4.14

Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.14,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . This includes both M3
and H3 ULCB and Salvator-X boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoMerge git://git.denx.de/u-boot-mmc
Tom Rini [Wed, 24 Jan 2018 16:28:44 +0000 (11:28 -0500)]
Merge git://git.denx.de/u-boot-mmc

6 years agodoc: Update the zynq u-boot status
Ezequiel Garcia [Sat, 13 Jan 2018 20:48:27 +0000 (17:48 -0300)]
doc: Update the zynq u-boot status

NAND and QSPI devices are now supported, so mark
them as such.

Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agoarm: zynq: Enable SPL_CLK only if SPL is enabled
Ezequiel Garcia [Fri, 12 Jan 2018 15:33:24 +0000 (12:33 -0300)]
arm: zynq: Enable SPL_CLK only if SPL is enabled

Setup proper dependency in Kconfig for SPL_CLK.
If SPL is not enabled, SPL_CLK shouldn't be selected.

Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agommc: Poll for broken card detection case
Jun Nie [Tue, 2 Jan 2018 04:25:57 +0000 (12:25 +0800)]
mmc: Poll for broken card detection case

Poll for broken card detection case instead of return
no card detected.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
6 years agommc: fix to assign to correct clock value when clock is enabling
Jaehoon Chung [Tue, 23 Jan 2018 05:04:30 +0000 (14:04 +0900)]
mmc: fix to assign to correct clock value when clock is enabling

When clock is enabling, it's assigned to 0 as mmc->clock.
Then it can't initialize any card.
Fix to assign to correct clock value as mmc->cfg->f_min or f_max.

Fixes: 9546eb92cb6 ("mmc: fix the wrong disabling clock")
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Guillaume GARDET <guillaume.gardet@free.fr>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
6 years agoconfigs: odroid-xu3: enable the configs relevant to regulator
Jaehoon Chung [Tue, 16 Jan 2018 06:33:52 +0000 (15:33 +0900)]
configs: odroid-xu3: enable the configs relevant to regulator

Enable the CONFIG_CMD_REGULATOR and CONFIG_DM_REGULATOR_S2MPS11.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
6 years agopower: pmic: s2mps11: probe the regulator driver
Jaehoon Chung [Tue, 16 Jan 2018 06:33:51 +0000 (15:33 +0900)]
power: pmic: s2mps11: probe the regulator driver

Add the probe function to support the s2mps11 regulator driver.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
6 years agopower: regulator: s2mps11: add a regulator driver for s2mps11
Jaehoon Chung [Tue, 16 Jan 2018 06:33:50 +0000 (15:33 +0900)]
power: regulator: s2mps11: add a regulator driver for s2mps11

exynos5422 has the s2mps11 PMIC.
s2mps11 pmic has the 10-BUCK and 38-LDO regulators.
Each IP and devices in exynos5422 can be controlled by each regulators.
This patch is support for s2mps11 regulator driver.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
6 years agospi: cadence_qspi_apb: Make flash writes 32 bit aligned
Vignesh R [Wed, 24 Jan 2018 05:14:07 +0000 (10:44 +0530)]
spi: cadence_qspi_apb: Make flash writes 32 bit aligned

Make flash writes 32 bit aligned by using bounce buffers to deal with
non 32 bit aligned buffers.
This is required because as per TI K2G TRM[1], the external master is
only permitted to issue 32-bit data interface writes until the last word
of an indirect transfer. Otherwise indirect writes is known to fail
sometimes.

[1] http://www.ti.com/lit/ug/spruhy8g/spruhy8g.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agoRevert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"
Vignesh R [Wed, 24 Jan 2018 05:14:06 +0000 (10:44 +0530)]
Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"

This reverts commit 57897c13de03ac0136d64641a3eab526c6810387.

Using bounce_buf.c to handle non-DMA alignment problems is bad as
bounce_buf.c does cache manipulations which is not required. Therefore
revert this patch in favour of local bounce buffer solution in the next
patch.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agoRevert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"
Goldschmidt Simon [Wed, 24 Jan 2018 05:14:05 +0000 (10:44 +0530)]
Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"

This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f.

This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates
the data cache after reading. This is meant for dma transfers only and
breaks the cadence_qspi driver which copies via cpu only: data that is
copied by the cpu is in cache only and the cache invalidation at the end
throws away this data.

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agodts: cadence_spi: Update documentation for DT bindings
Jason Rush [Tue, 23 Jan 2018 23:13:12 +0000 (17:13 -0600)]
dts: cadence_spi: Update documentation for DT bindings

Update documentation to reflect adopting the Linux DT bindings.

Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>
Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>
6 years agoconfig: cadence_spi: Remove defines read from DT
Jason Rush [Tue, 23 Jan 2018 23:13:11 +0000 (17:13 -0600)]
config: cadence_spi: Remove defines read from DT

Cleanup unused #define values that are read from the DT.

Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>
Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>
6 years agodts: cadence_spi: Sync DT bindings with Linux
Jason Rush [Tue, 23 Jan 2018 23:13:10 +0000 (17:13 -0600)]
dts: cadence_spi: Sync DT bindings with Linux

Adopt the Linux DT bindings and clean-up duplicate
and unused values.

Fix indentation of the QSPI node in the keystone k2g
device tree.

Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>
Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>
6 years agospi: cadence_spi: Sync DT bindings with Linux
Jason Rush [Tue, 23 Jan 2018 23:13:09 +0000 (17:13 -0600)]
spi: cadence_spi: Sync DT bindings with Linux

Adopt the Linux DT bindings. This also fixes an issue
with the indaddrtrig register on the Cadence QSPI
device being programmed with the wrong value for the
socfpga arch.

Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>
Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>
6 years agospi: kirkwood_spi: implement workaround for FE-9144572
Chris Packham [Mon, 22 Jan 2018 09:44:20 +0000 (22:44 +1300)]
spi: kirkwood_spi: implement workaround for FE-9144572

Erratum NO. FE-9144572: The device SPI interface supports frequencies of
up to 50 MHz.  However, due to this erratum, when the device core clock
is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and
CPOL=CPHA=1 there might occur data corruption on reads from the SPI
device.

Implement the workaround by setting the TMISO_SAMPLE value to 0x2
in the timing1 register.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agosf_probe: Merge spi_flash_probe_tail into spi_flash_probe
Mario Six [Mon, 15 Jan 2018 10:08:42 +0000 (11:08 +0100)]
sf_probe: Merge spi_flash_probe_tail into spi_flash_probe

spi_flash_probe_tail is now only called from spi_flash_probe, hence we
can merge its body into spi_flash_probe.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years agospi: spi-uclass: Fix style violations
Mario Six [Mon, 15 Jan 2018 10:08:41 +0000 (11:08 +0100)]
spi: spi-uclass: Fix style violations

Remove a superfluous newline, and reduce the scope of a variable.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years agospi: sf_probe: Fix style violations
Mario Six [Mon, 15 Jan 2018 10:08:40 +0000 (11:08 +0100)]
spi: sf_probe: Fix style violations

Fix two indention-related style violations.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agospi: Remove CONFIG_OF_SPI_FLASH
Mario Six [Mon, 15 Jan 2018 10:08:39 +0000 (11:08 +0100)]
spi: Remove CONFIG_OF_SPI_FLASH

Previous patches removed the last usages of this config variable, so
that it is now obsolete.

This patch removes it from the whitelist.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years agospi: Remove spi_setup_slave_fdt
Mario Six [Mon, 15 Jan 2018 10:08:38 +0000 (11:08 +0100)]
spi: Remove spi_setup_slave_fdt

A previous patch removed the spi_flash_probe_fdt function, which
contained the last call of the spi_setup_slave_fdt function, which is
now equally obsolete.

This patch removes the function.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years agospi: Remove spi_flash_probe_fdt
Mario Six [Mon, 15 Jan 2018 10:08:37 +0000 (11:08 +0100)]
spi: Remove spi_flash_probe_fdt

Commit ba45756 ("dm: x86: spi: Convert ICH SPI driver to driver model")
removed the last usage of the spi_flash_probe_fdt function, rendering it
obsolete.

This patch removes the function.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years agospi: Remove obsolete spi_base_setup_slave_fdt
Mario Six [Mon, 15 Jan 2018 10:08:36 +0000 (11:08 +0100)]
spi: Remove obsolete spi_base_setup_slave_fdt

0efc024 ("spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT
node") added a helper function spi_base_setup_slave_fdt to to set up a
SPI slave from a given FDT blob. The only user was the exynos SPI
driver.

But commit 73186c9 ("dm: exynos: Convert SPI to driver model") removed
the use of this function, hence rendering it obsolete.

Remove this function, as well as the CONFIG_OF_SPI option, which guarded
only this function.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
6 years agospi: Fix style violation and improve code
Mario Six [Mon, 15 Jan 2018 10:08:35 +0000 (11:08 +0100)]
spi: Fix style violation and improve code

This patch fixes a printf specifier style violation, reduces the scope
of a variable, and turns a void pointer that is used with pointer
arithmetic into a u8 pointer.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agomips: bmips: enable the SPI flash on the Comtrend AR-5387un
Álvaro Fernández Rojas [Sat, 20 Jan 2018 01:13:41 +0000 (02:13 +0100)]
mips: bmips: enable the SPI flash on the Comtrend AR-5387un

It's a Macronix (mx25l12805d) 16 MB SPI flash.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agomips: bmips: add bcm63xx-hsspi driver support for BCM63268
Álvaro Fernández Rojas [Sat, 20 Jan 2018 01:13:40 +0000 (02:13 +0100)]
mips: bmips: add bcm63xx-hsspi driver support for BCM63268

This driver manages the high speed SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agomips: bmips: add bcm63xx-hsspi driver support for BCM6328
Álvaro Fernández Rojas [Sat, 20 Jan 2018 01:13:39 +0000 (02:13 +0100)]
mips: bmips: add bcm63xx-hsspi driver support for BCM6328

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agodm: spi: add BCM63xx HSSPI driver
Álvaro Fernández Rojas [Sat, 20 Jan 2018 01:13:38 +0000 (02:13 +0100)]
dm: spi: add BCM63xx HSSPI driver

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agomips: bmips: enable the SPI flash on the Netgear CG3100D
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:15:05 +0000 (17:15 +0100)]
mips: bmips: enable the SPI flash on the Netgear CG3100D

It's a Spansion (s25fl064a) 8 MB SPI flash.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agomips: bmips: enable the SPI flash on the Sagem F@ST1704
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:15:04 +0000 (17:15 +0100)]
mips: bmips: enable the SPI flash on the Sagem F@ST1704

It's a Winbond (w25x32) 4 MB SPI flash.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agomips: bmips: add bcm63xx-spi driver support for BCM63268
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:15:03 +0000 (17:15 +0100)]
mips: bmips: add bcm63xx-spi driver support for BCM63268

This driver manages the low speed SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agomips: bmips: add bcm63xx-spi driver support for BCM3380
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:15:02 +0000 (17:15 +0100)]
mips: bmips: add bcm63xx-spi driver support for BCM3380

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agomips: bmips: add bcm63xx-spi driver support for BCM6358
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:15:01 +0000 (17:15 +0100)]
mips: bmips: add bcm63xx-spi driver support for BCM6358

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agomips: bmips: add bcm63xx-spi driver support for BCM6348
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:15:00 +0000 (17:15 +0100)]
mips: bmips: add bcm63xx-spi driver support for BCM6348

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agomips: bmips: add bcm63xx-spi driver support for BCM6338
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:14:59 +0000 (17:14 +0100)]
mips: bmips: add bcm63xx-spi driver support for BCM6338

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agodm: spi: add BCM63xx SPI driver
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:14:58 +0000 (17:14 +0100)]
dm: spi: add BCM63xx SPI driver

This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agodrivers: spi: consider command bytes when sending transfers
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:14:57 +0000 (17:14 +0100)]
drivers: spi: consider command bytes when sending transfers

Command bytes are part of the written bytes and they should be taken into
account when sending a spi transfer.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agodrivers: spi: allow limiting reads
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:14:56 +0000 (17:14 +0100)]
drivers: spi: allow limiting reads

For some SPI controllers it's not possible to keep the CS active between
transfers and they are limited to a known number of bytes.
This splits spi_flash reads into different iterations in order to respect
the SPI controller limits.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agowait_bit: use wait_for_bit_le32 and remove wait_for_bit
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:14:55 +0000 (17:14 +0100)]
wait_bit: use wait_for_bit_le32 and remove wait_for_bit

wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agowait_bit: add 8/16/32 BE/LE versions of wait_for_bit
Álvaro Fernández Rojas [Tue, 23 Jan 2018 16:14:54 +0000 (17:14 +0100)]
wait_bit: add 8/16/32 BE/LE versions of wait_for_bit

Add 8/16/32 bits and BE/LE versions of wait_for_bit.
This is needed for reading registers that are not aligned to 32 bits, and for
Big Endian platforms.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
6 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Wed, 24 Jan 2018 02:48:53 +0000 (21:48 -0500)]
Merge git://git.denx.de/u-boot-fsl-qoriq

6 years agocommon/board_f.c: align m68k arch to use CONFIG_DISPLAY_CPUINFO
Angelo Dureghello [Sat, 19 Aug 2017 22:01:55 +0000 (00:01 +0200)]
common/board_f.c: align m68k arch to use CONFIG_DISPLAY_CPUINFO

Change all coldfire arch files to use CONFIG_DISPLAY_CPUINFO.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes for v2:
   - update common/Kconfig to add M68K to the default y list

6 years agoarmv8: ls1088a: Add IFC and eMMC as qixis boot sources
Ashish Kumar [Wed, 17 Jan 2018 06:46:37 +0000 (12:16 +0530)]
armv8: ls1088a: Add IFC and eMMC as qixis boot sources

Add macro QIXIS_LBMAP_EMMC, QIXIS_LBMAP_IFC, QIXIS_RCW_SRC_IFC,
QIXIS_RCW_SRC_EMMC to enable IFC and eMMC as boot sources for
qixis commands.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
[YS: Modify subject and add commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
6 years agofsl: common: qixis: Add ifc and emmc switching via qixis
Ashish Kumar [Wed, 17 Jan 2018 06:46:36 +0000 (12:16 +0530)]
fsl: common: qixis: Add ifc and emmc switching via qixis

Currently only SD, NAND can be secondary boot sources controlled
by FPGA/CPLD via qixis commands. For SoC like LS1088 IFC-NOR
can be secondary boot source, while QSPI-NOR is the primary.
Add options in qixis to switch to other boot sources including
ifc and emmc.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
6 years agocrypto/fsl: Fix HW accelerated hash commands
Breno Lima [Wed, 17 Jan 2018 12:03:45 +0000 (10:03 -0200)]
crypto/fsl: Fix HW accelerated hash commands

The hash command function were not flushing the dcache before passing data
to CAAM/DMA and not invalidating the dcache when getting data back.

Due the data cache incoherency, HW accelerated hash commands used to fail
with CAAM errors like "Invalid KEY Command".

Check if pbuf and pout buffers are properly aligned to the cache line size
and flush/invalidate the memory regions to address this issue.

This solution is based in a previous work from Clemens Gruber in
commit 598e9dccc75d ("crypto/fsl: fix BLOB encapsulation and
decapsulation")

Reported-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
6 years agoARM: dts: Freescale: re-license device tree files under GPLv2+/X11
Pankaj Bansal [Thu, 18 Jan 2018 04:13:33 +0000 (09:43 +0530)]
ARM: dts: Freescale: re-license device tree files under GPLv2+/X11

The current GPL only licensing on the device trees makes it very
impractical for other software components licensed under another
license.

To make it easier to reuse them, re-license the the device trees for
Freescale (now NXP) SoCs and boards under GPLv2+/X11 dual license.

Same trend is followed in linux.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
6 years agoarmv8: ls1088a: vid: Compiling VID specific functions for SPL
Rajesh Bhagat [Wed, 17 Jan 2018 10:43:10 +0000 (16:13 +0530)]
armv8: ls1088a: vid: Compiling VID specific functions for SPL

Enables and compiles VID specific functions for SPL.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
6 years agols1088a: Add VID support for QDS and RDB platforms
Rajesh Bhagat [Wed, 17 Jan 2018 10:43:09 +0000 (16:13 +0530)]
ls1088a: Add VID support for QDS and RDB platforms

This patch adds the support for VID on LS1088AQDS and LS1088ARDB systems.
It reads the fusesr register and changes the VDD accordingly by adjusting
the voltage via LTC3882 regulator.

This patch also takes care of the special case of 0.9V VDD is present in
fusesr register. In that case,it also changes the SERDES voltage by
disabling the SERDES, changing the SVDD and then re-enabling SERDES.

Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
6 years agocommon: board_f: vid: Add VID specific API to adjust core voltage
Rajesh Bhagat [Wed, 17 Jan 2018 10:43:08 +0000 (16:13 +0530)]
common: board_f: vid: Add VID specific API to adjust core voltage

Adds a VID specific API in init_sequence_f and spl code flow
namely init_func_vid which is required to adjust core voltage.

VID specific code is required in spl, hence moving flag CONFIG_VID
out of spl flags.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>