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(parent: 66197ff) | patch
Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignmen...
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Mon, 14 Oct 2019 00:16:25 +0000 (00:16 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Mon, 14 Oct 2019 00:16:25 +0000 (00:16 +0000)
commite9495e90a65fa51783c8577067beff7fe8992e5a
tree3dcc6c473743b77c50f23278f77c5c93786a9370tree | snapshot
parent66197ff15a8800313d6df2e04ca822d15ae758f2commit | diff
Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignment of constant loads from assembly code.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2739 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/full_demo/RegTest.S diff | blob | history
FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S diff | blob | history
FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/main.c diff | blob | history
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