+++ /dev/null
-/**************************************************************************//**\r
- * @file cmsis_armcc.h\r
- * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#ifndef __CMSIS_ARMCC_H\r
-#define __CMSIS_ARMCC_H\r
-\r
-\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
- */\r
-\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-/**\r
- \brief Get Control Register\r
- \details Returns the content of the Control Register.\r
- \return Control Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Control Register\r
- \details Writes the given value to the Control Register.\r
- \param [in] control Control Register value to set\r
- */\r
-__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-\r
-/**\r
- \brief Get IPSR Register\r
- \details Returns the content of the IPSR Register.\r
- \return IPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- register uint32_t __regIPSR __ASM("ipsr");\r
- return(__regIPSR);\r
-}\r
-\r
-\r
-/**\r
- \brief Get APSR Register\r
- \details Returns the content of the APSR Register.\r
- \return APSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- register uint32_t __regAPSR __ASM("apsr");\r
- return(__regAPSR);\r
-}\r
-\r
-\r
-/**\r
- \brief Get xPSR Register\r
- \details Returns the content of the xPSR Register.\r
- \return xPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- register uint32_t __regXPSR __ASM("xpsr");\r
- return(__regXPSR);\r
-}\r
-\r
-\r
-/**\r
- \brief Get Process Stack Pointer\r
- \details Returns the current value of the Process Stack Pointer (PSP).\r
- \return PSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- return(__regProcessStackPointer);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Process Stack Pointer\r
- \details Assigns the given value to the Process Stack Pointer (PSP).\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- __regProcessStackPointer = topOfProcStack;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Main Stack Pointer\r
- \details Returns the current value of the Main Stack Pointer (MSP).\r
- \return MSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- return(__regMainStackPointer);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Main Stack Pointer\r
- \details Assigns the given value to the Main Stack Pointer (MSP).\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- __regMainStackPointer = topOfMainStack;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Mask\r
- \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
- \return Priority Mask value\r
- */\r
-__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Priority Mask\r
- \details Assigns the given value to the Priority Mask Register.\r
- \param [in] priMask Priority Mask\r
- */\r
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
-\r
-/**\r
- \brief Enable FIQ\r
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __enable_fault_irq __enable_fiq\r
-\r
-\r
-/**\r
- \brief Disable FIQ\r
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-\r
-/**\r
- \brief Get Base Priority\r
- \details Returns the current value of the Base Priority register.\r
- \return Base Priority register value\r
- */\r
-__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Base Priority\r
- \details Assigns the given value to the Base Priority register.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xFFU);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Base Priority with condition\r
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
- or the new value increases the BASEPRI priority level.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePriMax __ASM("basepri_max");\r
- __regBasePriMax = (basePri & 0xFFU);\r
-}\r
-\r
-\r
-/**\r
- \brief Get Fault Mask\r
- \details Returns the current value of the Fault Mask register.\r
- \return Fault Mask register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Fault Mask\r
- \details Assigns the given value to the Fault Mask register.\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & (uint32_t)1);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r
-\r
-/**\r
- \brief Get FPSCR\r
- \details Returns the current value of the Floating Point Status/Control register.\r
- \return Floating Point Status/Control register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- return(__regfpscr);\r
-#else\r
- return(0U);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
- \brief Set FPSCR\r
- \details Assigns the given value to the Floating Point Status/Control register.\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- __regfpscr = (fpscr);\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r
-\r
-\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-/**\r
- \brief No Operation\r
- \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP __nop\r
-\r
-\r
-/**\r
- \brief Wait For Interrupt\r
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
- */\r
-#define __WFI __wfi\r
-\r
-\r
-/**\r
- \brief Wait For Event\r
- \details Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE __wfe\r
-\r
-\r
-/**\r
- \brief Send Event\r
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV __sev\r
-\r
-\r
-/**\r
- \brief Instruction Synchronization Barrier\r
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or memory,\r
- after the instruction has been completed.\r
- */\r
-#define __ISB() do {\\r
- __schedule_barrier();\\r
- __isb(0xF);\\r
- __schedule_barrier();\\r
- } while (0U)\r
-\r
-/**\r
- \brief Data Synchronization Barrier\r
- \details Acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-#define __DSB() do {\\r
- __schedule_barrier();\\r
- __dsb(0xF);\\r
- __schedule_barrier();\\r
- } while (0U)\r
-\r
-/**\r
- \brief Data Memory Barrier\r
- \details Ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-#define __DMB() do {\\r
- __schedule_barrier();\\r
- __dmb(0xF);\\r
- __schedule_barrier();\\r
- } while (0U)\r
-\r
-/**\r
- \brief Reverse byte order (32 bit)\r
- \details Reverses the byte order in integer value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __REV __rev\r
-\r
-\r
-/**\r
- \brief Reverse byte order (16 bit)\r
- \details Reverses the byte order in two unsigned short values.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-/**\r
- \brief Reverse byte order in signed short value\r
- \details Reverses the byte order in a signed short value with sign extension to integer.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Rotate Right in unsigned value (32 bit)\r
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-#define __ROR __ror\r
-\r
-\r
-/**\r
- \brief Breakpoint\r
- \details Causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __breakpoint(value)\r
-\r
-\r
-/**\r
- \brief Reverse bit order of value\r
- \details Reverses the bit order of the given value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
- #define __RBIT __rbit\r
-#else\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
-\r
- result = value; /* r will be reversed bits of v; first get LSB of v */\r
- for (value >>= 1U; value; value >>= 1U)\r
- {\r
- result <<= 1U;\r
- result |= value & 1U;\r
- s--;\r
- }\r
- result <<= s; /* shift when v's highest bits are zero */\r
- return(result);\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief Count leading zeros\r
- \details Counts the number of leading zeros of a data value.\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __clz\r
-\r
-\r
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
-\r
-/**\r
- \brief LDR Exclusive (8 bit)\r
- \details Executes a exclusive LDR instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
-#else\r
- #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (16 bit)\r
- \details Executes a exclusive LDR instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
-#else\r
- #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (32 bit)\r
- \details Executes a exclusive LDR instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
-#else\r
- #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief STR Exclusive (8 bit)\r
- \details Executes a exclusive STR instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __STREXB(value, ptr) __strex(value, ptr)\r
-#else\r
- #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief STR Exclusive (16 bit)\r
- \details Executes a exclusive STR instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __STREXH(value, ptr) __strex(value, ptr)\r
-#else\r
- #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief STR Exclusive (32 bit)\r
- \details Executes a exclusive STR instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
- #define __STREXW(value, ptr) __strex(value, ptr)\r
-#else\r
- #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
-#endif\r
-\r
-\r
-/**\r
- \brief Remove the exclusive lock\r
- \details Removes the exclusive lock which is created by LDREX.\r
- */\r
-#define __CLREX __clrex\r
-\r
-\r
-/**\r
- \brief Signed Saturate\r
- \details Saturates a signed value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT __ssat\r
-\r
-\r
-/**\r
- \brief Unsigned Saturate\r
- \details Saturates an unsigned value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT __usat\r
-\r
-\r
-/**\r
- \brief Rotate Right with Extend (32 bit)\r
- \details Moves each bit of a bitstring right by one bit.\r
- The carry input is shifted in at the left end of the bitstring.\r
- \param [in] value Value to rotate\r
- \return Rotated value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
-{\r
- rrx r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged STRT instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-#define __STRBT(value, ptr) __strt(value, ptr)\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged STRT instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-#define __STRHT(value, ptr) __strt(value, ptr)\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged STRT instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-#define __STRT(value, ptr) __strt(value, ptr)\r
-\r
-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
- Access to dedicated SIMD instructions\r
- @{\r
-*/\r
-\r
-#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */\r
-\r
-#define __SADD8 __sadd8\r
-#define __QADD8 __qadd8\r
-#define __SHADD8 __shadd8\r
-#define __UADD8 __uadd8\r
-#define __UQADD8 __uqadd8\r
-#define __UHADD8 __uhadd8\r
-#define __SSUB8 __ssub8\r
-#define __QSUB8 __qsub8\r
-#define __SHSUB8 __shsub8\r
-#define __USUB8 __usub8\r
-#define __UQSUB8 __uqsub8\r
-#define __UHSUB8 __uhsub8\r
-#define __SADD16 __sadd16\r
-#define __QADD16 __qadd16\r
-#define __SHADD16 __shadd16\r
-#define __UADD16 __uadd16\r
-#define __UQADD16 __uqadd16\r
-#define __UHADD16 __uhadd16\r
-#define __SSUB16 __ssub16\r
-#define __QSUB16 __qsub16\r
-#define __SHSUB16 __shsub16\r
-#define __USUB16 __usub16\r
-#define __UQSUB16 __uqsub16\r
-#define __UHSUB16 __uhsub16\r
-#define __SASX __sasx\r
-#define __QASX __qasx\r
-#define __SHASX __shasx\r
-#define __UASX __uasx\r
-#define __UQASX __uqasx\r
-#define __UHASX __uhasx\r
-#define __SSAX __ssax\r
-#define __QSAX __qsax\r
-#define __SHSAX __shsax\r
-#define __USAX __usax\r
-#define __UQSAX __uqsax\r
-#define __UHSAX __uhsax\r
-#define __USAD8 __usad8\r
-#define __USADA8 __usada8\r
-#define __SSAT16 __ssat16\r
-#define __USAT16 __usat16\r
-#define __UXTB16 __uxtb16\r
-#define __UXTAB16 __uxtab16\r
-#define __SXTB16 __sxtb16\r
-#define __SXTAB16 __sxtab16\r
-#define __SMUAD __smuad\r
-#define __SMUADX __smuadx\r
-#define __SMLAD __smlad\r
-#define __SMLADX __smladx\r
-#define __SMLALD __smlald\r
-#define __SMLALDX __smlaldx\r
-#define __SMUSD __smusd\r
-#define __SMUSDX __smusdx\r
-#define __SMLSD __smlsd\r
-#define __SMLSDX __smlsdx\r
-#define __SMLSLD __smlsld\r
-#define __SMLSLDX __smlsldx\r
-#define __SEL __sel\r
-#define __QADD __qadd\r
-#define __QSUB __qsub\r
-\r
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
-\r
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
-\r
-#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
- ((int64_t)(ARG3) << 32U) ) >> 32U))\r
-\r
-#endif /* (__CORTEX_M >= 0x04) */\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#endif /* __CMSIS_ARMCC_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file cmsis_gcc.h\r
- * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
- * @version V5.00\r
- * @date 02. March 2016\r
- ******************************************************************************/\r
-/*\r
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
- *\r
- * SPDX-License-Identifier: Apache-2.0\r
- *\r
- * Licensed under the Apache License, Version 2.0 (the License); you may\r
- * not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at\r
- *\r
- * http://www.apache.org/licenses/LICENSE-2.0\r
- *\r
- * Unless required by applicable law or agreed to in writing, software\r
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- */\r
-\r
-#ifndef __CMSIS_GCC_H\r
-#define __CMSIS_GCC_H\r
-\r
-/* ignore some GCC warnings */\r
-#if defined ( __GNUC__ )\r
-#pragma GCC diagnostic push\r
-#pragma GCC diagnostic ignored "-Wsign-conversion"\r
-#pragma GCC diagnostic ignored "-Wconversion"\r
-#pragma GCC diagnostic ignored "-Wunused-parameter"\r
-#endif\r
-\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
- */\r
-\r
-/**\r
- \brief Enable IRQ Interrupts\r
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)\r
-{\r
- __ASM volatile ("cpsie i" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Disable IRQ Interrupts\r
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)\r
-{\r
- __ASM volatile ("cpsid i" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Control Register\r
- \details Returns the content of the Control Register.\r
- \return Control Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Control Register\r
- \details Writes the given value to the Control Register.\r
- \param [in] control Control Register value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get IPSR Register\r
- \details Returns the content of the IPSR Register.\r
- \return IPSR Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Get APSR Register\r
- \details Returns the content of the APSR Register.\r
- \return APSR Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Get xPSR Register\r
- \details Returns the content of the xPSR Register.\r
- \return xPSR Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Get Process Stack Pointer\r
- \details Returns the current value of the Process Stack Pointer (PSP).\r
- \return PSP Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Process Stack Pointer\r
- \details Assigns the given value to the Process Stack Pointer (PSP).\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Main Stack Pointer\r
- \details Returns the current value of the Main Stack Pointer (MSP).\r
- \return MSP Register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Main Stack Pointer\r
- \details Assigns the given value to the Main Stack Pointer (MSP).\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Mask\r
- \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
- \return Priority Mask value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Priority Mask\r
- \details Assigns the given value to the Priority Mask Register.\r
- \param [in] priMask Priority Mask\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
-}\r
-\r
-\r
-#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
- (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) )\r
-\r
-/**\r
- \brief Enable FIQ\r
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsie f" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Disable FIQ\r
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsid f" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Base Priority\r
- \details Returns the current value of the Base Priority register.\r
- \return Base Priority register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Base Priority\r
- \details Assigns the given value to the Base Priority register.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Set Base Priority with condition\r
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
- or the new value increases the BASEPRI priority level.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Fault Mask\r
- \details Returns the current value of the Fault Mask register.\r
- \return Fault Mask register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Fault Mask\r
- \details Assigns the given value to the Fault Mask register.\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
-}\r
-\r
-#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
- (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */\r
-\r
-\r
-#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U))\r
-\r
-/**\r
- \brief Get FPSCR\r
- \details Returns the current value of the Floating Point Status/Control register.\r
- \return Floating Point Status/Control register value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
- uint32_t result;\r
-\r
- __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
- __ASM volatile ("");\r
- return(result);\r
-#else\r
- return(0U);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
- \brief Set FPSCR\r
- \details Assigns the given value to the Floating Point Status/Control register.\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
- __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
- __ASM volatile ("");\r
-#endif\r
-}\r
-\r
-#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */\r
-\r
-\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-/* Define macros for porting to both thumb1 and thumb2.\r
- * For thumb1, use low register (r0-r7), specified by constraint "l"\r
- * Otherwise, use general registers, specified by constraint "r" */\r
-#if defined (__thumb__) && !defined (__thumb2__)\r
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
-#else\r
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
-#endif\r
-\r
-/**\r
- \brief No Operation\r
- \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r
-{\r
- __ASM volatile ("nop");\r
-}\r
-\r
-\r
-/**\r
- \brief Wait For Interrupt\r
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r
-{\r
- __ASM volatile ("wfi");\r
-}\r
-\r
-\r
-/**\r
- \brief Wait For Event\r
- \details Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r
-{\r
- __ASM volatile ("wfe");\r
-}\r
-\r
-\r
-/**\r
- \brief Send Event\r
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r
-{\r
- __ASM volatile ("sev");\r
-}\r
-\r
-\r
-/**\r
- \brief Instruction Synchronization Barrier\r
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or memory,\r
- after the instruction has been completed.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r
-{\r
- __ASM volatile ("isb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Data Synchronization Barrier\r
- \details Acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r
-{\r
- __ASM volatile ("dsb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Data Memory Barrier\r
- \details Ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r
-{\r
- __ASM volatile ("dmb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Reverse byte order (32 bit)\r
- \details Reverses the byte order in integer value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
- return __builtin_bswap32(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
- \brief Reverse byte order (16 bit)\r
- \details Reverses the byte order in two unsigned short values.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Reverse byte order in signed short value\r
- \details Reverses the byte order in a signed short value with sign extension to integer.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- return (short)__builtin_bswap16(value);\r
-#else\r
- int32_t result;\r
-\r
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
- \brief Rotate Right in unsigned value (32 bit)\r
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
- \param [in] op1 Value to rotate\r
- \param [in] op2 Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-{\r
- return (op1 >> op2) | (op1 << (32U - op2));\r
-}\r
-\r
-\r
-/**\r
- \brief Breakpoint\r
- \details Causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
-\r
-\r
-/**\r
- \brief Reverse bit order of value\r
- \details Reverses the bit order of the given value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
-#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
- (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) )\r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
-#else\r
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
-\r
- result = value; /* r will be reversed bits of v; first get LSB of v */\r
- for (value >>= 1U; value; value >>= 1U)\r
- {\r
- result <<= 1U;\r
- result |= value & 1U;\r
- s--;\r
- }\r
- result <<= s; /* shift when v's highest bits are zero */\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Count leading zeros\r
- \details Counts the number of leading zeros of a data value.\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __builtin_clz\r
-\r
-\r
-#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
- (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) )\r
-\r
-/**\r
- \brief LDR Exclusive (8 bit)\r
- \details Executes a exclusive LDR instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return ((uint8_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (16 bit)\r
- \details Executes a exclusive LDR instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return ((uint16_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (32 bit)\r
- \details Executes a exclusive LDR instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STR Exclusive (8 bit)\r
- \details Executes a exclusive STR instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STR Exclusive (16 bit)\r
- \details Executes a exclusive STR instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STR Exclusive (32 bit)\r
- \details Executes a exclusive STR instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Remove the exclusive lock\r
- \details Removes the exclusive lock which is created by LDREX.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r
-{\r
- __ASM volatile ("clrex" ::: "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Signed Saturate\r
- \details Saturates a signed value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT(ARG1,ARG2) \\r
-({ \\r
- int32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/**\r
- \brief Unsigned Saturate\r
- \details Saturates an unsigned value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/**\r
- \brief Rotate Right with Extend (32 bit)\r
- \details Moves each bit of a bitstring right by one bit.\r
- The carry input is shifted in at the left end of the bitstring.\r
- \param [in] value Value to rotate\r
- \return Rotated value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
-#endif\r
- return ((uint8_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
-#endif\r
- return ((uint16_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged STRT instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
-{\r
- __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged STRT instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
-{\r
- __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged STRT instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
-{\r
- __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
-}\r
-\r
-#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
- (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
- Access to dedicated SIMD instructions\r
- @{\r
-*/\r
-\r
-#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U))\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-#define __SSAT16(ARG1,ARG2) \\r
-({ \\r
- int32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-#define __USAT16(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-#define __PKHBT(ARG1,ARG2,ARG3) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
- __RES; \\r
- })\r
-\r
-#define __PKHTB(ARG1,ARG2,ARG3) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
- if (ARG3 == 0) \\r
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
- else \\r
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
- __RES; \\r
- })\r
-\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#if defined ( __GNUC__ )\r
-#pragma GCC diagnostic pop\r
-#endif\r
-\r
-#endif /* __CMSIS_GCC_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm4.h\r
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CM4_H_GENERIC\r
-#define __CORE_CM4_H_GENERIC\r
-\r
-#include <stdint.h>\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/**\r
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/**\r
- \ingroup Cortex_M4\r
- @{\r
- */\r
-\r
-/* CMSIS CM4 definitions */\r
-#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x04U) /*!< Cortex-M Core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __packed\r
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
- #define __STATIC_INLINE static inline\r
-\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #if defined __ARM_PCS_VFP\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1U\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TMS470__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#elif defined ( __CSMC__ )\r
- #if ( __CSMC__ & 0x400U)\r
- #if (__FPU_PRESENT == 1U)\r
- #define __FPU_USED 1U\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0U\r
- #endif\r
- #else\r
- #define __FPU_USED 0U\r
- #endif\r
-\r
-#endif\r
-\r
-#include "core_cmInstr.h" /* Core Instruction Access */\r
-#include "core_cmFunc.h" /* Core Function Access */\r
-#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM4_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM4_H_DEPENDANT\r
-#define __CORE_CM4_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM4_REV\r
- #define __CM4_REV 0x0000U\r
- #warning "__CM4_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __FPU_PRESENT\r
- #define __FPU_PRESENT 0U\r
- #warning "__FPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0U\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4U\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0U\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/* following defines should be used for structure members */\r
-#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
-#define __OM volatile /*! Defines 'write only' structure member permissions */\r
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
-\r
-/*@} end of group Cortex_M4 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- - Core FPU Register\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-/* APSR Register Definitions */\r
-#define APSR_N_Pos 31U /*!< APSR: N Position */\r
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
-\r
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
-\r
-#define APSR_C_Pos 29U /*!< APSR: C Position */\r
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
-\r
-#define APSR_V_Pos 28U /*!< APSR: V Position */\r
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
-\r
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
-\r
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-/* IPSR Register Definitions */\r
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-/* xPSR Register Definitions */\r
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
-\r
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
-\r
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
-\r
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
-\r
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
-\r
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
-\r
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
-\r
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
-\r
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
-\r
-\r
-/**\r
- \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/* CONTROL Register Definitions */\r
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
-\r
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
-\r
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24U];\r
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24U];\r
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24U];\r
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24U];\r
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56U];\r
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644U];\r
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[5U];\r
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Register Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Register Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */\r
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */\r
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __OM union\r
- {\r
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864U];\r
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15U];\r
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15U];\r
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29U];\r
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43U];\r
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6U];\r
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1U];\r
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1U];\r
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2U];\r
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55U];\r
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131U];\r
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759U];\r
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1U];\r
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39U];\r
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8U];\r
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if (__MPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register Definitions */\r
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register Definitions */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register Definitions */\r
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register Definitions */\r
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register Definitions */\r
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-#if (__FPU_PRESENT == 1U)\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
- \brief Type definitions for the Floating Point Unit (FPU)\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1U];\r
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register Definitions */\r
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register Definitions */\r
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register Definitions */\r
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 Definitions */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 Definitions */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-#endif\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/**\r
- \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register Definitions */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register Definitions */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register Definitions */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_bitfield Core register bit field macros\r
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
- @{\r
- */\r
-\r
-/**\r
- \brief Mask and shift a bit field value for use in a register bit range.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of the bit field.\r
- \return Masked and shifted value.\r
-*/\r
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
-\r
-/**\r
- \brief Mask and shift a register value to extract a bit filed value.\r
- \param[in] field Name of the register bit field.\r
- \param[in] value Value of register.\r
- \return Masked and shifted bit field value.\r
-*/\r
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
-\r
-/*@} end of group CMSIS_core_bitfield */\r
-\r
-\r
-/**\r
- \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M4 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1U)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-#if (__FPU_PRESENT == 1U)\r
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/**\r
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/**\r
- \brief Set Priority Grouping\r
- \details Sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Grouping\r
- \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
-}\r
-\r
-\r
-/**\r
- \brief Enable External Interrupt\r
- \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Disable External Interrupt\r
- \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Pending Interrupt\r
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Pending Interrupt\r
- \details Sets the pending bit of an external interrupt.\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Clear Pending Interrupt\r
- \details Clears the pending bit of an external interrupt.\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
-}\r
-\r
-\r
-/**\r
- \brief Get Active Interrupt\r
- \details Reads the active register in NVIC and returns the active bit.\r
- \param [in] IRQn Interrupt number.\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
-}\r
-\r
-\r
-/**\r
- \brief Set Interrupt Priority\r
- \details Sets the priority of an interrupt.\r
- \note The priority cannot be set for every core interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
- else\r
- {\r
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Get Interrupt Priority\r
- \details Reads the priority of an interrupt.\r
- The interrupt number can be positive to specify an external (device specific) interrupt,\r
- or negative to specify an internal (core) interrupt.\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority.\r
- Value is aligned automatically to the implemented priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if ((int32_t)(IRQn) < 0)\r
- {\r
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
- else\r
- {\r
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
- }\r
-}\r
-\r
-\r
-/**\r
- \brief Encode Priority\r
- \details Encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- return (\r
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- \brief Decode Priority\r
- \details Decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
-}\r
-\r
-\r
-/**\r
- \brief System Reset\r
- \details Initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
-\r
- for(;;) /* wait until reset */\r
- {\r
- __NOP();\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0U)\r
-\r
-/**\r
- \brief System Tick Configuration\r
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
- \param [in] ticks Number of ticks between two interrupts.\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
- {\r
- return (1UL); /* Reload value impossible */\r
- }\r
-\r
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0UL); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/**\r
- \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/**\r
- \brief ITM Send Character\r
- \details Transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
- \param [in] ch Character to transmit.\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0U].u32 == 0UL)\r
- {\r
- __NOP();\r
- }\r
- ITM->PORT[0U].u8 = (uint8_t)ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Receive Character\r
- \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
-{\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
- {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- \brief ITM Check Character\r
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void)\r
-{\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
- {\r
- return (0); /* no character available */\r
- }\r
- else\r
- {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM4_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmFunc.h\r
- * @brief CMSIS Cortex-M Core Function Access Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CMFUNC_H\r
-#define __CORE_CMFUNC_H\r
-\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
-*/\r
-\r
-/*------------------ RealView Compiler -----------------*/\r
-#if defined ( __CC_ARM )\r
- #include "cmsis_armcc.h"\r
-\r
-/*------------------ ARM Compiler V6 -------------------*/\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #include "cmsis_armcc_V6.h"\r
-\r
-/*------------------ GNU Compiler ----------------------*/\r
-#elif defined ( __GNUC__ )\r
- #include "cmsis_gcc.h"\r
-\r
-/*------------------ ICC Compiler ----------------------*/\r
-#elif defined ( __ICCARM__ )\r
- #include <cmsis_iar.h>\r
-\r
-/*------------------ TI CCS Compiler -------------------*/\r
-#elif defined ( __TMS470__ )\r
- #include <cmsis_ccs.h>\r
-\r
-/*------------------ TASKING Compiler ------------------*/\r
-#elif defined ( __TASKING__ )\r
- /*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-/*------------------ COSMIC Compiler -------------------*/\r
-#elif defined ( __CSMC__ )\r
- #include <cmsis_csm.h>\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-#endif /* __CORE_CMFUNC_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmInstr.h\r
- * @brief CMSIS Cortex-M Core Instruction Access Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CMINSTR_H\r
-#define __CORE_CMINSTR_H\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-/*------------------ RealView Compiler -----------------*/\r
-#if defined ( __CC_ARM )\r
- #include "cmsis_armcc.h"\r
-\r
-/*------------------ ARM Compiler V6 -------------------*/\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #include "cmsis_armcc_V6.h"\r
-\r
-/*------------------ GNU Compiler ----------------------*/\r
-#elif defined ( __GNUC__ )\r
- #include "cmsis_gcc.h"\r
-\r
-/*------------------ ICC Compiler ----------------------*/\r
-#elif defined ( __ICCARM__ )\r
- #include <cmsis_iar.h>\r
-\r
-/*------------------ TI CCS Compiler -------------------*/\r
-#elif defined ( __TMS470__ )\r
- #include <cmsis_ccs.h>\r
-\r
-/*------------------ TASKING Compiler ------------------*/\r
-#elif defined ( __TASKING__ )\r
- /*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-/*------------------ COSMIC Compiler -------------------*/\r
-#elif defined ( __CSMC__ )\r
- #include <cmsis_csm.h>\r
-\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-#endif /* __CORE_CMINSTR_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmSimd.h\r
- * @brief CMSIS Cortex-M SIMD Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CMSIMD_H\r
-#define __CORE_CMSIMD_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
- Access to dedicated SIMD instructions\r
- @{\r
-*/\r
-\r
-/*------------------ RealView Compiler -----------------*/\r
-#if defined ( __CC_ARM )\r
- #include "cmsis_armcc.h"\r
-\r
-/*------------------ ARM Compiler V6 -------------------*/\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #include "cmsis_armcc_V6.h"\r
-\r
-/*------------------ GNU Compiler ----------------------*/\r
-#elif defined ( __GNUC__ )\r
- #include "cmsis_gcc.h"\r
-\r
-/*------------------ ICC Compiler ----------------------*/\r
-#elif defined ( __ICCARM__ )\r
- #include <cmsis_iar.h>\r
-\r
-/*------------------ TI CCS Compiler -------------------*/\r
-#elif defined ( __TMS470__ )\r
- #include <cmsis_ccs.h>\r
-\r
-/*------------------ TASKING Compiler ------------------*/\r
-#elif defined ( __TASKING__ )\r
- /*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-/*------------------ COSMIC Compiler -------------------*/\r
-#elif defined ( __CSMC__ )\r
- #include <cmsis_csm.h>\r
-\r
-#endif\r
-\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CMSIMD_H */\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-\r
-#ifndef FREERTOS_CONFIG_H\r
-#define FREERTOS_CONFIG_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/*-----------------------------------------------------------\r
- * Application specific definitions.\r
- *\r
- * These definitions should be adjusted for your particular hardware and\r
- * application requirements.\r
- *\r
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
- *\r
- * See http://www.freertos.org/a00110.html.\r
- *----------------------------------------------------------*/\r
-\r
-\r
-/* Set configCREATE_LOW_POWER_DEMO to one to run the simple blinky demo low power\r
-example, or 1 to run the more comprehensive test and demo application. See\r
-the comments at the top of main.c for more information. */\r
-#define configCREATE_LOW_POWER_DEMO 1\r
-\r
-/* Some configuration is dependent on the demo being built. */\r
-#if( configCREATE_LOW_POWER_DEMO == 1 )\r
-\r
- /* The low power demo uses a slow low power clock, so the SysTick clock,\r
- which is used by default by Cortex-M ports, is not used to generate the\r
- tick interrupt. */\r
- #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 1\r
-\r
- /* The slow clock used to generate the tick interrupt in the low power demo\r
- runs at 32768Hz. Ensure the clock is a multiple of the tick rate. */\r
- #define configTICK_RATE_HZ ( 128 )\r
-\r
- /* The low power demo uses the tickless idle feature. */\r
- #define configUSE_TICKLESS_IDLE 1\r
-\r
-#else\r
-\r
- /* Some of the standard demo test tasks assume a tick rate of 1KHz, even\r
- though that is faster than would normally be warranted by a real\r
- application. */\r
- #define configTICK_RATE_HZ ( 1000 )\r
-\r
- /* The full demo always has tasks to run so the tick will never be turned\r
- off. The blinky demo will use the default tickless idle implementation to\r
- turn the tick off. */\r
- #define configUSE_TICKLESS_IDLE 0\r
-\r
-#endif\r
-\r
-#define configUSE_PREEMPTION 1\r
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\r
-#define configUSE_QUEUE_SETS 1\r
-#define configUSE_IDLE_HOOK 0\r
-#define configUSE_TICK_HOOK 1\r
-#define configCPU_CLOCK_HZ 48000000\r
-#define configMAX_PRIORITIES ( 5 )\r
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 28 * 1024 ) )\r
-#define configMAX_TASK_NAME_LEN ( 10 )\r
-#define configUSE_TRACE_FACILITY 0\r
-#define configUSE_16_BIT_TICKS 0\r
-#define configIDLE_SHOULD_YIELD 1\r
-#define configUSE_MUTEXES 1\r
-#define configQUEUE_REGISTRY_SIZE 0\r
-#define configCHECK_FOR_STACK_OVERFLOW 2\r
-#define configUSE_RECURSIVE_MUTEXES 1\r
-#define configUSE_MALLOC_FAILED_HOOK 1\r
-#define configUSE_APPLICATION_TASK_TAG 0\r
-#define configUSE_COUNTING_SEMAPHORES 1\r
-#define configSUPPORT_STATIC_ALLOCATION 1\r
-\r
-/* Run time stats gathering definitions. */\r
-#define configGENERATE_RUN_TIME_STATS 0\r
-#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
-#define portGET_RUN_TIME_COUNTER_VALUE()\r
-\r
-/* This demo makes use of one or more example stats formatting functions. These\r
-format the raw data provided by the uxTaskGetSystemState() function in to human\r
-readable ASCII form. See the notes in the implementation of vTaskList() within\r
-FreeRTOS/Source/tasks.c for limitations. */\r
-#define configUSE_STATS_FORMATTING_FUNCTIONS 0\r
-\r
-/* Co-routine definitions. */\r
-#define configUSE_CO_ROUTINES 0\r
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
-\r
-/* Software timer definitions. */\r
-#define configUSE_TIMERS 1\r
-#define configTIMER_TASK_PRIORITY ( 2 )\r
-#define configTIMER_QUEUE_LENGTH 5\r
-#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
-\r
-/* Set the following definitions to 1 to include the API function, or zero\r
-to exclude the API function. */\r
-#define INCLUDE_vTaskPrioritySet 1\r
-#define INCLUDE_uxTaskPriorityGet 1\r
-#define INCLUDE_vTaskDelete 1\r
-#define INCLUDE_vTaskCleanUpResources 1\r
-#define INCLUDE_vTaskSuspend 1\r
-#define INCLUDE_vTaskDelayUntil 1\r
-#define INCLUDE_vTaskDelay 1\r
-#define INCLUDE_eTaskGetState 1\r
-#define INCLUDE_xTimerPendFunctionCall 1\r
-\r
-/* Cortex-M specific definitions. */\r
-#ifdef __NVIC_PRIO_BITS\r
- /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
- #define configPRIO_BITS __NVIC_PRIO_BITS\r
-#else\r
- #define configPRIO_BITS 3 /* 7 priority levels */\r
-#endif\r
-\r
-/* The lowest interrupt priority that can be used in a call to a "set priority"\r
-function. */\r
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x7\r
-\r
-/* The highest interrupt priority that can be used by any interrupt service\r
-routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
-\r
-/* Interrupt priorities used by the kernel port layer itself. These are generic\r
-to all Cortex-M ports, and do not rely on any particular library functions. */\r
-#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
-\r
-\r
-/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
-standard names. */\r
-#define xPortPendSVHandler PendSV_Handler\r
-#define vPortSVCHandler SVC_Handler\r
-#define xPortSysTickHandler SysTick_Handler\r
-\r
-/* Normal assert() semantics without relying on the provision of an assert.h\r
-header file. */\r
-#define configASSERT( x ) if( ( x ) == 0UL ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
-\r
-/* LED not used at present, so just increment a variable to keep a count of the\r
-number of times the LED would otherwise have been toggled. */\r
-#define configTOGGLE_LED() ulLED++\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* FREERTOS_CONFIG_H */\r
+++ /dev/null
-\r
-T220C 000:298 SEGGER J-Link V4.98e Log File (0000ms, 0270ms total)\r
-T220C 000:298 DLL Compiled: May 5 2015 11:00:52 (0000ms, 0270ms total)\r
-T220C 000:298 Logging started @ 2016-01-08 12:24 (0000ms, 0270ms total)\r
-T220C 000:298 JLINK_SetWarnOutHandler(...) (0000ms, 0270ms total)\r
-T220C 000:298 JLINK_OpenEx(...)
-Firmware: J-Link V9 compiled Oct 9 2015 20:34:47
-Hardware: V9.10
-S/N: 59101789
-Feature(s): GDB, JFlash returns O.K. (0266ms, 0536ms total)\r
-T220C 000:564 JLINK_SetErrorOutHandler(...) (0000ms, 0536ms total)\r
-T220C 000:564 JLINK_ExecCommand("ProjectFile = "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M4F_CEC1302_Clicker_2\Keil_Specific\JLinkSettings.ini"", ...)Device "UNSPECIFIED" selected. returns 0x00 (0002ms, 0538ms total)\r
-T220C 000:566 JLINK_ExecCommand("Device = ARMCM4_FP", ...)Device "UNSPECIFIED" selected. returns 0x00 (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetCompileDateTime() (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0001ms, 0539ms total)\r
-T220C 000:567 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0003ms, 0542ms total)\r
-T220C 000:570 JLINK_SetSpeed(5000) (0000ms, 0542ms total)\r
-T220C 000:570 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 4, IRPrint = 0x01 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x48 JTAG> >0x78 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG>Found Cortex-M4 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC)\r
- -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0)\r
- -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)\r
-ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM ScanLen=4 NumDevices=1 aId[0]=0x4BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0026ms, 0568ms total)\r
-T220C 000:596 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x4BA00477 (0000ms, 0568ms total)\r
-T220C 000:596 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0000ms, 0568ms total)\r
-T220C 000:596 JLINK_GetDLLVersion() returns 49805 (0000ms, 0568ms total)\r
-T220C 000:596 JLINK_CORE_GetFound() returns 0xE0000FF (0000ms, 0568ms total)\r
-T220C 000:596 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003 returns 0x00 (0000ms, 0568ms total)\r
-T220C 000:596 JLINK_ReadMem (0xE00FF000, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 03 10 F0 FF ... returns 0x00 (0001ms, 0569ms total)\r
-T220C 000:597 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0570ms total)\r
-T220C 000:598 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0571ms total)\r
-T220C 000:599 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0571ms total)\r
-T220C 000:599 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0572ms total)\r
-T220C 000:600 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0573ms total)\r
-T220C 000:601 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0573ms total)\r
-T220C 000:601 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0574ms total)\r
-T220C 000:602 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0574ms total)\r
-T220C 000:602 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0575ms total)\r
-T220C 000:603 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0576ms total)\r
-T220C 000:604 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0576ms total)\r
-T220C 000:604 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0577ms total)\r
-T220C 000:605 JLINK_ReadMemU32(0xE000EF40, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF40) - Data: 21 00 11 10 returns 0x01 (0001ms, 0578ms total)\r
-T220C 000:606 JLINK_ReadMemU32(0xE000EF44, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF44) - Data: 11 00 00 11 returns 0x01 (0000ms, 0578ms total)\r
-T220C 000:606 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 41 C2 0F 41 returns 0x01 (0001ms, 0579ms total)\r
-T220C 000:607 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0579ms total)\r
-T220C 000:607 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0)\r
- -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048)\r
- -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1225ms total)\r
-T220C 001:253 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1225ms total)\r
-T220C 001:253 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1225ms total)\r
-T220C 001:253 JLINK_Halt() returns 0x00 (0000ms, 1225ms total)\r
-T220C 001:253 JLINK_IsHalted() returns TRUE (0000ms, 1225ms total)\r
-T220C 001:253 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 1226ms total)\r
-T220C 001:254 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0000ms, 1226ms total)\r
-T220C 001:254 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 1227ms total)\r
-T220C 001:255 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_GetSpeed() returns 0x1388 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0001ms, 1228ms total)\r
-T220C 001:257 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 1229ms total)\r
-T220C 001:258 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 1230ms total)\r
-T220C 001:259 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1230ms total)\r
-T220C 001:259 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1230ms total)\r
-T220C 001:270 JLINK_WriteMem(0x00100000, 0x02AC Bytes, ...) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... -- CPU_WriteMem(684 bytes @ 0x00100000) returns 0x2AC (0003ms, 1233ms total)\r
-T220C 001:273 JLINK_ReadMem (0x00100000, 0x02AC Bytes, ...) -- CPU_ReadMem(684 bytes @ 0x00100000) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... returns 0x00 (0003ms, 1236ms total)\r
-T220C 001:330 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1236ms total)\r
-T220C 001:330 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1882ms total)\r
-T220C 001:977 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1882ms total)\r
-T220C 001:977 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1882ms total)\r
-T220C 001:977 JLINK_ReadMem (0x00118000, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x00118000) - Data: FE E7 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... returns 0x00 (0001ms, 1883ms total)\r
-T220C 002:517 JLINK_ReadMem (0x001001DA, 0x0002 Bytes, ...) -- CPU_ReadMem(2 bytes @ 0x001001DA) - Data: 00 47 returns 0x00 (0001ms, 1884ms total)\r
-T220C 002:518 JLINK_ReadMem (0x001001DC, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x001001DC) - Data: 4F F0 01 07 FE E7 4F F0 02 07 FE E7 4F F0 03 07 ... returns 0x00 (0001ms, 1885ms total)\r
-T220C 002:601 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1885ms total)\r
-T220C 002:601 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 2531ms total)\r
-T220C 003:248 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2531ms total)\r
-T220C 003:249 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2531ms total)\r
-T220C 003:249 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00 returns 0x01 (0000ms, 2531ms total)\r
-T1854 003:277 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0001ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(FPSCR) returns 0x00000000 (0005ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:292 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2537ms total)\r
-T1854 003:292 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total)\r
-T1854 003:292 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS8) returns 0x00000000 (0001ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R12) returns 0x00000000 (0001ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2539ms total)\r
-T220C 003:312 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) - Data: 00 00 00 00 returns 0x01 (0000ms, 2539ms total)\r
-T220C 027:508 JLINK_Close() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001004) >0x78 JTAG> >0x08 JTAG> (0005ms, 2544ms total)\r
-T220C 027:508 (0005ms, 2544ms total)\r
-T220C 027:508 Closed (0005ms, 2544ms total)\r
+++ /dev/null
-[BREAKPOINTS]\r
-ForceImpTypeAny = 0\r
-ShowInfoWin = 1\r
-EnableFlashBP = 2\r
-BPDuringExecution = 0\r
-[CFI]\r
-CFISize = 0x00\r
-CFIAddr = 0x00\r
-[CPU]\r
-OverrideMemMap = 0\r
-AllowSimulation = 1\r
-ScriptFile=""\r
-[FLASH]\r
-CacheExcludeSize = 0x00\r
-CacheExcludeAddr = 0x00\r
-MinNumBytesFlashDL = 0\r
-SkipProgOnCRCMatch = 1\r
-VerifyDownload = 1\r
-AllowCaching = 1\r
-EnableFlashDL = 2\r
-Override = 1\r
-Device="Unspecified"\r
-[GENERAL]\r
-WorkRAMSize = 0x00\r
-WorkRAMAddr = 0x00\r
-RAMUsageLimit = 0x00\r
-[SWO]\r
-SWOLogFile=""\r
-[MEM]\r
-RdOverrideOrMask = 0x00\r
-RdOverrideAndMask = 0xFFFFFFFF\r
-RdOverrideAddr = 0xFFFFFFFF\r
-WrOverrideOrMask = 0x00\r
-WrOverrideAndMask = 0xFFFFFFFF\r
-WrOverrideAddr = 0xFFFFFFFF\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectGui xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_guix.xsd">
-
- <SchemaVersion>-5.1</SchemaVersion>
-
- <Header>### uVision Project, (C) Keil Software</Header>
-
- <ViewPool/>
-
- <SECTreeCtrl>
- <View>
- <WinId>38003</WinId>
- <ViewName>Registers</ViewName>
- <TableColWidths>115 235</TableColWidths>
- </View>
- <View>
- <WinId>346</WinId>
- <ViewName>Code Coverage</ViewName>
- <TableColWidths>868 678</TableColWidths>
- </View>
- <View>
- <WinId>204</WinId>
- <ViewName>Performance Analyzer</ViewName>
- <TableColWidths>1028 154 154 210</TableColWidths>
- </View>
- </SECTreeCtrl>
-
- <TreeListPane>
- <View>
- <WinId>1506</WinId>
- <ViewName>Symbols</ViewName>
- <UserString></UserString>
- <TableColWidths>70 70 70</TableColWidths>
- </View>
- <View>
- <WinId>1936</WinId>
- <ViewName>Watch 1</ViewName>
- <UserString></UserString>
- <TableColWidths>154 184 70</TableColWidths>
- </View>
- <View>
- <WinId>1937</WinId>
- <ViewName>Watch 2</ViewName>
- <UserString></UserString>
- <TableColWidths>70 70 70</TableColWidths>
- </View>
- <View>
- <WinId>1935</WinId>
- <ViewName>Call Stack + Locals</ViewName>
- <UserString></UserString>
- <TableColWidths>235 70 70</TableColWidths>
- </View>
- <View>
- <WinId>2506</WinId>
- <ViewName>Trace Data</ViewName>
- <UserString>FiltIdx=0;DescrEn=0;DescrHeight=4;FuncTrc=1;FindType=8;ColWidths=004B00870082005F004600E600C80096</UserString>
- <TableColWidths>75 135 130 95 70 230 200 150</TableColWidths>
- </View>
- </TreeListPane>
-
- <WindowSettings>
- <LogicAnalizer>
- <ShowLACursor>0</ShowLACursor>
- <ShowSignalInfo>0</ShowSignalInfo>
- <ShowCycles>0</ShowCycles>
- <LeftSideBarSize>50</LeftSideBarSize>
- <TimeBaseIndex>16</TimeBaseIndex>
- </LogicAnalizer>
- </WindowSettings>
-
- <WinLayoutEx>
- <sActiveDebugView></sActiveDebugView>
- <WindowPosition>
- <length>44</length>
- <flags>2</flags>
- <showCmd>3</showCmd>
- <MinPosition>
- <xPos>-1</xPos>
- <yPos>-1</yPos>
- </MinPosition>
- <MaxPosition>
- <xPos>-1</xPos>
- <yPos>-1</yPos>
- </MaxPosition>
- <NormalPosition>
- <Top>0</Top>
- <Left>0</Left>
- <Right>1238</Right>
- <Bottom>872</Bottom>
- </NormalPosition>
- </WindowPosition>
- <MDIClientArea>
- <RegID>0</RegID>
- <MDITabState>
- <Len>270</Len>
- <Data>0100000004000000010000000100000001000000010000000000000002000000000000000100000001000000000000002800000028000000010000000100000000000000010000004A433A5C455C4465765C4672656552544F535C576F726B696E67436F70795C4672656552544F535C44656D6F5C434F525445585F4D34465F434543313330325F4B65696C5C6D61696E2E6300000000066D61696E2E6300000000BECEA100FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000340100005E000000800700006E030000</Data>
- </MDITabState>
- </MDIClientArea>
- <ViewEx>
- <ViewType>0</ViewType>
- <ViewName>Build</ViewName>
- <Window>
- <RegID>-1</RegID>
- <PaneID>-1</PaneID>
- <IsVisible>0</IsVisible>
- <IsFloating>0</IsFloating>
- <IsTabbed>0</IsTabbed>
- <IsActivated>0</IsActivated>
- <MRUWidth>32767</MRUWidth>
- <PinState>0</PinState>
- <RecentFrameAlignment>4096</RecentFrameAlignment>
- <RecentRowIndex>0</RecentRowIndex>
- <RectRecentDocked>
- <Len>16</Len>
- <Data>D60000004B000000E4040000DB000000</Data>
- </RectRecentDocked>
- <RectRecentFloat>
- <Len>16</Len>
- <Data>D60000005E000000E4040000EE000000</Data>
- </RectRecentFloat>
- </Window>
- <Window>
- <RegID>1005</RegID>
- <PaneID>1005</PaneID>
- <IsVisible>1</IsVisible>
- <IsFloating>0</IsFloating>
- <IsTabbed>0</IsTabbed>
- <IsActivated>0</IsActivated>
- <MRUWidth>32767</MRUWidth>
- <PinState>0</PinState>
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+++ /dev/null
-/*\r
- FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*\r
- * "Reg test" tasks - These fill the registers with known values, then check\r
- * that each register maintains its expected value for the lifetime of the\r
- * task. Each task uses a different set of values. The reg test tasks execute\r
- * with a very low priority, so get preempted very frequently. A register\r
- * containing an unexpected value is indicative of an error in the context\r
- * switching mechanism.\r
- */\r
-\r
-void vRegTest1Implementation( void ) __attribute__ ((naked));\r
-void vRegTest2Implementation( void ) __attribute__ ((naked));\r
-\r
-void vRegTest1Implementation( void )\r
-{\r
- __asm volatile\r
- (\r
- ".extern ulRegTest1LoopCounter \n"\r
- "/* Fill the core registers with known values. */ \n"\r
- "mov r0, #100 \n"\r
- "mov r1, #101 \n"\r
- "mov r2, #102 \n"\r
- "mov r3, #103 \n"\r
- "mov r4, #104 \n"\r
- "mov r5, #105 \n"\r
- "mov r6, #106 \n"\r
- "mov r7, #107 \n"\r
- "mov r8, #108 \n"\r
- "mov r9, #109 \n"\r
- "mov r10, #110 \n"\r
- "mov r11, #111 \n"\r
- "mov r12, #112 \n"\r
-\r
- "/* Fill the VFP registers with known values. */ \n"\r
- "vmov d0, r0, r1 \n"\r
- "vmov d1, r2, r3 \n"\r
- "vmov d2, r4, r5 \n"\r
- "vmov d3, r6, r7 \n"\r
- "vmov d4, r8, r9 \n"\r
- "vmov d5, r10, r11 \n"\r
- "vmov d6, r0, r1 \n"\r
- "vmov d7, r2, r3 \n"\r
- "vmov d8, r4, r5 \n"\r
- "vmov d9, r6, r7 \n"\r
- "vmov d10, r8, r9 \n"\r
- "vmov d11, r10, r11 \n"\r
- "vmov d12, r0, r1 \n"\r
- "vmov d13, r2, r3 \n"\r
- "vmov d14, r4, r5 \n"\r
- "vmov d15, r6, r7 \n"\r
-\r
- "reg1_loop: \n"\r
- "/* Check all the VFP registers still contain the values set above. \n"\r
- "First save registers that are clobbered by the test. */ \n"\r
- "push { r0-r1 } \n"\r
-\r
- "vmov r0, r1, d0 \n"\r
- "cmp r0, #100 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #101 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d1 \n"\r
- "cmp r0, #102 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #103 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d2 \n"\r
- "cmp r0, #104 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #105 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d3 \n"\r
- "cmp r0, #106 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #107 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d4 \n"\r
- "cmp r0, #108 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #109 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d5 \n"\r
- "cmp r0, #110 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #111 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d6 \n"\r
- "cmp r0, #100 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #101 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d7 \n"\r
- "cmp r0, #102 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #103 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d8 \n"\r
- "cmp r0, #104 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #105 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d9 \n"\r
- "cmp r0, #106 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #107 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d10 \n"\r
- "cmp r0, #108 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #109 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d11 \n"\r
- "cmp r0, #110 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #111 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d12 \n"\r
- "cmp r0, #100 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #101 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d13 \n"\r
- "cmp r0, #102 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #103 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d14 \n"\r
- "cmp r0, #104 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #105 \n"\r
- "bne reg1_error_loopf \n"\r
- "vmov r0, r1, d15 \n"\r
- "cmp r0, #106 \n"\r
- "bne reg1_error_loopf \n"\r
- "cmp r1, #107 \n"\r
- "bne reg1_error_loopf \n"\r
-\r
- "/* Restore the registers that were clobbered by the test. */ \n"\r
- "pop {r0-r1} \n"\r
-\r
- "/* VFP register test passed. Jump to the core register test. */ \n"\r
- "b reg1_loopf_pass \n"\r
-\r
- "reg1_error_loopf: \n"\r
- "/* If this line is hit then a VFP register value was found to be incorrect. */ \n"\r
- "b reg1_error_loopf \n"\r
-\r
- "reg1_loopf_pass: \n"\r
-\r
- "cmp r0, #100 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r1, #101 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r2, #102 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r3, #103 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r4, #104 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r5, #105 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r6, #106 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r7, #107 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r8, #108 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r9, #109 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r10, #110 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r11, #111 \n"\r
- "bne reg1_error_loop \n"\r
- "cmp r12, #112 \n"\r
- "bne reg1_error_loop \n"\r
-\r
- "/* Everything passed, increment the loop counter. */ \n"\r
- "push { r0-r1 } \n"\r
- "ldr r0, =ulRegTest1LoopCounter \n"\r
- "ldr r1, [r0] \n"\r
- "adds r1, r1, #1 \n"\r
- "str r1, [r0] \n"\r
- "pop { r0-r1 } \n"\r
-\r
- "/* Start again. */ \n"\r
- "b reg1_loop \n"\r
-\r
- "reg1_error_loop: \n"\r
- "/* If this line is hit then there was an error in a core register value. \n"\r
- "The loop ensures the loop counter stops incrementing. */ \n"\r
- "b reg1_error_loop \n"\r
- "nop "\r
- ); /* __asm volatile. */\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vRegTest2Implementation( void )\r
-{\r
- __asm volatile\r
- (\r
- ".extern ulRegTest2LoopCounter \n"\r
- "/* Set all the core registers to known values. */ \n"\r
- "mov r0, #-1 \n"\r
- "mov r1, #1 \n"\r
- "mov r2, #2 \n"\r
- "mov r3, #3 \n"\r
- "mov r4, #4 \n"\r
- "mov r5, #5 \n"\r
- "mov r6, #6 \n"\r
- "mov r7, #7 \n"\r
- "mov r8, #8 \n"\r
- "mov r9, #9 \n"\r
- "mov r10, #10 \n"\r
- "mov r11, #11 \n"\r
- "mov r12, #12 \n"\r
-\r
- "/* Set all the VFP to known values. */ \n"\r
- "vmov d0, r0, r1 \n"\r
- "vmov d1, r2, r3 \n"\r
- "vmov d2, r4, r5 \n"\r
- "vmov d3, r6, r7 \n"\r
- "vmov d4, r8, r9 \n"\r
- "vmov d5, r10, r11 \n"\r
- "vmov d6, r0, r1 \n"\r
- "vmov d7, r2, r3 \n"\r
- "vmov d8, r4, r5 \n"\r
- "vmov d9, r6, r7 \n"\r
- "vmov d10, r8, r9 \n"\r
- "vmov d11, r10, r11 \n"\r
- "vmov d12, r0, r1 \n"\r
- "vmov d13, r2, r3 \n"\r
- "vmov d14, r4, r5 \n"\r
- "vmov d15, r6, r7 \n"\r
-\r
- "reg2_loop: \n"\r
-\r
- "/* Check all the VFP registers still contain the values set above. \n"\r
- "First save registers that are clobbered by the test. */ \n"\r
- "push { r0-r1 } \n"\r
-\r
- "vmov r0, r1, d0 \n"\r
- "cmp r0, #-1 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #1 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d1 \n"\r
- "cmp r0, #2 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #3 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d2 \n"\r
- "cmp r0, #4 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #5 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d3 \n"\r
- "cmp r0, #6 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #7 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d4 \n"\r
- "cmp r0, #8 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #9 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d5 \n"\r
- "cmp r0, #10 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #11 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d6 \n"\r
- "cmp r0, #-1 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #1 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d7 \n"\r
- "cmp r0, #2 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #3 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d8 \n"\r
- "cmp r0, #4 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #5 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d9 \n"\r
- "cmp r0, #6 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #7 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d10 \n"\r
- "cmp r0, #8 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #9 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d11 \n"\r
- "cmp r0, #10 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #11 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d12 \n"\r
- "cmp r0, #-1 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #1 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d13 \n"\r
- "cmp r0, #2 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #3 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d14 \n"\r
- "cmp r0, #4 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #5 \n"\r
- "bne reg2_error_loopf \n"\r
- "vmov r0, r1, d15 \n"\r
- "cmp r0, #6 \n"\r
- "bne reg2_error_loopf \n"\r
- "cmp r1, #7 \n"\r
- "bne reg2_error_loopf \n"\r
-\r
- "/* Restore the registers that were clobbered by the test. */ \n"\r
- "pop {r0-r1} \n"\r
-\r
- "/* VFP register test passed. Jump to the core register test. */ \n"\r
- "b reg2_loopf_pass \n"\r
-\r
- "reg2_error_loopf: \n"\r
- "/* If this line is hit then a VFP register value was found to be \n"\r
- "incorrect. */ \n"\r
- "b reg2_error_loopf \n"\r
-\r
- "reg2_loopf_pass: \n"\r
-\r
- "cmp r0, #-1 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r1, #1 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r2, #2 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r3, #3 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r4, #4 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r5, #5 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r6, #6 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r7, #7 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r8, #8 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r9, #9 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r10, #10 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r11, #11 \n"\r
- "bne reg2_error_loop \n"\r
- "cmp r12, #12 \n"\r
- "bne reg2_error_loop \n"\r
-\r
- "/* Increment the loop counter to indicate this test is still functioning \n"\r
- "correctly. */ \n"\r
- "push { r0-r1 } \n"\r
- "ldr r0, =ulRegTest2LoopCounter \n"\r
- "ldr r1, [r0] \n"\r
- "adds r1, r1, #1 \n"\r
- "str r1, [r0] \n"\r
-\r
- "/* Yield to increase test coverage. */ \n"\r
- "movs r0, #0x01 \n"\r
- "ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ \n"\r
- "lsl r0, r0, #28 /* Shift to PendSV bit */ \n"\r
- "str r0, [r1] \n"\r
- "dsb \n"\r
-\r
- "pop { r0-r1 } \n"\r
-\r
- "/* Start again. */ \n"\r
- "b reg2_loop \n"\r
-\r
- "reg2_error_loop: \n"\r
- "/* If this line is hit then there was an error in a core register value. \n"\r
- "This loop ensures the loop counter variable stops incrementing. */ \n"\r
- "b reg2_error_loop \n"\r
- ); /* __asm volatile */\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
+++ /dev/null
-//Initialization file for the application code\r
-RESET\r
-T\r
-T\r
-T\r
-//eval PC = *(&(__isr_vector) + 1) ; // startup code loc to the Jump routine\r
-eval PC = Reset_Handler;\r
-T\r
+++ /dev/null
-/*\r
- * Memory Spaces Definitions.\r
- *\r
- * Need modifying for a specific board. \r
- * FLASH.ORIGIN: starting address of flash\r
- * FLASH.LENGTH: length of flash\r
- * RAM.ORIGIN: starting address of RAM bank 0\r
- * RAM.LENGTH: length of RAM bank 0\r
- *\r
- * The values below can be addressed in further linker scripts\r
- * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.\r
- */\r
-\r
-MEMORY\r
-{\r
- ROM (rx) : ORIGIN = 0x100000, LENGTH = 0x18000\r
- RAM (rw) : ORIGIN = 0x118000, LENGTH = 0x8000\r
-}\r
-\r
+++ /dev/null
-/*\r
- * Default linker script for GCC MEC1322\r
- * Based upon linker scripts from GNU ARM Eclipse plug-in\r
- */\r
-\r
-INCLUDE mem.ld\r
-\r
-/*\r
- * The '__stack' definition is required by crt0, do not remove it.\r
- */\r
-/* Place top of stack immediate before ROM Log\r
- *__stack = ORIGIN(RAM) + LENGTH(RAM);\r
- */\r
-__stack = ORIGIN(RAM) + LENGTH(RAM);\r
-\r
-_estack = __stack;\r
-\r
-/*\r
- * Default stack sizes.\r
- * These are used by the startup in order to allocate stacks\r
- * for the different modes.\r
- */\r
-\r
-__Main_Stack_Size = 2048 ;\r
-\r
-PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ;\r
-\r
-__Main_Stack_Limit = __stack - __Main_Stack_Size ;\r
-\r
-/*"PROVIDE" allows to easily override these values from an object file or the command line. */\r
-PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ;\r
-\r
-/*\r
- * There will be a link error if there is not this amount of\r
- * RAM free at the end.\r
- */\r
-_Minimum_Stack_Size = 256 ;\r
-\r
-/*\r
- * Default heap definitions.\r
- * The heap start immediately after the last statically allocated\r
- * .sbss/.noinit section, and extends up to the main stack limit.\r
- */\r
-PROVIDE ( _Heap_Begin = _end_noinit ) ;\r
-PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ;\r
-\r
-/*\r
- * The entry point is informative, for debuggers and simulators,\r
- * since the Cortex-M vector points to it anyway.\r
- */\r
-ENTRY(_start)\r
-\r
-/* Sections Definitions */\r
-\r
-SECTIONS\r
-{\r
- /*\r
- * For Cortex-M devices, the beginning of the startup code is stored in\r
- * the .isr_vector section, which goes to ROM\r
- */\r
- \r
- .isr_vector :\r
- {\r
- . = ALIGN(4);\r
- _isr_vector = .;\r
- KEEP(*(.isr_vector))\r
- . = ALIGN(4);\r
- } >ROM\r
- \r
- \r
- .text :\r
- {\r
- . = ALIGN(4);\r
-\r
- /*\r
- * This section is here for convenience, to store the\r
- * startup code at the beginning of the flash area, hoping that\r
- * this will increase the readability of the listing.\r
- */\r
- KEEP(*(.after_vectors .after_vectors.*)) /* Startup code and ISR */\r
-\r
- . = ALIGN(4);\r
-\r
- /*\r
- * These are the old initialisation sections, intended to contain\r
- * naked code, with the prologue/epilogue added by crti.o/crtn.o\r
- * when linking with startup files. The standalone startup code\r
- * currently does not run these, better use the init arrays below.\r
- */\r
- KEEP(*(.init))\r
- KEEP(*(.fini))\r
-\r
- . = ALIGN(4);\r
-\r
- /*\r
- * The preinit code, i.e. an array of pointers to initialisation\r
- * functions to be performed before constructors.\r
- */\r
- PROVIDE_HIDDEN (__preinit_array_start = .);\r
-\r
- /*\r
- * Used to run the SystemInit() before anything else.\r
- */\r
- KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))\r
-\r
- /*\r
- * Used for other platform inits.\r
- */\r
- KEEP(*(.preinit_array_platform .preinit_array_platform.*))\r
-\r
- /*\r
- * The application inits. If you need to enforce some order in\r
- * execution, create new sections, as before.\r
- */\r
- KEEP(*(.preinit_array .preinit_array.*))\r
-\r
- PROVIDE_HIDDEN (__preinit_array_end = .);\r
-\r
- . = ALIGN(4);\r
-\r
- /*\r
- * The init code, i.e. an array of pointers to static constructors.\r
- */\r
- PROVIDE_HIDDEN (__init_array_start = .);\r
- KEEP(*(SORT(.init_array.*)))\r
- KEEP(*(.init_array))\r
- PROVIDE_HIDDEN (__init_array_end = .);\r
-\r
- . = ALIGN(4);\r
-\r
- /*\r
- * The fini code, i.e. an array of pointers to static destructors.\r
- */\r
- PROVIDE_HIDDEN (__fini_array_start = .);\r
- KEEP(*(SORT(.fini_array.*)))\r
- KEEP(*(.fini_array))\r
- PROVIDE_HIDDEN (__fini_array_end = .);\r
- . = ALIGN(4);\r
-\r
- . = ALIGN(4);\r
-\r
- *(.text*) /* all remaining code */\r
-\r
- *(vtable) /* C++ virtual tables */\r
-\r
- } >ROM\r
-\r
- .rodata :\r
- {\r
- *(.rodata*) /* read-only data (constants) */\r
- } >ROM\r
-\r
- .glue :\r
- {\r
- KEEP(*(.eh_frame*))\r
-\r
- /*\r
- * Stub sections generated by the linker, to glue together\r
- * ARM and Thumb code. .glue_7 is used for ARM code calling\r
- * Thumb code, and .glue_7t is used for Thumb code calling\r
- * ARM code. Apparently always generated by the linker, for some\r
- * architectures, so better leave them here.\r
- */\r
- *(.glue_7)\r
- *(.glue_7t)\r
- } >ROM\r
-\r
- /* ARM magic sections */\r
- .ARM.extab :\r
- {\r
- *(.ARM.extab* .gnu.linkonce.armextab.*)\r
- } > ROM\r
-\r
- __exidx_start = .;\r
- .ARM.exidx :\r
- {\r
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
- } > ROM\r
- __exidx_end = .;\r
-\r
- . = ALIGN(4);\r
- _etext = .;\r
- __etext = .;\r
-\r
- /*\r
- * This address is used by the startup code to\r
- * initialise the .data section.\r
- */\r
- _sidata = _etext;\r
-\r
- /* MEMORY_ARRAY */\r
- /*\r
- .ROarraySection :\r
- {\r
- *(.ROarraySection .ROarraySection.*)\r
- } >MEMORY_ARRAY\r
- */\r
- /*\r
- * The initialised data section.\r
- * The program executes knowing that the data is in the RAM\r
- * but the loader puts the initial values in the ROM (inidata).\r
- * It is one task of the startup to copy the initial values from\r
- * ROM to RAM.\r
- */\r
- .data : AT ( _sidata )\r
- {\r
- . = ALIGN(4);\r
-\r
- /* This is used by the startup code to initialise the .data section */\r
- _sdata = . ; /* STM specific definition */\r
- __data_start__ = . ;\r
- *(.data_begin .data_begin.*)\r
-\r
- *(.data .data.*)\r
-\r
- *(.data_end .data_end.*)\r
- . = ALIGN(4);\r
-\r
- /* This is used by the startup code to initialise the .data section */\r
- _edata = . ; /* STM specific definition */\r
- __data_end__ = . ;\r
-\r
- } >RAM\r
-\r
-\r
- /*\r
- * The uninitialised data section. NOLOAD is used to avoid\r
- * the "section `.bss' type changed to PROGBITS" warning\r
- */\r
- .bss (NOLOAD) :\r
- {\r
- . = ALIGN(4);\r
- __bss_start__ = .; /* standard newlib definition */\r
- _sbss = .; /* STM specific definition */\r
- *(.bss_begin .bss_begin.*)\r
-\r
- *(.bss .bss.*)\r
- *(COMMON)\r
-\r
- *(.bss_end .bss_end.*)\r
- . = ALIGN(4);\r
- __bss_end__ = .; /* standard newlib definition */\r
- _ebss = . ; /* STM specific definition */\r
- } >RAM\r
-\r
- .noinit (NOLOAD) :\r
- {\r
- . = ALIGN(4);\r
- _noinit = .;\r
-\r
- *(.noinit .noinit.*)\r
-\r
- . = ALIGN(4) ;\r
- _end_noinit = .;\r
- } > RAM\r
-\r
- /* Mandatory to be word aligned, _sbrk assumes this */\r
- PROVIDE ( end = _end_noinit ); /* was _ebss */\r
- PROVIDE ( _end = _end_noinit );\r
- PROVIDE ( __end = _end_noinit );\r
- PROVIDE ( __end__ = _end_noinit );\r
- PROVIDE ( ROM_DATA_START = __data_start__ );\r
-\r
- /*\r
- * Used for validation only, do not allocate anything here!\r
- *\r
- * This is just to check that there is enough RAM left for the Main\r
- * stack. It should generate an error if it's full.\r
- */\r
- ._check_stack :\r
- {\r
- . = ALIGN(4);\r
-\r
- . = . + _Minimum_Stack_Size ;\r
-\r
- . = ALIGN(4);\r
- } >RAM\r
-\r
- ._check_rom_log :\r
- {\r
- . = ALIGN(4);\r
-\r
-/* . = . + __ROM_Log_Size ; */\r
-\r
- . = ALIGN(4);\r
- } >RAM\r
-\r
-/*\r
- .bss_CCMRAM : ALIGN(4)\r
- {\r
- *(.bss.CCMRAM .bss.CCMRAM.*)\r
- } > CCMRAM\r
-*/\r
- /*\r
- * The ROM Bank1.\r
- * The C or assembly source must explicitly place the code\r
- * or data there using the "section" attribute.\r
- */\r
-\r
-\r
- /* remaining code */\r
- /* read-only data (constants) */\r
-/*\r
- .b1text :\r
- {\r
- *(.b1text)\r
- *(.b1rodata)\r
- *(.b1rodata.*)\r
- } >ROMB1\r
-*/\r
- /*\r
- * The EXTMEM.\r
- * The C or assembly source must explicitly place the code or data there\r
- * using the "section" attribute.\r
- */\r
-\r
- /* EXTMEM Bank0 */\r
-/*\r
- .eb0text :\r
- {\r
- *(.eb0text)\r
- *(.eb0rodata)\r
- *(.eb0rodata.*)\r
- } >EXTMEMB0\r
-*/\r
- /* EXTMEM Bank1 */\r
-/*\r
- .eb1text :\r
- {\r
- *(.eb1text)\r
- *(.eb1rodata)\r
- *(.eb1rodata.*)\r
- } >EXTMEMB1\r
-*/\r
- /* EXTMEM Bank2 */\r
-/*\r
- .eb2text :\r
- {\r
- *(.eb2text)\r
- *(.eb2rodata)\r
- *(.eb2rodata.*)\r
- } >EXTMEMB2\r
-*/\r
- /* EXTMEM Bank0 */\r
-/*\r
- .eb3text :\r
- {\r
- *(.eb3text)\r
- *(.eb3rodata)\r
- *(.eb3rodata.*)\r
- } >EXTMEMB3\r
-*/\r
-\r
- /* After that there are only debugging sections. */\r
-\r
- /* This can remove the debugging information from the standard libraries */\r
- /*\r
- DISCARD :\r
- {\r
- libc.a ( * )\r
- libm.a ( * )\r
- libgcc.a ( * )\r
- }\r
- */\r
-\r
- /* Stabs debugging sections. */\r
- .stab 0 : { *(.stab) }\r
- .stabstr 0 : { *(.stabstr) }\r
- .stab.excl 0 : { *(.stab.excl) }\r
- .stab.exclstr 0 : { *(.stab.exclstr) }\r
- .stab.index 0 : { *(.stab.index) }\r
- .stab.indexstr 0 : { *(.stab.indexstr) }\r
- .comment 0 : { *(.comment) }\r
- /*\r
- * DWARF debug sections.\r
- * Symbols in the DWARF debugging sections are relative to the beginning\r
- * of the section so we begin them at 0.\r
- */\r
- /* DWARF 1 */\r
- .debug 0 : { *(.debug) }\r
- .line 0 : { *(.line) }\r
- /* GNU DWARF 1 extensions */\r
- .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
- .debug_sfnames 0 : { *(.debug_sfnames) }\r
- /* DWARF 1.1 and DWARF 2 */\r
- .debug_aranges 0 : { *(.debug_aranges) }\r
- .debug_pubnames 0 : { *(.debug_pubnames) }\r
- /* DWARF 2 */\r
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
- .debug_abbrev 0 : { *(.debug_abbrev) }\r
- .debug_line 0 : { *(.debug_line) }\r
- .debug_frame 0 : { *(.debug_frame) }\r
- .debug_str 0 : { *(.debug_str) }\r
- .debug_loc 0 : { *(.debug_loc) }\r
- .debug_macinfo 0 : { *(.debug_macinfo) }\r
- /* SGI/MIPS DWARF 2 extensions */\r
- .debug_weaknames 0 : { *(.debug_weaknames) }\r
- .debug_funcnames 0 : { *(.debug_funcnames) }\r
- .debug_typenames 0 : { *(.debug_typenames) }\r
- .debug_varnames 0 : { *(.debug_varnames) }\r
-}\r
+++ /dev/null
-/* File: startup_ARMCM4.S
- * Purpose: startup file for Cortex-M4 devices. Should use with
- * GCC for ARM Embedded Processors
- * Version: V2.0
- * Date: 16 August 2013
- *
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
- .syntax unified
- .arch armv7e-m
-
- .section .stack
- .align 3
-
- .equ ulMainStackSize, 200 * 4
- .equ Stack_Size, 0x004
- .globl __StackTop
- .globl __StackLimit
- .extern ulMainStack
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
-
- .section .isr_vector,"a",%progbits
- .global __Vectors
- .type __Vectors, %object
- .size __Vectors, .-__Vectors
-__Vectors:
- .long ulMainStack + ulMainStackSize /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External interrupts */
- .long NVIC_Handler_I2C0
- .long NVIC_Handler_I2C1
- .long NVIC_Handler_I2C2
- .long NVIC_Handler_I2C3
- .long NVIC_Handler_DMA0
- .long NVIC_Handler_DMA1
- .long NVIC_Handler_DMA2
- .long NVIC_Handler_DMA3
- .long NVIC_Handler_DMA4
- .long NVIC_Handler_DMA5
- .long NVIC_Handler_DMA6
- .long NVIC_Handler_DMA7
- .long NVIC_Handler_LPCBERR
- .long NVIC_Handler_UART0
- .long NVIC_Handler_IMAP0
- .long NVIC_Handler_EC0_IBF
- .long NVIC_Handler_EC0_OBF
- .long NVIC_Handler_EC1_IBF
- .long NVIC_Handler_EC1_OBF
- .long NVIC_Handler_PM1_CTL
- .long NVIC_Handler_PM1_EN
- .long NVIC_Handler_PM1_STS
- .long NVIC_Handler_MIF8042_OBF
- .long NVIC_Handler_MIF8042_IBF
- .long NVIC_Handler_MAILBOX
- .long NVIC_Handler_PECI
- .long NVIC_Handler_TACH0
- .long NVIC_Handler_TACH1
- .long NVIC_Handler_ADC_SNGL
- .long NVIC_Handler_ADC_RPT
- .long NVIC_Handler_V2P_INT0
- .long NVIC_Handler_V2P_INT1
- .long NVIC_Handler_PS2_CH0
- .long NVIC_Handler_PS2_CH1
- .long NVIC_Handler_PS2_CH2
- .long NVIC_Handler_PS2_CH3
- .long NVIC_Handler_SPI0_TX
- .long NVIC_Handler_SPI0_RX
- .long NVIC_Handler_HIB_TMR
- .long NVIC_Handler_KEY_INT
- .long NVIC_Handler_KEY_WAKE
- .long NVIC_Handler_RPM_STALL
- .long NVIC_Handler_RPM_SPIN
- .long NVIC_Handler_VBAT
- .long NVIC_Handler_LED0
- .long NVIC_Handler_LED1
- .long NVIC_Handler_LED2
- .long NVIC_Handler_MBC_ERR
- .long NVIC_Handler_MBC_BUSY
- .long NVIC_Handler_TMR0
- .long NVIC_Handler_TMR1
- .long NVIC_Handler_TMR2
- .long NVIC_Handler_TMR3
- .long NVIC_Handler_TMR4
- .long NVIC_Handler_TMR5
- .long NVIC_Handler_SPI1_TX
- .long NVIC_Handler_SPI1_RX
- .long NVIC_Handler_GIRQ08
- .long NVIC_Handler_GIRQ09
- .long NVIC_Handler_GIRQ10
- .long NVIC_Handler_GIRQ11
- ;.long NVIC_Handler_GIRQ12
- .long interrupt_irq12
- ;.long NVIC_Handler_GIRQ13
- .long NVIC_Handler_GIRQ13
- .long NVIC_Handler_GIRQ14
- .long NVIC_Handler_GIRQ15
- .long NVIC_Handler_GIRQ16
- .long NVIC_Handler_GIRQ17
- .long NVIC_Handler_GIRQ18
- .long NVIC_Handler_GIRQ19
- .long NVIC_Handler_GIRQ20
- .long NVIC_Handler_GIRQ21
- .long NVIC_Handler_GIRQ22
- .long NVIC_Handler_GIRQ23
- .long NVIC_Handler_073
- .long NVIC_Handler_074
- .long NVIC_Handler_075
- .long NVIC_Handler_076
- .long NVIC_Handler_077
- .long NVIC_Handler_078
- .long NVIC_Handler_079
- .long NVIC_Handler_080
- .long NVIC_Handler_DMA8
- .long NVIC_Handler_DMA9
- .long NVIC_Handler_DMA10
- .long NVIC_Handler_DMA11
- .long NVIC_Handler_LED3
- .long NVIC_Handler_PKE_ERR
- .long NVIC_Handler_PKE_END
- .long NVIC_Handler_TRNG
- .long NVIC_Handler_AES
- .long NVIC_Handler_HASH
-
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl _start
- .extern main
- .globl Reset_Handler
- .type Reset_Handler, %function
-_start:
-Reset_Handler:
-/* Firstly it copies data from read only memory to RAM. There are two schemes
- * to copy. One can copy more than one sections. Another can only copy
- * one section. The former scheme needs more instructions and read-only
- * data to implement than the latter.
- * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
-
-/* Single section scheme.
- *
- * The ranges of copy from/to are specified by following symbols
- * __etext: LMA of start of the section to copy from. Usually end of text
- * __data_start__: VMA of start of the section to copy to
- * __data_end__: VMA of end of the section to copy to
- *
- * All addresses must be aligned to 4 bytes boundary.
- */
- ldr sp, =ulMainStack + ulMainStackSize
- sub sp, sp, #4
-
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.L_loop1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .L_loop1
-
-/* This part of work usually is done in C library startup code. Otherwise,
- * define this macro to enable it in this startup.
- *
- * There are two schemes too. One can clear multiple BSS sections. Another
- * can only clear one section. The former is more size expensive than the
- * latter.
- *
- * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-
- /* Single BSS section scheme.
- *
- * The BSS section is specified by following symbols
- * __bss_start__: start of the BSS section.
- * __bss_end__: end of the BSS section.
- *
- * Both addresses must be aligned to 4 bytes boundary.
- */
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
- movs r0, 0
-.L_loop3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .L_loop3
-
-#ifndef __NO_SYSTEM_INIT
-/* bl SystemInit */
-#endif
-
- bl main
-
- .pool
- .size Reset_Handler, . - Reset_Handler
-
- .align 1
- .thumb_func
- .weak Default_Handler
- .type Default_Handler, %function
-Default_Handler:
- b .
- .size Default_Handler, . - Default_Handler
-
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_irq_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
-
- def_irq_handler NMI_Handler
- def_irq_handler HardFault_Handler
- def_irq_handler MemManage_Handler
- def_irq_handler BusFault_Handler
- def_irq_handler UsageFault_Handler
-/* def_irq_handler SVC_Handler */
- def_irq_handler DebugMon_Handler
-/* def_irq_handler PendSV_Handler */
-/* def_irq_handler SysTick_Handler */
- def_irq_handler DEF_IRQHandler
-
- def_irq_handler NVIC_Handler_I2C0
- def_irq_handler NVIC_Handler_I2C1
- def_irq_handler NVIC_Handler_I2C2
- def_irq_handler NVIC_Handler_I2C3
- def_irq_handler NVIC_Handler_DMA0
- def_irq_handler NVIC_Handler_DMA1
- def_irq_handler NVIC_Handler_DMA2
- def_irq_handler NVIC_Handler_DMA3
- def_irq_handler NVIC_Handler_DMA4
- def_irq_handler NVIC_Handler_DMA5
- def_irq_handler NVIC_Handler_DMA6
- def_irq_handler NVIC_Handler_DMA7
- def_irq_handler NVIC_Handler_LPCBERR
- def_irq_handler NVIC_Handler_UART0
- def_irq_handler NVIC_Handler_IMAP0
- def_irq_handler NVIC_Handler_EC0_IBF
- def_irq_handler NVIC_Handler_EC0_OBF
- def_irq_handler NVIC_Handler_EC1_IBF
- def_irq_handler NVIC_Handler_EC1_OBF
- def_irq_handler NVIC_Handler_PM1_CTL
- def_irq_handler NVIC_Handler_PM1_EN
- def_irq_handler NVIC_Handler_PM1_STS
- def_irq_handler NVIC_Handler_MIF8042_OBF
- def_irq_handler NVIC_Handler_MIF8042_IBF
- def_irq_handler NVIC_Handler_MAILBOX
- def_irq_handler NVIC_Handler_PECI
- def_irq_handler NVIC_Handler_TACH0
- def_irq_handler NVIC_Handler_TACH1
- def_irq_handler NVIC_Handler_ADC_SNGL
- def_irq_handler NVIC_Handler_ADC_RPT
- def_irq_handler NVIC_Handler_V2P_INT0
- def_irq_handler NVIC_Handler_V2P_INT1
- def_irq_handler NVIC_Handler_PS2_CH0
- def_irq_handler NVIC_Handler_PS2_CH1
- def_irq_handler NVIC_Handler_PS2_CH2
- def_irq_handler NVIC_Handler_PS2_CH3
- def_irq_handler NVIC_Handler_SPI0_TX
- def_irq_handler NVIC_Handler_SPI0_RX
- def_irq_handler NVIC_Handler_HIB_TMR
- def_irq_handler NVIC_Handler_KEY_INT
- def_irq_handler NVIC_Handler_KEY_WAKE
- def_irq_handler NVIC_Handler_RPM_STALL
- def_irq_handler NVIC_Handler_RPM_SPIN
- def_irq_handler NVIC_Handler_VBAT
- def_irq_handler NVIC_Handler_LED0
- def_irq_handler NVIC_Handler_LED1
- def_irq_handler NVIC_Handler_LED2
- def_irq_handler NVIC_Handler_MBC_ERR
- def_irq_handler NVIC_Handler_MBC_BUSY
- def_irq_handler NVIC_Handler_TMR0
- def_irq_handler NVIC_Handler_TMR1
- def_irq_handler NVIC_Handler_TMR2
- def_irq_handler NVIC_Handler_TMR3
- def_irq_handler NVIC_Handler_TMR4
- def_irq_handler NVIC_Handler_TMR5
- def_irq_handler NVIC_Handler_SPI1_TX
- def_irq_handler NVIC_Handler_SPI1_RX
- def_irq_handler NVIC_Handler_GIRQ08
- def_irq_handler NVIC_Handler_GIRQ09
- def_irq_handler NVIC_Handler_GIRQ10
- def_irq_handler NVIC_Handler_GIRQ11
- ;def_irq_handler NVIC_Handler_GIRQ12
- def_irq_handler interrupt_irq12
- ;def_irq_handler NVIC_Handler_GIRQ13
- def_irq_handler interrupt_irq13
- def_irq_handler NVIC_Handler_GIRQ14
- def_irq_handler NVIC_Handler_GIRQ15
- def_irq_handler NVIC_Handler_GIRQ16
- def_irq_handler NVIC_Handler_GIRQ17
- def_irq_handler NVIC_Handler_GIRQ18
- def_irq_handler NVIC_Handler_GIRQ19
- def_irq_handler NVIC_Handler_GIRQ20
- def_irq_handler NVIC_Handler_GIRQ21
- def_irq_handler NVIC_Handler_GIRQ22
- def_irq_handler NVIC_Handler_GIRQ23
- def_irq_handler NVIC_Handler_073
- def_irq_handler NVIC_Handler_074
- def_irq_handler NVIC_Handler_075
- def_irq_handler NVIC_Handler_076
- def_irq_handler NVIC_Handler_077
- def_irq_handler NVIC_Handler_078
- def_irq_handler NVIC_Handler_079
- def_irq_handler NVIC_Handler_080
- def_irq_handler NVIC_Handler_DMA8
- def_irq_handler NVIC_Handler_DMA9
- def_irq_handler NVIC_Handler_DMA10
- def_irq_handler NVIC_Handler_DMA11
- def_irq_handler NVIC_Handler_LED3
- def_irq_handler NVIC_Handler_PKE_ERR
- def_irq_handler NVIC_Handler_PKE_END
- def_irq_handler NVIC_Handler_TRNG
- def_irq_handler NVIC_Handler_AES
- def_irq_handler NVIC_Handler_HASH
-
- .end
+++ /dev/null
-/****************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-*/\r
-\r
-/** @defgroup pwm pwm_c_wrapper\r
- * @{\r
- */\r
-/** @file pwm_c_wrapper.cpp\r
- \brief the pwm component C wrapper \r
- This program is designed to allow the other C programs to be able to use this component\r
-\r
- There are entry points for all C wrapper API implementation\r
-\r
-<b>Platform:</b> This is ARC-based component \r
-\r
-<b>Toolset:</b> Metaware IDE(8.5.1)\r
-<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
-\r
-/*******************************************************************************\r
- * SMSC version control information (Perforce):\r
- *\r
- * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/system/system.c $\r
- * REVISION: $Revision: #1 $\r
- * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
- * AUTHOR: $Author: akrishnan $\r
- *\r
- * Revision history (latest first):\r
- * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1) \r
- * #2 2011/03/25 martin_y support FPGA build 058 apps\r
- * #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200\r
- ***********************************************************************************\r
- */\r
-/* Imported Header File */\r
-//#include "common.h"\r
-//#include "build.h"\r
-#include <stdint.h>\r
-\r
-#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120\r
-#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))\r
-#define CPU_CLOCK_DIVIDER 1\r
-\r
-/* The start up code is configured to use the following array as the stack used\r
-by main(), which will then also get used by FreeRTOS interrupt handlers after \r
-the scheduler has been started. */\r
-#warning If the array size is modified here then ulMainStackSize must also be modified in startup_ARMCM4.S.\r
-volatile uint32_t ulMainStack[ 200 ];\r
-\r
-/******************************************************************************/\r
-/** system_set_ec_clock\r
-* Set CPU speed\r
-* @param void\r
-* @return void\r
-*******************************************************************************/\r
-\r
-void system_set_ec_clock(void)\r
-{\r
-\r
- /* Set ARC CPU Clock Divider to determine the CPU speed */\r
- /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */\r
- MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER;\r
-\r
-} /* End system_set_ec_clock() */\r
-\r
+++ /dev/null
-\r
-T220C 000:298 SEGGER J-Link V4.98e Log File (0000ms, 0270ms total)\r
-T220C 000:298 DLL Compiled: May 5 2015 11:00:52 (0000ms, 0270ms total)\r
-T220C 000:298 Logging started @ 2016-01-08 12:24 (0000ms, 0270ms total)\r
-T220C 000:298 JLINK_SetWarnOutHandler(...) (0000ms, 0270ms total)\r
-T220C 000:298 JLINK_OpenEx(...)
-Firmware: J-Link V9 compiled Oct 9 2015 20:34:47
-Hardware: V9.10
-S/N: 59101789
-Feature(s): GDB, JFlash returns O.K. (0266ms, 0536ms total)\r
-T220C 000:564 JLINK_SetErrorOutHandler(...) (0000ms, 0536ms total)\r
-T220C 000:564 JLINK_ExecCommand("ProjectFile = "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M4F_CEC1302_Clicker_2\Keil_Specific\JLinkSettings.ini"", ...)Device "UNSPECIFIED" selected. returns 0x00 (0002ms, 0538ms total)\r
-T220C 000:566 JLINK_ExecCommand("Device = ARMCM4_FP", ...)Device "UNSPECIFIED" selected. returns 0x00 (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetCompileDateTime() (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total)\r
-T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0001ms, 0539ms total)\r
-T220C 000:567 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0003ms, 0542ms total)\r
-T220C 000:570 JLINK_SetSpeed(5000) (0000ms, 0542ms total)\r
-T220C 000:570 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 4, IRPrint = 0x01 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x48 JTAG> >0x78 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG>Found Cortex-M4 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC)\r
- -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0)\r
- -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)\r
-ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM ScanLen=4 NumDevices=1 aId[0]=0x4BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0026ms, 0568ms total)\r
-T220C 000:596 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x4BA00477 (0000ms, 0568ms total)\r
-T220C 000:596 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0000ms, 0568ms total)\r
-T220C 000:596 JLINK_GetDLLVersion() returns 49805 (0000ms, 0568ms total)\r
-T220C 000:596 JLINK_CORE_GetFound() returns 0xE0000FF (0000ms, 0568ms total)\r
-T220C 000:596 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003 returns 0x00 (0000ms, 0568ms total)\r
-T220C 000:596 JLINK_ReadMem (0xE00FF000, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 03 10 F0 FF ... returns 0x00 (0001ms, 0569ms total)\r
-T220C 000:597 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0570ms total)\r
-T220C 000:598 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0571ms total)\r
-T220C 000:599 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0571ms total)\r
-T220C 000:599 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0572ms total)\r
-T220C 000:600 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0573ms total)\r
-T220C 000:601 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0573ms total)\r
-T220C 000:601 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0574ms total)\r
-T220C 000:602 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0574ms total)\r
-T220C 000:602 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0575ms total)\r
-T220C 000:603 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0576ms total)\r
-T220C 000:604 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0576ms total)\r
-T220C 000:604 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0577ms total)\r
-T220C 000:605 JLINK_ReadMemU32(0xE000EF40, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF40) - Data: 21 00 11 10 returns 0x01 (0001ms, 0578ms total)\r
-T220C 000:606 JLINK_ReadMemU32(0xE000EF44, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF44) - Data: 11 00 00 11 returns 0x01 (0000ms, 0578ms total)\r
-T220C 000:606 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 41 C2 0F 41 returns 0x01 (0001ms, 0579ms total)\r
-T220C 000:607 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0579ms total)\r
-T220C 000:607 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0)\r
- -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048)\r
- -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1225ms total)\r
-T220C 001:253 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1225ms total)\r
-T220C 001:253 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1225ms total)\r
-T220C 001:253 JLINK_Halt() returns 0x00 (0000ms, 1225ms total)\r
-T220C 001:253 JLINK_IsHalted() returns TRUE (0000ms, 1225ms total)\r
-T220C 001:253 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 1226ms total)\r
-T220C 001:254 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0000ms, 1226ms total)\r
-T220C 001:254 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 1227ms total)\r
-T220C 001:255 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_GetSpeed() returns 0x1388 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0000ms, 1227ms total)\r
-T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0001ms, 1228ms total)\r
-T220C 001:257 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 1229ms total)\r
-T220C 001:258 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 1230ms total)\r
-T220C 001:259 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1230ms total)\r
-T220C 001:259 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1230ms total)\r
-T220C 001:270 JLINK_WriteMem(0x00100000, 0x02AC Bytes, ...) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... -- CPU_WriteMem(684 bytes @ 0x00100000) returns 0x2AC (0003ms, 1233ms total)\r
-T220C 001:273 JLINK_ReadMem (0x00100000, 0x02AC Bytes, ...) -- CPU_ReadMem(684 bytes @ 0x00100000) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... returns 0x00 (0003ms, 1236ms total)\r
-T220C 001:330 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1236ms total)\r
-T220C 001:330 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1882ms total)\r
-T220C 001:977 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1882ms total)\r
-T220C 001:977 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1882ms total)\r
-T220C 001:977 JLINK_ReadMem (0x00118000, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x00118000) - Data: FE E7 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... returns 0x00 (0001ms, 1883ms total)\r
-T220C 002:517 JLINK_ReadMem (0x001001DA, 0x0002 Bytes, ...) -- CPU_ReadMem(2 bytes @ 0x001001DA) - Data: 00 47 returns 0x00 (0001ms, 1884ms total)\r
-T220C 002:518 JLINK_ReadMem (0x001001DC, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x001001DC) - Data: 4F F0 01 07 FE E7 4F F0 02 07 FE E7 4F F0 03 07 ... returns 0x00 (0001ms, 1885ms total)\r
-T220C 002:601 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1885ms total)\r
-T220C 002:601 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
- -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 2531ms total)\r
-T220C 003:248 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2531ms total)\r
-T220C 003:249 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2531ms total)\r
-T220C 003:249 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00 returns 0x01 (0000ms, 2531ms total)\r
-T1854 003:277 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0001ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2532ms total)\r
-T1854 003:278 JLINK_ReadReg(FPSCR) returns 0x00000000 (0005ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:283 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:284 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:292 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2537ms total)\r
-T1854 003:292 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total)\r
-T1854 003:292 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total)\r
-T1854 003:293 JLINK_ReadReg(FPS8) returns 0x00000000 (0001ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:294 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2538ms total)\r
-T1854 003:297 JLINK_ReadReg(R12) returns 0x00000000 (0001ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2539ms total)\r
-T1854 003:298 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2539ms total)\r
-T220C 003:312 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) - Data: 00 00 00 00 returns 0x01 (0000ms, 2539ms total)\r
-T220C 027:508 JLINK_Close() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001004) >0x78 JTAG> >0x08 JTAG> (0005ms, 2544ms total)\r
-T220C 027:508 (0005ms, 2544ms total)\r
-T220C 027:508 Closed (0005ms, 2544ms total)\r
+++ /dev/null
-[BREAKPOINTS]\r
-ForceImpTypeAny = 0\r
-ShowInfoWin = 1\r
-EnableFlashBP = 2\r
-BPDuringExecution = 0\r
-[CFI]\r
-CFISize = 0x00\r
-CFIAddr = 0x00\r
-[CPU]\r
-OverrideMemMap = 0\r
-AllowSimulation = 1\r
-ScriptFile=""\r
-[FLASH]\r
-CacheExcludeSize = 0x00\r
-CacheExcludeAddr = 0x00\r
-MinNumBytesFlashDL = 0\r
-SkipProgOnCRCMatch = 1\r
-VerifyDownload = 1\r
-AllowCaching = 1\r
-EnableFlashDL = 2\r
-Override = 1\r
-Device="Unspecified"\r
-[GENERAL]\r
-WorkRAMSize = 0x00\r
-WorkRAMAddr = 0x00\r
-RAMUsageLimit = 0x00\r
-[SWO]\r
-SWOLogFile=""\r
-[MEM]\r
-RdOverrideOrMask = 0x00\r
-RdOverrideAndMask = 0xFFFFFFFF\r
-RdOverrideAddr = 0xFFFFFFFF\r
-WrOverrideOrMask = 0x00\r
-WrOverrideAndMask = 0xFFFFFFFF\r
-WrOverrideAddr = 0xFFFFFFFF\r
+++ /dev/null
-; *************************************************************\r
-; *** Scatter-Loading Description File generated by uVision ***\r
-; *************************************************************\r
-\r
-\r
-LR_IROM1 0x00100000 0x00020000 { ; load region size_region\r
- ER_IROM1 0x00000000 0x00000000 { ; load address = execution address\r
- }\r
- RW_IRAM1 0x00100000 0x00020000 { ; RW data\r
- *.o (RESET, +First)\r
- *(InRoot$$Sections)\r
- .ANY (+RO)\r
- .ANY (+RW +ZI)\r
- }\r
-}\r
-\r
-\r
-;LR_IROM1 0x00100000 0x00018000 { ; load region size_region\r
-; ER_IROM1 0x00100000 0x00018000 { ; load address = execution address\r
-; *.o (RESET, +First)\r
-; *(InRoot$$Sections)\r
-; .ANY (+RO)\r
-; }\r
-; RW_IRAM1 0x00118000 0x00008000 { ; RW data\r
-; .ANY (+RW +ZI)\r
-; }\r
-;}\r
-\r
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
-
- <SchemaVersion>1.0</SchemaVersion>
-
- <Header>### uVision Project, (C) Keil Software</Header>
-
- <Extensions>
- <cExt>*.c</cExt>
- <aExt>*.s*; *.src; *.a*</aExt>
- <oExt>*.obj</oExt>
- <lExt>*.lib</lExt>
- <tExt>*.txt; *.h; *.inc</tExt>
- <pExt>*.plm</pExt>
- <CppX>*.cpp</CppX>
- <nMigrate>0</nMigrate>
- </Extensions>
-
- <DaveTm>
- <dwLowDateTime>0</dwLowDateTime>
- <dwHighDateTime>0</dwHighDateTime>
- </DaveTm>
-
- <Target>
- <TargetName>RTOSDemo</TargetName>
- <ToolsetNumber>0x4</ToolsetNumber>
- <ToolsetName>ARM-ADS</ToolsetName>
- <TargetOption>
- <CLKADS>48000000</CLKADS>
- <OPTTT>
- <gFlags>1</gFlags>
- <BeepAtEnd>1</BeepAtEnd>
- <RunSim>0</RunSim>
- <RunTarget>1</RunTarget>
- <RunAbUc>0</RunAbUc>
- </OPTTT>
- <OPTHX>
- <HexSelection>1</HexSelection>
- <FlashByte>65535</FlashByte>
- <HexRangeLowAddress>0</HexRangeLowAddress>
- <HexRangeHighAddress>0</HexRangeHighAddress>
- <HexOffset>0</HexOffset>
- </OPTHX>
- <OPTLEX>
- <PageWidth>79</PageWidth>
- <PageLength>66</PageLength>
- <TabStop>8</TabStop>
- <ListingPath>.\Listings\</ListingPath>
- </OPTLEX>
- <ListingPage>
- <CreateCListing>1</CreateCListing>
- <CreateAListing>1</CreateAListing>
- <CreateLListing>1</CreateLListing>
- <CreateIListing>0</CreateIListing>
- <AsmCond>1</AsmCond>
- <AsmSymb>1</AsmSymb>
- <AsmXref>0</AsmXref>
- <CCond>1</CCond>
- <CCode>0</CCode>
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- </OCR_RVCT10>
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- </Target>
- </Targets>
-
-</Project>
+++ /dev/null
-/*\r
- FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*\r
- * "Reg test" tasks - These fill the registers with known values, then check\r
- * that each register maintains its expected value for the lifetime of the\r
- * task. Each task uses a different set of values. The reg test tasks execute\r
- * with a very low priority, so get preempted very frequently. A register\r
- * containing an unexpected value is indicative of an error in the context\r
- * switching mechanism.\r
- */\r
- \r
- \r
-__asm void vRegTest1Implementation( void )\r
-{\r
- PRESERVE8\r
- IMPORT ulRegTest1LoopCounter\r
-\r
- /* Fill the core registers with known values. */\r
- mov r0, #100\r
- mov r1, #101\r
- mov r2, #102\r
- mov r3, #103\r
- mov r4, #104\r
- mov r5, #105\r
- mov r6, #106\r
- mov r7, #107\r
- mov r8, #108\r
- mov r9, #109\r
- mov r10, #110\r
- mov r11, #111\r
- mov r12, #112\r
-\r
- /* Fill the VFP registers with known values. */\r
- vmov d0, r0, r1\r
- vmov d1, r2, r3\r
- vmov d2, r4, r5\r
- vmov d3, r6, r7\r
- vmov d4, r8, r9\r
- vmov d5, r10, r11\r
- vmov d6, r0, r1\r
- vmov d7, r2, r3\r
- vmov d8, r4, r5\r
- vmov d9, r6, r7\r
- vmov d10, r8, r9\r
- vmov d11, r10, r11\r
- vmov d12, r0, r1\r
- vmov d13, r2, r3\r
- vmov d14, r4, r5\r
- vmov d15, r6, r7\r
-\r
-reg1_loop\r
- /* Check all the VFP registers still contain the values set above.\r
- First save registers that are clobbered by the test. */\r
- push { r0-r1 }\r
- \r
- vmov r0, r1, d0\r
- cmp r0, #100\r
- bne reg1_error_loopf\r
- cmp r1, #101\r
- bne reg1_error_loopf\r
- vmov r0, r1, d1\r
- cmp r0, #102\r
- bne reg1_error_loopf\r
- cmp r1, #103\r
- bne reg1_error_loopf\r
- vmov r0, r1, d2\r
- cmp r0, #104\r
- bne reg1_error_loopf\r
- cmp r1, #105\r
- bne reg1_error_loopf\r
- vmov r0, r1, d3\r
- cmp r0, #106\r
- bne reg1_error_loopf\r
- cmp r1, #107\r
- bne reg1_error_loopf\r
- vmov r0, r1, d4\r
- cmp r0, #108\r
- bne reg1_error_loopf\r
- cmp r1, #109\r
- bne reg1_error_loopf\r
- vmov r0, r1, d5\r
- cmp r0, #110\r
- bne reg1_error_loopf\r
- cmp r1, #111\r
- bne reg1_error_loopf\r
- vmov r0, r1, d6\r
- cmp r0, #100\r
- bne reg1_error_loopf\r
- cmp r1, #101\r
- bne reg1_error_loopf\r
- vmov r0, r1, d7\r
- cmp r0, #102\r
- bne reg1_error_loopf\r
- cmp r1, #103\r
- bne reg1_error_loopf\r
- vmov r0, r1, d8\r
- cmp r0, #104\r
- bne reg1_error_loopf\r
- cmp r1, #105\r
- bne reg1_error_loopf\r
- vmov r0, r1, d9\r
- cmp r0, #106\r
- bne reg1_error_loopf\r
- cmp r1, #107\r
- bne reg1_error_loopf\r
- vmov r0, r1, d10\r
- cmp r0, #108\r
- bne reg1_error_loopf\r
- cmp r1, #109\r
- bne reg1_error_loopf\r
- vmov r0, r1, d11\r
- cmp r0, #110\r
- bne reg1_error_loopf\r
- cmp r1, #111\r
- bne reg1_error_loopf\r
- vmov r0, r1, d12\r
- cmp r0, #100\r
- bne reg1_error_loopf\r
- cmp r1, #101\r
- bne reg1_error_loopf\r
- vmov r0, r1, d13\r
- cmp r0, #102\r
- bne reg1_error_loopf\r
- cmp r1, #103\r
- bne reg1_error_loopf\r
- vmov r0, r1, d14\r
- cmp r0, #104\r
- bne reg1_error_loopf\r
- cmp r1, #105\r
- bne reg1_error_loopf\r
- vmov r0, r1, d15\r
- cmp r0, #106\r
- bne reg1_error_loopf\r
- cmp r1, #107\r
- bne reg1_error_loopf\r
- \r
- /* Restore the registers that were clobbered by the test. */\r
- pop {r0-r1}\r
- \r
- /* VFP register test passed. Jump to the core register test. */\r
- b reg1_loopf_pass\r
-\r
-reg1_error_loopf\r
- /* If this line is hit then a VFP register value was found to be\r
- incorrect. */\r
- b reg1_error_loopf\r
-\r
-reg1_loopf_pass\r
-\r
- cmp r0, #100\r
- bne reg1_error_loop\r
- cmp r1, #101\r
- bne reg1_error_loop\r
- cmp r2, #102\r
- bne reg1_error_loop\r
- cmp r3, #103\r
- bne reg1_error_loop\r
- cmp r4, #104\r
- bne reg1_error_loop\r
- cmp r5, #105\r
- bne reg1_error_loop\r
- cmp r6, #106\r
- bne reg1_error_loop\r
- cmp r7, #107\r
- bne reg1_error_loop\r
- cmp r8, #108\r
- bne reg1_error_loop\r
- cmp r9, #109\r
- bne reg1_error_loop\r
- cmp r10, #110\r
- bne reg1_error_loop\r
- cmp r11, #111\r
- bne reg1_error_loop\r
- cmp r12, #112\r
- bne reg1_error_loop\r
- \r
- /* Everything passed, increment the loop counter. */\r
- push { r0-r1 }\r
- ldr r0, =ulRegTest1LoopCounter\r
- ldr r1, [r0]\r
- adds r1, r1, #1\r
- str r1, [r0]\r
- pop { r0-r1 }\r
- \r
- /* Start again. */\r
- b reg1_loop\r
-\r
-reg1_error_loop\r
- /* If this line is hit then there was an error in a core register value.\r
- The loop ensures the loop counter stops incrementing. */\r
- b reg1_error_loop\r
- nop\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-__asm void vRegTest2Implementation( void )\r
-{\r
- PRESERVE8\r
- IMPORT ulRegTest2LoopCounter\r
-\r
- /* Set all the core registers to known values. */\r
- mov r0, #-1\r
- mov r1, #1\r
- mov r2, #2\r
- mov r3, #3\r
- mov r4, #4\r
- mov r5, #5\r
- mov r6, #6\r
- mov r7, #7\r
- mov r8, #8\r
- mov r9, #9\r
- mov r10, #10\r
- mov r11, #11\r
- mov r12, #12\r
-\r
- /* Set all the VFP to known values. */\r
- vmov d0, r0, r1\r
- vmov d1, r2, r3\r
- vmov d2, r4, r5\r
- vmov d3, r6, r7\r
- vmov d4, r8, r9\r
- vmov d5, r10, r11\r
- vmov d6, r0, r1\r
- vmov d7, r2, r3\r
- vmov d8, r4, r5\r
- vmov d9, r6, r7\r
- vmov d10, r8, r9\r
- vmov d11, r10, r11\r
- vmov d12, r0, r1\r
- vmov d13, r2, r3\r
- vmov d14, r4, r5\r
- vmov d15, r6, r7\r
-\r
-reg2_loop\r
- \r
- /* Check all the VFP registers still contain the values set above.\r
- First save registers that are clobbered by the test. */\r
- push { r0-r1 }\r
- \r
- vmov r0, r1, d0\r
- cmp r0, #-1\r
- bne reg2_error_loopf\r
- cmp r1, #1\r
- bne reg2_error_loopf\r
- vmov r0, r1, d1\r
- cmp r0, #2\r
- bne reg2_error_loopf\r
- cmp r1, #3\r
- bne reg2_error_loopf\r
- vmov r0, r1, d2\r
- cmp r0, #4\r
- bne reg2_error_loopf\r
- cmp r1, #5\r
- bne reg2_error_loopf\r
- vmov r0, r1, d3\r
- cmp r0, #6\r
- bne reg2_error_loopf\r
- cmp r1, #7\r
- bne reg2_error_loopf\r
- vmov r0, r1, d4\r
- cmp r0, #8\r
- bne reg2_error_loopf\r
- cmp r1, #9\r
- bne reg2_error_loopf\r
- vmov r0, r1, d5\r
- cmp r0, #10\r
- bne reg2_error_loopf\r
- cmp r1, #11\r
- bne reg2_error_loopf\r
- vmov r0, r1, d6\r
- cmp r0, #-1\r
- bne reg2_error_loopf\r
- cmp r1, #1\r
- bne reg2_error_loopf\r
- vmov r0, r1, d7\r
- cmp r0, #2\r
- bne reg2_error_loopf\r
- cmp r1, #3\r
- bne reg2_error_loopf\r
- vmov r0, r1, d8\r
- cmp r0, #4\r
- bne reg2_error_loopf\r
- cmp r1, #5\r
- bne reg2_error_loopf\r
- vmov r0, r1, d9\r
- cmp r0, #6\r
- bne reg2_error_loopf\r
- cmp r1, #7\r
- bne reg2_error_loopf\r
- vmov r0, r1, d10\r
- cmp r0, #8\r
- bne reg2_error_loopf\r
- cmp r1, #9\r
- bne reg2_error_loopf\r
- vmov r0, r1, d11\r
- cmp r0, #10\r
- bne reg2_error_loopf\r
- cmp r1, #11\r
- bne reg2_error_loopf\r
- vmov r0, r1, d12\r
- cmp r0, #-1\r
- bne reg2_error_loopf\r
- cmp r1, #1\r
- bne reg2_error_loopf\r
- vmov r0, r1, d13\r
- cmp r0, #2\r
- bne reg2_error_loopf\r
- cmp r1, #3\r
- bne reg2_error_loopf\r
- vmov r0, r1, d14\r
- cmp r0, #4\r
- bne reg2_error_loopf\r
- cmp r1, #5\r
- bne reg2_error_loopf\r
- vmov r0, r1, d15\r
- cmp r0, #6\r
- bne reg2_error_loopf\r
- cmp r1, #7\r
- bne reg2_error_loopf\r
- \r
- /* Restore the registers that were clobbered by the test. */\r
- pop {r0-r1}\r
- \r
- /* VFP register test passed. Jump to the core register test. */\r
- b reg2_loopf_pass\r
-\r
-reg2_error_loopf\r
- /* If this line is hit then a VFP register value was found to be\r
- incorrect. */\r
- b reg2_error_loopf\r
-\r
-reg2_loopf_pass\r
-\r
- cmp r0, #-1\r
- bne reg2_error_loop\r
- cmp r1, #1\r
- bne reg2_error_loop\r
- cmp r2, #2\r
- bne reg2_error_loop\r
- cmp r3, #3\r
- bne reg2_error_loop\r
- cmp r4, #4\r
- bne reg2_error_loop\r
- cmp r5, #5\r
- bne reg2_error_loop\r
- cmp r6, #6\r
- bne reg2_error_loop\r
- cmp r7, #7\r
- bne reg2_error_loop\r
- cmp r8, #8\r
- bne reg2_error_loop\r
- cmp r9, #9\r
- bne reg2_error_loop\r
- cmp r10, #10\r
- bne reg2_error_loop\r
- cmp r11, #11\r
- bne reg2_error_loop\r
- cmp r12, #12\r
- bne reg2_error_loop\r
- \r
- /* Increment the loop counter to indicate this test is still functioning\r
- correctly. */\r
- push { r0-r1 }\r
- ldr r0, =ulRegTest2LoopCounter\r
- ldr r1, [r0]\r
- adds r1, r1, #1\r
- str r1, [r0]\r
- \r
- /* Yield to increase test coverage. */\r
- movs r0, #0x01\r
- ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */\r
- lsl r0, r0, #28 /* Shift to PendSV bit */\r
- str r0, [r1]\r
- dsb\r
- \r
- pop { r0-r1 }\r
- \r
- /* Start again. */\r
- b reg2_loop\r
-\r
-reg2_error_loop\r
- /* If this line is hit then there was an error in a core register value.\r
- This loop ensures the loop counter variable stops incrementing. */\r
- b reg2_error_loop\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
+++ /dev/null
-//Initialization file for the application code\r
-RESET\r
-T\r
-T\r
-T\r
-eval PC = *(&(__Vectors) + 1) ; // startup code loc to the Jump routine\r
-T\r
+++ /dev/null
-;/*\r
-;******************************************************************************\r
-;* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-;* You may use this software and any derivatives exclusively with\r
-;* Microchip products.\r
-;* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-;* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-;* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-;* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-;* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-;* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-;* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-;* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-;* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-;* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-;* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-;* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-;* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-;* OF THESE TERMS.\r
-;******************************************************************************\r
-; */\r
-;/** @file startup_MEC1322.s\r
-; *MEC1322 API Test: startup and vector table\r
-; */\r
-;/** @defgroup startup_MEC1322\r
-; * @{\r
-; */\r
-\r
- IMPORT __main\r
- IMPORT |Image$$RW_IRAM1$$Base|\r
- IMPORT |Image$$RW_IRAM1$$Limit|\r
- IMPORT |Image$$RW_IRAM1$$Length|\r
- IMPORT |Image$$RW_IRAM1$$ZI$$Base|\r
- IMPORT |Image$$RW_IRAM1$$ZI$$Limit|\r
- IMPORT |Image$$ER_IROM1$$Base|\r
- IMPORT |Image$$ER_IROM1$$Limit|\r
- IMPORT main\r
- IMPORT system_set_ec_clock\r
-\r
- EXPORT Reset_Handler\r
-\r
-; <h> Stack Configuration\r
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-; </h>\r
-\r
-Stack_Size EQU 0x00000800\r
-\r
- AREA STACK, NOINIT, READWRITE, ALIGN=3\r
- EXPORT __stack_bottom\r
-__stack_bottom\r
-Stack_Mem SPACE Stack_Size\r
-__initial_sp\r
-\r
-; <h> Heap Configuration\r
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-; </h>\r
-\r
-Heap_Size EQU 0x00000000 \r
-\r
- AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
-__heap_base\r
-Heap_Mem SPACE Heap_Size\r
-__heap_limit\r
-\r
- PRESERVE8\r
- THUMB\r
-\r
-; Vector Table Mapped to Address 0 at Reset\r
-\r
- AREA RESET, DATA, READONLY\r
- EXPORT __Vectors\r
- EXPORT __tx_vectors\r
-__tx_vectors\r
-__Vectors DCD __initial_sp ; Top of Stack\r
- DCD Reset_Handler ; Reset Handler\r
- DCD NMI_Handler ; NMI Handler\r
- DCD HardFault_Handler ; Hard Fault Handler\r
- DCD MemManage_Handler ; MPU Fault Handler\r
- DCD BusFault_Handler ; Bus Fault Handler\r
- DCD UsageFault_Handler ; Usage Fault Handler\r
- DCD 0 ; Reserved\r
- DCD 0 ; Reserved\r
- DCD 0 ; Reserved\r
- DCD 0 ; Reserved\r
- DCD SVC_Handler ; SVCall Handler\r
- DCD DebugMon_Handler ; Debug Monitor Handler\r
- DCD 0 ; Reserved\r
- DCD PendSV_Handler ; PendSV Handler\r
- DCD SysTick_Handler ; SysTick Handler\r
-\r
- ; MEC1322 External Interrupts\r
- DCD NVIC_Handler_I2C0 ; 40h: 0, I2C/SMBus 0\r
- DCD NVIC_Handler_I2C1 ; 44h: 1, I2C/SMBus 1\r
- DCD NVIC_Handler_I2C2 ; 48h: 2, I2C/SMBus 2\r
- DCD NVIC_Handler_I2C3 ; 4Ch: 3, I2C/SMBus 3\r
- DCD NVIC_Handler_DMA0 ; 50h: 4, DMA Channel 0\r
- DCD NVIC_Handler_DMA1 ; 54h: 5, DMA Channel 1\r
- DCD NVIC_Handler_DMA2 ; 58h: 6, DMA Channel 2\r
- DCD NVIC_Handler_DMA3 ; 5Ch: 7, DMA Channel 3\r
- DCD NVIC_Handler_DMA4 ; 60h: 8, DMA Channel 4\r
- DCD NVIC_Handler_DMA5 ; 64h: 9, DMA Channel 5\r
- DCD NVIC_Handler_DMA6 ; 68h: 10, DMA Channel 6\r
- DCD NVIC_Handler_DMA7 ; 6Ch: 11, DMA Channel 7\r
- DCD NVIC_Handler_LPCBERR ; 70h: 12, LPC Bus Error\r
- DCD NVIC_Handler_UART0 ; 74h: 13, UART0\r
- DCD NVIC_Handler_IMAP0 ; 78h: 14, IMAP0\r
- DCD NVIC_Handler_EC0_IBF ; 7Ch: 15, ACPI_EC0_IBF\r
- DCD NVIC_Handler_EC0_OBF ; 80h: 16, ACPI_EC0_OBF\r
- DCD NVIC_Handler_EC1_IBF ; 84h: 17, ACPI_EC1_IBF\r
- DCD NVIC_Handler_EC1_OBF ; 88h: 18, ACPI_EC1_OBF\r
- DCD NVIC_Handler_PM1_CTL ; 8Ch: 19, ACPI_PM1_CTL\r
- DCD NVIC_Handler_PM1_EN ; 90h: 20, ACPI_PM1_EN\r
- DCD NVIC_Handler_PM1_STS ; 94h: 21, ACPI_PM1_STS\r
- DCD NVIC_Handler_MIF8042_OBF ; 98h: 22, MIF8042_OBF\r
- DCD NVIC_Handler_MIF8042_IBF ; 9Ch: 23, MIF8042_IBF\r
- DCD NVIC_Handler_MAILBOX ; A0h: 24, Mailbox\r
- DCD NVIC_Handler_PECI ; A4h: 25, PECI\r
- DCD NVIC_Handler_TACH0 ; A8h: 26, TACH0\r
- DCD NVIC_Handler_TACH1 ; ACh: 27, TACH1\r
- DCD NVIC_Handler_ADC_SNGL ; B0h: 28, ADC_SNGL\r
- DCD NVIC_Handler_ADC_RPT ; B4h: 29, ADC_RPT\r
- DCD NVIC_Handler_V2P_INT0 ; B8h: 30, V2P_INT0\r
- DCD NVIC_Handler_V2P_INT1 ; BCh: 31, V2P_INT1\r
- DCD NVIC_Handler_PS2_CH0 ; C0h: 32, PS2_0\r
- DCD NVIC_Handler_PS2_CH1 ; C4h: 33, PS2_1\r
- DCD NVIC_Handler_PS2_CH2 ; C8h: 34, PS2_2\r
- DCD NVIC_Handler_PS2_CH3 ; CCh: 35, PS2_3\r
- DCD NVIC_Handler_SPI0_TX ; D0h: 36, SPI0_TX\r
- DCD NVIC_Handler_SPI0_RX ; D4h: 37, SPI0_RX\r
- DCD NVIC_Handler_HIB_TMR ; D8h: 38, HIB_TMR\r
- DCD NVIC_Handler_KEY_INT ; DCh: 39, KEY_INT\r
- DCD NVIC_Handler_KEY_WAKE ; E0h: 40, KEY_WAKE\r
- DCD NVIC_Handler_RPM_STALL ; E4h: 41, RPM_STALL\r
- DCD NVIC_Handler_RPM_SPIN ; E8h: 42, RPM_SPIN\r
- DCD NVIC_Handler_VBAT ; ECh: 43, VBAT\r
- DCD NVIC_Handler_LED0 ; F0h: 44, LED0\r
- DCD NVIC_Handler_LED1 ; F4h: 45, LED1\r
- DCD NVIC_Handler_LED2 ; F8h: 46, LED2\r
- DCD NVIC_Handler_MBC_ERR ; FCh: 47, MBC_ERR\r
- DCD NVIC_Handler_MBC_BUSY ; 100h: 48, MBC_BUSY\r
- DCD NVIC_Handler_TMR0 ; 104h: 49, TMR0\r
- DCD NVIC_Handler_TMR1 ; 108h: 50, TMR1\r
- DCD NVIC_Handler_TMR2 ; 10Ch: 51, TMR2\r
- DCD NVIC_Handler_TMR3 ; 110h: 52, TMR3\r
- DCD NVIC_Handler_TMR4 ; 114h: 53, TMR4\r
- DCD NVIC_Handler_TMR5 ; 118h: 54, TMR5\r
- DCD NVIC_Handler_SPI1_TX ; 11Ch: 55, SPI1_TX\r
- DCD NVIC_Handler_SPI1_RX ; 120h: 56, SPI1_RX\r
- DCD NVIC_Handler_GIRQ08 ; 124h: 57, GIRQ08\r
- DCD NVIC_Handler_GIRQ09 ; 128h: 58, GIRQ09\r
- DCD NVIC_Handler_GIRQ10 ; 12Ch: 59, GIRQ10\r
- DCD NVIC_Handler_GIRQ11 ; 130h: 60, GIRQ11\r
- DCD NVIC_Handler_GIRQ12 ; 134h: 61, GIRQ12\r
- DCD NVIC_Handler_GIRQ13 ; 138h: 62, GIRQ13\r
- DCD NVIC_Handler_GIRQ14 ; 13Ch: 63, GIRQ14\r
- DCD NVIC_Handler_GIRQ15 ; 140h: 64, GIRQ15\r
- DCD NVIC_Handler_GIRQ16 ; 144h: 65, GIRQ16\r
- DCD NVIC_Handler_GIRQ17 ; 148h: 66, GIRQ17\r
- DCD NVIC_Handler_GIRQ18 ; 14Ch: 67, GIRQ18\r
- DCD NVIC_Handler_GIRQ19 ; 150h: 68, GIRQ19\r
- DCD NVIC_Handler_GIRQ20 ; 154h: 69, GIRQ20\r
- DCD NVIC_Handler_GIRQ21 ; 158h: 70, GIRQ21\r
- DCD NVIC_Handler_GIRQ22 ; 15Ch: 71, GIRQ22\r
- DCD NVIC_Handler_GIRQ23 ; 160h: 72, GIRQ23\r
- DCD NVIC_Handler_073 ; 164h: 73, unknown\r
- DCD NVIC_Handler_074 ; 168h: 74, unknown\r
- DCD NVIC_Handler_075 ; 16Ch: 75, unknown\r
- DCD NVIC_Handler_076 ; 170h: 76, unknown\r
- DCD NVIC_Handler_077 ; 174h: 77, unknown\r
- DCD NVIC_Handler_078 ; 178h: 78, unknown\r
- DCD NVIC_Handler_079 ; 17Ch: 79, unknown\r
- DCD NVIC_Handler_080 ; 180h: 80, unknown\r
- DCD NVIC_Handler_DMA8 ; 184h: 81, DMA CH8\r
- DCD NVIC_Handler_DMA9 ; 188h: 82, DMA CH9\r
- DCD NVIC_Handler_DMA10 ; 18Ch: 83, DMA CH10\r
- DCD NVIC_Handler_DMA11 ; 190h: 84, DMA CH11\r
- DCD NVIC_Handler_LED3 ; 194h: 85, LED3\r
- DCD NVIC_Handler_PKE_ERR ; 198h: 86, PKE Error\r
- DCD NVIC_Handler_PKE_END ; 19Ch: 87, PKE End\r
- DCD NVIC_Handler_TRNG ; 1A0h: 88, TRandom Num Gen\r
- DCD NVIC_Handler_AES ; 1A4h: 89, AES \r
- DCD NVIC_Handler_HASH ; 1A8h: 90, HASH\r
- \r
-\r
- AREA ROMTABLE, CODE, READONLY\r
- THUMB\r
-; ---------- ROM API ----------\r
-; Jump table to ROM API C functions\r
-;\r
-;\r
-; ---------- ROM API End ------\r
-; Reset Handler\r
-\r
- AREA |.text|, CODE, READONLY\r
- THUMB\r
-\r
-Reset_Handler PROC\r
- EXPORT Reset_Handler [WEAK]\r
-\r
- CPSID i\r
- \r
- ; support code is loaded from ROM loader\r
- LDR SP, =__initial_sp\r
- ; configure CPU speed \r
- LDR R0, =system_set_ec_clock\r
- BLX R0\r
-\r
- LDR SP, =__initial_sp\r
-\r
- ; support FPU\r
- IF {CPU} = "Cortex-M4.fp"\r
- LDR R0, =0xE000ED88 ; Enable CP10,CP11\r
- LDR R1,[R0]\r
- ORR R1,R1,#(0xF << 20)\r
- STR R1,[R0]\r
- ENDIF\r
-\r
- ; Enter Keil startup code which calls our main\r
- LDR R0, =__main\r
- BX R0\r
- ENDP\r
-\r
-; Dummy Exception Handlers (infinite loops which can be modified)\r
-\r
-NMI_Handler PROC\r
- EXPORT NMI_Handler [WEAK]\r
- MOV R7,#1\r
- B .\r
- ENDP\r
-HardFault_Handler\\r
- PROC\r
- EXPORT HardFault_Handler [WEAK]\r
- MOV R7,#2\r
- B .\r
- ENDP\r
-MemManage_Handler\\r
- PROC\r
- EXPORT MemManage_Handler [WEAK]\r
- MOV R7,#3\r
- B .\r
- ENDP\r
-BusFault_Handler\\r
- PROC\r
- EXPORT BusFault_Handler [WEAK]\r
- MOV R7,#4\r
- B .\r
- ENDP\r
-UsageFault_Handler\\r
- PROC\r
- EXPORT UsageFault_Handler [WEAK]\r
- MOV R7,#5\r
- B .\r
- ENDP\r
-SVC_Handler PROC\r
- EXPORT SVC_Handler [WEAK]\r
- MOV R7,#6\r
- B .\r
- ENDP\r
-DebugMon_Handler\\r
- PROC\r
- EXPORT DebugMon_Handler [WEAK]\r
- MOV R7,#7\r
- B .\r
- ENDP\r
-PendSV_Handler PROC\r
- EXPORT PendSV_Handler [WEAK]\r
- MOV R7,#8\r
- B .\r
- ENDP\r
-SysTick_Handler PROC\r
- EXPORT SysTick_Handler [WEAK]\r
- MOV R7,#9\r
- B .\r
- ENDP\r
-\r
-Default_Handler PROC\r
-\r
- ; External MEC1322 NVIC Interrupt Inputs\r
- EXPORT NVIC_Handler_I2C0 [WEAK]\r
- EXPORT NVIC_Handler_I2C1 [WEAK]\r
- EXPORT NVIC_Handler_I2C2 [WEAK]\r
- EXPORT NVIC_Handler_I2C3 [WEAK]\r
- EXPORT NVIC_Handler_DMA0 [WEAK]\r
- EXPORT NVIC_Handler_DMA1 [WEAK]\r
- EXPORT NVIC_Handler_DMA2 [WEAK]\r
- EXPORT NVIC_Handler_DMA3 [WEAK]\r
- EXPORT NVIC_Handler_DMA4 [WEAK]\r
- EXPORT NVIC_Handler_DMA5 [WEAK]\r
- EXPORT NVIC_Handler_DMA6 [WEAK]\r
- EXPORT NVIC_Handler_DMA7 [WEAK]\r
- EXPORT NVIC_Handler_LPCBERR [WEAK]\r
- EXPORT NVIC_Handler_UART0 [WEAK]\r
- EXPORT NVIC_Handler_IMAP0 [WEAK]\r
- EXPORT NVIC_Handler_EC0_IBF [WEAK]\r
- EXPORT NVIC_Handler_EC0_OBF [WEAK]\r
- EXPORT NVIC_Handler_EC1_IBF [WEAK]\r
- EXPORT NVIC_Handler_EC1_OBF [WEAK]\r
- EXPORT NVIC_Handler_PM1_CTL [WEAK]\r
- EXPORT NVIC_Handler_PM1_EN [WEAK]\r
- EXPORT NVIC_Handler_PM1_STS [WEAK]\r
- EXPORT NVIC_Handler_MIF8042_OBF [WEAK]\r
- EXPORT NVIC_Handler_MIF8042_IBF [WEAK]\r
- EXPORT NVIC_Handler_MAILBOX [WEAK]\r
- EXPORT NVIC_Handler_PECI [WEAK]\r
- EXPORT NVIC_Handler_TACH0 [WEAK]\r
- EXPORT NVIC_Handler_TACH1 [WEAK]\r
- EXPORT NVIC_Handler_ADC_SNGL [WEAK]\r
- EXPORT NVIC_Handler_ADC_RPT [WEAK]\r
- EXPORT NVIC_Handler_V2P_INT0 [WEAK]\r
- EXPORT NVIC_Handler_V2P_INT1 [WEAK]\r
- EXPORT NVIC_Handler_PS2_CH0 [WEAK]\r
- EXPORT NVIC_Handler_PS2_CH1 [WEAK]\r
- EXPORT NVIC_Handler_PS2_CH2 [WEAK]\r
- EXPORT NVIC_Handler_PS2_CH3 [WEAK]\r
- EXPORT NVIC_Handler_SPI0_TX [WEAK]\r
- EXPORT NVIC_Handler_SPI0_RX [WEAK]\r
- EXPORT NVIC_Handler_HIB_TMR [WEAK]\r
- EXPORT NVIC_Handler_KEY_INT [WEAK]\r
- EXPORT NVIC_Handler_KEY_WAKE [WEAK]\r
- EXPORT NVIC_Handler_RPM_STALL [WEAK]\r
- EXPORT NVIC_Handler_RPM_SPIN [WEAK]\r
- EXPORT NVIC_Handler_VBAT [WEAK]\r
- EXPORT NVIC_Handler_LED0 [WEAK]\r
- EXPORT NVIC_Handler_LED1 [WEAK]\r
- EXPORT NVIC_Handler_LED2 [WEAK]\r
- EXPORT NVIC_Handler_MBC_ERR [WEAK]\r
- EXPORT NVIC_Handler_MBC_BUSY [WEAK]\r
- EXPORT NVIC_Handler_TMR0 [WEAK]\r
- EXPORT NVIC_Handler_TMR1 [WEAK]\r
- EXPORT NVIC_Handler_TMR2 [WEAK]\r
- EXPORT NVIC_Handler_TMR3 [WEAK]\r
- EXPORT NVIC_Handler_TMR4 [WEAK]\r
- EXPORT NVIC_Handler_TMR5 [WEAK]\r
- EXPORT NVIC_Handler_SPI1_TX [WEAK]\r
- EXPORT NVIC_Handler_SPI1_RX [WEAK]\r
- EXPORT NVIC_Handler_GIRQ08 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ09 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ10 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ11 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ12 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ13 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ14 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ15 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ16 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ17 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ18 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ19 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ20 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ21 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ22 [WEAK]\r
- EXPORT NVIC_Handler_GIRQ23 [WEAK]\r
- EXPORT NVIC_Handler_073 [WEAK]\r
- EXPORT NVIC_Handler_074 [WEAK]\r
- EXPORT NVIC_Handler_075 [WEAK]\r
- EXPORT NVIC_Handler_076 [WEAK]\r
- EXPORT NVIC_Handler_077 [WEAK]\r
- EXPORT NVIC_Handler_078 [WEAK]\r
- EXPORT NVIC_Handler_079 [WEAK]\r
- EXPORT NVIC_Handler_080 [WEAK]\r
- EXPORT NVIC_Handler_DMA8 [WEAK]\r
- EXPORT NVIC_Handler_DMA9 [WEAK]\r
- EXPORT NVIC_Handler_DMA10 [WEAK]\r
- EXPORT NVIC_Handler_DMA11 [WEAK]\r
- EXPORT NVIC_Handler_LED3 [WEAK]\r
- EXPORT NVIC_Handler_PKE_ERR [WEAK]\r
- EXPORT NVIC_Handler_PKE_END [WEAK]\r
- EXPORT NVIC_Handler_TRNG [WEAK]\r
- EXPORT NVIC_Handler_AES [WEAK]\r
- EXPORT NVIC_Handler_HASH [WEAK]\r
-\r
-NVIC_Handler_I2C0\r
-NVIC_Handler_I2C1\r
-NVIC_Handler_I2C2\r
-NVIC_Handler_I2C3\r
-NVIC_Handler_DMA0\r
-NVIC_Handler_DMA1\r
-NVIC_Handler_DMA2\r
-NVIC_Handler_DMA3\r
-NVIC_Handler_DMA4\r
-NVIC_Handler_DMA5\r
-NVIC_Handler_DMA6\r
-NVIC_Handler_DMA7\r
-NVIC_Handler_LPCBERR\r
-NVIC_Handler_UART0\r
-NVIC_Handler_IMAP0\r
-NVIC_Handler_EC0_IBF\r
-NVIC_Handler_EC0_OBF\r
-NVIC_Handler_EC1_IBF\r
-NVIC_Handler_EC1_OBF\r
-NVIC_Handler_PM1_CTL\r
-NVIC_Handler_PM1_EN\r
-NVIC_Handler_PM1_STS\r
-NVIC_Handler_MIF8042_OBF\r
-NVIC_Handler_MIF8042_IBF\r
-NVIC_Handler_MAILBOX\r
-NVIC_Handler_PECI\r
-NVIC_Handler_TACH0\r
-NVIC_Handler_TACH1\r
-NVIC_Handler_ADC_SNGL\r
-NVIC_Handler_ADC_RPT\r
-NVIC_Handler_V2P_INT0\r
-NVIC_Handler_V2P_INT1\r
-NVIC_Handler_PS2_CH0\r
-NVIC_Handler_PS2_CH1\r
-NVIC_Handler_PS2_CH2\r
-NVIC_Handler_PS2_CH3\r
-NVIC_Handler_SPI0_TX\r
-NVIC_Handler_SPI0_RX\r
-NVIC_Handler_HIB_TMR\r
-NVIC_Handler_KEY_INT\r
-NVIC_Handler_KEY_WAKE\r
-NVIC_Handler_RPM_STALL\r
-NVIC_Handler_RPM_SPIN\r
-NVIC_Handler_VBAT\r
-NVIC_Handler_LED0\r
-NVIC_Handler_LED1\r
-NVIC_Handler_LED2\r
-NVIC_Handler_MBC_ERR\r
-NVIC_Handler_MBC_BUSY\r
-NVIC_Handler_TMR0\r
-NVIC_Handler_TMR1\r
-NVIC_Handler_TMR2\r
-NVIC_Handler_TMR3\r
-NVIC_Handler_TMR4\r
-NVIC_Handler_TMR5\r
-NVIC_Handler_SPI1_TX\r
-NVIC_Handler_SPI1_RX\r
-NVIC_Handler_GIRQ08\r
-NVIC_Handler_GIRQ09\r
-NVIC_Handler_GIRQ10\r
-NVIC_Handler_GIRQ11\r
-NVIC_Handler_GIRQ12\r
-NVIC_Handler_GIRQ13\r
-NVIC_Handler_GIRQ14\r
-NVIC_Handler_GIRQ15\r
-NVIC_Handler_GIRQ16\r
-NVIC_Handler_GIRQ17\r
-NVIC_Handler_GIRQ18\r
-NVIC_Handler_GIRQ19\r
-NVIC_Handler_GIRQ20\r
-NVIC_Handler_GIRQ21\r
-NVIC_Handler_GIRQ22\r
-NVIC_Handler_GIRQ23\r
-NVIC_Handler_073\r
-NVIC_Handler_074\r
-NVIC_Handler_075\r
-NVIC_Handler_076\r
-NVIC_Handler_077\r
-NVIC_Handler_078\r
-NVIC_Handler_079\r
-NVIC_Handler_080\r
-NVIC_Handler_DMA8\r
-NVIC_Handler_DMA9\r
-NVIC_Handler_DMA10\r
-NVIC_Handler_DMA11\r
-NVIC_Handler_LED3\r
-NVIC_Handler_PKE_ERR\r
-NVIC_Handler_PKE_END\r
-NVIC_Handler_TRNG\r
-NVIC_Handler_AES\r
-NVIC_Handler_HASH\r
- B .\r
-\r
- ENDP\r
-\r
- ALIGN\r
-\r
-; User Initial Stack & Heap\r
-\r
- IF :DEF:__MICROLIB\r
- \r
- EXPORT __initial_sp\r
- EXPORT __heap_base\r
- EXPORT __heap_limit\r
- EXPORT __stack_bottom\r
-\r
- ELSE\r
- \r
- IMPORT __use_two_region_memory\r
- EXPORT __user_initial_stackheap\r
-__user_initial_stackheap\r
-\r
- LDR R0, = Heap_Mem\r
- LDR R1, =(Stack_Mem + Stack_Size)\r
- LDR R2, = (Heap_Mem + Heap_Size)\r
- LDR R3, = Stack_Mem\r
- BX LR\r
-\r
- ALIGN\r
-\r
- ENDIF\r
-\r
- END\r
-\r
-;/** @}\r
-; */\r
+++ /dev/null
-/****************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-*/\r
-\r
-/** @defgroup pwm pwm_c_wrapper\r
- * @{\r
- */\r
-/** @file pwm_c_wrapper.cpp\r
- \brief the pwm component C wrapper \r
- This program is designed to allow the other C programs to be able to use this component\r
-\r
- There are entry points for all C wrapper API implementation\r
-\r
-<b>Platform:</b> This is ARC-based component \r
-\r
-<b>Toolset:</b> Metaware IDE(8.5.1)\r
-<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
-\r
-/*******************************************************************************\r
- * SMSC version control information (Perforce):\r
- *\r
- * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/system/system.c $\r
- * REVISION: $Revision: #1 $\r
- * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
- * AUTHOR: $Author: akrishnan $\r
- *\r
- * Revision history (latest first):\r
- * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1) \r
- * #2 2011/03/25 martin_y support FPGA build 058 apps\r
- * #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200\r
- ***********************************************************************************\r
- */\r
-/* Imported Header File */\r
-//#include "common.h"\r
-//#include "build.h"\r
-#include <stdint.h>\r
-\r
-#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120\r
-#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))\r
-#define CPU_CLOCK_DIVIDER 1\r
-\r
-/******************************************************************************/\r
-/** system_set_ec_clock\r
-* Set CPU speed\r
-* @param void\r
-* @return void\r
-*******************************************************************************/\r
-\r
-void system_set_ec_clock(void)\r
-{\r
-\r
- /* Set ARC CPU Clock Divider to determine the CPU speed */\r
- /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */\r
- MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER;\r
-\r
-} /* End system_set_ec_clock() */\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * This project provides two demo applications. A simple blinky style project\r
- * that demonstrates low power tickless functionality, and a more comprehensive\r
- * test and demo application. The configCREATE_LOW_POWER_DEMO setting, which is\r
- * defined in FreeRTOSConfig.h, is used to select between the two. The simply\r
- * blinky low power demo is implemented and described in main_low_power.c. The\r
- * more comprehensive test and demo application is implemented and described in\r
- * main_full.c.\r
- *\r
- * This file implements the code that is not demo specific, including the\r
- * hardware setup and standard FreeRTOS hook functions.\r
- *\r
- * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON\r
- * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO\r
- * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!\r
- *\r
- */\r
-\r
-/* Scheduler include files. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Hardware register addresses. */\r
-#define mainVTOR ( * ( uint32_t * ) 0xE000ED08 )\r
-#define mainNVIC_AUX_ACTLR ( * ( uint32_t * ) 0xE000E008 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Configure the hardware as necessary to run this demo.\r
- */\r
-static void prvSetupHardware( void );\r
-\r
-/*\r
- * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1.\r
- * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0.\r
- */\r
-#if( configCREATE_LOW_POWER_DEMO == 1 )\r
-\r
- extern void main_low_power( void );\r
-\r
-#else\r
-\r
- extern void main_full( void );\r
-\r
- /* Some of the tests and examples executed as part of the full demo make use\r
- of the tick hook to call API functions from an interrupt context. */\r
- extern void vFullDemoTickHook( void );\r
-\r
-#endif /* #if configCREATE_LOW_POWER_DEMO == 1 */\r
-\r
-/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
-within this file. */\r
-void vApplicationMallocFailedHook( void );\r
-void vApplicationIdleHook( void );\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
-void vApplicationTickHook( void );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The variable that is incremented to represent each LED toggle. On the\r
-clicker hardware the LED state is set to the value of the least significant bit\r
-of this variable. On other hardware, where an LED is not used, the LED just\r
-keeps a count of the number of times the LED would otherwise have been toggled.\r
-See the comments in main_low_power.c and main_full.c for information on the\r
-expected LED toggle rate). */\r
-volatile uint32_t ulLED = 0;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-int main( void )\r
-{\r
- /* Configure the hardware ready to run the demo. */\r
- prvSetupHardware();\r
-\r
- /* The configCREATE_LOW_POWER_DEMO setting is described at the top\r
- of this file. */\r
- #if( configCREATE_LOW_POWER_DEMO == 1 )\r
- {\r
- main_low_power();\r
- }\r
- #else\r
- {\r
- main_full();\r
- }\r
- #endif\r
-\r
- /* Should not get here. */\r
- return 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvSetupHardware( void )\r
-{\r
-extern void system_set_ec_clock( void );\r
-extern unsigned long __Vectors[];\r
- \r
- /* Disable M4 write buffer: fix MEC1322 hardware bug. */\r
- mainNVIC_AUX_ACTLR |= 0x07;\r
-\r
- system_set_ec_clock();\r
- \r
- /* Assuming downloading code via the debugger - so ensure the hardware\r
- is using the vector table downloaded with the application. */\r
- mainVTOR = ( uint32_t ) __Vectors;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationMallocFailedHook( void )\r
-{\r
- /* Called if a call to pvPortMalloc() fails because there is insufficient\r
- free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
- internally by FreeRTOS API functions that create tasks, queues, software\r
- timers, and semaphores. The size of the FreeRTOS heap is set by the\r
- configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
-\r
- /* Force an assert. */\r
- configASSERT( ( volatile void * ) NULL );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
-{\r
- ( void ) pcTaskName;\r
- ( void ) pxTask;\r
-\r
- /* Run time stack overflow checking is performed if\r
- configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
- function is called if a stack overflow is detected. */\r
-\r
- /* Force an assert. */\r
- configASSERT( ( volatile void * ) NULL );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationIdleHook( void )\r
-{\r
-volatile size_t xFreeHeapSpace;\r
-\r
- /* This is just a trivial example of an idle hook. It is called on each\r
- cycle of the idle task. It must *NOT* attempt to block. In this case the\r
- idle task just queries the amount of FreeRTOS heap that remains. See the\r
- memory management section on the http://www.FreeRTOS.org web site for memory\r
- management options. If there is a lot of heap memory free then the\r
- configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
- RAM. */\r
- xFreeHeapSpace = xPortGetFreeHeapSize();\r
-\r
- /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
- ( void ) xFreeHeapSpace;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationTickHook( void )\r
-{\r
- /* The full demo includes tests that run from the tick hook. */\r
- #if( configCREATE_LOW_POWER_DEMO == 0 )\r
- {\r
- /* Some of the tests and demo tasks executed by the full demo include\r
- interaction from an interrupt - for which the tick interrupt is used\r
- via the tick hook function. */\r
- vFullDemoTickHook();\r
- }\r
- #endif\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
-implementation of vApplicationGetIdleTaskMemory() to provide the memory that is\r
-used by the Idle task. */\r
-void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )\r
-{\r
-/* If the buffers to be provided to the Idle task are declared inside this\r
-function then they must be declared static - otherwise they will be allocated on\r
-the stack and so not exists after this function exits. */\r
-static StaticTask_t xIdleTaskTCB;\r
-static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];\r
-\r
- /* Pass out a pointer to the StaticTask_t structure in which the Idle task's\r
- state will be stored. */\r
- *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
-\r
- /* Pass out the array that will be used as the Idle task's stack. */\r
- *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
-\r
- /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
- Note that, as the array is necessarily of type StackType_t,\r
- configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
- *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the\r
-application must provide an implementation of vApplicationGetTimerTaskMemory()\r
-to provide the memory that is used by the Timer service task. */\r
-void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )\r
-{\r
-/* If the buffers to be provided to the Timer task are declared inside this\r
-function then they must be declared static - otherwise they will be allocated on\r
-the stack and so not exists after this function exits. */\r
-static StaticTask_t xTimerTaskTCB;\r
-static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];\r
-\r
- /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
- task's state will be stored. */\r
- *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
-\r
- /* Pass out the array that will be used as the Timer task's stack. */\r
- *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
-\r
- /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
- Note that, as the array is necessarily of type StackType_t,\r
- configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
- *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
-}\r
-\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*\r
- * This file initialises three timers as follows:\r
- *\r
- * Basic timer channels 0 and 1 provide the interrupts that are used with the\r
- * IntQ standard demo tasks, which test interrupt nesting and using queues from\r
- * interrupts. The interrupts use slightly different frequencies so will\r
- * occasionally nest.\r
- *\r
- * Basic timer channel 2 provides a much higher frequency timer that tests the\r
- * nesting of interrupts that don't use the FreeRTOS API.\r
- *\r
- * All the timers can nest with the tick interrupt - creating a maximum\r
- * interrupt nesting depth of 4 (which is shown as a max nest count of 3 as the\r
- * tick interrupt does not increment the nesting count variable).\r
- *\r
- */\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Demo includes. */\r
-#include "IntQueueTimer.h"\r
-#include "IntQueue.h"\r
-\r
-/* Library includes. */\r
-#include "common_lib.h"\r
-#include "peripheral_library/interrupt/interrupt.h"\r
-#include "peripheral_library/basic_timer/btimer.h"\r
-\r
-/* The frequencies at which the first two timers expire are slightly offset to\r
-ensure they don't remain synchronised. The frequency of the highest priority\r
-interrupt is 20 times faster so really hammers the interrupt entry and exit\r
-code. */\r
-#define tmrTIMER_0_FREQUENCY ( 2000UL )\r
-#define tmrTIMER_1_FREQUENCY ( 2003UL )\r
-#define tmrTIMER_2_FREQUENCY ( 20000UL )\r
-\r
-/* The basic timer channels used for generating the three interrupts. */\r
-#define tmrTIMER_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */\r
-#define tmrTIMER_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */\r
-#define tmrTIMER_CHANNEL_2 2 /* At tmrTIMER_2_FREQUENCY */\r
-\r
-/* The high frequency interrupt is given a priority above the maximum at which\r
-interrupt safe FreeRTOS calls can be made. The priority of the lower frequency\r
-timers must still be above the tick interrupt priority. */\r
-#define tmrLOWER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1 )\r
-#define tmrMEDIUM_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 )\r
-#define tmrHIGHER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )\r
-\r
-/* Hardware register locations. */\r
-#define tmrGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 )\r
-#define tmrMMCR_EC_INTERRUPT_CONTROL ( * ( volatile uint8_t * ) 0x4000FC18 )\r
-\r
-#define tmrRECORD_NESTING_DEPTH() \\r
- ulNestingDepth++; \\r
- if( ulNestingDepth > ulMaxRecordedNestingDepth ) \\r
- { \\r
- ulMaxRecordedNestingDepth = ulNestingDepth; \\r
- }\r
-\r
-/* Used to count the nesting depth, and record the maximum nesting depth. */\r
-volatile uint32_t ulNestingDepth = 0, ulMaxRecordedNestingDepth = 0;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void vInitialiseTimerForIntQueueTest( void )\r
-{\r
-const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY;\r
-const uint32_t ulTimer1Count = configCPU_CLOCK_HZ / tmrTIMER_1_FREQUENCY;\r
-const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;\r
-\r
- tmrGIRQ23_ENABLE_SET = 0x03;\r
- tmrMMCR_EC_INTERRUPT_CONTROL = 1; \r
- \r
- /* Initialise the three timers as described at the top of this file, and \r
- enable their interrupts in the NVIC. */\r
- btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );\r
- btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 ); \r
- enable_timer0_irq();\r
- NVIC_SetPriority( TIMER0_IRQn, tmrLOWER_PRIORITY ); //0xc0 into 0xe000e431\r
- NVIC_ClearPendingIRQ( TIMER0_IRQn );\r
- NVIC_EnableIRQ( TIMER0_IRQn );\r
- btimer_start( tmrTIMER_CHANNEL_0 );\r
-\r
- btimer_init( tmrTIMER_CHANNEL_1, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer1Count, ulTimer1Count );\r
- btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_1 );\r
- enable_timer1_irq();\r
- NVIC_SetPriority( TIMER1_IRQn, tmrMEDIUM_PRIORITY ); //0xa0 into 0xe000e432\r
- NVIC_ClearPendingIRQ( TIMER1_IRQn );\r
- NVIC_EnableIRQ( TIMER1_IRQn );\r
- btimer_start( tmrTIMER_CHANNEL_1 );\r
-\r
- btimer_init( tmrTIMER_CHANNEL_2, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer2Count, ulTimer2Count );\r
- btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_2 );\r
- enable_timer2_irq();\r
- NVIC_SetPriority( TIMER2_IRQn, tmrHIGHER_PRIORITY );\r
- NVIC_ClearPendingIRQ( TIMER2_IRQn );\r
- NVIC_EnableIRQ( TIMER2_IRQn );\r
- btimer_start( tmrTIMER_CHANNEL_2 );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The TMR0 interrupt is used for different purposes by the low power and full\r
-demos respectively. */\r
-#if( configCREATE_LOW_POWER_DEMO == 0 )\r
-\r
- void NVIC_Handler_TMR0( void )\r
- {\r
- tmrRECORD_NESTING_DEPTH();\r
-\r
- /* Call the IntQ test function for this channel. */\r
- portYIELD_FROM_ISR( xFirstTimerHandler() );\r
-\r
- ulNestingDepth--;\r
- }\r
-\r
-#endif /* configCREATE_LOW_POWER_DEMO */\r
-/*-----------------------------------------------------------*/\r
-\r
-void NVIC_Handler_TMR1( void )\r
-{\r
- tmrRECORD_NESTING_DEPTH();\r
-\r
- /* Just testing the xPortIsInsideInterrupt() functionality. */\r
- configASSERT( xPortIsInsideInterrupt() == pdTRUE );\r
-\r
- /* Call the IntQ test function for this channel. */\r
- portYIELD_FROM_ISR( xSecondTimerHandler() );\r
-\r
- ulNestingDepth--;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void NVIC_Handler_TMR2( void )\r
-{\r
- tmrRECORD_NESTING_DEPTH();\r
- ulNestingDepth--;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-#ifndef INT_QUEUE_TIMER_H\r
-#define INT_QUEUE_TIMER_H\r
-\r
-void vInitialiseTimerForIntQueueTest( void );\r
-BaseType_t xTimer0Handler( void );\r
-BaseType_t xTimer1Handler( void );\r
-\r
-#endif\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * NOTE 1: This project provides two demo applications. A simple blinky style\r
- * project that demonstrates the tickless low power features of FreeRTOS, and a\r
- * more comprehensive test and demo application. The configCREATE_LOW_POWER_DEMO\r
- * setting in FreeRTOSConifg.h is used to select between the two. See the notes\r
- * on using conifgCREATE_LOW_POWER_DEMO in main.c. This file implements the\r
- * comprehensive test and demo version.\r
- *\r
- * NOTE 2: This file only contains the source code that is specific to the\r
- * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
- * required to configure the hardware, are defined in main.c.\r
- *\r
- ******************************************************************************\r
- *\r
- * main_full() creates all the demo application tasks and software timers, then\r
- * starts the scheduler. The web documentation provides more details of the\r
- * standard demo application tasks, which provide no particular functionality,\r
- * but do provide a good example of how to use the FreeRTOS API.\r
- *\r
- * In addition to the standard demo tasks, the following tasks and tests are\r
- * defined and/or created within this file:\r
- *\r
- * "Reg test" tasks - These fill both the core and floating point registers with\r
- * known values, then check that each register maintains its expected value for\r
- * the lifetime of the task. Each task uses a different set of values. The reg\r
- * test tasks execute with a very low priority, so get preempted very\r
- * frequently. A register containing an unexpected value is indicative of an\r
- * error in the context switching mechanism.\r
- *\r
- * "Check" task - The check task period is initially set to three seconds. The\r
- * task checks that all the standard demo tasks, and the register check tasks,\r
- * are not only still executing, but are executing without reporting any errors.\r
- * If the check task discovers that a task has either stalled, or reported an\r
- * error, then it changes its own execution period from the initial three\r
- * seconds, to just 200ms. The check task also toggles an LED each time it is\r
- * called. This provides a visual indication of the system status: If the LED\r
- * toggles every three seconds, then no issues have been discovered. If the LED\r
- * toggles every 200ms, then an issue has been discovered with at least one\r
- * task.\r
- */\r
-\r
-/* Standard includes. */\r
-#include <stdio.h>\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "timers.h"\r
-#include "semphr.h"\r
-\r
-/* Standard demo application includes. */\r
-#include "flop.h"\r
-#include "semtest.h"\r
-#include "dynamic.h"\r
-#include "blocktim.h"\r
-#include "countsem.h"\r
-#include "GenQTest.h"\r
-#include "death.h"\r
-#include "TimerDemo.h"\r
-#include "IntQueue.h"\r
-#include "EventGroupsDemo.h"\r
-#include "TaskNotify.h"\r
-\r
-/* Priorities for the demo application tasks. */\r
-#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
-#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
-#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
-#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
-#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
-\r
-/* A block time of zero simply means "don't block". */\r
-#define mainDONT_BLOCK ( 0UL )\r
-\r
-/* The period of the check task, in ms, provided no errors have been reported by\r
-any of the standard demo tasks. ms are converted to the equivalent in ticks\r
-using the pdMS_TO_TICKS() macro constant. */\r
-#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL )\r
-\r
-/* The period of the check task, in ms, if an error has been reported in one of\r
-the standard demo tasks. ms are converted to the equivalent in ticks using the\r
-pdMS_TO_TICKS() macro. */\r
-#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL )\r
-\r
-/* Parameters that are passed into the register check tasks solely for the\r
-purpose of ensuring parameters are passed into tasks correctly. */\r
-#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )\r
-#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )\r
-\r
-/* The base period used by the timer test tasks. */\r
-#define mainTIMER_TEST_PERIOD ( 50 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Called by main() to run the full demo (as opposed to the blinky demo) when\r
- * configCREATE_LOW_POWER_DEMO is set to 0.\r
- */\r
-void main_full( void );\r
-\r
-/*\r
- * The check task, as described at the top of this file.\r
- */\r
-static void prvCheckTask( void *pvParameters );\r
-\r
-/*\r
- * Some of the tests and demo tasks executed by the full demo include\r
- * interaction from an interrupt - for which the tick interrupt is used via the\r
- * tick hook function.\r
- */\r
-void vFullDemoTickHook( void );\r
-\r
-/*\r
- * Register check tasks, and the tasks used to write over and check the contents\r
- * of the FPU registers, as described at the top of this file. The nature of\r
- * these files necessitates that they are written in an assembly file, but the\r
- * entry points are kept in the C file for the convenience of checking the task\r
- * parameter.\r
- */\r
-static void prvRegTestTaskEntry1( void *pvParameters );\r
-extern void vRegTest1Implementation( void );\r
-static void prvRegTestTaskEntry2( void *pvParameters );\r
-extern void vRegTest2Implementation( void );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The following two variables are used to communicate the status of the\r
-register check tasks to the check task. If the variables keep incrementing,\r
-then the register check tasks have not discovered any errors. If a variable\r
-stops incrementing, then an error has been found. */\r
-volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
-\r
-/* The variable that is incremented to represent each LED toggle. On the\r
-clicker hardware the LED state is set to the value of the least significant bit\r
-of this variable. On other hardware, where an LED is not used, the LED just\r
-keeps a count of the number of times the LED would otherwise have been toggled.\r
-See the comments at the top of this file for information on the expected LED\r
-toggle rate. */\r
-extern volatile uint32_t ulLED;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void main_full( void )\r
-{\r
- /* Start all the other standard demo/test tasks. They have no particular\r
- functionality, but do demonstrate how to use the FreeRTOS API and test the\r
- kernel port. */\r
- vStartDynamicPriorityTasks();\r
- vCreateBlockTimeTasks();\r
- vStartCountingSemaphoreTasks();\r
- vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
- vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
- vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
- vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
- vStartEventGroupTasks();\r
- vStartTaskNotifyTask();\r
- vStartInterruptQueueTasks();\r
-\r
- /* Create the register check tasks, as described at the top of this file */\r
- xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
- xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
-\r
- /* Create the task that performs the 'check' functionality, as described at\r
- the top of this file. */\r
- xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
-\r
- /* The set of tasks created by the following function call have to be\r
- created last as they keep account of the number of tasks they expect to see\r
- running. */\r
- vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
-\r
- /* Start the scheduler. */\r
- vTaskStartScheduler();\r
-\r
- /* If all is well, the scheduler will now be running, and the following\r
- line will never be reached. If the following line does execute, then\r
- there was insufficient FreeRTOS heap memory available for the Idle and/or\r
- timer tasks to be created. See the memory management section on the\r
- FreeRTOS web site for more details on the FreeRTOS heap\r
- http://www.freertos.org/a00111.html. */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvCheckTask( void *pvParameters )\r
-{\r
-TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
-TickType_t xLastExecutionTime;\r
-static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
-unsigned long ulErrorFound = pdFALSE;\r
-\r
- /* Just to stop compiler warnings. */\r
- ( void ) pvParameters;\r
-\r
- /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
- works correctly. */\r
- xLastExecutionTime = xTaskGetTickCount();\r
-\r
- /* Cycle for ever, delaying then checking all the other tasks are still\r
- operating without error. The onboard LED is toggled on each iteration.\r
- If an error is detected then the delay period is decreased from\r
- mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
- effect of increasing the rate at which the onboard LED toggles, and in so\r
- doing gives visual feedback of the system status. */\r
- for( ;; )\r
- {\r
- /* Delay until it is time to execute again. */\r
- vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
-\r
- /* Check all the demo tasks (other than the flash tasks) to ensure\r
- that they are all still running, and that none have detected an error. */\r
- if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = 1UL << 0UL;\r
- }\r
-\r
- if( xAreMathsTaskStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = 1UL << 1UL;\r
- }\r
-\r
- if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = 1UL << 2UL;\r
- }\r
-\r
- if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = 1UL << 4UL;\r
- }\r
-\r
- if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = 1UL << 5UL;\r
- }\r
-\r
- if( xIsCreateTaskStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = 1UL << 7UL;\r
- }\r
-\r
- if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = 1UL << 8UL;\r
- }\r
-\r
- if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) != pdPASS )\r
- {\r
- ulErrorFound = 1UL << 9UL;\r
- }\r
-\r
- if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- ulErrorFound = 1UL << 10UL;\r
- }\r
-\r
- if( xAreEventGroupTasksStillRunning() != pdPASS )\r
- {\r
- ulErrorFound = 1UL << 12UL;\r
- }\r
-\r
- if( xAreTaskNotificationTasksStillRunning() != pdPASS )\r
- {\r
- ulErrorFound = 1UL << 14UL;\r
- }\r
-\r
- /* Check that the register test 1 task is still running. */\r
- if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
- {\r
- ulErrorFound = 1UL << 15UL;\r
- }\r
- ulLastRegTest1Value = ulRegTest1LoopCounter;\r
-\r
- /* Check that the register test 2 task is still running. */\r
- if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
- {\r
- ulErrorFound = 1UL << 16UL;\r
- }\r
- ulLastRegTest2Value = ulRegTest2LoopCounter;\r
-\r
- /* Toggle the check LED to give an indication of the system status. If\r
- the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
- everything is ok. A faster toggle indicates an error. */\r
- configTOGGLE_LED();\r
-\r
- if( ulErrorFound != pdFALSE )\r
- {\r
- /* An error has been detected in one of the tasks - flash the LED\r
- at a higher frequency to give visible feedback that something has\r
- gone wrong (it might just be that the loop back connector required\r
- by the comtest tasks has not been fitted). */\r
- xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
- }\r
-\r
- configASSERT( ulErrorFound == pdFALSE );\r
-\r
- /* Just testing the xPortIsInsideInterrupt() functionality. */\r
- configASSERT( xPortIsInsideInterrupt() == pdFALSE );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvRegTestTaskEntry1( void *pvParameters )\r
-{\r
- /* Although the regtest task is written in assembler, its entry point is\r
- written in C for convenience of checking the task parameter is being passed\r
- in correctly. */\r
- if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )\r
- {\r
- /* Start the part of the test that is written in assembler. */\r
- vRegTest1Implementation();\r
- }\r
-\r
- /* The following line will only execute if the task parameter is found to\r
- be incorrect. The check task will detect that the regtest loop counter is\r
- not being incremented and flag an error. */\r
- vTaskDelete( NULL );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvRegTestTaskEntry2( void *pvParameters )\r
-{\r
- /* Although the regtest task is written in assembler, its entry point is\r
- written in C for convenience of checking the task parameter is being passed\r
- in correctly. */\r
- if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )\r
- {\r
- /* Start the part of the test that is written in assembler. */\r
- vRegTest2Implementation();\r
- }\r
-\r
- /* The following line will only execute if the task parameter is found to\r
- be incorrect. The check task will detect that the regtest loop counter is\r
- not being incremented and flag an error. */\r
- vTaskDelete( NULL );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vFullDemoTickHook( void )\r
-{\r
- /* Some of the tests and demo tasks executed by the full demo include\r
- interaction from an interrupt - for which the tick interrupt is used via\r
- the tick hook function. */\r
-\r
- /* The full demo includes a software timer demo/test that requires\r
- prodding periodically from the tick interrupt. */\r
- vTimerPeriodicISRTests();\r
-\r
- /* Call the periodic event group from ISR demo. */\r
- vPeriodicEventGroupsProcessing();\r
-\r
- /* Call the code that 'gives' a task notification from an ISR. */\r
- xNotifyTaskFromISR();\r
-}\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/* Standard includes. */\r
-#include <limits.h>\r
-\r
-/* FreeRTOS includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Library includes. */\r
-#include "common_lib.h"\r
-\r
-/* This file contains functions that will override the default implementations\r
-in the RTOS port layer. Therefore only build this file if the low power demo\r
-is being built. */\r
-#if( configCREATE_LOW_POWER_DEMO == 1 )\r
-\r
-/* ID of the hibernation timer used to generate the tick. */\r
-#define mainTICK_HTIMER_ID 0\r
-\r
-/* Written to the hibernation timer control register to configure the timer for\r
-its higher resolution. */\r
-#define mainHTIMER_HIGH_RESOLUTION 0\r
-\r
-/* The frequency of the hibernation timer when it is running at its higher\r
-resolution and low resolution respectively. */\r
-#define mainHIGHER_RESOLUTION_TIMER_HZ ( 32787UL ) /* (1000000us / 30.5us) as each LSB is 30.5us. */\r
-#define mainLOW_RESOLUTION_TIMER_HZ ( 8UL ) /* ( 1000ms / 125ms ) as each LSB is 0.125s. */\r
-\r
-/* When lpINCLUDE_TEST_TIMER is set to 1 a basic timer is used to generate\r
-interrupts at a low frequency. The purpose being to bring the CPU out of its\r
-sleep mode by an interrupt other than the tick interrupt, and therefore\r
-allowing an additional paths through the code to be tested. */\r
-#define lpINCLUDE_TEST_TIMER 0\r
-\r
-/* Some registers are accessed directly as the library is not compatible with\r
-all the compilers used. */\r
-#define lpHTIMER_PRELOAD_REGISTER ( * ( volatile uint16_t * ) 0x40009800 )\r
-#define lpHTIMER_CONTROL_REGISTER ( * ( volatile uint16_t * ) 0x40009804 )\r
-#define lpHTIMER_COUNT_REGISTER ( * ( volatile uint16_t * ) 0x40009808 )\r
-#define lpEC_GIRQ17_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C0B8 )\r
-#define lpHTIMER_INTERRUPT_CONTROL_BIT ( 1UL << 20UL )\r
-\r
-/*\r
- * The low power demo does not use the SysTick, so override the\r
- * vPortSetupTickInterrupt() function with an implementation that configures\r
- * the low power clock. NOTE: This function name must not be changed as it\r
- * is called from the RTOS portable layer.\r
- */\r
-void vPortSetupTimerInterrupt( void );\r
-\r
-/*\r
- * To fully test the low power tick processing it is necessary to sometimes\r
- * bring the MCU out of its sleep state by a method other than the tick\r
- * interrupt. Interrupts generated from a basic timer are used for this\r
- * purpose.\r
- */\r
-#if( lpINCLUDE_TEST_TIMER == 1 )\r
- static void prvSetupBasicTimer( void );\r
-#endif\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The reload value to use in the timer to generate the tick interrupt -\r
-assumes the timer is running at its higher resolution. */\r
-static const uint32_t ulHighResolutionReloadValue = ( mainHIGHER_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ );\r
-\r
-/* Calculate how many clock increments make up a single tick period. */\r
-static const uint32_t ulReloadValueForOneHighResolutionTick = ( mainHIGHER_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ );\r
-//static const uint32_t usReloadValueForOneLowResolutionTick = ( mainLOW_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ );\r
-\r
-/* Calculate the maximum number of ticks that can be suppressed when using the\r
-high resolution clock and low resolution clock respectively. */\r
-static uint32_t ulMaximumPossibleSuppressedHighResolutionTicks = 0;\r
-//static const uint16_t usMaximumPossibleSuppressedLowResolutionTicks = USHRT_MAX / usReloadValueForOneLowResolutionTick;\r
-\r
-/* As the clock is only 2KHz, it is likely a value of 1 will be too much, so\r
-use zero - but leave the value here to assist porting to different clock\r
-speeds. */\r
-static const uint32_t ulStoppedTimerCompensation = 0UL;\r
-\r
-/* Flag set from the tick interrupt to allow the sleep processing to know if\r
-sleep mode was exited because of an timer interrupt or a different interrupt. */\r
-static volatile uint32_t ulTickFlag = pdFALSE;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void NVIC_Handler_HIB_TMR( void )\r
-{\r
- lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue;\r
-\r
- /* Increment the RTOS tick. */\r
- if( xTaskIncrementTick() != pdFALSE )\r
- {\r
- /* A context switch is required. Context switching is performed in\r
- the PendSV interrupt. Pend the PendSV interrupt. */\r
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
- }\r
-\r
- /* The CPU woke because of a tick. */\r
- ulTickFlag = pdTRUE;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#if( lpINCLUDE_TEST_TIMER == 1 )\r
-\r
- #define GIRQ23_ENABLE_SET ( * ( uint32_t * ) 0x4000C130 )\r
-\r
- static void prvSetupBasicTimer( void )\r
- {\r
- const uint8_t ucTimerChannel = 0;\r
- const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / 10;\r
-\r
- GIRQ23_ENABLE_SET = 0x03;\r
- *(unsigned int*)0x4000FC18 = 1;\r
-\r
- /* To fully test the low power tick processing it is necessary to sometimes\r
- bring the MCU out of its sleep state by a method other than the tick\r
- interrupt. Interrupts generated from a basic timer are used for this\r
- purpose. */\r
- btimer_init( ucTimerChannel, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );\r
- btimer_interrupt_status_get_clr( ucTimerChannel );\r
- enable_timer0_irq();\r
- NVIC_SetPriority( TIMER0_IRQn, ucTimerChannel );\r
- NVIC_ClearPendingIRQ( TIMER0_IRQn );\r
- NVIC_EnableIRQ( TIMER0_IRQn );\r
- btimer_start( ucTimerChannel );\r
- }\r
-\r
-#endif /* lpINCLUDE_TEST_TIMER */\r
-/*-----------------------------------------------------------*/\r
-\r
-void vPortSetupTimerInterrupt( void )\r
-{\r
- ulMaximumPossibleSuppressedHighResolutionTicks = ( ( uint32_t ) USHRT_MAX ) / ulReloadValueForOneHighResolutionTick;\r
-\r
- /* Set up the hibernation timer to start at the value required by the\r
- tick interrupt. Equivalent to the following libarary call. The library\r
- is not used as it is not compatible with all the compilers used:\r
- htimer_enable( mainTICK_HTIMER_ID, ulHighResolutionReloadValue, mainHTIMER_HIGH_RESOLUTION ); */\r
- lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue;\r
- lpHTIMER_CONTROL_REGISTER = mainHTIMER_HIGH_RESOLUTION;\r
-\r
- /* Enable the HTIMER interrupt. Equivalent to enable_htimer0_irq(); */\r
- lpEC_GIRQ17_ENABLE_SET |= lpHTIMER_INTERRUPT_CONTROL_BIT;\r
-\r
- /* The hibernation timer is not an auto-reload timer, so gets reset\r
- from within the ISR itself. For that reason it's interrupt is set\r
- to the highest possible priority to ensure clock slippage is minimised. */\r
- NVIC_SetPriority( HTIMER_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
- NVIC_ClearPendingIRQ( HTIMER_IRQn );\r
- NVIC_EnableIRQ( HTIMER_IRQn );\r
-\r
- /* A basic timer is also started, purely for test purposes. Its only\r
- purpose is to bring the CPU out of its sleep mode by an interrupt other\r
- than the tick interrupt in order to get more code test coverage. */\r
- #if( lpINCLUDE_TEST_TIMER == 1 )\r
- {\r
- prvSetupBasicTimer();\r
- }\r
- #endif\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Override the default definition of vPortSuppressTicksAndSleep() that is\r
-weakly defined in the FreeRTOS Cortex-M port layer with a version that manages\r
-the hibernation timer, as the tick is generated from the low power hibernation\r
-timer and not the SysTick as would normally be the case on a Cortex-M. */\r
-void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
-{\r
-uint32_t ulCompleteTickPeriods, ulReloadValue, ulCompletedTimerDecrements, ulCountAfterSleep, ulCountBeforeSleep;\r
-eSleepModeStatus eSleepAction;\r
-TickType_t xModifiableIdleTime;\r
-\r
- /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */\r
-\r
- /* Make sure the hibernation timer reload value does not overflow the\r
- counter. */\r
- if( xExpectedIdleTime > ( TickType_t ) ulMaximumPossibleSuppressedHighResolutionTicks )\r
- {\r
- xExpectedIdleTime = ( TickType_t ) ulMaximumPossibleSuppressedHighResolutionTicks;\r
- }\r
-\r
- /* Stop the timer momentarily. The time the timer is stopped for is\r
- accounted for as best it can be, but using the tickless mode will\r
- inevitably result in some tiny drift of the time maintained by the kernel\r
- with respect to calendar time. Take the count value first as clearing\r
- the preload value also seems to clear the count. */\r
- ulCountBeforeSleep = ( uint32_t ) lpHTIMER_COUNT_REGISTER;\r
- lpHTIMER_PRELOAD_REGISTER = 0;\r
-\r
- /* Calculate the reload value required to wait xExpectedIdleTime tick\r
- periods. -1 is used as the current time slice will already be part way\r
- through, the part value coming from the current timer count value. */\r
- ulReloadValue = ulCountBeforeSleep + ( ulReloadValueForOneHighResolutionTick * ( xExpectedIdleTime - 1UL ) );\r
-\r
- if( ulReloadValue > ulStoppedTimerCompensation )\r
- {\r
- /* Compensate for the fact that the timer is going to be stopped\r
- momentarily. */\r
- ulReloadValue -= ulStoppedTimerCompensation;\r
- }\r
-\r
- /* Enter a critical section but don't use the taskENTER_CRITICAL() method as\r
- that will mask interrupts that should exit sleep mode. */\r
- __asm volatile( "cpsid i" );\r
- __asm volatile( "dsb" );\r
- __asm volatile( "isb" );\r
-\r
- /* The tick flag is set to false before sleeping. If it is true when sleep\r
- mode is exited then sleep mode was probably exited because the tick was\r
- suppressed for the entire xExpectedIdleTime period. */\r
- ulTickFlag = pdFALSE;\r
-\r
- /* If a context switch is pending then abandon the low power entry as\r
- the context switch might have been pended by an external interrupt that\r
- requires processing. */\r
- eSleepAction = eTaskConfirmSleepModeStatus();\r
- if( eSleepAction == eAbortSleep )\r
- {\r
- /* Resetart the timer from whatever remains in the counter register,\r
- but 0 is not a valid value. */\r
- ulReloadValue = ulCountBeforeSleep - ulStoppedTimerCompensation;\r
-\r
- if( ulReloadValue == 0 )\r
- {\r
- ulReloadValue = ulReloadValueForOneHighResolutionTick;\r
- ulCompleteTickPeriods = 1UL;\r
- }\r
- else\r
- {\r
- ulCompleteTickPeriods = 0UL;\r
- }\r
-\r
- lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue;\r
-\r
- /* Re-enable interrupts - see comments above the cpsid instruction()\r
- above. */\r
- __asm volatile( "cpsie i" );\r
- __asm volatile( "dsb" );\r
- __asm volatile( "isb" );\r
- }\r
- else\r
- {\r
- /* Write the calculated reload value, which will also start the\r
- timer. */\r
- lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue;\r
-\r
- /* Allow the application to define some pre-sleep processing. */\r
- xModifiableIdleTime = xExpectedIdleTime;\r
- configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
-\r
- /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()\r
- means the application defined code has already executed the sleep\r
- instructions. */\r
- if( xModifiableIdleTime > 0 )\r
- {\r
- __asm volatile( "dsb" );\r
- __asm volatile( "wfi" );\r
- __asm volatile( "isb" );\r
- }\r
-\r
- /* Allow the application to define some post sleep processing. */\r
- configPOST_SLEEP_PROCESSING( xModifiableIdleTime );\r
-\r
- /* Stop the hibernation timer. Again, the time the tiemr is stopped\r
- for is accounted for as best it can be, but using the tickless mode\r
- will inevitably result in some tiny drift of the time maintained by the\r
- kernel with respect to calendar time. Take the count value first as\r
- setting the preload to zero also seems to clear the count. */\r
- ulCountAfterSleep = lpHTIMER_COUNT_REGISTER;\r
- lpHTIMER_PRELOAD_REGISTER = 0;\r
-\r
- /* Re-enable interrupts - see comments above the cpsid instruction()\r
- above. */\r
- __asm volatile( "cpsie i" );\r
- __asm volatile( "dsb" );\r
- __asm volatile( "isb" );\r
-\r
- if( ulTickFlag != pdFALSE )\r
- {\r
- /* The tick interrupt has already executed, although because this\r
- function is called with the scheduler suspended the actual tick\r
- processing will not occur until after this function has exited.\r
- The timer has already been reloaded to count in ticks, and can just\r
- continue counting down from its current value. */\r
- ulReloadValue = ulCountAfterSleep;\r
-\r
- /* Sanity check that the timer's reload value has indeed been\r
- reset. */\r
- configASSERT( ( uint32_t ) lpHTIMER_PRELOAD_REGISTER == ulReloadValueForOneHighResolutionTick );\r
-\r
- /* The tick interrupt handler will already have pended the tick\r
- processing in the kernel. As the pending tick will be processed as\r
- soon as this function exits, the tick value maintained by the tick\r
- is stepped forward by one less than the time spent sleeping. The\r
- actual stepping of the tick appears later in this function. */\r
- ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
- }\r
- else\r
- {\r
- /* Something other than the tick interrupt ended the sleep. How\r
- many complete tick periods passed while the processor was\r
- sleeping? */\r
- ulCompletedTimerDecrements = ulReloadValue - ulCountAfterSleep;\r
-\r
- /* Undo the adjustment that was made to the reload value to account\r
- for the fact that a time slice was part way through when this\r
- function was called before working out how many complete tick\r
- periods this represents. (could have used [ulExpectedIdleTime *\r
- ulReloadValueForOneHighResolutionTick] instead of ulReloadValue on\r
- the previous line, but this way avoids the multiplication). */\r
- ulCompletedTimerDecrements += ( ulReloadValueForOneHighResolutionTick - ulCountBeforeSleep );\r
- ulCompleteTickPeriods = ulCompletedTimerDecrements / ulReloadValueForOneHighResolutionTick;\r
-\r
- /* The reload value is set to whatever fraction of a single tick\r
- period remains. */\r
- ulReloadValue = ( ( ulCompleteTickPeriods + 1UL ) * ulReloadValueForOneHighResolutionTick ) - ulCompletedTimerDecrements;\r
- }\r
-\r
- /* Cannot use a reload value of 0 - it will not start the timer. */\r
- if( ulReloadValue == 0 )\r
- {\r
- /* There is no fraction remaining. */\r
- ulReloadValue = ulReloadValueForOneHighResolutionTick;\r
- ulCompleteTickPeriods++;\r
- }\r
-\r
- /* Restart the timer so it runs down from the reload value. The reload\r
- value will get set to the value required to generate exactly one tick\r
- period the next time the tick interrupt executes. */\r
- lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue;\r
- }\r
-\r
- /* Wind the tick forward by the number of tick periods that the CPU\r
- remained in a low power state. */\r
- vTaskStepTick( ulCompleteTickPeriods );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void NVIC_Handler_TMR0( void )\r
-{\r
- /* This timer is used for test purposes. Its only function is to\r
- generate interrupts while the MCU is sleeping, so the MCU is sometimes\r
- brought out of sleep by a means other than the tick interrupt. */\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-\r
-#endif /* configCREATE_LOW_POWER_DEMO */\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
- All rights reserved\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
-\r
- ***************************************************************************\r
- >>! NOTE: The modification to the GPL is included to allow you to !<<\r
- >>! distribute a combined work that includes FreeRTOS without being !<<\r
- >>! obliged to provide the source code for proprietary components !<<\r
- >>! outside of the FreeRTOS kernel. !<<\r
- ***************************************************************************\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that is more than just the market leader, it *\r
- * is the industry's de facto standard. *\r
- * *\r
- * Help yourself get started quickly while simultaneously helping *\r
- * to support the FreeRTOS project by purchasing a FreeRTOS *\r
- * tutorial book, reference manual, or both: *\r
- * http://www.FreeRTOS.org/Documentation *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
- the FAQ page "My application does not run, what could be wrong?". Have you\r
- defined configASSERT()?\r
-\r
- http://www.FreeRTOS.org/support - In return for receiving this top quality\r
- embedded software for free we request you assist our global community by\r
- participating in the support forum.\r
-\r
- http://www.FreeRTOS.org/training - Investing in training allows your team to\r
- be as productive as possible as early as possible. Now you can receive\r
- FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
- Ltd, and the world's leading authority on the world's leading RTOS.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
- Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
- Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and commercial middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * NOTE 1: This project provides two demo applications. A simple blinky demo\r
- * that demonstrates tickless low power operation, and a more comprehensive\r
- * test and demo application. The configCREATE_LOW_POWER_DEMO setting in\r
- * FreeRTOSConfig.h is used to select between the two. See the notes on using\r
- * configCREATE_LOW_POWER_DEMO in main.c. This file implements the low power\r
- * version.\r
- *\r
- * NOTE 2: This file only contains the source code that is specific to the\r
- * low power demo. Generic functions, such FreeRTOS hook functions, and\r
- * functions required to configure the hardware are defined in main.c.\r
- ******************************************************************************\r
- *\r
- * main_low_power() creates one queue, and two tasks. It then starts the\r
- * scheduler.\r
- *\r
- * The Queue Send Task:\r
- * The queue send task is implemented by the prvQueueSendTask() function in\r
- * this file. It sends the value 100 to the queue every second.\r
- *\r
- * The Queue Receive Task:\r
- * The queue receive task is implemented by the prvQueueReceiveTask() function\r
- * in this file. prvQueueReceiveTask() blocks on the queue, blipping (quickly\r
- * turn on then off again) the LED each time it received the value 100 from the\r
- * queue send task. The queue send task writes to the queue every second, so\r
- * the LED will blip once a second.\r
- *\r
- * The RTOS tick is turned off when the queue send task and queue receive task\r
- * are both in the Blocked state.\r
- *\r
- */\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "semphr.h"\r
-\r
-/* Priorities at which the tasks are created. */\r
-#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-\r
-/* The rate at which data is sent to the queue. The 200ms value is converted\r
-to ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 1000 )\r
-\r
-/* The number of items the queue can hold. This is 1 as the receive task\r
-will remove items as they are added, meaning the send task should always find\r
-the queue empty. */\r
-#define mainQUEUE_LENGTH ( 1 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Called by main when configCREATE_LOW_POWER_DEMO is set to 1 in\r
- * main.c.\r
- */\r
-void main_low_power( void );\r
-\r
-/*\r
- * The tasks as described in the comments at the top of this file.\r
- */\r
-static void prvQueueReceiveTask( void *pvParameters );\r
-static void prvQueueSendTask( void *pvParameters );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The queue used by both tasks. */\r
-static QueueHandle_t xQueue = NULL;\r
-\r
-/* The variable that is incremented to represent each LED toggle. On the\r
-clicker hardware the LED state is set to the value of the least significant bit\r
-of this variable. On other hardware, where an LED is not used, the LED just\r
-keeps a count of the number of times the LED would otherwise have been toggled.\r
-See the comments at the top of this file for information on the expected LED\r
-toggle rate. */\r
-extern volatile uint32_t ulLED;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void main_low_power( void )\r
-{\r
- /* Create the queue. */\r
- xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
-\r
- if( xQueue != NULL )\r
- {\r
- /* Start the two tasks as described in the comments at the top of this\r
- file. */\r
- xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
- "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
- configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
- NULL, /* The parameter passed to the task - not used in this case. */\r
- mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
- NULL ); /* The task handle is not required, so NULL is passed. */\r
-\r
- xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
-\r
- /* Start the tasks and timer running. */\r
- vTaskStartScheduler();\r
- }\r
-\r
- /* If all is well, the scheduler will now be running, and the following\r
- line will never be reached. If the following line does execute, then\r
- there was insufficient FreeRTOS heap memory available for the Idle and/or\r
- timer tasks to be created. See the memory management section on the\r
- FreeRTOS web site for more details on the FreeRTOS heap\r
- http://www.freertos.org/a00111.html. */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueSendTask( void *pvParameters )\r
-{\r
-TickType_t xNextWakeTime;\r
-const uint32_t ulValueToSend = 100UL;\r
-\r
- /* Remove compiler warning about unused parameter. */\r
- ( void ) pvParameters;\r
-\r
- /* Initialise xNextWakeTime - this only needs to be done once. */\r
- xNextWakeTime = xTaskGetTickCount();\r
-\r
- for( ;; )\r
- {\r
- /* Place this task in the blocked state until it is time to run again. */\r
- vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
-\r
- /* Send to the queue - causing the queue receive task to unblock and\r
- toggle the LED. 0 is used as the block time so the sending operation\r
- will not block - it shouldn't need to block as the queue should always\r
- be empty at this point in the code. */\r
- xQueueSend( xQueue, &ulValueToSend, 0U );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueReceiveTask( void *pvParameters )\r
-{\r
-uint32_t ulReceivedValue;\r
-const uint32_t ulExpectedValue = 100UL;\r
-const TickType_t xShortDelay = pdMS_TO_TICKS( 10 );\r
-\r
- /* Remove compiler warning about unused parameter. */\r
- ( void ) pvParameters;\r
-\r
- for( ;; )\r
- {\r
- /* Wait until something arrives in the queue - this task will block\r
- indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
- FreeRTOSConfig.h. */\r
- xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
-\r
- /* To get here something must have been received from the queue, but\r
- is it the expected value? If it is, toggle the LED. */\r
- if( ulReceivedValue == ulExpectedValue )\r
- {\r
- /* Blip the LED briefly to show the demo is running, but without\r
- leaving the LED on too long as energy is being conserved. */\r
- configTOGGLE_LED();\r
- vTaskDelay( xShortDelay );\r
- configTOGGLE_LED();\r
-\r
- ulReceivedValue = 0U;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
+++ /dev/null
-/*\r
- **********************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
- **********************************************************************************\r
- * ARM_REG.h\r
- * This is the header to define Cortex-M3 system control & status registers\r
- **********************************************************************************\r
- * SMSC version control information (Perforce):\r
- *\r
- * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/ARM_REG.h $\r
- * REVISION: $Revision: #1 $\r
- * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
- * AUTHOR: $Author: akrishnan $\r
- *\r
- * Revision history (latest first):\r
- * #xx\r
- ***********************************************************************************\r
- */\r
-\r
-/******************************************************************************/\r
-/** @defgroup ARM_REG ARM_REG\r
- * @{\r
- */\r
-\r
-/** @file ARM_REG.h\r
-* \brief ARM Cortex-M3 registers header file\r
-* \author KBCEC Team\r
-* \r
-* This file contains ARM Cortex-M3 system control & status registers.\r
-******************************************************************************/ \r
-#ifndef ARM_REG_H_\r
-#define ARM_REG_H_\r
-\r
-#define REG8(x) (*((volatile unsigned char *)(x)))\r
-#define REG16(x) (*((volatile unsigned short *)(x)))\r
-#define REG32(x) (*((volatile unsigned long *)(x)))\r
-\r
-/* NVIC Registers */\r
-#define NVIC_INT_TYPE REG32(0xE000E004)\r
-#define NVIC_AUX_ACTLR REG32(0xE000E008)\r
- #define WR_BUF_DISABLE (1 << 1)\r
-#define NVIC_ST_CTRL REG32(0xE000E010)\r
- #define ST_ENABLE (1 << 0)\r
- #define ST_TICKINT (1 << 1)\r
- #define ST_CLKSOURCE (1 << 2)\r
- #define ST_COUNTFLAG (1 << 3)\r
-#define NVIC_ST_RELOAD REG32(0xE000E014)\r
-#define NVIC_ST_CURRENT REG32(0xE000E018)\r
-#define NVIC_ST_CALIB REG32(0xE000E01C)\r
-#define NVIC_ENABLE0 REG32(0xE000E100)\r
-#define NVIC_ENABLE1 REG32(0xE000E104)\r
-#define NVIC_ENABLE2 REG32(0xE000E108)\r
-#define NVIC_ENABLE3 REG32(0xE000E10C)\r
-#define NVIC_ENABLE4 REG32(0xE000E110)\r
-#define NVIC_ENABLE5 REG32(0xE000E114)\r
-#define NVIC_ENABLE6 REG32(0xE000E118)\r
-#define NVIC_ENABLE7 REG32(0xE000E11C)\r
-#define NVIC_DISABLE0 REG32(0xE000E180)\r
-#define NVIC_DISABLE1 REG32(0xE000E184)\r
-#define NVIC_DISABLE2 REG32(0xE000E188)\r
-#define NVIC_DISABLE3 REG32(0xE000E18C)\r
-#define NVIC_DISABLE4 REG32(0xE000E190)\r
-#define NVIC_DISABLE5 REG32(0xE000E194)\r
-#define NVIC_DISABLE6 REG32(0xE000E198)\r
-#define NVIC_DISABLE7 REG32(0xE000E19C)\r
-#define NVIC_PEND0 REG32(0xE000E200)\r
-#define NVIC_PEND1 REG32(0xE000E204)\r
-#define NVIC_PEND2 REG32(0xE000E208)\r
-#define NVIC_PEND3 REG32(0xE000E20C)\r
-#define NVIC_PEND4 REG32(0xE000E210)\r
-#define NVIC_PEND5 REG32(0xE000E214)\r
-#define NVIC_PEND6 REG32(0xE000E218)\r
-#define NVIC_PEND7 REG32(0xE000E21C)\r
-#define NVIC_UNPEND0 REG32(0xE000E280)\r
-#define NVIC_UNPEND1 REG32(0xE000E284)\r
-#define NVIC_UNPEND2 REG32(0xE000E288)\r
-#define NVIC_UNPEND3 REG32(0xE000E28C)\r
-#define NVIC_UNPEND4 REG32(0xE000E290)\r
-#define NVIC_UNPEND5 REG32(0xE000E294)\r
-#define NVIC_UNPEND6 REG32(0xE000E298)\r
-#define NVIC_UNPEND7 REG32(0xE000E29C)\r
-#define NVIC_ACTIVE0 REG32(0xE000E300)\r
-#define NVIC_ACTIVE1 REG32(0xE000E304)\r
-#define NVIC_ACTIVE2 REG32(0xE000E308)\r
-#define NVIC_ACTIVE3 REG32(0xE000E30C)\r
-#define NVIC_ACTIVE4 REG32(0xE000E310)\r
-#define NVIC_ACTIVE5 REG32(0xE000E314)\r
-#define NVIC_ACTIVE6 REG32(0xE000E318)\r
-#define NVIC_ACTIVE7 REG32(0xE000E31C)\r
-#define NVIC_PRI0 REG32(0xE000E400)\r
-#define NVIC_PRI1 REG32(0xE000E404)\r
-#define NVIC_PRI2 REG32(0xE000E408)\r
-#define NVIC_PRI3 REG32(0xE000E40C)\r
-#define NVIC_PRI4 REG32(0xE000E410)\r
-#define NVIC_PRI5 REG32(0xE000E414)\r
-#define NVIC_PRI6 REG32(0xE000E418)\r
-#define NVIC_PRI7 REG32(0xE000E41C)\r
-#define NVIC_PRI8 REG32(0xE000E420)\r
-#define NVIC_PRI9 REG32(0xE000E424)\r
-#define NVIC_PRI10 REG32(0xE000E428)\r
-#define NVIC_PRI11 REG32(0xE000E42C)\r
-#define NVIC_PRI12 REG32(0xE000E430)\r
-#define NVIC_PRI13 REG32(0xE000E434)\r
-#define NVIC_PRI14 REG32(0xE000E438)\r
-#define NVIC_PRI15 REG32(0xE000E43C)\r
-#define NVIC_PRI16 REG32(0xE000E440)\r
-#define NVIC_PRI17 REG32(0xE000E444)\r
-#define NVIC_PRI18 REG32(0xE000E448)\r
-#define NVIC_PRI19 REG32(0xE000E44C)\r
-#define NVIC_PRI20 REG32(0xE000E450)\r
-#define NVIC_PRI21 REG32(0xE000E454)\r
-#define NVIC_PRI22 REG32(0xE000E458)\r
-#define NVIC_PRI23 REG32(0xE000E45C)\r
-#define NVIC_PRI24 REG32(0xE000E460)\r
-#define NVIC_PRI25 REG32(0xE000E464)\r
-#define NVIC_PRI26 REG32(0xE000E468)\r
-#define NVIC_PRI27 REG32(0xE000E46C)\r
-#define NVIC_PRI28 REG32(0xE000E470)\r
-#define NVIC_PRI29 REG32(0xE000E474)\r
-#define NVIC_PRI30 REG32(0xE000E478)\r
-#define NVIC_PRI31 REG32(0xE000E47C)\r
-#define NVIC_PRI32 REG32(0xE000E480)\r
-#define NVIC_PRI33 REG32(0xE000E484)\r
-#define NVIC_PRI34 REG32(0xE000E488)\r
-#define NVIC_PRI35 REG32(0xE000E48C)\r
-#define NVIC_PRI36 REG32(0xE000E490)\r
-#define NVIC_PRI37 REG32(0xE000E494)\r
-#define NVIC_PRI38 REG32(0xE000E498)\r
-#define NVIC_PRI39 REG32(0xE000E49C)\r
-#define NVIC_PRI40 REG32(0xE000E4A0)\r
-#define NVIC_PRI41 REG32(0xE000E4A4)\r
-#define NVIC_PRI42 REG32(0xE000E4A8)\r
-#define NVIC_PRI43 REG32(0xE000E4AC)\r
-#define NVIC_PRI44 REG32(0xE000E4B0)\r
-#define NVIC_PRI45 REG32(0xE000E4B4)\r
-#define NVIC_PRI46 REG32(0xE000E4B8)\r
-#define NVIC_PRI47 REG32(0xE000E4BC)\r
-#define NVIC_PRI48 REG32(0xE000E4C0)\r
-#define NVIC_PRI49 REG32(0xE000E4C4)\r
-#define NVIC_PRI50 REG32(0xE000E4C8)\r
-#define NVIC_PRI51 REG32(0xE000E4CC)\r
-#define NVIC_PRI52 REG32(0xE000E4D0)\r
-#define NVIC_PRI53 REG32(0xE000E4D4)\r
-#define NVIC_PRI54 REG32(0xE000E4D8)\r
-#define NVIC_PRI55 REG32(0xE000E4DC)\r
-#define NVIC_PRI56 REG32(0xE000E4E0)\r
-#define NVIC_PRI57 REG32(0xE000E4E4)\r
-#define NVIC_PRI58 REG32(0xE000E4E8)\r
-#define NVIC_PRI59 REG32(0xE000E4EC)\r
-#define NVIC_CPUID REG32(0xE000ED00)\r
-#define NVIC_INT_CTRL REG32(0xE000ED04)\r
-#define NVIC_VECT_TABLE REG32(0xE000ED08)\r
-#define NVIC_AP_INT_RST REG32(0xE000ED0C)\r
-#define NVIC_SYS_CTRL REG32(0xE000ED10)\r
-#define NVIC_CFG_CTRL REG32(0xE000ED14)\r
-#define NVIC_SYS_H_PRI1 REG32(0xE000ED18)\r
-#define NVIC_SYS_H_PRI2 REG32(0xE000ED1C)\r
-#define NVIC_SYS_H_PRI3 REG32(0xE000ED20)\r
-#define NVIC_SYS_H_CTRL REG32(0xE000ED24)\r
-#define NVIC_FAULT_STA REG32(0xE000ED28)\r
-#define NVIC_HARD_F_STA REG32(0xE000ED2C)\r
-#define NVIC_DBG_F_STA REG32(0xE000ED30)\r
-#define NVIC_MM_F_ADR REG32(0xE000ED34)\r
-#define NVIC_BUS_F_ADR REG32(0xE000ED38)\r
-#define NVIC_SW_TRIG REG32(0xE000EF00)\r
-\r
-/* MPU Registers */\r
-#define MPU_TYPE REG32(0xE000ED90)\r
-#define MPU_CTRL REG32(0xE000ED94)\r
-#define MPU_RG_NUM REG32(0xE000ED98)\r
-#define MPU_RG_ADDR REG32(0xE000ED9C)\r
-#define MPU_RG_AT_SZ REG32(0xE000EDA0)\r
-\r
-\r
-#endif /* #ifndef ARM_REG_H_ */\r
-\r
-/** @}\r
- */\r
+++ /dev/null
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-*****************************************************************************/\r
-\r
-\r
-\r
-#ifndef INCLUDE_CEC1302_CRYPTO_API_H_\r
-#define INCLUDE_CEC1302_CRYPTO_API_H_\r
-\r
-#include <stdint.h>\r
-#include <stdbool.h>\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/* Misc. */\r
-\r
-/* RNG */\r
-/**\r
- * \rng_power\r
- * \r
- * \param [in] pwr_on Power On?\r
- * \return none\r
- * \r
- * \details Gate clocks on/off to NDRNG block\r
- */\r
-extern void\r
-rng_power(bool pwr_on);\r
-\r
-\r
-/**\r
- * \rng_reset\r
- * \r
- * \return Reset NDRNG block\r
- * \r
- * \details \r
- */\r
-extern void\r
-rng_reset(void);\r
-\r
-\r
-/**\r
- * \rng_mode\r
- * \r
- * \param [in] mode tmode_pseudo 0(asynchronous/true random mode), \r
- * Non-zero(pseudo-random mode)\r
- * \return None\r
- * \r
- * \details Set NDRNG random number generation mode\r
- */\r
-extern void\r
-rng_mode(uint8_t mode);\r
-\r
-\r
-/**\r
- * \rng_is_on\r
- * \r
- * \return is NDRNG Block powered on? True if yes, false otherwise\r
- * \r
- * \details Check if NDRNG block is powered on.\r
- */\r
-extern bool\r
-rng_is_on(void);\r
-\r
-\r
-/**\r
- * \rng_start\r
- * \r
- * \return None\r
- * \r
- * \details Start NDRNG engine\r
- */\r
-extern void\r
-rng_start(void);\r
-\r
-/**\r
- * \rng_stop\r
- * \r
- * \return Void\r
- * \r
- * \details Stop NDRNG engine\r
- */\r
-extern void\r
-rng_stop(void);\r
-\r
-\r
-/**\r
- * \rng_get_fifo_level\r
- * \r
- * \return actual number of 32-bit words in the NDRNG FIFO.\r
- * \r
- * \details return the number of 32-bit words of random data \r
- * currently in the FIFO.\r
- */\r
-extern uint32_t\r
-rng_get_fifo_level(void);\r
-\r
-\r
-/**\r
- * \rng_get_bytes\r
- * \r
- * \param [in] pbuff Output Buffer\r
- * \param [in] nbytes Number of bytes to be read\r
- * \return Number of bytes retrieved\r
- * \r
- * \details read bytes from the NDRNG FIFO\r
- */\r
-extern uint32_t\r
-rng_get_bytes(uint8_t* pbuff, uint32_t nbytes);\r
-\r
-\r
-/**\r
- * \rng_get_words\r
- * \r
- * \param [in] pwords Pointer to output buffer\r
- * \param [in] nwords Number of words to read\r
- * \return actual number of words read\r
- * \r
- * \details Details\r
- */\r
-extern uint32_t\r
-rng_get_words(uint32_t* pwords, uint32_t nwords);\r
-\r
-\r
-/* AES */\r
-/**\r
- * \aes_hash_power\r
- * \r
- * \param [in] pwr_on Gate/Ungate clocks to block\r
- * \return None\r
- * \r
- * \details Enable/Disable AES and HASH H/W Block\r
- */\r
-extern void\r
-aes_hash_power(uint8_t pwr_on);\r
-\r
-/**\r
- * \aes_hash_reset\r
- * \r
- * \return None\r
- * \r
- * \details Stop AES and HASH\r
- */\r
-extern void\r
-aes_hash_reset(void);\r
-\r
-/**\r
- * \aes_busy\r
- * \r
- * \return Is AES Block Running? True if yes, false Otherwise.\r
- * \r
- * \details Is AES Block Running?\r
- */\r
-extern bool\r
-aes_busy(void);\r
-\r
-\r
-/**\r
- * \aes_status\r
- * \r
- * \return Status of AES Block\r
- * \r
- * \details Returns the Status of AES Block\r
- */\r
-extern uint32_t\r
-aes_status(void);\r
-\r
-/**\r
- * \aes_done_status\r
- * \r
- * \param [in] hw_status Pointer to where the status value will be updated\r
- * \return True if done, false otherwise\r
- * \r
- * \details Returns the done status of AES block\r
- */\r
-extern bool\r
-aes_done_status(uint32_t* hw_status);\r
-\r
-/**\r
- * \aes_stop\r
- * \r
- * \return Return aes_busy() Status\r
- * \r
- * \details Stop AES Operations\r
- */\r
-extern bool\r
-aes_stop(void);\r
-\r
-/**\r
- * \aes_start\r
- * \r
- * \param [in] ien Enable interrupts?\r
- * \return None\r
- * \r
- * \details Start AES block with or without interrupts\r
- */\r
-extern void\r
-aes_start(bool ien);\r
-\r
-/**\r
- * \aes_iclr\r
- * \r
- * \return Status of the AES Block\r
- * \r
- * \details Clears AES Hash Interrupts\r
- */\r
-extern uint32_t\r
-aes_iclr(void);\r
-\r
-\r
-/**\r
- * \brief Brief\r
- * \r
- * \param [in] pkey Aligned buffer with AES Key\r
- * \param [in] piv Aligned buffer with AES initialization\r
- * \param [in] key_len AES_KEYLEN_128, AES_KEYLEN_192, AES_KEYLEN_256\r
- * \param [in] msbf Most Significant Byte order first?\r
- * \return AES_ERR_BAD_POINTER, AES_ERR_BAD_KEY_LEN, AES_OK\r
- * \r
- * \details Load AES Accelerator with key and optional Initialization vector\r
- */\r
-extern uint8_t\r
-aes_set_key(const uint32_t* pkey,\r
- const uint32_t* piv,\r
- uint8_t key_len, bool msbf);\r
-\r
-/**\r
- * \aes_crypt\r
- * \r
- * \param [in] data_in Aligned input data Buffer\r
- * \param [in] data_out Aligned output data buffer\r
- * \param [in] num_128bit_blocks Size of input in 16-byte blocks\r
- * \param [in] mode AES Encryption/Decryption Mode\r
- * \return AES_OK, AES_ERR_BAD_POINTER, \r
- * \r
- * \details Program specified AES Operation using currently programmed key\r
- */\r
-extern uint8_t\r
-aes_crypt(const uint32_t* data_in,\r
- uint32_t* data_out,\r
- uint32_t num_128bit_blocks, uint8_t mode);\r
-\r
-\r
-/* SHA */\r
-#define SHA1_BLEN (20u)\r
-#define SHA1_WLEN (5u)\r
-#define SHA2_BLEN (32u)\r
-#define SHA2_WLEN (8u)\r
-#define SHA12_BLOCK_BLEN (64u)\r
-#define SHA12_BLOCK_WLEN (16u)\r
-#define SHA3_BLEN (48u)\r
-#define SHA3_WLEN (12u)\r
-#define SHA5_BLEN (64u)\r
-#define SHA5_WLEN (16u)\r
-\r
-/* return values */\r
-#define SHA_RET_OK (0) /* OK */\r
-#define SHA_RET_START (1) /* OK, SHA Engine started */\r
-#define SHA_RET_ERROR (0x80) /* b[7]==1 indicates an error */\r
-#define SHA_RET_ERR_BUSY (0x80)\r
-#define SHA_RET_ERR_BAD_ADDR (0x81)\r
-#define SHA_RET_ERR_TIMEOUT (0x82)\r
-#define SHA_RET_ERR_MAX_LEN (0x83)\r
-#define SHA_RET_ERR_UNSUPPORTED (0x84)\r
-\r
-#define SHA_MODE_MD5 (0) // Not supported by HW\r
-#define SHA_MODE_1 (1)\r
-#define SHA_MODE_224 (2) // Not supported by HW\r
-#define SHA_MODE_256 (3)\r
-#define SHA_MODE_384 (4) // Not supported by HW\r
-#define SHA_MODE_512 (5) // Not supported by HW\r
-\r
-#define HASH_START_IEN (1u)\r
-#define HASH_START_NOIEN (0u)\r
-\r
-typedef union {\r
- uint32_t w[SHA2_WLEN];\r
- uint8_t b[SHA2_BLEN];\r
-} SHA12_DIGEST_U;\r
-\r
-\r
-/*\r
- * !!! SHA-1 & SHA-256\r
- * HW Engine requires alignment >= 4-byte boundary !!!\r
- */\r
-typedef struct sha12_context_s SHA12_CONTEXT_T;\r
-struct sha12_context_s {\r
- SHA12_DIGEST_U hash;\r
- union {\r
- uint32_t w[(SHA12_BLOCK_WLEN) * 2];\r
- uint8_t b[(SHA12_BLOCK_BLEN) * 2];\r
- } block;\r
- uint8_t mode;\r
- uint8_t block_len;\r
- uint8_t rsvd[2];\r
- uint32_t total_msg_len;\r
-};\r
-\r
-\r
-/**\r
- * \hash_busy\r
- * \r
- * \return is busy? True if yes, Flase other wise\r
- * \r
- * \details returns the busy status of Hash Block\r
- */\r
-extern bool hash_busy(void);\r
-\r
-/**\r
- * \hash_start\r
- * \r
- * \param [in] ien enable/disable interrupts\r
- * \return None\r
- * \r
- * \details start hash block\r
- */\r
-extern void\r
-hash_start(bool ien);\r
-\r
-/**\r
- * \hash_done_status\r
- * \r
- * \param [in] hw_status Hash Status Register Value\r
- * \return true if done, false otherwise\r
- * \r
- * \details reflects the done status of HASH black and updates\r
- * status regsiter value into the input variable\r
- */\r
-extern bool\r
-hash_done_status(uint32_t* hw_status);\r
-\r
-/**\r
- * \sha12_init\r
- * \r
- * \param [in] psha12_ctx Data Structure for Input data and Output Digest\r
- * \param [in] mode SHA_MODE_1 or SHA_MODE_256\r
- * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_UNSPPORTED ,SHA_RET_OK\r
- * \r
- * \details Initializes the Data structure provided\r
- */\r
-extern uint8_t\r
-sha12_init(SHA12_CONTEXT_T* psha12_ctx, uint8_t mode);\r
-\r
-/**\r
- * \sha12_update\r
- * \r
- * \param [in] psha12_ctx Data Structure for Input data and Output Digest\r
- * \param [in] pdata Input Data to Hash Block\r
- * \param [in] num_bytes Byte length of input data\r
- * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY, SHA_RET_ERR_MAX_LEN, SHA_RET_OK \r
- * \r
- * \details Run hash block on data and if data greater than block size, put remaining bytes back into the data structure \r
- */\r
-extern uint8_t\r
-sha12_update(SHA12_CONTEXT_T* psha12_ctx,\r
- const uint32_t* pdata, uint32_t num_bytes);\r
-\r
-/**\r
- * \sha12_finalize\r
- * \r
- * \param [in] psha12_ctx Data Structure for Input data and Output Digest\r
- * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START \r
- * \r
- * \details Apply FIPS padding to SHA256 and perform final hash calculation.\r
- */\r
-extern uint8_t\r
-sha12_finalize(SHA12_CONTEXT_T* psha12_ctx);\r
-\r
-/**\r
- * \sha256_pad_fill\r
- * \r
- * \param [in] pblock64 Aligned Memory buffer of atleast 64 bytes\r
- * \param [in] msg_byte_len Length of Message in bytes\r
- * \return None\r
- * \r
- * \details Zero and fill a 64-byte SHA256 pad block with FIP padding values\r
- */\r
-extern void\r
-sha256_pad_fill(uint32_t* pblock64, uint32_t msg_byte_len);\r
-\r
-\r
-/**\r
- * \sha256_raw\r
- * \r
- * \param [in] pdata Input Message\r
- * \param [in] pdigest Pointer to biffer where digest will be written\r
- * \param [in] num64byte_blocks size of input data in blocks\r
- * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START \r
- * \r
- * \details Calculate SHA256 on data\r
- */\r
-extern uint8_t\r
-sha256_raw(uint32_t* pdata, uint32_t* pdigest, uint32_t num64byte_blocks);\r
-\r
-/**\r
- * \sha256_raw_init\r
- * \r
- * \param [in] psha256_digest Pointer to buffer where digest will be written\r
- * \return None\r
- * \r
- * \details Initialize the SHA256 Digest data block\r
- */\r
-extern void\r
-sha256_raw_init(uint32_t* psha256_digest);\r
-\r
-/**\r
- * \sha256_raw_update\r
- * \r
- * \param [in] pdata Message on which HASH block is to be called\r
- * \param [in] pdigest Pointer to where the digest will be stored\r
- * \param [in] num64byte_blocks size of input data in blocks\r
- * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START\r
- * \r
- * \details run Hash block on data\r
- */\r
-extern uint8_t\r
-sha256_raw_update(uint32_t* pdata,\r
- uint32_t* pdigest, uint32_t num64byte_blocks);\r
-\r
-/**\r
- * \hash_iclr\r
- * \r
- * \return Hash Block status\r
- * \r
- * \details Clear Hash Interrupt\r
- */\r
-extern uint32_t\r
-hash_iclr(void);\r
-\r
-\r
-/**\r
- * \sha_init\r
- * \r
- * \param [in] mode SHA_MODE_1, SHA_MODE_256, SHA_MODE_512\r
- * \param [in] pdigest Address where digest will be stored\r
- * \return * 0 = Success \r
- * 1 = Hash Engine busy \r
- * 2 = Unsupported SHA operation \r
- * 3 = Bad digest pointer, NULL or mis-aligned. \r
- * \details Initialize Hash engine for SHA operation.\r
- * Programs supported SHA operation's initial value, digest address, \r
- * and operation\r
- */\r
-extern uint8_t\r
-sha_init(uint8_t mode, uint32_t* pdigest);\r
-\r
-\r
-/**\r
- * \sha_update\r
- * \r
- * \param [in] pdata Input Data\r
- * \param [in] nblocks Size in blocks\r
- * \param [in] flags bit(0) - Clear Status?, bit(1) - Enable Interrupts?, bit(2) - Start?\r
- * \return 0 - OK, 1 - Hash Busy, 2 - bad address for data, 3 - Buffer not aligned\r
- * \r
- * \details Run Hash block on data\r
- */\r
-extern uint8_t\r
-sha_update(uint32_t* pdata, uint16_t nblocks, uint8_t flags);\r
-\r
-\r
-/**\r
- * \sha_final\r
- * \r
- * \param [in] padbuf Buffer for padding (Twice block size)\r
- * \param [in] total_msg_len Message length in bytes\r
- * \param [in] prem Parameter_Description\r
- * \param [in] flags bit(0) - Clear Status?, bit(1) - Enable Interrupts?, bit(2) - Start?\r
- * \return 0 - OK, 1 - Hash Busy, 2 - bad address for data, 3 - Buffer not aligned\r
- * \r
- * \details Run final SHA Calculations and add padding\r
- */\r
-extern uint8_t\r
-sha_final(uint32_t* padbuf, uint32_t total_msg_len,\r
- const uint8_t* prem, uint8_t flags);\r
-\r
-\r
-/* PKE Miscellaneous */\r
-\r
-#define PKE_RET_STARTED (0)\r
-#define PKE_RET_OK (0)\r
-#define PKE_RET_ERR_BUSY (1)\r
-#define PKE_RET_ERR_BAD_PARAM (2)\r
-#define PKE_RET_ERR_BAD_ADDR (3)\r
-#define PKE_RET_ERR_UNKNOWN_OP (4)\r
-#define PKE_RET_ERR_INVALID_BIT_LENGTH (5)\r
-#define PKE_RET_ERR_INVALID_MSG_LENGTH (6)\r
-\r
-\r
-/**\r
- * \pke_power\r
- * \r
- * \param [in] pwr_on power on? \r
- * \return None\r
- * \r
- * \details Gate or Ungate power to PKE block\r
- */\r
-extern void\r
-pke_power(bool pwr_on);\r
-\r
-\r
-/**\r
- * \brief pke_reset\r
- * \r
- * \return None\r
- * \r
- * \details Reset PKE Block\r
- */\r
-extern void\r
-pke_reset(void);\r
-\r
-/**\r
- * \pke_status\r
- * \r
- * \return Return PKE Status register value\r
- * \r
- * \details Details\r
- */\r
-extern uint32_t\r
-pke_status(void);\r
-\r
-/**\r
- * \pke_done_status\r
- * \r
- * \param [in] hw_status POinter where PKE Status is updated\r
- * \return True if done, false otherwise\r
- * \r
- * \details Returns the done status of PKE block\r
- */\r
-extern bool\r
-pke_done_status(uint32_t* hw_status);\r
-\r
-/**\r
- * \pke_start\r
- * \r
- * \param [in] ien Interrupt Enable?\r
- * \return None\r
- * \r
- * \details Start PKE Block\r
- */\r
-extern void\r
-pke_start(bool ien);\r
-\r
-\r
-/**\r
- * \pke_busy\r
- * \r
- * \return Busy? True if busy, false otherwise\r
- * \r
- * \details Details\r
- */\r
-extern bool\r
-pke_busy(void);\r
-\r
-\r
-/**\r
- * \pke_clear_scm\r
- * \r
- * \return None\r
- * \r
- * \details Clear the Shared Crypto memory\r
- */\r
-extern void\r
-pke_clear_scm(void);\r
-\r
-/**\r
- * \pke_scm_clear_slot\r
- * \r
- * \param [in] slot_num Slot number in Shared Crypto Memory\r
- * \return None\r
- * \r
- * \details Clear the specified slot in Shared Crypto Memory\r
- */\r
-extern void\r
-pke_scm_clear_slot(uint8_t slot_num);\r
-\r
-/**\r
- * \pke_read_scm \r
- * \r
- * \param [in] dest Pointer to where the data is to be read\r
- * \param [in] nbytes Number of bytes to be read\r
- * \param [in] slot_num Slot number from which data is to be read\r
- * \param [in] reverse_byte_order Reverse Byte order? True if yes, false otherwise\r
- * \return Number of bytes Read\r
- * \r
- * \details Read data from specified slot number in Shared Crypto memory\r
- */\r
-extern uint16_t\r
-pke_read_scm(uint8_t* dest, uint16_t nbytes,\r
- uint8_t slot_num, bool reverse_byte_order);\r
-\r
-\r
-/**\r
- * \pke_write_scm \r
- * \r
- * \param [in] pdata Data to be written\r
- * \param [in] num_bytes Number of bytes to be written\r
- * \param [in] slot_num Slot number to which data ought to be written\r
- * \param [in] reverse_byte_order Reverse Byte order? True if yes, false otherwise\r
- * \return None\r
- * \r
- * \details Write data provided to specified slot in Shared Crypto Memory\r
- */\r
-extern void\r
-pke_write_scm(const void* pdata, uint16_t num_bytes,\r
- uint8_t slot_num, uint8_t reverse_byte_order);\r
-\r
-/* PKE RSA */\r
-\r
-/**\r
- * \ rsa_load_key\r
- * \r
- * \param [in] rsa_bit_len 1024, 2048\r
- * \param [in] private_exponent Pointer to private exponent\r
- * \param [in] public_modulus Pointer to Public modulus\r
- * \param [in] public_exponent Pointer to Public Exponent\r
- * \param [in] public_exponent_byte_len Length in bytes of Public Exponent\r
- * \param [in] msbf Reverse Byte order? True if yes, false otherwise\r
- * \return PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK\r
- * \r
- * \details Load RSA keys into Crypto memory\r
- */\r
-extern uint8_t\r
-rsa_load_key(uint16_t rsa_bit_len,\r
- const uint8_t* private_exponent,\r
- const uint8_t* public_modulus,\r
- const uint8_t* public_exponent,\r
- uint16_t public_exponent_byte_len,\r
- bool msbf);\r
-\r
- \r
-/**\r
- * \ rsa_encrypt\r
- * \r
- * \param [in] rsa_bit_len 1024, 2048\r
- * \param [in] mesg Message to be encrypted\r
- * \param [in] mlen length of message\r
- * \param [in] flags bit[0]=0(do not start), 1(start after programming), bit[4] = byte order: 0 = Least significant byte first, 1 = Most significant byte first, bit[1]=0(do not enable interrupt), 1(enable interrupt before starting) \r
- * \return PKE_RET_ERR_BAD_ADDR, PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_MSG_LENGTH, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK\r
- * \r
- * \details Encrypt provided message. Load Keys before this function is called\r
- */\r
-extern uint8_t\r
-rsa_encrypt(uint16_t rsa_bit_len,\r
- const uint8_t* mesg,\r
- uint16_t mlen,\r
- uint8_t flags);\r
- \r
-\r
-\r
-/**\r
- * \ rsa_decrypt\r
- * \r
- * \param [in] rsa_bit_len 1024, 2048\r
- * \param [in] encrypted_mesg Encrypted data\r
- * \param [in] mlen length of encrypted message\r
- * \param [in] flags flags bit[0]=0(do not start), 1(start after programming), bit[4] = byte order: 0 = Least significant byte first, 1 = Most significant byte first, bit[1]=0(do not enable interrupt), 1(enable interrupt before starting)\r
- * \return PKE_RET_ERR_BAD_ADDR, PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_MSG_LENGTH, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK\r
- * \r
- * \details Perform decryption on provided encrypted message. load keys before calling this function\r
- */\r
-extern uint8_t\r
-rsa_decrypt(uint16_t rsa_bit_len,\r
- const uint8_t* encrypted_mesg,\r
- uint16_t mlen,\r
- uint8_t flags);\r
-\r
- \r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* INCLUDE_CEC1302_CRYPTO_API_H_ */\r
+++ /dev/null
-\r
-/****************************************************************************************************//**\r
- * @file MCHP_CEC1302.h\r
- *\r
- * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for\r
- * MCHP_CEC1302 from Microchip Technology Inc..\r
- *\r
- * @version V1.1\r
- * @date 6. November 2015\r
- *\r
- * @note Generated with SVDConv V2.87e \r
- * from CMSIS SVD File 'MCHP_CEC1302.svd' Version 1.1,\r
- *\r
- * @par ARM Limited (ARM) is supplying this software for use with Cortex-M processor based \r
- * microcontroller, but can be equally used for other suitable processor architectures.\r
- * This file can be freely distributed. Modifications to this file shall be clearly marked.\r
- * \r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. \r
- *\r
- *******************************************************************************************************/\r
-\r
-\r
-\r
-/** @addtogroup Microchip Technology Inc.\r
- * @{\r
- */\r
-\r
-/** @addtogroup MCHP_CEC1302\r
- * @{\r
- */\r
-\r
-#ifndef MCHP_CEC1302_H\r
-#define MCHP_CEC1302_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-\r
-/* ------------------------- Interrupt Number Definition ------------------------ */\r
-\r
-typedef enum {\r
-/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */\r
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */\r
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */\r
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */\r
- MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation\r
- and No Match */\r
- BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory\r
- related Fault */\r
- UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */\r
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */\r
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */\r
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */\r
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */\r
-/* ------------------- MCHP_CEC1302 Specific Interrupt Numbers ------------------ */\r
- I2C0_IRQn = 0, /*!< 0 I2C0 / SMB0 Interrupt ................. Also see GIRQ 12.0 */\r
- I2C1_IRQn = 1, /*!< 1 I2C1 / SMB1 Interrupt ................. Also see GIRQ 12.1 */\r
- I2C2_IRQn = 2, /*!< 2 I2C2 / SMB2 Interrupt ................. Also see GIRQ 12.2 */\r
- I2C3_IRQn = 3, /*!< 3 I2C3 / SMB3 Interrupt ................. Also see GIRQ 12.3 */\r
- DMA0_IRQn = 4, /*!< 4 DMA_CH0 Interrupt ..................... Also see GIRQ 13.16 */\r
- DMA1_IRQn = 5, /*!< 5 DMA_CH1 Interrupt ..................... Also see GIRQ 13.17 */\r
- DMA2_IRQn = 6, /*!< 6 DMA_CH2 Interrupt ..................... Also see GIRQ 13.18 */\r
- DMA3_IRQn = 7, /*!< 7 DMA_CH3 Interrupt ..................... Also see GIRQ 13.19 */\r
- DMA4_IRQn = 8, /*!< 8 DMA_CH4 Interrupt ..................... Also see GIRQ 13.20 */\r
- DMA5_IRQn = 9, /*!< 9 DMA_CH5 Interrupt ..................... Also see GIRQ 13.21 */\r
- DMA6_IRQn = 10, /*!< 10 DMA_CH6 Interrupt ..................... Also see GIRQ 13.22 */\r
- DMA7_IRQn = 11, /*!< 11 DMA_CH7 Interrupt ..................... Also see GIRQ 13.23 */\r
- LPC_IRQn = 12, /*!< 12 LPC Interrupt ......................... Also see GIRQ 14.2 */\r
- UART_IRQn = 13, /*!< 13 UART Interrupt ........................ Also see GIRQ 15.0 */\r
- EMI_0_IRQn = 14, /*!< 14 EMI_0 (IMAP) Interrupt ................ Also see GIRQ 15.2 */\r
- ACPIEC0_IBF_IRQn = 15, /*!< 15 ACPIEC[0] IBF Interrupt ............... Also see GIRQ 15.6 */\r
- ACPIEC0_OBF_IRQn = 16, /*!< 16 ACPIEC[0] OBF Interrupt ............... Also see GIRQ 15.7 */\r
- ACPIEC1_IBF_IRQn = 17, /*!< 17 ACPIEC[1] IBF Interrupt ............... Also see GIRQ 15.8 */\r
- ACPIEC1_OBF_IRQn = 18, /*!< 18 ACPIEC[1] OBF Interrupt ............... Also see GIRQ 15.9 */\r
- ACPIPM1_CTL_IRQn = 19, /*!< 19 ACPIPM1_CTL Interrupt ................. Also see GIRQ 15.10 */\r
- ACPIPM1_EN_IRQn = 20, /*!< 20 ACPIPM1_EN Interrupt .................. Also see GIRQ 15.11 */\r
- ACPIPM1_STS_IRQn = 21, /*!< 21 ACPIPM1_STS Interrupt ................. Also see GIRQ 15.12 */\r
- KBC8042_OBF_IRQn = 22, /*!< 22 8042EM OBF Interrupt .................. Also see GIRQ 15.13 */\r
- KBC8042_IBF_IRQn = 23, /*!< 23 8042EM IBF Interrupt .................. Also see GIRQ 15.14 */\r
- MAILBOX_IRQn = 24, /*!< 24 MAILBOX Interrupt ..................... Also see GIRQ 15.15 */\r
- PECIHOST_IRQn = 25, /*!< 25 PECIHOST Interrupt .................... Also see GIRQ 16.3 */\r
- TACH_0_IRQn = 26, /*!< 26 TACH_0 Interrupt ...................... Also see GIRQ 17.0 */\r
- TACH_1_IRQn = 27, /*!< 27 TACH_1 Interrupt ...................... Also see GIRQ 17.1 */\r
- ADC_SNGL_IRQn = 28, /*!< 28 ADC_SNGL Interrupt .................... Also see GIRQ 17.10 */\r
- ADC_RPT_IRQn = 29, /*!< 29 ADC_RPT Interrupt ..................... Also see GIRQ 17.11 */\r
- ADC2PWM_N1_IRQn = 30, /*!< 30 MCHP Reserved ADC2PWM_INT_N1 .......... Also see GIRQ 17.12 */\r
- ADC2PWM_N2_IRQn = 31, /*!< 31 MCHP Reserved ADC2PWM_INT_N2 .......... Also see GIRQ 17.13 */\r
- PS2_0_IRQn = 32, /*!< 32 PS2_0 Interrupt ....................... Also see GIRQ 17.14 */\r
- PS2_1_IRQn = 33, /*!< 33 PS2_1 Interrupt ....................... Also see GIRQ 17.15 */\r
- PS2_2_IRQn = 34, /*!< 34 PS2_2 Interrupt ....................... Also see GIRQ 17.16 */\r
- PS2_3_IRQn = 35, /*!< 35 PS2_3 Interrupt ....................... Also see GIRQ 17.17 */\r
- SPI0_TX_IRQn = 36, /*!< 36 SPI0 TX Interrupt ..................... Also see GIRQ 18.0 */\r
- SPI0_RX_IRQn = 37, /*!< 37 SPI0 RX Interrupt ..................... Also see GIRQ 18.1 */\r
- HTIMER_IRQn = 38, /*!< 38 HTIMER Interrupt ...................... Also see GIRQ 17.20 */\r
- KEYSCAN_IRQn = 39, /*!< 39 KSC Interrupt ......................... Also see GIRQ 17.21 */\r
- MAILBOX_DATA_IRQn = 40, /*!< 40 MAILBOX DATA Interrupt ................ Also see GIRQ 15.16 */\r
- RPM_STALL_IRQn = 41, /*!< 41 RPM_INT Stall Interrupt ............... Also see GIRQ 17.23 */\r
- RPM_SPIN_IRQn = 42, /*!< 42 RPM_INT Spin Interrupt ................ Also see GIRQ 17.24 */\r
- PFR_STS_IRQn = 43, /*!< 43 PFR_STS Interrupt ..................... Also see GIRQ 17.25 */\r
- PWM_WDT0_IRQn = 44, /*!< 44 PWM_WDT0 Interrupt .................... Also see GIRQ 17.26 */\r
- PWM_WDT1_IRQn = 45, /*!< 45 PWM_WDT1 Interrupt .................... Also see GIRQ 17.27 */\r
- PWM_WDT2_IRQn = 46, /*!< 46 PWM_WDT2 Interrupt .................... Also see GIRQ 17.28 */\r
- BCM_ERR_IRQn = 47, /*!< 47 BCM_INT Err Interrupt ................. Also see GIRQ 17.29 */\r
- BCM_BUSY_IRQn = 48, /*!< 48 BCM_INT Busy Interrupt ................ Also see GIRQ 17.30 */\r
- TIMER0_IRQn = 49, /*!< 49 TIMER_16_0 Interrupt .................. Also see GIRQ 23.0 */\r
- TIMER1_IRQn = 50, /*!< 50 TIMER_16_1 Interrupt .................. Also see GIRQ 23.1 */\r
- TIMER2_IRQn = 51, /*!< 51 TIMER_16_2 Interrupt .................. Also see GIRQ 23.2 */\r
- TIMER3_IRQn = 52, /*!< 52 TIMER_16_3 Interrupt .................. Also see GIRQ 23.3 */\r
- TIMER4_IRQn = 53, /*!< 53 TIMER_32_0 Interrupt .................. Also see GIRQ 23.4 */\r
- TIMER5_IRQn = 54, /*!< 54 TIMER_32_1 Interrupt .................. Also see GIRQ 23.5 */\r
- SPI1_TX_IRQn = 55, /*!< 55 SPI1 TX Interrupt ..................... Also see GIRQ 18.2 */\r
- SPI1_RX_IRQn = 56, /*!< 56 SPI1 RX Interrupt ..................... Also see GIRQ 18.3 */\r
- GIRQ08_IRQn = 57, /*!< 57 GIRQ08 ................................ Interrupt Aggregator */\r
- GIRQ09_IRQn = 58, /*!< 58 GIRQ09 ................................ Interrupt Aggregator */\r
- GIRQ10_IRQn = 59, /*!< 59 GIRQ10 ................................ Interrupt Aggregator */\r
- GIRQ11_IRQn = 60, /*!< 60 GIRQ11 ................................ Interrupt Aggregator */\r
- GIRQ12_IRQn = 61, /*!< 61 GIRQ12 ................................ Interrupt Aggregator */\r
- GIRQ13_IRQn = 62, /*!< 62 GIRQ13 ................................ Interrupt Aggregator */\r
- GIRQ14_IRQn = 63, /*!< 63 GIRQ14 ................................ Interrupt Aggregator */\r
- GIRQ15_IRQn = 64, /*!< 64 GIRQ15 ................................ Interrupt Aggregator */\r
- GIRQ16_IRQn = 65, /*!< 65 GIRQ16 ................................ Interrupt Aggregator */\r
- GIRQ17_IRQn = 66, /*!< 66 GIRQ17 ................................ Interrupt Aggregator */\r
- GIRQ18_IRQn = 67, /*!< 67 GIRQ18 ................................ Interrupt Aggregator */\r
- GIRQ19_IRQn = 68, /*!< 68 GIRQ19 ................................ Interrupt Aggregator */\r
- GIRQ20_IRQn = 69, /*!< 69 GIRQ20 ................................ Interrupt Aggregator */\r
- GIRQ21_IRQn = 70, /*!< 70 GIRQ21 ................................ Interrupt Aggregator */\r
- GIRQ22_IRQn = 71, /*!< 71 GIRQ22 ................................ Interrupt Aggregator */\r
- GIRQ23_IRQn = 72, /*!< 72 GIRQ23 ................................ Interrupt Aggregator */\r
- DMA8_IRQn = 81, /*!< 81 DMA_CH8 Interrupt ..................... Also see GIRQ 13.24 */\r
- DMA9_IRQn = 82, /*!< 82 DMA_CH9 Interrupt ..................... Also see GIRQ 13.25 */\r
- DMA10_IRQn = 83, /*!< 83 DMA_CH10 Interrupt .................... Also see GIRQ 13.26 */\r
- DMA11_IRQn = 84, /*!< 84 DMA_CH11 Interrupt .................... Also see GIRQ 13.27 */\r
- PWM_WDT3_IRQn = 85, /*!< 85 PWM_WDT3 Interrupt .................... Also see GIRQ 18.4 */\r
- RTC_IRQn = 91, /*!< 91 RTC Interrupt ......................... Also see GIRQ 17.18 */\r
- RTC_ALARM_IRQn = 92, /*!< 92 RTC ALARM Interrupt ................... Also see GIRQ 17.19 */\r
- MAX_IRQn\r
-} IRQn_Type;\r
-\r
-\r
-/** @addtogroup Configuration_of_CMSIS\r
- * @{\r
- */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Processor and Core Peripheral Section ================ */\r
-/* ================================================================================ */\r
-\r
-/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */\r
-#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */\r
-#define __MPU_PRESENT 0 /*!< MPU present or not */\r
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */\r
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
-#define __FPU_PRESENT 1 /*!< FPU present or not */\r
-/** @} */ /* End of group Configuration_of_CMSIS */\r
-\r
-#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */\r
-\r
-/* ================================================================================ */\r
-/* ================ Custom Defines (added manually) ================ */\r
-/* ================================================================================ */\r
-\r
-/* Register Union */\r
-typedef union\r
-{\r
- uint32_t w;\r
- uint16_t h[2];\r
- uint8_t b[4];\r
-} REG32_U;\r
-\r
-/* ================================================================================ */\r
-/* ================ Device Specific Peripheral Section ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/** @addtogroup Device_Peripheral_Registers\r
- * @{\r
- */\r
-\r
-\r
-/* ------------------- Start of section using anonymous unions ------------------ */\r
-#if defined(__CC_ARM)\r
- #pragma push\r
- #pragma anon_unions\r
-#elif defined(__ICCARM__)\r
- #pragma language=extended\r
-#elif defined(__GNUC__)\r
- /* anonymous unions are enabled by default */\r
-#elif defined(__TMS470__)\r
-/* anonymous unions are enabled by default */\r
-#elif defined(__TASKING__)\r
- #pragma warning 586\r
-#else\r
- #warning Not supported compiler type\r
-#endif\r
-\r
-\r
-typedef struct {\r
- union {\r
- __IO uint16_t CR; /*!< MEM_BAR Control [15:0] */\r
- \r
- struct {\r
- __IO uint16_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
- __IO uint16_t FRAME : 6; /*!< Specify a logical device frame number */\r
- uint16_t : 1;\r
- __IO uint16_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
- } CR_b; /*!< BitSize */\r
- };\r
- __IO uint16_t HOST_LO_ADDR; /*!< HOST_ADDRESS[15:0] */\r
- __IO uint16_t HOST_HI_ADDR; /*!< HOST_ADDRESS[31:16] */\r
-} LPC_CONFIG_MEM_BAR_Type;\r
-\r
-typedef struct {\r
- __IO uint32_t SOURCE; /*!< GIRQx Source Register(R/WC) */\r
- __IO uint32_t ENABLE_SET; /*!< GIRQx Enable Set Register (R/WS) */\r
- __I uint32_t RESULT; /*!< GIRQx Result Register */\r
- __IO uint32_t ENABLE_CLEAR; /*!< GIRQx Enable Clear Register. */\r
- __I uint32_t RESERVED;\r
-} INTR_IRQ_Type;\r
-\r
-typedef struct {\r
- union {\r
- __IO uint8_t ACTIVATE; /*!< Enable this channel for operation. */\r
- \r
- struct {\r
- __IO uint8_t EN : 1; /*!< Enable this channel for operation. */\r
- } ACTIVATE_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED1[3];\r
- __IO uint32_t MEM_START_ADDR; /*!< starting address for the Memory device. */\r
- __IO uint32_t MEM_END_ADDR; /*!< ending address for the Memory device. */\r
- __IO uint32_t DEVICE_ADDR; /*!< This is the Master Device address. */\r
- \r
- union {\r
- __IO uint32_t CONTROL; /*!< DMA Channel N Control */\r
- \r
- struct {\r
- __IO uint32_t RUN : 1; /*!< 1= enabled and will service transfer requests */\r
- __I uint32_t REQUEST : 1; /*!< 1= transfer request from the Master Device */\r
- __I uint32_t DONE : 1; /*!< status signal. 1=Channel is done */\r
- __I uint32_t STATUS : 2; /*!< 3: Error,2/1: ext/locally done,0:Disabled */\r
- __IO uint32_t BUSY : 1; /*!< 1=Channel is busy (FSM is not IDLE) */\r
- uint32_t : 2;\r
- __IO uint32_t TX_DIRECTION: 1; /*!< direction of Transfer. 1=Memory to Device */\r
- __IO uint32_t HARDWARE_FLOW_CONTROL_DEVICE: 7;/*!< device as its Hardware Flow Control master. */\r
- __IO uint32_t INCREMENT_MEM_ADDR: 1; /*!< auto-increment DMA Channel Memory Address. */\r
- __IO uint32_t INCREMENT_DEVICE_ADDR: 1; /*!< auto-increment DMA Channel Device Address. */\r
- __IO uint32_t LOCK : 1; /*!< lock the arbitration of Channel Arbiter */\r
- __IO uint32_t DISABLE_HW_FLOW_CONTROL: 1; /*!< Disable the Hardware Flow Control. */\r
- __IO uint32_t TRANSFER_SIZE: 3; /*!< transfer size in Bytes of each Data Packet */\r
- uint32_t : 1;\r
- __IO uint32_t TRANSFER_GO: 1; /*!< Firmware Flow Control DMA transfer. */\r
- __IO uint32_t TRANSFER_ABORT: 1; /*!< abort the current transfer */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint8_t INT_STATUS; /*!< DMA Channel N Interrupt Status */\r
- \r
- struct {\r
- __IO uint8_t BUS_ERROR : 1; /*!< interrupt source. 1: Error detected.(R/WC) */\r
- __IO uint8_t FLOW_CONTROL: 1; /*!< Intr source.1=HW Flow Ctrl is requesting */\r
- __IO uint8_t DONE : 1; /*!< intr source. 1= Start Address equals End */\r
- } INT_STATUS_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED2[3];\r
- \r
- union {\r
- __IO uint8_t INT_EN; /*!< DMA CHANNEL N INTERRUPT ENABLE */\r
- \r
- struct {\r
- __IO uint8_t BUS_ERROR : 1; /*!< 1=enable Interrupt:Status AMBA Bus Error. */\r
- __IO uint8_t FLOW_CONTROL: 1; /*!< 1=enable Interrupt:Status Flow Control Error. */\r
- __IO uint8_t DONE : 1; /*!< 1=enable Interrupt:Status Done.\r
- */\r
- } INT_EN_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED3[7];\r
-} DMA_CH_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PCR ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The Power, Clocks, and Resets (PCR) chapter identifies all the power supplies,\r
- clock sources, and reset inputs to the chip and defines all the derived power, clock, and reset signals. (PCR)\r
- */\r
-\r
-typedef struct { /*!< PCR Structure */\r
- __IO uint32_t CHIP_SLP_EN; /*!< Chip Sleep Enable Register. (MCHP Reserved) */\r
- __I uint32_t CHIP_CLK_REQ_STS; /*!< Chip Clock Required Status. (MCHP Reserved) */\r
- \r
- union {\r
- __IO uint32_t EC_SLP_EN; /*!< EC Sleep Enable Register (EC_SLP_EN) */\r
- \r
- struct {\r
- __IO uint32_t INT_SLP_EN : 1; /*!< INT Sleep Enable (INT_SLP_EN) */\r
- __IO uint32_t PECI_SLP_EN: 1; /*!< PECI Sleep Enable (PECI_SLP_EN) */\r
- __IO uint32_t TACH0_SLP_EN: 1; /*!< TACH0 Sleep Enable (TACH0_SLP_EN) */\r
- uint32_t : 1;\r
- __IO uint32_t PWM0_SLP_EN: 1; /*!< PWM0 Sleep Enable (PWM0_SLP_EN) */\r
- __IO uint32_t PMC_SLP_EN : 1; /*!< PMC Sleep Enable (PMC_SLP_EN) */\r
- __IO uint32_t DMA_SLP_EN : 1; /*!< DMA Sleep Enable (DMA_SLP_EN) */\r
- __IO uint32_t TFDP_SLP_EN: 1; /*!< TFDP Sleep Enable (TFDP_SLP_EN) */\r
- __IO uint32_t PROCESSOR_SLP_EN: 1; /*!< PROCESSOR Sleep Enable (PROCESSOR_SLP_EN) */\r
- __IO uint32_t WDT_SLP_EN : 1; /*!< WDT Sleep Enable (WDT_SLP_EN) */\r
- __IO uint32_t SMB0_SLP_EN: 1; /*!< SMB0 Sleep Enable (SMB0_SLP_EN) */\r
- __IO uint32_t TACH1_SLP_EN: 1; /*!< TACH1 Sleep Enable (TACH1_SLP_EN) */\r
- uint32_t : 8;\r
- __IO uint32_t PWM1_SLP_EN: 1; /*!< PWM1 Sleep Enable (PWM1_SLP_EN) */\r
- __IO uint32_t PWM2_SLP_EN: 1; /*!< PWM2 Sleep Enable (PWM2_SLP_EN) */\r
- __IO uint32_t PWM3_SLP_EN: 1; /*!< PWM3 Sleep Enable (PWM3_SLP_EN) */\r
- uint32_t : 6;\r
- __IO uint32_t EC_REG_BANK_SLP_EN: 1; /*!< EC_REG_BANK Sleep Enable (EC_REG_BANK_SLP_EN) */\r
- __IO uint32_t TIMER16_0_SLP_EN: 1; /*!< TIMER16_0 Sleep Enable (TIMER16_0_SLP_EN) */\r
- __IO uint32_t TIMER16_1_SLP_EN: 1; /*!< TIMER16_1 Sleep Enable (TIMER16_1_SLP_EN) */\r
- } EC_SLP_EN_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __I uint32_t EC_CLK_REQ_STS; /*!< EC Clock Required Status Registers */\r
- \r
- struct {\r
- __I uint32_t INT_CLK_REQ: 1; /*!< INT Clock Required (INT_CLK_REQ) */\r
- __I uint32_t PECI_CLK_REQ: 1; /*!< PECI Clock Required (PECI_CLK_REQ) */\r
- __I uint32_t TACH0_CLK_REQ: 1; /*!< TACH0 Clock Required (TACH0_CLK_REQ) */\r
- uint32_t : 1;\r
- __I uint32_t PWM0_CLK_REQ: 1; /*!< PWM0 Clock Required (PWM0_CLK_REQ) */\r
- __I uint32_t PMC_CLK_REQ: 1; /*!< PMC Clock Required (PMC_CLK_REQ) */\r
- __I uint32_t DMA_CLK_REQ: 1; /*!< DMA Clock Required (DMA_CLK_REQ) */\r
- __I uint32_t TFDP_CLK_REQ: 1; /*!< TFDP Clock Required (TFDP_CLK_REQ) */\r
- __I uint32_t PROCESSOR_CLK_REQ: 1; /*!< PROCESSOR Clock Required (PROCESSOR_CLK_REQ) */\r
- __I uint32_t WDT_CLK_REQ: 1; /*!< WDT Clock Required (WDT_CLK_REQ) */\r
- __I uint32_t SMB0_CLK_REQ: 1; /*!< SMB0 Clock Required (SMB0_CLK_REQ) */\r
- __I uint32_t TACH1_CLK_REQ: 1; /*!< TACH1 Clock Required (TACH1_CLK_REQ) */\r
- uint32_t : 8;\r
- __I uint32_t PWM1_CLK_REQ: 1; /*!< PWM1 Clock Required (PWM1_CLK_REQ) */\r
- __I uint32_t PWM2_CLK_REQ: 1; /*!< PWM2 Clock Required (PWM2_CLK_REQ) */\r
- __I uint32_t PWM3_CLK_REQ: 1; /*!< PWM3 Clock Required (PWM3_CLK_REQ) */\r
- uint32_t : 6;\r
- __I uint32_t EC_REG_BANK_CLK_REQ: 1; /*!< EC_REG_BANK Clock Required (EC_REG_BANK_CLK_REQ) */\r
- __I uint32_t TIMER16_0_CLK_REQ: 1; /*!< TIMER16_0 Clock Required (TIMER16_0_CLK_REQ) */\r
- __I uint32_t TIMER16_1_CLK_REQ: 1; /*!< TIMER16_1 Clock Required (TIMER16_1_CLK_REQ) */\r
- } EC_CLK_REQ_STS_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t HOST_SLP_EN; /*!< Host Sleep Enable Register (HOST_SLP_EN) */\r
- \r
- struct {\r
- __IO uint32_t LPC_SLP_EN : 1; /*!< LPC Sleep Enable (LPC_SLP_EN) */\r
- __IO uint32_t UART_0_SLP_EN: 1; /*!< UART 0 Sleep Enable (UART_0_SLP_EN) */\r
- uint32_t : 10;\r
- __IO uint32_t GLBL_CFG_SLP_EN: 1; /*!< GLBL_CFG (GLBL_CFG_SLP_EN) */\r
- __IO uint32_t ACPI_EC_0_SLP_EN: 1; /*!< ACPI EC 0 Sleep Enable (ACPI_EC_0_SLP_EN) */\r
- __IO uint32_t ACPI_EC_1_SLP_EN: 1; /*!< ACPI EC 1 Sleep Enable (ACPI_EC_1_SLP_EN) */\r
- __IO uint32_t ACPI_PM1_SLP_EN: 1; /*!< ACPI PM1 Sleep Enable (ACPI_PM1_SLP_EN) */\r
- __IO uint32_t KBCEM_SLP_EN: 1; /*!< 8042EM Sleep Enable (8042EM_SLP_EN) */\r
- uint32_t : 1;\r
- __IO uint32_t RTC_SLP_EN : 1; /*!< RTC Sleep Enable (RTC_SLP_EN) */\r
- } HOST_SLP_EN_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __I uint32_t HOST_CLK_REQ; /*!< Host Clock Required Status Registers */\r
- \r
- struct {\r
- __I uint32_t LPC_CLK_REQ: 1; /*!< LPC Clock Required (LPC_CLK_REQ) */\r
- __I uint32_t UART_0_CLK_REQ: 1; /*!< UART 0 Clock Required (UART_0_CLK_REQ) */\r
- uint32_t : 10;\r
- __I uint32_t GLBL_CFG_CLK_REQ: 1; /*!< GLBL_CFG Clock Required (GLBL_CFG_CLK_REQ) */\r
- __I uint32_t ACPI_EC_0_CLK_REQ: 1; /*!< ACPI EC 0 Clock Required (ACPI_EC_0_CLK_REQ) */\r
- __I uint32_t ACPI_EC_1_CLK_REQ: 1; /*!< ACPI EC 1 Clock Required (ACPI_EC_1_CLK_REQ) */\r
- __I uint32_t ACPI_PM1_CLK_REQ: 1; /*!< ACPI PM1 Clock Required (ACPI_PM1_CLK_REQ) */\r
- __I uint32_t KBCEM_CLK_REQ: 1; /*!< 8042EM Clock Required (8042EM_CLK_REQ) */\r
- uint32_t : 1;\r
- __I uint32_t RTC_CLK_REQ: 1; /*!< RTC Clock Required (RTC_CLK_REQ) */\r
- } HOST_CLK_REQ_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t SYS_SLP_CNTRL; /*!< System Sleep Control Register */\r
- \r
- struct {\r
- __IO uint32_t ROSC_PD : 1; /*!< Ring oscillator power down (ROSC_PD) */\r
- __IO uint32_t ROSC_GATE : 1; /*!< Ring oscillator output gate (ROSC_GATE) */\r
- __IO uint32_t REGULATOR_STDBY: 1; /*!< Core regulator standby */\r
- } SYS_SLP_CNTRL_b; /*!< BitSize */\r
- };\r
- __I uint32_t RESERVED;\r
- __IO uint32_t PROC_CLK_CNTRL; /*!< Processor Clock Control Register (PROC_CLK_CNTRL) [7:0] Processor\r
- Clock Divide Value (PROC_DIV)\r
- 1: divide 48 MHz Ring Oscillator by 1.\r
- 4: divide 48 MHz Ring Oscillator by 4.(default)\r
- 16: divide 48 MHz Ring Oscillator by 16.\r
- 48: divide 48 MHz Ring Oscillator by 48.\r
- No other values are supported \r
- --------------------------------------------------------- */\r
- \r
- union {\r
- __IO uint32_t EC_SLP_EN2; /*!< EC Sleep Enable 2 Register (EC_SLP_EN2) */\r
- \r
- struct {\r
- uint32_t : 3;\r
- __IO uint32_t ADC_SLP_EN : 1; /*!< ADC Sleep Enable (ADC_SLP_EN) */\r
- uint32_t : 1;\r
- __IO uint32_t PS2_0_SLP_EN: 1; /*!< PS2_0 Sleep Enable (PS2_0_SLP_EN) */\r
- __IO uint32_t PS2_1_SLP_EN: 1; /*!< PS2_1 Sleep Enable (PS2_1_SLP_EN) */\r
- __IO uint32_t PS2_2_SLP_EN: 1; /*!< PS2_2 Sleep Enable (PS2_2_SLP_EN) */\r
- __IO uint32_t PS2_3_SLP_EN: 1; /*!< PS2_3 Sleep Enable (PS2_3_SLP_EN) */\r
- __IO uint32_t SPI0_SLP_EN: 1; /*!< SPI0 Sleep Enable (SPI0_SLP_EN) */\r
- __IO uint32_t HTIMER_SLP_EN: 1; /*!< HTIMER Sleep Enable (HTIMER_SLP_EN) */\r
- __IO uint32_t KEYSCAN_SLP_EN: 1; /*!< KEYSCAN Sleep Enable (KEYSCAN_SLP_EN) */\r
- __IO uint32_t RPMPWM_SLP_EN: 1; /*!< RPM-PWM Sleep Enable (RPMPWM_SLP_EN) */\r
- __IO uint32_t SMB1_SLP_EN: 1; /*!< SMB1 Sleep Enable (SMB1_SLP_EN) */\r
- __IO uint32_t SMB2_SLP_EN: 1; /*!< SMB2 Sleep Enable (SMB2_SLP_EN) */\r
- __IO uint32_t SMB3_SLP_EN: 1; /*!< SMB3 Sleep Enable (SMB3_SLP_EN) */\r
- __IO uint32_t LED0_SLP_EN: 1; /*!< LED0 Sleep Enable (LED0_SLP_EN) */\r
- __IO uint32_t LED1_SLP_EN: 1; /*!< LED1 Sleep Enable (LED1_SLP_EN) */\r
- __IO uint32_t LED2_SLP_EN: 1; /*!< LED2 Sleep Enable (LED2_SLP_EN) */\r
- __IO uint32_t BCM_SLP_EN : 1; /*!< BCM Sleep Enable (BCM_SLP_EN) */\r
- __IO uint32_t SPI1_SLP_EN: 1; /*!< SPI1 Sleep Enable (SPI1_SLP_EN) */\r
- __IO uint32_t TIMER16_2_SLP_EN: 1; /*!< TIMER16_2_Sleep Enable (TIMER16_2_SLP_EN) */\r
- __IO uint32_t TIMER16_3_SLP_EN: 1; /*!< TIMER16_3 Sleep Enable (TIMER16_3_SLP_EN) */\r
- __IO uint32_t TIMER32_0_SLP_EN: 1; /*!< TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN) */\r
- __IO uint32_t TIMER32_1_SLP_EN: 1; /*!< TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN) */\r
- __IO uint32_t LED3_SLP_EN: 1; /*!< LED3 Sleep Enable (LED3_SLP_EN) */\r
- } EC_SLP_EN2_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __I uint32_t EC_CLK_REQ2_STS; /*!< EC Clock Required 2 Status Register */\r
- \r
- struct {\r
- uint32_t : 3;\r
- __I uint32_t ADC_CLK_REQ: 1; /*!< ADC Clock Required (ADC_CLK_REQ) */\r
- uint32_t : 1;\r
- __I uint32_t PS2_0_SLP_CLK_REQ: 1; /*!< PS2_0 Clock Required (PS2_0_SLP_CLK_REQ) */\r
- __I uint32_t PS2_1_SLP_CLK_REQ: 1; /*!< PS2_1 Clock Required (PS2_1_SLP_CLK_REQ) */\r
- __I uint32_t PS2_2_SLP_CLK_REQ: 1; /*!< PS2_2 Clock Required (PS2_2_SLP_CLK_REQ) */\r
- __I uint32_t PS2_3_SLP_CLK_REQ: 1; /*!< PS2_3 Clock Required (PS2_3_SLP_CLK_REQ) */\r
- __I uint32_t SPI0_SLP_CLK_REQ: 1; /*!< SPI0 Clock Required (SPI0_SLP_CLK_REQ) */\r
- __I uint32_t HTIMER_SLP_CLK_REQ: 1; /*!< HTIMER Clock Required (HTIMER_SLP_CLK_REQ) */\r
- __I uint32_t KEYSCAN_SLP_CLK_REQ: 1; /*!< KEYSCAN Clock Required (KEYSCAN_SLP_CLK_REQ) */\r
- __I uint32_t RPMPWM_SLP_CLK_REQ: 1; /*!< RPM-PWM Clock Required (RPMPWM_SLP_CLK_REQ) */\r
- __I uint32_t SMB1_SLP_CLK_REQ: 1; /*!< SMB1 Clock Required (SMB1_SLP_CLK_REQ) */\r
- __I uint32_t SMB2_SLP_CLK_REQ: 1; /*!< SMB2 Clock Required (SMB2_SLP_CLK_REQ) */\r
- __I uint32_t SMB3_SLP_CLK_REQ: 1; /*!< SMB3 Clock Required (SMB3_SLP_CLK_REQ) */\r
- __I uint32_t LED0_SLP_CLK_REQ: 1; /*!< LED0 Clock Required (LED0_SLP_CLK_REQ) */\r
- __I uint32_t LED1_SLP_CLK_REQ: 1; /*!< LED1 Clock Required (LED1_SLP_CLK_REQ) */\r
- __I uint32_t LED2_SLP_CLK_REQ: 1; /*!< LED2 Clock Required (LED2_SLP_CLK_REQ) */\r
- __I uint32_t BCM_SLP_CLK_REQ: 1; /*!< BCM Clock Required (BCM_SLP_CLK_REQ) */\r
- __I uint32_t SPI1_SLP_CLK_REQ: 1; /*!< SPI1 Clock Required (SPI1_SLP_CLK_REQ) */\r
- __I uint32_t TIMER16_2_SLP_CLK_REQ: 1; /*!< TIMER16_2_Clock Required (TIMER16_2_SLP_CLK_REQ) */\r
- __I uint32_t TIMER16_3_SLP_CLK_REQ: 1; /*!< TIMER16_3 Clock Required (TIMER16_3_SLP_CLK_REQ) */\r
- __I uint32_t TIMER32_0_SLP_CLK_REQ: 1; /*!< TIMER32_0 Clock Required (TIMER32_0_SLP_CLK_REQ) */\r
- __I uint32_t TIMER32_1_SLP_CLK_REQ: 1; /*!< TIMER32_1 Clock Required (TIMER32_1_SLP_CLK_REQ) */\r
- __I uint32_t LED3_SLP_CLK_REQ: 1; /*!< LED3 Clock Required (LED3_SLP_CLK_REQ) */\r
- } EC_CLK_REQ2_STS_b; /*!< BitSize */\r
- };\r
- __IO uint32_t SLOW_CLK_CNTRL; /*!< Slow Clock Control Register (SLOW_CLK_CNTRL) Slow Clock (100\r
- kHz) Divide Value (slow_div) Configures the 100kHz_Clk.\r
- 0: Clock off \r
- n: divide by n.\r
- Note: The default setting is for 100 kHz. \r
- --------------------------------------------------------- */\r
- \r
- union {\r
- __I uint32_t CHIP_OSC_ID; /*!< Oscillator ID Register (CHIP_OSC_ID) */\r
- \r
- struct {\r
- uint32_t : 8;\r
- __I uint32_t OSC_LOCK : 1; /*!< OSC_LOCK (OSC_LOCK) */\r
- } CHIP_OSC_ID_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t CHIP_PWR_RST_STS; /*!< PCR chip sub-system power reset status */\r
- \r
- struct {\r
- uint32_t : 2;\r
- __I uint32_t VCC_nRST : 1; /*!< 0=active, 1=not active (PWRGD asserted). */\r
- __I uint32_t SIO_nRST : 1; /*!< nSIO_RESET. 0=active, 1=not active. */\r
- uint32_t : 1;\r
- __IO uint32_t VBAT_RST : 1; /*!< VBAT: 0=No reset, 1=reset occurred.(R/WC) */\r
- __IO uint32_t VCC1_RST : 1; /*!< VCC1: 0=No reset, 1=reset occurred.(R/WC) */\r
- uint32_t : 3;\r
- __I uint32_t _32K_ACTIVE: 1; /*!< 32K_ACTIVE (32K_ACTIVE) */\r
- __I uint32_t PCICLK_ACTIVE: 1; /*!< PCICLK_ACTIVE (PCICLK_ACTIVE) */\r
- } CHIP_PWR_RST_STS_b; /*!< BitSize */\r
- };\r
- __IO uint32_t CHIP_RST_EN; /*!< Chip Reset Enable (MCHP Reserved) */\r
- \r
- union {\r
- __IO uint32_t HOST_RST_EN; /*!< Host Reset Enable Register */\r
- \r
- struct {\r
- __IO uint32_t LPC_RST_EN : 1; /*!< LPC Reset Enable (LPC_RST_EN) */\r
- __IO uint32_t UART_0_RST_EN: 1; /*!< UART 0 Reset Enable */\r
- uint32_t : 10;\r
- __IO uint32_t GLBL_CFG_RST_EN: 1; /*!< GLBL_CFG Reset Enable */\r
- __IO uint32_t ACPI_EC_0_RST_EN: 1; /*!< ACPI EC 0 Reset Enable */\r
- __IO uint32_t ACPI_EC_1_RST_EN: 1; /*!< ACPI EC 1 Reset Enable */\r
- __IO uint32_t ACPI_PM1_RST_EN: 1; /*!< ACPI PM1 Reset Enable */\r
- __IO uint32_t KBCEM_RST_EN: 1; /*!< 8042EM Reset Enable */\r
- uint32_t : 1;\r
- __IO uint32_t RTC_RST_EN : 1; /*!< RTC Reset Enable (RTC_RST_EN) */\r
- } HOST_RST_EN_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t EC_RST_EN; /*!< EC Reset Enable Register */\r
- \r
- struct {\r
- __IO uint32_t INT_RST_EN : 1; /*!< INT Reset Enable (INT_RST_EN) */\r
- __IO uint32_t PECI_RST_EN: 1; /*!< PECI Reset Enable (PECI_RST_EN) */\r
- __IO uint32_t TACH0_RST_EN: 1; /*!< TACH0 Reset Enable (TACH0_RST_EN) */\r
- uint32_t : 1;\r
- __IO uint32_t PWM0_RST_EN: 1; /*!< PWM0 Reset Enable (PWM0_RST_EN) */\r
- __IO uint32_t PMC_RST_EN : 1; /*!< PMC Reset Enable (PMC_RST_EN) */\r
- __IO uint32_t DMA_RST_EN : 1; /*!< DMA Reset Enable (DMA_RST_EN) */\r
- __IO uint32_t TFDP_RST_EN: 1; /*!< TFDP Reset Enable (TFDP_RST_EN) */\r
- __IO uint32_t PROCESSOR_RST_EN: 1; /*!< PROCESSOR Sleep Enable (PROCESSOR_RST_EN) */\r
- __IO uint32_t WDT_RST_EN : 1; /*!< WDT Reset Enable (WDT_RST_EN) */\r
- __IO uint32_t SMB0_RST_EN: 1; /*!< SMB0 Reset Enable (SMB0_RST_EN) */\r
- __IO uint32_t TACH1_RST_EN: 1; /*!< TACH1 Reset Enable (TACH1_RST_EN) */\r
- uint32_t : 8;\r
- __IO uint32_t PWM1_RST_EN: 1; /*!< PWM1 Reset Enable (PWM1_RST_EN) */\r
- __IO uint32_t PWM2_RST_EN: 1; /*!< PWM2 Reset Enable (PWM2_RST_EN) */\r
- __IO uint32_t PWM3_RST_EN: 1; /*!< PWM3 Reset Enable (PWM3_RST_EN) */\r
- uint32_t : 6;\r
- __IO uint32_t EC_REG_BANK_RST_EN: 1; /*!< EC_REG_BANK Reset Enable (EC_REG_BANK_RST_EN) */\r
- __IO uint32_t TIMER16_0_RST_EN: 1; /*!< TIMER16_0 Reset Enable (TIMER16_0_RST_EN) */\r
- __IO uint32_t TIMER16_1_RST_EN: 1; /*!< TIMER16_1 Reset Enable (TIMER16_1_RST_EN) */\r
- } EC_RST_EN_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t EC_RST_EN2; /*!< EC Reset Enable 2 Register */\r
- \r
- struct {\r
- uint32_t : 3;\r
- __IO uint32_t ADC_RST_EN : 1; /*!< ADC Reset Enable (ADC_RST_EN) */\r
- uint32_t : 1;\r
- __IO uint32_t PS2_0_RST_EN: 1; /*!< PS2_0 Reset Enable (PS2_0_RST_EN) */\r
- __IO uint32_t PS2_1_RST_EN: 1; /*!< PS2_1 Reset Enable (PS2_1_RST_EN) */\r
- __IO uint32_t PS2_2_RST_EN: 1; /*!< PS2_2 Reset Enable (PS2_2_RST_EN) */\r
- __IO uint32_t PS2_3_RST_EN: 1; /*!< PS2_3 Reset Enable (PS2_3_RST_EN) */\r
- __IO uint32_t SPI0_SLP_EN: 1; /*!< SPI0 Reset Enable (SPI0_SLP_EN) */\r
- __IO uint32_t HTIMER_RST_EN: 1; /*!< HTIMER Reset Enable (HTIMER_RST_EN) */\r
- __IO uint32_t KEYSCAN_RST_EN: 1; /*!< KEYSCAN Reset Enable (KEYSCAN_RST_EN) */\r
- __IO uint32_t RPMPWM_RST_EN: 1; /*!< RPM-PWM Reset Enable (RPMPWM_RST_EN) */\r
- __IO uint32_t SMB1_RST_EN: 1; /*!< SMB1 Reset Enable (SMB1_RST_EN) */\r
- __IO uint32_t SMB2_RST_EN: 1; /*!< SMB2 Reset Enable (SMB2_RST_EN) */\r
- __IO uint32_t SMB3_RST_EN: 1; /*!< SMB3 Reset Enable (SMB3_RST_EN) */\r
- __IO uint32_t LED0_RST_EN: 1; /*!< LED0 Reset Enable (LED0_RST_EN) */\r
- __IO uint32_t LED1_RST_EN: 1; /*!< LED1 Reset Enable (LED1_RST_EN) */\r
- __IO uint32_t LED2_RST_EN: 1; /*!< LED2 Reset Enable (LED2_RST_EN) */\r
- __IO uint32_t BCM_RST_EN : 1; /*!< BCM Reset Enable (BCM_RST_EN) */\r
- __IO uint32_t SPI1_RST_EN: 1; /*!< SPI1 Reset Enable (SPI1_RST_EN) */\r
- __IO uint32_t TIMER16_2_RST_EN: 1; /*!< TIMER16_2_Reset Enable (TIMER16_2_RST_EN) */\r
- __IO uint32_t TIMER16_3_RST_EN: 1; /*!< TIMER16_3 Reset Enable (TIMER16_3_RST_EN) */\r
- __IO uint32_t TIMER32_0_RST_EN: 1; /*!< TIMER32_0 Reset Enable (TIMER32_0_RST_EN) */\r
- __IO uint32_t TIMER32_1_RST_EN: 1; /*!< TIMER32_1 Reset Enable (TIMER32_1_RST_EN) */\r
- __IO uint32_t LED3_RST_EN: 1; /*!< LED3 Reset Enable (LED3_RST_EN) */\r
- } EC_RST_EN2_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t PWR_RST_CTRL; /*!< Power Reset Control (PWR_RST_CTRL) Register */\r
- \r
- struct {\r
- __IO uint32_t IRESET_OUT : 1; /*!< iRESET_OUT (IRESET_OUT) */\r
- } PWR_RST_CTRL_b; /*!< BitSize */\r
- };\r
-} PCR_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ VBAT ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The VBAT Register Bank block is a block implemented for aggregating miscellaneous battery-backed registers \r
- required the host and by the Embedded Controller (EC) Subsystem that are not unique to a block implemented in the EC subsystem.\r
- The VBAT Powered RAM provides a 64 Byte Random Accessed Memory that is operational while the main power rail is operational, \r
- and will retain its values powered by battery power while the main rail is unpowered. (VBAT)\r
- */\r
-\r
-typedef struct { /*!< VBAT Structure */\r
- \r
- union {\r
- __IO uint8_t PFR_STS; /*!< Power-Fail and Reset Status Register */\r
- \r
- struct {\r
- __I uint8_t DET32K_IN : 1; /*!< XTAL[1:2] 0=No clock, 1= Clock detected */\r
- uint8_t : 4;\r
- __IO uint8_t WDT : 1; /*!< 1=Watch-Dog Timer Forced Reset (R/WC). */\r
- uint8_t : 1;\r
- __IO uint8_t VBAT_RST : 1; /*!< 1=VBAT_POR is detected.(R/WC) */\r
- } PFR_STS_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED[7];\r
- \r
- union {\r
- __IO uint32_t CLOCK_EN; /*!< CLOCK ENABLE Control */\r
- \r
- struct {\r
- __IO uint32_t XOSEL : 1; /*!< 32KHz, 1=single-ended, 0=crystal (default). */\r
- __IO uint32_t _32K_EN : 1; /*!< 1=32K_ON, 0=OFF (VBAT_POR default) */\r
- } CLOCK_EN_b; /*!< BitSize */\r
- };\r
-} VBAT_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ LPC ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Section 5.10, "EC-Only Registers"and Section 5.11, "Runtime Registers". (LPC)\r
- */\r
-\r
-typedef struct { /*!< LPC Structure */\r
- __IO uint8_t INDEX; /*!< A pointer to a Configuration Reg. Address. */\r
- __IO uint8_t DATA_REG; /*!< To rd/wt data with the INDEX Register. */\r
- __I uint16_t RESERVED[129];\r
- \r
- union {\r
- __I uint32_t BUS_MONITOR; /*!< LPC BUS MONITOR REGISTER */\r
- \r
- struct {\r
- uint32_t : 1;\r
- __I uint32_t LRESET_STATUS: 1; /*!< Reflects the inverse state of LRESET# pin. */\r
- } BUS_MONITOR_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t HOST_BUS_ERROR; /*!< Host Bus Error Register */\r
- \r
- struct {\r
- __IO uint32_t LPC_ERR : 1; /*!< A BAR conflict or an internal bus error. (R/WC) */\r
- __IO uint32_t EN_ERR : 1; /*!< Internal bus errors. (R/WC) */\r
- __IO uint32_t BAR_ERR : 1; /*!< a BAR conflict occurs on an LPC address. (R/WC) */\r
- __IO uint32_t RUNTIME_ERR: 1; /*!< A BAR is misconfigured. (R/WC) */\r
- __IO uint32_t CONFIG_ERR : 1; /*!< LPC Config access causes a bus error.(R/WC) */\r
- __IO uint32_t DMA_ERR : 1; /*!< LPC DMA access causes a bus error. (R/WC) */\r
- uint32_t : 2;\r
- __I uint32_t ERR_ADDR : 24; /*!< 24-bit internal addr. of LPC transaction */\r
- } HOST_BUS_ERROR_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t EC_SERIRQ; /*!< the interrupt source of EC SERIRQ */\r
- \r
- struct {\r
- __IO uint32_t EC_IRQ : 1; /*!< interrupt source of a LPC Logical Device */\r
- } EC_SERIRQ_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t CLK_CTRL; /*!< Controls throughput of LPC transactions. */\r
- \r
- struct {\r
- __IO uint32_t CR : 2; /*!< controls ring oscillator to be shut down. */\r
- __IO uint32_t HANDSHAKE : 1; /*!< controls throughput of LPC transactions. */\r
- } CLK_CTRL_b; /*!< BitSize */\r
- };\r
- __I uint32_t RESERVED1[3];\r
- __IO uint32_t BAR_INHIBIT; /*!< The BAR for Logical Device i is disabled */\r
- __I uint32_t RESERVED2[3];\r
- __IO uint32_t BAR_INIT; /*!< Init value of LPC BAR at offset 60h on nSIO_RESET. */\r
-} LPC_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ LPC_CONFIG ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief LPC Configuration Registers. See Section 5.9 (LPC_CONFIG)\r
- */\r
-\r
-typedef struct { /*!< LPC_CONFIG Structure */\r
- __I uint32_t RESERVED[12];\r
- __IO uint8_t ACTIVATE; /*!< 1=LPC Logical Device is powered/functional */\r
- __I uint8_t RESERVED1[15];\r
- \r
- union {\r
- __IO uint8_t SIRQ[16]; /*!< 16 SIRQ channels */\r
- \r
- struct {\r
- __IO uint8_t FRAME : 6; /*!< Six bits select the Logical Device. */\r
- __IO uint8_t DEVICE : 1; /*!< Set to 0 in order to enable a SERIRQ. */\r
- __IO uint8_t SELECT : 1; /*!< 1: 1st LD's intr is selected,0: 2nd intr. */\r
- } SIRQ_b[16]; /*!< BitSize */\r
- };\r
- __I uint32_t RESERVED2[4];\r
- \r
- union {\r
- __IO uint32_t LPC_BAR; /*!< LPC Interface BAR Register */\r
- \r
- struct {\r
- __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
- __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
- __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
- __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
- __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
- } LPC_BAR_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t EM_BAR; /*!< EM Interface 0 BAR */\r
- \r
- struct {\r
- __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
- __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
- __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
- __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
- __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
- } EM_BAR_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t UART_BAR; /*!< UART 0 BAR Register */\r
- \r
- struct {\r
- __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
- __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
- __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
- __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
- __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
- } UART_BAR_b; /*!< BitSize */\r
- };\r
- __I uint32_t RESERVED3[3];\r
- \r
- union {\r
- __IO uint32_t KBC_BAR; /*!< Keyboard Controller (8042) BAR */\r
- \r
- struct {\r
- __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
- __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
- __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
- __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
- __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
- } KBC_BAR_b; /*!< BitSize */\r
- };\r
- __I uint32_t RESERVED4[3];\r
- \r
- union {\r
- __IO uint32_t EC0_BAR; /*!< ACPI EC Interface 0 BAR */\r
- \r
- struct {\r
- __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
- __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
- __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
- __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
- __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
- } EC0_BAR_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t EC1_BAR; /*!< ACPI EC Interface 1 BAR */\r
- \r
- struct {\r
- __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
- __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
- __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
- __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
- __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
- } EC1_BAR_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t PM1_BAR; /*!< ACPI PM1 Interface BAR */\r
- \r
- struct {\r
- __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
- __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
- __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
- __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
- __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
- } PM1_BAR_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t LGC_BAR; /*!< Legacy (GATEA20) Interface BAR */\r
- \r
- struct {\r
- __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
- __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
- __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
- __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
- __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
- } LGC_BAR_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t MBX_BAR; /*!< Mailbox Registers Interface BAR */\r
- \r
- struct {\r
- __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
- __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
- __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
- __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
- __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
- } MBX_BAR_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t RTC_BAR; /*!< RTC Registers Interface BAR */\r
- \r
- struct {\r
- __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
- __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
- __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
- __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
- __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
- } RTC_BAR_b; /*!< BitSize */\r
- };\r
- __I uint32_t RESERVED5[8];\r
- \r
- union {\r
- LPC_CONFIG_MEM_BAR_Type MBX_MEM_BAR; /*!< Mailbox Registers I/F Memory BAR */\r
- LPC_CONFIG_MEM_BAR_Type MEM_BAR; /*!< Mailbox Registers I/F Memory BAR */\r
- };\r
- LPC_CONFIG_MEM_BAR_Type EC0_MEM_BAR; /*!< ACPI EC Interface 0 Memory BAR */\r
- LPC_CONFIG_MEM_BAR_Type EC1_MEM_BAR; /*!< ACPI EC Interface 1 Memory BAR */\r
- LPC_CONFIG_MEM_BAR_Type EMI_MEM_BAR; /*!< EM Interface 0 Memory BAR */\r
-} LPC_CONFIG_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ GCR ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The Logical Device Configuration registers support motherboard designs in which the resources required \r
- by their components are known and assigned by the BIOS at POST. (GCR)\r
- */\r
-\r
-typedef struct { /*!< GCR Structure */\r
- __I uint8_t RESERVED[7];\r
- __IO uint8_t LOGICAL_DEVICE_NUMBER; /*!< Selects the current logical device. */\r
- __I uint32_t RESERVED1[6];\r
- __I uint8_t DEVICE_ID; /*!< provides device identification. */\r
- __I uint8_t DEVICE_REVISION; /*!< provides device revision information. */\r
-} GCR_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ EMI ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The Embedded Memory Interface (EMI) provides a standard run-time mechanism for the system host \r
- to communicate with the Embedded Controller (EC) and other logical components. (EMI)\r
- */\r
-\r
-typedef struct { /*!< EMI Structure */\r
- __IO uint8_t HOST_EC_MBX; /*!< Host-to-EC Mailbox Register */\r
- __IO uint8_t EC_HOST_MBX; /*!< EC-to-Host Mailbox Register (R/WC) */\r
- \r
- union {\r
- __IO uint16_t EC_ADDRESS; /*!< EC Address Access Control Register */\r
- \r
- struct {\r
- __IO uint16_t ACCESS_TYPE: 2; /*!< defines the type of EC Data rd/wt access */\r
- __IO uint16_t EC_ADDRESS : 13; /*!< defines bits[14:2] of EC_Address [15:0]. */\r
- __IO uint16_t REGION : 1; /*!< Selector of two segments. */\r
- } EC_ADDRESS_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t EC_DATA; /*!< EC Data Register */\r
- __IO uint8_t EC_DATA_BYTE[4]; /*!< EC Data Byte Register */\r
- };\r
- \r
- union {\r
- __IO uint16_t EC_SWI; /*!< Notification of EC Software Interrupt */\r
- \r
- struct {\r
- __I uint16_t EC_WR : 1; /*!< EC Mailbox Write. */\r
- __IO uint16_t NOTIFICATION: 15; /*!< EC to notify the host of an event(R/WC) */\r
- } EC_SWI_b; /*!< BitSize */\r
- };\r
- __IO uint16_t EC_SWI_EN; /*!< [15:1] enables generation of Event interrupts */\r
- __IO uint8_t APPLICATION_ID; /*!< Application ID Register */\r
- __I uint8_t RESERVED[243];\r
- __IO uint8_t HOST2EC_MBX; /*!< Host-to-EC Mailbox Register(R/WC) */\r
- __IO uint8_t EC2HOST_MBX; /*!< EC-to-Host Mailbox Register */\r
- __I uint16_t RESERVED1;\r
- __IO uint32_t MEMORY_BASE_ADDRESS_0; /*!< [31:2] defines the beginning of region 0 */\r
- __IO uint16_t MEMORY_READ_LIMIT_0; /*!< [14:2]Memory Read Limit 0 Register */\r
- __IO uint16_t MEMORY_WRITE_LIMIT_0; /*!< [14:2] Memory Write Limit 0 Register */\r
- __IO uint32_t MEMORY_BASE_ADDRESS_1; /*!< [31:2] defines the beginning of region 1 */\r
- __IO uint16_t MEMORY_READ_LIMIT_1; /*!< [14:2]Memory Read Limit 1 Register */\r
- __IO uint16_t MEMORY_WRITE_LIMIT_1; /*!< [14:2] Memory Write Limit 1 Register */\r
- __IO uint16_t EC_SWI_SET; /*!< [15:1] Interrupt Set Register */\r
- __IO uint16_t EC_SWI_CLR; /*!< [15:1] Host Clear Enable Register */\r
-} EMI_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ ACPI_EC0 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The ACPI Embedded Controller Interface (ACPI-ECI) provides a four byte full duplex data interface \r
- which is a superset of the standard ACPI Embedded Controller Interface (ACPI-ECI) one byte data interface. The\r
- ACPI Embedded Controller Interface (ACPI-ECI) defaults to the standard one byte interface. (ACPI_EC0)\r
- */\r
-\r
-typedef struct { /*!< ACPI_EC0 Structure */\r
- \r
- union {\r
- __IO uint32_t OS_DATA; /*!< ACPI OS Data Register */\r
- __IO uint8_t OS_DATA_BYTE[4]; /*!< aliased to the OS2EC DATA BYTES[n]. */\r
- };\r
- \r
- union {\r
- union {\r
- __I uint8_t OS_STATUS; /*!< aliased to the EC STATUS Register */\r
- \r
- struct {\r
- __I uint8_t OBF : 1; /*!< Output Buffer Full bit */\r
- __I uint8_t IBF : 1; /*!< Input Buffer Full bit */\r
- __I uint8_t UD1B : 1; /*!< User Defined */\r
- __I uint8_t CMD : 1; /*!< OS2EC Data contains a command byte */\r
- __I uint8_t BURST : 1; /*!< set when the ACPI_EC is in Burst Mode */\r
- __I uint8_t SCI_EVT : 1; /*!< set when an SCI event is pending */\r
- __I uint8_t SMI_EVT : 1; /*!< set when an SMI event is pending */\r
- __I uint8_t UD0B : 1; /*!< User Defined */\r
- } OS_STATUS_b; /*!< BitSize */\r
- };\r
- __O uint8_t OS_COMMAND; /*!< aliased to the OS2EC Data Byte0 */\r
- };\r
- __I uint8_t OS_BYTE_CONTROL; /*!< OS Control [0:0] FOUR_BYTE_ACCESS */\r
- __I uint16_t RESERVED[125];\r
- \r
- union {\r
- __IO uint32_t EC2OS_DATA; /*!< EC2OS Data */\r
- __IO uint8_t EC2OS_DATA_BYTE[4]; /*!< EC2OS Data Bytes */\r
- };\r
- \r
- union {\r
- __IO uint8_t EC_STATUS; /*!< EC STATUS */\r
- \r
- struct {\r
- __I uint8_t OBF : 1; /*!< Output Buffer Full bit */\r
- __I uint8_t IBF : 1; /*!< Input Buffer Full bit */\r
- __I uint8_t UD1A : 1; /*!< User Defined */\r
- __I uint8_t CMD : 1; /*!< OS2EC Data contains a command byte */\r
- __IO uint8_t BURST : 1; /*!< set when the ACPI_EC is in Burst Mode */\r
- __IO uint8_t SCI_EVT : 1; /*!< set when an SCI event is pending */\r
- __IO uint8_t SMI_EVT : 1; /*!< set when an SMI event is pending */\r
- __IO uint8_t UD0A : 1; /*!< User Defined */\r
- } EC_STATUS_b; /*!< BitSize */\r
- };\r
- __IO uint8_t EC_BYTE_CONTROL; /*!< OS Control [0:0] FOUR_BYTE_ACCESS */\r
- __I uint16_t RESERVED1;\r
- \r
- union {\r
- __IO uint32_t OS2EC_DATA; /*!< OS2EC Data EC-Register */\r
- __IO uint8_t OS2EC_DATA_BYTE[4]; /*!< OS2EC Data Bytes */\r
- };\r
-} ACPI_EC0_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ KBC ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The CEC1302 keyboard controller uses the EC to produce a superset of the\r
- features provided by the industry-standard 8042 keyboard controller. The 8042 Emulated\r
- Keyboard Controller is a Host/EC Message Interface with hardware assists to emulate 8042\r
- behavior and provide Legacy GATEA20 support. (KBC)\r
- */\r
-\r
-typedef struct { /*!< KBC Structure */\r
- \r
- union {\r
- __O uint8_t WT_PORT60_DATA; /*!< Host_EC Data Register (=Host Write 60h) */\r
- __I uint8_t RD_PORT60_DATA; /*!< EC_Host Data/Aux Register (=Host Read 60h) */\r
- };\r
- __I uint8_t RESERVED[3];\r
- \r
- union {\r
- union {\r
- __I uint8_t RD_PORT64_STATUS; /*!< Keyboard Status Register (=Host Read 64h) */\r
- \r
- struct {\r
- __I uint8_t OBF : 1; /*!< Output Buffer Full. */\r
- __I uint8_t IBF : 1; /*!< Input Buffer Full. */\r
- __I uint8_t UD0 : 1; /*!< User-defined data. */\r
- __I uint8_t CMDnDATA : 1; /*!< data register contains data(0) or command(1) */\r
- __I uint8_t UD1 : 1; /*!< User-defined data. */\r
- __I uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */\r
- __I uint8_t UD2 : 2; /*!< User-defined data. */\r
- } RD_PORT64_STATUS_b; /*!< BitSize */\r
- };\r
- __O uint8_t WT_PORT64_CMD; /*!< Host_EC Command Register (=Host Write 64h) */\r
- };\r
- __I uint8_t RESERVED1[251];\r
- \r
- union {\r
- __O uint8_t EC_DATA; /*!< EC2Host Data Register */\r
- __I uint8_t HOST2EC_DATA; /*!< Host2EC Data/Cmd Register */\r
- };\r
- __I uint8_t RESERVED2[3];\r
- \r
- union {\r
- __IO uint8_t STATUS; /*!< EC KEYBOARD STATUS REGISTER */\r
- \r
- struct {\r
- __I uint8_t OBF : 1; /*!< Output Buffer Full. */\r
- __I uint8_t IBF : 1; /*!< Input Buffer Full. */\r
- __IO uint8_t UD0 : 1; /*!< User-defined data. */\r
- __I uint8_t CMDnDATA : 1; /*!< data register contains data(0) or command(1) */\r
- __IO uint8_t UD1 : 1; /*!< User-defined data. */\r
- __IO uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */\r
- __IO uint8_t UD2 : 2; /*!< User-defined data. */\r
- } STATUS_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED3[3];\r
- \r
- union {\r
- __IO uint8_t CONTROL; /*!< Keyboard Control Register */\r
- \r
- struct {\r
- __IO uint8_t UD3 : 1; /*!< User-defined data. */\r
- __IO uint8_t SAEN : 1; /*!< Software-assist enable. */\r
- __IO uint8_t PCOBFEN : 1; /*!< 1=write to PCOBF, 0=writes to EC Data Reg. */\r
- __IO uint8_t UD4 : 2; /*!< User-defined data. */\r
- __IO uint8_t OBFEN : 1; /*!< 1=KIRQ is driven by PCOBF and MIRQ */\r
- __IO uint8_t UD5 : 1; /*!< User-defined data. */\r
- __IO uint8_t AUXH : 1; /*!< AUX in Hardware. */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED4[3];\r
- __O uint8_t AUX_DATA; /*!< EC_Host Aux Register */\r
- __I uint8_t RESERVED5[7];\r
- __IO uint8_t PCOBF; /*!< [0:0] PCOBF Register */\r
- __I uint8_t RESERVED6[539];\r
- __IO uint8_t ACTIVATE; /*!< [0:0] 1=8042 I/F is powered/functional */\r
-} KBC_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PORT92 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The registers listed in the Configuration Register Summary table are for a \r
- single instance of the Legacy Port92 and GATEA20 logic. (PORT92)\r
- */\r
-\r
-typedef struct { /*!< PORT92 Structure */\r
- \r
- union {\r
- __IO uint8_t PORT92; /*!< Support GATE_A20 CPU_RESET control */\r
- \r
- struct {\r
- __IO uint8_t ALT_CPU_RESET: 1; /*!< provides to generate a CPU_RESET pulse. */\r
- __IO uint8_t ALT_GATE_A20: 1; /*!< provides system to control GATEA20 pin. */\r
- } PORT92_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED[255];\r
- __IO uint8_t GATEA20; /*!< [0:0] 0=GATEA20 output low, 1=outputn high */\r
- __I uint8_t RESERVED1[7];\r
- __O uint8_t SETGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */\r
- __I uint8_t RESERVED2[3];\r
- __IO uint8_t RSTGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */\r
- __I uint8_t RESERVED3[547];\r
- __IO uint8_t PORT92_ENABLE; /*!< [0:0] 1= Port92h Register is enabled. */\r
-} PORT92_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ MBX ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The Mailbox provides a standard run-time mechanism for the host to\r
- communicate with the Embedded Controller (EC) (MBX)\r
- */\r
-\r
-typedef struct { /*!< MBX Structure */\r
- __IO uint8_t INDEX; /*!< MBX_Index Register */\r
- __IO uint8_t DATA_REG; /*!< MBX_Data_Register */\r
- __I uint16_t RESERVED[127];\r
- __IO uint8_t HOST_TO_EC; /*!< HOST-to-EC Mailbox Register */\r
- __I uint8_t RESERVED1[3];\r
- __IO uint8_t EC_TO_HOST; /*!< EC-to-Host Mailbox Register */\r
- __I uint8_t RESERVED2[3];\r
- \r
- union {\r
- __IO uint8_t SMI_SOURCE; /*!< SMI Interrupt Source Register */\r
- \r
- struct {\r
- __I uint8_t EC_WR : 1; /*!< EC Mailbox Write (flag). */\r
- __IO uint8_t EC_SMI : 7; /*!< EC Software Interrupt source control */\r
- } SMI_SOURCE_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED3[3];\r
- \r
- union {\r
- __IO uint8_t SMI_MASK; /*!< SMI Interrupt Mask Register */\r
- \r
- struct {\r
- __IO uint8_t EC_WR_EN : 1; /*!< EC Mailbox Write Interrupt Enable. */\r
- __IO uint8_t EC_SMI_EN : 7; /*!< EC Software Interrupt Enable. */\r
- } SMI_MASK_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED4[3];\r
- __IO uint8_t REG[42]; /*!< Mailbox Register */\r
-} MBX_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PM1 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The CEC1302 implements the ACPI fixed registers but includes only those bits that apply to the power\r
- button sleep button and RTC alarm events. The ACPI WAK_STS, SLP_TYP, and SLP_EN bits are also supported. (PM1)\r
- */\r
-\r
-typedef struct { /*!< PM1 Structure */\r
- __I uint8_t RESERVED;\r
- \r
- union {\r
- __IO uint8_t STS2; /*!< PM1 Status 2 */\r
- \r
- struct {\r
- __IO uint8_t PWRBTN_STS : 1; /*!< simulate a Power button status (R/WC) */\r
- __IO uint8_t SLPBTN_STS : 1; /*!< simulate a Sleep button status (R/WC) */\r
- __IO uint8_t RTC_STS : 1; /*!< simulate a RTC status. (R/WC) */\r
- __IO uint8_t PWRBTNOR_STS: 1; /*!< simulate a Power button override status(R/WC) */\r
- uint8_t : 3;\r
- __IO uint8_t WAK_STS : 1; /*!< Host writing a one to this bit. (R/WC) */\r
- } STS2_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED1;\r
- \r
- union {\r
- __IO uint8_t EN2; /*!< PM1 Enable 2 */\r
- \r
- struct {\r
- __IO uint8_t PWRBTN_EN : 1; /*!< Controlled by Host. read by the EC. */\r
- __IO uint8_t SLPBTN_EN : 1; /*!< Controlled by Host. read by the EC. */\r
- __IO uint8_t RTC_EN : 1; /*!< Controlled by Host. read by the EC. */\r
- } EN2_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED2;\r
- \r
- union {\r
- __IO uint8_t CTRL2; /*!< PM1 Control 2 */\r
- \r
- struct {\r
- uint8_t : 1;\r
- __IO uint8_t PWRBTNOR_EN: 1; /*!< Controlled by Host. read by the EC. */\r
- __IO uint8_t SLP_TYP : 3; /*!< Controlled by Host. read by the EC. */\r
- __IO uint8_t SLP_EN : 1; /*!< Host Wt 1 to set, EC wt 1 to Clr */\r
- } CTRL2_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED3[251];\r
- \r
- union {\r
- __IO uint8_t STS_2; /*!< PM1 Status 2 */\r
- \r
- struct {\r
- __IO uint8_t PWRBTN_STS : 1; /*!< simulate a Power button status (R/WC) */\r
- __IO uint8_t SLPBTN_STS : 1; /*!< simulate a Sleep button status (R/WC) */\r
- __IO uint8_t RTC_STS : 1; /*!< simulate a RTC status. (R/WC) */\r
- __IO uint8_t PWRBTNOR_STS: 1; /*!< simulate a Power button override status(R/WC) */\r
- uint8_t : 3;\r
- __IO uint8_t WAK_STS : 1; /*!< Host writing a one to this bit. (R/WC) */\r
- } STS_2_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED4;\r
- \r
- union {\r
- __IO uint8_t EN_2; /*!< PM1 Enable 2 */\r
- \r
- struct {\r
- __IO uint8_t PWRBTN_EN : 1; /*!< Controlled by Host. read by the EC. */\r
- __IO uint8_t SLPBTN_EN : 1; /*!< Controlled by Host. read by the EC. */\r
- __IO uint8_t RTC_EN : 1; /*!< Controlled by Host. read by the EC. */\r
- } EN_2_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED5;\r
- \r
- union {\r
- __IO uint8_t CTRL_2; /*!< PM1 Control 2 */\r
- \r
- struct {\r
- uint8_t : 1;\r
- __IO uint8_t PWRBTNOR_EN: 1; /*!< Controlled by Host. read by the EC. */\r
- __IO uint8_t SLP_TYP : 3; /*!< Controlled by Host. read by the EC. */\r
- __IO uint8_t SLP_EN : 1; /*!< Host Wt 1 to set, EC wt 1 to Clr */\r
- } CTRL_2_b; /*!< BitSize */\r
- };\r
- __I uint16_t RESERVED6[5];\r
- __IO uint8_t PM_STS; /*!< [0:0]wt 1 interrupt is generated on EC_SCI# */\r
-} PM1_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ UART ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The 16550 UART (Universal Asynchronous Receiver/Transmitter) is a full-function\r
- Two Pin Serial Port that supports the standard RS-232 Interface. (UART)\r
- */\r
-\r
-typedef struct { /*!< UART Structure */\r
- \r
- union {\r
- __O uint8_t TX_DATA; /*!< UART Transmit Buffer Register */\r
- __I uint8_t RX_DATA; /*!< UART Receive Buffer Register */\r
- __IO uint8_t BAUDRATE_LSB; /*!< Programmable BAUD Rate Generator (LSB) Reg. */\r
- };\r
- \r
- union {\r
- union {\r
- __IO uint8_t INT_EN; /*!< UART Interrupt Enable Register */\r
- \r
- struct {\r
- __IO uint8_t ERDAI : 1; /*!< enables Received Data Available Interrupt */\r
- __IO uint8_t ETHREI : 1; /*!< enables Transmitter Holding Empty Interrupt */\r
- __IO uint8_t ELSI : 1; /*!< enables Received Line Status Interrupt */\r
- __IO uint8_t EMSI : 1; /*!< enables the MODEM Status Interrupt */\r
- } INT_EN_b; /*!< BitSize */\r
- };\r
- __IO uint8_t BAUDRATE_MSB; /*!< [6:0]BAUD_RATE_DIVISOR_MSB [7]BAUD_CLK_SEL */\r
- };\r
- \r
- union {\r
- union {\r
- __I uint8_t INT_ID; /*!< UART Interrupt Identification Register */\r
- \r
- struct {\r
- __I uint8_t IPEND : 1; /*!< indicate whether an interrupt is pending. */\r
- __I uint8_t INTID : 3; /*!< highest priority interrupt pending */\r
- uint8_t : 2;\r
- __I uint8_t FIFO_EN : 2; /*!< two bits are set when FIFO CONTROL bit 0=1 */\r
- } INT_ID_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __O uint8_t FIFO_CR; /*!< UART FIFO Control Register */\r
- \r
- struct {\r
- __O uint8_t EXRF : 1; /*!< Enable XMIT and RECV FIFO. */\r
- __O uint8_t CLEAR_RECV_FIFO: 1; /*!< clears all bytes in RCVR FIFO, resets counter */\r
- __O uint8_t CLEAR_XMIT_FIFO: 1; /*!< clears all bytes in XMIT FIFO, resets counter */\r
- __IO uint8_t DMA_MODE_SELECT: 1; /*!< RXRDY,TXRDY pins functions are reserved. */\r
- uint8_t : 2;\r
- __IO uint8_t RECV_FIFO_TRIGGER_LEVEL: 2; /*!< set trigger level for RCVR FIFO Intr */\r
- } FIFO_CR_b; /*!< BitSize */\r
- };\r
- };\r
- \r
- union {\r
- __IO uint8_t LINE_CR; /*!< UART Line Control Register */\r
- \r
- struct {\r
- __IO uint8_t WORD_LENGTH: 2; /*!< number of bits in transmitted or received */\r
- __IO uint8_t STOP_BITS : 1; /*!< number of stop bits in transmitted or received */\r
- __IO uint8_t ENABLE_PARITY: 1; /*!< Parity Enable bit. */\r
- __IO uint8_t PARITY_SELECT: 1; /*!< Even Parity Select bit. */\r
- __IO uint8_t STICK_PARITY: 1; /*!< Stick Parity bit. */\r
- __IO uint8_t BREAK_CONTROL: 1; /*!< Set Break Control bit */\r
- __IO uint8_t DLAB : 1; /*!< DLAB Divisor Latch Access Bit (DLAB). */\r
- } LINE_CR_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint8_t MODEM_CR; /*!< UART Modem Control Register */\r
- \r
- struct {\r
- __IO uint8_t DTR : 1; /*!< Data Terminal Ready (nDTR) output. */\r
- __IO uint8_t RTS : 1; /*!< Request To Send (nRTS) output. */\r
- __IO uint8_t OUT1 : 1; /*!< controls the Output 1 (OUT1) bit. */\r
- __IO uint8_t OUT2 : 1; /*!< enable an UART interrupt. */\r
- __IO uint8_t LOOPBACK : 1; /*!< provides loopback for diagnostic */\r
- } MODEM_CR_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __I uint8_t LINE_STS; /*!< UART Line Status Register */\r
- \r
- struct {\r
- __I uint8_t DATA_READY : 1; /*!< 1= data into Rx Buffer Register or FIFO */\r
- __I uint8_t OVERRUN : 1; /*!< OVERRUN Overrun Error. */\r
- __I uint8_t PE : 1; /*!< PARITY ERROR Parity Error. */\r
- __I uint8_t FRAME_ERROR: 1; /*!< FRAME_ERROR Framing Error. */\r
- __I uint8_t BREAK_INTERRUPT: 1; /*!< BREAK_INTERRUPT Break Interrupt. */\r
- __I uint8_t TRANSMIT_EMPTY: 1; /*!< Transmitter Holding Register Empty */\r
- __I uint8_t TRANSMIT_ERROR: 1; /*!< Transmitter Holding/Shift are both empty. */\r
- __I uint8_t FIFO_ERROR : 1; /*!< FIFO_ERROR */\r
- } LINE_STS_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __I uint8_t MODEM_STS; /*!< UART Modem Status Register */\r
- \r
- struct {\r
- __I uint8_t CTS : 1; /*!< CTS Delta Clear To Send (DCTS). */\r
- __I uint8_t DSR : 1; /*!< DSR Delta Data Set Ready (DDSR). */\r
- __I uint8_t RI : 1; /*!< Trailing Edge of Ring Indicator (TERI). */\r
- __I uint8_t DCD : 1; /*!< DCD Delta Data Carrier Detect (DDCD). */\r
- __IO uint8_t nCTS : 1; /*!< complement of Clear To Send (nCTS) input. */\r
- __IO uint8_t nDSR : 1; /*!< complement of Data Set Ready (nDSR) input. */\r
- __IO uint8_t nRI : 1; /*!< complement of Ring Indicator (nRI) input. */\r
- __IO uint8_t nDCD : 1; /*!< complement of Data Carrier Detect (nDCD) input. */\r
- } MODEM_STS_b; /*!< BitSize */\r
- };\r
- __IO uint8_t SCRATCHPAD; /*!< as a scratchpad reg. be used by programmer */\r
- __I uint32_t RESERVED[202];\r
- __IO uint8_t ACTIVATE; /*!< [0:0] 1= UART is powered/functional. */\r
- __I uint8_t RESERVED1[191];\r
- \r
- union {\r
- __IO uint8_t CONFIG; /*!< UART Config Select Register */\r
- \r
- struct {\r
- __IO uint8_t CLK_SRC : 1; /*!< 1=Baud Clock from external clock, 0=internal */\r
- __IO uint8_t POWER : 1; /*!< 1=reset from nSIO_RESET, 0=VCC1_RESET */\r
- __IO uint8_t POLARITY : 1; /*!< 1=UART_TX and UART_RX pins are inverted */\r
- } CONFIG_b; /*!< BitSize */\r
- };\r
-} UART_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ INTR ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The interrupt generation logic is made of 16 groups of signals, each of which\r
- consist of a Status register, a Enable register and a Result register. The Status and Enable\r
- are latched registers. The Result register is a bit by bit AND function of the Source and Enable\r
- registers. All the bits of the Result register are OR'ed together and AND'ed with the corresponding\r
- bit in the Block Select register to form the interrupt signal that is routed to the ARM interrupt controller. (INTR)\r
- */\r
-\r
-typedef struct { /*!< INTR Structure */\r
- INTR_IRQ_Type IRQ[16]; /*!< DEFINITIONS FOR GIRQi SOURCE/ENABLE/RESULT */\r
- __I uint32_t RESERVED[48];\r
- __IO uint32_t BLOCK_ENABLE_SET; /*!< [23:8] IRQ Vector Enable Set */\r
- __IO uint32_t BLOCK_ENABLE_CLEAR; /*!< [23:8] IRQ Vector Enable Clear */\r
- __I uint32_t IRQ_VECTOR_STATE; /*!< [23:8] reflects current state of IRQi */\r
-} INTR_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ WDT ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The function of the Watchdog Timer is to provide a mechanism to detect if the\r
- internal embedded controller has failed. When enabled, the Watchdog Timer (WDT) circuit will generate\r
- a WDT Event if the user program fails to reload the WDT within a specified length of time known as the WDT Interval. (WDT)\r
- */\r
-\r
-typedef struct { /*!< WDT Structure */\r
- __IO uint16_t LOAD; /*!< Writing to reload Watch Dog Timer counter */\r
- __I uint16_t RESERVED;\r
- \r
- union {\r
- __IO uint8_t CONTROL; /*!< WDT Control Register */\r
- \r
- struct {\r
- __IO uint8_t ENABLE : 1; /*!< WDT Block enabled */\r
- __IO uint8_t STATUS : 1; /*!< last reset was caused by an underflow (R/WC) */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED1[3];\r
- __O uint8_t KICK; /*!< Writes to reload and start decrementing */\r
- __I uint8_t RESERVED2[3];\r
- __I uint16_t COUNT; /*!< current WDT count. */\r
-} WDT_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ TIMER_16_0 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief This timer block offers a simple mechanism for firmware to maintain a time\r
- base. This timer may be instantiated as 16 bits or 32 bits. (TIMER_16_0)\r
- */\r
-\r
-typedef struct { /*!< TIMER_16_0 Structure */\r
- __IO uint32_t COUNT; /*!< Timer counter. may be set by Firmware. */\r
- __IO uint32_t PRE_LOAD; /*!< Timer pre-load for counter upon restart. */\r
- __IO uint32_t INTERRUPT_STATUS; /*!< [0:0] Interrupt status (R/WC) */\r
- __IO uint32_t INTERRUPT_ENABLE; /*!< [0:0] interrupt enable */\r
- \r
- union {\r
- __IO REG32_U CONTROL; /*!< Timer Control Register */\r
- \r
- struct {\r
- __IO uint32_t ENABLE : 1; /*!< This enables the block for operation. */\r
- uint32_t : 1;\r
- __IO uint32_t COUNT_UP : 1; /*!< This selects the counter direction. */\r
- __IO uint32_t AUTO_RESTART: 1; /*!< select action taken upon completing a count. */\r
- __IO uint32_t SOFT_RESET : 1; /*!< soft reset. self clearing 1 cycle. */\r
- __IO uint32_t START : 1; /*!< This bit triggers the timer counter. */\r
- __IO uint32_t RELOAD : 1; /*!< reloads counter without interrupting. */\r
- __IO uint32_t HALT : 1; /*!< halt bit. */\r
- uint32_t : 8;\r
- __IO uint32_t PRE_SCALE : 16; /*!< to divide down system clock */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
-} TIMER_16_0_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ HTM ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The Hibernation Timer can generate a wake event to the Embedded Controller (EC)\r
- when it is in a hibernation mode. This block supports wake events up to 2 hours in duration. \r
- The timer is a 16-bit binary count-down timer that can be programmed in 30.5us and 0.125 second \r
- increments for period ranges of 30.5us to 2s or 0.125s to 136.5 minutes, respectively. (HTM)\r
- */\r
-\r
-typedef struct { /*!< HTM Structure */\r
- __IO uint16_t PRELOAD; /*!< [15:0] set Hibernation Timer Preload value */\r
- __I uint16_t RESERVED;\r
- __IO uint16_t CONTROL; /*!< [0:0] 1= resolution 0.125s, 0= 30.5us */\r
- __I uint16_t RESERVED1;\r
- __I uint16_t COUNT; /*!< Count of the Hibernation Timer. */\r
-} HTM_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ RTC ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief This is the set of registers that are automatically counted by hardware\r
- every 1 second while the block is enabled to run and to update. These registers are:\r
- Seconds, Minutes, Hours, Day of Week, Day of Month, Month, and Year. (RTC)\r
- */\r
-\r
-typedef struct { /*!< RTC Structure */\r
- __IO uint8_t SEC; /*!< Seconds Register */\r
- __IO uint8_t SEC_ALARM; /*!< Seconds Alarm Register */\r
- __IO uint8_t MIN; /*!< Minutes Register */\r
- __IO uint8_t MIN_ALARM; /*!< Minutes Alarm Register */\r
- __IO uint8_t HR; /*!< Hours Register */\r
- __IO uint8_t HR_ALARM; /*!< Hours Alarm Register */\r
- __IO uint8_t DAY_WEEK; /*!< Day of Week Register */\r
- __IO uint8_t DAY_MONTH; /*!< Day of Month Register */\r
- __IO uint8_t MONTH; /*!< Month Register */\r
- __IO uint8_t YEAR; /*!< Year Register */\r
- __IO uint8_t REG_A; /*!< Register A */\r
- __IO uint8_t REG_B; /*!< Register B */\r
- __IO uint8_t REG_C; /*!< Register C */\r
- __IO uint8_t REG_D; /*!< Register D */\r
- __I uint16_t RESERVED;\r
- \r
- union {\r
- __IO uint8_t CONTROL; /*!< RTC Control Register */\r
- \r
- struct {\r
- __IO uint8_t BLOCK_ENABLE: 1; /*!< 1= block to function internally */\r
- __IO uint8_t SOFT_RESET : 1; /*!< 1= RTC_RST reset (self-clearing no waiting) */\r
- uint8_t : 1;\r
- __IO uint8_t ALARM_ENABLE: 1; /*!< 1=Enables Alarm, 0=Disables */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED1[3];\r
- __IO uint8_t WEEK_ALARM; /*!< Set value in range 1-7 */\r
- __I uint8_t RESERVED2[3];\r
- \r
- union {\r
- __IO uint32_t DAYLIGHT_SAVINGS_FORWARD; /*!< Daylight Savings Forward Register */\r
- \r
- struct {\r
- __IO uint32_t DST_MONTH : 8; /*!< This field matches the Month Register. */\r
- __IO uint32_t DST_DAY_OF_WEEK: 3; /*!< matches the Day of Week Register bits[2:0]. */\r
- uint32_t : 5;\r
- __IO uint32_t DST_WEEK : 3; /*!< week number (1,,5) within current month. */\r
- uint32_t : 5;\r
- __IO uint32_t DST_HOUR : 7; /*!< matching value for bits[6:0] of Hours register */\r
- __IO uint32_t DST_AM_PM : 1; /*!< This bit selects AM vs. PM. */\r
- } DAYLIGHT_SAVINGS_FORWARD_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t DAYLIGHT_SAVINGS_BACKWARD; /*!< Daylight Savings Backward Register */\r
- \r
- struct {\r
- __IO uint32_t DST_MONTH : 8; /*!< This field matches the Month Register. */\r
- __IO uint32_t DST_DAY_OF_WEEK: 3; /*!< matches the Day of Week Register bits[2:0]. */\r
- uint32_t : 5;\r
- __IO uint32_t DST_WEEK : 3; /*!< week number (1,,5) within current month. */\r
- uint32_t : 5;\r
- __IO uint32_t DST_HOUR : 7; /*!< matching value for bits[6:0] of Hours register */\r
- __IO uint32_t DST_AM_PM : 1; /*!< This bit selects AM vs. PM. */\r
- } DAYLIGHT_SAVINGS_BACKWARD_b; /*!< BitSize */\r
- };\r
-} RTC_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ GPIO ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The CEC1302/24 GPIO Interface provides general purpose input monitoring and output control,\r
- as well as managing many aspects of pin functionality; including, multi-function Pin Multiplexing Control, GPIO\r
- Direction control, PU/PD (PU_PD) resistors, asynchronous wakeup and synchronous Interrupt Detection (int_det),\r
- GPIO Direction, and Polarity control, as well as control of pin drive strength and slew rate. (GPIO)\r
- */\r
-\r
-typedef struct { /*!< GPIO Structure */\r
- \r
- union {\r
- __IO uint32_t PIN_CONTROL[160]; /*!< 1st Pin Control Register */\r
- \r
- struct {\r
- __IO uint32_t PU_PD : 2; /*!< 01= Pull Up, 10= Pull Down, 11/00= None */\r
- __IO uint32_t PWR : 2; /*!< 00= VCC1, 01= VCC2 Power Rail 1x = Reserved */\r
- __IO uint32_t INT_DET : 3; /*!< \r
- [7654] --------------------------------------------\r
- 0 000 = Low Level Sensitive \r
- 0 001 = High Level Sensitive\r
- 0 100 = Interrupt events are disabled\r
- 1 101 = Rising Edge Triggered \r
- 1 110 = Falling Edge Triggered \r
- 1 111 = Either edge triggered \r
- --------------------------------------------------- */\r
- __IO uint32_t EDGE_EN : 1; /*!< 1= Edge detection enabled */\r
- __IO uint32_t BUFFER : 1; /*!< Output Buffer Type. 0 = Push-Pull, 1 = Open Drain */\r
- __IO uint32_t DIR : 1; /*!< GPIO Direction. 0 = Input, 1 = Output */\r
- __IO uint32_t OUTPUT_WRITE_EN: 1; /*!< 0= Alternative GPIO data write enabled */\r
- __IO uint32_t POLARITY : 1; /*!< 0 = Non-inverted, 1 = Inverted */\r
- __IO uint32_t MUX : 2; /*!< 00= GPIO Function, 01/10/11=Func 1/2/3 */\r
- uint32_t : 2;\r
- __IO uint32_t OUTPUT : 1; /*!< 0: GPIO[x] out = '0', 1: GPIO[x] out = '1' */\r
- uint32_t : 7;\r
- __I uint32_t INPUT : 1; /*!< reflects the state of GPIO input */\r
- } PIN_CONTROL_b[160]; /*!< BitSize */\r
- };\r
- __IO uint32_t OUTPUT[5]; /*!< Group 0: GPIO[x] out =0, 1: =1 */\r
- __I uint32_t RESERVED[27];\r
- __IO uint32_t INPUT[5]; /*!< Group GPIO Input Registers */\r
- __I uint32_t RESERVED1[123];\r
- \r
- union {\r
- __IO uint32_t CONTROL2_000_067[56]; /*!< PIN CONTROL REGISTER 2, from 000 - 067 */\r
- \r
- struct {\r
- __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */\r
- uint32_t : 3;\r
- __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */\r
- } CONTROL2_000_067_b[56]; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t CONTROL2_100_167[56]; /*!< PIN CONTROL REGISTER 2, from 100 - 167 */\r
- \r
- struct {\r
- __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */\r
- uint32_t : 3;\r
- __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */\r
- } CONTROL2_100_167_b[56]; /*!< BitSize */\r
- };\r
- __I uint32_t RESERVED2[24];\r
- \r
- union {\r
- __IO uint32_t CONTROL2_200_267[56]; /*!< PIN CONTROL REGISTER 2, from 200 - 267 */\r
- \r
- struct {\r
- __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */\r
- uint32_t : 3;\r
- __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */\r
- } CONTROL2_200_267_b[56]; /*!< BitSize */\r
- };\r
-} GPIO_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ DMA ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The Internal DMA Controller transfers data to/from the source from/to the\r
- destination. The firmware is responsible for setting up each channel. Afterwards either the\r
- firmware or the hardware may perform the flow control. The hardware flow control exists entirely\r
- inside the source device. Each transfer may be 1, 2, or 4 bytes in size, so long as the device\r
- supports a transfer of that size. Every device must be on the internal 32-bit address space. (DMA)\r
- */\r
-\r
-typedef struct { /*!< DMA Structure */\r
- \r
- union {\r
- __IO uint8_t CONTROL; /*!< Soft reset. Enable the blocks operation. */\r
- \r
- struct {\r
- __IO uint8_t ACTIVATE : 1; /*!< Enable the blocks operation. (R/WS) */\r
- __O uint8_t SOFT_RESET : 1; /*!< Soft reset entire module. self-clearing. */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED[3];\r
- __I uint32_t DATA_PACKET; /*!< data from currently active transfer source */\r
- __I uint32_t RESERVED1[2];\r
- DMA_CH_Type CH[12]; /*!< registers to determine channel's operation. */\r
-} DMA_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ SMB0 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface. (SMB0)\r
- */\r
-\r
-typedef struct { /*!< SMB0 Structure */\r
- \r
- union {\r
- union {\r
- __I uint8_t STATUS; /*!< Status Register */\r
- \r
- struct {\r
- __I uint8_t nBB : 1; /*!< 0= Bus Busy */\r
- __I uint8_t LAB : 1; /*!< Lost Arbitration Bit */\r
- __I uint8_t AAS : 1; /*!< Addressed As Slave */\r
- __I uint8_t LRB_AD0 : 1; /*!< "Last Received Bit"/Address 0 (general call) */\r
- __I uint8_t BER : 1; /*!< Bus Error (BER) */\r
- __I uint8_t STS : 1; /*!< 1=ext generated STOP condition is detected. */\r
- __I uint8_t SAD : 1; /*!< SMBus Address Decoded (SAD) */\r
- __I uint8_t PIN : 1; /*!< Pending Interrupt bit */\r
- } STATUS_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __O uint8_t CONTROL; /*!< Control Register */\r
- \r
- struct {\r
- __IO uint8_t ACK : 1; /*!< 1= send an acknowledge automatically */\r
- __IO uint8_t STO : 1; /*!< See STA description */\r
- __IO uint8_t STA : 1; /*!< generation of repeated Start and Stop condition */\r
- __IO uint8_t ENI : 1; /*!< Enable Interrupt bit */\r
- uint8_t : 2;\r
- __IO uint8_t ESO : 1; /*!< enables/disables SMB serial data output */\r
- __IO uint8_t PIN : 1; /*!< Pending Interrupt Not (PIN) software reset */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- };\r
- __I uint8_t RESERVED[3];\r
- \r
- union {\r
- __IO uint16_t OWN; /*!< Own Address Reg. wt 55h= AAh addr */\r
- \r
- struct {\r
- __IO uint16_t ADDRESS_1 : 7; /*!< Own Address 1 addressed as a slave. */\r
- uint16_t : 1;\r
- __IO uint16_t ADDRESS_2 : 7; /*!< Own Address 2 addressed as a slave. */\r
- } OWN_b; /*!< BitSize */\r
- };\r
- __I uint16_t RESERVED1;\r
- __IO uint8_t DATA_REG; /*!< Data */\r
- __I uint8_t RESERVED2[3];\r
- \r
- union {\r
- __IO uint32_t MASTER_COMMAND; /*!< SMBus Master Command Register */\r
- \r
- struct {\r
- __IO uint32_t MRUN : 1; /*!< 1= transfer bytes over SMBus. */\r
- __IO uint32_t MPROCEED : 1; /*!< 1:WAIT-BUSBUSY and MRUN-RECEIVE */\r
- uint32_t : 6;\r
- __IO uint32_t START0 : 1; /*!< 1: send a Start bit on the SMBus */\r
- __IO uint32_t STARTN : 1; /*!< 1: send a Start before the last byte */\r
- __IO uint32_t STOP : 1; /*!< 1: send a Stop bit after transaction completes */\r
- __IO uint32_t PEC_TERM : 1; /*!< 1: PEC is transmitted when WriteCount is 0. */\r
- __IO uint32_t READM : 1; /*!< 1: ReadCount field is replaced by byte */\r
- __IO uint32_t READ_PEC : 1; /*!< 1: reading when ReadCount is 0 for one more byte */\r
- uint32_t : 2;\r
- __IO uint32_t WRITECOUNT : 8; /*!< number of Master Transmit Buffer bytes */\r
- __IO uint32_t READCOUNT : 8; /*!< number of Master Receive Buffer bytes */\r
- } MASTER_COMMAND_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t SLAVE_COMMAND; /*!< SMBus Slave Command Register */\r
- \r
- struct {\r
- __IO uint32_t SRUN : 1; /*!< 1:enables the Slave State Machine to operate */\r
- __IO uint32_t SPROCEED : 1; /*!< Slave to START_WAIT/RECEIVE/TRANSMIT states */\r
- __IO uint32_t SLAVE_PEC : 1; /*!< 1:PEC is copied to the DATA register */\r
- uint32_t : 5;\r
- __IO uint32_t SLAVE_WRITECOUNT: 8; /*!< number bytes software expects to send to Master */\r
- __IO uint32_t SLAVE_READCOUNT: 8; /*!< number copied from DATA to Slave Receive Buffer */\r
- } SLAVE_COMMAND_b; /*!< BitSize */\r
- };\r
- __IO uint8_t PEC; /*!< PEC byte */\r
- __I uint8_t RESERVED3[3];\r
- __IO uint8_t DATA_TIMING2; /*!< HOLD TIME (clock) START BIT */\r
- __I uint8_t RESERVED4[7];\r
- \r
- union {\r
- __IO uint32_t COMPLETION; /*!< Completion Register */\r
- \r
- struct {\r
- uint32_t : 2;\r
- __IO uint32_t DTEN : 1; /*!< 1: Device Time-out checking is enabled. */\r
- __IO uint32_t MCEN : 1; /*!< 1: enable Master Cumulative Time-Out checking */\r
- __IO uint32_t SCEN : 1; /*!< 1:enable Slave Cumulative Time-Out checking */\r
- __IO uint32_t BIDEN : 1; /*!< 1:Bus Idle Detect Time-Out checking is enabled */\r
- __I uint32_t TIMERR : 1; /*!< 1:timeout error detect status are asserted. */\r
- uint32_t : 1;\r
- __IO uint32_t DTO : 1; /*!< DTO is the Device Time-out bit. (R/WC) */\r
- __IO uint32_t MCTO : 1; /*!< Master Cumulative Time-out bit. (R/WC) */\r
- __IO uint32_t SCTO : 1; /*!< SCTO is the Slave Cumulative Time-out bit(R/WC) */\r
- __IO uint32_t CHDL : 1; /*!< CHDL is the clock high time-out detect bit(R/WC) */\r
- __IO uint32_t CHDH : 1; /*!< CHDH is the bus idle time-out detect bit(R/WC) */\r
- __IO uint32_t BER : 1; /*!< 1: BER in Status was set (R/WC) */\r
- __IO uint32_t LAB : 1; /*!< 1: LAB in Status was set (R/WC) */\r
- uint32_t : 1;\r
- __IO uint32_t SNAKR : 1; /*!< 1: Slave sent NACK to transmitting Master */\r
- __I uint32_t STR : 1; /*!< 0: finished receive, 1:finished transmit phase */\r
- uint32_t : 1;\r
- __IO uint32_t SPROT : 1; /*!< 1: WriteCount in Slave counted down to 0(R/WC) */\r
- __IO uint32_t REPEAT_READ: 1; /*!< 1: Slave stopped because a Repeat Start for Rd */\r
- __IO uint32_t REPEAT_WRITE: 1; /*!< 1: Slave stopped because a Repeat Start for Wt */\r
- uint32_t : 2;\r
- __IO uint32_t MNAKX : 1; /*!< 1: Master received a NACK while transmitting */\r
- __I uint32_t MTR : 1; /*!< Master finished 0: receive 1: transmit */\r
- uint32_t : 3;\r
- __IO uint32_t IDLE : 1; /*!< 1: I2C bus becomes idle (R/WC) */\r
- __IO uint32_t MDONE : 1; /*!< 1: Master completed operation (R/WC) */\r
- __IO uint32_t SDONE : 1; /*!< 1: Slave completed operation (R/WC) */\r
- } COMPLETION_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t IDLE_SCALING; /*!< Idle Scaling Register */\r
- \r
- struct {\r
- __IO uint32_t FAIR_BUS_IDLE_MIN: 12; /*!< number ticks to satisfy the fairness protocol */\r
- uint32_t : 4;\r
- __IO uint32_t FAIR_IDLE_DELAY: 12; /*!< number ticks to program the delay */\r
- } IDLE_SCALING_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t CONFIGURATION; /*!< Configuration Register */\r
- \r
- struct {\r
- __IO uint32_t PORT_SEL : 4; /*!< determine one of 16 bus ports apply to SDAT/SCLK */\r
- __IO uint32_t TCEN : 1; /*!< 1: Bus Time-Outs are enabled */\r
- __I uint32_t SLOW_CLOCK : 1; /*!< 1: Bus Clock multiplied by 4, thus frequency/4 */\r
- uint32_t : 1;\r
- __IO uint32_t PECEN : 1; /*!< 1: Hardware PEC Support is enabled */\r
- __IO uint32_t DFEN : 1; /*!< 1: Digital Filter is enabled. 0: bypassed. */\r
- __IO uint32_t RESET : 1; /*!< 1: initialized to power-on default state. */\r
- __IO uint32_t ENAB : 1; /*!< 1: normal operation, 0: lowest power */\r
- __IO uint32_t DSA : 1; /*!< 0: Slave Address I2C Compatibility, 1: SMBus */\r
- __IO uint32_t FAIR : 1; /*!< 1: MCTP Fairness protocol is in effect. */\r
- uint32_t : 1;\r
- __I uint32_t GC_DIS : 1; /*!< General Call address 0: enabled, 1: disabled */\r
- uint32_t : 1;\r
- __O uint32_t FLUSH_SXBUF: 1; /*!< 1: Slave Transmit Buffer to be marked empty. */\r
- __O uint32_t FLUSH_SRBUF: 1; /*!< 1: Slave Receive Buffer to be marked empty. */\r
- __O uint32_t FLUSH_MXBUF: 1; /*!< 1: Master Transmit Buffer to be marked empty. */\r
- __O uint32_t FLUSH_MRBUF: 1; /*!< 1: Master Receive Buffer to be marked empty. */\r
- uint32_t : 8;\r
- __I uint32_t EN_AAS : 1; /*!< 0: Disable AAS Interrupt, 1: Enable */\r
- __IO uint32_t ENIDI : 1; /*!< 1: Idle interrupt is enabled. 0: disabled. */\r
- __IO uint32_t ENMI : 1; /*!< 1: Master Done interrupt is enabled. 0: disabled */\r
- __IO uint32_t ENSI : 1; /*!< 1: Slave Done interrupt is enabled. 0: disabled */\r
- } CONFIGURATION_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint16_t BUS_CLOCK; /*!< Bus Clock Register */\r
- \r
- struct {\r
- __IO uint16_t LOW_PERIOD : 8; /*!< number of I2C Baud Clock to make up low phase */\r
- __IO uint16_t HIGH_PERIOD: 8; /*!< number of I2C Baud Clock to make up high phase */\r
- } BUS_CLOCK_b; /*!< BitSize */\r
- };\r
- __I uint16_t RESERVED5;\r
- __I uint8_t BLOCK_ID; /*!< Block ID Register */\r
- __I uint8_t RESERVED6[3];\r
- __I uint8_t REVISION; /*!< Revision Register */\r
- __I uint8_t RESERVED7[3];\r
- \r
- union {\r
- __IO uint8_t BIT_BANG_CONTROL; /*!< Bit-Bang Control Register */\r
- \r
- struct {\r
- __IO uint8_t BBEN : 1; /*!< 1: Bit-Bang Mode Enable. */\r
- __IO uint8_t CLDIR : 1; /*!< Bit-Bang Clock Direction. 0 - Input, 1 - Output */\r
- __IO uint8_t DADIR : 1; /*!< Bit-Bang Data Direction. 0 - Input. 1 - Output */\r
- __IO uint8_t BBCLK : 1; /*!< controls state of SCLK when BBEN = CLDIR = 1 */\r
- __IO uint8_t BBDAT : 1; /*!< controls state of SDAT when BBEN = DADIR = 1 */\r
- __I uint8_t BBCLKI : 1; /*!< Bit-Bang Clock In. returns the state of SCLK. */\r
- __I uint8_t BBDATI : 1; /*!< Bit-Bang Data In. returns the state of SDAT */\r
- } BIT_BANG_CONTROL_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED8[7];\r
- \r
- union {\r
- __IO uint32_t DATA_TIMING; /*!< Data Timing Register */\r
- \r
- struct {\r
- __IO uint32_t DATA_HOLD : 8; /*!< SDAT hold time following SCLK driven low. */\r
- __IO uint32_t RESTART_SETUP: 8; /*!< SDAT setup time for a repeated START condition. */\r
- __IO uint32_t STOP_SETUP : 8; /*!< SDAT setup time for a STOP condition. */\r
- __IO uint32_t START_HOLD : 8; /*!< SCLK hold time during a START condition. */\r
- } DATA_TIMING_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t TIME_OUT_SCALING; /*!< Time-Out Scaling Register */\r
- \r
- struct {\r
- __IO uint32_t CLOCK_HIGH : 8; /*!< = Clock High Time-Out x Baud_Clock_Period x 2 */\r
- __IO uint32_t SLAVE_CUM : 8; /*!< = Slave Cum Time-Out x Baud_Clock_Period x 1024 */\r
- __IO uint32_t MASTER_CUM : 8; /*!< = Master Cum Time-Out x Baud_Clock_Periodx 512 */\r
- __IO uint32_t BUS_IDLE_MIN: 8; /*!< = Bus Idle Min [7:0] x Baud_Clock_Period */\r
- } TIME_OUT_SCALING_b; /*!< BitSize */\r
- };\r
- __IO uint8_t SLAVE_TRANSMIT_BUFFER; /*!< SMBus Slave Transmit Buffer Register */\r
- __I uint8_t RESERVED9[3];\r
- __IO uint8_t SLAVE_RECEIVE_BUFFER; /*!< SMBus Slave Receive Buffer Register */\r
- __I uint8_t RESERVED10[3];\r
- __IO uint8_t MASTER_TRANSMIT_BUFER; /*!< SMBus Master Transmit Bufer Register */\r
- __I uint8_t RESERVED11[3];\r
- __IO uint8_t MASTER_RECEIVE_BUFFER; /*!< SMBus Master Receive Buffer Register */\r
-} SMB0_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PECI ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The CEC1302 includes a PECI Interface to allow the EC to retrieve temperature readings from PECI-compliant devices. (PECI)\r
- */\r
-\r
-typedef struct { /*!< PECI Structure */\r
- __IO uint8_t WRITE_DATA; /*!< Tprovides access to a 32-byte Transmit FIFO. */\r
- __I uint8_t RESERVED[3];\r
- __IO uint8_t READ_DATA; /*!< provides access to a 32-byte Receive FIFO. */\r
- __I uint8_t RESERVED1[3];\r
- \r
- union {\r
- __IO uint8_t CONTROL; /*!< Control Register */\r
- \r
- struct {\r
- __IO uint8_t PD : 1; /*!< Power Down controls Power Management Interface */\r
- uint8_t : 2;\r
- __IO uint8_t RST : 1; /*!< RST indicates that the PECI Core should be reset. */\r
- uint8_t : 1;\r
- __IO uint8_t FRST : 1; /*!< FRST is the FIFO Reset bit. */\r
- __IO uint8_t TXEN : 1; /*!< TXEN is the Transmit Enable bit. */\r
- __IO uint8_t MIEN : 1; /*!< MIEN is the Master Interrupt Enable */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED2[3];\r
- \r
- union {\r
- __IO uint8_t STATUS1; /*!< Status Register 1 */\r
- \r
- struct {\r
- __IO uint8_t BOF : 1; /*!< PECI begins Address Timing Negotiation(R/WC) */\r
- __IO uint8_t nEOF : 1; /*!< End of Frame asserted following Message Stop(R/WC) */\r
- __I uint8_t ERR : 1; /*!< error for current transaction has been detected */\r
- __I uint8_t RDY : 1; /*!< state of the READY signal function */\r
- __IO uint8_t RDYLO : 1; /*!< 1: falling edge of the READY signal function(R/WC) */\r
- __IO uint8_t RDYHI : 1; /*!< 1: rising edge of the READY signal function (R/WC) */\r
- uint8_t : 1;\r
- __I uint8_t MINT : 1; /*!< asserted when any interrupt status is asserted. */\r
- } STATUS1_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED3[3];\r
- \r
- union {\r
- __I uint8_t STATUS2; /*!< Status Register 2 */\r
- \r
- struct {\r
- __I uint8_t WFF : 1; /*!< Write Data Register FIFO is full. No interrupt. */\r
- __I uint8_t WFE : 1; /*!< Write Data Register FIFO is empty. */\r
- __I uint8_t RFF : 1; /*!< RFF indicates Read Data Register FIFO is full. */\r
- __I uint8_t RFE : 1; /*!< Read Data Register FIFO is empty. No interrupt. */\r
- uint8_t : 3;\r
- __I uint8_t IDLE : 1; /*!< SST/PECI bus is idle, a new transaction may begin */\r
- } STATUS2_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED4[3];\r
- \r
- union {\r
- __IO uint8_t ERROR; /*!< Error Register */\r
- \r
- struct {\r
- __IO uint8_t FERR : 1; /*!< FERR (Frame Check Sequence Error). (R/WC) */\r
- __IO uint8_t BERR : 1; /*!< reads value different from it has driven (R/WC) */\r
- uint8_t : 1;\r
- __IO uint8_t REQERR : 1; /*!< READY is not asserted when counts down to zero */\r
- __IO uint8_t WROV : 1; /*!< WROV (Write Overrun). (R/WC) */\r
- __IO uint8_t WRUN : 1; /*!< WRUN (Write Underrun). (R/WC) */\r
- __IO uint8_t RDOV : 1; /*!< indicates read buffer has overflowed (R/WC) */\r
- __IO uint8_t CLKERR : 1; /*!< READY de-asserted in middle of a transaction(R/WC) */\r
- } ERROR_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED5[3];\r
- \r
- union {\r
- __IO uint8_t INT_EN1; /*!< Interrupt Enable 1 Register */\r
- \r
- struct {\r
- __IO uint8_t BIEN : 1; /*!< '1' the BOF interrupt is enabled. */\r
- __IO uint8_t EIEN : 1; /*!< '1' the EOF interrupt is enabled. */\r
- __IO uint8_t EREN : 1; /*!< '1' the ERR interrupt is enabled. */\r
- uint8_t : 1;\r
- __IO uint8_t RLEN : 1; /*!< '1' the RDYLO interrupt is enabled. */\r
- __IO uint8_t RHEN : 1; /*!< '1' the RDYHI interrupt is enabled. */\r
- } INT_EN1_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED6[3];\r
- \r
- union {\r
- __IO uint8_t INT_EN2; /*!< Interrupt Enable 2 Register */\r
- \r
- struct {\r
- uint8_t : 1;\r
- __IO uint8_t ENWFE : 1; /*!< '1' the WFE interrupt is enabled. */\r
- __IO uint8_t ENRFF : 1; /*!< '1' the RFF interrupt is enabled. */\r
- } INT_EN2_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED7[3];\r
- __IO uint8_t OBT1; /*!< Optimal Bit Time Register (Low Byte) */\r
- __I uint8_t RESERVED8[3];\r
- __IO uint8_t OBT2; /*!< Optimal Bit Time Register (High Byte) */\r
- __I uint8_t RESERVED9[27];\r
- __IO uint32_t ID; /*!< Block ID Register */\r
- __IO uint32_t REV; /*!< Revision Register */\r
-} PECI_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ TACH_0 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief This block monitors TACH output signals (or locked rotor signals) from\r
- various types of fans, and determines their speed. (TACH_0)\r
- */\r
-\r
-typedef struct { /*!< TACH_0 Structure */\r
- \r
- union {\r
- __IO uint32_t CONTROL; /*!< TACHx Control Register */\r
- \r
- struct {\r
- __IO uint32_t OUT_LIMIT_ENABLE: 1; /*!< 1=Enable interrupt output from Tach block */\r
- __IO uint32_t TACH_EN : 1; /*!< 1= TACH Monitoring/ clock enabled, 0= TACH Idle */\r
- uint32_t : 6;\r
- __IO uint32_t FILTER_EN : 1; /*!< remove high frequency glitches. 1=Filter enabled */\r
- uint32_t : 1;\r
- __IO uint32_t MODE_SELECT: 1; /*!< 1=Counter is incremented on rising edge */\r
- __IO uint32_t EDGES : 2; /*!< 00/01/10/11: 2/3/5/9 Tach edges */\r
- uint32_t : 1;\r
- __IO uint32_t READY_INT_EN: 1; /*!< 1=Enable Count Ready interrupt, 0=Disable */\r
- __IO uint32_t INPUT_INT_EN: 1; /*!< 1=Enable Tach Input toggle interrupt, 0=Disable */\r
- __I uint32_t COUNTER : 16; /*!< latched value of the internal Tach pulse counter */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t STATUS; /*!< TACHx Status Register */\r
- \r
- struct {\r
- __IO uint32_t OUT_LIMIT : 1; /*!< 1=Tach is outside of limits (R/WC) */\r
- __I uint32_t PIN : 1; /*!< 1= Tach Input is high, 0= Input is low */\r
- __IO uint32_t TOGGLE : 1; /*!< 1=Tach Input changed state, 0= stable (R/WC) */\r
- __IO uint32_t COUNT_READY: 1; /*!< 1=Reading ready, 0=Reading not ready */\r
- } STATUS_b; /*!< BitSize */\r
- };\r
- __IO uint16_t HIGH_LIMIT; /*!< value is compared with TACHX_COUNTER field. */\r
- __I uint16_t RESERVED;\r
- __IO uint16_t LOW_LIMIT; /*!< value is compared with TACHX_COUNTER field. */\r
-} TACH_0_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PWM_0 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief This block generates a PWM output that can be used to control 4-wire fans, blinking LEDs, and \r
- other similar devices. Each PWM can generate an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz. \r
- The PWM controller can also used to generate the PROCHOT output and Speaker output. (PWM_0)\r
- */\r
-\r
-typedef struct { /*!< PWM_0 Structure */\r
- __IO uint32_t COUNTER_ON_TIME; /*!< determine both frequency and duty cycle */\r
- __IO uint32_t COUNTER_OFF_TIME; /*!< determine both frequency and duty cycle */\r
- \r
- union {\r
- __IO uint32_t CONFIG; /*!< PWMx CONFIGURATION REGISTER */\r
- \r
- struct {\r
- __IO uint32_t EN : 1; /*!< 1=Enabled (default), 0=Disabled */\r
- __IO uint32_t CLK_SELECT : 1; /*!< determines clock source, 1=CLOCK_LOW, 0=HIGH */\r
- __IO uint32_t INVERT : 1; /*!< 1= PWM_OUTPUT ON State is active low, 0=high */\r
- __IO uint32_t CLK_PRE_DIVIDER: 4; /*!< Clock source is divided by Pre-Divider+1 */\r
- } CONFIG_b; /*!< BitSize */\r
- };\r
-} PWM_0_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ RPM_FAN ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The RPM-PWM Interface is an RPM based Fan Control Algorithm that monitors\r
- the fan's speed and automatically adjusts the drive to maintain the desired fan speed. This\r
- RPM based Fan Control Algorithm controls a PWM output based on a tachometer input. (RPM_FAN)\r
- */\r
-\r
-typedef struct { /*!< RPM_FAN Structure */\r
- __IO uint8_t SETTING; /*!< Drive = (FAN_SETTING VALUE/255) x 100%. */\r
- __IO uint8_t PWM_DIVIDE; /*!< PWM_Frequency = base_clk / PWM_DIVIDE */\r
- \r
- union {\r
- __IO uint16_t CONFIGURATION; /*!< general operation of Fan Control Algorithm */\r
- \r
- struct {\r
- __IO uint16_t UPDATE : 3; /*!< Determines base time between fan driver updates */\r
- __IO uint16_t EDGES : 2; /*!< minimum number of edges that must be detected */\r
- __IO uint16_t RANGE : 2; /*!< Adjusts the range of tachometer reading values. */\r
- __IO uint16_t EN_ALGO : 1; /*!< Enables the RPM based Fan Control Algorithm. */\r
- __IO uint16_t POLARITY : 1; /*!< 1: The Polarity of the PWM driver is inverted. */\r
- __IO uint16_t ERR_RNG : 2; /*!< Control advanced options that affect error window. */\r
- __IO uint16_t DER_OPT : 2; /*!< Control portion of RPM fan control algorithm */\r
- __IO uint16_t DIS_GLITCH : 1; /*!< 1: The glitch filter is disabled. */\r
- __IO uint16_t EN_RRC : 1; /*!< Enables the ramp rate control circuitry */\r
- } CONFIGURATION_b; /*!< BitSize */\r
- };\r
- __I uint8_t RESERVED;\r
- \r
- union {\r
- __IO uint8_t GAIN; /*!< gain for proportional/integral portion */\r
- \r
- struct {\r
- __IO uint8_t GAINP : 2; /*!< derivative gain term */\r
- __IO uint8_t GAINI : 2; /*!< derivative gain term */\r
- __IO uint8_t GAIND : 2; /*!< derivative gain term */\r
- } GAIN_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint8_t SPIN_UP_CONFIGURATION; /*!< settings of Spin Up Routine. */\r
- \r
- struct {\r
- __IO uint8_t SPINUP_TIME: 2; /*!< maximum Spin Time that Spin Up Routine run */\r
- __IO uint8_t SPIN_LVL : 3; /*!< final drive level used by the Spin Up Routine */\r
- __IO uint8_t NOKICK : 1; /*!< 1: Spin Routine will not drive fan to 100% */\r
- __IO uint8_t DRIVE_FAIL_CNT: 2; /*!< update cycles are used for Drive Fail detection */\r
- } SPIN_UP_CONFIGURATION_b; /*!< BitSize */\r
- };\r
- __IO uint8_t STEP; /*!< max step driver take between update */\r
- __IO uint8_t MINIMUM_DRIVE; /*!< minimum drive setting for Fan Algorithm. */\r
- __IO uint8_t VALID_TACH_COUNT; /*!< max value to indicate fan spin properly */\r
- __IO uint16_t DRIVE_FAIL_BAND; /*!< [15:3]counts for Drive Fail circuitry */\r
- __IO uint16_t TACH_TARGET; /*!< [12:0] The target tachometer value. */\r
- __IO uint8_t TACH_READING; /*!< [15:3]current tachometer reading value. */\r
- __I uint8_t RESERVED1;\r
- __IO uint8_t DRIVER_BASE_FREQUENCY; /*!< [1:0]frequency range of the PWM fan driver */\r
- \r
- union {\r
- __IO uint8_t STATUS; /*!< The bits are routed to interrupts */\r
- \r
- struct {\r
- __IO uint8_t FAN_STALL : 1; /*!< 1 - Stalled fan detected. (R/WC) */\r
- __IO uint8_t FAN_SPIN : 1; /*!< 1: Spin up Routine not detect a valid tachometer */\r
- uint8_t : 3;\r
- __IO uint8_t DRIVE_FAIL : 1; /*!< 1- cannot drive to target setting (R/WC) */\r
- } STATUS_b; /*!< BitSize */\r
- };\r
-} RPM_FAN_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ SPI_0 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The General Purpose Serial Peripheral Interface (GP-SPI) may be used\r
- to communicate with various peripheral devices, e.g., EEPROMS, DACs, ADCs, that use a\r
- standard Serial Peripheral Interface. (SPI_0)\r
- */\r
-\r
-typedef struct { /*!< SPI_0 Structure */\r
- __IO uint32_t ENABLE; /*!< [0:0] 1=Enabled. device is fully operational */\r
- \r
- union {\r
- __IO uint32_t CONTROL; /*!< SPI Control */\r
- \r
- struct {\r
- __IO uint32_t LSBF : 1; /*!< Least Significant Bit First */\r
- __IO uint32_t BIOEN : 1; /*!< Bidirectional Output Enable control. */\r
- __IO uint32_t SPDIN_SELECT: 2; /*!< [3:2]1xb=SPDIN1,SPDIN2. Select Dual Mode */\r
- __IO uint32_t SOFT_RESET : 1; /*!< Wt 1 to Soft Reset. self-clearing */\r
- __IO uint32_t AUTO_READ : 1; /*!< Auto Read Enable. */\r
- __IO uint32_t CE : 1; /*!< SPI Chip Select Enable. */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __I uint32_t STATUS; /*!< SPI Status */\r
- \r
- struct {\r
- __I uint32_t TXBE : 1; /*!< 1=TX_Data buffer is empty */\r
- __I uint32_t RXBF : 1; /*!< 1=RX_Data buffer is full */\r
- __I uint32_t ACTIVE : 1; /*!< ACTIVE status */\r
- } STATUS_b; /*!< BitSize */\r
- };\r
- __IO uint32_t TX_DATA; /*!< [7:0]wt to initiate a SPI transaction. */\r
- __IO uint32_t RX_DATA; /*!< [7:0]read value returned by ext SPI device */\r
- \r
- union {\r
- __IO uint32_t CLOCK_Control; /*!< SPI Clock Control. */\r
- \r
- struct {\r
- __IO uint32_t TCLKPH : 1; /*!< Valid data is clocked out on 1st SPI_CLK */\r
- __IO uint32_t RCLKPH : 1; /*!< Valid data is expected after 1st SPI_CLK edge */\r
- __IO uint32_t CLKPOL : 1; /*!< SPI_CLK is high when 1st clock edge falling */\r
- uint32_t : 1;\r
- __IO uint32_t CLKSRC : 1; /*!< 1=2MHz, 0=48 MHz Ring Oscillator */\r
- } CLOCK_Control_b; /*!< BitSize */\r
- };\r
- __IO uint32_t CLOCK_GENERATOR; /*!< [5:0] PRELOAD SPI Clock Generator Preload value. */\r
-} SPI_0_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ LED_0 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The blinking/breathing hardware is implemented using a PWM. The PWM can be\r
- driven either by the 48 MHz clock or by a 32.768 KHz clock input. When driven by the 48 MHz clock,\r
- the PWM can be used as a standard 8-bit PWM in order to control a fan. When used to drive blinking\r
- or breathing LEDs, the 32.768 KHz clock source is used. (LED_0)\r
- */\r
-\r
-typedef struct { /*!< LED_0 Structure */\r
- \r
- union {\r
- __IO uint32_t CONFIG; /*!< LED Configuration */\r
- \r
- struct {\r
- __IO uint32_t CONTROL : 2; /*!< 3=on,2=blinking,1=breathing,0=off */\r
- __IO uint32_t CLOCK_SOURCE: 1; /*!< 1=48MHz, 0=32.768 KHz clock */\r
- __IO uint32_t SYNCHRONIZE: 1; /*!< 1: all LEDs are reset to initial values. */\r
- __IO uint32_t PWM_SIZE : 2; /*!< 3:reserved, 2:6bit, 1:7bit,0:8bit PWM */\r
- __IO uint32_t ENABLE_UPDATE: 1; /*!< ENABLE_UPDATE */\r
- __O uint32_t RESET : 1; /*!< 1 resets PWM to default values self clearing */\r
- __IO uint32_t WDT_RELOAD : 8; /*!< PWM Watchdog Timer counter reload value */\r
- __IO uint32_t SYMMETRY : 1; /*!< 1=rising/falling ramp are in Asymmetric mode */\r
- } CONFIG_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t LIMITS; /*!< LED Limits */\r
- \r
- struct {\r
- __IO uint32_t MINIMUM : 8; /*!< wait in breathing if current cycle less this value */\r
- __IO uint32_t MAXIMUM : 8; /*!< wait, breathing if current cycle great this value */\r
- } LIMITS_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t DELAY; /*!< LED Delay */\r
- \r
- struct {\r
- __IO uint32_t LOWPULSE : 12; /*!< number to wait before updating current cycle */\r
- __IO uint32_t HIGHPULSE : 12; /*!< number to wait before updating current cycle */\r
- } DELAY_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t UPDATE_STEPSIZE; /*!< provide amount duty cycle to adjust */\r
- \r
- struct {\r
- __IO uint32_t STEP0 : 4; /*!< when the segment index is equal to 000. */\r
- __IO uint32_t STEP1 : 4; /*!< when the segment index is equal to 001. */\r
- __IO uint32_t STEP2 : 4; /*!< when the segment index is equal to 010. */\r
- __IO uint32_t STEP3 : 4; /*!< when the segment index is equal to 011. */\r
- __IO uint32_t STEP4 : 4; /*!< when the segment index is equal to 100. */\r
- __IO uint32_t STEP5 : 4; /*!< when the segment index is equal to 101 */\r
- __IO uint32_t STEP6 : 4; /*!< when the segment index is equal to 110. */\r
- __IO uint32_t STEP7 : 4; /*!< when the segment index is equal to 111. */\r
- } UPDATE_STEPSIZE_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t UPDATE_INTERVAL; /*!< LED Update Interval */\r
- \r
- struct {\r
- __IO uint32_t INTERVAL0 : 4; /*!< when the segment index is equal to 000b. */\r
- __IO uint32_t INTERVAL1 : 4; /*!< when the segment index is equal to 001b. */\r
- __IO uint32_t INTERVAL2 : 4; /*!< when the segment index is equal to 010b. */\r
- __IO uint32_t INTERVAL3 : 4; /*!< when the segment index is equal to 011b. */\r
- __IO uint32_t INTERVAL4 : 4; /*!< when the segment index is equal to 100b. */\r
- __IO uint32_t INTERVAL5 : 4; /*!< when the segment index is equal to 101b. */\r
- __IO uint32_t INTERVAL6 : 4; /*!< when the segment index is equal to 110b. */\r
- __IO uint32_t INTERVAL7 : 4; /*!< when the segment index is equal to 111b. */\r
- } UPDATE_INTERVAL_b; /*!< BitSize */\r
- };\r
-} LED_0_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PS2_0 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief There are four PS/2 Ports in the MEC1320 which are directly controlled\r
- by the EC. The hardware implementation eliminates the need to bit bang I/O ports to generate\r
- PS/2 traffic, however bit banging is available via the associated GPIO pins. (PS2_0)\r
- */\r
-\r
-typedef struct { /*!< PS2_0 Structure */\r
- \r
- union {\r
- __I uint32_t RX_DATA; /*!< Data received from a peripheral */\r
- __O uint32_t TX_DATA; /*!< Writes to start a transmission */\r
- };\r
- \r
- union {\r
- __IO uint32_t CONTROL; /*!< PS2 Control Register */\r
- \r
- struct {\r
- __IO uint32_t TR : 1; /*!< PS/2 1:Transmit, 0:Receive data */\r
- __IO uint32_t EN : 1; /*!< 1: PS/2 Enable */\r
- __IO uint32_t PARITY : 2; /*!< 00b=Receiver expects Odd Parity (default). */\r
- __IO uint32_t STOP : 2; /*!< 00b=Receiver expects an active high stop bit */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t STATUS; /*!< PS2 Status Register */\r
- \r
- struct {\r
- __I uint32_t RDATA_RDY : 1; /*!< Data Ready. Reading Receive data to clears */\r
- __IO uint32_t REC_TIMEOUT: 1; /*!< REC_TIMEOUT is cleared when Status is read */\r
- __IO uint32_t PE : 1; /*!< Parity Error */\r
- __IO uint32_t FE : 1; /*!< Framing Error */\r
- __I uint32_t XMIT_IDLE : 1; /*!< 0=actively transmitting PS/2 data. 1=Idle */\r
- __IO uint32_t XMIT_TIME_OUT: 1; /*!< Transmitter Time-out */\r
- __I uint32_t RX_BUSY : 1; /*!< 0=actively receiving PS/2 data, 1=Idle */\r
- __IO uint32_t XMIT_START_TIMEOUT: 1; /*!< Transmit Start Timeout (over 25 ms) */\r
- } STATUS_b; /*!< BitSize */\r
- };\r
-} PS2_0_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ KEYSCAN ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The Keyboard Scan Interface block provides a register interface to the EC\r
- to directly scan an external keyboard matrix of size up to 18x8. (KEYSCAN)\r
- */\r
-\r
-typedef struct { /*!< KEYSCAN Structure */\r
- __I uint32_t RESERVED;\r
- \r
- union {\r
- __IO uint32_t CONTROL; /*!< KSO Select and control */\r
- \r
- struct {\r
- __IO uint32_t SELECT : 5; /*!< selects a KSO line (00000b=KSO[0] etc.) */\r
- __IO uint32_t ALL : 1; /*!< 0=KSO_SELECT set KSO, 1=KSO[x] driven high */\r
- __IO uint32_t KSEN : 1; /*!< 0=Keyboard scan enabled, 1=disabled. */\r
- __IO uint32_t INVERT : 1; /*!< 0=KSO[x] driven low, 1=high when selected. */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- __I uint32_t KSI; /*!< [7:0]returns the current state of KSI pins */\r
- __IO uint32_t STATUS; /*!< [7:0]set on falling edge of KSI */\r
- __IO uint32_t INT_EN; /*!< [7:0]enables int due to H2L on a KSI */\r
- __IO uint32_t EXTENDED_CONTROL; /*!< [0:0] 1=Enable predrive on KSO pins. */\r
-} KEYSCAN_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ BC_LINK ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief This block provides BC-Link connectivity to a slave device. The BC-Link protocol\r
- includes a start bit to signal the beginning of a message and a turnaround (TAR) period\r
- for bus transfer between the Master and Companion devices. (BC_LINK)\r
- */\r
-\r
-typedef struct { /*!< BC_LINK Structure */\r
- \r
- union {\r
- __IO uint32_t STATUS; /*!< BC-Link Status */\r
- \r
- struct {\r
- __I uint32_t BUSY : 1; /*!< 1: BC is transferring data and on reset */\r
- uint32_t : 3;\r
- __IO uint32_t BUSY_CLR_INT_EN: 1; /*!< enable for generating an interrupt */\r
- __IO uint32_t ERR_INT_EN : 1; /*!< enable interrupt when BC_ERR bit set */\r
- __IO uint32_t ERROR : 1; /*!< indicates a BC Bus Error has occurred. (R/WC) */\r
- __IO uint32_t RESET : 1; /*!< 1: Reset BC_Link Master Interface */\r
- } STATUS_b; /*!< BitSize */\r
- };\r
- __IO uint32_t ADDRESS; /*!< Address in Companion for BC-Link */\r
- __IO uint32_t DATA_REG; /*!< hold data used in a BC-Link transaction. */\r
- __IO uint32_t CLOCK_SELECT; /*!< [7:0] DIVIDER 48MHz/ (Divider +1). */\r
-} BC_LINK_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ TFDP ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The TFDP serially transmits Embedded Controller (EC)-originated \r
- diagnostic vectors to an external debug trace system. (TFDP)\r
- */\r
-\r
-typedef struct { /*!< TFDP Structure */\r
- __IO uint8_t DATA_REG; /*!< Debug data to be shifted out on TFDP port */\r
- __I uint8_t RESERVED[3];\r
- \r
- union {\r
- __IO uint8_t CONTROL; /*!< Debug Control Register */\r
- \r
- struct {\r
- __IO uint8_t EN : 1; /*!< 1=Clock enabled, 0=Clock is disabled (Default) */\r
- __IO uint8_t EDGE_SEL : 1; /*!< 1= shifted out on falling edge, 0= rising */\r
- __IO uint8_t DIVSEL : 2; /*!< Clock Divider Select. */\r
- __IO uint8_t IP_DELAY : 3; /*!< Inter-packet Delay. */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
-} TFDP_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ ADC ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief This block is designed to convert external analog voltage readings into digital values. (ADC)\r
- */\r
-\r
-typedef struct { /*!< ADC Structure */\r
- \r
- union {\r
- __IO uint32_t CONTROL; /*!< control behavior of ADC */\r
- \r
- struct {\r
- __IO uint32_t ACTIVATE : 1; /*!< 1: ADC is enabled for operation. */\r
- __IO uint32_t START_SINGLE: 1; /*!< 1: ADC Single Mode is enabled. self-clearing */\r
- __IO uint32_t START_REPEAT: 1; /*!< 1: ADC Repeat Mode is enabled. */\r
- __IO uint32_t POWER_SAVER_DIS: 1; /*!< 0: Power saving enabled. 1: disabled. */\r
- __IO uint32_t SOFT_RESET : 1; /*!< 1: reset of ADC */\r
- uint32_t : 1;\r
- __IO uint32_t REPEAT_DONE_STAT: 1; /*!< 1: ADC repeat conversion is completed.(R/WC) */\r
- __IO uint32_t SINGLE_DONE_STAT: 1; /*!< 1: ADC single conversion is completed.(R/WC) */\r
- } CONTROL_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t DELAY; /*!< delay fm set Start_Repeat and conversion */\r
- \r
- struct {\r
- __IO uint32_t START : 16; /*!< start delay before conv. when Start_Repeat=1 */\r
- __IO uint32_t REPEAT : 16; /*!< interval between conversion when Start_Repeat=1 */\r
- } DELAY_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t STATUS; /*!< 1: conversion is complete (R/WC) */\r
- \r
- struct {\r
- __IO uint32_t CH0 : 1; /*!< ADC_Ch0_Status */\r
- __IO uint32_t CH1 : 1; /*!< ADC_Ch1_Status */\r
- __IO uint32_t CH2 : 1; /*!< ADC_Ch2_Status */\r
- __IO uint32_t CH3 : 1; /*!< ADC_Ch3_Status */\r
- __IO uint32_t CH4 : 1; /*!< ADC_Ch4_Status */\r
- } STATUS_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t SINGLE_EN; /*!< ADC Single-Sample conversion control */\r
- \r
- struct {\r
- __IO uint32_t CH0 : 1; /*!< Ch0 single conversions, 1:enabled/0:disabled */\r
- __IO uint32_t CH1 : 1; /*!< Ch1 single conversions, 1:enabled/0:disabled */\r
- __IO uint32_t CH2 : 1; /*!< Ch2 single conversions, 1:enabled/0:disabled */\r
- __IO uint32_t CH3 : 1; /*!< Ch3 single conversions, 1:enabled/0:disabled */\r
- __IO uint32_t CH4 : 1; /*!< Ch4 single conversions, 1:enabled/0:disabled */\r
- } SINGLE_EN_b; /*!< BitSize */\r
- };\r
- \r
- union {\r
- __IO uint32_t REPEAT; /*!< ADC channels repeat conversion control */\r
- \r
- struct {\r
- __IO uint32_t CH0 : 1; /*!< Ch0 repeat conversions, 1:enabled/0:disabled */\r
- __IO uint32_t CH1 : 1; /*!< Ch1 repeat conversions, 1:enabled/0:disabled */\r
- __IO uint32_t CH2 : 1; /*!< Ch2 repeat conversions, 1:enabled/0:disabled */\r
- __IO uint32_t CH3 : 1; /*!< Ch3 repeat conversions, 1:enabled/0:disabled */\r
- __IO uint32_t CH4 : 1; /*!< Ch4 repeat conversions, 1:enabled/0:disabled */\r
- } REPEAT_b; /*!< BitSize */\r
- };\r
- __IO uint32_t READING[5]; /*!< ADC channels 32-bit reading register. */\r
-} ADC_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ EC_REG_BANK ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief This block is designed to be accessed internally by the EC via the register interface. (EC_REG_BANK)\r
- */\r
-\r
-typedef struct { /*!< EC_REG_BANK Structure */\r
- __I uint32_t RESERVED[5];\r
- __IO uint8_t AHB_ERROR_CONTROL; /*!< 1: EC memory exceptions are disabled. */\r
- __I uint8_t RESERVED1[3];\r
- __IO uint32_t INTERRUPT_CONTROL; /*!< 1= Alternate NVIC vectors enabled */\r
- __IO uint32_t ETM_TRACE_ENABLE; /*!< 1= ARM TRACE port enabled */\r
- __IO uint32_t JTAG_Enable; /*!< 1= JTAG port enabled. */\r
- __I uint32_t RESERVED2;\r
- __IO uint32_t WDT_EVENT_COUNT; /*!< [3:0]EC Rd/Wt are cleared to 0 on VCC1 POR */\r
- __I uint32_t RESERVED3[3];\r
- __IO uint32_t ADC_VREF_PD; /*!< [0:0] ADC VREF Power down. 0=on 1=off */\r
-} EC_REG_BANK_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ JTAG ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief The Controller, which is an IEEE compliant JTAG Port, has implemented all\r
- the mandatory JTAG instructions. This interface may be used to access the embedded controller's\r
- test access port (TAP). (JTAG)\r
- */\r
-\r
-typedef struct { /*!< JTAG Structure */\r
- __IO uint32_t MESSAGE_OBF; /*!< JTAG Message OBF */\r
- __IO uint32_t MESSAGE_IBF; /*!< JTAG Message IBF */\r
- __IO uint8_t OBF_STATUS; /*!< JTAG OBF Status */\r
- __IO uint8_t IBF_STATUS; /*!< JTAG IBF Status */\r
- __I uint16_t RESERVED;\r
- __IO uint32_t DBG_CTRL; /*!< JTAG DBG Ctrl */\r
-} JTAG_Type;\r
-\r
-\r
-/*------------- Public Key Encryption Subsystem (PKE) -----------------------------*/\r
-/** @addtogroup MEC1322_PKE Public Key Encryption (PKE)\r
- @{\r
-*/\r
-typedef struct\r
-{\r
- __IO uint32_t CONFIG; /*!< Offset: 0x0000 Configuration */\r
- __IO uint32_t COMMAND; /*!< Offset: 0x0004 Command */\r
- __IO uint32_t CONTROL; /*!< Offset: 0x0008 Control */\r
- __I uint32_t STATUS; /*!< Offset: 0x000C Status */\r
- __I uint32_t VERSION; /*!< Offset: 0x0010 Version */\r
- __IO uint32_t LOAD_MICRO_CODE; /*!< Offset: 0x0014 Load Micro Code */\r
-} PKE_TypeDef;\r
-/*@}*/ /* end of group MEC1322_PKE */\r
-\r
-/*------------- Random Number Generator Subsystem (TRNG) -----------------------------*/\r
-/** @addtogroup MEC1322_TRNG Random Number Generator (TRNG)\r
- @{\r
-*/\r
-typedef struct\r
-{\r
- __IO uint32_t CONTROL; /*!< Offset: 0x0000 Control */\r
- __I uint32_t FIFO_LEVEL; /*!< Offset: 0x0004 FIFO Level */\r
- __I uint32_t VERSION; /*!< Offset: 0x0008 Version */\r
-} TRNG_TypeDef;\r
-/*@}*/ /* end of group MEC1322_TRNG */\r
-\r
-/*------------- Hash Subsystem (HASH) -----------------------------*/\r
-/** @addtogroup MEC1322_HASH Hash Security (HASH)\r
- @{\r
-*/\r
-typedef struct\r
-{\r
- __IO uint32_t SHA_MODE; /*!< Offset: 0x0000 SHA Mode */\r
- __IO uint32_t NB_BLOCK; /*!< Offset: 0x0004 NbBlock */\r
- __IO uint32_t CONTROL; /*!< Offset: 0x0008 Config */\r
- __I uint32_t STATUS; /*!< Offset: 0x000C Status, Read to clear interrupt */\r
- __I uint32_t VERSION; /*!< Offset: 0x0010 Version */\r
- __I uint32_t GENERIC_VALUE; /*!< Offset: 0x0014 Generic Value */\r
- __IO uint32_t INIT_HASH_ADDR; /*!< Offset: 0x0018 Initial Hash value Address */\r
- __IO uint32_t DATA_SOURCE_ADDR; /*!< Offset: 0x001C Data to hash Address */\r
- __IO uint32_t HASH_RESULT_ADDR; /*!< Offset: 0x0020 Hash result address */\r
-} HASH_TypeDef;\r
-/*@}*/ /* end of group MEC1322_HASH */\r
-\r
-\r
-\r
-/*------------- Advanced Encryption Subsystem (AES) -----------------------------*/\r
-/** @addtogroup MEC1322_AES Advanced Encryption Subsys (AES)\r
- @{\r
-*/\r
-\r
-#define AES_MAX_KEY_WLEN (8)\r
-#define AES_MAX_IV_WLEN (4)\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CONFIG; /*!< Offset: 0x0000 Configuration */\r
- __IO uint32_t COMMAND; /*!< Offset: 0x0004 Command */\r
- __IO uint32_t CONTROL; /*!< Offset: 0x0008 Control */\r
- __I uint32_t STATUS; /*!< Offset: 0x000C Status */\r
- __I uint32_t VERSION; /*!< Offset: 0x0010 Version */\r
- __IO uint32_t NB_HEADER; /*!< Offset: 0x0014 Number of Headers */\r
- __IO uint32_t LAST_HEADER; /*!< Offset: 0x0018 Last Header */\r
- __IO uint32_t NB_BLOCK; /*!< Offset: 0x001C Number of Blocks */\r
- __IO uint32_t LAST_BLOCK; /*!< Offset: 0x0020 Last Block */\r
- __IO uint32_t DMA_IN; /*!< Offset: 0x0024 DMA Input Address */\r
- __IO uint32_t DMA_OUT; /*!< Offset: 0x0028 DMA Output Address */\r
- uint32_t RESERVEDA[(0xFC - 0x2C)/4 + 1];\r
- __IO uint32_t KEY1[AES_MAX_KEY_WLEN];/*!< Offset: 0x0100 KeyIn1[159:128] \r
- !< Offset: 0x0104 KeyIn1[191:160] \r
- !< Offset: 0x0108 KeyIn1[223:192] \r
- !< Offset: 0x010C KeyIn1[255:224] \r
- !< Offset: 0x0110 KeyIn1[31:0] \r
- !< Offset: 0x0114 KeyIn1[63:32] \r
- !< Offset: 0x0118 KeyIn1[95:64] \r
- !< Offset: 0x011C KeyIn1[127:96] */\r
- __IO uint32_t IV[AES_MAX_IV_WLEN]; /*!< Offset: 0x0120 IV[31:0] \r
- !< Offset: 0x0124 IV[63:32] \r
- !< Offset: 0x0128 IV[95:64] \r
- !< Offset: 0x012C IV[127:96] */\r
- uint32_t RESERVEDB[4];\r
- __IO uint32_t KEY2[AES_MAX_KEY_WLEN];/*!< Offset: 0x0140 KeyIn1[159:128] \r
- !< Offset: 0x0144 KeyIn1[191:160] \r
- !< Offset: 0x0148 KeyIn1[223:192] \r
- !< Offset: 0x014C KeyIn1[255:224] \r
- !< Offset: 0x0150 KeyIn1[31:0] \r
- !< Offset: 0x0154 KeyIn1[63:32] \r
- !< Offset: 0x0158 KeyIn1[95:64] \r
- !< Offset: 0x015C KeyIn1[127:96] */\r
-} AES_TypeDef;\r
-/*@}*/ /* end of group MEC1322_AES */\r
-\r
-/* -------------------- End of section using anonymous unions ------------------- */\r
-#if defined(__CC_ARM)\r
- #pragma pop\r
-#elif defined(__ICCARM__)\r
- /* leave anonymous unions enabled */\r
-#elif defined(__GNUC__)\r
- /* anonymous unions are enabled by default */\r
-#elif defined(__TMS470__)\r
- /* anonymous unions are enabled by default */\r
-#elif defined(__TASKING__)\r
- #pragma warning restore\r
-#else\r
- #warning Not supported compiler type\r
-#endif\r
-\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PCR' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PCR_EC_SLP_EN ------------------------------- */\r
-#define PCR_EC_SLP_EN_INT_SLP_EN_Pos (0UL) /*!< PCR EC_SLP_EN: INT_SLP_EN (Bit 0) */\r
-#define PCR_EC_SLP_EN_INT_SLP_EN_Msk (0x1UL) /*!< PCR EC_SLP_EN: INT_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_PECI_SLP_EN_Pos (1UL) /*!< PCR EC_SLP_EN: PECI_SLP_EN (Bit 1) */\r
-#define PCR_EC_SLP_EN_PECI_SLP_EN_Msk (0x2UL) /*!< PCR EC_SLP_EN: PECI_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_TACH0_SLP_EN_Pos (2UL) /*!< PCR EC_SLP_EN: TACH0_SLP_EN (Bit 2) */\r
-#define PCR_EC_SLP_EN_TACH0_SLP_EN_Msk (0x4UL) /*!< PCR EC_SLP_EN: TACH0_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_PWM0_SLP_EN_Pos (4UL) /*!< PCR EC_SLP_EN: PWM0_SLP_EN (Bit 4) */\r
-#define PCR_EC_SLP_EN_PWM0_SLP_EN_Msk (0x10UL) /*!< PCR EC_SLP_EN: PWM0_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_PMC_SLP_EN_Pos (5UL) /*!< PCR EC_SLP_EN: PMC_SLP_EN (Bit 5) */\r
-#define PCR_EC_SLP_EN_PMC_SLP_EN_Msk (0x20UL) /*!< PCR EC_SLP_EN: PMC_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_DMA_SLP_EN_Pos (6UL) /*!< PCR EC_SLP_EN: DMA_SLP_EN (Bit 6) */\r
-#define PCR_EC_SLP_EN_DMA_SLP_EN_Msk (0x40UL) /*!< PCR EC_SLP_EN: DMA_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_TFDP_SLP_EN_Pos (7UL) /*!< PCR EC_SLP_EN: TFDP_SLP_EN (Bit 7) */\r
-#define PCR_EC_SLP_EN_TFDP_SLP_EN_Msk (0x80UL) /*!< PCR EC_SLP_EN: TFDP_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_PROCESSOR_SLP_EN_Pos (8UL) /*!< PCR EC_SLP_EN: PROCESSOR_SLP_EN (Bit 8) */\r
-#define PCR_EC_SLP_EN_PROCESSOR_SLP_EN_Msk (0x100UL) /*!< PCR EC_SLP_EN: PROCESSOR_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_WDT_SLP_EN_Pos (9UL) /*!< PCR EC_SLP_EN: WDT_SLP_EN (Bit 9) */\r
-#define PCR_EC_SLP_EN_WDT_SLP_EN_Msk (0x200UL) /*!< PCR EC_SLP_EN: WDT_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_SMB0_SLP_EN_Pos (10UL) /*!< PCR EC_SLP_EN: SMB0_SLP_EN (Bit 10) */\r
-#define PCR_EC_SLP_EN_SMB0_SLP_EN_Msk (0x400UL) /*!< PCR EC_SLP_EN: SMB0_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_TACH1_SLP_EN_Pos (11UL) /*!< PCR EC_SLP_EN: TACH1_SLP_EN (Bit 11) */\r
-#define PCR_EC_SLP_EN_TACH1_SLP_EN_Msk (0x800UL) /*!< PCR EC_SLP_EN: TACH1_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_PWM1_SLP_EN_Pos (20UL) /*!< PCR EC_SLP_EN: PWM1_SLP_EN (Bit 20) */\r
-#define PCR_EC_SLP_EN_PWM1_SLP_EN_Msk (0x100000UL) /*!< PCR EC_SLP_EN: PWM1_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_PWM2_SLP_EN_Pos (21UL) /*!< PCR EC_SLP_EN: PWM2_SLP_EN (Bit 21) */\r
-#define PCR_EC_SLP_EN_PWM2_SLP_EN_Msk (0x200000UL) /*!< PCR EC_SLP_EN: PWM2_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_PWM3_SLP_EN_Pos (22UL) /*!< PCR EC_SLP_EN: PWM3_SLP_EN (Bit 22) */\r
-#define PCR_EC_SLP_EN_PWM3_SLP_EN_Msk (0x400000UL) /*!< PCR EC_SLP_EN: PWM3_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_EC_REG_BANK_SLP_EN_Pos (29UL) /*!< PCR EC_SLP_EN: EC_REG_BANK_SLP_EN (Bit 29) */\r
-#define PCR_EC_SLP_EN_EC_REG_BANK_SLP_EN_Msk (0x20000000UL) /*!< PCR EC_SLP_EN: EC_REG_BANK_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_TIMER16_0_SLP_EN_Pos (30UL) /*!< PCR EC_SLP_EN: TIMER16_0_SLP_EN (Bit 30) */\r
-#define PCR_EC_SLP_EN_TIMER16_0_SLP_EN_Msk (0x40000000UL) /*!< PCR EC_SLP_EN: TIMER16_0_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN_TIMER16_1_SLP_EN_Pos (31UL) /*!< PCR EC_SLP_EN: TIMER16_1_SLP_EN (Bit 31) */\r
-#define PCR_EC_SLP_EN_TIMER16_1_SLP_EN_Msk (0x80000000UL) /*!< PCR EC_SLP_EN: TIMER16_1_SLP_EN (Bitfield-Mask: 0x01) */\r
-\r
-/* ----------------------------- PCR_EC_CLK_REQ_STS ----------------------------- */\r
-#define PCR_EC_CLK_REQ_STS_INT_CLK_REQ_Pos (0UL) /*!< PCR EC_CLK_REQ_STS: INT_CLK_REQ (Bit 0) */\r
-#define PCR_EC_CLK_REQ_STS_INT_CLK_REQ_Msk (0x1UL) /*!< PCR EC_CLK_REQ_STS: INT_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_PECI_CLK_REQ_Pos (1UL) /*!< PCR EC_CLK_REQ_STS: PECI_CLK_REQ (Bit 1) */\r
-#define PCR_EC_CLK_REQ_STS_PECI_CLK_REQ_Msk (0x2UL) /*!< PCR EC_CLK_REQ_STS: PECI_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_TACH0_CLK_REQ_Pos (2UL) /*!< PCR EC_CLK_REQ_STS: TACH0_CLK_REQ (Bit 2) */\r
-#define PCR_EC_CLK_REQ_STS_TACH0_CLK_REQ_Msk (0x4UL) /*!< PCR EC_CLK_REQ_STS: TACH0_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_PWM0_CLK_REQ_Pos (4UL) /*!< PCR EC_CLK_REQ_STS: PWM0_CLK_REQ (Bit 4) */\r
-#define PCR_EC_CLK_REQ_STS_PWM0_CLK_REQ_Msk (0x10UL) /*!< PCR EC_CLK_REQ_STS: PWM0_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_PMC_CLK_REQ_Pos (5UL) /*!< PCR EC_CLK_REQ_STS: PMC_CLK_REQ (Bit 5) */\r
-#define PCR_EC_CLK_REQ_STS_PMC_CLK_REQ_Msk (0x20UL) /*!< PCR EC_CLK_REQ_STS: PMC_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_DMA_CLK_REQ_Pos (6UL) /*!< PCR EC_CLK_REQ_STS: DMA_CLK_REQ (Bit 6) */\r
-#define PCR_EC_CLK_REQ_STS_DMA_CLK_REQ_Msk (0x40UL) /*!< PCR EC_CLK_REQ_STS: DMA_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_TFDP_CLK_REQ_Pos (7UL) /*!< PCR EC_CLK_REQ_STS: TFDP_CLK_REQ (Bit 7) */\r
-#define PCR_EC_CLK_REQ_STS_TFDP_CLK_REQ_Msk (0x80UL) /*!< PCR EC_CLK_REQ_STS: TFDP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_PROCESSOR_CLK_REQ_Pos (8UL) /*!< PCR EC_CLK_REQ_STS: PROCESSOR_CLK_REQ (Bit 8) */\r
-#define PCR_EC_CLK_REQ_STS_PROCESSOR_CLK_REQ_Msk (0x100UL) /*!< PCR EC_CLK_REQ_STS: PROCESSOR_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_WDT_CLK_REQ_Pos (9UL) /*!< PCR EC_CLK_REQ_STS: WDT_CLK_REQ (Bit 9) */\r
-#define PCR_EC_CLK_REQ_STS_WDT_CLK_REQ_Msk (0x200UL) /*!< PCR EC_CLK_REQ_STS: WDT_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_SMB0_CLK_REQ_Pos (10UL) /*!< PCR EC_CLK_REQ_STS: SMB0_CLK_REQ (Bit 10) */\r
-#define PCR_EC_CLK_REQ_STS_SMB0_CLK_REQ_Msk (0x400UL) /*!< PCR EC_CLK_REQ_STS: SMB0_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_TACH1_CLK_REQ_Pos (11UL) /*!< PCR EC_CLK_REQ_STS: TACH1_CLK_REQ (Bit 11) */\r
-#define PCR_EC_CLK_REQ_STS_TACH1_CLK_REQ_Msk (0x800UL) /*!< PCR EC_CLK_REQ_STS: TACH1_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_PWM1_CLK_REQ_Pos (20UL) /*!< PCR EC_CLK_REQ_STS: PWM1_CLK_REQ (Bit 20) */\r
-#define PCR_EC_CLK_REQ_STS_PWM1_CLK_REQ_Msk (0x100000UL) /*!< PCR EC_CLK_REQ_STS: PWM1_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_PWM2_CLK_REQ_Pos (21UL) /*!< PCR EC_CLK_REQ_STS: PWM2_CLK_REQ (Bit 21) */\r
-#define PCR_EC_CLK_REQ_STS_PWM2_CLK_REQ_Msk (0x200000UL) /*!< PCR EC_CLK_REQ_STS: PWM2_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_PWM3_CLK_REQ_Pos (22UL) /*!< PCR EC_CLK_REQ_STS: PWM3_CLK_REQ (Bit 22) */\r
-#define PCR_EC_CLK_REQ_STS_PWM3_CLK_REQ_Msk (0x400000UL) /*!< PCR EC_CLK_REQ_STS: PWM3_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_EC_REG_BANK_CLK_REQ_Pos (29UL) /*!< PCR EC_CLK_REQ_STS: EC_REG_BANK_CLK_REQ (Bit 29) */\r
-#define PCR_EC_CLK_REQ_STS_EC_REG_BANK_CLK_REQ_Msk (0x20000000UL) /*!< PCR EC_CLK_REQ_STS: EC_REG_BANK_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_TIMER16_0_CLK_REQ_Pos (30UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_0_CLK_REQ (Bit 30) */\r
-#define PCR_EC_CLK_REQ_STS_TIMER16_0_CLK_REQ_Msk (0x40000000UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ_STS_TIMER16_1_CLK_REQ_Pos (31UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_1_CLK_REQ (Bit 31) */\r
-#define PCR_EC_CLK_REQ_STS_TIMER16_1_CLK_REQ_Msk (0x80000000UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_1_CLK_REQ (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------- PCR_HOST_SLP_EN ------------------------------ */\r
-#define PCR_HOST_SLP_EN_LPC_SLP_EN_Pos (0UL) /*!< PCR HOST_SLP_EN: LPC_SLP_EN (Bit 0) */\r
-#define PCR_HOST_SLP_EN_LPC_SLP_EN_Msk (0x1UL) /*!< PCR HOST_SLP_EN: LPC_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_SLP_EN_UART_0_SLP_EN_Pos (1UL) /*!< PCR HOST_SLP_EN: UART_0_SLP_EN (Bit 1) */\r
-#define PCR_HOST_SLP_EN_UART_0_SLP_EN_Msk (0x2UL) /*!< PCR HOST_SLP_EN: UART_0_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_SLP_EN_GLBL_CFG_SLP_EN_Pos (12UL) /*!< PCR HOST_SLP_EN: GLBL_CFG_SLP_EN (Bit 12) */\r
-#define PCR_HOST_SLP_EN_GLBL_CFG_SLP_EN_Msk (0x1000UL) /*!< PCR HOST_SLP_EN: GLBL_CFG_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_SLP_EN_ACPI_EC_0_SLP_EN_Pos (13UL) /*!< PCR HOST_SLP_EN: ACPI_EC_0_SLP_EN (Bit 13) */\r
-#define PCR_HOST_SLP_EN_ACPI_EC_0_SLP_EN_Msk (0x2000UL) /*!< PCR HOST_SLP_EN: ACPI_EC_0_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_SLP_EN_ACPI_EC_1_SLP_EN_Pos (14UL) /*!< PCR HOST_SLP_EN: ACPI_EC_1_SLP_EN (Bit 14) */\r
-#define PCR_HOST_SLP_EN_ACPI_EC_1_SLP_EN_Msk (0x4000UL) /*!< PCR HOST_SLP_EN: ACPI_EC_1_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_SLP_EN_ACPI_PM1_SLP_EN_Pos (15UL) /*!< PCR HOST_SLP_EN: ACPI_PM1_SLP_EN (Bit 15) */\r
-#define PCR_HOST_SLP_EN_ACPI_PM1_SLP_EN_Msk (0x8000UL) /*!< PCR HOST_SLP_EN: ACPI_PM1_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_SLP_EN_KBCEM_SLP_EN_Pos (16UL) /*!< PCR HOST_SLP_EN: KBCEM_SLP_EN (Bit 16) */\r
-#define PCR_HOST_SLP_EN_KBCEM_SLP_EN_Msk (0x10000UL) /*!< PCR HOST_SLP_EN: KBCEM_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_SLP_EN_RTC_SLP_EN_Pos (18UL) /*!< PCR HOST_SLP_EN: RTC_SLP_EN (Bit 18) */\r
-#define PCR_HOST_SLP_EN_RTC_SLP_EN_Msk (0x40000UL) /*!< PCR HOST_SLP_EN: RTC_SLP_EN (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------ PCR_HOST_CLK_REQ ------------------------------ */\r
-#define PCR_HOST_CLK_REQ_LPC_CLK_REQ_Pos (0UL) /*!< PCR HOST_CLK_REQ: LPC_CLK_REQ (Bit 0) */\r
-#define PCR_HOST_CLK_REQ_LPC_CLK_REQ_Msk (0x1UL) /*!< PCR HOST_CLK_REQ: LPC_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_CLK_REQ_UART_0_CLK_REQ_Pos (1UL) /*!< PCR HOST_CLK_REQ: UART_0_CLK_REQ (Bit 1) */\r
-#define PCR_HOST_CLK_REQ_UART_0_CLK_REQ_Msk (0x2UL) /*!< PCR HOST_CLK_REQ: UART_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_CLK_REQ_GLBL_CFG_CLK_REQ_Pos (12UL) /*!< PCR HOST_CLK_REQ: GLBL_CFG_CLK_REQ (Bit 12) */\r
-#define PCR_HOST_CLK_REQ_GLBL_CFG_CLK_REQ_Msk (0x1000UL) /*!< PCR HOST_CLK_REQ: GLBL_CFG_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_CLK_REQ_ACPI_EC_0_CLK_REQ_Pos (13UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_0_CLK_REQ (Bit 13) */\r
-#define PCR_HOST_CLK_REQ_ACPI_EC_0_CLK_REQ_Msk (0x2000UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_CLK_REQ_ACPI_EC_1_CLK_REQ_Pos (14UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_1_CLK_REQ (Bit 14) */\r
-#define PCR_HOST_CLK_REQ_ACPI_EC_1_CLK_REQ_Msk (0x4000UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_1_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_CLK_REQ_ACPI_PM1_CLK_REQ_Pos (15UL) /*!< PCR HOST_CLK_REQ: ACPI_PM1_CLK_REQ (Bit 15) */\r
-#define PCR_HOST_CLK_REQ_ACPI_PM1_CLK_REQ_Msk (0x8000UL) /*!< PCR HOST_CLK_REQ: ACPI_PM1_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_CLK_REQ_KBCEM_CLK_REQ_Pos (16UL) /*!< PCR HOST_CLK_REQ: KBCEM_CLK_REQ (Bit 16) */\r
-#define PCR_HOST_CLK_REQ_KBCEM_CLK_REQ_Msk (0x10000UL) /*!< PCR HOST_CLK_REQ: KBCEM_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_CLK_REQ_RTC_CLK_REQ_Pos (18UL) /*!< PCR HOST_CLK_REQ: RTC_CLK_REQ (Bit 18) */\r
-#define PCR_HOST_CLK_REQ_RTC_CLK_REQ_Msk (0x40000UL) /*!< PCR HOST_CLK_REQ: RTC_CLK_REQ (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------ PCR_SYS_SLP_CNTRL ----------------------------- */\r
-#define PCR_SYS_SLP_CNTRL_ROSC_PD_Pos (0UL) /*!< PCR SYS_SLP_CNTRL: ROSC_PD (Bit 0) */\r
-#define PCR_SYS_SLP_CNTRL_ROSC_PD_Msk (0x1UL) /*!< PCR SYS_SLP_CNTRL: ROSC_PD (Bitfield-Mask: 0x01) */\r
-#define PCR_SYS_SLP_CNTRL_ROSC_GATE_Pos (1UL) /*!< PCR SYS_SLP_CNTRL: ROSC_GATE (Bit 1) */\r
-#define PCR_SYS_SLP_CNTRL_ROSC_GATE_Msk (0x2UL) /*!< PCR SYS_SLP_CNTRL: ROSC_GATE (Bitfield-Mask: 0x01) */\r
-#define PCR_SYS_SLP_CNTRL_REGULATOR_STDBY_Pos (2UL) /*!< PCR SYS_SLP_CNTRL: REGULATOR_STDBY (Bit 2) */\r
-#define PCR_SYS_SLP_CNTRL_REGULATOR_STDBY_Msk (0x4UL) /*!< PCR SYS_SLP_CNTRL: REGULATOR_STDBY (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------- PCR_EC_SLP_EN2 ------------------------------- */\r
-#define PCR_EC_SLP_EN2_ADC_SLP_EN_Pos (3UL) /*!< PCR EC_SLP_EN2: ADC_SLP_EN (Bit 3) */\r
-#define PCR_EC_SLP_EN2_ADC_SLP_EN_Msk (0x8UL) /*!< PCR EC_SLP_EN2: ADC_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_PS2_0_SLP_EN_Pos (5UL) /*!< PCR EC_SLP_EN2: PS2_0_SLP_EN (Bit 5) */\r
-#define PCR_EC_SLP_EN2_PS2_0_SLP_EN_Msk (0x20UL) /*!< PCR EC_SLP_EN2: PS2_0_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_PS2_1_SLP_EN_Pos (6UL) /*!< PCR EC_SLP_EN2: PS2_1_SLP_EN (Bit 6) */\r
-#define PCR_EC_SLP_EN2_PS2_1_SLP_EN_Msk (0x40UL) /*!< PCR EC_SLP_EN2: PS2_1_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_PS2_2_SLP_EN_Pos (7UL) /*!< PCR EC_SLP_EN2: PS2_2_SLP_EN (Bit 7) */\r
-#define PCR_EC_SLP_EN2_PS2_2_SLP_EN_Msk (0x80UL) /*!< PCR EC_SLP_EN2: PS2_2_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_PS2_3_SLP_EN_Pos (8UL) /*!< PCR EC_SLP_EN2: PS2_3_SLP_EN (Bit 8) */\r
-#define PCR_EC_SLP_EN2_PS2_3_SLP_EN_Msk (0x100UL) /*!< PCR EC_SLP_EN2: PS2_3_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_SPI0_SLP_EN_Pos (9UL) /*!< PCR EC_SLP_EN2: SPI0_SLP_EN (Bit 9) */\r
-#define PCR_EC_SLP_EN2_SPI0_SLP_EN_Msk (0x200UL) /*!< PCR EC_SLP_EN2: SPI0_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_HTIMER_SLP_EN_Pos (10UL) /*!< PCR EC_SLP_EN2: HTIMER_SLP_EN (Bit 10) */\r
-#define PCR_EC_SLP_EN2_HTIMER_SLP_EN_Msk (0x400UL) /*!< PCR EC_SLP_EN2: HTIMER_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_KEYSCAN_SLP_EN_Pos (11UL) /*!< PCR EC_SLP_EN2: KEYSCAN_SLP_EN (Bit 11) */\r
-#define PCR_EC_SLP_EN2_KEYSCAN_SLP_EN_Msk (0x800UL) /*!< PCR EC_SLP_EN2: KEYSCAN_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_RPMPWM_SLP_EN_Pos (12UL) /*!< PCR EC_SLP_EN2: RPMPWM_SLP_EN (Bit 12) */\r
-#define PCR_EC_SLP_EN2_RPMPWM_SLP_EN_Msk (0x1000UL) /*!< PCR EC_SLP_EN2: RPMPWM_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_SMB1_SLP_EN_Pos (13UL) /*!< PCR EC_SLP_EN2: SMB1_SLP_EN (Bit 13) */\r
-#define PCR_EC_SLP_EN2_SMB1_SLP_EN_Msk (0x2000UL) /*!< PCR EC_SLP_EN2: SMB1_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_SMB2_SLP_EN_Pos (14UL) /*!< PCR EC_SLP_EN2: SMB2_SLP_EN (Bit 14) */\r
-#define PCR_EC_SLP_EN2_SMB2_SLP_EN_Msk (0x4000UL) /*!< PCR EC_SLP_EN2: SMB2_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_SMB3_SLP_EN_Pos (15UL) /*!< PCR EC_SLP_EN2: SMB3_SLP_EN (Bit 15) */\r
-#define PCR_EC_SLP_EN2_SMB3_SLP_EN_Msk (0x8000UL) /*!< PCR EC_SLP_EN2: SMB3_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_LED0_SLP_EN_Pos (16UL) /*!< PCR EC_SLP_EN2: LED0_SLP_EN (Bit 16) */\r
-#define PCR_EC_SLP_EN2_LED0_SLP_EN_Msk (0x10000UL) /*!< PCR EC_SLP_EN2: LED0_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_LED1_SLP_EN_Pos (17UL) /*!< PCR EC_SLP_EN2: LED1_SLP_EN (Bit 17) */\r
-#define PCR_EC_SLP_EN2_LED1_SLP_EN_Msk (0x20000UL) /*!< PCR EC_SLP_EN2: LED1_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_LED2_SLP_EN_Pos (18UL) /*!< PCR EC_SLP_EN2: LED2_SLP_EN (Bit 18) */\r
-#define PCR_EC_SLP_EN2_LED2_SLP_EN_Msk (0x40000UL) /*!< PCR EC_SLP_EN2: LED2_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_BCM_SLP_EN_Pos (19UL) /*!< PCR EC_SLP_EN2: BCM_SLP_EN (Bit 19) */\r
-#define PCR_EC_SLP_EN2_BCM_SLP_EN_Msk (0x80000UL) /*!< PCR EC_SLP_EN2: BCM_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_SPI1_SLP_EN_Pos (20UL) /*!< PCR EC_SLP_EN2: SPI1_SLP_EN (Bit 20) */\r
-#define PCR_EC_SLP_EN2_SPI1_SLP_EN_Msk (0x100000UL) /*!< PCR EC_SLP_EN2: SPI1_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_TIMER16_2_SLP_EN_Pos (21UL) /*!< PCR EC_SLP_EN2: TIMER16_2_SLP_EN (Bit 21) */\r
-#define PCR_EC_SLP_EN2_TIMER16_2_SLP_EN_Msk (0x200000UL) /*!< PCR EC_SLP_EN2: TIMER16_2_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_TIMER16_3_SLP_EN_Pos (22UL) /*!< PCR EC_SLP_EN2: TIMER16_3_SLP_EN (Bit 22) */\r
-#define PCR_EC_SLP_EN2_TIMER16_3_SLP_EN_Msk (0x400000UL) /*!< PCR EC_SLP_EN2: TIMER16_3_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_TIMER32_0_SLP_EN_Pos (23UL) /*!< PCR EC_SLP_EN2: TIMER32_0_SLP_EN (Bit 23) */\r
-#define PCR_EC_SLP_EN2_TIMER32_0_SLP_EN_Msk (0x800000UL) /*!< PCR EC_SLP_EN2: TIMER32_0_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_TIMER32_1_SLP_EN_Pos (24UL) /*!< PCR EC_SLP_EN2: TIMER32_1_SLP_EN (Bit 24) */\r
-#define PCR_EC_SLP_EN2_TIMER32_1_SLP_EN_Msk (0x1000000UL) /*!< PCR EC_SLP_EN2: TIMER32_1_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_SLP_EN2_LED3_SLP_EN_Pos (25UL) /*!< PCR EC_SLP_EN2: LED3_SLP_EN (Bit 25) */\r
-#define PCR_EC_SLP_EN2_LED3_SLP_EN_Msk (0x2000000UL) /*!< PCR EC_SLP_EN2: LED3_SLP_EN (Bitfield-Mask: 0x01) */\r
-\r
-/* ----------------------------- PCR_EC_CLK_REQ2_STS ---------------------------- */\r
-#define PCR_EC_CLK_REQ2_STS_ADC_CLK_REQ_Pos (3UL) /*!< PCR EC_CLK_REQ2_STS: ADC_CLK_REQ (Bit 3) */\r
-#define PCR_EC_CLK_REQ2_STS_ADC_CLK_REQ_Msk (0x8UL) /*!< PCR EC_CLK_REQ2_STS: ADC_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_PS2_0_SLP_CLK_REQ_Pos (5UL) /*!< PCR EC_CLK_REQ2_STS: PS2_0_SLP_CLK_REQ (Bit 5) */\r
-#define PCR_EC_CLK_REQ2_STS_PS2_0_SLP_CLK_REQ_Msk (0x20UL) /*!< PCR EC_CLK_REQ2_STS: PS2_0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_PS2_1_SLP_CLK_REQ_Pos (6UL) /*!< PCR EC_CLK_REQ2_STS: PS2_1_SLP_CLK_REQ (Bit 6) */\r
-#define PCR_EC_CLK_REQ2_STS_PS2_1_SLP_CLK_REQ_Msk (0x40UL) /*!< PCR EC_CLK_REQ2_STS: PS2_1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_PS2_2_SLP_CLK_REQ_Pos (7UL) /*!< PCR EC_CLK_REQ2_STS: PS2_2_SLP_CLK_REQ (Bit 7) */\r
-#define PCR_EC_CLK_REQ2_STS_PS2_2_SLP_CLK_REQ_Msk (0x80UL) /*!< PCR EC_CLK_REQ2_STS: PS2_2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_PS2_3_SLP_CLK_REQ_Pos (8UL) /*!< PCR EC_CLK_REQ2_STS: PS2_3_SLP_CLK_REQ (Bit 8) */\r
-#define PCR_EC_CLK_REQ2_STS_PS2_3_SLP_CLK_REQ_Msk (0x100UL) /*!< PCR EC_CLK_REQ2_STS: PS2_3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_SPI0_SLP_CLK_REQ_Pos (9UL) /*!< PCR EC_CLK_REQ2_STS: SPI0_SLP_CLK_REQ (Bit 9) */\r
-#define PCR_EC_CLK_REQ2_STS_SPI0_SLP_CLK_REQ_Msk (0x200UL) /*!< PCR EC_CLK_REQ2_STS: SPI0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_HTIMER_SLP_CLK_REQ_Pos (10UL) /*!< PCR EC_CLK_REQ2_STS: HTIMER_SLP_CLK_REQ (Bit 10) */\r
-#define PCR_EC_CLK_REQ2_STS_HTIMER_SLP_CLK_REQ_Msk (0x400UL) /*!< PCR EC_CLK_REQ2_STS: HTIMER_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_KEYSCAN_SLP_CLK_REQ_Pos (11UL) /*!< PCR EC_CLK_REQ2_STS: KEYSCAN_SLP_CLK_REQ (Bit 11) */\r
-#define PCR_EC_CLK_REQ2_STS_KEYSCAN_SLP_CLK_REQ_Msk (0x800UL) /*!< PCR EC_CLK_REQ2_STS: KEYSCAN_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_RPMPWM_SLP_CLK_REQ_Pos (12UL) /*!< PCR EC_CLK_REQ2_STS: RPMPWM_SLP_CLK_REQ (Bit 12) */\r
-#define PCR_EC_CLK_REQ2_STS_RPMPWM_SLP_CLK_REQ_Msk (0x1000UL) /*!< PCR EC_CLK_REQ2_STS: RPMPWM_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_SMB1_SLP_CLK_REQ_Pos (13UL) /*!< PCR EC_CLK_REQ2_STS: SMB1_SLP_CLK_REQ (Bit 13) */\r
-#define PCR_EC_CLK_REQ2_STS_SMB1_SLP_CLK_REQ_Msk (0x2000UL) /*!< PCR EC_CLK_REQ2_STS: SMB1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_SMB2_SLP_CLK_REQ_Pos (14UL) /*!< PCR EC_CLK_REQ2_STS: SMB2_SLP_CLK_REQ (Bit 14) */\r
-#define PCR_EC_CLK_REQ2_STS_SMB2_SLP_CLK_REQ_Msk (0x4000UL) /*!< PCR EC_CLK_REQ2_STS: SMB2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_SMB3_SLP_CLK_REQ_Pos (15UL) /*!< PCR EC_CLK_REQ2_STS: SMB3_SLP_CLK_REQ (Bit 15) */\r
-#define PCR_EC_CLK_REQ2_STS_SMB3_SLP_CLK_REQ_Msk (0x8000UL) /*!< PCR EC_CLK_REQ2_STS: SMB3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_LED0_SLP_CLK_REQ_Pos (16UL) /*!< PCR EC_CLK_REQ2_STS: LED0_SLP_CLK_REQ (Bit 16) */\r
-#define PCR_EC_CLK_REQ2_STS_LED0_SLP_CLK_REQ_Msk (0x10000UL) /*!< PCR EC_CLK_REQ2_STS: LED0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_LED1_SLP_CLK_REQ_Pos (17UL) /*!< PCR EC_CLK_REQ2_STS: LED1_SLP_CLK_REQ (Bit 17) */\r
-#define PCR_EC_CLK_REQ2_STS_LED1_SLP_CLK_REQ_Msk (0x20000UL) /*!< PCR EC_CLK_REQ2_STS: LED1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_LED2_SLP_CLK_REQ_Pos (18UL) /*!< PCR EC_CLK_REQ2_STS: LED2_SLP_CLK_REQ (Bit 18) */\r
-#define PCR_EC_CLK_REQ2_STS_LED2_SLP_CLK_REQ_Msk (0x40000UL) /*!< PCR EC_CLK_REQ2_STS: LED2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_BCM_SLP_CLK_REQ_Pos (19UL) /*!< PCR EC_CLK_REQ2_STS: BCM_SLP_CLK_REQ (Bit 19) */\r
-#define PCR_EC_CLK_REQ2_STS_BCM_SLP_CLK_REQ_Msk (0x80000UL) /*!< PCR EC_CLK_REQ2_STS: BCM_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_SPI1_SLP_CLK_REQ_Pos (20UL) /*!< PCR EC_CLK_REQ2_STS: SPI1_SLP_CLK_REQ (Bit 20) */\r
-#define PCR_EC_CLK_REQ2_STS_SPI1_SLP_CLK_REQ_Msk (0x100000UL) /*!< PCR EC_CLK_REQ2_STS: SPI1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_TIMER16_2_SLP_CLK_REQ_Pos (21UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_2_SLP_CLK_REQ (Bit 21) */\r
-#define PCR_EC_CLK_REQ2_STS_TIMER16_2_SLP_CLK_REQ_Msk (0x200000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_TIMER16_3_SLP_CLK_REQ_Pos (22UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_3_SLP_CLK_REQ (Bit 22) */\r
-#define PCR_EC_CLK_REQ2_STS_TIMER16_3_SLP_CLK_REQ_Msk (0x400000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_TIMER32_0_SLP_CLK_REQ_Pos (23UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_0_SLP_CLK_REQ (Bit 23) */\r
-#define PCR_EC_CLK_REQ2_STS_TIMER32_0_SLP_CLK_REQ_Msk (0x800000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_TIMER32_1_SLP_CLK_REQ_Pos (24UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_1_SLP_CLK_REQ (Bit 24) */\r
-#define PCR_EC_CLK_REQ2_STS_TIMER32_1_SLP_CLK_REQ_Msk (0x1000000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_CLK_REQ2_STS_LED3_SLP_CLK_REQ_Pos (25UL) /*!< PCR EC_CLK_REQ2_STS: LED3_SLP_CLK_REQ (Bit 25) */\r
-#define PCR_EC_CLK_REQ2_STS_LED3_SLP_CLK_REQ_Msk (0x2000000UL) /*!< PCR EC_CLK_REQ2_STS: LED3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------- PCR_CHIP_OSC_ID ------------------------------ */\r
-#define PCR_CHIP_OSC_ID_OSC_LOCK_Pos (8UL) /*!< PCR CHIP_OSC_ID: OSC_LOCK (Bit 8) */\r
-#define PCR_CHIP_OSC_ID_OSC_LOCK_Msk (0x100UL) /*!< PCR CHIP_OSC_ID: OSC_LOCK (Bitfield-Mask: 0x01) */\r
-\r
-/* ---------------------------- PCR_CHIP_PWR_RST_STS ---------------------------- */\r
-#define PCR_CHIP_PWR_RST_STS_VCC_nRST_Pos (2UL) /*!< PCR CHIP_PWR_RST_STS: VCC_nRST (Bit 2) */\r
-#define PCR_CHIP_PWR_RST_STS_VCC_nRST_Msk (0x4UL) /*!< PCR CHIP_PWR_RST_STS: VCC_nRST (Bitfield-Mask: 0x01) */\r
-#define PCR_CHIP_PWR_RST_STS_SIO_nRST_Pos (3UL) /*!< PCR CHIP_PWR_RST_STS: SIO_nRST (Bit 3) */\r
-#define PCR_CHIP_PWR_RST_STS_SIO_nRST_Msk (0x8UL) /*!< PCR CHIP_PWR_RST_STS: SIO_nRST (Bitfield-Mask: 0x01) */\r
-#define PCR_CHIP_PWR_RST_STS_VBAT_RST_Pos (5UL) /*!< PCR CHIP_PWR_RST_STS: VBAT_RST (Bit 5) */\r
-#define PCR_CHIP_PWR_RST_STS_VBAT_RST_Msk (0x20UL) /*!< PCR CHIP_PWR_RST_STS: VBAT_RST (Bitfield-Mask: 0x01) */\r
-#define PCR_CHIP_PWR_RST_STS_VCC1_RST_Pos (6UL) /*!< PCR CHIP_PWR_RST_STS: VCC1_RST (Bit 6) */\r
-#define PCR_CHIP_PWR_RST_STS_VCC1_RST_Msk (0x40UL) /*!< PCR CHIP_PWR_RST_STS: VCC1_RST (Bitfield-Mask: 0x01) */\r
-#define PCR_CHIP_PWR_RST_STS__32K_ACTIVE_Pos (10UL) /*!< PCR CHIP_PWR_RST_STS: _32K_ACTIVE (Bit 10) */\r
-#define PCR_CHIP_PWR_RST_STS__32K_ACTIVE_Msk (0x400UL) /*!< PCR CHIP_PWR_RST_STS: _32K_ACTIVE (Bitfield-Mask: 0x01) */\r
-#define PCR_CHIP_PWR_RST_STS_PCICLK_ACTIVE_Pos (11UL) /*!< PCR CHIP_PWR_RST_STS: PCICLK_ACTIVE (Bit 11) */\r
-#define PCR_CHIP_PWR_RST_STS_PCICLK_ACTIVE_Msk (0x800UL) /*!< PCR CHIP_PWR_RST_STS: PCICLK_ACTIVE (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------- PCR_HOST_RST_EN ------------------------------ */\r
-#define PCR_HOST_RST_EN_LPC_RST_EN_Pos (0UL) /*!< PCR HOST_RST_EN: LPC_RST_EN (Bit 0) */\r
-#define PCR_HOST_RST_EN_LPC_RST_EN_Msk (0x1UL) /*!< PCR HOST_RST_EN: LPC_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_RST_EN_UART_0_RST_EN_Pos (1UL) /*!< PCR HOST_RST_EN: UART_0_RST_EN (Bit 1) */\r
-#define PCR_HOST_RST_EN_UART_0_RST_EN_Msk (0x2UL) /*!< PCR HOST_RST_EN: UART_0_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_RST_EN_GLBL_CFG_RST_EN_Pos (12UL) /*!< PCR HOST_RST_EN: GLBL_CFG_RST_EN (Bit 12) */\r
-#define PCR_HOST_RST_EN_GLBL_CFG_RST_EN_Msk (0x1000UL) /*!< PCR HOST_RST_EN: GLBL_CFG_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_RST_EN_ACPI_EC_0_RST_EN_Pos (13UL) /*!< PCR HOST_RST_EN: ACPI_EC_0_RST_EN (Bit 13) */\r
-#define PCR_HOST_RST_EN_ACPI_EC_0_RST_EN_Msk (0x2000UL) /*!< PCR HOST_RST_EN: ACPI_EC_0_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_RST_EN_ACPI_EC_1_RST_EN_Pos (14UL) /*!< PCR HOST_RST_EN: ACPI_EC_1_RST_EN (Bit 14) */\r
-#define PCR_HOST_RST_EN_ACPI_EC_1_RST_EN_Msk (0x4000UL) /*!< PCR HOST_RST_EN: ACPI_EC_1_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_RST_EN_ACPI_PM1_RST_EN_Pos (15UL) /*!< PCR HOST_RST_EN: ACPI_PM1_RST_EN (Bit 15) */\r
-#define PCR_HOST_RST_EN_ACPI_PM1_RST_EN_Msk (0x8000UL) /*!< PCR HOST_RST_EN: ACPI_PM1_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_RST_EN_KBCEM_RST_EN_Pos (16UL) /*!< PCR HOST_RST_EN: KBCEM_RST_EN (Bit 16) */\r
-#define PCR_HOST_RST_EN_KBCEM_RST_EN_Msk (0x10000UL) /*!< PCR HOST_RST_EN: KBCEM_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_HOST_RST_EN_RTC_RST_EN_Pos (18UL) /*!< PCR HOST_RST_EN: RTC_RST_EN (Bit 18) */\r
-#define PCR_HOST_RST_EN_RTC_RST_EN_Msk (0x40000UL) /*!< PCR HOST_RST_EN: RTC_RST_EN (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- PCR_EC_RST_EN ------------------------------- */\r
-#define PCR_EC_RST_EN_INT_RST_EN_Pos (0UL) /*!< PCR EC_RST_EN: INT_RST_EN (Bit 0) */\r
-#define PCR_EC_RST_EN_INT_RST_EN_Msk (0x1UL) /*!< PCR EC_RST_EN: INT_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_PECI_RST_EN_Pos (1UL) /*!< PCR EC_RST_EN: PECI_RST_EN (Bit 1) */\r
-#define PCR_EC_RST_EN_PECI_RST_EN_Msk (0x2UL) /*!< PCR EC_RST_EN: PECI_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_TACH0_RST_EN_Pos (2UL) /*!< PCR EC_RST_EN: TACH0_RST_EN (Bit 2) */\r
-#define PCR_EC_RST_EN_TACH0_RST_EN_Msk (0x4UL) /*!< PCR EC_RST_EN: TACH0_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_PWM0_RST_EN_Pos (4UL) /*!< PCR EC_RST_EN: PWM0_RST_EN (Bit 4) */\r
-#define PCR_EC_RST_EN_PWM0_RST_EN_Msk (0x10UL) /*!< PCR EC_RST_EN: PWM0_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_PMC_RST_EN_Pos (5UL) /*!< PCR EC_RST_EN: PMC_RST_EN (Bit 5) */\r
-#define PCR_EC_RST_EN_PMC_RST_EN_Msk (0x20UL) /*!< PCR EC_RST_EN: PMC_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_DMA_RST_EN_Pos (6UL) /*!< PCR EC_RST_EN: DMA_RST_EN (Bit 6) */\r
-#define PCR_EC_RST_EN_DMA_RST_EN_Msk (0x40UL) /*!< PCR EC_RST_EN: DMA_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_TFDP_RST_EN_Pos (7UL) /*!< PCR EC_RST_EN: TFDP_RST_EN (Bit 7) */\r
-#define PCR_EC_RST_EN_TFDP_RST_EN_Msk (0x80UL) /*!< PCR EC_RST_EN: TFDP_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_PROCESSOR_RST_EN_Pos (8UL) /*!< PCR EC_RST_EN: PROCESSOR_RST_EN (Bit 8) */\r
-#define PCR_EC_RST_EN_PROCESSOR_RST_EN_Msk (0x100UL) /*!< PCR EC_RST_EN: PROCESSOR_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_WDT_RST_EN_Pos (9UL) /*!< PCR EC_RST_EN: WDT_RST_EN (Bit 9) */\r
-#define PCR_EC_RST_EN_WDT_RST_EN_Msk (0x200UL) /*!< PCR EC_RST_EN: WDT_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_SMB0_RST_EN_Pos (10UL) /*!< PCR EC_RST_EN: SMB0_RST_EN (Bit 10) */\r
-#define PCR_EC_RST_EN_SMB0_RST_EN_Msk (0x400UL) /*!< PCR EC_RST_EN: SMB0_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_TACH1_RST_EN_Pos (11UL) /*!< PCR EC_RST_EN: TACH1_RST_EN (Bit 11) */\r
-#define PCR_EC_RST_EN_TACH1_RST_EN_Msk (0x800UL) /*!< PCR EC_RST_EN: TACH1_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_PWM1_RST_EN_Pos (20UL) /*!< PCR EC_RST_EN: PWM1_RST_EN (Bit 20) */\r
-#define PCR_EC_RST_EN_PWM1_RST_EN_Msk (0x100000UL) /*!< PCR EC_RST_EN: PWM1_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_PWM2_RST_EN_Pos (21UL) /*!< PCR EC_RST_EN: PWM2_RST_EN (Bit 21) */\r
-#define PCR_EC_RST_EN_PWM2_RST_EN_Msk (0x200000UL) /*!< PCR EC_RST_EN: PWM2_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_PWM3_RST_EN_Pos (22UL) /*!< PCR EC_RST_EN: PWM3_RST_EN (Bit 22) */\r
-#define PCR_EC_RST_EN_PWM3_RST_EN_Msk (0x400000UL) /*!< PCR EC_RST_EN: PWM3_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_EC_REG_BANK_RST_EN_Pos (29UL) /*!< PCR EC_RST_EN: EC_REG_BANK_RST_EN (Bit 29) */\r
-#define PCR_EC_RST_EN_EC_REG_BANK_RST_EN_Msk (0x20000000UL) /*!< PCR EC_RST_EN: EC_REG_BANK_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_TIMER16_0_RST_EN_Pos (30UL) /*!< PCR EC_RST_EN: TIMER16_0_RST_EN (Bit 30) */\r
-#define PCR_EC_RST_EN_TIMER16_0_RST_EN_Msk (0x40000000UL) /*!< PCR EC_RST_EN: TIMER16_0_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN_TIMER16_1_RST_EN_Pos (31UL) /*!< PCR EC_RST_EN: TIMER16_1_RST_EN (Bit 31) */\r
-#define PCR_EC_RST_EN_TIMER16_1_RST_EN_Msk (0x80000000UL) /*!< PCR EC_RST_EN: TIMER16_1_RST_EN (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------- PCR_EC_RST_EN2 ------------------------------- */\r
-#define PCR_EC_RST_EN2_ADC_RST_EN_Pos (3UL) /*!< PCR EC_RST_EN2: ADC_RST_EN (Bit 3) */\r
-#define PCR_EC_RST_EN2_ADC_RST_EN_Msk (0x8UL) /*!< PCR EC_RST_EN2: ADC_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_PS2_0_RST_EN_Pos (5UL) /*!< PCR EC_RST_EN2: PS2_0_RST_EN (Bit 5) */\r
-#define PCR_EC_RST_EN2_PS2_0_RST_EN_Msk (0x20UL) /*!< PCR EC_RST_EN2: PS2_0_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_PS2_1_RST_EN_Pos (6UL) /*!< PCR EC_RST_EN2: PS2_1_RST_EN (Bit 6) */\r
-#define PCR_EC_RST_EN2_PS2_1_RST_EN_Msk (0x40UL) /*!< PCR EC_RST_EN2: PS2_1_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_PS2_2_RST_EN_Pos (7UL) /*!< PCR EC_RST_EN2: PS2_2_RST_EN (Bit 7) */\r
-#define PCR_EC_RST_EN2_PS2_2_RST_EN_Msk (0x80UL) /*!< PCR EC_RST_EN2: PS2_2_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_PS2_3_RST_EN_Pos (8UL) /*!< PCR EC_RST_EN2: PS2_3_RST_EN (Bit 8) */\r
-#define PCR_EC_RST_EN2_PS2_3_RST_EN_Msk (0x100UL) /*!< PCR EC_RST_EN2: PS2_3_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_SPI0_SLP_EN_Pos (9UL) /*!< PCR EC_RST_EN2: SPI0_SLP_EN (Bit 9) */\r
-#define PCR_EC_RST_EN2_SPI0_SLP_EN_Msk (0x200UL) /*!< PCR EC_RST_EN2: SPI0_SLP_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_HTIMER_RST_EN_Pos (10UL) /*!< PCR EC_RST_EN2: HTIMER_RST_EN (Bit 10) */\r
-#define PCR_EC_RST_EN2_HTIMER_RST_EN_Msk (0x400UL) /*!< PCR EC_RST_EN2: HTIMER_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_KEYSCAN_RST_EN_Pos (11UL) /*!< PCR EC_RST_EN2: KEYSCAN_RST_EN (Bit 11) */\r
-#define PCR_EC_RST_EN2_KEYSCAN_RST_EN_Msk (0x800UL) /*!< PCR EC_RST_EN2: KEYSCAN_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_RPMPWM_RST_EN_Pos (12UL) /*!< PCR EC_RST_EN2: RPMPWM_RST_EN (Bit 12) */\r
-#define PCR_EC_RST_EN2_RPMPWM_RST_EN_Msk (0x1000UL) /*!< PCR EC_RST_EN2: RPMPWM_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_SMB1_RST_EN_Pos (13UL) /*!< PCR EC_RST_EN2: SMB1_RST_EN (Bit 13) */\r
-#define PCR_EC_RST_EN2_SMB1_RST_EN_Msk (0x2000UL) /*!< PCR EC_RST_EN2: SMB1_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_SMB2_RST_EN_Pos (14UL) /*!< PCR EC_RST_EN2: SMB2_RST_EN (Bit 14) */\r
-#define PCR_EC_RST_EN2_SMB2_RST_EN_Msk (0x4000UL) /*!< PCR EC_RST_EN2: SMB2_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_SMB3_RST_EN_Pos (15UL) /*!< PCR EC_RST_EN2: SMB3_RST_EN (Bit 15) */\r
-#define PCR_EC_RST_EN2_SMB3_RST_EN_Msk (0x8000UL) /*!< PCR EC_RST_EN2: SMB3_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_LED0_RST_EN_Pos (16UL) /*!< PCR EC_RST_EN2: LED0_RST_EN (Bit 16) */\r
-#define PCR_EC_RST_EN2_LED0_RST_EN_Msk (0x10000UL) /*!< PCR EC_RST_EN2: LED0_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_LED1_RST_EN_Pos (17UL) /*!< PCR EC_RST_EN2: LED1_RST_EN (Bit 17) */\r
-#define PCR_EC_RST_EN2_LED1_RST_EN_Msk (0x20000UL) /*!< PCR EC_RST_EN2: LED1_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_LED2_RST_EN_Pos (18UL) /*!< PCR EC_RST_EN2: LED2_RST_EN (Bit 18) */\r
-#define PCR_EC_RST_EN2_LED2_RST_EN_Msk (0x40000UL) /*!< PCR EC_RST_EN2: LED2_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_BCM_RST_EN_Pos (19UL) /*!< PCR EC_RST_EN2: BCM_RST_EN (Bit 19) */\r
-#define PCR_EC_RST_EN2_BCM_RST_EN_Msk (0x80000UL) /*!< PCR EC_RST_EN2: BCM_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_SPI1_RST_EN_Pos (20UL) /*!< PCR EC_RST_EN2: SPI1_RST_EN (Bit 20) */\r
-#define PCR_EC_RST_EN2_SPI1_RST_EN_Msk (0x100000UL) /*!< PCR EC_RST_EN2: SPI1_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_TIMER16_2_RST_EN_Pos (21UL) /*!< PCR EC_RST_EN2: TIMER16_2_RST_EN (Bit 21) */\r
-#define PCR_EC_RST_EN2_TIMER16_2_RST_EN_Msk (0x200000UL) /*!< PCR EC_RST_EN2: TIMER16_2_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_TIMER16_3_RST_EN_Pos (22UL) /*!< PCR EC_RST_EN2: TIMER16_3_RST_EN (Bit 22) */\r
-#define PCR_EC_RST_EN2_TIMER16_3_RST_EN_Msk (0x400000UL) /*!< PCR EC_RST_EN2: TIMER16_3_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_TIMER32_0_RST_EN_Pos (23UL) /*!< PCR EC_RST_EN2: TIMER32_0_RST_EN (Bit 23) */\r
-#define PCR_EC_RST_EN2_TIMER32_0_RST_EN_Msk (0x800000UL) /*!< PCR EC_RST_EN2: TIMER32_0_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_TIMER32_1_RST_EN_Pos (24UL) /*!< PCR EC_RST_EN2: TIMER32_1_RST_EN (Bit 24) */\r
-#define PCR_EC_RST_EN2_TIMER32_1_RST_EN_Msk (0x1000000UL) /*!< PCR EC_RST_EN2: TIMER32_1_RST_EN (Bitfield-Mask: 0x01) */\r
-#define PCR_EC_RST_EN2_LED3_RST_EN_Pos (25UL) /*!< PCR EC_RST_EN2: LED3_RST_EN (Bit 25) */\r
-#define PCR_EC_RST_EN2_LED3_RST_EN_Msk (0x2000000UL) /*!< PCR EC_RST_EN2: LED3_RST_EN (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------ PCR_PWR_RST_CTRL ------------------------------ */\r
-#define PCR_PWR_RST_CTRL_IRESET_OUT_Pos (0UL) /*!< PCR PWR_RST_CTRL: IRESET_OUT (Bit 0) */\r
-#define PCR_PWR_RST_CTRL_IRESET_OUT_Msk (0x1UL) /*!< PCR PWR_RST_CTRL: IRESET_OUT (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'VBAT' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- VBAT_PFR_STS -------------------------------- */\r
-#define VBAT_PFR_STS_DET32K_IN_Pos (0UL) /*!< VBAT PFR_STS: DET32K_IN (Bit 0) */\r
-#define VBAT_PFR_STS_DET32K_IN_Msk (0x1UL) /*!< VBAT PFR_STS: DET32K_IN (Bitfield-Mask: 0x01) */\r
-#define VBAT_PFR_STS_WDT_Pos (5UL) /*!< VBAT PFR_STS: WDT (Bit 5) */\r
-#define VBAT_PFR_STS_WDT_Msk (0x20UL) /*!< VBAT PFR_STS: WDT (Bitfield-Mask: 0x01) */\r
-#define VBAT_PFR_STS_VBAT_RST_Pos (7UL) /*!< VBAT PFR_STS: VBAT_RST (Bit 7) */\r
-#define VBAT_PFR_STS_VBAT_RST_Msk (0x80UL) /*!< VBAT PFR_STS: VBAT_RST (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- VBAT_CLOCK_EN ------------------------------- */\r
-#define VBAT_CLOCK_EN_XOSEL_Pos (0UL) /*!< VBAT CLOCK_EN: XOSEL (Bit 0) */\r
-#define VBAT_CLOCK_EN_XOSEL_Msk (0x1UL) /*!< VBAT CLOCK_EN: XOSEL (Bitfield-Mask: 0x01) */\r
-#define VBAT_CLOCK_EN__32K_EN_Pos (1UL) /*!< VBAT CLOCK_EN: _32K_EN (Bit 1) */\r
-#define VBAT_CLOCK_EN__32K_EN_Msk (0x2UL) /*!< VBAT CLOCK_EN: _32K_EN (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'LPC' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ------------------------------- LPC_BUS_MONITOR ------------------------------ */\r
-#define LPC_BUS_MONITOR_LRESET_STATUS_Pos (1UL) /*!< LPC BUS_MONITOR: LRESET_STATUS (Bit 1) */\r
-#define LPC_BUS_MONITOR_LRESET_STATUS_Msk (0x2UL) /*!< LPC BUS_MONITOR: LRESET_STATUS (Bitfield-Mask: 0x01) */\r
-\r
-/* ----------------------------- LPC_HOST_BUS_ERROR ----------------------------- */\r
-#define LPC_HOST_BUS_ERROR_LPC_ERR_Pos (0UL) /*!< LPC HOST_BUS_ERROR: LPC_ERR (Bit 0) */\r
-#define LPC_HOST_BUS_ERROR_LPC_ERR_Msk (0x1UL) /*!< LPC HOST_BUS_ERROR: LPC_ERR (Bitfield-Mask: 0x01) */\r
-#define LPC_HOST_BUS_ERROR_EN_ERR_Pos (1UL) /*!< LPC HOST_BUS_ERROR: EN_ERR (Bit 1) */\r
-#define LPC_HOST_BUS_ERROR_EN_ERR_Msk (0x2UL) /*!< LPC HOST_BUS_ERROR: EN_ERR (Bitfield-Mask: 0x01) */\r
-#define LPC_HOST_BUS_ERROR_BAR_ERR_Pos (2UL) /*!< LPC HOST_BUS_ERROR: BAR_ERR (Bit 2) */\r
-#define LPC_HOST_BUS_ERROR_BAR_ERR_Msk (0x4UL) /*!< LPC HOST_BUS_ERROR: BAR_ERR (Bitfield-Mask: 0x01) */\r
-#define LPC_HOST_BUS_ERROR_RUNTIME_ERR_Pos (3UL) /*!< LPC HOST_BUS_ERROR: RUNTIME_ERR (Bit 3) */\r
-#define LPC_HOST_BUS_ERROR_RUNTIME_ERR_Msk (0x8UL) /*!< LPC HOST_BUS_ERROR: RUNTIME_ERR (Bitfield-Mask: 0x01) */\r
-#define LPC_HOST_BUS_ERROR_CONFIG_ERR_Pos (4UL) /*!< LPC HOST_BUS_ERROR: CONFIG_ERR (Bit 4) */\r
-#define LPC_HOST_BUS_ERROR_CONFIG_ERR_Msk (0x10UL) /*!< LPC HOST_BUS_ERROR: CONFIG_ERR (Bitfield-Mask: 0x01) */\r
-#define LPC_HOST_BUS_ERROR_DMA_ERR_Pos (5UL) /*!< LPC HOST_BUS_ERROR: DMA_ERR (Bit 5) */\r
-#define LPC_HOST_BUS_ERROR_DMA_ERR_Msk (0x20UL) /*!< LPC HOST_BUS_ERROR: DMA_ERR (Bitfield-Mask: 0x01) */\r
-#define LPC_HOST_BUS_ERROR_ERR_ADDR_Pos (8UL) /*!< LPC HOST_BUS_ERROR: ERR_ADDR (Bit 8) */\r
-#define LPC_HOST_BUS_ERROR_ERR_ADDR_Msk (0xffffff00UL) /*!< LPC HOST_BUS_ERROR: ERR_ADDR (Bitfield-Mask: 0xffffff) */\r
-\r
-/* -------------------------------- LPC_EC_SERIRQ ------------------------------- */\r
-#define LPC_EC_SERIRQ_EC_IRQ_Pos (0UL) /*!< LPC EC_SERIRQ: EC_IRQ (Bit 0) */\r
-#define LPC_EC_SERIRQ_EC_IRQ_Msk (0x1UL) /*!< LPC EC_SERIRQ: EC_IRQ (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- LPC_CLK_CTRL -------------------------------- */\r
-#define LPC_CLK_CTRL_CR_Pos (0UL) /*!< LPC CLK_CTRL: CR (Bit 0) */\r
-#define LPC_CLK_CTRL_CR_Msk (0x3UL) /*!< LPC CLK_CTRL: CR (Bitfield-Mask: 0x03) */\r
-#define LPC_CLK_CTRL_HANDSHAKE_Pos (2UL) /*!< LPC CLK_CTRL: HANDSHAKE (Bit 2) */\r
-#define LPC_CLK_CTRL_HANDSHAKE_Msk (0x4UL) /*!< LPC CLK_CTRL: HANDSHAKE (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'LPC_CONFIG' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ------------------------------- LPC_CONFIG_SIRQ ------------------------------ */\r
-#define LPC_CONFIG_SIRQ_FRAME_Pos (0UL) /*!< LPC_CONFIG SIRQ: FRAME (Bit 0) */\r
-#define LPC_CONFIG_SIRQ_FRAME_Msk (0x3fUL) /*!< LPC_CONFIG SIRQ: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_SIRQ_DEVICE_Pos (6UL) /*!< LPC_CONFIG SIRQ: DEVICE (Bit 6) */\r
-#define LPC_CONFIG_SIRQ_DEVICE_Msk (0x40UL) /*!< LPC_CONFIG SIRQ: DEVICE (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_SIRQ_SELECT_Pos (7UL) /*!< LPC_CONFIG SIRQ: SELECT (Bit 7) */\r
-#define LPC_CONFIG_SIRQ_SELECT_Msk (0x80UL) /*!< LPC_CONFIG SIRQ: SELECT (Bitfield-Mask: 0x01) */\r
-\r
-/* ----------------------------- LPC_CONFIG_LPC_BAR ----------------------------- */\r
-#define LPC_CONFIG_LPC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG LPC_BAR: MASK (Bit 0) */\r
-#define LPC_CONFIG_LPC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG LPC_BAR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_LPC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG LPC_BAR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_LPC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG LPC_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_LPC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG LPC_BAR: DEVICE (Bit 14) */\r
-#define LPC_CONFIG_LPC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG LPC_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_LPC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG LPC_BAR: VALID (Bit 15) */\r
-#define LPC_CONFIG_LPC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG LPC_BAR: VALID (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_LPC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG LPC_BAR: LPC_HOST_ADDR (Bit 16) */\r
-#define LPC_CONFIG_LPC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG LPC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
-\r
-/* ------------------------------ LPC_CONFIG_EM_BAR ----------------------------- */\r
-#define LPC_CONFIG_EM_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EM_BAR: MASK (Bit 0) */\r
-#define LPC_CONFIG_EM_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EM_BAR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_EM_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EM_BAR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_EM_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EM_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_EM_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EM_BAR: DEVICE (Bit 14) */\r
-#define LPC_CONFIG_EM_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EM_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_EM_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EM_BAR: VALID (Bit 15) */\r
-#define LPC_CONFIG_EM_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EM_BAR: VALID (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_EM_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EM_BAR: LPC_HOST_ADDR (Bit 16) */\r
-#define LPC_CONFIG_EM_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EM_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
-\r
-/* ----------------------------- LPC_CONFIG_UART_BAR ---------------------------- */\r
-#define LPC_CONFIG_UART_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG UART_BAR: MASK (Bit 0) */\r
-#define LPC_CONFIG_UART_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG UART_BAR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_UART_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG UART_BAR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_UART_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG UART_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_UART_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG UART_BAR: DEVICE (Bit 14) */\r
-#define LPC_CONFIG_UART_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG UART_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_UART_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG UART_BAR: VALID (Bit 15) */\r
-#define LPC_CONFIG_UART_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG UART_BAR: VALID (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_UART_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG UART_BAR: LPC_HOST_ADDR (Bit 16) */\r
-#define LPC_CONFIG_UART_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG UART_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
-\r
-/* ----------------------------- LPC_CONFIG_KBC_BAR ----------------------------- */\r
-#define LPC_CONFIG_KBC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG KBC_BAR: MASK (Bit 0) */\r
-#define LPC_CONFIG_KBC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG KBC_BAR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_KBC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG KBC_BAR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_KBC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG KBC_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_KBC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG KBC_BAR: DEVICE (Bit 14) */\r
-#define LPC_CONFIG_KBC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG KBC_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_KBC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG KBC_BAR: VALID (Bit 15) */\r
-#define LPC_CONFIG_KBC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG KBC_BAR: VALID (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_KBC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG KBC_BAR: LPC_HOST_ADDR (Bit 16) */\r
-#define LPC_CONFIG_KBC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG KBC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
-\r
-/* ----------------------------- LPC_CONFIG_EC0_BAR ----------------------------- */\r
-#define LPC_CONFIG_EC0_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EC0_BAR: MASK (Bit 0) */\r
-#define LPC_CONFIG_EC0_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EC0_BAR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_EC0_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EC0_BAR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_EC0_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EC0_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_EC0_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EC0_BAR: DEVICE (Bit 14) */\r
-#define LPC_CONFIG_EC0_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EC0_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_EC0_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EC0_BAR: VALID (Bit 15) */\r
-#define LPC_CONFIG_EC0_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EC0_BAR: VALID (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_EC0_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EC0_BAR: LPC_HOST_ADDR (Bit 16) */\r
-#define LPC_CONFIG_EC0_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EC0_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
-\r
-/* ----------------------------- LPC_CONFIG_EC1_BAR ----------------------------- */\r
-#define LPC_CONFIG_EC1_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EC1_BAR: MASK (Bit 0) */\r
-#define LPC_CONFIG_EC1_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EC1_BAR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_EC1_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EC1_BAR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_EC1_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EC1_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_EC1_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EC1_BAR: DEVICE (Bit 14) */\r
-#define LPC_CONFIG_EC1_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EC1_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_EC1_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EC1_BAR: VALID (Bit 15) */\r
-#define LPC_CONFIG_EC1_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EC1_BAR: VALID (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_EC1_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EC1_BAR: LPC_HOST_ADDR (Bit 16) */\r
-#define LPC_CONFIG_EC1_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EC1_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
-\r
-/* ----------------------------- LPC_CONFIG_PM1_BAR ----------------------------- */\r
-#define LPC_CONFIG_PM1_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG PM1_BAR: MASK (Bit 0) */\r
-#define LPC_CONFIG_PM1_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG PM1_BAR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_PM1_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG PM1_BAR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_PM1_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG PM1_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_PM1_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG PM1_BAR: DEVICE (Bit 14) */\r
-#define LPC_CONFIG_PM1_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG PM1_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_PM1_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG PM1_BAR: VALID (Bit 15) */\r
-#define LPC_CONFIG_PM1_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG PM1_BAR: VALID (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_PM1_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG PM1_BAR: LPC_HOST_ADDR (Bit 16) */\r
-#define LPC_CONFIG_PM1_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG PM1_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
-\r
-/* ----------------------------- LPC_CONFIG_LGC_BAR ----------------------------- */\r
-#define LPC_CONFIG_LGC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG LGC_BAR: MASK (Bit 0) */\r
-#define LPC_CONFIG_LGC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG LGC_BAR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_LGC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG LGC_BAR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_LGC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG LGC_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_LGC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG LGC_BAR: DEVICE (Bit 14) */\r
-#define LPC_CONFIG_LGC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG LGC_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_LGC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG LGC_BAR: VALID (Bit 15) */\r
-#define LPC_CONFIG_LGC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG LGC_BAR: VALID (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_LGC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG LGC_BAR: LPC_HOST_ADDR (Bit 16) */\r
-#define LPC_CONFIG_LGC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG LGC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
-\r
-/* ----------------------------- LPC_CONFIG_MBX_BAR ----------------------------- */\r
-#define LPC_CONFIG_MBX_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG MBX_BAR: MASK (Bit 0) */\r
-#define LPC_CONFIG_MBX_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG MBX_BAR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_MBX_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG MBX_BAR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_MBX_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG MBX_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_MBX_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG MBX_BAR: DEVICE (Bit 14) */\r
-#define LPC_CONFIG_MBX_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG MBX_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_MBX_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG MBX_BAR: VALID (Bit 15) */\r
-#define LPC_CONFIG_MBX_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG MBX_BAR: VALID (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_MBX_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG MBX_BAR: LPC_HOST_ADDR (Bit 16) */\r
-#define LPC_CONFIG_MBX_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG MBX_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
-\r
-/* ----------------------------- LPC_CONFIG_RTC_BAR ----------------------------- */\r
-#define LPC_CONFIG_RTC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG RTC_BAR: MASK (Bit 0) */\r
-#define LPC_CONFIG_RTC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG RTC_BAR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_RTC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG RTC_BAR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_RTC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG RTC_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_RTC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG RTC_BAR: DEVICE (Bit 14) */\r
-#define LPC_CONFIG_RTC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG RTC_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_RTC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG RTC_BAR: VALID (Bit 15) */\r
-#define LPC_CONFIG_RTC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG RTC_BAR: VALID (Bitfield-Mask: 0x01) */\r
-#define LPC_CONFIG_RTC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG RTC_BAR: LPC_HOST_ADDR (Bit 16) */\r
-#define LPC_CONFIG_RTC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG RTC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'MEM_BAR' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- MEM_BAR_CR --------------------------------- */\r
-#define MEM_BAR_CR_MASK_Pos (0UL) /*!< MEM_BAR CR: MASK (Bit 0) */\r
-#define MEM_BAR_CR_MASK_Msk (0xffUL) /*!< MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */\r
-#define MEM_BAR_CR_FRAME_Pos (8UL) /*!< MEM_BAR CR: FRAME (Bit 8) */\r
-#define MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define MEM_BAR_CR_VALID_Pos (15UL) /*!< MEM_BAR CR: VALID (Bit 15) */\r
-#define MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'MBX_MEM_BAR' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------- LPC_CONFIG_MBX_MEM_BAR_CR ------------------------- */\r
-#define LPC_CONFIG_MBX_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: MASK (Bit 0) */\r
-#define LPC_CONFIG_MBX_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_MBX_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_MBX_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_MBX_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: VALID (Bit 15) */\r
-#define LPC_CONFIG_MBX_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'EC0_MEM_BAR' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------- LPC_CONFIG_EC0_MEM_BAR_CR ------------------------- */\r
-#define LPC_CONFIG_EC0_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: MASK (Bit 0) */\r
-#define LPC_CONFIG_EC0_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_EC0_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_EC0_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_EC0_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: VALID (Bit 15) */\r
-#define LPC_CONFIG_EC0_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'EC1_MEM_BAR' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------- LPC_CONFIG_EC1_MEM_BAR_CR ------------------------- */\r
-#define LPC_CONFIG_EC1_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: MASK (Bit 0) */\r
-#define LPC_CONFIG_EC1_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_EC1_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_EC1_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_EC1_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: VALID (Bit 15) */\r
-#define LPC_CONFIG_EC1_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'EMI_MEM_BAR' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------- LPC_CONFIG_EMI_MEM_BAR_CR ------------------------- */\r
-#define LPC_CONFIG_EMI_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: MASK (Bit 0) */\r
-#define LPC_CONFIG_EMI_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */\r
-#define LPC_CONFIG_EMI_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: FRAME (Bit 8) */\r
-#define LPC_CONFIG_EMI_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */\r
-#define LPC_CONFIG_EMI_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: VALID (Bit 15) */\r
-#define LPC_CONFIG_EMI_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'EMI' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ------------------------------- EMI_EC_ADDRESS ------------------------------- */\r
-#define EMI_EC_ADDRESS_ACCESS_TYPE_Pos (0UL) /*!< EMI EC_ADDRESS: ACCESS_TYPE (Bit 0) */\r
-#define EMI_EC_ADDRESS_ACCESS_TYPE_Msk (0x3UL) /*!< EMI EC_ADDRESS: ACCESS_TYPE (Bitfield-Mask: 0x03) */\r
-#define EMI_EC_ADDRESS_EC_ADDRESS_Pos (2UL) /*!< EMI EC_ADDRESS: EC_ADDRESS (Bit 2) */\r
-#define EMI_EC_ADDRESS_EC_ADDRESS_Msk (0x7ffcUL) /*!< EMI EC_ADDRESS: EC_ADDRESS (Bitfield-Mask: 0x1fff) */\r
-#define EMI_EC_ADDRESS_REGION_Pos (15UL) /*!< EMI EC_ADDRESS: REGION (Bit 15) */\r
-#define EMI_EC_ADDRESS_REGION_Msk (0x8000UL) /*!< EMI EC_ADDRESS: REGION (Bitfield-Mask: 0x01) */\r
-\r
-/* --------------------------------- EMI_EC_SWI --------------------------------- */\r
-#define EMI_EC_SWI_EC_WR_Pos (0UL) /*!< EMI EC_SWI: EC_WR (Bit 0) */\r
-#define EMI_EC_SWI_EC_WR_Msk (0x1UL) /*!< EMI EC_SWI: EC_WR (Bitfield-Mask: 0x01) */\r
-#define EMI_EC_SWI_NOTIFICATION_Pos (1UL) /*!< EMI EC_SWI: NOTIFICATION (Bit 1) */\r
-#define EMI_EC_SWI_NOTIFICATION_Msk (0xfffeUL) /*!< EMI EC_SWI: NOTIFICATION (Bitfield-Mask: 0x7fff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'ACPI_EC0' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------- ACPI_EC0_OS_STATUS ----------------------------- */\r
-#define ACPI_EC0_OS_STATUS_OBF_Pos (0UL) /*!< ACPI_EC0 OS_STATUS: OBF (Bit 0) */\r
-#define ACPI_EC0_OS_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC0 OS_STATUS: OBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_OS_STATUS_IBF_Pos (1UL) /*!< ACPI_EC0 OS_STATUS: IBF (Bit 1) */\r
-#define ACPI_EC0_OS_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC0 OS_STATUS: IBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_OS_STATUS_UD1B_Pos (2UL) /*!< ACPI_EC0 OS_STATUS: UD1B (Bit 2) */\r
-#define ACPI_EC0_OS_STATUS_UD1B_Msk (0x4UL) /*!< ACPI_EC0 OS_STATUS: UD1B (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_OS_STATUS_CMD_Pos (3UL) /*!< ACPI_EC0 OS_STATUS: CMD (Bit 3) */\r
-#define ACPI_EC0_OS_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC0 OS_STATUS: CMD (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_OS_STATUS_BURST_Pos (4UL) /*!< ACPI_EC0 OS_STATUS: BURST (Bit 4) */\r
-#define ACPI_EC0_OS_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC0 OS_STATUS: BURST (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_OS_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC0 OS_STATUS: SCI_EVT (Bit 5) */\r
-#define ACPI_EC0_OS_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC0 OS_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_OS_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC0 OS_STATUS: SMI_EVT (Bit 6) */\r
-#define ACPI_EC0_OS_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC0 OS_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_OS_STATUS_UD0B_Pos (7UL) /*!< ACPI_EC0 OS_STATUS: UD0B (Bit 7) */\r
-#define ACPI_EC0_OS_STATUS_UD0B_Msk (0x80UL) /*!< ACPI_EC0 OS_STATUS: UD0B (Bitfield-Mask: 0x01) */\r
-\r
-/* ----------------------------- ACPI_EC0_EC_STATUS ----------------------------- */\r
-#define ACPI_EC0_EC_STATUS_OBF_Pos (0UL) /*!< ACPI_EC0 EC_STATUS: OBF (Bit 0) */\r
-#define ACPI_EC0_EC_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC0 EC_STATUS: OBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_EC_STATUS_IBF_Pos (1UL) /*!< ACPI_EC0 EC_STATUS: IBF (Bit 1) */\r
-#define ACPI_EC0_EC_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC0 EC_STATUS: IBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_EC_STATUS_UD1A_Pos (2UL) /*!< ACPI_EC0 EC_STATUS: UD1A (Bit 2) */\r
-#define ACPI_EC0_EC_STATUS_UD1A_Msk (0x4UL) /*!< ACPI_EC0 EC_STATUS: UD1A (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_EC_STATUS_CMD_Pos (3UL) /*!< ACPI_EC0 EC_STATUS: CMD (Bit 3) */\r
-#define ACPI_EC0_EC_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC0 EC_STATUS: CMD (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_EC_STATUS_BURST_Pos (4UL) /*!< ACPI_EC0 EC_STATUS: BURST (Bit 4) */\r
-#define ACPI_EC0_EC_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC0 EC_STATUS: BURST (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_EC_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC0 EC_STATUS: SCI_EVT (Bit 5) */\r
-#define ACPI_EC0_EC_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC0 EC_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_EC_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC0 EC_STATUS: SMI_EVT (Bit 6) */\r
-#define ACPI_EC0_EC_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC0 EC_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC0_EC_STATUS_UD0A_Pos (7UL) /*!< ACPI_EC0 EC_STATUS: UD0A (Bit 7) */\r
-#define ACPI_EC0_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC0 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'ACPI_EC1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------- ACPI_EC1_OS_STATUS ----------------------------- */\r
-#define ACPI_EC1_OS_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bit 0) */\r
-#define ACPI_EC1_OS_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bit 1) */\r
-#define ACPI_EC1_OS_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_UD1B_Pos (2UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bit 2) */\r
-#define ACPI_EC1_OS_STATUS_UD1B_Msk (0x4UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bit 3) */\r
-#define ACPI_EC1_OS_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bit 4) */\r
-#define ACPI_EC1_OS_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bit 5) */\r
-#define ACPI_EC1_OS_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bit 6) */\r
-#define ACPI_EC1_OS_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_OS_STATUS_UD0B_Pos (7UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bit 7) */\r
-#define ACPI_EC1_OS_STATUS_UD0B_Msk (0x80UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bitfield-Mask: 0x01) */\r
-\r
-/* ----------------------------- ACPI_EC1_EC_STATUS ----------------------------- */\r
-#define ACPI_EC1_EC_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bit 0) */\r
-#define ACPI_EC1_EC_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bit 1) */\r
-#define ACPI_EC1_EC_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_UD1A_Pos (2UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bit 2) */\r
-#define ACPI_EC1_EC_STATUS_UD1A_Msk (0x4UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bit 3) */\r
-#define ACPI_EC1_EC_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bit 4) */\r
-#define ACPI_EC1_EC_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bit 5) */\r
-#define ACPI_EC1_EC_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bit 6) */\r
-#define ACPI_EC1_EC_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */\r
-#define ACPI_EC1_EC_STATUS_UD0A_Pos (7UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bit 7) */\r
-#define ACPI_EC1_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'KBC' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------- KBC_RD_PORT64_STATUS ---------------------------- */\r
-#define KBC_RD_PORT64_STATUS_OBF_Pos (0UL) /*!< KBC RD_PORT64_STATUS: OBF (Bit 0) */\r
-#define KBC_RD_PORT64_STATUS_OBF_Msk (0x1UL) /*!< KBC RD_PORT64_STATUS: OBF (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_IBF_Pos (1UL) /*!< KBC RD_PORT64_STATUS: IBF (Bit 1) */\r
-#define KBC_RD_PORT64_STATUS_IBF_Msk (0x2UL) /*!< KBC RD_PORT64_STATUS: IBF (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_UD0_Pos (2UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bit 2) */\r
-#define KBC_RD_PORT64_STATUS_UD0_Msk (0x4UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_CMDnDATA_Pos (3UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bit 3) */\r
-#define KBC_RD_PORT64_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_UD1_Pos (4UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bit 4) */\r
-#define KBC_RD_PORT64_STATUS_UD1_Msk (0x10UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_AUXOBF_Pos (5UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bit 5) */\r
-#define KBC_RD_PORT64_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bitfield-Mask: 0x01) */\r
-#define KBC_RD_PORT64_STATUS_UD2_Pos (6UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bit 6) */\r
-#define KBC_RD_PORT64_STATUS_UD2_Msk (0xc0UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bitfield-Mask: 0x03) */\r
-\r
-/* --------------------------------- KBC_STATUS --------------------------------- */\r
-#define KBC_STATUS_OBF_Pos (0UL) /*!< KBC STATUS: OBF (Bit 0) */\r
-#define KBC_STATUS_OBF_Msk (0x1UL) /*!< KBC STATUS: OBF (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_IBF_Pos (1UL) /*!< KBC STATUS: IBF (Bit 1) */\r
-#define KBC_STATUS_IBF_Msk (0x2UL) /*!< KBC STATUS: IBF (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_UD0_Pos (2UL) /*!< KBC STATUS: UD0 (Bit 2) */\r
-#define KBC_STATUS_UD0_Msk (0x4UL) /*!< KBC STATUS: UD0 (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_CMDnDATA_Pos (3UL) /*!< KBC STATUS: CMDnDATA (Bit 3) */\r
-#define KBC_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC STATUS: CMDnDATA (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_UD1_Pos (4UL) /*!< KBC STATUS: UD1 (Bit 4) */\r
-#define KBC_STATUS_UD1_Msk (0x10UL) /*!< KBC STATUS: UD1 (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_AUXOBF_Pos (5UL) /*!< KBC STATUS: AUXOBF (Bit 5) */\r
-#define KBC_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC STATUS: AUXOBF (Bitfield-Mask: 0x01) */\r
-#define KBC_STATUS_UD2_Pos (6UL) /*!< KBC STATUS: UD2 (Bit 6) */\r
-#define KBC_STATUS_UD2_Msk (0xc0UL) /*!< KBC STATUS: UD2 (Bitfield-Mask: 0x03) */\r
-\r
-/* --------------------------------- KBC_CONTROL -------------------------------- */\r
-#define KBC_CONTROL_UD3_Pos (0UL) /*!< KBC CONTROL: UD3 (Bit 0) */\r
-#define KBC_CONTROL_UD3_Msk (0x1UL) /*!< KBC CONTROL: UD3 (Bitfield-Mask: 0x01) */\r
-#define KBC_CONTROL_SAEN_Pos (1UL) /*!< KBC CONTROL: SAEN (Bit 1) */\r
-#define KBC_CONTROL_SAEN_Msk (0x2UL) /*!< KBC CONTROL: SAEN (Bitfield-Mask: 0x01) */\r
-#define KBC_CONTROL_PCOBFEN_Pos (2UL) /*!< KBC CONTROL: PCOBFEN (Bit 2) */\r
-#define KBC_CONTROL_PCOBFEN_Msk (0x4UL) /*!< KBC CONTROL: PCOBFEN (Bitfield-Mask: 0x01) */\r
-#define KBC_CONTROL_UD4_Pos (3UL) /*!< KBC CONTROL: UD4 (Bit 3) */\r
-#define KBC_CONTROL_UD4_Msk (0x18UL) /*!< KBC CONTROL: UD4 (Bitfield-Mask: 0x03) */\r
-#define KBC_CONTROL_OBFEN_Pos (5UL) /*!< KBC CONTROL: OBFEN (Bit 5) */\r
-#define KBC_CONTROL_OBFEN_Msk (0x20UL) /*!< KBC CONTROL: OBFEN (Bitfield-Mask: 0x01) */\r
-#define KBC_CONTROL_UD5_Pos (6UL) /*!< KBC CONTROL: UD5 (Bit 6) */\r
-#define KBC_CONTROL_UD5_Msk (0x40UL) /*!< KBC CONTROL: UD5 (Bitfield-Mask: 0x01) */\r
-#define KBC_CONTROL_AUXH_Pos (7UL) /*!< KBC CONTROL: AUXH (Bit 7) */\r
-#define KBC_CONTROL_AUXH_Msk (0x80UL) /*!< KBC CONTROL: AUXH (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PORT92' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PORT92_PORT92 ------------------------------- */\r
-#define PORT92_PORT92_ALT_CPU_RESET_Pos (0UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bit 0) */\r
-#define PORT92_PORT92_ALT_CPU_RESET_Msk (0x1UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bitfield-Mask: 0x01) */\r
-#define PORT92_PORT92_ALT_GATE_A20_Pos (1UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bit 1) */\r
-#define PORT92_PORT92_ALT_GATE_A20_Msk (0x2UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'MBX' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ------------------------------- MBX_SMI_SOURCE ------------------------------- */\r
-#define MBX_SMI_SOURCE_EC_WR_Pos (0UL) /*!< MBX SMI_SOURCE: EC_WR (Bit 0) */\r
-#define MBX_SMI_SOURCE_EC_WR_Msk (0x1UL) /*!< MBX SMI_SOURCE: EC_WR (Bitfield-Mask: 0x01) */\r
-#define MBX_SMI_SOURCE_EC_SMI_Pos (1UL) /*!< MBX SMI_SOURCE: EC_SMI (Bit 1) */\r
-#define MBX_SMI_SOURCE_EC_SMI_Msk (0xfeUL) /*!< MBX SMI_SOURCE: EC_SMI (Bitfield-Mask: 0x7f) */\r
-\r
-/* -------------------------------- MBX_SMI_MASK -------------------------------- */\r
-#define MBX_SMI_MASK_EC_WR_EN_Pos (0UL) /*!< MBX SMI_MASK: EC_WR_EN (Bit 0) */\r
-#define MBX_SMI_MASK_EC_WR_EN_Msk (0x1UL) /*!< MBX SMI_MASK: EC_WR_EN (Bitfield-Mask: 0x01) */\r
-#define MBX_SMI_MASK_EC_SMI_EN_Pos (1UL) /*!< MBX SMI_MASK: EC_SMI_EN (Bit 1) */\r
-#define MBX_SMI_MASK_EC_SMI_EN_Msk (0xfeUL) /*!< MBX SMI_MASK: EC_SMI_EN (Bitfield-Mask: 0x7f) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PM1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------------- PM1_STS2 ---------------------------------- */\r
-#define PM1_STS2_PWRBTN_STS_Pos (0UL) /*!< PM1 STS2: PWRBTN_STS (Bit 0) */\r
-#define PM1_STS2_PWRBTN_STS_Msk (0x1UL) /*!< PM1 STS2: PWRBTN_STS (Bitfield-Mask: 0x01) */\r
-#define PM1_STS2_SLPBTN_STS_Pos (1UL) /*!< PM1 STS2: SLPBTN_STS (Bit 1) */\r
-#define PM1_STS2_SLPBTN_STS_Msk (0x2UL) /*!< PM1 STS2: SLPBTN_STS (Bitfield-Mask: 0x01) */\r
-#define PM1_STS2_RTC_STS_Pos (2UL) /*!< PM1 STS2: RTC_STS (Bit 2) */\r
-#define PM1_STS2_RTC_STS_Msk (0x4UL) /*!< PM1 STS2: RTC_STS (Bitfield-Mask: 0x01) */\r
-#define PM1_STS2_PWRBTNOR_STS_Pos (3UL) /*!< PM1 STS2: PWRBTNOR_STS (Bit 3) */\r
-#define PM1_STS2_PWRBTNOR_STS_Msk (0x8UL) /*!< PM1 STS2: PWRBTNOR_STS (Bitfield-Mask: 0x01) */\r
-#define PM1_STS2_WAK_STS_Pos (7UL) /*!< PM1 STS2: WAK_STS (Bit 7) */\r
-#define PM1_STS2_WAK_STS_Msk (0x80UL) /*!< PM1 STS2: WAK_STS (Bitfield-Mask: 0x01) */\r
-\r
-/* ----------------------------------- PM1_EN2 ---------------------------------- */\r
-#define PM1_EN2_PWRBTN_EN_Pos (0UL) /*!< PM1 EN2: PWRBTN_EN (Bit 0) */\r
-#define PM1_EN2_PWRBTN_EN_Msk (0x1UL) /*!< PM1 EN2: PWRBTN_EN (Bitfield-Mask: 0x01) */\r
-#define PM1_EN2_SLPBTN_EN_Pos (1UL) /*!< PM1 EN2: SLPBTN_EN (Bit 1) */\r
-#define PM1_EN2_SLPBTN_EN_Msk (0x2UL) /*!< PM1 EN2: SLPBTN_EN (Bitfield-Mask: 0x01) */\r
-#define PM1_EN2_RTC_EN_Pos (2UL) /*!< PM1 EN2: RTC_EN (Bit 2) */\r
-#define PM1_EN2_RTC_EN_Msk (0x4UL) /*!< PM1 EN2: RTC_EN (Bitfield-Mask: 0x01) */\r
-\r
-/* ---------------------------------- PM1_CTRL2 --------------------------------- */\r
-#define PM1_CTRL2_PWRBTNOR_EN_Pos (1UL) /*!< PM1 CTRL2: PWRBTNOR_EN (Bit 1) */\r
-#define PM1_CTRL2_PWRBTNOR_EN_Msk (0x2UL) /*!< PM1 CTRL2: PWRBTNOR_EN (Bitfield-Mask: 0x01) */\r
-#define PM1_CTRL2_SLP_TYP_Pos (2UL) /*!< PM1 CTRL2: SLP_TYP (Bit 2) */\r
-#define PM1_CTRL2_SLP_TYP_Msk (0x1cUL) /*!< PM1 CTRL2: SLP_TYP (Bitfield-Mask: 0x07) */\r
-#define PM1_CTRL2_SLP_EN_Pos (5UL) /*!< PM1 CTRL2: SLP_EN (Bit 5) */\r
-#define PM1_CTRL2_SLP_EN_Msk (0x20UL) /*!< PM1 CTRL2: SLP_EN (Bitfield-Mask: 0x01) */\r
-\r
-/* ---------------------------------- PM1_STS_2 --------------------------------- */\r
-#define PM1_STS_2_PWRBTN_STS_Pos (0UL) /*!< PM1 STS_2: PWRBTN_STS (Bit 0) */\r
-#define PM1_STS_2_PWRBTN_STS_Msk (0x1UL) /*!< PM1 STS_2: PWRBTN_STS (Bitfield-Mask: 0x01) */\r
-#define PM1_STS_2_SLPBTN_STS_Pos (1UL) /*!< PM1 STS_2: SLPBTN_STS (Bit 1) */\r
-#define PM1_STS_2_SLPBTN_STS_Msk (0x2UL) /*!< PM1 STS_2: SLPBTN_STS (Bitfield-Mask: 0x01) */\r
-#define PM1_STS_2_RTC_STS_Pos (2UL) /*!< PM1 STS_2: RTC_STS (Bit 2) */\r
-#define PM1_STS_2_RTC_STS_Msk (0x4UL) /*!< PM1 STS_2: RTC_STS (Bitfield-Mask: 0x01) */\r
-#define PM1_STS_2_PWRBTNOR_STS_Pos (3UL) /*!< PM1 STS_2: PWRBTNOR_STS (Bit 3) */\r
-#define PM1_STS_2_PWRBTNOR_STS_Msk (0x8UL) /*!< PM1 STS_2: PWRBTNOR_STS (Bitfield-Mask: 0x01) */\r
-#define PM1_STS_2_WAK_STS_Pos (7UL) /*!< PM1 STS_2: WAK_STS (Bit 7) */\r
-#define PM1_STS_2_WAK_STS_Msk (0x80UL) /*!< PM1 STS_2: WAK_STS (Bitfield-Mask: 0x01) */\r
-\r
-/* ---------------------------------- PM1_EN_2 ---------------------------------- */\r
-#define PM1_EN_2_PWRBTN_EN_Pos (0UL) /*!< PM1 EN_2: PWRBTN_EN (Bit 0) */\r
-#define PM1_EN_2_PWRBTN_EN_Msk (0x1UL) /*!< PM1 EN_2: PWRBTN_EN (Bitfield-Mask: 0x01) */\r
-#define PM1_EN_2_SLPBTN_EN_Pos (1UL) /*!< PM1 EN_2: SLPBTN_EN (Bit 1) */\r
-#define PM1_EN_2_SLPBTN_EN_Msk (0x2UL) /*!< PM1 EN_2: SLPBTN_EN (Bitfield-Mask: 0x01) */\r
-#define PM1_EN_2_RTC_EN_Pos (2UL) /*!< PM1 EN_2: RTC_EN (Bit 2) */\r
-#define PM1_EN_2_RTC_EN_Msk (0x4UL) /*!< PM1 EN_2: RTC_EN (Bitfield-Mask: 0x01) */\r
-\r
-/* --------------------------------- PM1_CTRL_2 --------------------------------- */\r
-#define PM1_CTRL_2_PWRBTNOR_EN_Pos (1UL) /*!< PM1 CTRL_2: PWRBTNOR_EN (Bit 1) */\r
-#define PM1_CTRL_2_PWRBTNOR_EN_Msk (0x2UL) /*!< PM1 CTRL_2: PWRBTNOR_EN (Bitfield-Mask: 0x01) */\r
-#define PM1_CTRL_2_SLP_TYP_Pos (2UL) /*!< PM1 CTRL_2: SLP_TYP (Bit 2) */\r
-#define PM1_CTRL_2_SLP_TYP_Msk (0x1cUL) /*!< PM1 CTRL_2: SLP_TYP (Bitfield-Mask: 0x07) */\r
-#define PM1_CTRL_2_SLP_EN_Pos (5UL) /*!< PM1 CTRL_2: SLP_EN (Bit 5) */\r
-#define PM1_CTRL_2_SLP_EN_Msk (0x20UL) /*!< PM1 CTRL_2: SLP_EN (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'UART' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- UART_INT_EN -------------------------------- */\r
-#define UART_INT_EN_ERDAI_Pos (0UL) /*!< UART INT_EN: ERDAI (Bit 0) */\r
-#define UART_INT_EN_ERDAI_Msk (0x1UL) /*!< UART INT_EN: ERDAI (Bitfield-Mask: 0x01) */\r
-#define UART_INT_EN_ETHREI_Pos (1UL) /*!< UART INT_EN: ETHREI (Bit 1) */\r
-#define UART_INT_EN_ETHREI_Msk (0x2UL) /*!< UART INT_EN: ETHREI (Bitfield-Mask: 0x01) */\r
-#define UART_INT_EN_ELSI_Pos (2UL) /*!< UART INT_EN: ELSI (Bit 2) */\r
-#define UART_INT_EN_ELSI_Msk (0x4UL) /*!< UART INT_EN: ELSI (Bitfield-Mask: 0x01) */\r
-#define UART_INT_EN_EMSI_Pos (3UL) /*!< UART INT_EN: EMSI (Bit 3) */\r
-#define UART_INT_EN_EMSI_Msk (0x8UL) /*!< UART INT_EN: EMSI (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- UART_FIFO_CR -------------------------------- */\r
-#define UART_FIFO_CR_EXRF_Pos (0UL) /*!< UART FIFO_CR: EXRF (Bit 0) */\r
-#define UART_FIFO_CR_EXRF_Msk (0x1UL) /*!< UART FIFO_CR: EXRF (Bitfield-Mask: 0x01) */\r
-#define UART_FIFO_CR_CLEAR_RECV_FIFO_Pos (1UL) /*!< UART FIFO_CR: CLEAR_RECV_FIFO (Bit 1) */\r
-#define UART_FIFO_CR_CLEAR_RECV_FIFO_Msk (0x2UL) /*!< UART FIFO_CR: CLEAR_RECV_FIFO (Bitfield-Mask: 0x01) */\r
-#define UART_FIFO_CR_CLEAR_XMIT_FIFO_Pos (2UL) /*!< UART FIFO_CR: CLEAR_XMIT_FIFO (Bit 2) */\r
-#define UART_FIFO_CR_CLEAR_XMIT_FIFO_Msk (0x4UL) /*!< UART FIFO_CR: CLEAR_XMIT_FIFO (Bitfield-Mask: 0x01) */\r
-#define UART_FIFO_CR_DMA_MODE_SELECT_Pos (3UL) /*!< UART FIFO_CR: DMA_MODE_SELECT (Bit 3) */\r
-#define UART_FIFO_CR_DMA_MODE_SELECT_Msk (0x8UL) /*!< UART FIFO_CR: DMA_MODE_SELECT (Bitfield-Mask: 0x01) */\r
-#define UART_FIFO_CR_RECV_FIFO_TRIGGER_LEVEL_Pos (6UL) /*!< UART FIFO_CR: RECV_FIFO_TRIGGER_LEVEL (Bit 6) */\r
-#define UART_FIFO_CR_RECV_FIFO_TRIGGER_LEVEL_Msk (0xc0UL) /*!< UART FIFO_CR: RECV_FIFO_TRIGGER_LEVEL (Bitfield-Mask: 0x03) */\r
-\r
-/* --------------------------------- UART_INT_ID -------------------------------- */\r
-#define UART_INT_ID_IPEND_Pos (0UL) /*!< UART INT_ID: IPEND (Bit 0) */\r
-#define UART_INT_ID_IPEND_Msk (0x1UL) /*!< UART INT_ID: IPEND (Bitfield-Mask: 0x01) */\r
-#define UART_INT_ID_INTID_Pos (1UL) /*!< UART INT_ID: INTID (Bit 1) */\r
-#define UART_INT_ID_INTID_Msk (0xeUL) /*!< UART INT_ID: INTID (Bitfield-Mask: 0x07) */\r
-#define UART_INT_ID_FIFO_EN_Pos (6UL) /*!< UART INT_ID: FIFO_EN (Bit 6) */\r
-#define UART_INT_ID_FIFO_EN_Msk (0xc0UL) /*!< UART INT_ID: FIFO_EN (Bitfield-Mask: 0x03) */\r
-\r
-/* -------------------------------- UART_LINE_CR -------------------------------- */\r
-#define UART_LINE_CR_WORD_LENGTH_Pos (0UL) /*!< UART LINE_CR: WORD_LENGTH (Bit 0) */\r
-#define UART_LINE_CR_WORD_LENGTH_Msk (0x3UL) /*!< UART LINE_CR: WORD_LENGTH (Bitfield-Mask: 0x03) */\r
-#define UART_LINE_CR_STOP_BITS_Pos (2UL) /*!< UART LINE_CR: STOP_BITS (Bit 2) */\r
-#define UART_LINE_CR_STOP_BITS_Msk (0x4UL) /*!< UART LINE_CR: STOP_BITS (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_CR_ENABLE_PARITY_Pos (3UL) /*!< UART LINE_CR: ENABLE_PARITY (Bit 3) */\r
-#define UART_LINE_CR_ENABLE_PARITY_Msk (0x8UL) /*!< UART LINE_CR: ENABLE_PARITY (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_CR_PARITY_SELECT_Pos (4UL) /*!< UART LINE_CR: PARITY_SELECT (Bit 4) */\r
-#define UART_LINE_CR_PARITY_SELECT_Msk (0x10UL) /*!< UART LINE_CR: PARITY_SELECT (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_CR_STICK_PARITY_Pos (5UL) /*!< UART LINE_CR: STICK_PARITY (Bit 5) */\r
-#define UART_LINE_CR_STICK_PARITY_Msk (0x20UL) /*!< UART LINE_CR: STICK_PARITY (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_CR_BREAK_CONTROL_Pos (6UL) /*!< UART LINE_CR: BREAK_CONTROL (Bit 6) */\r
-#define UART_LINE_CR_BREAK_CONTROL_Msk (0x40UL) /*!< UART LINE_CR: BREAK_CONTROL (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_CR_DLAB_Pos (7UL) /*!< UART LINE_CR: DLAB (Bit 7) */\r
-#define UART_LINE_CR_DLAB_Msk (0x80UL) /*!< UART LINE_CR: DLAB (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- UART_MODEM_CR ------------------------------- */\r
-#define UART_MODEM_CR_DTR_Pos (0UL) /*!< UART MODEM_CR: DTR (Bit 0) */\r
-#define UART_MODEM_CR_DTR_Msk (0x1UL) /*!< UART MODEM_CR: DTR (Bitfield-Mask: 0x01) */\r
-#define UART_MODEM_CR_RTS_Pos (1UL) /*!< UART MODEM_CR: RTS (Bit 1) */\r
-#define UART_MODEM_CR_RTS_Msk (0x2UL) /*!< UART MODEM_CR: RTS (Bitfield-Mask: 0x01) */\r
-#define UART_MODEM_CR_OUT1_Pos (2UL) /*!< UART MODEM_CR: OUT1 (Bit 2) */\r
-#define UART_MODEM_CR_OUT1_Msk (0x4UL) /*!< UART MODEM_CR: OUT1 (Bitfield-Mask: 0x01) */\r
-#define UART_MODEM_CR_OUT2_Pos (3UL) /*!< UART MODEM_CR: OUT2 (Bit 3) */\r
-#define UART_MODEM_CR_OUT2_Msk (0x8UL) /*!< UART MODEM_CR: OUT2 (Bitfield-Mask: 0x01) */\r
-#define UART_MODEM_CR_LOOPBACK_Pos (4UL) /*!< UART MODEM_CR: LOOPBACK (Bit 4) */\r
-#define UART_MODEM_CR_LOOPBACK_Msk (0x10UL) /*!< UART MODEM_CR: LOOPBACK (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- UART_LINE_STS ------------------------------- */\r
-#define UART_LINE_STS_DATA_READY_Pos (0UL) /*!< UART LINE_STS: DATA_READY (Bit 0) */\r
-#define UART_LINE_STS_DATA_READY_Msk (0x1UL) /*!< UART LINE_STS: DATA_READY (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_STS_OVERRUN_Pos (1UL) /*!< UART LINE_STS: OVERRUN (Bit 1) */\r
-#define UART_LINE_STS_OVERRUN_Msk (0x2UL) /*!< UART LINE_STS: OVERRUN (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_STS_PE_Pos (2UL) /*!< UART LINE_STS: PE (Bit 2) */\r
-#define UART_LINE_STS_PE_Msk (0x4UL) /*!< UART LINE_STS: PE (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_STS_FRAME_ERROR_Pos (3UL) /*!< UART LINE_STS: FRAME_ERROR (Bit 3) */\r
-#define UART_LINE_STS_FRAME_ERROR_Msk (0x8UL) /*!< UART LINE_STS: FRAME_ERROR (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_STS_BREAK_INTERRUPT_Pos (4UL) /*!< UART LINE_STS: BREAK_INTERRUPT (Bit 4) */\r
-#define UART_LINE_STS_BREAK_INTERRUPT_Msk (0x10UL) /*!< UART LINE_STS: BREAK_INTERRUPT (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_STS_TRANSMIT_EMPTY_Pos (5UL) /*!< UART LINE_STS: TRANSMIT_EMPTY (Bit 5) */\r
-#define UART_LINE_STS_TRANSMIT_EMPTY_Msk (0x20UL) /*!< UART LINE_STS: TRANSMIT_EMPTY (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_STS_TRANSMIT_ERROR_Pos (6UL) /*!< UART LINE_STS: TRANSMIT_ERROR (Bit 6) */\r
-#define UART_LINE_STS_TRANSMIT_ERROR_Msk (0x40UL) /*!< UART LINE_STS: TRANSMIT_ERROR (Bitfield-Mask: 0x01) */\r
-#define UART_LINE_STS_FIFO_ERROR_Pos (7UL) /*!< UART LINE_STS: FIFO_ERROR (Bit 7) */\r
-#define UART_LINE_STS_FIFO_ERROR_Msk (0x80UL) /*!< UART LINE_STS: FIFO_ERROR (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------- UART_MODEM_STS ------------------------------- */\r
-#define UART_MODEM_STS_CTS_Pos (0UL) /*!< UART MODEM_STS: CTS (Bit 0) */\r
-#define UART_MODEM_STS_CTS_Msk (0x1UL) /*!< UART MODEM_STS: CTS (Bitfield-Mask: 0x01) */\r
-#define UART_MODEM_STS_DSR_Pos (1UL) /*!< UART MODEM_STS: DSR (Bit 1) */\r
-#define UART_MODEM_STS_DSR_Msk (0x2UL) /*!< UART MODEM_STS: DSR (Bitfield-Mask: 0x01) */\r
-#define UART_MODEM_STS_RI_Pos (2UL) /*!< UART MODEM_STS: RI (Bit 2) */\r
-#define UART_MODEM_STS_RI_Msk (0x4UL) /*!< UART MODEM_STS: RI (Bitfield-Mask: 0x01) */\r
-#define UART_MODEM_STS_DCD_Pos (3UL) /*!< UART MODEM_STS: DCD (Bit 3) */\r
-#define UART_MODEM_STS_DCD_Msk (0x8UL) /*!< UART MODEM_STS: DCD (Bitfield-Mask: 0x01) */\r
-#define UART_MODEM_STS_nCTS_Pos (4UL) /*!< UART MODEM_STS: nCTS (Bit 4) */\r
-#define UART_MODEM_STS_nCTS_Msk (0x10UL) /*!< UART MODEM_STS: nCTS (Bitfield-Mask: 0x01) */\r
-#define UART_MODEM_STS_nDSR_Pos (5UL) /*!< UART MODEM_STS: nDSR (Bit 5) */\r
-#define UART_MODEM_STS_nDSR_Msk (0x20UL) /*!< UART MODEM_STS: nDSR (Bitfield-Mask: 0x01) */\r
-#define UART_MODEM_STS_nRI_Pos (6UL) /*!< UART MODEM_STS: nRI (Bit 6) */\r
-#define UART_MODEM_STS_nRI_Msk (0x40UL) /*!< UART MODEM_STS: nRI (Bitfield-Mask: 0x01) */\r
-#define UART_MODEM_STS_nDCD_Pos (7UL) /*!< UART MODEM_STS: nDCD (Bit 7) */\r
-#define UART_MODEM_STS_nDCD_Msk (0x80UL) /*!< UART MODEM_STS: nDCD (Bitfield-Mask: 0x01) */\r
-\r
-/* --------------------------------- UART_CONFIG -------------------------------- */\r
-#define UART_CONFIG_CLK_SRC_Pos (0UL) /*!< UART CONFIG: CLK_SRC (Bit 0) */\r
-#define UART_CONFIG_CLK_SRC_Msk (0x1UL) /*!< UART CONFIG: CLK_SRC (Bitfield-Mask: 0x01) */\r
-#define UART_CONFIG_POWER_Pos (1UL) /*!< UART CONFIG: POWER (Bit 1) */\r
-#define UART_CONFIG_POWER_Msk (0x2UL) /*!< UART CONFIG: POWER (Bitfield-Mask: 0x01) */\r
-#define UART_CONFIG_POLARITY_Pos (2UL) /*!< UART CONFIG: POLARITY (Bit 2) */\r
-#define UART_CONFIG_POLARITY_Msk (0x4UL) /*!< UART CONFIG: POLARITY (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'WDT' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- WDT_CONTROL -------------------------------- */\r
-#define WDT_CONTROL_ENABLE_Pos (0UL) /*!< WDT CONTROL: ENABLE (Bit 0) */\r
-#define WDT_CONTROL_ENABLE_Msk (0x1UL) /*!< WDT CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
-#define WDT_CONTROL_STATUS_Pos (1UL) /*!< WDT CONTROL: STATUS (Bit 1) */\r
-#define WDT_CONTROL_STATUS_Msk (0x2UL) /*!< WDT CONTROL: STATUS (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'TIMER_16_0' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------- TIMER_16_0_CONTROL ----------------------------- */\r
-#define TIMER_16_0_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_0 CONTROL: ENABLE (Bit 0) */\r
-#define TIMER_16_0_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_0 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_0_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_0 CONTROL: COUNT_UP (Bit 2) */\r
-#define TIMER_16_0_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_0 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_0_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_0 CONTROL: AUTO_RESTART (Bit 3) */\r
-#define TIMER_16_0_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_0 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_0 CONTROL: SOFT_RESET (Bit 4) */\r
-#define TIMER_16_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_0_CONTROL_START_Pos (5UL) /*!< TIMER_16_0 CONTROL: START (Bit 5) */\r
-#define TIMER_16_0_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_0 CONTROL: START (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_0_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_0 CONTROL: RELOAD (Bit 6) */\r
-#define TIMER_16_0_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_0 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_0_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_0 CONTROL: HALT (Bit 7) */\r
-#define TIMER_16_0_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_0 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_0_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_0 CONTROL: PRE_SCALE (Bit 16) */\r
-#define TIMER_16_0_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_0 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'TIMER_16_1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------- TIMER_16_1_CONTROL ----------------------------- */\r
-#define TIMER_16_1_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_1 CONTROL: ENABLE (Bit 0) */\r
-#define TIMER_16_1_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_1 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_1_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_1 CONTROL: COUNT_UP (Bit 2) */\r
-#define TIMER_16_1_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_1 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_1_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_1 CONTROL: AUTO_RESTART (Bit 3) */\r
-#define TIMER_16_1_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_1 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_1 CONTROL: SOFT_RESET (Bit 4) */\r
-#define TIMER_16_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_1_CONTROL_START_Pos (5UL) /*!< TIMER_16_1 CONTROL: START (Bit 5) */\r
-#define TIMER_16_1_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_1 CONTROL: START (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_1_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_1 CONTROL: RELOAD (Bit 6) */\r
-#define TIMER_16_1_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_1 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_1_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_1 CONTROL: HALT (Bit 7) */\r
-#define TIMER_16_1_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_1 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_1_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_1 CONTROL: PRE_SCALE (Bit 16) */\r
-#define TIMER_16_1_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_1 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'TIMER_16_2' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------- TIMER_16_2_CONTROL ----------------------------- */\r
-#define TIMER_16_2_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_2 CONTROL: ENABLE (Bit 0) */\r
-#define TIMER_16_2_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_2 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_2_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_2 CONTROL: COUNT_UP (Bit 2) */\r
-#define TIMER_16_2_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_2 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_2_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_2 CONTROL: AUTO_RESTART (Bit 3) */\r
-#define TIMER_16_2_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_2 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_2_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_2 CONTROL: SOFT_RESET (Bit 4) */\r
-#define TIMER_16_2_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_2 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_2_CONTROL_START_Pos (5UL) /*!< TIMER_16_2 CONTROL: START (Bit 5) */\r
-#define TIMER_16_2_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_2 CONTROL: START (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_2_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_2 CONTROL: RELOAD (Bit 6) */\r
-#define TIMER_16_2_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_2 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_2_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_2 CONTROL: HALT (Bit 7) */\r
-#define TIMER_16_2_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_2 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_2_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_2 CONTROL: PRE_SCALE (Bit 16) */\r
-#define TIMER_16_2_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_2 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'TIMER_16_3' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------- TIMER_16_3_CONTROL ----------------------------- */\r
-#define TIMER_16_3_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_3 CONTROL: ENABLE (Bit 0) */\r
-#define TIMER_16_3_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_3 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_3_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_3 CONTROL: COUNT_UP (Bit 2) */\r
-#define TIMER_16_3_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_3 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_3_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_3 CONTROL: AUTO_RESTART (Bit 3) */\r
-#define TIMER_16_3_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_3 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_3_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_3 CONTROL: SOFT_RESET (Bit 4) */\r
-#define TIMER_16_3_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_3 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_3_CONTROL_START_Pos (5UL) /*!< TIMER_16_3 CONTROL: START (Bit 5) */\r
-#define TIMER_16_3_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_3 CONTROL: START (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_3_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_3 CONTROL: RELOAD (Bit 6) */\r
-#define TIMER_16_3_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_3 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_3_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_3 CONTROL: HALT (Bit 7) */\r
-#define TIMER_16_3_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_3 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
-#define TIMER_16_3_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_3 CONTROL: PRE_SCALE (Bit 16) */\r
-#define TIMER_16_3_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_3 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'TIMER_32_0' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------- TIMER_32_0_CONTROL ----------------------------- */\r
-#define TIMER_32_0_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_32_0 CONTROL: ENABLE (Bit 0) */\r
-#define TIMER_32_0_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_32_0 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_0_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_32_0 CONTROL: COUNT_UP (Bit 2) */\r
-#define TIMER_32_0_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_32_0 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_0_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_32_0 CONTROL: AUTO_RESTART (Bit 3) */\r
-#define TIMER_32_0_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_32_0 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_32_0 CONTROL: SOFT_RESET (Bit 4) */\r
-#define TIMER_32_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_32_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_0_CONTROL_START_Pos (5UL) /*!< TIMER_32_0 CONTROL: START (Bit 5) */\r
-#define TIMER_32_0_CONTROL_START_Msk (0x20UL) /*!< TIMER_32_0 CONTROL: START (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_0_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_32_0 CONTROL: RELOAD (Bit 6) */\r
-#define TIMER_32_0_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_32_0 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_0_CONTROL_HALT_Pos (7UL) /*!< TIMER_32_0 CONTROL: HALT (Bit 7) */\r
-#define TIMER_32_0_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_32_0 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_0_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_32_0 CONTROL: PRE_SCALE (Bit 16) */\r
-#define TIMER_32_0_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_32_0 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'TIMER_32_1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------- TIMER_32_1_CONTROL ----------------------------- */\r
-#define TIMER_32_1_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_32_1 CONTROL: ENABLE (Bit 0) */\r
-#define TIMER_32_1_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_32_1 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_1_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_32_1 CONTROL: COUNT_UP (Bit 2) */\r
-#define TIMER_32_1_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_32_1 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_1_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_32_1 CONTROL: AUTO_RESTART (Bit 3) */\r
-#define TIMER_32_1_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_32_1 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_32_1 CONTROL: SOFT_RESET (Bit 4) */\r
-#define TIMER_32_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_32_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_1_CONTROL_START_Pos (5UL) /*!< TIMER_32_1 CONTROL: START (Bit 5) */\r
-#define TIMER_32_1_CONTROL_START_Msk (0x20UL) /*!< TIMER_32_1 CONTROL: START (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_1_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_32_1 CONTROL: RELOAD (Bit 6) */\r
-#define TIMER_32_1_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_32_1 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_1_CONTROL_HALT_Pos (7UL) /*!< TIMER_32_1 CONTROL: HALT (Bit 7) */\r
-#define TIMER_32_1_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_32_1 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
-#define TIMER_32_1_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_32_1 CONTROL: PRE_SCALE (Bit 16) */\r
-#define TIMER_32_1_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_32_1 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'RTC' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- RTC_CONTROL -------------------------------- */\r
-#define RTC_CONTROL_BLOCK_ENABLE_Pos (0UL) /*!< RTC CONTROL: BLOCK_ENABLE (Bit 0) */\r
-#define RTC_CONTROL_BLOCK_ENABLE_Msk (0x1UL) /*!< RTC CONTROL: BLOCK_ENABLE (Bitfield-Mask: 0x01) */\r
-#define RTC_CONTROL_SOFT_RESET_Pos (1UL) /*!< RTC CONTROL: SOFT_RESET (Bit 1) */\r
-#define RTC_CONTROL_SOFT_RESET_Msk (0x2UL) /*!< RTC CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
-#define RTC_CONTROL_ALARM_ENABLE_Pos (3UL) /*!< RTC CONTROL: ALARM_ENABLE (Bit 3) */\r
-#define RTC_CONTROL_ALARM_ENABLE_Msk (0x8UL) /*!< RTC CONTROL: ALARM_ENABLE (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------ RTC_DAYLIGHT_SAVINGS_FORWARD ------------------------ */\r
-#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_MONTH_Pos (0UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_MONTH (Bit 0) */\r
-#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_MONTH_Msk (0xffUL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_MONTH (Bitfield-Mask: 0xff) */\r
-#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_DAY_OF_WEEK_Pos (8UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_DAY_OF_WEEK (Bit 8) */\r
-#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_DAY_OF_WEEK_Msk (0x700UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_DAY_OF_WEEK (Bitfield-Mask: 0x07) */\r
-#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_WEEK_Pos (16UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_WEEK (Bit 16) */\r
-#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_WEEK_Msk (0x70000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_WEEK (Bitfield-Mask: 0x07) */\r
-#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_HOUR_Pos (24UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_HOUR (Bit 24) */\r
-#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_HOUR_Msk (0x7f000000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_HOUR (Bitfield-Mask: 0x7f) */\r
-#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_AM_PM_Pos (31UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_AM_PM (Bit 31) */\r
-#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_AM_PM_Msk (0x80000000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_AM_PM (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------ RTC_DAYLIGHT_SAVINGS_BACKWARD ----------------------- */\r
-#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_MONTH_Pos (0UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_MONTH (Bit 0) */\r
-#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_MONTH_Msk (0xffUL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_MONTH (Bitfield-Mask: 0xff) */\r
-#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_DAY_OF_WEEK_Pos (8UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_DAY_OF_WEEK (Bit 8) */\r
-#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_DAY_OF_WEEK_Msk (0x700UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_DAY_OF_WEEK (Bitfield-Mask: 0x07) */\r
-#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_WEEK_Pos (16UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_WEEK (Bit 16) */\r
-#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_WEEK_Msk (0x70000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_WEEK (Bitfield-Mask: 0x07) */\r
-#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_HOUR_Pos (24UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_HOUR (Bit 24) */\r
-#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_HOUR_Msk (0x7f000000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_HOUR (Bitfield-Mask: 0x7f) */\r
-#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_AM_PM_Pos (31UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_AM_PM (Bit 31) */\r
-#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_AM_PM_Msk (0x80000000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_AM_PM (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'GPIO' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ------------------------------ GPIO_PIN_CONTROL ------------------------------ */\r
-#define GPIO_PIN_CONTROL_PU_PD_Pos (0UL) /*!< GPIO PIN_CONTROL: PU_PD (Bit 0) */\r
-#define GPIO_PIN_CONTROL_PU_PD_Msk (0x3UL) /*!< GPIO PIN_CONTROL: PU_PD (Bitfield-Mask: 0x03) */\r
-#define GPIO_PIN_CONTROL_PWR_Pos (2UL) /*!< GPIO PIN_CONTROL: PWR (Bit 2) */\r
-#define GPIO_PIN_CONTROL_PWR_Msk (0xcUL) /*!< GPIO PIN_CONTROL: PWR (Bitfield-Mask: 0x03) */\r
-#define GPIO_PIN_CONTROL_INT_DET_Pos (4UL) /*!< GPIO PIN_CONTROL: INT_DET (Bit 4) */\r
-#define GPIO_PIN_CONTROL_INT_DET_Msk (0x70UL) /*!< GPIO PIN_CONTROL: INT_DET (Bitfield-Mask: 0x07) */\r
-#define GPIO_PIN_CONTROL_EDGE_EN_Pos (7UL) /*!< GPIO PIN_CONTROL: EDGE_EN (Bit 7) */\r
-#define GPIO_PIN_CONTROL_EDGE_EN_Msk (0x80UL) /*!< GPIO PIN_CONTROL: EDGE_EN (Bitfield-Mask: 0x01) */\r
-#define GPIO_PIN_CONTROL_BUFFER_Pos (8UL) /*!< GPIO PIN_CONTROL: BUFFER (Bit 8) */\r
-#define GPIO_PIN_CONTROL_BUFFER_Msk (0x100UL) /*!< GPIO PIN_CONTROL: BUFFER (Bitfield-Mask: 0x01) */\r
-#define GPIO_PIN_CONTROL_DIR_Pos (9UL) /*!< GPIO PIN_CONTROL: DIR (Bit 9) */\r
-#define GPIO_PIN_CONTROL_DIR_Msk (0x200UL) /*!< GPIO PIN_CONTROL: DIR (Bitfield-Mask: 0x01) */\r
-#define GPIO_PIN_CONTROL_OUTPUT_WRITE_EN_Pos (10UL) /*!< GPIO PIN_CONTROL: OUTPUT_WRITE_EN (Bit 10) */\r
-#define GPIO_PIN_CONTROL_OUTPUT_WRITE_EN_Msk (0x400UL) /*!< GPIO PIN_CONTROL: OUTPUT_WRITE_EN (Bitfield-Mask: 0x01) */\r
-#define GPIO_PIN_CONTROL_POLARITY_Pos (11UL) /*!< GPIO PIN_CONTROL: POLARITY (Bit 11) */\r
-#define GPIO_PIN_CONTROL_POLARITY_Msk (0x800UL) /*!< GPIO PIN_CONTROL: POLARITY (Bitfield-Mask: 0x01) */\r
-#define GPIO_PIN_CONTROL_MUX_Pos (12UL) /*!< GPIO PIN_CONTROL: MUX (Bit 12) */\r
-#define GPIO_PIN_CONTROL_MUX_Msk (0x3000UL) /*!< GPIO PIN_CONTROL: MUX (Bitfield-Mask: 0x03) */\r
-#define GPIO_PIN_CONTROL_OUTPUT_Pos (16UL) /*!< GPIO PIN_CONTROL: OUTPUT (Bit 16) */\r
-#define GPIO_PIN_CONTROL_OUTPUT_Msk (0x10000UL) /*!< GPIO PIN_CONTROL: OUTPUT (Bitfield-Mask: 0x01) */\r
-#define GPIO_PIN_CONTROL_INPUT_Pos (24UL) /*!< GPIO PIN_CONTROL: INPUT (Bit 24) */\r
-#define GPIO_PIN_CONTROL_INPUT_Msk (0x1000000UL) /*!< GPIO PIN_CONTROL: INPUT (Bitfield-Mask: 0x01) */\r
-\r
-/* ---------------------------- GPIO_CONTROL2_000_067 --------------------------- */\r
-#define GPIO_CONTROL2_000_067_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_000_067: SLEW_RATE (Bit 0) */\r
-#define GPIO_CONTROL2_000_067_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_000_067: SLEW_RATE (Bitfield-Mask: 0x01) */\r
-#define GPIO_CONTROL2_000_067_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_000_067: DRIVE_STRENGTH (Bit 4) */\r
-#define GPIO_CONTROL2_000_067_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_000_067: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */\r
-\r
-/* ---------------------------- GPIO_CONTROL2_100_167 --------------------------- */\r
-#define GPIO_CONTROL2_100_167_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_100_167: SLEW_RATE (Bit 0) */\r
-#define GPIO_CONTROL2_100_167_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_100_167: SLEW_RATE (Bitfield-Mask: 0x01) */\r
-#define GPIO_CONTROL2_100_167_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_100_167: DRIVE_STRENGTH (Bit 4) */\r
-#define GPIO_CONTROL2_100_167_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_100_167: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */\r
-\r
-/* ---------------------------- GPIO_CONTROL2_200_267 --------------------------- */\r
-#define GPIO_CONTROL2_200_267_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_200_267: SLEW_RATE (Bit 0) */\r
-#define GPIO_CONTROL2_200_267_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_200_267: SLEW_RATE (Bitfield-Mask: 0x01) */\r
-#define GPIO_CONTROL2_200_267_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_200_267: DRIVE_STRENGTH (Bit 4) */\r
-#define GPIO_CONTROL2_200_267_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_200_267: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'DMA' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- DMA_CONTROL -------------------------------- */\r
-#define DMA_CONTROL_ACTIVATE_Pos (0UL) /*!< DMA CONTROL: ACTIVATE (Bit 0) */\r
-#define DMA_CONTROL_ACTIVATE_Msk (0x1UL) /*!< DMA CONTROL: ACTIVATE (Bitfield-Mask: 0x01) */\r
-#define DMA_CONTROL_SOFT_RESET_Pos (1UL) /*!< DMA CONTROL: SOFT_RESET (Bit 1) */\r
-#define DMA_CONTROL_SOFT_RESET_Msk (0x2UL) /*!< DMA CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'CH' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- CH_ACTIVATE -------------------------------- */\r
-#define CH_ACTIVATE_EN_Pos (0UL) /*!< CH ACTIVATE: EN (Bit 0) */\r
-#define CH_ACTIVATE_EN_Msk (0x1UL) /*!< CH ACTIVATE: EN (Bitfield-Mask: 0x01) */\r
-\r
-/* --------------------------------- CH_CONTROL --------------------------------- */\r
-#define CH_CONTROL_RUN_Pos (0UL) /*!< CH CONTROL: RUN (Bit 0) */\r
-#define CH_CONTROL_RUN_Msk (0x1UL) /*!< CH CONTROL: RUN (Bitfield-Mask: 0x01) */\r
-#define CH_CONTROL_REQUEST_Pos (1UL) /*!< CH CONTROL: REQUEST (Bit 1) */\r
-#define CH_CONTROL_REQUEST_Msk (0x2UL) /*!< CH CONTROL: REQUEST (Bitfield-Mask: 0x01) */\r
-#define CH_CONTROL_DONE_Pos (2UL) /*!< CH CONTROL: DONE (Bit 2) */\r
-#define CH_CONTROL_DONE_Msk (0x4UL) /*!< CH CONTROL: DONE (Bitfield-Mask: 0x01) */\r
-#define CH_CONTROL_STATUS_Pos (3UL) /*!< CH CONTROL: STATUS (Bit 3) */\r
-#define CH_CONTROL_STATUS_Msk (0x18UL) /*!< CH CONTROL: STATUS (Bitfield-Mask: 0x03) */\r
-#define CH_CONTROL_BUSY_Pos (5UL) /*!< CH CONTROL: BUSY (Bit 5) */\r
-#define CH_CONTROL_BUSY_Msk (0x20UL) /*!< CH CONTROL: BUSY (Bitfield-Mask: 0x01) */\r
-#define CH_CONTROL_TX_DIRECTION_Pos (8UL) /*!< CH CONTROL: TX_DIRECTION (Bit 8) */\r
-#define CH_CONTROL_TX_DIRECTION_Msk (0x100UL) /*!< CH CONTROL: TX_DIRECTION (Bitfield-Mask: 0x01) */\r
-#define CH_CONTROL_HARDWARE_FLOW_CONTROL_DEVICE_Pos (9UL) /*!< CH CONTROL: HARDWARE_FLOW_CONTROL_DEVICE (Bit 9) */\r
-#define CH_CONTROL_HARDWARE_FLOW_CONTROL_DEVICE_Msk (0xfe00UL) /*!< CH CONTROL: HARDWARE_FLOW_CONTROL_DEVICE (Bitfield-Mask: 0x7f) */\r
-#define CH_CONTROL_INCREMENT_MEM_ADDR_Pos (16UL) /*!< CH CONTROL: INCREMENT_MEM_ADDR (Bit 16) */\r
-#define CH_CONTROL_INCREMENT_MEM_ADDR_Msk (0x10000UL) /*!< CH CONTROL: INCREMENT_MEM_ADDR (Bitfield-Mask: 0x01) */\r
-#define CH_CONTROL_INCREMENT_DEVICE_ADDR_Pos (17UL) /*!< CH CONTROL: INCREMENT_DEVICE_ADDR (Bit 17) */\r
-#define CH_CONTROL_INCREMENT_DEVICE_ADDR_Msk (0x20000UL) /*!< CH CONTROL: INCREMENT_DEVICE_ADDR (Bitfield-Mask: 0x01) */\r
-#define CH_CONTROL_LOCK_Pos (18UL) /*!< CH CONTROL: LOCK (Bit 18) */\r
-#define CH_CONTROL_LOCK_Msk (0x40000UL) /*!< CH CONTROL: LOCK (Bitfield-Mask: 0x01) */\r
-#define CH_CONTROL_DISABLE_HW_FLOW_CONTROL_Pos (19UL) /*!< CH CONTROL: DISABLE_HW_FLOW_CONTROL (Bit 19) */\r
-#define CH_CONTROL_DISABLE_HW_FLOW_CONTROL_Msk (0x80000UL) /*!< CH CONTROL: DISABLE_HW_FLOW_CONTROL (Bitfield-Mask: 0x01) */\r
-#define CH_CONTROL_TRANSFER_SIZE_Pos (20UL) /*!< CH CONTROL: TRANSFER_SIZE (Bit 20) */\r
-#define CH_CONTROL_TRANSFER_SIZE_Msk (0x700000UL) /*!< CH CONTROL: TRANSFER_SIZE (Bitfield-Mask: 0x07) */\r
-#define CH_CONTROL_TRANSFER_GO_Pos (24UL) /*!< CH CONTROL: TRANSFER_GO (Bit 24) */\r
-#define CH_CONTROL_TRANSFER_GO_Msk (0x1000000UL) /*!< CH CONTROL: TRANSFER_GO (Bitfield-Mask: 0x01) */\r
-#define CH_CONTROL_TRANSFER_ABORT_Pos (25UL) /*!< CH CONTROL: TRANSFER_ABORT (Bit 25) */\r
-#define CH_CONTROL_TRANSFER_ABORT_Msk (0x2000000UL) /*!< CH CONTROL: TRANSFER_ABORT (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- CH_INT_STATUS ------------------------------- */\r
-#define CH_INT_STATUS_BUS_ERROR_Pos (0UL) /*!< CH INT_STATUS: BUS_ERROR (Bit 0) */\r
-#define CH_INT_STATUS_BUS_ERROR_Msk (0x1UL) /*!< CH INT_STATUS: BUS_ERROR (Bitfield-Mask: 0x01) */\r
-#define CH_INT_STATUS_FLOW_CONTROL_Pos (1UL) /*!< CH INT_STATUS: FLOW_CONTROL (Bit 1) */\r
-#define CH_INT_STATUS_FLOW_CONTROL_Msk (0x2UL) /*!< CH INT_STATUS: FLOW_CONTROL (Bitfield-Mask: 0x01) */\r
-#define CH_INT_STATUS_DONE_Pos (2UL) /*!< CH INT_STATUS: DONE (Bit 2) */\r
-#define CH_INT_STATUS_DONE_Msk (0x4UL) /*!< CH INT_STATUS: DONE (Bitfield-Mask: 0x01) */\r
-\r
-/* ---------------------------------- CH_INT_EN --------------------------------- */\r
-#define CH_INT_EN_BUS_ERROR_Pos (0UL) /*!< CH INT_EN: BUS_ERROR (Bit 0) */\r
-#define CH_INT_EN_BUS_ERROR_Msk (0x1UL) /*!< CH INT_EN: BUS_ERROR (Bitfield-Mask: 0x01) */\r
-#define CH_INT_EN_FLOW_CONTROL_Pos (1UL) /*!< CH INT_EN: FLOW_CONTROL (Bit 1) */\r
-#define CH_INT_EN_FLOW_CONTROL_Msk (0x2UL) /*!< CH INT_EN: FLOW_CONTROL (Bitfield-Mask: 0x01) */\r
-#define CH_INT_EN_DONE_Pos (2UL) /*!< CH INT_EN: DONE (Bit 2) */\r
-#define CH_INT_EN_DONE_Msk (0x4UL) /*!< CH INT_EN: DONE (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SMB0' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- SMB0_CONTROL -------------------------------- */\r
-#define SMB0_CONTROL_ACK_Pos (0UL) /*!< SMB0 CONTROL: ACK (Bit 0) */\r
-#define SMB0_CONTROL_ACK_Msk (0x1UL) /*!< SMB0 CONTROL: ACK (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONTROL_STO_Pos (1UL) /*!< SMB0 CONTROL: STO (Bit 1) */\r
-#define SMB0_CONTROL_STO_Msk (0x2UL) /*!< SMB0 CONTROL: STO (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONTROL_STA_Pos (2UL) /*!< SMB0 CONTROL: STA (Bit 2) */\r
-#define SMB0_CONTROL_STA_Msk (0x4UL) /*!< SMB0 CONTROL: STA (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONTROL_ENI_Pos (3UL) /*!< SMB0 CONTROL: ENI (Bit 3) */\r
-#define SMB0_CONTROL_ENI_Msk (0x8UL) /*!< SMB0 CONTROL: ENI (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONTROL_ESO_Pos (6UL) /*!< SMB0 CONTROL: ESO (Bit 6) */\r
-#define SMB0_CONTROL_ESO_Msk (0x40UL) /*!< SMB0 CONTROL: ESO (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONTROL_PIN_Pos (7UL) /*!< SMB0 CONTROL: PIN (Bit 7) */\r
-#define SMB0_CONTROL_PIN_Msk (0x80UL) /*!< SMB0 CONTROL: PIN (Bitfield-Mask: 0x01) */\r
-\r
-/* --------------------------------- SMB0_STATUS -------------------------------- */\r
-#define SMB0_STATUS_nBB_Pos (0UL) /*!< SMB0 STATUS: nBB (Bit 0) */\r
-#define SMB0_STATUS_nBB_Msk (0x1UL) /*!< SMB0 STATUS: nBB (Bitfield-Mask: 0x01) */\r
-#define SMB0_STATUS_LAB_Pos (1UL) /*!< SMB0 STATUS: LAB (Bit 1) */\r
-#define SMB0_STATUS_LAB_Msk (0x2UL) /*!< SMB0 STATUS: LAB (Bitfield-Mask: 0x01) */\r
-#define SMB0_STATUS_AAS_Pos (2UL) /*!< SMB0 STATUS: AAS (Bit 2) */\r
-#define SMB0_STATUS_AAS_Msk (0x4UL) /*!< SMB0 STATUS: AAS (Bitfield-Mask: 0x01) */\r
-#define SMB0_STATUS_LRB_AD0_Pos (3UL) /*!< SMB0 STATUS: LRB_AD0 (Bit 3) */\r
-#define SMB0_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB0 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */\r
-#define SMB0_STATUS_BER_Pos (4UL) /*!< SMB0 STATUS: BER (Bit 4) */\r
-#define SMB0_STATUS_BER_Msk (0x10UL) /*!< SMB0 STATUS: BER (Bitfield-Mask: 0x01) */\r
-#define SMB0_STATUS_STS_Pos (5UL) /*!< SMB0 STATUS: STS (Bit 5) */\r
-#define SMB0_STATUS_STS_Msk (0x20UL) /*!< SMB0 STATUS: STS (Bitfield-Mask: 0x01) */\r
-#define SMB0_STATUS_SAD_Pos (6UL) /*!< SMB0 STATUS: SAD (Bit 6) */\r
-#define SMB0_STATUS_SAD_Msk (0x40UL) /*!< SMB0 STATUS: SAD (Bitfield-Mask: 0x01) */\r
-#define SMB0_STATUS_PIN_Pos (7UL) /*!< SMB0 STATUS: PIN (Bit 7) */\r
-#define SMB0_STATUS_PIN_Msk (0x80UL) /*!< SMB0 STATUS: PIN (Bitfield-Mask: 0x01) */\r
-\r
-/* ---------------------------------- SMB0_OWN ---------------------------------- */\r
-#define SMB0_OWN_ADDRESS_1_Pos (0UL) /*!< SMB0 OWN: ADDRESS_1 (Bit 0) */\r
-#define SMB0_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB0 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */\r
-#define SMB0_OWN_ADDRESS_2_Pos (8UL) /*!< SMB0 OWN: ADDRESS_2 (Bit 8) */\r
-#define SMB0_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB0 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */\r
-\r
-/* ----------------------------- SMB0_MASTER_COMMAND ---------------------------- */\r
-#define SMB0_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB0 MASTER_COMMAND: MRUN (Bit 0) */\r
-#define SMB0_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB0 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */\r
-#define SMB0_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB0 MASTER_COMMAND: MPROCEED (Bit 1) */\r
-#define SMB0_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB0 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */\r
-#define SMB0_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB0 MASTER_COMMAND: START0 (Bit 8) */\r
-#define SMB0_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB0 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */\r
-#define SMB0_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB0 MASTER_COMMAND: STARTN (Bit 9) */\r
-#define SMB0_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB0 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */\r
-#define SMB0_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB0 MASTER_COMMAND: STOP (Bit 10) */\r
-#define SMB0_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB0 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */\r
-#define SMB0_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB0 MASTER_COMMAND: PEC_TERM (Bit 11) */\r
-#define SMB0_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB0 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */\r
-#define SMB0_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB0 MASTER_COMMAND: READM (Bit 12) */\r
-#define SMB0_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB0 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */\r
-#define SMB0_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB0 MASTER_COMMAND: READ_PEC (Bit 13) */\r
-#define SMB0_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB0 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */\r
-#define SMB0_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB0 MASTER_COMMAND: WRITECOUNT (Bit 16) */\r
-#define SMB0_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB0 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */\r
-#define SMB0_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB0 MASTER_COMMAND: READCOUNT (Bit 24) */\r
-#define SMB0_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB0 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */\r
-\r
-/* ----------------------------- SMB0_SLAVE_COMMAND ----------------------------- */\r
-#define SMB0_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB0 SLAVE_COMMAND: SRUN (Bit 0) */\r
-#define SMB0_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB0 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */\r
-#define SMB0_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB0 SLAVE_COMMAND: SPROCEED (Bit 1) */\r
-#define SMB0_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB0 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */\r
-#define SMB0_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */\r
-#define SMB0_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */\r
-#define SMB0_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */\r
-#define SMB0_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */\r
-#define SMB0_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */\r
-#define SMB0_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */\r
-\r
-/* ------------------------------- SMB0_COMPLETION ------------------------------ */\r
-#define SMB0_COMPLETION_DTEN_Pos (2UL) /*!< SMB0 COMPLETION: DTEN (Bit 2) */\r
-#define SMB0_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB0 COMPLETION: DTEN (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_MCEN_Pos (3UL) /*!< SMB0 COMPLETION: MCEN (Bit 3) */\r
-#define SMB0_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB0 COMPLETION: MCEN (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_SCEN_Pos (4UL) /*!< SMB0 COMPLETION: SCEN (Bit 4) */\r
-#define SMB0_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB0 COMPLETION: SCEN (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_BIDEN_Pos (5UL) /*!< SMB0 COMPLETION: BIDEN (Bit 5) */\r
-#define SMB0_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB0 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_TIMERR_Pos (6UL) /*!< SMB0 COMPLETION: TIMERR (Bit 6) */\r
-#define SMB0_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB0 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_DTO_Pos (8UL) /*!< SMB0 COMPLETION: DTO (Bit 8) */\r
-#define SMB0_COMPLETION_DTO_Msk (0x100UL) /*!< SMB0 COMPLETION: DTO (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_MCTO_Pos (9UL) /*!< SMB0 COMPLETION: MCTO (Bit 9) */\r
-#define SMB0_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB0 COMPLETION: MCTO (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_SCTO_Pos (10UL) /*!< SMB0 COMPLETION: SCTO (Bit 10) */\r
-#define SMB0_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB0 COMPLETION: SCTO (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_CHDL_Pos (11UL) /*!< SMB0 COMPLETION: CHDL (Bit 11) */\r
-#define SMB0_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB0 COMPLETION: CHDL (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_CHDH_Pos (12UL) /*!< SMB0 COMPLETION: CHDH (Bit 12) */\r
-#define SMB0_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB0 COMPLETION: CHDH (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_BER_Pos (13UL) /*!< SMB0 COMPLETION: BER (Bit 13) */\r
-#define SMB0_COMPLETION_BER_Msk (0x2000UL) /*!< SMB0 COMPLETION: BER (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_LAB_Pos (14UL) /*!< SMB0 COMPLETION: LAB (Bit 14) */\r
-#define SMB0_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB0 COMPLETION: LAB (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_SNAKR_Pos (16UL) /*!< SMB0 COMPLETION: SNAKR (Bit 16) */\r
-#define SMB0_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB0 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_STR_Pos (17UL) /*!< SMB0 COMPLETION: STR (Bit 17) */\r
-#define SMB0_COMPLETION_STR_Msk (0x20000UL) /*!< SMB0 COMPLETION: STR (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_SPROT_Pos (19UL) /*!< SMB0 COMPLETION: SPROT (Bit 19) */\r
-#define SMB0_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB0 COMPLETION: SPROT (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB0 COMPLETION: REPEAT_READ (Bit 20) */\r
-#define SMB0_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB0 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB0 COMPLETION: REPEAT_WRITE (Bit 21) */\r
-#define SMB0_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB0 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_MNAKX_Pos (24UL) /*!< SMB0 COMPLETION: MNAKX (Bit 24) */\r
-#define SMB0_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB0 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_MTR_Pos (25UL) /*!< SMB0 COMPLETION: MTR (Bit 25) */\r
-#define SMB0_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB0 COMPLETION: MTR (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_IDLE_Pos (29UL) /*!< SMB0 COMPLETION: IDLE (Bit 29) */\r
-#define SMB0_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB0 COMPLETION: IDLE (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_MDONE_Pos (30UL) /*!< SMB0 COMPLETION: MDONE (Bit 30) */\r
-#define SMB0_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB0 COMPLETION: MDONE (Bitfield-Mask: 0x01) */\r
-#define SMB0_COMPLETION_SDONE_Pos (31UL) /*!< SMB0 COMPLETION: SDONE (Bit 31) */\r
-#define SMB0_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB0 COMPLETION: SDONE (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------ SMB0_IDLE_SCALING ----------------------------- */\r
-#define SMB0_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB0 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */\r
-#define SMB0_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB0 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */\r
-#define SMB0_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB0 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */\r
-#define SMB0_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB0 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */\r
-\r
-/* ----------------------------- SMB0_CONFIGURATION ----------------------------- */\r
-#define SMB0_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB0 CONFIGURATION: PORT_SEL (Bit 0) */\r
-#define SMB0_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB0 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */\r
-#define SMB0_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB0 CONFIGURATION: TCEN (Bit 4) */\r
-#define SMB0_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB0 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB0 CONFIGURATION: SLOW_CLOCK (Bit 5) */\r
-#define SMB0_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB0 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB0 CONFIGURATION: PECEN (Bit 7) */\r
-#define SMB0_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB0 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB0 CONFIGURATION: DFEN (Bit 8) */\r
-#define SMB0_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB0 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_RESET_Pos (9UL) /*!< SMB0 CONFIGURATION: RESET (Bit 9) */\r
-#define SMB0_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB0 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB0 CONFIGURATION: ENAB (Bit 10) */\r
-#define SMB0_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB0 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_DSA_Pos (11UL) /*!< SMB0 CONFIGURATION: DSA (Bit 11) */\r
-#define SMB0_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB0 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB0 CONFIGURATION: FAIR (Bit 12) */\r
-#define SMB0_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB0 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB0 CONFIGURATION: GC_DIS (Bit 14) */\r
-#define SMB0_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB0 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB0 CONFIGURATION: FLUSH_SXBUF (Bit 16) */\r
-#define SMB0_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB0 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB0 CONFIGURATION: FLUSH_SRBUF (Bit 17) */\r
-#define SMB0_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB0 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB0 CONFIGURATION: FLUSH_MXBUF (Bit 18) */\r
-#define SMB0_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB0 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB0 CONFIGURATION: FLUSH_MRBUF (Bit 19) */\r
-#define SMB0_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB0 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB0 CONFIGURATION: EN_AAS (Bit 28) */\r
-#define SMB0_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB0 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB0 CONFIGURATION: ENIDI (Bit 29) */\r
-#define SMB0_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB0 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB0 CONFIGURATION: ENMI (Bit 30) */\r
-#define SMB0_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB0 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */\r
-#define SMB0_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB0 CONFIGURATION: ENSI (Bit 31) */\r
-#define SMB0_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB0 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------- SMB0_BUS_CLOCK ------------------------------- */\r
-#define SMB0_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB0 BUS_CLOCK: LOW_PERIOD (Bit 0) */\r
-#define SMB0_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB0 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */\r
-#define SMB0_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB0 BUS_CLOCK: HIGH_PERIOD (Bit 8) */\r
-#define SMB0_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB0 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */\r
-\r
-/* ---------------------------- SMB0_BIT_BANG_CONTROL --------------------------- */\r
-#define SMB0_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB0 BIT_BANG_CONTROL: BBEN (Bit 0) */\r
-#define SMB0_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB0 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */\r
-#define SMB0_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB0 BIT_BANG_CONTROL: CLDIR (Bit 1) */\r
-#define SMB0_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB0 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */\r
-#define SMB0_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB0 BIT_BANG_CONTROL: DADIR (Bit 2) */\r
-#define SMB0_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB0 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */\r
-#define SMB0_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLK (Bit 3) */\r
-#define SMB0_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */\r
-#define SMB0_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB0 BIT_BANG_CONTROL: BBDAT (Bit 4) */\r
-#define SMB0_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB0 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */\r
-#define SMB0_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLKI (Bit 5) */\r
-#define SMB0_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */\r
-#define SMB0_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB0 BIT_BANG_CONTROL: BBDATI (Bit 6) */\r
-#define SMB0_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB0 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------ SMB0_DATA_TIMING ------------------------------ */\r
-#define SMB0_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB0 DATA_TIMING: DATA_HOLD (Bit 0) */\r
-#define SMB0_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB0 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */\r
-#define SMB0_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB0 DATA_TIMING: RESTART_SETUP (Bit 8) */\r
-#define SMB0_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB0 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */\r
-#define SMB0_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB0 DATA_TIMING: STOP_SETUP (Bit 16) */\r
-#define SMB0_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB0 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */\r
-#define SMB0_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB0 DATA_TIMING: START_HOLD (Bit 24) */\r
-#define SMB0_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB0 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */\r
-\r
-/* ---------------------------- SMB0_TIME_OUT_SCALING --------------------------- */\r
-#define SMB0_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB0 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */\r
-#define SMB0_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB0 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */\r
-#define SMB0_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB0 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */\r
-#define SMB0_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB0 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */\r
-#define SMB0_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB0 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */\r
-#define SMB0_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB0 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */\r
-#define SMB0_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB0 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */\r
-#define SMB0_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB0 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SMB1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- SMB1_STATUS -------------------------------- */\r
-#define SMB1_STATUS_nBB_Pos (0UL) /*!< SMB1 STATUS: nBB (Bit 0) */\r
-#define SMB1_STATUS_nBB_Msk (0x1UL) /*!< SMB1 STATUS: nBB (Bitfield-Mask: 0x01) */\r
-#define SMB1_STATUS_LAB_Pos (1UL) /*!< SMB1 STATUS: LAB (Bit 1) */\r
-#define SMB1_STATUS_LAB_Msk (0x2UL) /*!< SMB1 STATUS: LAB (Bitfield-Mask: 0x01) */\r
-#define SMB1_STATUS_AAS_Pos (2UL) /*!< SMB1 STATUS: AAS (Bit 2) */\r
-#define SMB1_STATUS_AAS_Msk (0x4UL) /*!< SMB1 STATUS: AAS (Bitfield-Mask: 0x01) */\r
-#define SMB1_STATUS_LRB_AD0_Pos (3UL) /*!< SMB1 STATUS: LRB_AD0 (Bit 3) */\r
-#define SMB1_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB1 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */\r
-#define SMB1_STATUS_BER_Pos (4UL) /*!< SMB1 STATUS: BER (Bit 4) */\r
-#define SMB1_STATUS_BER_Msk (0x10UL) /*!< SMB1 STATUS: BER (Bitfield-Mask: 0x01) */\r
-#define SMB1_STATUS_STS_Pos (5UL) /*!< SMB1 STATUS: STS (Bit 5) */\r
-#define SMB1_STATUS_STS_Msk (0x20UL) /*!< SMB1 STATUS: STS (Bitfield-Mask: 0x01) */\r
-#define SMB1_STATUS_SAD_Pos (6UL) /*!< SMB1 STATUS: SAD (Bit 6) */\r
-#define SMB1_STATUS_SAD_Msk (0x40UL) /*!< SMB1 STATUS: SAD (Bitfield-Mask: 0x01) */\r
-#define SMB1_STATUS_PIN_Pos (7UL) /*!< SMB1 STATUS: PIN (Bit 7) */\r
-#define SMB1_STATUS_PIN_Msk (0x80UL) /*!< SMB1 STATUS: PIN (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- SMB1_CONTROL -------------------------------- */\r
-#define SMB1_CONTROL_ACK_Pos (0UL) /*!< SMB1 CONTROL: ACK (Bit 0) */\r
-#define SMB1_CONTROL_ACK_Msk (0x1UL) /*!< SMB1 CONTROL: ACK (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONTROL_STO_Pos (1UL) /*!< SMB1 CONTROL: STO (Bit 1) */\r
-#define SMB1_CONTROL_STO_Msk (0x2UL) /*!< SMB1 CONTROL: STO (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONTROL_STA_Pos (2UL) /*!< SMB1 CONTROL: STA (Bit 2) */\r
-#define SMB1_CONTROL_STA_Msk (0x4UL) /*!< SMB1 CONTROL: STA (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONTROL_ENI_Pos (3UL) /*!< SMB1 CONTROL: ENI (Bit 3) */\r
-#define SMB1_CONTROL_ENI_Msk (0x8UL) /*!< SMB1 CONTROL: ENI (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONTROL_ESO_Pos (6UL) /*!< SMB1 CONTROL: ESO (Bit 6) */\r
-#define SMB1_CONTROL_ESO_Msk (0x40UL) /*!< SMB1 CONTROL: ESO (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONTROL_PIN_Pos (7UL) /*!< SMB1 CONTROL: PIN (Bit 7) */\r
-#define SMB1_CONTROL_PIN_Msk (0x80UL) /*!< SMB1 CONTROL: PIN (Bitfield-Mask: 0x01) */\r
-\r
-/* ---------------------------------- SMB1_OWN ---------------------------------- */\r
-#define SMB1_OWN_ADDRESS_1_Pos (0UL) /*!< SMB1 OWN: ADDRESS_1 (Bit 0) */\r
-#define SMB1_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB1 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */\r
-#define SMB1_OWN_ADDRESS_2_Pos (8UL) /*!< SMB1 OWN: ADDRESS_2 (Bit 8) */\r
-#define SMB1_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB1 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */\r
-\r
-/* ----------------------------- SMB1_MASTER_COMMAND ---------------------------- */\r
-#define SMB1_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB1 MASTER_COMMAND: MRUN (Bit 0) */\r
-#define SMB1_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB1 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */\r
-#define SMB1_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB1 MASTER_COMMAND: MPROCEED (Bit 1) */\r
-#define SMB1_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB1 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */\r
-#define SMB1_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB1 MASTER_COMMAND: START0 (Bit 8) */\r
-#define SMB1_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB1 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */\r
-#define SMB1_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB1 MASTER_COMMAND: STARTN (Bit 9) */\r
-#define SMB1_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB1 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */\r
-#define SMB1_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB1 MASTER_COMMAND: STOP (Bit 10) */\r
-#define SMB1_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB1 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */\r
-#define SMB1_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB1 MASTER_COMMAND: PEC_TERM (Bit 11) */\r
-#define SMB1_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB1 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */\r
-#define SMB1_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB1 MASTER_COMMAND: READM (Bit 12) */\r
-#define SMB1_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB1 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */\r
-#define SMB1_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB1 MASTER_COMMAND: READ_PEC (Bit 13) */\r
-#define SMB1_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB1 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */\r
-#define SMB1_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB1 MASTER_COMMAND: WRITECOUNT (Bit 16) */\r
-#define SMB1_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB1 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */\r
-#define SMB1_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB1 MASTER_COMMAND: READCOUNT (Bit 24) */\r
-#define SMB1_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB1 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */\r
-\r
-/* ----------------------------- SMB1_SLAVE_COMMAND ----------------------------- */\r
-#define SMB1_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB1 SLAVE_COMMAND: SRUN (Bit 0) */\r
-#define SMB1_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB1 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */\r
-#define SMB1_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB1 SLAVE_COMMAND: SPROCEED (Bit 1) */\r
-#define SMB1_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB1 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */\r
-#define SMB1_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */\r
-#define SMB1_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */\r
-#define SMB1_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */\r
-#define SMB1_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */\r
-#define SMB1_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */\r
-#define SMB1_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */\r
-\r
-/* ------------------------------- SMB1_COMPLETION ------------------------------ */\r
-#define SMB1_COMPLETION_DTEN_Pos (2UL) /*!< SMB1 COMPLETION: DTEN (Bit 2) */\r
-#define SMB1_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB1 COMPLETION: DTEN (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_MCEN_Pos (3UL) /*!< SMB1 COMPLETION: MCEN (Bit 3) */\r
-#define SMB1_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB1 COMPLETION: MCEN (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_SCEN_Pos (4UL) /*!< SMB1 COMPLETION: SCEN (Bit 4) */\r
-#define SMB1_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB1 COMPLETION: SCEN (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_BIDEN_Pos (5UL) /*!< SMB1 COMPLETION: BIDEN (Bit 5) */\r
-#define SMB1_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB1 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_TIMERR_Pos (6UL) /*!< SMB1 COMPLETION: TIMERR (Bit 6) */\r
-#define SMB1_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB1 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_DTO_Pos (8UL) /*!< SMB1 COMPLETION: DTO (Bit 8) */\r
-#define SMB1_COMPLETION_DTO_Msk (0x100UL) /*!< SMB1 COMPLETION: DTO (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_MCTO_Pos (9UL) /*!< SMB1 COMPLETION: MCTO (Bit 9) */\r
-#define SMB1_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB1 COMPLETION: MCTO (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_SCTO_Pos (10UL) /*!< SMB1 COMPLETION: SCTO (Bit 10) */\r
-#define SMB1_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB1 COMPLETION: SCTO (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_CHDL_Pos (11UL) /*!< SMB1 COMPLETION: CHDL (Bit 11) */\r
-#define SMB1_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB1 COMPLETION: CHDL (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_CHDH_Pos (12UL) /*!< SMB1 COMPLETION: CHDH (Bit 12) */\r
-#define SMB1_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB1 COMPLETION: CHDH (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_BER_Pos (13UL) /*!< SMB1 COMPLETION: BER (Bit 13) */\r
-#define SMB1_COMPLETION_BER_Msk (0x2000UL) /*!< SMB1 COMPLETION: BER (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_LAB_Pos (14UL) /*!< SMB1 COMPLETION: LAB (Bit 14) */\r
-#define SMB1_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB1 COMPLETION: LAB (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_SNAKR_Pos (16UL) /*!< SMB1 COMPLETION: SNAKR (Bit 16) */\r
-#define SMB1_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB1 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_STR_Pos (17UL) /*!< SMB1 COMPLETION: STR (Bit 17) */\r
-#define SMB1_COMPLETION_STR_Msk (0x20000UL) /*!< SMB1 COMPLETION: STR (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_SPROT_Pos (19UL) /*!< SMB1 COMPLETION: SPROT (Bit 19) */\r
-#define SMB1_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB1 COMPLETION: SPROT (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB1 COMPLETION: REPEAT_READ (Bit 20) */\r
-#define SMB1_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB1 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB1 COMPLETION: REPEAT_WRITE (Bit 21) */\r
-#define SMB1_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB1 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_MNAKX_Pos (24UL) /*!< SMB1 COMPLETION: MNAKX (Bit 24) */\r
-#define SMB1_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB1 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_MTR_Pos (25UL) /*!< SMB1 COMPLETION: MTR (Bit 25) */\r
-#define SMB1_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB1 COMPLETION: MTR (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_IDLE_Pos (29UL) /*!< SMB1 COMPLETION: IDLE (Bit 29) */\r
-#define SMB1_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB1 COMPLETION: IDLE (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_MDONE_Pos (30UL) /*!< SMB1 COMPLETION: MDONE (Bit 30) */\r
-#define SMB1_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB1 COMPLETION: MDONE (Bitfield-Mask: 0x01) */\r
-#define SMB1_COMPLETION_SDONE_Pos (31UL) /*!< SMB1 COMPLETION: SDONE (Bit 31) */\r
-#define SMB1_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB1 COMPLETION: SDONE (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------ SMB1_IDLE_SCALING ----------------------------- */\r
-#define SMB1_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB1 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */\r
-#define SMB1_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB1 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */\r
-#define SMB1_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB1 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */\r
-#define SMB1_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB1 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */\r
-\r
-/* ----------------------------- SMB1_CONFIGURATION ----------------------------- */\r
-#define SMB1_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB1 CONFIGURATION: PORT_SEL (Bit 0) */\r
-#define SMB1_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB1 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */\r
-#define SMB1_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB1 CONFIGURATION: TCEN (Bit 4) */\r
-#define SMB1_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB1 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB1 CONFIGURATION: SLOW_CLOCK (Bit 5) */\r
-#define SMB1_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB1 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB1 CONFIGURATION: PECEN (Bit 7) */\r
-#define SMB1_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB1 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB1 CONFIGURATION: DFEN (Bit 8) */\r
-#define SMB1_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB1 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_RESET_Pos (9UL) /*!< SMB1 CONFIGURATION: RESET (Bit 9) */\r
-#define SMB1_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB1 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB1 CONFIGURATION: ENAB (Bit 10) */\r
-#define SMB1_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB1 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_DSA_Pos (11UL) /*!< SMB1 CONFIGURATION: DSA (Bit 11) */\r
-#define SMB1_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB1 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB1 CONFIGURATION: FAIR (Bit 12) */\r
-#define SMB1_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB1 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB1 CONFIGURATION: GC_DIS (Bit 14) */\r
-#define SMB1_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB1 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB1 CONFIGURATION: FLUSH_SXBUF (Bit 16) */\r
-#define SMB1_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB1 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB1 CONFIGURATION: FLUSH_SRBUF (Bit 17) */\r
-#define SMB1_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB1 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB1 CONFIGURATION: FLUSH_MXBUF (Bit 18) */\r
-#define SMB1_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB1 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB1 CONFIGURATION: FLUSH_MRBUF (Bit 19) */\r
-#define SMB1_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB1 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB1 CONFIGURATION: EN_AAS (Bit 28) */\r
-#define SMB1_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB1 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB1 CONFIGURATION: ENIDI (Bit 29) */\r
-#define SMB1_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB1 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB1 CONFIGURATION: ENMI (Bit 30) */\r
-#define SMB1_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB1 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */\r
-#define SMB1_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB1 CONFIGURATION: ENSI (Bit 31) */\r
-#define SMB1_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB1 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------- SMB1_BUS_CLOCK ------------------------------- */\r
-#define SMB1_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB1 BUS_CLOCK: LOW_PERIOD (Bit 0) */\r
-#define SMB1_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB1 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */\r
-#define SMB1_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB1 BUS_CLOCK: HIGH_PERIOD (Bit 8) */\r
-#define SMB1_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB1 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */\r
-\r
-/* ---------------------------- SMB1_BIT_BANG_CONTROL --------------------------- */\r
-#define SMB1_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB1 BIT_BANG_CONTROL: BBEN (Bit 0) */\r
-#define SMB1_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB1 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */\r
-#define SMB1_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB1 BIT_BANG_CONTROL: CLDIR (Bit 1) */\r
-#define SMB1_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB1 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */\r
-#define SMB1_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB1 BIT_BANG_CONTROL: DADIR (Bit 2) */\r
-#define SMB1_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB1 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */\r
-#define SMB1_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLK (Bit 3) */\r
-#define SMB1_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */\r
-#define SMB1_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB1 BIT_BANG_CONTROL: BBDAT (Bit 4) */\r
-#define SMB1_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB1 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */\r
-#define SMB1_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLKI (Bit 5) */\r
-#define SMB1_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */\r
-#define SMB1_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB1 BIT_BANG_CONTROL: BBDATI (Bit 6) */\r
-#define SMB1_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB1 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------ SMB1_DATA_TIMING ------------------------------ */\r
-#define SMB1_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB1 DATA_TIMING: DATA_HOLD (Bit 0) */\r
-#define SMB1_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB1 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */\r
-#define SMB1_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB1 DATA_TIMING: RESTART_SETUP (Bit 8) */\r
-#define SMB1_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB1 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */\r
-#define SMB1_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB1 DATA_TIMING: STOP_SETUP (Bit 16) */\r
-#define SMB1_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB1 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */\r
-#define SMB1_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB1 DATA_TIMING: START_HOLD (Bit 24) */\r
-#define SMB1_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB1 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */\r
-\r
-/* ---------------------------- SMB1_TIME_OUT_SCALING --------------------------- */\r
-#define SMB1_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB1 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */\r
-#define SMB1_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB1 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */\r
-#define SMB1_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB1 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */\r
-#define SMB1_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB1 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */\r
-#define SMB1_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB1 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */\r
-#define SMB1_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB1 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */\r
-#define SMB1_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB1 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */\r
-#define SMB1_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB1 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SMB2' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- SMB2_STATUS -------------------------------- */\r
-#define SMB2_STATUS_nBB_Pos (0UL) /*!< SMB2 STATUS: nBB (Bit 0) */\r
-#define SMB2_STATUS_nBB_Msk (0x1UL) /*!< SMB2 STATUS: nBB (Bitfield-Mask: 0x01) */\r
-#define SMB2_STATUS_LAB_Pos (1UL) /*!< SMB2 STATUS: LAB (Bit 1) */\r
-#define SMB2_STATUS_LAB_Msk (0x2UL) /*!< SMB2 STATUS: LAB (Bitfield-Mask: 0x01) */\r
-#define SMB2_STATUS_AAS_Pos (2UL) /*!< SMB2 STATUS: AAS (Bit 2) */\r
-#define SMB2_STATUS_AAS_Msk (0x4UL) /*!< SMB2 STATUS: AAS (Bitfield-Mask: 0x01) */\r
-#define SMB2_STATUS_LRB_AD0_Pos (3UL) /*!< SMB2 STATUS: LRB_AD0 (Bit 3) */\r
-#define SMB2_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB2 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */\r
-#define SMB2_STATUS_BER_Pos (4UL) /*!< SMB2 STATUS: BER (Bit 4) */\r
-#define SMB2_STATUS_BER_Msk (0x10UL) /*!< SMB2 STATUS: BER (Bitfield-Mask: 0x01) */\r
-#define SMB2_STATUS_STS_Pos (5UL) /*!< SMB2 STATUS: STS (Bit 5) */\r
-#define SMB2_STATUS_STS_Msk (0x20UL) /*!< SMB2 STATUS: STS (Bitfield-Mask: 0x01) */\r
-#define SMB2_STATUS_SAD_Pos (6UL) /*!< SMB2 STATUS: SAD (Bit 6) */\r
-#define SMB2_STATUS_SAD_Msk (0x40UL) /*!< SMB2 STATUS: SAD (Bitfield-Mask: 0x01) */\r
-#define SMB2_STATUS_PIN_Pos (7UL) /*!< SMB2 STATUS: PIN (Bit 7) */\r
-#define SMB2_STATUS_PIN_Msk (0x80UL) /*!< SMB2 STATUS: PIN (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- SMB2_CONTROL -------------------------------- */\r
-#define SMB2_CONTROL_ACK_Pos (0UL) /*!< SMB2 CONTROL: ACK (Bit 0) */\r
-#define SMB2_CONTROL_ACK_Msk (0x1UL) /*!< SMB2 CONTROL: ACK (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONTROL_STO_Pos (1UL) /*!< SMB2 CONTROL: STO (Bit 1) */\r
-#define SMB2_CONTROL_STO_Msk (0x2UL) /*!< SMB2 CONTROL: STO (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONTROL_STA_Pos (2UL) /*!< SMB2 CONTROL: STA (Bit 2) */\r
-#define SMB2_CONTROL_STA_Msk (0x4UL) /*!< SMB2 CONTROL: STA (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONTROL_ENI_Pos (3UL) /*!< SMB2 CONTROL: ENI (Bit 3) */\r
-#define SMB2_CONTROL_ENI_Msk (0x8UL) /*!< SMB2 CONTROL: ENI (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONTROL_ESO_Pos (6UL) /*!< SMB2 CONTROL: ESO (Bit 6) */\r
-#define SMB2_CONTROL_ESO_Msk (0x40UL) /*!< SMB2 CONTROL: ESO (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONTROL_PIN_Pos (7UL) /*!< SMB2 CONTROL: PIN (Bit 7) */\r
-#define SMB2_CONTROL_PIN_Msk (0x80UL) /*!< SMB2 CONTROL: PIN (Bitfield-Mask: 0x01) */\r
-\r
-/* ---------------------------------- SMB2_OWN ---------------------------------- */\r
-#define SMB2_OWN_ADDRESS_1_Pos (0UL) /*!< SMB2 OWN: ADDRESS_1 (Bit 0) */\r
-#define SMB2_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB2 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */\r
-#define SMB2_OWN_ADDRESS_2_Pos (8UL) /*!< SMB2 OWN: ADDRESS_2 (Bit 8) */\r
-#define SMB2_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB2 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */\r
-\r
-/* ----------------------------- SMB2_MASTER_COMMAND ---------------------------- */\r
-#define SMB2_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB2 MASTER_COMMAND: MRUN (Bit 0) */\r
-#define SMB2_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB2 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */\r
-#define SMB2_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB2 MASTER_COMMAND: MPROCEED (Bit 1) */\r
-#define SMB2_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB2 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */\r
-#define SMB2_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB2 MASTER_COMMAND: START0 (Bit 8) */\r
-#define SMB2_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB2 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */\r
-#define SMB2_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB2 MASTER_COMMAND: STARTN (Bit 9) */\r
-#define SMB2_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB2 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */\r
-#define SMB2_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB2 MASTER_COMMAND: STOP (Bit 10) */\r
-#define SMB2_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB2 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */\r
-#define SMB2_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB2 MASTER_COMMAND: PEC_TERM (Bit 11) */\r
-#define SMB2_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB2 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */\r
-#define SMB2_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB2 MASTER_COMMAND: READM (Bit 12) */\r
-#define SMB2_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB2 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */\r
-#define SMB2_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB2 MASTER_COMMAND: READ_PEC (Bit 13) */\r
-#define SMB2_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB2 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */\r
-#define SMB2_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB2 MASTER_COMMAND: WRITECOUNT (Bit 16) */\r
-#define SMB2_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB2 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */\r
-#define SMB2_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB2 MASTER_COMMAND: READCOUNT (Bit 24) */\r
-#define SMB2_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB2 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */\r
-\r
-/* ----------------------------- SMB2_SLAVE_COMMAND ----------------------------- */\r
-#define SMB2_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB2 SLAVE_COMMAND: SRUN (Bit 0) */\r
-#define SMB2_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB2 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */\r
-#define SMB2_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB2 SLAVE_COMMAND: SPROCEED (Bit 1) */\r
-#define SMB2_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB2 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */\r
-#define SMB2_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */\r
-#define SMB2_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */\r
-#define SMB2_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */\r
-#define SMB2_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */\r
-#define SMB2_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */\r
-#define SMB2_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */\r
-\r
-/* ------------------------------- SMB2_COMPLETION ------------------------------ */\r
-#define SMB2_COMPLETION_DTEN_Pos (2UL) /*!< SMB2 COMPLETION: DTEN (Bit 2) */\r
-#define SMB2_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB2 COMPLETION: DTEN (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_MCEN_Pos (3UL) /*!< SMB2 COMPLETION: MCEN (Bit 3) */\r
-#define SMB2_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB2 COMPLETION: MCEN (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_SCEN_Pos (4UL) /*!< SMB2 COMPLETION: SCEN (Bit 4) */\r
-#define SMB2_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB2 COMPLETION: SCEN (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_BIDEN_Pos (5UL) /*!< SMB2 COMPLETION: BIDEN (Bit 5) */\r
-#define SMB2_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB2 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_TIMERR_Pos (6UL) /*!< SMB2 COMPLETION: TIMERR (Bit 6) */\r
-#define SMB2_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB2 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_DTO_Pos (8UL) /*!< SMB2 COMPLETION: DTO (Bit 8) */\r
-#define SMB2_COMPLETION_DTO_Msk (0x100UL) /*!< SMB2 COMPLETION: DTO (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_MCTO_Pos (9UL) /*!< SMB2 COMPLETION: MCTO (Bit 9) */\r
-#define SMB2_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB2 COMPLETION: MCTO (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_SCTO_Pos (10UL) /*!< SMB2 COMPLETION: SCTO (Bit 10) */\r
-#define SMB2_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB2 COMPLETION: SCTO (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_CHDL_Pos (11UL) /*!< SMB2 COMPLETION: CHDL (Bit 11) */\r
-#define SMB2_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB2 COMPLETION: CHDL (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_CHDH_Pos (12UL) /*!< SMB2 COMPLETION: CHDH (Bit 12) */\r
-#define SMB2_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB2 COMPLETION: CHDH (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_BER_Pos (13UL) /*!< SMB2 COMPLETION: BER (Bit 13) */\r
-#define SMB2_COMPLETION_BER_Msk (0x2000UL) /*!< SMB2 COMPLETION: BER (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_LAB_Pos (14UL) /*!< SMB2 COMPLETION: LAB (Bit 14) */\r
-#define SMB2_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB2 COMPLETION: LAB (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_SNAKR_Pos (16UL) /*!< SMB2 COMPLETION: SNAKR (Bit 16) */\r
-#define SMB2_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB2 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_STR_Pos (17UL) /*!< SMB2 COMPLETION: STR (Bit 17) */\r
-#define SMB2_COMPLETION_STR_Msk (0x20000UL) /*!< SMB2 COMPLETION: STR (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_SPROT_Pos (19UL) /*!< SMB2 COMPLETION: SPROT (Bit 19) */\r
-#define SMB2_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB2 COMPLETION: SPROT (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB2 COMPLETION: REPEAT_READ (Bit 20) */\r
-#define SMB2_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB2 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB2 COMPLETION: REPEAT_WRITE (Bit 21) */\r
-#define SMB2_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB2 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_MNAKX_Pos (24UL) /*!< SMB2 COMPLETION: MNAKX (Bit 24) */\r
-#define SMB2_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB2 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_MTR_Pos (25UL) /*!< SMB2 COMPLETION: MTR (Bit 25) */\r
-#define SMB2_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB2 COMPLETION: MTR (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_IDLE_Pos (29UL) /*!< SMB2 COMPLETION: IDLE (Bit 29) */\r
-#define SMB2_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB2 COMPLETION: IDLE (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_MDONE_Pos (30UL) /*!< SMB2 COMPLETION: MDONE (Bit 30) */\r
-#define SMB2_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB2 COMPLETION: MDONE (Bitfield-Mask: 0x01) */\r
-#define SMB2_COMPLETION_SDONE_Pos (31UL) /*!< SMB2 COMPLETION: SDONE (Bit 31) */\r
-#define SMB2_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB2 COMPLETION: SDONE (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------ SMB2_IDLE_SCALING ----------------------------- */\r
-#define SMB2_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB2 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */\r
-#define SMB2_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB2 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */\r
-#define SMB2_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB2 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */\r
-#define SMB2_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB2 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */\r
-\r
-/* ----------------------------- SMB2_CONFIGURATION ----------------------------- */\r
-#define SMB2_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB2 CONFIGURATION: PORT_SEL (Bit 0) */\r
-#define SMB2_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB2 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */\r
-#define SMB2_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB2 CONFIGURATION: TCEN (Bit 4) */\r
-#define SMB2_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB2 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB2 CONFIGURATION: SLOW_CLOCK (Bit 5) */\r
-#define SMB2_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB2 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB2 CONFIGURATION: PECEN (Bit 7) */\r
-#define SMB2_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB2 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB2 CONFIGURATION: DFEN (Bit 8) */\r
-#define SMB2_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB2 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_RESET_Pos (9UL) /*!< SMB2 CONFIGURATION: RESET (Bit 9) */\r
-#define SMB2_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB2 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB2 CONFIGURATION: ENAB (Bit 10) */\r
-#define SMB2_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB2 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_DSA_Pos (11UL) /*!< SMB2 CONFIGURATION: DSA (Bit 11) */\r
-#define SMB2_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB2 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB2 CONFIGURATION: FAIR (Bit 12) */\r
-#define SMB2_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB2 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB2 CONFIGURATION: GC_DIS (Bit 14) */\r
-#define SMB2_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB2 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB2 CONFIGURATION: FLUSH_SXBUF (Bit 16) */\r
-#define SMB2_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB2 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB2 CONFIGURATION: FLUSH_SRBUF (Bit 17) */\r
-#define SMB2_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB2 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB2 CONFIGURATION: FLUSH_MXBUF (Bit 18) */\r
-#define SMB2_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB2 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB2 CONFIGURATION: FLUSH_MRBUF (Bit 19) */\r
-#define SMB2_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB2 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB2 CONFIGURATION: EN_AAS (Bit 28) */\r
-#define SMB2_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB2 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB2 CONFIGURATION: ENIDI (Bit 29) */\r
-#define SMB2_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB2 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB2 CONFIGURATION: ENMI (Bit 30) */\r
-#define SMB2_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB2 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */\r
-#define SMB2_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB2 CONFIGURATION: ENSI (Bit 31) */\r
-#define SMB2_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB2 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------- SMB2_BUS_CLOCK ------------------------------- */\r
-#define SMB2_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB2 BUS_CLOCK: LOW_PERIOD (Bit 0) */\r
-#define SMB2_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB2 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */\r
-#define SMB2_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB2 BUS_CLOCK: HIGH_PERIOD (Bit 8) */\r
-#define SMB2_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB2 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */\r
-\r
-/* ---------------------------- SMB2_BIT_BANG_CONTROL --------------------------- */\r
-#define SMB2_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB2 BIT_BANG_CONTROL: BBEN (Bit 0) */\r
-#define SMB2_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB2 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */\r
-#define SMB2_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB2 BIT_BANG_CONTROL: CLDIR (Bit 1) */\r
-#define SMB2_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB2 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */\r
-#define SMB2_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB2 BIT_BANG_CONTROL: DADIR (Bit 2) */\r
-#define SMB2_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB2 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */\r
-#define SMB2_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLK (Bit 3) */\r
-#define SMB2_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */\r
-#define SMB2_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB2 BIT_BANG_CONTROL: BBDAT (Bit 4) */\r
-#define SMB2_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB2 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */\r
-#define SMB2_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLKI (Bit 5) */\r
-#define SMB2_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */\r
-#define SMB2_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB2 BIT_BANG_CONTROL: BBDATI (Bit 6) */\r
-#define SMB2_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB2 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------ SMB2_DATA_TIMING ------------------------------ */\r
-#define SMB2_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB2 DATA_TIMING: DATA_HOLD (Bit 0) */\r
-#define SMB2_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB2 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */\r
-#define SMB2_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB2 DATA_TIMING: RESTART_SETUP (Bit 8) */\r
-#define SMB2_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB2 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */\r
-#define SMB2_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB2 DATA_TIMING: STOP_SETUP (Bit 16) */\r
-#define SMB2_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB2 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */\r
-#define SMB2_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB2 DATA_TIMING: START_HOLD (Bit 24) */\r
-#define SMB2_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB2 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */\r
-\r
-/* ---------------------------- SMB2_TIME_OUT_SCALING --------------------------- */\r
-#define SMB2_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB2 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */\r
-#define SMB2_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB2 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */\r
-#define SMB2_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB2 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */\r
-#define SMB2_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB2 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */\r
-#define SMB2_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB2 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */\r
-#define SMB2_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB2 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */\r
-#define SMB2_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB2 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */\r
-#define SMB2_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB2 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SMB3' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- SMB3_STATUS -------------------------------- */\r
-#define SMB3_STATUS_nBB_Pos (0UL) /*!< SMB3 STATUS: nBB (Bit 0) */\r
-#define SMB3_STATUS_nBB_Msk (0x1UL) /*!< SMB3 STATUS: nBB (Bitfield-Mask: 0x01) */\r
-#define SMB3_STATUS_LAB_Pos (1UL) /*!< SMB3 STATUS: LAB (Bit 1) */\r
-#define SMB3_STATUS_LAB_Msk (0x2UL) /*!< SMB3 STATUS: LAB (Bitfield-Mask: 0x01) */\r
-#define SMB3_STATUS_AAS_Pos (2UL) /*!< SMB3 STATUS: AAS (Bit 2) */\r
-#define SMB3_STATUS_AAS_Msk (0x4UL) /*!< SMB3 STATUS: AAS (Bitfield-Mask: 0x01) */\r
-#define SMB3_STATUS_LRB_AD0_Pos (3UL) /*!< SMB3 STATUS: LRB_AD0 (Bit 3) */\r
-#define SMB3_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB3 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */\r
-#define SMB3_STATUS_BER_Pos (4UL) /*!< SMB3 STATUS: BER (Bit 4) */\r
-#define SMB3_STATUS_BER_Msk (0x10UL) /*!< SMB3 STATUS: BER (Bitfield-Mask: 0x01) */\r
-#define SMB3_STATUS_STS_Pos (5UL) /*!< SMB3 STATUS: STS (Bit 5) */\r
-#define SMB3_STATUS_STS_Msk (0x20UL) /*!< SMB3 STATUS: STS (Bitfield-Mask: 0x01) */\r
-#define SMB3_STATUS_SAD_Pos (6UL) /*!< SMB3 STATUS: SAD (Bit 6) */\r
-#define SMB3_STATUS_SAD_Msk (0x40UL) /*!< SMB3 STATUS: SAD (Bitfield-Mask: 0x01) */\r
-#define SMB3_STATUS_PIN_Pos (7UL) /*!< SMB3 STATUS: PIN (Bit 7) */\r
-#define SMB3_STATUS_PIN_Msk (0x80UL) /*!< SMB3 STATUS: PIN (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- SMB3_CONTROL -------------------------------- */\r
-#define SMB3_CONTROL_ACK_Pos (0UL) /*!< SMB3 CONTROL: ACK (Bit 0) */\r
-#define SMB3_CONTROL_ACK_Msk (0x1UL) /*!< SMB3 CONTROL: ACK (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONTROL_STO_Pos (1UL) /*!< SMB3 CONTROL: STO (Bit 1) */\r
-#define SMB3_CONTROL_STO_Msk (0x2UL) /*!< SMB3 CONTROL: STO (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONTROL_STA_Pos (2UL) /*!< SMB3 CONTROL: STA (Bit 2) */\r
-#define SMB3_CONTROL_STA_Msk (0x4UL) /*!< SMB3 CONTROL: STA (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONTROL_ENI_Pos (3UL) /*!< SMB3 CONTROL: ENI (Bit 3) */\r
-#define SMB3_CONTROL_ENI_Msk (0x8UL) /*!< SMB3 CONTROL: ENI (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONTROL_ESO_Pos (6UL) /*!< SMB3 CONTROL: ESO (Bit 6) */\r
-#define SMB3_CONTROL_ESO_Msk (0x40UL) /*!< SMB3 CONTROL: ESO (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONTROL_PIN_Pos (7UL) /*!< SMB3 CONTROL: PIN (Bit 7) */\r
-#define SMB3_CONTROL_PIN_Msk (0x80UL) /*!< SMB3 CONTROL: PIN (Bitfield-Mask: 0x01) */\r
-\r
-/* ---------------------------------- SMB3_OWN ---------------------------------- */\r
-#define SMB3_OWN_ADDRESS_1_Pos (0UL) /*!< SMB3 OWN: ADDRESS_1 (Bit 0) */\r
-#define SMB3_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB3 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */\r
-#define SMB3_OWN_ADDRESS_2_Pos (8UL) /*!< SMB3 OWN: ADDRESS_2 (Bit 8) */\r
-#define SMB3_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB3 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */\r
-\r
-/* ----------------------------- SMB3_MASTER_COMMAND ---------------------------- */\r
-#define SMB3_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB3 MASTER_COMMAND: MRUN (Bit 0) */\r
-#define SMB3_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB3 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */\r
-#define SMB3_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB3 MASTER_COMMAND: MPROCEED (Bit 1) */\r
-#define SMB3_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB3 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */\r
-#define SMB3_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB3 MASTER_COMMAND: START0 (Bit 8) */\r
-#define SMB3_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB3 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */\r
-#define SMB3_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB3 MASTER_COMMAND: STARTN (Bit 9) */\r
-#define SMB3_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB3 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */\r
-#define SMB3_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB3 MASTER_COMMAND: STOP (Bit 10) */\r
-#define SMB3_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB3 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */\r
-#define SMB3_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB3 MASTER_COMMAND: PEC_TERM (Bit 11) */\r
-#define SMB3_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB3 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */\r
-#define SMB3_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB3 MASTER_COMMAND: READM (Bit 12) */\r
-#define SMB3_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB3 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */\r
-#define SMB3_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB3 MASTER_COMMAND: READ_PEC (Bit 13) */\r
-#define SMB3_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB3 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */\r
-#define SMB3_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB3 MASTER_COMMAND: WRITECOUNT (Bit 16) */\r
-#define SMB3_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB3 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */\r
-#define SMB3_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB3 MASTER_COMMAND: READCOUNT (Bit 24) */\r
-#define SMB3_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB3 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */\r
-\r
-/* ----------------------------- SMB3_SLAVE_COMMAND ----------------------------- */\r
-#define SMB3_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB3 SLAVE_COMMAND: SRUN (Bit 0) */\r
-#define SMB3_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB3 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */\r
-#define SMB3_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB3 SLAVE_COMMAND: SPROCEED (Bit 1) */\r
-#define SMB3_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB3 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */\r
-#define SMB3_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */\r
-#define SMB3_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */\r
-#define SMB3_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */\r
-#define SMB3_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */\r
-#define SMB3_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */\r
-#define SMB3_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */\r
-\r
-/* ------------------------------- SMB3_COMPLETION ------------------------------ */\r
-#define SMB3_COMPLETION_DTEN_Pos (2UL) /*!< SMB3 COMPLETION: DTEN (Bit 2) */\r
-#define SMB3_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB3 COMPLETION: DTEN (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_MCEN_Pos (3UL) /*!< SMB3 COMPLETION: MCEN (Bit 3) */\r
-#define SMB3_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB3 COMPLETION: MCEN (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_SCEN_Pos (4UL) /*!< SMB3 COMPLETION: SCEN (Bit 4) */\r
-#define SMB3_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB3 COMPLETION: SCEN (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_BIDEN_Pos (5UL) /*!< SMB3 COMPLETION: BIDEN (Bit 5) */\r
-#define SMB3_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB3 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_TIMERR_Pos (6UL) /*!< SMB3 COMPLETION: TIMERR (Bit 6) */\r
-#define SMB3_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB3 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_DTO_Pos (8UL) /*!< SMB3 COMPLETION: DTO (Bit 8) */\r
-#define SMB3_COMPLETION_DTO_Msk (0x100UL) /*!< SMB3 COMPLETION: DTO (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_MCTO_Pos (9UL) /*!< SMB3 COMPLETION: MCTO (Bit 9) */\r
-#define SMB3_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB3 COMPLETION: MCTO (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_SCTO_Pos (10UL) /*!< SMB3 COMPLETION: SCTO (Bit 10) */\r
-#define SMB3_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB3 COMPLETION: SCTO (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_CHDL_Pos (11UL) /*!< SMB3 COMPLETION: CHDL (Bit 11) */\r
-#define SMB3_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB3 COMPLETION: CHDL (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_CHDH_Pos (12UL) /*!< SMB3 COMPLETION: CHDH (Bit 12) */\r
-#define SMB3_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB3 COMPLETION: CHDH (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_BER_Pos (13UL) /*!< SMB3 COMPLETION: BER (Bit 13) */\r
-#define SMB3_COMPLETION_BER_Msk (0x2000UL) /*!< SMB3 COMPLETION: BER (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_LAB_Pos (14UL) /*!< SMB3 COMPLETION: LAB (Bit 14) */\r
-#define SMB3_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB3 COMPLETION: LAB (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_SNAKR_Pos (16UL) /*!< SMB3 COMPLETION: SNAKR (Bit 16) */\r
-#define SMB3_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB3 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_STR_Pos (17UL) /*!< SMB3 COMPLETION: STR (Bit 17) */\r
-#define SMB3_COMPLETION_STR_Msk (0x20000UL) /*!< SMB3 COMPLETION: STR (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_SPROT_Pos (19UL) /*!< SMB3 COMPLETION: SPROT (Bit 19) */\r
-#define SMB3_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB3 COMPLETION: SPROT (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB3 COMPLETION: REPEAT_READ (Bit 20) */\r
-#define SMB3_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB3 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB3 COMPLETION: REPEAT_WRITE (Bit 21) */\r
-#define SMB3_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB3 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_MNAKX_Pos (24UL) /*!< SMB3 COMPLETION: MNAKX (Bit 24) */\r
-#define SMB3_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB3 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_MTR_Pos (25UL) /*!< SMB3 COMPLETION: MTR (Bit 25) */\r
-#define SMB3_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB3 COMPLETION: MTR (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_IDLE_Pos (29UL) /*!< SMB3 COMPLETION: IDLE (Bit 29) */\r
-#define SMB3_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB3 COMPLETION: IDLE (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_MDONE_Pos (30UL) /*!< SMB3 COMPLETION: MDONE (Bit 30) */\r
-#define SMB3_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB3 COMPLETION: MDONE (Bitfield-Mask: 0x01) */\r
-#define SMB3_COMPLETION_SDONE_Pos (31UL) /*!< SMB3 COMPLETION: SDONE (Bit 31) */\r
-#define SMB3_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB3 COMPLETION: SDONE (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------ SMB3_IDLE_SCALING ----------------------------- */\r
-#define SMB3_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB3 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */\r
-#define SMB3_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB3 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */\r
-#define SMB3_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB3 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */\r
-#define SMB3_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB3 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */\r
-\r
-/* ----------------------------- SMB3_CONFIGURATION ----------------------------- */\r
-#define SMB3_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB3 CONFIGURATION: PORT_SEL (Bit 0) */\r
-#define SMB3_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB3 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */\r
-#define SMB3_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB3 CONFIGURATION: TCEN (Bit 4) */\r
-#define SMB3_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB3 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB3 CONFIGURATION: SLOW_CLOCK (Bit 5) */\r
-#define SMB3_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB3 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB3 CONFIGURATION: PECEN (Bit 7) */\r
-#define SMB3_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB3 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB3 CONFIGURATION: DFEN (Bit 8) */\r
-#define SMB3_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB3 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_RESET_Pos (9UL) /*!< SMB3 CONFIGURATION: RESET (Bit 9) */\r
-#define SMB3_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB3 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB3 CONFIGURATION: ENAB (Bit 10) */\r
-#define SMB3_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB3 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_DSA_Pos (11UL) /*!< SMB3 CONFIGURATION: DSA (Bit 11) */\r
-#define SMB3_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB3 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB3 CONFIGURATION: FAIR (Bit 12) */\r
-#define SMB3_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB3 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB3 CONFIGURATION: GC_DIS (Bit 14) */\r
-#define SMB3_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB3 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB3 CONFIGURATION: FLUSH_SXBUF (Bit 16) */\r
-#define SMB3_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB3 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB3 CONFIGURATION: FLUSH_SRBUF (Bit 17) */\r
-#define SMB3_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB3 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB3 CONFIGURATION: FLUSH_MXBUF (Bit 18) */\r
-#define SMB3_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB3 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB3 CONFIGURATION: FLUSH_MRBUF (Bit 19) */\r
-#define SMB3_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB3 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB3 CONFIGURATION: EN_AAS (Bit 28) */\r
-#define SMB3_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB3 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB3 CONFIGURATION: ENIDI (Bit 29) */\r
-#define SMB3_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB3 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB3 CONFIGURATION: ENMI (Bit 30) */\r
-#define SMB3_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB3 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */\r
-#define SMB3_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB3 CONFIGURATION: ENSI (Bit 31) */\r
-#define SMB3_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB3 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------- SMB3_BUS_CLOCK ------------------------------- */\r
-#define SMB3_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB3 BUS_CLOCK: LOW_PERIOD (Bit 0) */\r
-#define SMB3_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB3 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */\r
-#define SMB3_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB3 BUS_CLOCK: HIGH_PERIOD (Bit 8) */\r
-#define SMB3_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB3 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */\r
-\r
-/* ---------------------------- SMB3_BIT_BANG_CONTROL --------------------------- */\r
-#define SMB3_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB3 BIT_BANG_CONTROL: BBEN (Bit 0) */\r
-#define SMB3_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB3 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */\r
-#define SMB3_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB3 BIT_BANG_CONTROL: CLDIR (Bit 1) */\r
-#define SMB3_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB3 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */\r
-#define SMB3_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB3 BIT_BANG_CONTROL: DADIR (Bit 2) */\r
-#define SMB3_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB3 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */\r
-#define SMB3_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLK (Bit 3) */\r
-#define SMB3_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */\r
-#define SMB3_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB3 BIT_BANG_CONTROL: BBDAT (Bit 4) */\r
-#define SMB3_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB3 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */\r
-#define SMB3_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLKI (Bit 5) */\r
-#define SMB3_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */\r
-#define SMB3_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB3 BIT_BANG_CONTROL: BBDATI (Bit 6) */\r
-#define SMB3_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB3 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */\r
-\r
-/* ------------------------------ SMB3_DATA_TIMING ------------------------------ */\r
-#define SMB3_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB3 DATA_TIMING: DATA_HOLD (Bit 0) */\r
-#define SMB3_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB3 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */\r
-#define SMB3_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB3 DATA_TIMING: RESTART_SETUP (Bit 8) */\r
-#define SMB3_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB3 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */\r
-#define SMB3_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB3 DATA_TIMING: STOP_SETUP (Bit 16) */\r
-#define SMB3_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB3 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */\r
-#define SMB3_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB3 DATA_TIMING: START_HOLD (Bit 24) */\r
-#define SMB3_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB3 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */\r
-\r
-/* ---------------------------- SMB3_TIME_OUT_SCALING --------------------------- */\r
-#define SMB3_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB3 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */\r
-#define SMB3_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB3 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */\r
-#define SMB3_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB3 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */\r
-#define SMB3_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB3 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */\r
-#define SMB3_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB3 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */\r
-#define SMB3_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB3 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */\r
-#define SMB3_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB3 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */\r
-#define SMB3_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB3 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PECI' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PECI_CONTROL -------------------------------- */\r
-#define PECI_CONTROL_PD_Pos (0UL) /*!< PECI CONTROL: PD (Bit 0) */\r
-#define PECI_CONTROL_PD_Msk (0x1UL) /*!< PECI CONTROL: PD (Bitfield-Mask: 0x01) */\r
-#define PECI_CONTROL_RST_Pos (3UL) /*!< PECI CONTROL: RST (Bit 3) */\r
-#define PECI_CONTROL_RST_Msk (0x8UL) /*!< PECI CONTROL: RST (Bitfield-Mask: 0x01) */\r
-#define PECI_CONTROL_FRST_Pos (5UL) /*!< PECI CONTROL: FRST (Bit 5) */\r
-#define PECI_CONTROL_FRST_Msk (0x20UL) /*!< PECI CONTROL: FRST (Bitfield-Mask: 0x01) */\r
-#define PECI_CONTROL_TXEN_Pos (6UL) /*!< PECI CONTROL: TXEN (Bit 6) */\r
-#define PECI_CONTROL_TXEN_Msk (0x40UL) /*!< PECI CONTROL: TXEN (Bitfield-Mask: 0x01) */\r
-#define PECI_CONTROL_MIEN_Pos (7UL) /*!< PECI CONTROL: MIEN (Bit 7) */\r
-#define PECI_CONTROL_MIEN_Msk (0x80UL) /*!< PECI CONTROL: MIEN (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- PECI_STATUS1 -------------------------------- */\r
-#define PECI_STATUS1_BOF_Pos (0UL) /*!< PECI STATUS1: BOF (Bit 0) */\r
-#define PECI_STATUS1_BOF_Msk (0x1UL) /*!< PECI STATUS1: BOF (Bitfield-Mask: 0x01) */\r
-#define PECI_STATUS1_EOF_Pos (1UL) /*!< PECI STATUS1: EOF (Bit 1) */\r
-#define PECI_STATUS1_EOF_Msk (0x2UL) /*!< PECI STATUS1: EOF (Bitfield-Mask: 0x01) */\r
-#define PECI_STATUS1_ERR_Pos (2UL) /*!< PECI STATUS1: ERR (Bit 2) */\r
-#define PECI_STATUS1_ERR_Msk (0x4UL) /*!< PECI STATUS1: ERR (Bitfield-Mask: 0x01) */\r
-#define PECI_STATUS1_RDY_Pos (3UL) /*!< PECI STATUS1: RDY (Bit 3) */\r
-#define PECI_STATUS1_RDY_Msk (0x8UL) /*!< PECI STATUS1: RDY (Bitfield-Mask: 0x01) */\r
-#define PECI_STATUS1_RDYLO_Pos (4UL) /*!< PECI STATUS1: RDYLO (Bit 4) */\r
-#define PECI_STATUS1_RDYLO_Msk (0x10UL) /*!< PECI STATUS1: RDYLO (Bitfield-Mask: 0x01) */\r
-#define PECI_STATUS1_RDYHI_Pos (5UL) /*!< PECI STATUS1: RDYHI (Bit 5) */\r
-#define PECI_STATUS1_RDYHI_Msk (0x20UL) /*!< PECI STATUS1: RDYHI (Bitfield-Mask: 0x01) */\r
-#define PECI_STATUS1_MINT_Pos (7UL) /*!< PECI STATUS1: MINT (Bit 7) */\r
-#define PECI_STATUS1_MINT_Msk (0x80UL) /*!< PECI STATUS1: MINT (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- PECI_STATUS2 -------------------------------- */\r
-#define PECI_STATUS2_WFF_Pos (0UL) /*!< PECI STATUS2: WFF (Bit 0) */\r
-#define PECI_STATUS2_WFF_Msk (0x1UL) /*!< PECI STATUS2: WFF (Bitfield-Mask: 0x01) */\r
-#define PECI_STATUS2_WFE_Pos (1UL) /*!< PECI STATUS2: WFE (Bit 1) */\r
-#define PECI_STATUS2_WFE_Msk (0x2UL) /*!< PECI STATUS2: WFE (Bitfield-Mask: 0x01) */\r
-#define PECI_STATUS2_RFF_Pos (2UL) /*!< PECI STATUS2: RFF (Bit 2) */\r
-#define PECI_STATUS2_RFF_Msk (0x4UL) /*!< PECI STATUS2: RFF (Bitfield-Mask: 0x01) */\r
-#define PECI_STATUS2_RFE_Pos (3UL) /*!< PECI STATUS2: RFE (Bit 3) */\r
-#define PECI_STATUS2_RFE_Msk (0x8UL) /*!< PECI STATUS2: RFE (Bitfield-Mask: 0x01) */\r
-#define PECI_STATUS2_IDLE_Pos (7UL) /*!< PECI STATUS2: IDLE (Bit 7) */\r
-#define PECI_STATUS2_IDLE_Msk (0x80UL) /*!< PECI STATUS2: IDLE (Bitfield-Mask: 0x01) */\r
-\r
-/* --------------------------------- PECI_ERROR --------------------------------- */\r
-#define PECI_ERROR_FERR_Pos (0UL) /*!< PECI ERROR: FERR (Bit 0) */\r
-#define PECI_ERROR_FERR_Msk (0x1UL) /*!< PECI ERROR: FERR (Bitfield-Mask: 0x01) */\r
-#define PECI_ERROR_BERR_Pos (1UL) /*!< PECI ERROR: BERR (Bit 1) */\r
-#define PECI_ERROR_BERR_Msk (0x2UL) /*!< PECI ERROR: BERR (Bitfield-Mask: 0x01) */\r
-#define PECI_ERROR_REQERR_Pos (3UL) /*!< PECI ERROR: REQERR (Bit 3) */\r
-#define PECI_ERROR_REQERR_Msk (0x8UL) /*!< PECI ERROR: REQERR (Bitfield-Mask: 0x01) */\r
-#define PECI_ERROR_WROV_Pos (4UL) /*!< PECI ERROR: WROV (Bit 4) */\r
-#define PECI_ERROR_WROV_Msk (0x10UL) /*!< PECI ERROR: WROV (Bitfield-Mask: 0x01) */\r
-#define PECI_ERROR_WRUN_Pos (5UL) /*!< PECI ERROR: WRUN (Bit 5) */\r
-#define PECI_ERROR_WRUN_Msk (0x20UL) /*!< PECI ERROR: WRUN (Bitfield-Mask: 0x01) */\r
-#define PECI_ERROR_RDOV_Pos (6UL) /*!< PECI ERROR: RDOV (Bit 6) */\r
-#define PECI_ERROR_RDOV_Msk (0x40UL) /*!< PECI ERROR: RDOV (Bitfield-Mask: 0x01) */\r
-#define PECI_ERROR_CLKERR_Pos (7UL) /*!< PECI ERROR: CLKERR (Bit 7) */\r
-#define PECI_ERROR_CLKERR_Msk (0x80UL) /*!< PECI ERROR: CLKERR (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- PECI_INT_EN1 -------------------------------- */\r
-#define PECI_INT_EN1_BIEN_Pos (0UL) /*!< PECI INT_EN1: BIEN (Bit 0) */\r
-#define PECI_INT_EN1_BIEN_Msk (0x1UL) /*!< PECI INT_EN1: BIEN (Bitfield-Mask: 0x01) */\r
-#define PECI_INT_EN1_EIEN_Pos (1UL) /*!< PECI INT_EN1: EIEN (Bit 1) */\r
-#define PECI_INT_EN1_EIEN_Msk (0x2UL) /*!< PECI INT_EN1: EIEN (Bitfield-Mask: 0x01) */\r
-#define PECI_INT_EN1_EREN_Pos (2UL) /*!< PECI INT_EN1: EREN (Bit 2) */\r
-#define PECI_INT_EN1_EREN_Msk (0x4UL) /*!< PECI INT_EN1: EREN (Bitfield-Mask: 0x01) */\r
-#define PECI_INT_EN1_RLEN_Pos (4UL) /*!< PECI INT_EN1: RLEN (Bit 4) */\r
-#define PECI_INT_EN1_RLEN_Msk (0x10UL) /*!< PECI INT_EN1: RLEN (Bitfield-Mask: 0x01) */\r
-#define PECI_INT_EN1_RHEN_Pos (5UL) /*!< PECI INT_EN1: RHEN (Bit 5) */\r
-#define PECI_INT_EN1_RHEN_Msk (0x20UL) /*!< PECI INT_EN1: RHEN (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- PECI_INT_EN2 -------------------------------- */\r
-#define PECI_INT_EN2_ENWFE_Pos (1UL) /*!< PECI INT_EN2: ENWFE (Bit 1) */\r
-#define PECI_INT_EN2_ENWFE_Msk (0x2UL) /*!< PECI INT_EN2: ENWFE (Bitfield-Mask: 0x01) */\r
-#define PECI_INT_EN2_ENRFF_Pos (2UL) /*!< PECI INT_EN2: ENRFF (Bit 2) */\r
-#define PECI_INT_EN2_ENRFF_Msk (0x4UL) /*!< PECI INT_EN2: ENRFF (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'TACH_0' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ------------------------------- TACH_0_CONTROL ------------------------------- */\r
-#define TACH_0_CONTROL_OUT_LIMIT_ENABLE_Pos (0UL) /*!< TACH_0 CONTROL: OUT_LIMIT_ENABLE (Bit 0) */\r
-#define TACH_0_CONTROL_OUT_LIMIT_ENABLE_Msk (0x1UL) /*!< TACH_0 CONTROL: OUT_LIMIT_ENABLE (Bitfield-Mask: 0x01) */\r
-#define TACH_0_CONTROL_TACH_EN_Pos (1UL) /*!< TACH_0 CONTROL: TACH_EN (Bit 1) */\r
-#define TACH_0_CONTROL_TACH_EN_Msk (0x2UL) /*!< TACH_0 CONTROL: TACH_EN (Bitfield-Mask: 0x01) */\r
-#define TACH_0_CONTROL_FILTER_EN_Pos (8UL) /*!< TACH_0 CONTROL: FILTER_EN (Bit 8) */\r
-#define TACH_0_CONTROL_FILTER_EN_Msk (0x100UL) /*!< TACH_0 CONTROL: FILTER_EN (Bitfield-Mask: 0x01) */\r
-#define TACH_0_CONTROL_MODE_SELECT_Pos (10UL) /*!< TACH_0 CONTROL: MODE_SELECT (Bit 10) */\r
-#define TACH_0_CONTROL_MODE_SELECT_Msk (0x400UL) /*!< TACH_0 CONTROL: MODE_SELECT (Bitfield-Mask: 0x01) */\r
-#define TACH_0_CONTROL_EDGES_Pos (11UL) /*!< TACH_0 CONTROL: EDGES (Bit 11) */\r
-#define TACH_0_CONTROL_EDGES_Msk (0x1800UL) /*!< TACH_0 CONTROL: EDGES (Bitfield-Mask: 0x03) */\r
-#define TACH_0_CONTROL_READY_INT_EN_Pos (14UL) /*!< TACH_0 CONTROL: READY_INT_EN (Bit 14) */\r
-#define TACH_0_CONTROL_READY_INT_EN_Msk (0x4000UL) /*!< TACH_0 CONTROL: READY_INT_EN (Bitfield-Mask: 0x01) */\r
-#define TACH_0_CONTROL_INPUT_INT_EN_Pos (15UL) /*!< TACH_0 CONTROL: INPUT_INT_EN (Bit 15) */\r
-#define TACH_0_CONTROL_INPUT_INT_EN_Msk (0x8000UL) /*!< TACH_0 CONTROL: INPUT_INT_EN (Bitfield-Mask: 0x01) */\r
-#define TACH_0_CONTROL_COUNTER_Pos (16UL) /*!< TACH_0 CONTROL: COUNTER (Bit 16) */\r
-#define TACH_0_CONTROL_COUNTER_Msk (0xffff0000UL) /*!< TACH_0 CONTROL: COUNTER (Bitfield-Mask: 0xffff) */\r
-\r
-/* -------------------------------- TACH_0_STATUS ------------------------------- */\r
-#define TACH_0_STATUS_OUT_LIMIT_Pos (0UL) /*!< TACH_0 STATUS: OUT_LIMIT (Bit 0) */\r
-#define TACH_0_STATUS_OUT_LIMIT_Msk (0x1UL) /*!< TACH_0 STATUS: OUT_LIMIT (Bitfield-Mask: 0x01) */\r
-#define TACH_0_STATUS_PIN_Pos (1UL) /*!< TACH_0 STATUS: PIN (Bit 1) */\r
-#define TACH_0_STATUS_PIN_Msk (0x2UL) /*!< TACH_0 STATUS: PIN (Bitfield-Mask: 0x01) */\r
-#define TACH_0_STATUS_TOGGLE_Pos (2UL) /*!< TACH_0 STATUS: TOGGLE (Bit 2) */\r
-#define TACH_0_STATUS_TOGGLE_Msk (0x4UL) /*!< TACH_0 STATUS: TOGGLE (Bitfield-Mask: 0x01) */\r
-#define TACH_0_STATUS_COUNT_READY_Pos (3UL) /*!< TACH_0 STATUS: COUNT_READY (Bit 3) */\r
-#define TACH_0_STATUS_COUNT_READY_Msk (0x8UL) /*!< TACH_0 STATUS: COUNT_READY (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'TACH_1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ------------------------------- TACH_1_CONTROL ------------------------------- */\r
-#define TACH_1_CONTROL_OUT_LIMIT_ENABLE_Pos (0UL) /*!< TACH_1 CONTROL: OUT_LIMIT_ENABLE (Bit 0) */\r
-#define TACH_1_CONTROL_OUT_LIMIT_ENABLE_Msk (0x1UL) /*!< TACH_1 CONTROL: OUT_LIMIT_ENABLE (Bitfield-Mask: 0x01) */\r
-#define TACH_1_CONTROL_TACH_EN_Pos (1UL) /*!< TACH_1 CONTROL: TACH_EN (Bit 1) */\r
-#define TACH_1_CONTROL_TACH_EN_Msk (0x2UL) /*!< TACH_1 CONTROL: TACH_EN (Bitfield-Mask: 0x01) */\r
-#define TACH_1_CONTROL_FILTER_EN_Pos (8UL) /*!< TACH_1 CONTROL: FILTER_EN (Bit 8) */\r
-#define TACH_1_CONTROL_FILTER_EN_Msk (0x100UL) /*!< TACH_1 CONTROL: FILTER_EN (Bitfield-Mask: 0x01) */\r
-#define TACH_1_CONTROL_MODE_SELECT_Pos (10UL) /*!< TACH_1 CONTROL: MODE_SELECT (Bit 10) */\r
-#define TACH_1_CONTROL_MODE_SELECT_Msk (0x400UL) /*!< TACH_1 CONTROL: MODE_SELECT (Bitfield-Mask: 0x01) */\r
-#define TACH_1_CONTROL_EDGES_Pos (11UL) /*!< TACH_1 CONTROL: EDGES (Bit 11) */\r
-#define TACH_1_CONTROL_EDGES_Msk (0x1800UL) /*!< TACH_1 CONTROL: EDGES (Bitfield-Mask: 0x03) */\r
-#define TACH_1_CONTROL_READY_INT_EN_Pos (14UL) /*!< TACH_1 CONTROL: READY_INT_EN (Bit 14) */\r
-#define TACH_1_CONTROL_READY_INT_EN_Msk (0x4000UL) /*!< TACH_1 CONTROL: READY_INT_EN (Bitfield-Mask: 0x01) */\r
-#define TACH_1_CONTROL_INPUT_INT_EN_Pos (15UL) /*!< TACH_1 CONTROL: INPUT_INT_EN (Bit 15) */\r
-#define TACH_1_CONTROL_INPUT_INT_EN_Msk (0x8000UL) /*!< TACH_1 CONTROL: INPUT_INT_EN (Bitfield-Mask: 0x01) */\r
-#define TACH_1_CONTROL_COUNTER_Pos (16UL) /*!< TACH_1 CONTROL: COUNTER (Bit 16) */\r
-#define TACH_1_CONTROL_COUNTER_Msk (0xffff0000UL) /*!< TACH_1 CONTROL: COUNTER (Bitfield-Mask: 0xffff) */\r
-\r
-/* -------------------------------- TACH_1_STATUS ------------------------------- */\r
-#define TACH_1_STATUS_OUT_LIMIT_Pos (0UL) /*!< TACH_1 STATUS: OUT_LIMIT (Bit 0) */\r
-#define TACH_1_STATUS_OUT_LIMIT_Msk (0x1UL) /*!< TACH_1 STATUS: OUT_LIMIT (Bitfield-Mask: 0x01) */\r
-#define TACH_1_STATUS_PIN_Pos (1UL) /*!< TACH_1 STATUS: PIN (Bit 1) */\r
-#define TACH_1_STATUS_PIN_Msk (0x2UL) /*!< TACH_1 STATUS: PIN (Bitfield-Mask: 0x01) */\r
-#define TACH_1_STATUS_TOGGLE_Pos (2UL) /*!< TACH_1 STATUS: TOGGLE (Bit 2) */\r
-#define TACH_1_STATUS_TOGGLE_Msk (0x4UL) /*!< TACH_1 STATUS: TOGGLE (Bitfield-Mask: 0x01) */\r
-#define TACH_1_STATUS_COUNT_READY_Pos (3UL) /*!< TACH_1 STATUS: COUNT_READY (Bit 3) */\r
-#define TACH_1_STATUS_COUNT_READY_Msk (0x8UL) /*!< TACH_1 STATUS: COUNT_READY (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PWM_0' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PWM_0_CONFIG -------------------------------- */\r
-#define PWM_0_CONFIG_EN_Pos (0UL) /*!< PWM_0 CONFIG: EN (Bit 0) */\r
-#define PWM_0_CONFIG_EN_Msk (0x1UL) /*!< PWM_0 CONFIG: EN (Bitfield-Mask: 0x01) */\r
-#define PWM_0_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_0 CONFIG: CLK_SELECT (Bit 1) */\r
-#define PWM_0_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_0 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */\r
-#define PWM_0_CONFIG_INVERT_Pos (2UL) /*!< PWM_0 CONFIG: INVERT (Bit 2) */\r
-#define PWM_0_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_0 CONFIG: INVERT (Bitfield-Mask: 0x01) */\r
-#define PWM_0_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_0 CONFIG: CLK_PRE_DIVIDER (Bit 3) */\r
-#define PWM_0_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_0 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PWM_1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PWM_1_CONFIG -------------------------------- */\r
-#define PWM_1_CONFIG_EN_Pos (0UL) /*!< PWM_1 CONFIG: EN (Bit 0) */\r
-#define PWM_1_CONFIG_EN_Msk (0x1UL) /*!< PWM_1 CONFIG: EN (Bitfield-Mask: 0x01) */\r
-#define PWM_1_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_1 CONFIG: CLK_SELECT (Bit 1) */\r
-#define PWM_1_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_1 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */\r
-#define PWM_1_CONFIG_INVERT_Pos (2UL) /*!< PWM_1 CONFIG: INVERT (Bit 2) */\r
-#define PWM_1_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_1 CONFIG: INVERT (Bitfield-Mask: 0x01) */\r
-#define PWM_1_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_1 CONFIG: CLK_PRE_DIVIDER (Bit 3) */\r
-#define PWM_1_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_1 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PWM_2' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PWM_2_CONFIG -------------------------------- */\r
-#define PWM_2_CONFIG_EN_Pos (0UL) /*!< PWM_2 CONFIG: EN (Bit 0) */\r
-#define PWM_2_CONFIG_EN_Msk (0x1UL) /*!< PWM_2 CONFIG: EN (Bitfield-Mask: 0x01) */\r
-#define PWM_2_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_2 CONFIG: CLK_SELECT (Bit 1) */\r
-#define PWM_2_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_2 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */\r
-#define PWM_2_CONFIG_INVERT_Pos (2UL) /*!< PWM_2 CONFIG: INVERT (Bit 2) */\r
-#define PWM_2_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_2 CONFIG: INVERT (Bitfield-Mask: 0x01) */\r
-#define PWM_2_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_2 CONFIG: CLK_PRE_DIVIDER (Bit 3) */\r
-#define PWM_2_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_2 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PWM_3' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PWM_3_CONFIG -------------------------------- */\r
-#define PWM_3_CONFIG_EN_Pos (0UL) /*!< PWM_3 CONFIG: EN (Bit 0) */\r
-#define PWM_3_CONFIG_EN_Msk (0x1UL) /*!< PWM_3 CONFIG: EN (Bitfield-Mask: 0x01) */\r
-#define PWM_3_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_3 CONFIG: CLK_SELECT (Bit 1) */\r
-#define PWM_3_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_3 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */\r
-#define PWM_3_CONFIG_INVERT_Pos (2UL) /*!< PWM_3 CONFIG: INVERT (Bit 2) */\r
-#define PWM_3_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_3 CONFIG: INVERT (Bitfield-Mask: 0x01) */\r
-#define PWM_3_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_3 CONFIG: CLK_PRE_DIVIDER (Bit 3) */\r
-#define PWM_3_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_3 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'RPM_FAN' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------- RPM_FAN_CONFIGURATION --------------------------- */\r
-#define RPM_FAN_CONFIGURATION_UPDATE_Pos (0UL) /*!< RPM_FAN CONFIGURATION: UPDATE (Bit 0) */\r
-#define RPM_FAN_CONFIGURATION_UPDATE_Msk (0x7UL) /*!< RPM_FAN CONFIGURATION: UPDATE (Bitfield-Mask: 0x07) */\r
-#define RPM_FAN_CONFIGURATION_EDGES_Pos (3UL) /*!< RPM_FAN CONFIGURATION: EDGES (Bit 3) */\r
-#define RPM_FAN_CONFIGURATION_EDGES_Msk (0x18UL) /*!< RPM_FAN CONFIGURATION: EDGES (Bitfield-Mask: 0x03) */\r
-#define RPM_FAN_CONFIGURATION_RANGE_Pos (5UL) /*!< RPM_FAN CONFIGURATION: RANGE (Bit 5) */\r
-#define RPM_FAN_CONFIGURATION_RANGE_Msk (0x60UL) /*!< RPM_FAN CONFIGURATION: RANGE (Bitfield-Mask: 0x03) */\r
-#define RPM_FAN_CONFIGURATION_EN_ALGO_Pos (7UL) /*!< RPM_FAN CONFIGURATION: EN_ALGO (Bit 7) */\r
-#define RPM_FAN_CONFIGURATION_EN_ALGO_Msk (0x80UL) /*!< RPM_FAN CONFIGURATION: EN_ALGO (Bitfield-Mask: 0x01) */\r
-#define RPM_FAN_CONFIGURATION_POLARITY_Pos (8UL) /*!< RPM_FAN CONFIGURATION: POLARITY (Bit 8) */\r
-#define RPM_FAN_CONFIGURATION_POLARITY_Msk (0x100UL) /*!< RPM_FAN CONFIGURATION: POLARITY (Bitfield-Mask: 0x01) */\r
-#define RPM_FAN_CONFIGURATION_ERR_RNG_Pos (9UL) /*!< RPM_FAN CONFIGURATION: ERR_RNG (Bit 9) */\r
-#define RPM_FAN_CONFIGURATION_ERR_RNG_Msk (0x600UL) /*!< RPM_FAN CONFIGURATION: ERR_RNG (Bitfield-Mask: 0x03) */\r
-#define RPM_FAN_CONFIGURATION_DER_OPT_Pos (11UL) /*!< RPM_FAN CONFIGURATION: DER_OPT (Bit 11) */\r
-#define RPM_FAN_CONFIGURATION_DER_OPT_Msk (0x1800UL) /*!< RPM_FAN CONFIGURATION: DER_OPT (Bitfield-Mask: 0x03) */\r
-#define RPM_FAN_CONFIGURATION_DIS_GLITCH_Pos (13UL) /*!< RPM_FAN CONFIGURATION: DIS_GLITCH (Bit 13) */\r
-#define RPM_FAN_CONFIGURATION_DIS_GLITCH_Msk (0x2000UL) /*!< RPM_FAN CONFIGURATION: DIS_GLITCH (Bitfield-Mask: 0x01) */\r
-#define RPM_FAN_CONFIGURATION_EN_RRC_Pos (14UL) /*!< RPM_FAN CONFIGURATION: EN_RRC (Bit 14) */\r
-#define RPM_FAN_CONFIGURATION_EN_RRC_Msk (0x4000UL) /*!< RPM_FAN CONFIGURATION: EN_RRC (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- RPM_FAN_GAIN -------------------------------- */\r
-#define RPM_FAN_GAIN_GAINP_Pos (0UL) /*!< RPM_FAN GAIN: GAINP (Bit 0) */\r
-#define RPM_FAN_GAIN_GAINP_Msk (0x3UL) /*!< RPM_FAN GAIN: GAINP (Bitfield-Mask: 0x03) */\r
-#define RPM_FAN_GAIN_GAINI_Pos (2UL) /*!< RPM_FAN GAIN: GAINI (Bit 2) */\r
-#define RPM_FAN_GAIN_GAINI_Msk (0xcUL) /*!< RPM_FAN GAIN: GAINI (Bitfield-Mask: 0x03) */\r
-#define RPM_FAN_GAIN_GAIND_Pos (4UL) /*!< RPM_FAN GAIN: GAIND (Bit 4) */\r
-#define RPM_FAN_GAIN_GAIND_Msk (0x30UL) /*!< RPM_FAN GAIN: GAIND (Bitfield-Mask: 0x03) */\r
-\r
-/* ------------------------ RPM_FAN_SPIN_UP_CONFIGURATION ----------------------- */\r
-#define RPM_FAN_SPIN_UP_CONFIGURATION_SPINUP_TIME_Pos (0UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPINUP_TIME (Bit 0) */\r
-#define RPM_FAN_SPIN_UP_CONFIGURATION_SPINUP_TIME_Msk (0x3UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPINUP_TIME (Bitfield-Mask: 0x03) */\r
-#define RPM_FAN_SPIN_UP_CONFIGURATION_SPIN_LVL_Pos (2UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPIN_LVL (Bit 2) */\r
-#define RPM_FAN_SPIN_UP_CONFIGURATION_SPIN_LVL_Msk (0x1cUL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPIN_LVL (Bitfield-Mask: 0x07) */\r
-#define RPM_FAN_SPIN_UP_CONFIGURATION_NOKICK_Pos (5UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: NOKICK (Bit 5) */\r
-#define RPM_FAN_SPIN_UP_CONFIGURATION_NOKICK_Msk (0x20UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: NOKICK (Bitfield-Mask: 0x01) */\r
-#define RPM_FAN_SPIN_UP_CONFIGURATION_DRIVE_FAIL_CNT_Pos (6UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: DRIVE_FAIL_CNT (Bit 6) */\r
-#define RPM_FAN_SPIN_UP_CONFIGURATION_DRIVE_FAIL_CNT_Msk (0xc0UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: DRIVE_FAIL_CNT (Bitfield-Mask: 0x03) */\r
-\r
-/* ------------------------------- RPM_FAN_STATUS ------------------------------- */\r
-#define RPM_FAN_STATUS_FAN_STALL_Pos (0UL) /*!< RPM_FAN STATUS: FAN_STALL (Bit 0) */\r
-#define RPM_FAN_STATUS_FAN_STALL_Msk (0x1UL) /*!< RPM_FAN STATUS: FAN_STALL (Bitfield-Mask: 0x01) */\r
-#define RPM_FAN_STATUS_FAN_SPIN_Pos (1UL) /*!< RPM_FAN STATUS: FAN_SPIN (Bit 1) */\r
-#define RPM_FAN_STATUS_FAN_SPIN_Msk (0x2UL) /*!< RPM_FAN STATUS: FAN_SPIN (Bitfield-Mask: 0x01) */\r
-#define RPM_FAN_STATUS_DRIVE_FAIL_Pos (5UL) /*!< RPM_FAN STATUS: DRIVE_FAIL (Bit 5) */\r
-#define RPM_FAN_STATUS_DRIVE_FAIL_Msk (0x20UL) /*!< RPM_FAN STATUS: DRIVE_FAIL (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SPI_0' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- SPI_0_CONTROL ------------------------------- */\r
-#define SPI_0_CONTROL_LSBF_Pos (0UL) /*!< SPI_0 CONTROL: LSBF (Bit 0) */\r
-#define SPI_0_CONTROL_LSBF_Msk (0x1UL) /*!< SPI_0 CONTROL: LSBF (Bitfield-Mask: 0x01) */\r
-#define SPI_0_CONTROL_BIOEN_Pos (1UL) /*!< SPI_0 CONTROL: BIOEN (Bit 1) */\r
-#define SPI_0_CONTROL_BIOEN_Msk (0x2UL) /*!< SPI_0 CONTROL: BIOEN (Bitfield-Mask: 0x01) */\r
-#define SPI_0_CONTROL_SPDIN_SELECT_Pos (2UL) /*!< SPI_0 CONTROL: SPDIN_SELECT (Bit 2) */\r
-#define SPI_0_CONTROL_SPDIN_SELECT_Msk (0xcUL) /*!< SPI_0 CONTROL: SPDIN_SELECT (Bitfield-Mask: 0x03) */\r
-#define SPI_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< SPI_0 CONTROL: SOFT_RESET (Bit 4) */\r
-#define SPI_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< SPI_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
-#define SPI_0_CONTROL_AUTO_READ_Pos (5UL) /*!< SPI_0 CONTROL: AUTO_READ (Bit 5) */\r
-#define SPI_0_CONTROL_AUTO_READ_Msk (0x20UL) /*!< SPI_0 CONTROL: AUTO_READ (Bitfield-Mask: 0x01) */\r
-#define SPI_0_CONTROL_CE_Pos (6UL) /*!< SPI_0 CONTROL: CE (Bit 6) */\r
-#define SPI_0_CONTROL_CE_Msk (0x40UL) /*!< SPI_0 CONTROL: CE (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- SPI_0_STATUS -------------------------------- */\r
-#define SPI_0_STATUS_TXBE_Pos (0UL) /*!< SPI_0 STATUS: TXBE (Bit 0) */\r
-#define SPI_0_STATUS_TXBE_Msk (0x1UL) /*!< SPI_0 STATUS: TXBE (Bitfield-Mask: 0x01) */\r
-#define SPI_0_STATUS_RXBF_Pos (1UL) /*!< SPI_0 STATUS: RXBF (Bit 1) */\r
-#define SPI_0_STATUS_RXBF_Msk (0x2UL) /*!< SPI_0 STATUS: RXBF (Bitfield-Mask: 0x01) */\r
-#define SPI_0_STATUS_ACTIVE_Pos (2UL) /*!< SPI_0 STATUS: ACTIVE (Bit 2) */\r
-#define SPI_0_STATUS_ACTIVE_Msk (0x4UL) /*!< SPI_0 STATUS: ACTIVE (Bitfield-Mask: 0x01) */\r
-\r
-/* ----------------------------- SPI_0_CLOCK_Control ---------------------------- */\r
-#define SPI_0_CLOCK_Control_TCLKPH_Pos (0UL) /*!< SPI_0 CLOCK_Control: TCLKPH (Bit 0) */\r
-#define SPI_0_CLOCK_Control_TCLKPH_Msk (0x1UL) /*!< SPI_0 CLOCK_Control: TCLKPH (Bitfield-Mask: 0x01) */\r
-#define SPI_0_CLOCK_Control_RCLKPH_Pos (1UL) /*!< SPI_0 CLOCK_Control: RCLKPH (Bit 1) */\r
-#define SPI_0_CLOCK_Control_RCLKPH_Msk (0x2UL) /*!< SPI_0 CLOCK_Control: RCLKPH (Bitfield-Mask: 0x01) */\r
-#define SPI_0_CLOCK_Control_CLKPOL_Pos (2UL) /*!< SPI_0 CLOCK_Control: CLKPOL (Bit 2) */\r
-#define SPI_0_CLOCK_Control_CLKPOL_Msk (0x4UL) /*!< SPI_0 CLOCK_Control: CLKPOL (Bitfield-Mask: 0x01) */\r
-#define SPI_0_CLOCK_Control_CLKSRC_Pos (4UL) /*!< SPI_0 CLOCK_Control: CLKSRC (Bit 4) */\r
-#define SPI_0_CLOCK_Control_CLKSRC_Msk (0x10UL) /*!< SPI_0 CLOCK_Control: CLKSRC (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SPI_1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- SPI_1_CONTROL ------------------------------- */\r
-#define SPI_1_CONTROL_LSBF_Pos (0UL) /*!< SPI_1 CONTROL: LSBF (Bit 0) */\r
-#define SPI_1_CONTROL_LSBF_Msk (0x1UL) /*!< SPI_1 CONTROL: LSBF (Bitfield-Mask: 0x01) */\r
-#define SPI_1_CONTROL_BIOEN_Pos (1UL) /*!< SPI_1 CONTROL: BIOEN (Bit 1) */\r
-#define SPI_1_CONTROL_BIOEN_Msk (0x2UL) /*!< SPI_1 CONTROL: BIOEN (Bitfield-Mask: 0x01) */\r
-#define SPI_1_CONTROL_SPDIN_SELECT_Pos (2UL) /*!< SPI_1 CONTROL: SPDIN_SELECT (Bit 2) */\r
-#define SPI_1_CONTROL_SPDIN_SELECT_Msk (0xcUL) /*!< SPI_1 CONTROL: SPDIN_SELECT (Bitfield-Mask: 0x03) */\r
-#define SPI_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< SPI_1 CONTROL: SOFT_RESET (Bit 4) */\r
-#define SPI_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< SPI_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
-#define SPI_1_CONTROL_AUTO_READ_Pos (5UL) /*!< SPI_1 CONTROL: AUTO_READ (Bit 5) */\r
-#define SPI_1_CONTROL_AUTO_READ_Msk (0x20UL) /*!< SPI_1 CONTROL: AUTO_READ (Bitfield-Mask: 0x01) */\r
-#define SPI_1_CONTROL_CE_Pos (6UL) /*!< SPI_1 CONTROL: CE (Bit 6) */\r
-#define SPI_1_CONTROL_CE_Msk (0x40UL) /*!< SPI_1 CONTROL: CE (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- SPI_1_STATUS -------------------------------- */\r
-#define SPI_1_STATUS_TXBE_Pos (0UL) /*!< SPI_1 STATUS: TXBE (Bit 0) */\r
-#define SPI_1_STATUS_TXBE_Msk (0x1UL) /*!< SPI_1 STATUS: TXBE (Bitfield-Mask: 0x01) */\r
-#define SPI_1_STATUS_RXBF_Pos (1UL) /*!< SPI_1 STATUS: RXBF (Bit 1) */\r
-#define SPI_1_STATUS_RXBF_Msk (0x2UL) /*!< SPI_1 STATUS: RXBF (Bitfield-Mask: 0x01) */\r
-#define SPI_1_STATUS_ACTIVE_Pos (2UL) /*!< SPI_1 STATUS: ACTIVE (Bit 2) */\r
-#define SPI_1_STATUS_ACTIVE_Msk (0x4UL) /*!< SPI_1 STATUS: ACTIVE (Bitfield-Mask: 0x01) */\r
-\r
-/* ----------------------------- SPI_1_CLOCK_Control ---------------------------- */\r
-#define SPI_1_CLOCK_Control_TCLKPH_Pos (0UL) /*!< SPI_1 CLOCK_Control: TCLKPH (Bit 0) */\r
-#define SPI_1_CLOCK_Control_TCLKPH_Msk (0x1UL) /*!< SPI_1 CLOCK_Control: TCLKPH (Bitfield-Mask: 0x01) */\r
-#define SPI_1_CLOCK_Control_RCLKPH_Pos (1UL) /*!< SPI_1 CLOCK_Control: RCLKPH (Bit 1) */\r
-#define SPI_1_CLOCK_Control_RCLKPH_Msk (0x2UL) /*!< SPI_1 CLOCK_Control: RCLKPH (Bitfield-Mask: 0x01) */\r
-#define SPI_1_CLOCK_Control_CLKPOL_Pos (2UL) /*!< SPI_1 CLOCK_Control: CLKPOL (Bit 2) */\r
-#define SPI_1_CLOCK_Control_CLKPOL_Msk (0x4UL) /*!< SPI_1 CLOCK_Control: CLKPOL (Bitfield-Mask: 0x01) */\r
-#define SPI_1_CLOCK_Control_CLKSRC_Pos (4UL) /*!< SPI_1 CLOCK_Control: CLKSRC (Bit 4) */\r
-#define SPI_1_CLOCK_Control_CLKSRC_Msk (0x10UL) /*!< SPI_1 CLOCK_Control: CLKSRC (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'LED_0' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- LED_0_CONFIG -------------------------------- */\r
-#define LED_0_CONFIG_CONTROL_Pos (0UL) /*!< LED_0 CONFIG: CONTROL (Bit 0) */\r
-#define LED_0_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_0 CONFIG: CONTROL (Bitfield-Mask: 0x03) */\r
-#define LED_0_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_0 CONFIG: CLOCK_SOURCE (Bit 2) */\r
-#define LED_0_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_0 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */\r
-#define LED_0_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_0 CONFIG: SYNCHRONIZE (Bit 3) */\r
-#define LED_0_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_0 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */\r
-#define LED_0_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_0 CONFIG: PWM_SIZE (Bit 4) */\r
-#define LED_0_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_0 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */\r
-#define LED_0_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_0 CONFIG: ENABLE_UPDATE (Bit 6) */\r
-#define LED_0_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_0 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */\r
-#define LED_0_CONFIG_RESET_Pos (7UL) /*!< LED_0 CONFIG: RESET (Bit 7) */\r
-#define LED_0_CONFIG_RESET_Msk (0x80UL) /*!< LED_0 CONFIG: RESET (Bitfield-Mask: 0x01) */\r
-#define LED_0_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_0 CONFIG: WDT_RELOAD (Bit 8) */\r
-#define LED_0_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_0 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */\r
-#define LED_0_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_0 CONFIG: SYMMETRY (Bit 16) */\r
-#define LED_0_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_0 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- LED_0_LIMITS -------------------------------- */\r
-#define LED_0_LIMITS_MINIMUM_Pos (0UL) /*!< LED_0 LIMITS: MINIMUM (Bit 0) */\r
-#define LED_0_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_0 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */\r
-#define LED_0_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_0 LIMITS: MAXIMUM (Bit 8) */\r
-#define LED_0_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_0 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */\r
-\r
-/* --------------------------------- LED_0_DELAY -------------------------------- */\r
-#define LED_0_DELAY_LOW_Pos (0UL) /*!< LED_0 DELAY: LOW (Bit 0) */\r
-#define LED_0_DELAY_LOW_Msk (0xfffUL) /*!< LED_0 DELAY: LOW (Bitfield-Mask: 0xfff) */\r
-#define LED_0_DELAY_HIGH_Pos (12UL) /*!< LED_0 DELAY: HIGH (Bit 12) */\r
-#define LED_0_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_0 DELAY: HIGH (Bitfield-Mask: 0xfff) */\r
-\r
-/* ---------------------------- LED_0_UPDATE_STEPSIZE --------------------------- */\r
-#define LED_0_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_0 UPDATE_STEPSIZE: STEP0 (Bit 0) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_0 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_0 UPDATE_STEPSIZE: STEP1 (Bit 4) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_0 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_0 UPDATE_STEPSIZE: STEP2 (Bit 8) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_0 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_0 UPDATE_STEPSIZE: STEP3 (Bit 12) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_0 UPDATE_STEPSIZE: STEP4 (Bit 16) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_0 UPDATE_STEPSIZE: STEP5 (Bit 20) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_0 UPDATE_STEPSIZE: STEP6 (Bit 24) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_0 UPDATE_STEPSIZE: STEP7 (Bit 28) */\r
-#define LED_0_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */\r
-\r
-/* ---------------------------- LED_0_UPDATE_INTERVAL --------------------------- */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */\r
-#define LED_0_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'LED_1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- LED_1_CONFIG -------------------------------- */\r
-#define LED_1_CONFIG_CONTROL_Pos (0UL) /*!< LED_1 CONFIG: CONTROL (Bit 0) */\r
-#define LED_1_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_1 CONFIG: CONTROL (Bitfield-Mask: 0x03) */\r
-#define LED_1_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_1 CONFIG: CLOCK_SOURCE (Bit 2) */\r
-#define LED_1_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_1 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */\r
-#define LED_1_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_1 CONFIG: SYNCHRONIZE (Bit 3) */\r
-#define LED_1_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_1 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */\r
-#define LED_1_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_1 CONFIG: PWM_SIZE (Bit 4) */\r
-#define LED_1_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_1 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */\r
-#define LED_1_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_1 CONFIG: ENABLE_UPDATE (Bit 6) */\r
-#define LED_1_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_1 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */\r
-#define LED_1_CONFIG_RESET_Pos (7UL) /*!< LED_1 CONFIG: RESET (Bit 7) */\r
-#define LED_1_CONFIG_RESET_Msk (0x80UL) /*!< LED_1 CONFIG: RESET (Bitfield-Mask: 0x01) */\r
-#define LED_1_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_1 CONFIG: WDT_RELOAD (Bit 8) */\r
-#define LED_1_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_1 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */\r
-#define LED_1_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_1 CONFIG: SYMMETRY (Bit 16) */\r
-#define LED_1_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_1 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- LED_1_LIMITS -------------------------------- */\r
-#define LED_1_LIMITS_MINIMUM_Pos (0UL) /*!< LED_1 LIMITS: MINIMUM (Bit 0) */\r
-#define LED_1_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_1 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */\r
-#define LED_1_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_1 LIMITS: MAXIMUM (Bit 8) */\r
-#define LED_1_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_1 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */\r
-\r
-/* --------------------------------- LED_1_DELAY -------------------------------- */\r
-#define LED_1_DELAY_LOW_Pos (0UL) /*!< LED_1 DELAY: LOW (Bit 0) */\r
-#define LED_1_DELAY_LOW_Msk (0xfffUL) /*!< LED_1 DELAY: LOW (Bitfield-Mask: 0xfff) */\r
-#define LED_1_DELAY_HIGH_Pos (12UL) /*!< LED_1 DELAY: HIGH (Bit 12) */\r
-#define LED_1_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_1 DELAY: HIGH (Bitfield-Mask: 0xfff) */\r
-\r
-/* ---------------------------- LED_1_UPDATE_STEPSIZE --------------------------- */\r
-#define LED_1_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_1 UPDATE_STEPSIZE: STEP0 (Bit 0) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_1 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_1 UPDATE_STEPSIZE: STEP1 (Bit 4) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_1 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_1 UPDATE_STEPSIZE: STEP2 (Bit 8) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_1 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_1 UPDATE_STEPSIZE: STEP3 (Bit 12) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_1 UPDATE_STEPSIZE: STEP4 (Bit 16) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_1 UPDATE_STEPSIZE: STEP5 (Bit 20) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_1 UPDATE_STEPSIZE: STEP6 (Bit 24) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_1 UPDATE_STEPSIZE: STEP7 (Bit 28) */\r
-#define LED_1_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */\r
-\r
-/* ---------------------------- LED_1_UPDATE_INTERVAL --------------------------- */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */\r
-#define LED_1_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'LED_2' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- LED_2_CONFIG -------------------------------- */\r
-#define LED_2_CONFIG_CONTROL_Pos (0UL) /*!< LED_2 CONFIG: CONTROL (Bit 0) */\r
-#define LED_2_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_2 CONFIG: CONTROL (Bitfield-Mask: 0x03) */\r
-#define LED_2_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_2 CONFIG: CLOCK_SOURCE (Bit 2) */\r
-#define LED_2_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_2 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */\r
-#define LED_2_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_2 CONFIG: SYNCHRONIZE (Bit 3) */\r
-#define LED_2_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_2 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */\r
-#define LED_2_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_2 CONFIG: PWM_SIZE (Bit 4) */\r
-#define LED_2_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_2 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */\r
-#define LED_2_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_2 CONFIG: ENABLE_UPDATE (Bit 6) */\r
-#define LED_2_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_2 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */\r
-#define LED_2_CONFIG_RESET_Pos (7UL) /*!< LED_2 CONFIG: RESET (Bit 7) */\r
-#define LED_2_CONFIG_RESET_Msk (0x80UL) /*!< LED_2 CONFIG: RESET (Bitfield-Mask: 0x01) */\r
-#define LED_2_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_2 CONFIG: WDT_RELOAD (Bit 8) */\r
-#define LED_2_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_2 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */\r
-#define LED_2_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_2 CONFIG: SYMMETRY (Bit 16) */\r
-#define LED_2_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_2 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- LED_2_LIMITS -------------------------------- */\r
-#define LED_2_LIMITS_MINIMUM_Pos (0UL) /*!< LED_2 LIMITS: MINIMUM (Bit 0) */\r
-#define LED_2_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_2 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */\r
-#define LED_2_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_2 LIMITS: MAXIMUM (Bit 8) */\r
-#define LED_2_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_2 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */\r
-\r
-/* --------------------------------- LED_2_DELAY -------------------------------- */\r
-#define LED_2_DELAY_LOW_Pos (0UL) /*!< LED_2 DELAY: LOW (Bit 0) */\r
-#define LED_2_DELAY_LOW_Msk (0xfffUL) /*!< LED_2 DELAY: LOW (Bitfield-Mask: 0xfff) */\r
-#define LED_2_DELAY_HIGH_Pos (12UL) /*!< LED_2 DELAY: HIGH (Bit 12) */\r
-#define LED_2_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_2 DELAY: HIGH (Bitfield-Mask: 0xfff) */\r
-\r
-/* ---------------------------- LED_2_UPDATE_STEPSIZE --------------------------- */\r
-#define LED_2_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_2 UPDATE_STEPSIZE: STEP0 (Bit 0) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_2 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_2 UPDATE_STEPSIZE: STEP1 (Bit 4) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_2 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_2 UPDATE_STEPSIZE: STEP2 (Bit 8) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_2 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_2 UPDATE_STEPSIZE: STEP3 (Bit 12) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_2 UPDATE_STEPSIZE: STEP4 (Bit 16) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_2 UPDATE_STEPSIZE: STEP5 (Bit 20) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_2 UPDATE_STEPSIZE: STEP6 (Bit 24) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_2 UPDATE_STEPSIZE: STEP7 (Bit 28) */\r
-#define LED_2_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */\r
-\r
-/* ---------------------------- LED_2_UPDATE_INTERVAL --------------------------- */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */\r
-#define LED_2_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'LED_3' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- LED_3_CONFIG -------------------------------- */\r
-#define LED_3_CONFIG_CONTROL_Pos (0UL) /*!< LED_3 CONFIG: CONTROL (Bit 0) */\r
-#define LED_3_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_3 CONFIG: CONTROL (Bitfield-Mask: 0x03) */\r
-#define LED_3_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_3 CONFIG: CLOCK_SOURCE (Bit 2) */\r
-#define LED_3_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_3 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */\r
-#define LED_3_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_3 CONFIG: SYNCHRONIZE (Bit 3) */\r
-#define LED_3_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_3 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */\r
-#define LED_3_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_3 CONFIG: PWM_SIZE (Bit 4) */\r
-#define LED_3_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_3 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */\r
-#define LED_3_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_3 CONFIG: ENABLE_UPDATE (Bit 6) */\r
-#define LED_3_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_3 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */\r
-#define LED_3_CONFIG_RESET_Pos (7UL) /*!< LED_3 CONFIG: RESET (Bit 7) */\r
-#define LED_3_CONFIG_RESET_Msk (0x80UL) /*!< LED_3 CONFIG: RESET (Bitfield-Mask: 0x01) */\r
-#define LED_3_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_3 CONFIG: WDT_RELOAD (Bit 8) */\r
-#define LED_3_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_3 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */\r
-#define LED_3_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_3 CONFIG: SYMMETRY (Bit 16) */\r
-#define LED_3_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_3 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- LED_3_LIMITS -------------------------------- */\r
-#define LED_3_LIMITS_MINIMUM_Pos (0UL) /*!< LED_3 LIMITS: MINIMUM (Bit 0) */\r
-#define LED_3_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_3 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */\r
-#define LED_3_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_3 LIMITS: MAXIMUM (Bit 8) */\r
-#define LED_3_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_3 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */\r
-\r
-/* --------------------------------- LED_3_DELAY -------------------------------- */\r
-#define LED_3_DELAY_LOW_Pos (0UL) /*!< LED_3 DELAY: LOW (Bit 0) */\r
-#define LED_3_DELAY_LOW_Msk (0xfffUL) /*!< LED_3 DELAY: LOW (Bitfield-Mask: 0xfff) */\r
-#define LED_3_DELAY_HIGH_Pos (12UL) /*!< LED_3 DELAY: HIGH (Bit 12) */\r
-#define LED_3_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_3 DELAY: HIGH (Bitfield-Mask: 0xfff) */\r
-\r
-/* ---------------------------- LED_3_UPDATE_STEPSIZE --------------------------- */\r
-#define LED_3_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_3 UPDATE_STEPSIZE: STEP0 (Bit 0) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_3 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_3 UPDATE_STEPSIZE: STEP1 (Bit 4) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_3 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_3 UPDATE_STEPSIZE: STEP2 (Bit 8) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_3 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_3 UPDATE_STEPSIZE: STEP3 (Bit 12) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_3 UPDATE_STEPSIZE: STEP4 (Bit 16) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_3 UPDATE_STEPSIZE: STEP5 (Bit 20) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_3 UPDATE_STEPSIZE: STEP6 (Bit 24) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_3 UPDATE_STEPSIZE: STEP7 (Bit 28) */\r
-#define LED_3_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */\r
-\r
-/* ---------------------------- LED_3_UPDATE_INTERVAL --------------------------- */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */\r
-#define LED_3_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PS2_0' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PS2_0_CONTROL ------------------------------- */\r
-#define PS2_0_CONTROL_TR_Pos (0UL) /*!< PS2_0 CONTROL: TR (Bit 0) */\r
-#define PS2_0_CONTROL_TR_Msk (0x1UL) /*!< PS2_0 CONTROL: TR (Bitfield-Mask: 0x01) */\r
-#define PS2_0_CONTROL_EN_Pos (1UL) /*!< PS2_0 CONTROL: EN (Bit 1) */\r
-#define PS2_0_CONTROL_EN_Msk (0x2UL) /*!< PS2_0 CONTROL: EN (Bitfield-Mask: 0x01) */\r
-#define PS2_0_CONTROL_PARITY_Pos (2UL) /*!< PS2_0 CONTROL: PARITY (Bit 2) */\r
-#define PS2_0_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_0 CONTROL: PARITY (Bitfield-Mask: 0x03) */\r
-#define PS2_0_CONTROL_STOP_Pos (4UL) /*!< PS2_0 CONTROL: STOP (Bit 4) */\r
-#define PS2_0_CONTROL_STOP_Msk (0x30UL) /*!< PS2_0 CONTROL: STOP (Bitfield-Mask: 0x03) */\r
-\r
-/* -------------------------------- PS2_0_STATUS -------------------------------- */\r
-#define PS2_0_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_0 STATUS: RDATA_RDY (Bit 0) */\r
-#define PS2_0_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_0 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */\r
-#define PS2_0_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_0 STATUS: REC_TIMEOUT (Bit 1) */\r
-#define PS2_0_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_0 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */\r
-#define PS2_0_STATUS_PE_Pos (2UL) /*!< PS2_0 STATUS: PE (Bit 2) */\r
-#define PS2_0_STATUS_PE_Msk (0x4UL) /*!< PS2_0 STATUS: PE (Bitfield-Mask: 0x01) */\r
-#define PS2_0_STATUS_FE_Pos (3UL) /*!< PS2_0 STATUS: FE (Bit 3) */\r
-#define PS2_0_STATUS_FE_Msk (0x8UL) /*!< PS2_0 STATUS: FE (Bitfield-Mask: 0x01) */\r
-#define PS2_0_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_0 STATUS: XMIT_IDLE (Bit 4) */\r
-#define PS2_0_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_0 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */\r
-#define PS2_0_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_0 STATUS: XMIT_TIME_OUT (Bit 5) */\r
-#define PS2_0_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_0 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */\r
-#define PS2_0_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_0 STATUS: RX_BUSY (Bit 6) */\r
-#define PS2_0_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_0 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */\r
-#define PS2_0_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_0 STATUS: XMIT_START_TIMEOUT (Bit 7) */\r
-#define PS2_0_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_0 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PS2_1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PS2_1_CONTROL ------------------------------- */\r
-#define PS2_1_CONTROL_TR_Pos (0UL) /*!< PS2_1 CONTROL: TR (Bit 0) */\r
-#define PS2_1_CONTROL_TR_Msk (0x1UL) /*!< PS2_1 CONTROL: TR (Bitfield-Mask: 0x01) */\r
-#define PS2_1_CONTROL_EN_Pos (1UL) /*!< PS2_1 CONTROL: EN (Bit 1) */\r
-#define PS2_1_CONTROL_EN_Msk (0x2UL) /*!< PS2_1 CONTROL: EN (Bitfield-Mask: 0x01) */\r
-#define PS2_1_CONTROL_PARITY_Pos (2UL) /*!< PS2_1 CONTROL: PARITY (Bit 2) */\r
-#define PS2_1_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_1 CONTROL: PARITY (Bitfield-Mask: 0x03) */\r
-#define PS2_1_CONTROL_STOP_Pos (4UL) /*!< PS2_1 CONTROL: STOP (Bit 4) */\r
-#define PS2_1_CONTROL_STOP_Msk (0x30UL) /*!< PS2_1 CONTROL: STOP (Bitfield-Mask: 0x03) */\r
-\r
-/* -------------------------------- PS2_1_STATUS -------------------------------- */\r
-#define PS2_1_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_1 STATUS: RDATA_RDY (Bit 0) */\r
-#define PS2_1_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_1 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */\r
-#define PS2_1_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_1 STATUS: REC_TIMEOUT (Bit 1) */\r
-#define PS2_1_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_1 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */\r
-#define PS2_1_STATUS_PE_Pos (2UL) /*!< PS2_1 STATUS: PE (Bit 2) */\r
-#define PS2_1_STATUS_PE_Msk (0x4UL) /*!< PS2_1 STATUS: PE (Bitfield-Mask: 0x01) */\r
-#define PS2_1_STATUS_FE_Pos (3UL) /*!< PS2_1 STATUS: FE (Bit 3) */\r
-#define PS2_1_STATUS_FE_Msk (0x8UL) /*!< PS2_1 STATUS: FE (Bitfield-Mask: 0x01) */\r
-#define PS2_1_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_1 STATUS: XMIT_IDLE (Bit 4) */\r
-#define PS2_1_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_1 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */\r
-#define PS2_1_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_1 STATUS: XMIT_TIME_OUT (Bit 5) */\r
-#define PS2_1_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_1 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */\r
-#define PS2_1_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_1 STATUS: RX_BUSY (Bit 6) */\r
-#define PS2_1_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_1 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */\r
-#define PS2_1_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_1 STATUS: XMIT_START_TIMEOUT (Bit 7) */\r
-#define PS2_1_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_1 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PS2_2' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PS2_2_CONTROL ------------------------------- */\r
-#define PS2_2_CONTROL_TR_Pos (0UL) /*!< PS2_2 CONTROL: TR (Bit 0) */\r
-#define PS2_2_CONTROL_TR_Msk (0x1UL) /*!< PS2_2 CONTROL: TR (Bitfield-Mask: 0x01) */\r
-#define PS2_2_CONTROL_EN_Pos (1UL) /*!< PS2_2 CONTROL: EN (Bit 1) */\r
-#define PS2_2_CONTROL_EN_Msk (0x2UL) /*!< PS2_2 CONTROL: EN (Bitfield-Mask: 0x01) */\r
-#define PS2_2_CONTROL_PARITY_Pos (2UL) /*!< PS2_2 CONTROL: PARITY (Bit 2) */\r
-#define PS2_2_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_2 CONTROL: PARITY (Bitfield-Mask: 0x03) */\r
-#define PS2_2_CONTROL_STOP_Pos (4UL) /*!< PS2_2 CONTROL: STOP (Bit 4) */\r
-#define PS2_2_CONTROL_STOP_Msk (0x30UL) /*!< PS2_2 CONTROL: STOP (Bitfield-Mask: 0x03) */\r
-\r
-/* -------------------------------- PS2_2_STATUS -------------------------------- */\r
-#define PS2_2_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_2 STATUS: RDATA_RDY (Bit 0) */\r
-#define PS2_2_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_2 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */\r
-#define PS2_2_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_2 STATUS: REC_TIMEOUT (Bit 1) */\r
-#define PS2_2_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_2 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */\r
-#define PS2_2_STATUS_PE_Pos (2UL) /*!< PS2_2 STATUS: PE (Bit 2) */\r
-#define PS2_2_STATUS_PE_Msk (0x4UL) /*!< PS2_2 STATUS: PE (Bitfield-Mask: 0x01) */\r
-#define PS2_2_STATUS_FE_Pos (3UL) /*!< PS2_2 STATUS: FE (Bit 3) */\r
-#define PS2_2_STATUS_FE_Msk (0x8UL) /*!< PS2_2 STATUS: FE (Bitfield-Mask: 0x01) */\r
-#define PS2_2_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_2 STATUS: XMIT_IDLE (Bit 4) */\r
-#define PS2_2_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_2 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */\r
-#define PS2_2_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_2 STATUS: XMIT_TIME_OUT (Bit 5) */\r
-#define PS2_2_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_2 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */\r
-#define PS2_2_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_2 STATUS: RX_BUSY (Bit 6) */\r
-#define PS2_2_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_2 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */\r
-#define PS2_2_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_2 STATUS: XMIT_START_TIMEOUT (Bit 7) */\r
-#define PS2_2_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_2 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PS2_3' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PS2_3_CONTROL ------------------------------- */\r
-#define PS2_3_CONTROL_TR_Pos (0UL) /*!< PS2_3 CONTROL: TR (Bit 0) */\r
-#define PS2_3_CONTROL_TR_Msk (0x1UL) /*!< PS2_3 CONTROL: TR (Bitfield-Mask: 0x01) */\r
-#define PS2_3_CONTROL_EN_Pos (1UL) /*!< PS2_3 CONTROL: EN (Bit 1) */\r
-#define PS2_3_CONTROL_EN_Msk (0x2UL) /*!< PS2_3 CONTROL: EN (Bitfield-Mask: 0x01) */\r
-#define PS2_3_CONTROL_PARITY_Pos (2UL) /*!< PS2_3 CONTROL: PARITY (Bit 2) */\r
-#define PS2_3_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_3 CONTROL: PARITY (Bitfield-Mask: 0x03) */\r
-#define PS2_3_CONTROL_STOP_Pos (4UL) /*!< PS2_3 CONTROL: STOP (Bit 4) */\r
-#define PS2_3_CONTROL_STOP_Msk (0x30UL) /*!< PS2_3 CONTROL: STOP (Bitfield-Mask: 0x03) */\r
-\r
-/* -------------------------------- PS2_3_STATUS -------------------------------- */\r
-#define PS2_3_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_3 STATUS: RDATA_RDY (Bit 0) */\r
-#define PS2_3_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_3 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */\r
-#define PS2_3_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_3 STATUS: REC_TIMEOUT (Bit 1) */\r
-#define PS2_3_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_3 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */\r
-#define PS2_3_STATUS_PE_Pos (2UL) /*!< PS2_3 STATUS: PE (Bit 2) */\r
-#define PS2_3_STATUS_PE_Msk (0x4UL) /*!< PS2_3 STATUS: PE (Bitfield-Mask: 0x01) */\r
-#define PS2_3_STATUS_FE_Pos (3UL) /*!< PS2_3 STATUS: FE (Bit 3) */\r
-#define PS2_3_STATUS_FE_Msk (0x8UL) /*!< PS2_3 STATUS: FE (Bitfield-Mask: 0x01) */\r
-#define PS2_3_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_3 STATUS: XMIT_IDLE (Bit 4) */\r
-#define PS2_3_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_3 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */\r
-#define PS2_3_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_3 STATUS: XMIT_TIME_OUT (Bit 5) */\r
-#define PS2_3_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_3 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */\r
-#define PS2_3_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_3 STATUS: RX_BUSY (Bit 6) */\r
-#define PS2_3_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_3 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */\r
-#define PS2_3_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_3 STATUS: XMIT_START_TIMEOUT (Bit 7) */\r
-#define PS2_3_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_3 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'KEYSCAN' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ------------------------------- KEYSCAN_CONTROL ------------------------------ */\r
-#define KEYSCAN_CONTROL_SELECT_Pos (0UL) /*!< KEYSCAN CONTROL: SELECT (Bit 0) */\r
-#define KEYSCAN_CONTROL_SELECT_Msk (0x1fUL) /*!< KEYSCAN CONTROL: SELECT (Bitfield-Mask: 0x1f) */\r
-#define KEYSCAN_CONTROL_ALL_Pos (5UL) /*!< KEYSCAN CONTROL: ALL (Bit 5) */\r
-#define KEYSCAN_CONTROL_ALL_Msk (0x20UL) /*!< KEYSCAN CONTROL: ALL (Bitfield-Mask: 0x01) */\r
-#define KEYSCAN_CONTROL_KSEN_Pos (6UL) /*!< KEYSCAN CONTROL: KSEN (Bit 6) */\r
-#define KEYSCAN_CONTROL_KSEN_Msk (0x40UL) /*!< KEYSCAN CONTROL: KSEN (Bitfield-Mask: 0x01) */\r
-#define KEYSCAN_CONTROL_INVERT_Pos (7UL) /*!< KEYSCAN CONTROL: INVERT (Bit 7) */\r
-#define KEYSCAN_CONTROL_INVERT_Msk (0x80UL) /*!< KEYSCAN CONTROL: INVERT (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'BC_LINK' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ------------------------------- BC_LINK_STATUS ------------------------------- */\r
-#define BC_LINK_STATUS_BUSY_Pos (0UL) /*!< BC_LINK STATUS: BUSY (Bit 0) */\r
-#define BC_LINK_STATUS_BUSY_Msk (0x1UL) /*!< BC_LINK STATUS: BUSY (Bitfield-Mask: 0x01) */\r
-#define BC_LINK_STATUS_BUSY_CLR_INT_EN_Pos (4UL) /*!< BC_LINK STATUS: BUSY_CLR_INT_EN (Bit 4) */\r
-#define BC_LINK_STATUS_BUSY_CLR_INT_EN_Msk (0x10UL) /*!< BC_LINK STATUS: BUSY_CLR_INT_EN (Bitfield-Mask: 0x01) */\r
-#define BC_LINK_STATUS_ERR_INT_EN_Pos (5UL) /*!< BC_LINK STATUS: ERR_INT_EN (Bit 5) */\r
-#define BC_LINK_STATUS_ERR_INT_EN_Msk (0x20UL) /*!< BC_LINK STATUS: ERR_INT_EN (Bitfield-Mask: 0x01) */\r
-#define BC_LINK_STATUS_ERROR_Pos (6UL) /*!< BC_LINK STATUS: ERROR (Bit 6) */\r
-#define BC_LINK_STATUS_ERROR_Msk (0x40UL) /*!< BC_LINK STATUS: ERROR (Bitfield-Mask: 0x01) */\r
-#define BC_LINK_STATUS_RESET_Pos (7UL) /*!< BC_LINK STATUS: RESET (Bit 7) */\r
-#define BC_LINK_STATUS_RESET_Msk (0x80UL) /*!< BC_LINK STATUS: RESET (Bitfield-Mask: 0x01) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'TFDP' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- TFDP_CONTROL -------------------------------- */\r
-#define TFDP_CONTROL_EN_Pos (0UL) /*!< TFDP CONTROL: EN (Bit 0) */\r
-#define TFDP_CONTROL_EN_Msk (0x1UL) /*!< TFDP CONTROL: EN (Bitfield-Mask: 0x01) */\r
-#define TFDP_CONTROL_EDGE_SEL_Pos (1UL) /*!< TFDP CONTROL: EDGE_SEL (Bit 1) */\r
-#define TFDP_CONTROL_EDGE_SEL_Msk (0x2UL) /*!< TFDP CONTROL: EDGE_SEL (Bitfield-Mask: 0x01) */\r
-#define TFDP_CONTROL_DIVSEL_Pos (2UL) /*!< TFDP CONTROL: DIVSEL (Bit 2) */\r
-#define TFDP_CONTROL_DIVSEL_Msk (0xcUL) /*!< TFDP CONTROL: DIVSEL (Bitfield-Mask: 0x03) */\r
-#define TFDP_CONTROL_IP_DELAY_Pos (4UL) /*!< TFDP CONTROL: IP_DELAY (Bit 4) */\r
-#define TFDP_CONTROL_IP_DELAY_Msk (0x70UL) /*!< TFDP CONTROL: IP_DELAY (Bitfield-Mask: 0x07) */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'ADC' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- ADC_CONTROL -------------------------------- */\r
-#define ADC_CONTROL_ACTIVATE_Pos (0UL) /*!< ADC CONTROL: ACTIVATE (Bit 0) */\r
-#define ADC_CONTROL_ACTIVATE_Msk (0x1UL) /*!< ADC CONTROL: ACTIVATE (Bitfield-Mask: 0x01) */\r
-#define ADC_CONTROL_START_SINGLE_Pos (1UL) /*!< ADC CONTROL: START_SINGLE (Bit 1) */\r
-#define ADC_CONTROL_START_SINGLE_Msk (0x2UL) /*!< ADC CONTROL: START_SINGLE (Bitfield-Mask: 0x01) */\r
-#define ADC_CONTROL_START_REPEAT_Pos (2UL) /*!< ADC CONTROL: START_REPEAT (Bit 2) */\r
-#define ADC_CONTROL_START_REPEAT_Msk (0x4UL) /*!< ADC CONTROL: START_REPEAT (Bitfield-Mask: 0x01) */\r
-#define ADC_CONTROL_POWER_SAVER_DIS_Pos (3UL) /*!< ADC CONTROL: POWER_SAVER_DIS (Bit 3) */\r
-#define ADC_CONTROL_POWER_SAVER_DIS_Msk (0x8UL) /*!< ADC CONTROL: POWER_SAVER_DIS (Bitfield-Mask: 0x01) */\r
-#define ADC_CONTROL_SOFT_RESET_Pos (4UL) /*!< ADC CONTROL: SOFT_RESET (Bit 4) */\r
-#define ADC_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< ADC CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
-#define ADC_CONTROL_REPEAT_DONE_STAT_Pos (6UL) /*!< ADC CONTROL: REPEAT_DONE_STAT (Bit 6) */\r
-#define ADC_CONTROL_REPEAT_DONE_STAT_Msk (0x40UL) /*!< ADC CONTROL: REPEAT_DONE_STAT (Bitfield-Mask: 0x01) */\r
-#define ADC_CONTROL_SINGLE_DONE_STAT_Pos (7UL) /*!< ADC CONTROL: SINGLE_DONE_STAT (Bit 7) */\r
-#define ADC_CONTROL_SINGLE_DONE_STAT_Msk (0x80UL) /*!< ADC CONTROL: SINGLE_DONE_STAT (Bitfield-Mask: 0x01) */\r
-\r
-/* ---------------------------------- ADC_DELAY --------------------------------- */\r
-#define ADC_DELAY_START_Pos (0UL) /*!< ADC DELAY: START (Bit 0) */\r
-#define ADC_DELAY_START_Msk (0xffffUL) /*!< ADC DELAY: START (Bitfield-Mask: 0xffff) */\r
-#define ADC_DELAY_REPEAT_Pos (16UL) /*!< ADC DELAY: REPEAT (Bit 16) */\r
-#define ADC_DELAY_REPEAT_Msk (0xffff0000UL) /*!< ADC DELAY: REPEAT (Bitfield-Mask: 0xffff) */\r
-\r
-/* --------------------------------- ADC_STATUS --------------------------------- */\r
-#define ADC_STATUS_CH0_Pos (0UL) /*!< ADC STATUS: CH0 (Bit 0) */\r
-#define ADC_STATUS_CH0_Msk (0x1UL) /*!< ADC STATUS: CH0 (Bitfield-Mask: 0x01) */\r
-#define ADC_STATUS_CH1_Pos (1UL) /*!< ADC STATUS: CH1 (Bit 1) */\r
-#define ADC_STATUS_CH1_Msk (0x2UL) /*!< ADC STATUS: CH1 (Bitfield-Mask: 0x01) */\r
-#define ADC_STATUS_CH2_Pos (2UL) /*!< ADC STATUS: CH2 (Bit 2) */\r
-#define ADC_STATUS_CH2_Msk (0x4UL) /*!< ADC STATUS: CH2 (Bitfield-Mask: 0x01) */\r
-#define ADC_STATUS_CH3_Pos (3UL) /*!< ADC STATUS: CH3 (Bit 3) */\r
-#define ADC_STATUS_CH3_Msk (0x8UL) /*!< ADC STATUS: CH3 (Bitfield-Mask: 0x01) */\r
-#define ADC_STATUS_CH4_Pos (4UL) /*!< ADC STATUS: CH4 (Bit 4) */\r
-#define ADC_STATUS_CH4_Msk (0x10UL) /*!< ADC STATUS: CH4 (Bitfield-Mask: 0x01) */\r
-\r
-/* -------------------------------- ADC_SINGLE_EN ------------------------------- */\r
-#define ADC_SINGLE_EN_CH0_Pos (0UL) /*!< ADC SINGLE_EN: CH0 (Bit 0) */\r
-#define ADC_SINGLE_EN_CH0_Msk (0x1UL) /*!< ADC SINGLE_EN: CH0 (Bitfield-Mask: 0x01) */\r
-#define ADC_SINGLE_EN_CH1_Pos (1UL) /*!< ADC SINGLE_EN: CH1 (Bit 1) */\r
-#define ADC_SINGLE_EN_CH1_Msk (0x2UL) /*!< ADC SINGLE_EN: CH1 (Bitfield-Mask: 0x01) */\r
-#define ADC_SINGLE_EN_CH2_Pos (2UL) /*!< ADC SINGLE_EN: CH2 (Bit 2) */\r
-#define ADC_SINGLE_EN_CH2_Msk (0x4UL) /*!< ADC SINGLE_EN: CH2 (Bitfield-Mask: 0x01) */\r
-#define ADC_SINGLE_EN_CH3_Pos (3UL) /*!< ADC SINGLE_EN: CH3 (Bit 3) */\r
-#define ADC_SINGLE_EN_CH3_Msk (0x8UL) /*!< ADC SINGLE_EN: CH3 (Bitfield-Mask: 0x01) */\r
-#define ADC_SINGLE_EN_CH4_Pos (4UL) /*!< ADC SINGLE_EN: CH4 (Bit 4) */\r
-#define ADC_SINGLE_EN_CH4_Msk (0x10UL) /*!< ADC SINGLE_EN: CH4 (Bitfield-Mask: 0x01) */\r
-\r
-/* --------------------------------- ADC_REPEAT --------------------------------- */\r
-#define ADC_REPEAT_CH0_Pos (0UL) /*!< ADC REPEAT: CH0 (Bit 0) */\r
-#define ADC_REPEAT_CH0_Msk (0x1UL) /*!< ADC REPEAT: CH0 (Bitfield-Mask: 0x01) */\r
-#define ADC_REPEAT_CH1_Pos (1UL) /*!< ADC REPEAT: CH1 (Bit 1) */\r
-#define ADC_REPEAT_CH1_Msk (0x2UL) /*!< ADC REPEAT: CH1 (Bitfield-Mask: 0x01) */\r
-#define ADC_REPEAT_CH2_Pos (2UL) /*!< ADC REPEAT: CH2 (Bit 2) */\r
-#define ADC_REPEAT_CH2_Msk (0x4UL) /*!< ADC REPEAT: CH2 (Bitfield-Mask: 0x01) */\r
-#define ADC_REPEAT_CH3_Pos (3UL) /*!< ADC REPEAT: CH3 (Bit 3) */\r
-#define ADC_REPEAT_CH3_Msk (0x8UL) /*!< ADC REPEAT: CH3 (Bitfield-Mask: 0x01) */\r
-#define ADC_REPEAT_CH4_Pos (4UL) /*!< ADC REPEAT: CH4 (Bit 4) */\r
-#define ADC_REPEAT_CH4_Msk (0x10UL) /*!< ADC REPEAT: CH4 (Bitfield-Mask: 0x01) */\r
-\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Peripheral memory map ================ */\r
-/* ================================================================================ */\r
-\r
-#define PCR_BASE 0x40080100UL\r
-#define VBAT_BASE 0x4000A400UL\r
-#define LPC_BASE 0x400F3000UL\r
-#define LPC_CONFIG_BASE 0x400F3300UL\r
-#define GCR_BASE 0x400FFF00UL\r
-#define EMI_BASE 0x400F0000UL\r
-#define ACPI_EC0_BASE 0x400F0C00UL\r
-#define ACPI_EC1_BASE 0x400F1000UL\r
-#define KBC_BASE 0x400F0400UL\r
-#define PORT92_BASE 0x400F1800UL\r
-#define MBX_BASE 0x400F2400UL\r
-#define PM1_BASE 0x400F1400UL\r
-#define UART_BASE 0x400F1C00UL\r
-#define INTR_BASE 0x4000C000UL\r
-#define WDT_BASE 0x40000400UL\r
-#define TIMER_16_0_BASE 0x40000C00UL\r
-#define TIMER_16_1_BASE 0x40000C20UL\r
-#define TIMER_16_2_BASE 0x40000C40UL\r
-#define TIMER_16_3_BASE 0x40000C60UL\r
-#define TIMER_32_0_BASE 0x40000C80UL\r
-#define TIMER_32_1_BASE 0x40000CA0UL\r
-#define HTM_BASE 0x40009800UL\r
-#define RTC_BASE 0x400F2C00UL\r
-#define GPIO_BASE 0x40081000UL\r
-#define DMA_BASE 0x40002400UL\r
-#define SMB0_BASE 0x40001800UL\r
-#define SMB1_BASE 0x4000AC00UL\r
-#define SMB2_BASE 0x4000B000UL\r
-#define SMB3_BASE 0x4000B400UL\r
-#define PECI_BASE 0x40006400UL\r
-#define TACH_0_BASE 0x40006000UL\r
-#define TACH_1_BASE 0x40006100UL\r
-#define PWM_0_BASE 0x40005800UL\r
-#define PWM_1_BASE 0x40005810UL\r
-#define PWM_2_BASE 0x40005820UL\r
-#define PWM_3_BASE 0x40005830UL\r
-#define RPM_FAN_BASE 0x4000A000UL\r
-#define SPI_0_BASE 0x40009400UL\r
-#define SPI_1_BASE 0x40009480UL\r
-#define LED_0_BASE 0x4000B800UL\r
-#define LED_1_BASE 0x4000B900UL\r
-#define LED_2_BASE 0x4000BA00UL\r
-#define LED_3_BASE 0x4000BB00UL\r
-#define PS2_0_BASE 0x40009000UL\r
-#define PS2_1_BASE 0x40009040UL\r
-#define PS2_2_BASE 0x40009080UL\r
-#define PS2_3_BASE 0x400090C0UL\r
-#define KEYSCAN_BASE 0x40009C00UL\r
-#define BC_LINK_BASE 0x4000BC00UL\r
-#define TFDP_BASE 0x40008C00UL\r
-#define ADC_BASE 0x40007C00UL\r
-#define EC_REG_BANK_BASE 0x4000FC00UL\r
-#define JTAG_BASE 0x40080000UL\r
-#define PKE_BASE 0x4000BD00UL\r
-#define TRNG_BASE 0x4000BE00UL\r
-#define HASH_BASE 0x4000D000UL\r
-#define AES_BASE 0x4000D200UL\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Peripheral declaration ================ */\r
-/* ================================================================================ */\r
-\r
-#define CEC1302_PCR ((PCR_Type *) PCR_BASE)\r
-#define CEC1302_VBAT ((VBAT_Type *) VBAT_BASE)\r
-#define CEC1302_LPC ((LPC_Type *) LPC_BASE)\r
-#define CEC1302_LPC_CONFIG ((LPC_CONFIG_Type *) LPC_CONFIG_BASE)\r
-#define CEC1302_GCR ((GCR_Type *) GCR_BASE)\r
-#define CEC1302_EMI ((EMI_Type *) EMI_BASE)\r
-#define CEC1302_ACPI_EC0 ((ACPI_EC0_Type *) ACPI_EC0_BASE)\r
-#define CEC1302_ACPI_EC1 ((ACPI_EC0_Type *) ACPI_EC1_BASE)\r
-#define CEC1302_KBC ((KBC_Type *) KBC_BASE)\r
-#define CEC1302_PORT92 ((PORT92_Type *) PORT92_BASE)\r
-#define CEC1302_MBX ((MBX_Type *) MBX_BASE)\r
-#define CEC1302_PM1 ((PM1_Type *) PM1_BASE)\r
-#define CEC1302_UART ((UART_Type *) UART_BASE)\r
-#define CEC1302_INTR ((INTR_Type *) INTR_BASE)\r
-#define CEC1302_WDT ((WDT_Type *) WDT_BASE)\r
-#define CEC1302_TIMER_16_0 ((TIMER_16_0_Type *) TIMER_16_0_BASE)\r
-#define CEC1302_TIMER_16_1 ((TIMER_16_0_Type *) TIMER_16_1_BASE)\r
-#define CEC1302_TIMER_16_2 ((TIMER_16_0_Type *) TIMER_16_2_BASE)\r
-#define CEC1302_TIMER_16_3 ((TIMER_16_0_Type *) TIMER_16_3_BASE)\r
-#define CEC1302_TIMER_32_0 ((TIMER_16_0_Type *) TIMER_32_0_BASE)\r
-#define CEC1302_TIMER_32_1 ((TIMER_16_0_Type *) TIMER_32_1_BASE)\r
-#define CEC1302_HTM ((HTM_Type *) HTM_BASE)\r
-#define CEC1302_RTC ((RTC_Type *) RTC_BASE)\r
-#define CEC1302_GPIO ((GPIO_Type *) GPIO_BASE)\r
-#define CEC1302_DMA ((DMA_Type *) DMA_BASE)\r
-#define CEC1302_SMB0 ((SMB0_Type *) SMB0_BASE)\r
-#define CEC1302_SMB1 ((SMB0_Type *) SMB1_BASE)\r
-#define CEC1302_SMB2 ((SMB0_Type *) SMB2_BASE)\r
-#define CEC1302_SMB3 ((SMB0_Type *) SMB3_BASE)\r
-#define CEC1302_PECI ((PECI_Type *) PECI_BASE)\r
-#define CEC1302_TACH_0 ((TACH_0_Type *) TACH_0_BASE)\r
-#define CEC1302_TACH_1 ((TACH_0_Type *) TACH_1_BASE)\r
-#define CEC1302_PWM_0 ((PWM_0_Type *) PWM_0_BASE)\r
-#define CEC1302_PWM_1 ((PWM_0_Type *) PWM_1_BASE)\r
-#define CEC1302_PWM_2 ((PWM_0_Type *) PWM_2_BASE)\r
-#define CEC1302_PWM_3 ((PWM_0_Type *) PWM_3_BASE)\r
-#define CEC1302_RPM_FAN ((RPM_FAN_Type *) RPM_FAN_BASE)\r
-#define CEC1302_SPI_0 ((SPI_0_Type *) SPI_0_BASE)\r
-#define CEC1302_SPI_1 ((SPI_0_Type *) SPI_1_BASE)\r
-#define CEC1302_LED_0 ((LED_0_Type *) LED_0_BASE)\r
-#define CEC1302_LED_1 ((LED_0_Type *) LED_1_BASE)\r
-#define CEC1302_LED_2 ((LED_0_Type *) LED_2_BASE)\r
-#define CEC1302_LED_3 ((LED_0_Type *) LED_3_BASE)\r
-#define CEC1302_PS2_0 ((PS2_0_Type *) PS2_0_BASE)\r
-#define CEC1302_PS2_1 ((PS2_0_Type *) PS2_1_BASE)\r
-#define CEC1302_PS2_2 ((PS2_0_Type *) PS2_2_BASE)\r
-#define CEC1302_PS2_3 ((PS2_0_Type *) PS2_3_BASE)\r
-#define CEC1302_KEYSCAN ((KEYSCAN_Type *) KEYSCAN_BASE)\r
-#define CEC1302_BC_LINK ((BC_LINK_Type *) BC_LINK_BASE)\r
-#define CEC1302_TFDP ((TFDP_Type *) TFDP_BASE)\r
-#define CEC1302_ADC ((ADC_Type *) ADC_BASE)\r
-#define CEC1302_EC_REG_BANK ((EC_REG_BANK_Type *) EC_REG_BANK_BASE)\r
-#define CEC1302_JTAG ((JTAG_Type *) JTAG_BASE)\r
-#define CEC1302_PKE ((PKE_TypeDef *) PKE_BASE)\r
-#define CEC1302_TRNG ((TRNG_TypeDef *) TRNG_BASE)\r
-#define CEC1302_HASH ((HASH_TypeDef *) HASH_BASE)\r
-#define CEC1302_AES ((AES_TypeDef *) AES_BASE)\r
-\r
- \r
-/** @} */ /* End of group Device_Peripheral_Registers */\r
-/** @} */ /* End of group MCHP_CEC1302 */\r
-/** @} */ /* End of group Microchip Technology Inc. */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* MCHP_CEC1302_H */\r
-\r
-\r
+++ /dev/null
-/*******************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-********************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-$File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/MEC1322.h $\r
-********************************************************************************\r
-$Revision: #1 $\r
-$DateTime: 2015/12/23 15:37:58 $\r
-$Author: akrishnan $\r
- Change Description: Initial revision for MEC1322\r
-******************************************************************************/\r
-/** @file smscmmcr.h\r
-* brief the mmcr definitions\r
-* \r
-******************************************************************************/\r
-#ifndef SMSCMMCR_H_\r
-#define SMSCMMCR_H_\r
-\r
-//NOTE: Please Don't edit this File, this is extrated from the Spread sheet \r
-// : //depotAE/projects/MEC1322/docs/MMCRs/MEC1322_FPGA1_Query_All_Addressing_ResultSet.csv\r
-typedef volatile unsigned char VUINT8;\r
-typedef volatile unsigned short int VUINT16;\r
-typedef volatile unsigned long int VUINT32;\r
-\r
-/***************************************************************\r
-* PWM\r
-***************************************************************/\r
-#define ADDR_PWM_0_COUNTER_ON_TIME 0x40005800\r
-#define MMCR_PWM_0_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_0_COUNTER_OFF_TIME 0x40005804\r
-#define MMCR_PWM_0_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_0_CONFIGURATION 0x40005808\r
-#define MMCR_PWM_0_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_0_CONFIGURATION))\r
-\r
-#define ADDR_PWM_1_COUNTER_ON_TIME 0x40005810\r
-#define MMCR_PWM_1_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_1_COUNTER_OFF_TIME 0x40005814\r
-#define MMCR_PWM_1_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_1_CONFIGURATION 0x40005818\r
-#define MMCR_PWM_1_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_1_CONFIGURATION))\r
-\r
-#define ADDR_PWM_2_COUNTER_ON_TIME 0x40005820\r
-#define MMCR_PWM_2_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_2_COUNTER_OFF_TIME 0x40005824\r
-#define MMCR_PWM_2_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_2_CONFIGURATION 0x40005828\r
-#define MMCR_PWM_2_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_2_CONFIGURATION))\r
-\r
-#define ADDR_PWM_3_COUNTER_ON_TIME 0x40005830\r
-#define MMCR_PWM_3_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_ON_TIME))\r
-\r
-#define ADDR_PWM_3_COUNTER_OFF_TIME 0x40005834\r
-#define MMCR_PWM_3_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_OFF_TIME))\r
-\r
-#define ADDR_PWM_3_CONFIGURATION 0x40005838\r
-#define MMCR_PWM_3_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_3_CONFIGURATION))\r
-\r
-/***************************************************************\r
-* PECI\r
-***************************************************************/\r
-#define ADDR_PECI_WRITE_DATA 0x40006400\r
-#define MMCR_PECI_WRITE_DATA (*(VUINT32 *)(ADDR_PECI_WRITE_DATA))\r
-\r
-#define ADDR_PECI_READ_DATA 0x40006404\r
-#define MMCR_PECI_READ_DATA (*(VUINT32 *)(ADDR_PECI_READ_DATA))\r
-\r
-#define ADDR_PECI_CONTROL 0x40006408\r
-#define MMCR_PECI_CONTROL (*(VUINT32 *)(ADDR_PECI_CONTROL))\r
-\r
-#define ADDR_PECI_STATUS_1 0x4000640C\r
-#define MMCR_PECI_STATUS_1 (*(VUINT32 *)(ADDR_PECI_STATUS_1))\r
-\r
-#define ADDR_PECI_STATUS_2 0x40006410\r
-#define MMCR_PECI_STATUS_2 (*(VUINT32 *)(ADDR_PECI_STATUS_2))\r
-\r
-#define ADDR_PECI_ERROR 0x40006414\r
-#define MMCR_PECI_ERROR (*(VUINT32 *)(ADDR_PECI_ERROR))\r
-\r
-#define ADDR_PECI_INTERRUPT_ENABLE_1 0x40006418\r
-#define MMCR_PECI_INTERRUPT_ENABLE_1 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_1))\r
-\r
-#define ADDR_PECI_INTERRUPT_ENABLE_2 0x4000641C\r
-#define MMCR_PECI_INTERRUPT_ENABLE_2 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_2))\r
-\r
-#define ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE 0x40006420\r
-#define MMCR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE))\r
-\r
-#define ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE 0x40006424\r
-#define MMCR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE))\r
-\r
-#define ADDR_PECI_REQUEST_TIMER_LOW_BYTE 0x40006428\r
-#define MMCR_PECI_REQUEST_TIMER_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_LOW_BYTE))\r
-\r
-#define ADDR_PECI_REQUEST_TIMER_HIGH_BYTE 0x4000642C\r
-#define MMCR_PECI_REQUEST_TIMER_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_HIGH_BYTE))\r
-\r
-#define ADDR_PECI_BLOCK_ID 0x40006440\r
-#define MMCR_PECI_BLOCK_ID (*(VUINT32 *)(ADDR_PECI_BLOCK_ID))\r
-\r
-#define ADDR_PECI_BLOCK_REVISION 0x40006444\r
-#define MMCR_PECI_BLOCK_REVISION (*(VUINT32 *)(ADDR_PECI_BLOCK_REVISION))\r
-\r
-/***************************************************************\r
-* ACPI EC Interface \r
-***************************************************************/\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0 0x400F0D00\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1 0x400F0D01\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2 0x400F0D02\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3 0x400F0D03\r
-#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3))\r
-\r
-#define ADDR_ACPI_0_STATUS_EC 0x400F0D04\r
-#define MMCR_ACPI_0_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_0_STATUS_EC))\r
-\r
-#define ADDR_ACPI_0_BYTE_CONTROL_EC 0x400F0D05\r
-#define MMCR_ACPI_0_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_0_BYTE_CONTROL_EC))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1 0x400F0D09\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2 0x400F0D0A\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3 0x400F0D0B\r
-#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0 0x400F1100\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1 0x400F1101\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2 0x400F1102\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3 0x400F1103\r
-#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3))\r
-\r
-#define ADDR_ACPI_1_STATUS_EC 0x400F1104\r
-#define MMCR_ACPI_1_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_1_STATUS_EC))\r
-\r
-#define ADDR_ACPI_1_BYTE_CONTROL_EC 0x400F1105\r
-#define MMCR_ACPI_1_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_1_BYTE_CONTROL_EC))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1 0x400F1109\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2 0x400F110A\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2))\r
-\r
-#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3 0x400F110B\r
-#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3))\r
-\r
-/***************************************************************\r
-* Keyboard Matrix Scan Support\r
-***************************************************************/\r
-#define ADDR_KEYBOARD_KSO_SELECT 0x40009C04\r
-#define MMCR_KEYBOARD_KSO_SELECT (*(VUINT32 *)(ADDR_KEYBOARD_KSO_SELECT))\r
-\r
-#define ADDR_KEYBOARD_KSI_INPUT 0x40009C08\r
-#define MMCR_KEYBOARD_KSI_INPUT (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INPUT))\r
-\r
-#define ADDR_KEYBOARD_KSI_STATUS 0x40009C0C\r
-#define MMCR_KEYBOARD_KSI_STATUS (*(VUINT32 *)(ADDR_KEYBOARD_KSI_STATUS))\r
-\r
-#define ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE 0x40009C10\r
-#define MMCR_KEYBOARD_KSI_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL 0x40009C14\r
-#define MMCR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL (*(VUINT32 *)(ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL))\r
-\r
-/***************************************************************\r
-* PS/2 Device Interface\r
-***************************************************************/\r
-#define ADDR_PS2_3_STATUS 0x400090C8\r
-#define MMCR_PS2_3_STATUS (*(VUINT8 *)(ADDR_PS2_3_STATUS))\r
-\r
-#define ADDR_PS2_3_CONTROL 0x400090C4\r
-#define MMCR_PS2_3_CONTROL (*(VUINT8 *)(ADDR_PS2_3_CONTROL))\r
-\r
-#define ADDR_PS2_3_RECEIVE_BUFFER 0x400090C0\r
-#define MMCR_PS2_3_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_3_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_3_TRANSMIT_BUFFER 0x400090C0\r
-#define MMCR_PS2_3_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_3_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_0_TRANSMIT_BUFFER 0x40009000\r
-#define MMCR_PS2_0_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_0_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_0_RECEIVE_BUFFER 0x40009000\r
-#define MMCR_PS2_0_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_0_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_0_CONTROL 0x40009004\r
-#define MMCR_PS2_0_CONTROL (*(VUINT8 *)(ADDR_PS2_0_CONTROL))\r
-\r
-#define ADDR_PS2_0_STATUS 0x40009008\r
-#define MMCR_PS2_0_STATUS (*(VUINT8 *)(ADDR_PS2_0_STATUS))\r
-\r
-#define ADDR_PS2_1_TRANSMIT_BUFFER 0x40009040\r
-#define MMCR_PS2_1_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_1_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_1_RECEIVE_BUFFER 0x40009040\r
-#define MMCR_PS2_1_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_1_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_1_CONTROL 0x40009044\r
-#define MMCR_PS2_1_CONTROL (*(VUINT8 *)(ADDR_PS2_1_CONTROL))\r
-\r
-#define ADDR_PS2_1_STATUS 0x40009048\r
-#define MMCR_PS2_1_STATUS (*(VUINT8 *)(ADDR_PS2_1_STATUS))\r
-\r
-#define ADDR_PS2_2_RECEIVE_BUFFER 0x40009080\r
-#define MMCR_PS2_2_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_2_RECEIVE_BUFFER))\r
-\r
-#define ADDR_PS2_2_TRANSMIT_BUFFER 0x40009080\r
-#define MMCR_PS2_2_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_2_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_PS2_2_CONTROL 0x40009084\r
-#define MMCR_PS2_2_CONTROL (*(VUINT8 *)(ADDR_PS2_2_CONTROL))\r
-\r
-#define ADDR_PS2_2_STATUS 0x40009088\r
-#define MMCR_PS2_2_STATUS (*(VUINT8 *)(ADDR_PS2_2_STATUS))\r
-\r
-/***************************************************************\r
-* 8042 Host Interface\r
-***************************************************************/\r
-#define ADDR_8042_ACTIVATE 0x400F0730\r
-#define MMCR_8042_ACTIVATE (*(VUINT8 *)(ADDR_8042_ACTIVATE))\r
-\r
-#define ADDR_8042_HOST_EC_DATACMD 0x400F0500\r
-#define MMCR_8042_HOST_EC_DATACMD (*(VUINT8 *)(ADDR_8042_HOST_EC_DATACMD))\r
-\r
-#define ADDR_8042_EC_HOST_DATA 0x400F0500\r
-#define MMCR_8042_EC_HOST_DATA (*(VUINT8 *)(ADDR_8042_EC_HOST_DATA))\r
-\r
-#define ADDR_8042_KEYBOARD_STATUS_READ 0x400F0504\r
-#define MMCR_8042_KEYBOARD_STATUS_READ (*(VUINT8 *)(ADDR_8042_KEYBOARD_STATUS_READ))\r
-\r
-#define ADDR_8042_KEYBOARD_CONTROL 0x400F0508\r
-#define MMCR_8042_KEYBOARD_CONTROL (*(VUINT8 *)(ADDR_8042_KEYBOARD_CONTROL))\r
-\r
-#define ADDR_8042_EC_HOST_AUX 0x400F050C\r
-#define MMCR_8042_EC_HOST_AUX (*(VUINT8 *)(ADDR_8042_EC_HOST_AUX))\r
-\r
-#define ADDR_8042_PCOBF 0x400F0514\r
-#define MMCR_8042_PCOBF (*(VUINT8 *)(ADDR_8042_PCOBF))\r
-\r
-#define ADDR_8042_PORT92_ENABLE 0x400F1B30\r
-#define MMCR_8042_PORT92_ENABLE (*(VUINT8 *)(ADDR_8042_PORT92_ENABLE))\r
-\r
-#define ADDR_8042_GATEA20_CONTROL 0x400F1900\r
-#define MMCR_8042_GATEA20_CONTROL (*(VUINT8 *)(ADDR_8042_GATEA20_CONTROL))\r
-\r
-#define ADDR_8042_SETGA20L 0x400F1908\r
-#define MMCR_8042_SETGA20L (*(VUINT8 *)(ADDR_8042_SETGA20L))\r
-\r
-#define ADDR_8042_RSTGA20L 0x400F190C\r
-#define MMCR_8042_RSTGA20L (*(VUINT8 *)(ADDR_8042_RSTGA20L))\r
-\r
-/***************************************************************\r
-* SMBus\r
-***************************************************************/\r
-#define ADDR_SMB_3_DEBUG_FSM_SMB 0x4000B45C\r
-#define MMCR_SMB_3_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_SMB))\r
-\r
-#define ADDR_SMB_3_DEBUG_FSM_I2C 0x4000B458\r
-#define MMCR_SMB_3_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER 0x4000B454\r
-#define MMCR_SMBUS_3_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER 0x4000B450\r
-#define MMCR_SMBUS_3_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER 0x4000B44C\r
-#define MMCR_SMBUS_3_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER 0x4000B448\r
-#define MMCR_SMBUS_3_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMB_3_TIME_OUT_SCALING 0x4000B444\r
-#define MMCR_SMB_3_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_3_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMB_3_DATA_TIMING 0x4000B440\r
-#define MMCR_SMB_3_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_3_DATA_TIMING))\r
-\r
-#define ADDR_SMB_3_CLOCK_SYNC 0x4000B43C\r
-#define MMCR_SMB_3_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_3_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_3_BIT_BANG_CONTROL 0x4000B438\r
-#define MMCR_SMB_3_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_3_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_3_REVISION 0x4000B434\r
-#define MMCR_SMB_3_REVISION (*(VUINT8 *)(ADDR_SMB_3_REVISION))\r
-\r
-#define ADDR_SMB_3_BLOCK_ID 0x4000B430\r
-#define MMCR_SMB_3_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_3_BLOCK_ID))\r
-\r
-#define ADDR_SMB_3_BUS_CLOCK 0x4000B42C\r
-#define MMCR_SMB_3_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_3_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_3_CONFIGURATION 0x4000B428\r
-#define MMCR_SMB_3_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_3_CONFIGURATION))\r
-\r
-#define ADDR_SMB_3_IDLE_SCALING 0x4000B424\r
-#define MMCR_SMB_3_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_3_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_3_COMPLETION 0x4000B420\r
-#define MMCR_SMB_3_COMPLETION (*(VUINT32 *)(ADDR_SMB_3_COMPLETION))\r
-\r
-#define ADDR_SMB_3_DATA_TIMING2 0x4000B418\r
-#define MMCR_SMB_3_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_3_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_3_PEC 0x4000B414\r
-#define MMCR_SMB_3_PEC (*(VUINT8 *)(ADDR_SMB_3_PEC))\r
-\r
-#define ADDR_SMBUS_3_SLAVE_COMMAND 0x4000B410\r
-#define MMCR_SMBUS_3_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMBUS_3_MASTER_COMMAND 0x4000B40C\r
-#define MMCR_SMBUS_3_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_MASTER_COMMAND))\r
-\r
-#define ADDR_SMB_3_DATA 0x4000B408\r
-#define MMCR_SMB_3_DATA (*(VUINT8 *)(ADDR_SMB_3_DATA))\r
-\r
-#define ADDR_SMB_3_OWN_ADDRESS 0x4000B404\r
-#define MMCR_SMB_3_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_3_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_3_STATUS 0x4000B400\r
-#define MMCR_SMB_3_STATUS (*(VUINT8 *)(ADDR_SMB_3_STATUS))\r
-\r
-#define ADDR_SMB_3_CONTROL 0x4000B400\r
-#define MMCR_SMB_3_CONTROL (*(VUINT8 *)(ADDR_SMB_3_CONTROL))\r
-\r
-#define ADDR_SMB_2_CONTROL 0x4000B000\r
-#define MMCR_SMB_2_CONTROL (*(VUINT8 *)(ADDR_SMB_2_CONTROL))\r
-\r
-#define ADDR_SMB_2_STATUS 0x4000B000\r
-#define MMCR_SMB_2_STATUS (*(VUINT8 *)(ADDR_SMB_2_STATUS))\r
-\r
-#define ADDR_SMB_2_OWN_ADDRESS 0x4000B004\r
-#define MMCR_SMB_2_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_2_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_2_DATA 0x4000B008\r
-#define MMCR_SMB_2_DATA (*(VUINT8 *)(ADDR_SMB_2_DATA))\r
-\r
-#define ADDR_SMBUS_2_MASTER_COMMAND 0x4000B00C\r
-#define MMCR_SMBUS_2_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_MASTER_COMMAND))\r
-\r
-#define ADDR_SMBUS_2_SLAVE_COMMAND 0x4000B010\r
-#define MMCR_SMBUS_2_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMB_2_PEC 0x4000B014\r
-#define MMCR_SMB_2_PEC (*(VUINT8 *)(ADDR_SMB_2_PEC))\r
-\r
-#define ADDR_SMB_2_DATA_TIMING2 0x4000B018\r
-#define MMCR_SMB_2_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_2_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_2_COMPLETION 0x4000B020\r
-#define MMCR_SMB_2_COMPLETION (*(VUINT32 *)(ADDR_SMB_2_COMPLETION))\r
-\r
-#define ADDR_SMB_2_IDLE_SCALING 0x4000B024\r
-#define MMCR_SMB_2_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_2_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_2_CONFIGURATION 0x4000B028\r
-#define MMCR_SMB_2_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_2_CONFIGURATION))\r
-\r
-#define ADDR_SMB_2_BUS_CLOCK 0x4000B02C\r
-#define MMCR_SMB_2_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_2_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_2_BLOCK_ID 0x4000B030\r
-#define MMCR_SMB_2_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_2_BLOCK_ID))\r
-\r
-#define ADDR_SMB_2_REVISION 0x4000B034\r
-#define MMCR_SMB_2_REVISION (*(VUINT8 *)(ADDR_SMB_2_REVISION))\r
-\r
-#define ADDR_SMB_2_BIT_BANG_CONTROL 0x4000B038\r
-#define MMCR_SMB_2_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_2_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_2_CLOCK_SYNC 0x4000B03C\r
-#define MMCR_SMB_2_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_2_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_2_DATA_TIMING 0x4000B040\r
-#define MMCR_SMB_2_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_2_DATA_TIMING))\r
-\r
-#define ADDR_SMB_2_TIME_OUT_SCALING 0x4000B044\r
-#define MMCR_SMB_2_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_2_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER 0x4000B048\r
-#define MMCR_SMBUS_2_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER 0x4000B04C\r
-#define MMCR_SMBUS_2_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER 0x4000B050\r
-#define MMCR_SMBUS_2_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER 0x4000B054\r
-#define MMCR_SMBUS_2_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMB_2_DEBUG_FSM_I2C 0x4000B058\r
-#define MMCR_SMB_2_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMB_2_DEBUG_FSM_SMB 0x4000B05C\r
-#define MMCR_SMB_2_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_SMB))\r
-\r
-#define ADDR_SMB_1_CONTROL 0x4000AC00\r
-#define MMCR_SMB_1_CONTROL (*(VUINT8 *)(ADDR_SMB_1_CONTROL))\r
-\r
-#define ADDR_SMB_1_STATUS 0x4000AC00\r
-#define MMCR_SMB_1_STATUS (*(VUINT8 *)(ADDR_SMB_1_STATUS))\r
-\r
-#define ADDR_SMB_1_OWN_ADDRESS 0x4000AC04\r
-#define MMCR_SMB_1_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_1_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_1_DATA 0x4000AC08\r
-#define MMCR_SMB_1_DATA (*(VUINT8 *)(ADDR_SMB_1_DATA))\r
-\r
-#define ADDR_SMBUS_1_MASTER_COMMAND 0x4000AC0C\r
-#define MMCR_SMBUS_1_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_MASTER_COMMAND))\r
-\r
-#define ADDR_SMBUS_1_SLAVE_COMMAND 0x4000AC10\r
-#define MMCR_SMBUS_1_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMB_1_PEC 0x4000AC14\r
-#define MMCR_SMB_1_PEC (*(VUINT8 *)(ADDR_SMB_1_PEC))\r
-\r
-#define ADDR_SMB_1_DATA_TIMING2 0x4000AC18\r
-#define MMCR_SMB_1_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_1_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_1_COMPLETION 0x4000AC20\r
-#define MMCR_SMB_1_COMPLETION (*(VUINT32 *)(ADDR_SMB_1_COMPLETION))\r
-\r
-#define ADDR_SMB_1_IDLE_SCALING 0x4000AC24\r
-#define MMCR_SMB_1_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_1_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_1_CONFIGURATION 0x4000AC28\r
-#define MMCR_SMB_1_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_1_CONFIGURATION))\r
-\r
-#define ADDR_SMB_1_BUS_CLOCK 0x4000AC2C\r
-#define MMCR_SMB_1_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_1_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_1_BLOCK_ID 0x4000AC30\r
-#define MMCR_SMB_1_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_1_BLOCK_ID))\r
-\r
-#define ADDR_SMB_1_REVISION 0x4000AC34\r
-#define MMCR_SMB_1_REVISION (*(VUINT8 *)(ADDR_SMB_1_REVISION))\r
-\r
-#define ADDR_SMB_1_BIT_BANG_CONTROL 0x4000AC38\r
-#define MMCR_SMB_1_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_1_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_1_CLOCK_SYNC 0x4000AC3C\r
-#define MMCR_SMB_1_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_1_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_1_DATA_TIMING 0x4000AC40\r
-#define MMCR_SMB_1_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_1_DATA_TIMING))\r
-\r
-#define ADDR_SMB_1_TIME_OUT_SCALING 0x4000AC44\r
-#define MMCR_SMB_1_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_1_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER 0x4000AC48\r
-#define MMCR_SMBUS_1_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER 0x4000AC4C\r
-#define MMCR_SMBUS_1_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER 0x4000AC50\r
-#define MMCR_SMBUS_1_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER 0x4000AC54\r
-#define MMCR_SMBUS_1_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMB_1_DEBUG_FSM_I2C 0x4000AC58\r
-#define MMCR_SMB_1_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMB_1_DEBUG_FSM_SMB 0x4000AC5C\r
-#define MMCR_SMB_1_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_SMB))\r
-\r
-#define ADDR_SMB_0_STATUS 0x40001800\r
-#define MMCR_SMB_0_STATUS (*(VUINT8 *)(ADDR_SMB_0_STATUS))\r
-\r
-#define ADDR_SMB_0_CONTROL 0x40001800\r
-#define MMCR_SMB_0_CONTROL (*(VUINT8 *)(ADDR_SMB_0_CONTROL))\r
-\r
-#define ADDR_SMB_0_OWN_ADDRESS 0x40001804\r
-#define MMCR_SMB_0_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_0_OWN_ADDRESS))\r
-\r
-#define ADDR_SMB_0_DATA 0x40001808\r
-#define MMCR_SMB_0_DATA (*(VUINT8 *)(ADDR_SMB_0_DATA))\r
-\r
-#define ADDR_SMBUS_0_MASTER_COMMAND 0x4000180C\r
-#define MMCR_SMBUS_0_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_MASTER_COMMAND))\r
-\r
-#define ADDR_SMBUS_0_SLAVE_COMMAND 0x40001810\r
-#define MMCR_SMBUS_0_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_SLAVE_COMMAND))\r
-\r
-#define ADDR_SMB_0_PEC 0x40001814\r
-#define MMCR_SMB_0_PEC (*(VUINT8 *)(ADDR_SMB_0_PEC))\r
-\r
-#define ADDR_SMB_0_DATA_TIMING2 0x40001818\r
-#define MMCR_SMB_0_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_0_DATA_TIMING2))\r
-\r
-#define ADDR_SMB_0_COMPLETION 0x40001820\r
-#define MMCR_SMB_0_COMPLETION (*(VUINT32 *)(ADDR_SMB_0_COMPLETION))\r
-\r
-#define ADDR_SMB_0_IDLE_SCALING 0x40001824\r
-#define MMCR_SMB_0_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_0_IDLE_SCALING))\r
-\r
-#define ADDR_SMB_0_CONFIGURATION 0x40001828\r
-#define MMCR_SMB_0_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_0_CONFIGURATION))\r
-\r
-#define ADDR_SMB_0_BUS_CLOCK 0x4000182C\r
-#define MMCR_SMB_0_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_0_BUS_CLOCK))\r
-\r
-#define ADDR_SMB_0_BLOCK_ID 0x40001830\r
-#define MMCR_SMB_0_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_0_BLOCK_ID))\r
-\r
-#define ADDR_SMB_0_REVISION 0x40001834\r
-#define MMCR_SMB_0_REVISION (*(VUINT8 *)(ADDR_SMB_0_REVISION))\r
-\r
-#define ADDR_SMB_0_BIT_BANG_CONTROL 0x40001838\r
-#define MMCR_SMB_0_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_0_BIT_BANG_CONTROL))\r
-\r
-#define ADDR_SMB_0_CLOCK_SYNC 0x4000183C\r
-#define MMCR_SMB_0_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_0_CLOCK_SYNC))\r
-\r
-#define ADDR_SMB_0_DATA_TIMING 0x40001840\r
-#define MMCR_SMB_0_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_0_DATA_TIMING))\r
-\r
-#define ADDR_SMB_0_TIME_OUT_SCALING 0x40001844\r
-#define MMCR_SMB_0_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_0_TIME_OUT_SCALING))\r
-\r
-#define ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER 0x40001848\r
-#define MMCR_SMBUS_0_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER 0x4000184C\r
-#define MMCR_SMBUS_0_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER 0x40001850\r
-#define MMCR_SMBUS_0_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER))\r
-\r
-#define ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER 0x40001854\r
-#define MMCR_SMBUS_0_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER))\r
-\r
-#define ADDR_SMB_0_DEBUG_FSM_I2C 0x40001858\r
-#define MMCR_SMB_0_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_I2C))\r
-\r
-#define ADDR_SMB_0_DEBUG_FSM_SMB 0x4000185C\r
-#define MMCR_SMB_0_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_SMB))\r
-\r
-/***************************************************************\r
-* Watchdog Timer Interface\r
-***************************************************************/\r
-#define ADDR_WATCHDOG_WDT_LOAD 0x40000400\r
-#define MMCR_WATCHDOG_WDT_LOAD (*(VUINT16 *)(ADDR_WATCHDOG_WDT_LOAD))\r
-\r
-#define ADDR_WATCHDOG_WDT_CONTROL 0x40000404\r
-#define MMCR_WATCHDOG_WDT_CONTROL (*(VUINT8 *)(ADDR_WATCHDOG_WDT_CONTROL))\r
-\r
-#define ADDR_WATCHDOG_WDT_KICK 0x40000408\r
-#define MMCR_WATCHDOG_WDT_KICK (*(VUINT8 *)(ADDR_WATCHDOG_WDT_KICK))\r
-\r
-#define ADDR_WATCHDOG_WDT_COUNT 0x4000040C\r
-#define MMCR_WATCHDOG_WDT_COUNT (*(VUINT16 *)(ADDR_WATCHDOG_WDT_COUNT))\r
-\r
-/***************************************************************\r
-* ACPI PM1\r
-***************************************************************/\r
-#define ADDR_ACPI_0_PM1_STATUS_1 0x400F1500\r
-#define MMCR_ACPI_0_PM1_STATUS_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_1))\r
-\r
-#define ADDR_ACPI_0_PM1_STATUS_2 0x400F1501\r
-#define MMCR_ACPI_0_PM1_STATUS_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_2))\r
-\r
-#define ADDR_ACPI_0_PM1_ENABLE_1 0x400F1502\r
-#define MMCR_ACPI_0_PM1_ENABLE_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_1))\r
-\r
-#define ADDR_ACPI_0_PM1_ENABLE_2 0x400F1503\r
-#define MMCR_ACPI_0_PM1_ENABLE_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_2))\r
-\r
-#define ADDR_ACPI_0_PM1_CONTROL_1 0x400F1504\r
-#define MMCR_ACPI_0_PM1_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_1))\r
-\r
-#define ADDR_ACPI_0_PM1_CONTROL_2 0x400F1505\r
-#define MMCR_ACPI_0_PM1_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_2))\r
-\r
-#define ADDR_ACPI_0_PM2_CONTROL_1 0x400F1506\r
-#define MMCR_ACPI_0_PM2_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_1))\r
-\r
-#define ADDR_ACPI_0_PM2_CONTROL_2 0x400F1507\r
-#define MMCR_ACPI_0_PM2_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_2))\r
-\r
-#define ADDR_ACPI_0_PM1_EC_PM_STATUS 0x400F1510\r
-#define MMCR_ACPI_0_PM1_EC_PM_STATUS (*(VUINT8 *)(ADDR_ACPI_0_PM1_EC_PM_STATUS))\r
-\r
-/***************************************************************\r
-* EC GP-SPI\r
-***************************************************************/\r
-#define ADDR_EC_1_SPI_CLOCK_GENERATOR 0x40009498\r
-#define MMCR_EC_1_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_GENERATOR))\r
-\r
-#define ADDR_EC_1_SPI_CLOCK_CONTROL 0x40009494\r
-#define MMCR_EC_1_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_CONTROL))\r
-\r
-#define ADDR_EC_1_SPI_RX_DATA 0x40009490\r
-#define MMCR_EC_1_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_RX_DATA))\r
-\r
-#define ADDR_EC_1_SPI_TX_DATA 0x4000948C\r
-#define MMCR_EC_1_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_TX_DATA))\r
-\r
-#define ADDR_EC_1_SPI_STATUS 0x40009488\r
-#define MMCR_EC_1_SPI_STATUS (*(VUINT32 *)(ADDR_EC_1_SPI_STATUS))\r
-\r
-#define ADDR_EC_1_SPI_CONTROL 0x40009484\r
-#define MMCR_EC_1_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CONTROL))\r
-\r
-#define ADDR_EC_1_SPI_ENABLE 0x40009480\r
-#define MMCR_EC_1_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_1_SPI_ENABLE))\r
-\r
-#define ADDR_EC_0_SPI_ENABLE 0x40009400\r
-#define MMCR_EC_0_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_0_SPI_ENABLE))\r
-\r
-#define ADDR_EC_0_SPI_CONTROL 0x40009404\r
-#define MMCR_EC_0_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CONTROL))\r
-\r
-#define ADDR_EC_0_SPI_STATUS 0x40009408\r
-#define MMCR_EC_0_SPI_STATUS (*(VUINT32 *)(ADDR_EC_0_SPI_STATUS))\r
-\r
-#define ADDR_EC_0_SPI_TX_DATA 0x4000940C\r
-#define MMCR_EC_0_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_TX_DATA))\r
-\r
-#define ADDR_EC_0_SPI_RX_DATA 0x40009410\r
-#define MMCR_EC_0_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_RX_DATA))\r
-\r
-#define ADDR_EC_0_SPI_CLOCK_CONTROL 0x40009414\r
-#define MMCR_EC_0_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_CONTROL))\r
-\r
-#define ADDR_EC_0_SPI_CLOCK_GENERATOR 0x40009418\r
-#define MMCR_EC_0_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_GENERATOR))\r
-\r
-/***************************************************************\r
-* Mailbox Registers Interface\r
-***************************************************************/\r
-#define ADDR_MAILBOX_HOST_TO_EC_MAILBOX 0x400F2500\r
-#define MMCR_MAILBOX_HOST_TO_EC_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_HOST_TO_EC_MAILBOX))\r
-\r
-#define ADDR_MAILBOX_EC_TO_HOST_MAILBOX 0x400F2504\r
-#define MMCR_MAILBOX_EC_TO_HOST_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_EC_TO_HOST_MAILBOX))\r
-\r
-#define ADDR_MAILBOX_SMI_INTERRUPT_SOURCE 0x400F2508\r
-#define MMCR_MAILBOX_SMI_INTERRUPT_SOURCE (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_SOURCE))\r
-\r
-#define ADDR_MAILBOX_SMI_INTERRUPT_MASK 0x400F250C\r
-#define MMCR_MAILBOX_SMI_INTERRUPT_MASK (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_MASK))\r
-\r
-#define ADDR_MAILBOX_3_0 0x400F2510\r
-#define MMCR_MAILBOX_3_0 (*(VUINT32 *)(ADDR_MAILBOX_3_0))\r
-\r
-#define ADDR_MAILBOX_7_4 0x400F2514\r
-#define MMCR_MAILBOX_7_4 (*(VUINT32 *)(ADDR_MAILBOX_7_4))\r
-\r
-#define ADDR_MAILBOX_BH_8 0x400F2518\r
-#define MMCR_MAILBOX_BH_8 (*(VUINT32 *)(ADDR_MAILBOX_BH_8))\r
-\r
-#define ADDR_MAILBOX_FH_CH 0x400F251C\r
-#define MMCR_MAILBOX_FH_CH (*(VUINT32 *)(ADDR_MAILBOX_FH_CH))\r
-\r
-#define ADDR_MAILBOX_13H_10H 0x400F2520\r
-#define MMCR_MAILBOX_13H_10H (*(VUINT32 *)(ADDR_MAILBOX_13H_10H))\r
-\r
-#define ADDR_MAILBOX_17H_14H 0x400F2524\r
-#define MMCR_MAILBOX_17H_14H (*(VUINT32 *)(ADDR_MAILBOX_17H_14H))\r
-\r
-#define ADDR_MAILBOX_1BH_18H 0x400F2528\r
-#define MMCR_MAILBOX_1BH_18H (*(VUINT32 *)(ADDR_MAILBOX_1BH_18H))\r
-\r
-#define ADDR_MAILBOX_1FH_1CH 0x400F252C\r
-#define MMCR_MAILBOX_1FH_1CH (*(VUINT32 *)(ADDR_MAILBOX_1FH_1CH))\r
-\r
-/***************************************************************\r
-* Hibernation Timer\r
-***************************************************************/\r
-#define ADDR_HIBERNATION_0_HTIMER_X_PRELOAD 0x40009800\r
-#define MMCR_HIBERNATION_0_HTIMER_X_PRELOAD (*(VUINT16 *)(ADDR_HIBERNATION_0_HTIMER_X_PRELOAD))\r
-\r
-#define ADDR_HIBERNATION_0_TIMER_X_CONTROL 0x40009804\r
-#define MMCR_HIBERNATION_0_TIMER_X_CONTROL (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_CONTROL))\r
-\r
-#define ADDR_HIBERNATION_0_TIMER_X_COUNT 0x40009808\r
-#define MMCR_HIBERNATION_0_TIMER_X_COUNT (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_COUNT))\r
-\r
-/***************************************************************\r
-* UART\r
-***************************************************************/\r
-#define ADDR_M16C550A_UART_ACTIVATE 0x400F1F30\r
-#define MMCR_M16C550A_UART_ACTIVATE (*(VUINT8 *)(ADDR_M16C550A_UART_ACTIVATE))\r
-\r
-#define ADDR_M16C550A_UART_CONFIG_SELECT 0x400F1FF0\r
-#define MMCR_M16C550A_UART_CONFIG_SELECT (*(VUINT8 *)(ADDR_M16C550A_UART_CONFIG_SELECT))\r
-\r
-#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB 0x400F1D00\r
-#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB))\r
-\r
-#define ADDR_M16C550A_UART_RECEIVE_BUFFER 0x400F1D00\r
-#define MMCR_M16C550A_UART_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_RECEIVE_BUFFER))\r
-\r
-#define ADDR_M16C550A_UART_TRANSMIT_BUFFER 0x400F1D00\r
-#define MMCR_M16C550A_UART_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_TRANSMIT_BUFFER))\r
-\r
-#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB 0x400F1D01\r
-#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB))\r
-\r
-#define ADDR_M16C550A_UART_INTERRUPT_ENABLE 0x400F1D01\r
-#define MMCR_M16C550A_UART_INTERRUPT_ENABLE (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_M16C550A_UART_FIFO_CONTROL 0x400F1D02\r
-#define MMCR_M16C550A_UART_FIFO_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_FIFO_CONTROL))\r
-\r
-#define ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION 0x400F1D02\r
-#define MMCR_M16C550A_UART_INTERRUPT_IDENTIFICATION (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION))\r
-\r
-#define ADDR_M16C550A_UART_LINE_CONTROL 0x400F1D03\r
-#define MMCR_M16C550A_UART_LINE_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_CONTROL))\r
-\r
-#define ADDR_M16C550A_UART_MODEM_CONTROL 0x400F1D04\r
-#define MMCR_M16C550A_UART_MODEM_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_CONTROL))\r
-\r
-#define ADDR_M16C550A_UART_LINE_STATUS 0x400F1D05\r
-#define MMCR_M16C550A_UART_LINE_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_STATUS))\r
-\r
-#define ADDR_M16C550A_UART_MODEM_STATUS 0x400F1D06\r
-#define MMCR_M16C550A_UART_MODEM_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_STATUS))\r
-\r
-#define ADDR_M16C550A_UART_SCRATCHPAD 0x400F1D07\r
-#define MMCR_M16C550A_UART_SCRATCHPAD (*(VUINT8 *)(ADDR_M16C550A_UART_SCRATCHPAD))\r
-\r
-/***************************************************************\r
-* TACH\r
-***************************************************************/\r
-#define ADDR_TACH_0_CONTROL 0x40006000\r
-#define MMCR_TACH_0_CONTROL (*(VUINT32 *)(ADDR_TACH_0_CONTROL))\r
-\r
-#define ADDR_TACH_0_STATUS 0x40006004\r
-#define MMCR_TACH_0_STATUS (*(VUINT32 *)(ADDR_TACH_0_STATUS))\r
-\r
-#define ADDR_TACH_0_HIGH_LIMIT 0x40006008\r
-#define MMCR_TACH_0_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_0_HIGH_LIMIT))\r
-\r
-#define ADDR_TACH_0_LOW_LIMIT 0x4000600C\r
-#define MMCR_TACH_0_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_0_LOW_LIMIT))\r
-\r
-#define ADDR_TACH_1_CONTROL 0x40006010\r
-#define MMCR_TACH_1_CONTROL (*(VUINT32 *)(ADDR_TACH_1_CONTROL))\r
-\r
-#define ADDR_TACH_1_STATUS 0x40006014\r
-#define MMCR_TACH_1_STATUS (*(VUINT32 *)(ADDR_TACH_1_STATUS))\r
-\r
-#define ADDR_TACH_1_HIGH_LIMIT 0x40006018\r
-#define MMCR_TACH_1_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_1_HIGH_LIMIT))\r
-\r
-#define ADDR_TACH_1_LOW_LIMIT 0x4000601C\r
-#define MMCR_TACH_1_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_1_LOW_LIMIT))\r
-\r
-/***************************************************************\r
-* Global Config Regs Basic\r
-***************************************************************/\r
-#define ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER 0x400FFF07\r
-#define MMCR_GLOBAL_LOGICAL_DEVICE_NUMBER (*(VUINT8 *)(ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER))\r
-\r
-#define ADDR_GLOBAL_DEVICE_ID 0x400FFF20\r
-#define MMCR_GLOBAL_DEVICE_ID (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_ID))\r
-\r
-#define ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED 0x400FFF21\r
-#define MMCR_GLOBAL_DEVICE_REVISION_HARD_WIRED (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED))\r
-\r
-#define ADDR_GLOBAL_GCR_BUILD 0x400FFF28\r
-#define MMCR_GLOBAL_GCR_BUILD (*(VUINT16 *)(ADDR_GLOBAL_GCR_BUILD))\r
-\r
-#define ADDR_GLOBAL_GCR_SCRATCH 0x400FFF2C\r
-#define MMCR_GLOBAL_GCR_SCRATCH (*(VUINT32 *)(ADDR_GLOBAL_GCR_SCRATCH))\r
-\r
-/***************************************************************\r
-* Trace FIFO Debug Port\r
-***************************************************************/\r
-#define ADDR_TRACE_DATA 0x40008C00\r
-#define MMCR_TRACE_DATA (*(VUINT32 *)(ADDR_TRACE_DATA))\r
-\r
-#define ADDR_TRACE_CONTROL 0x40008C04\r
-#define MMCR_TRACE_CONTROL (*(VUINT32 *)(ADDR_TRACE_CONTROL))\r
-\r
-/***************************************************************\r
-* STAP\r
-***************************************************************/\r
-#define ADDR_STAP_MESSAGE_OBF 0x40080000\r
-#define MMCR_STAP_MESSAGE_OBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_OBF))\r
-\r
-#define ADDR_STAP_MESSAGE_IBF 0x40080004\r
-#define MMCR_STAP_MESSAGE_IBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_IBF))\r
-\r
-#define ADDR_STAP_OBF_STATUS 0x40080008\r
-#define MMCR_STAP_OBF_STATUS (*(VUINT8 *)(ADDR_STAP_OBF_STATUS))\r
-\r
-#define ADDR_STAP_IBF_STATUS 0x40080009\r
-#define MMCR_STAP_IBF_STATUS (*(VUINT8 *)(ADDR_STAP_IBF_STATUS))\r
-\r
-#define ADDR_STAP_DBG_CTRL 0x4008000C\r
-#define MMCR_STAP_DBG_CTRL (*(VUINT8 *)(ADDR_STAP_DBG_CTRL))\r
-\r
-/***************************************************************\r
-* EMI\r
-***************************************************************/\r
-#define ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX 0x400F0100\r
-#define MMCR_IMAP_EMI_HOST_TO_EC_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX))\r
-\r
-#define ADDR_IMAP_EC_TO_HOST_MAILBOX 0x400F0101\r
-#define MMCR_IMAP_EC_TO_HOST_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EC_TO_HOST_MAILBOX))\r
-\r
-#define ADDR_IMAP_MEMORY_BASE_ADDRESS_0 0x400F0104\r
-#define MMCR_IMAP_MEMORY_BASE_ADDRESS_0 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_0))\r
-\r
-#define ADDR_IMAP_MEMORY_READ_LIMIT_0 0x400F0108\r
-#define MMCR_IMAP_MEMORY_READ_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_0))\r
-\r
-#define ADDR_IMAP_MEMORY_WRITE_LIMIT_0 0x400F010A\r
-#define MMCR_IMAP_MEMORY_WRITE_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_0))\r
-\r
-#define ADDR_IMAP_MEMORY_BASE_ADDRESS_1 0x400F010C\r
-#define MMCR_IMAP_MEMORY_BASE_ADDRESS_1 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_1))\r
-\r
-#define ADDR_IMAP_MEMORY_READ_LIMIT_1 0x400F0110\r
-#define MMCR_IMAP_MEMORY_READ_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_1))\r
-\r
-#define ADDR_IMAP_MEMORY_WRITE_LIMIT_1 0x400F0112\r
-#define MMCR_IMAP_MEMORY_WRITE_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_1))\r
-\r
-#define ADDR_IMAP_INTERRUPT_SET 0x400F0114\r
-#define MMCR_IMAP_INTERRUPT_SET (*(VUINT16 *)(ADDR_IMAP_INTERRUPT_SET))\r
-\r
-#define ADDR_IMAP_HOST_CLEAR_ENABLE 0x400F0116\r
-#define MMCR_IMAP_HOST_CLEAR_ENABLE (*(VUINT16 *)(ADDR_IMAP_HOST_CLEAR_ENABLE))\r
-\r
-/***************************************************************\r
-* Blinking/Breathing PWM\r
-***************************************************************/\r
-#define ADDR_LED_3_UPDATE_INTERVAL 0x4000BB10\r
-#define MMCR_LED_3_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_3_UPDATE_INTERVAL))\r
-\r
-#define ADDR_LED_3_UPDATE_STEPSIZE 0x4000BB0C\r
-#define MMCR_LED_3_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_3_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_3_DELAY 0x4000BB08\r
-#define MMCR_LED_3_DELAY (*(VUINT32 *)(ADDR_LED_3_DELAY))\r
-\r
-#define ADDR_LED_3_LIMITS 0x4000BB04\r
-#define MMCR_LED_3_LIMITS (*(VUINT32 *)(ADDR_LED_3_LIMITS))\r
-\r
-#define ADDR_LED_3_CONFIGURATION 0x4000BB00\r
-#define MMCR_LED_3_CONFIGURATION (*(VUINT32 *)(ADDR_LED_3_CONFIGURATION))\r
-\r
-#define ADDR_LED_2_UPDATE_INTERVAL 0x4000BA10\r
-#define MMCR_LED_2_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_2_UPDATE_INTERVAL))\r
-\r
-#define ADDR_LED_2_UPDATE_STEPSIZE 0x4000BA0C\r
-#define MMCR_LED_2_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_2_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_2_DELAY 0x4000BA08\r
-#define MMCR_LED_2_DELAY (*(VUINT32 *)(ADDR_LED_2_DELAY))\r
-\r
-#define ADDR_LED_2_LIMITS 0x4000BA04\r
-#define MMCR_LED_2_LIMITS (*(VUINT32 *)(ADDR_LED_2_LIMITS))\r
-\r
-#define ADDR_LED_2_CONFIGURATION 0x4000BA00\r
-#define MMCR_LED_2_CONFIGURATION (*(VUINT32 *)(ADDR_LED_2_CONFIGURATION))\r
-\r
-#define ADDR_LED_1_CONFIGURATION 0x4000B900\r
-#define MMCR_LED_1_CONFIGURATION (*(VUINT32 *)(ADDR_LED_1_CONFIGURATION))\r
-\r
-#define ADDR_LED_1_LIMITS 0x4000B904\r
-#define MMCR_LED_1_LIMITS (*(VUINT32 *)(ADDR_LED_1_LIMITS))\r
-\r
-#define ADDR_LED_1_DELAY 0x4000B908\r
-#define MMCR_LED_1_DELAY (*(VUINT32 *)(ADDR_LED_1_DELAY))\r
-\r
-#define ADDR_LED_1_UPDATE_STEPSIZE 0x4000B90C\r
-#define MMCR_LED_1_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_1_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_1_UPDATE_INTERVAL 0x4000B910\r
-#define MMCR_LED_1_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_1_UPDATE_INTERVAL))\r
-\r
-#define ADDR_LED_0_CONFIGURATION 0x4000B800\r
-#define MMCR_LED_0_CONFIGURATION (*(VUINT32 *)(ADDR_LED_0_CONFIGURATION))\r
-\r
-#define ADDR_LED_0_LIMITS 0x4000B804\r
-#define MMCR_LED_0_LIMITS (*(VUINT32 *)(ADDR_LED_0_LIMITS))\r
-\r
-#define ADDR_LED_0_DELAY 0x4000B808\r
-#define MMCR_LED_0_DELAY (*(VUINT32 *)(ADDR_LED_0_DELAY))\r
-\r
-#define ADDR_LED_0_UPDATE_STEPSIZE 0x4000B80C\r
-#define MMCR_LED_0_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_0_UPDATE_STEPSIZE))\r
-\r
-#define ADDR_LED_0_UPDATE_INTERVAL 0x4000B810\r
-#define MMCR_LED_0_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_0_UPDATE_INTERVAL))\r
-\r
-/***************************************************************\r
-* SMSC BC-Link Master\r
-***************************************************************/\r
-#define ADDR_BC_LINK_STATUS 0x4000BC00\r
-#define MMCR_BC_LINK_STATUS (*(VUINT8 *)(ADDR_BC_LINK_STATUS))\r
-\r
-#define ADDR_BC_LINK_ADDRESS 0x4000BC04\r
-#define MMCR_BC_LINK_ADDRESS (*(VUINT8 *)(ADDR_BC_LINK_ADDRESS))\r
-\r
-#define ADDR_BC_LINK_DATA 0x4000BC08\r
-#define MMCR_BC_LINK_DATA (*(VUINT8 *)(ADDR_BC_LINK_DATA))\r
-\r
-#define ADDR_BC_LINK_CLOCK_SELECT 0x4000BC0C\r
-#define MMCR_BC_LINK_CLOCK_SELECT (*(VUINT8 *)(ADDR_BC_LINK_CLOCK_SELECT))\r
-\r
-/***************************************************************\r
-* Basic Timer\r
-***************************************************************/\r
-#define ADDR_BASIC_0_TIMER_COUNT 0x40000C00\r
-#define MMCR_BASIC_0_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_0_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_0_TIMER_PRELOAD 0x40000C04\r
-#define MMCR_BASIC_0_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_0_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_0_TIMER_STATUS 0x40000C08\r
-#define MMCR_BASIC_0_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_0_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE 0x40000C0C\r
-#define MMCR_BASIC_0_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_0_TIMER_CONTROL 0x40000C10\r
-#define MMCR_BASIC_0_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_0_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_1_TIMER_COUNT 0x40000C20\r
-#define MMCR_BASIC_1_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_1_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_1_TIMER_PRELOAD 0x40000C24\r
-#define MMCR_BASIC_1_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_1_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_1_TIMER_STATUS 0x40000C28\r
-#define MMCR_BASIC_1_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_1_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE 0x40000C2C\r
-#define MMCR_BASIC_1_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_1_TIMER_CONTROL 0x40000C30\r
-#define MMCR_BASIC_1_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_1_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_2_TIMER_COUNT 0x40000C40\r
-#define MMCR_BASIC_2_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_2_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_2_TIMER_PRELOAD 0x40000C44\r
-#define MMCR_BASIC_2_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_2_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_2_TIMER_STATUS 0x40000C48\r
-#define MMCR_BASIC_2_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_2_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE 0x40000C4C\r
-#define MMCR_BASIC_2_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_2_TIMER_CONTROL 0x40000C50\r
-#define MMCR_BASIC_2_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_2_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_3_TIMER_COUNT 0x40000C60\r
-#define MMCR_BASIC_3_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_3_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_3_TIMER_PRELOAD 0x40000C64\r
-#define MMCR_BASIC_3_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_3_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_3_TIMER_STATUS 0x40000C68\r
-#define MMCR_BASIC_3_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_3_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE 0x40000C6C\r
-#define MMCR_BASIC_3_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_3_TIMER_CONTROL 0x40000C70\r
-#define MMCR_BASIC_3_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_3_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_4_TIMER_COUNT 0x40000C80\r
-#define MMCR_BASIC_4_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_4_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_4_TIMER_PRELOAD 0x40000C84\r
-#define MMCR_BASIC_4_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_4_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_4_TIMER_STATUS 0x40000C88\r
-#define MMCR_BASIC_4_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_4_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE 0x40000C8C\r
-#define MMCR_BASIC_4_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_4_TIMER_CONTROL 0x40000C90\r
-#define MMCR_BASIC_4_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_4_TIMER_CONTROL))\r
-\r
-#define ADDR_BASIC_5_TIMER_COUNT 0x40000CA0\r
-#define MMCR_BASIC_5_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_5_TIMER_COUNT))\r
-\r
-#define ADDR_BASIC_5_TIMER_PRELOAD 0x40000CA4\r
-#define MMCR_BASIC_5_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_5_TIMER_PRELOAD))\r
-\r
-#define ADDR_BASIC_5_TIMER_STATUS 0x40000CA8\r
-#define MMCR_BASIC_5_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_5_TIMER_STATUS))\r
-\r
-#define ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE 0x40000CAC\r
-#define MMCR_BASIC_5_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_BASIC_5_TIMER_CONTROL 0x40000CB0\r
-#define MMCR_BASIC_5_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_5_TIMER_CONTROL))\r
-\r
-/***************************************************************\r
-* INTS\r
-***************************************************************/\r
-#define ADDR_EC_GIRQ8_SOURCE 0x4000C000\r
-#define MMCR_EC_GIRQ8_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ8_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ8_ENABLE_SET 0x4000C004\r
-#define MMCR_EC_GIRQ8_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ8_RESULT 0x4000C008\r
-#define MMCR_EC_GIRQ8_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ8_RESULT))\r
-\r
-#define ADDR_EC_GIRQ8_ENABLE_CLEAR 0x4000C00C\r
-#define MMCR_EC_GIRQ8_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ9_SOURCE 0x4000C014\r
-#define MMCR_EC_GIRQ9_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ9_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ9_ENABLE_SET 0x4000C018\r
-#define MMCR_EC_GIRQ9_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ9_RESULT 0x4000C01C\r
-#define MMCR_EC_GIRQ9_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ9_RESULT))\r
-\r
-#define ADDR_EC_GIRQ9_ENABLE_CLEAR 0x4000C020\r
-#define MMCR_EC_GIRQ9_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ10_SOURCE 0x4000C028\r
-#define MMCR_EC_GIRQ10_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ10_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ10_ENABLE_SET 0x4000C02C\r
-#define MMCR_EC_GIRQ10_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ10_RESULT 0x4000C030\r
-#define MMCR_EC_GIRQ10_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ10_RESULT))\r
-\r
-#define ADDR_EC_GIRQ10_ENABLE_CLEAR 0x4000C034\r
-#define MMCR_EC_GIRQ10_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ11_SOURCE 0x4000C03C\r
-#define MMCR_EC_GIRQ11_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ11_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ11_ENABLE_SET 0x4000C040\r
-#define MMCR_EC_GIRQ11_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ11_RESULT 0x4000C044\r
-#define MMCR_EC_GIRQ11_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ11_RESULT))\r
-\r
-#define ADDR_EC_GIRQ11_ENABLE_CLEAR 0x4000C048\r
-#define MMCR_EC_GIRQ11_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ12_SOURCE 0x4000C050\r
-#define MMCR_EC_GIRQ12_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ12_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ12_ENABLE_SET 0x4000C054\r
-#define MMCR_EC_GIRQ12_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ12_RESULT 0x4000C058\r
-#define MMCR_EC_GIRQ12_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ12_RESULT))\r
-\r
-#define ADDR_EC_GIRQ12_ENABLE_CLEAR 0x4000C05C\r
-#define MMCR_EC_GIRQ12_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ13_SOURCE 0x4000C064\r
-#define MMCR_EC_GIRQ13_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ13_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ13_ENABLE_SET 0x4000C068\r
-#define MMCR_EC_GIRQ13_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ13_RESULT 0x4000C06C\r
-#define MMCR_EC_GIRQ13_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ13_RESULT))\r
-\r
-#define ADDR_EC_GIRQ13_ENABLE_CLEAR 0x4000C070\r
-#define MMCR_EC_GIRQ13_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ14_SOURCE 0x4000C078\r
-#define MMCR_EC_GIRQ14_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ14_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ14_ENABLE_SET 0x4000C07C\r
-#define MMCR_EC_GIRQ14_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ14_RESULT 0x4000C080\r
-#define MMCR_EC_GIRQ14_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ14_RESULT))\r
-\r
-#define ADDR_EC_GIRQ14_ENABLE_CLEAR 0x4000C084\r
-#define MMCR_EC_GIRQ14_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ15_SOURCE 0x4000C08C\r
-#define MMCR_EC_GIRQ15_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ15_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ15_ENABLE_SET 0x4000C090\r
-#define MMCR_EC_GIRQ15_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ15_RESULT 0x4000C094\r
-#define MMCR_EC_GIRQ15_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ15_RESULT))\r
-\r
-#define ADDR_EC_GIRQ15_ENABLE_CLEAR 0x4000C098\r
-#define MMCR_EC_GIRQ15_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ16_SOURCE 0x4000C0A0\r
-#define MMCR_EC_GIRQ16_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ16_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ16_ENABLE_SET 0x4000C0A4\r
-#define MMCR_EC_GIRQ16_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ16_RESULT 0x4000C0A8\r
-#define MMCR_EC_GIRQ16_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ16_RESULT))\r
-\r
-#define ADDR_EC_GIRQ16_ENABLE_CLEAR 0x4000C0AC\r
-#define MMCR_EC_GIRQ16_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ17_SOURCE 0x4000C0B4\r
-#define MMCR_EC_GIRQ17_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ17_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ17_ENABLE_SET 0x4000C0B8\r
-#define MMCR_EC_GIRQ17_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ17_RESULT 0x4000C0BC\r
-#define MMCR_EC_GIRQ17_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ17_RESULT))\r
-\r
-#define ADDR_EC_GIRQ17_ENABLE_CLEAR 0x4000C0C0\r
-#define MMCR_EC_GIRQ17_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ18_SOURCE 0x4000C0C8\r
-#define MMCR_EC_GIRQ18_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ18_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ18_ENABLE_SET 0x4000C0CC\r
-#define MMCR_EC_GIRQ18_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ18_RESULT 0x4000C0D0\r
-#define MMCR_EC_GIRQ18_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ18_RESULT))\r
-\r
-#define ADDR_EC_GIRQ18_ENABLE_CLEAR 0x4000C0D4\r
-#define MMCR_EC_GIRQ18_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ19_SOURCE 0x4000C0DC\r
-#define MMCR_EC_GIRQ19_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ19_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ19_ENABLE_SET 0x4000C0E0\r
-#define MMCR_EC_GIRQ19_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ19_RESULT 0x4000C0E4\r
-#define MMCR_EC_GIRQ19_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ19_RESULT))\r
-\r
-#define ADDR_EC_GIRQ19_ENABLE_CLEAR 0x4000C0E8\r
-#define MMCR_EC_GIRQ19_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ20_SOURCE 0x4000C0F0\r
-#define MMCR_EC_GIRQ20_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ20_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ20_ENABLE_SET 0x4000C0F4\r
-#define MMCR_EC_GIRQ20_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ20_RESULT 0x4000C0F8\r
-#define MMCR_EC_GIRQ20_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ20_RESULT))\r
-\r
-#define ADDR_EC_GIRQ20_ENABLE_CLEAR 0x4000C0FC\r
-#define MMCR_EC_GIRQ20_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ21_SOURCE 0x4000C104\r
-#define MMCR_EC_GIRQ21_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ21_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ21_ENABLE_SET 0x4000C108\r
-#define MMCR_EC_GIRQ21_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ21_RESULT 0x4000C10C\r
-#define MMCR_EC_GIRQ21_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ21_RESULT))\r
-\r
-#define ADDR_EC_GIRQ21_ENABLE_CLEAR 0x4000C110\r
-#define MMCR_EC_GIRQ21_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ22_SOURCE 0x4000C118\r
-#define MMCR_EC_GIRQ22_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ22_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ22_ENABLE_SET 0x4000C11C\r
-#define MMCR_EC_GIRQ22_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ22_RESULT 0x4000C120\r
-#define MMCR_EC_GIRQ22_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ22_RESULT))\r
-\r
-#define ADDR_EC_GIRQ22_ENABLE_CLEAR 0x4000C124\r
-#define MMCR_EC_GIRQ22_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_GIRQ23_SOURCE 0x4000C12C\r
-#define MMCR_EC_GIRQ23_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ23_SOURCE))\r
-\r
-#define ADDR_EC_GIRQ23_ENABLE_SET 0x4000C130\r
-#define MMCR_EC_GIRQ23_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_SET))\r
-\r
-#define ADDR_EC_GIRQ23_RESULT 0x4000C134\r
-#define MMCR_EC_GIRQ23_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ23_RESULT))\r
-\r
-#define ADDR_EC_GIRQ23_ENABLE_CLEAR 0x4000C138\r
-#define MMCR_EC_GIRQ23_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_BLOCK_ENABLE_SET 0x4000C200\r
-#define MMCR_EC_BLOCK_ENABLE_SET (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_SET))\r
-\r
-#define ADDR_EC_BLOCK_ENABLE_CLEAR 0x4000C204\r
-#define MMCR_EC_BLOCK_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_CLEAR))\r
-\r
-#define ADDR_EC_BLOCK_IRQ_VECTOR 0x4000C208\r
-#define MMCR_EC_BLOCK_IRQ_VECTOR (*(VUINT32 *)(ADDR_EC_BLOCK_IRQ_VECTOR))\r
-\r
-/***************************************************************\r
-* RPM Fan Control\r
-***************************************************************/\r
-#define ADDR_RPM_FAN_SETTING 0x4000A000\r
-#define MMCR_RPM_FAN_SETTING (*(VUINT8 *)(ADDR_RPM_FAN_SETTING))\r
-\r
-#define ADDR_RPM_PWM_DIVIDE 0x4000A001\r
-#define MMCR_RPM_PWM_DIVIDE (*(VUINT8 *)(ADDR_RPM_PWM_DIVIDE))\r
-\r
-#define ADDR_RPM_FAN_CONFIGURATION_1 0x4000A002\r
-#define MMCR_RPM_FAN_CONFIGURATION_1 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_1))\r
-\r
-#define ADDR_RPM_FAN_CONFIGURATION_2 0x4000A003\r
-#define MMCR_RPM_FAN_CONFIGURATION_2 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_2))\r
-\r
-#define ADDR_RPM_GAIN 0x4000A005\r
-#define MMCR_RPM_GAIN (*(VUINT8 *)(ADDR_RPM_GAIN))\r
-\r
-#define ADDR_RPM_FAN_SPIN_UP_CONFIGURATION 0x4000A006\r
-#define MMCR_RPM_FAN_SPIN_UP_CONFIGURATION (*(VUINT8 *)(ADDR_RPM_FAN_SPIN_UP_CONFIGURATION))\r
-\r
-#define ADDR_RPM_FAN_STEP 0x4000A007\r
-#define MMCR_RPM_FAN_STEP (*(VUINT8 *)(ADDR_RPM_FAN_STEP))\r
-\r
-#define ADDR_RPM_FAN_MINIMUM_DRIVE 0x4000A008\r
-#define MMCR_RPM_FAN_MINIMUM_DRIVE (*(VUINT8 *)(ADDR_RPM_FAN_MINIMUM_DRIVE))\r
-\r
-#define ADDR_RPM_VALID_TACH_COUNT 0x4000A009\r
-#define MMCR_RPM_VALID_TACH_COUNT (*(VUINT8 *)(ADDR_RPM_VALID_TACH_COUNT))\r
-\r
-#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE 0x4000A00A\r
-#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE))\r
-\r
-#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE 0x4000A00B\r
-#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE))\r
-\r
-#define ADDR_RPM_TACH_TARGET_LOW_BYTE 0x4000A00C\r
-#define MMCR_RPM_TACH_TARGET_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_LOW_BYTE))\r
-\r
-#define ADDR_RPM_TACH_TARGET_HIGH_BYTE 0x4000A00D\r
-#define MMCR_RPM_TACH_TARGET_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_HIGH_BYTE))\r
-\r
-#define ADDR_RPM_TACH_READING_LOW_BYTE 0x4000A00E\r
-#define MMCR_RPM_TACH_READING_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_LOW_BYTE))\r
-\r
-#define ADDR_RPM_TACH_READING_HIGH_BYTE 0x4000A00F\r
-#define MMCR_RPM_TACH_READING_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_HIGH_BYTE))\r
-\r
-#define ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY 0x4000A010\r
-#define MMCR_RPM_PWM_DRIVER_BASE_FREQUENCY (*(VUINT8 *)(ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY))\r
-\r
-#define ADDR_RPM_FAN_STATUS 0x4000A011\r
-#define MMCR_RPM_FAN_STATUS (*(VUINT8 *)(ADDR_RPM_FAN_STATUS))\r
-\r
-#define ADDR_RPM_FAN_TEST 0x4000A014\r
-#define MMCR_RPM_FAN_TEST (*(VUINT8 *)(ADDR_RPM_FAN_TEST))\r
-\r
-#define ADDR_RPM_FAN_TEST1 0x4000A015\r
-#define MMCR_RPM_FAN_TEST1 (*(VUINT8 *)(ADDR_RPM_FAN_TEST1))\r
-\r
-#define ADDR_RPM_FAN_TEST2 0x4000A016\r
-#define MMCR_RPM_FAN_TEST2 (*(VUINT8 *)(ADDR_RPM_FAN_TEST2))\r
-\r
-#define ADDR_RPM_FAN_TEST3 0x4000A017\r
-#define MMCR_RPM_FAN_TEST3 (*(VUINT8 *)(ADDR_RPM_FAN_TEST3))\r
-\r
-/***************************************************************\r
-* V2P (HP ckt#1) 32bit_aligned\r
-***************************************************************/\r
-#define ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY 0x40007C80\r
-#define MMCR_V2P_ADC2PWM_OUTPUT_FREQUENCY (*(VUINT32 *)(ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY))\r
-\r
-#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW 0x40007C84\r
-#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW))\r
-\r
-#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH 0x40007C88\r
-#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH))\r
-\r
-#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA 0x40007C8C\r
-#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA))\r
-\r
-#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS 0x40007C90\r
-#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_STATUS (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS))\r
-\r
-#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 0x40007C94\r
-#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1))\r
-\r
-#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 0x40007C98\r
-#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2))\r
-\r
-#define ADDR_V2P_ADC2PWM_CONTROL 0x40007C9C\r
-#define MMCR_V2P_ADC2PWM_CONTROL (*(VUINT32 *)(ADDR_V2P_ADC2PWM_CONTROL))\r
-\r
-#define ADDR_V2P_LPF_CUT_OFF_FREQUENCY 0x40007CA0\r
-#define MMCR_V2P_LPF_CUT_OFF_FREQUENCY (*(VUINT32 *)(ADDR_V2P_LPF_CUT_OFF_FREQUENCY))\r
-\r
-#define ADDR_V2P_TEST 0x40007CA4\r
-#define MMCR_V2P_TEST (*(VUINT32 *)(ADDR_V2P_TEST))\r
-\r
-#define ADDR_V2P_NOTICE_DATA 0x40007CA8\r
-#define MMCR_V2P_NOTICE_DATA (*(VUINT32 *)(ADDR_V2P_NOTICE_DATA))\r
-\r
-#define ADDR_V2P_TEST_DATA 0x40007CAC\r
-#define MMCR_V2P_TEST_DATA (*(VUINT32 *)(ADDR_V2P_TEST_DATA))\r
-\r
-#define ADDR_V2P_COUNTER_START 0x40007CB0\r
-#define MMCR_V2P_COUNTER_START (*(VUINT32 *)(ADDR_V2P_COUNTER_START))\r
-\r
-#define ADDR_V2P_HYSTERESIS 0x40007CB4\r
-#define MMCR_V2P_HYSTERESIS (*(VUINT32 *)(ADDR_V2P_HYSTERESIS))\r
-\r
-#define ADDR_V2P_BIAS 0x40007CB8\r
-#define MMCR_V2P_BIAS (*(VUINT32 *)(ADDR_V2P_BIAS))\r
-\r
-#define ADDR_V2P_INTERRUPT_CONTROL 0x40007CBC\r
-#define MMCR_V2P_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_V2P_INTERRUPT_CONTROL))\r
-\r
-/***************************************************************\r
-* VBAT_REGS (1322)\r
-***************************************************************/\r
-#define ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS 0x4000A400\r
-#define MMCR_VBAT_POWER_FAIL_AND_RESET_STATUS (*(VUINT8 *)(ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS))\r
-\r
-#define ADDR_VBAT_CONTROL 0x4000A404\r
-#define MMCR_VBAT_CONTROL (*(VUINT8 *)(ADDR_VBAT_CONTROL))\r
-\r
-#define ADDR_VBAT_CLOCK_ENABLE 0x4000A408\r
-#define MMCR_VBAT_CLOCK_ENABLE (*(VUINT8 *)(ADDR_VBAT_CLOCK_ENABLE))\r
-\r
-/***************************************************************\r
-* EC_REG_BANK (1322)\r
-***************************************************************/\r
-#define ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS 0x4000FC04\r
-#define MMCR_EC_REG_BANK_AHB_ERROR_ADDRESS (*(VUINT32 *)(ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS))\r
-\r
-#define ADDR_EC_REG_BANK_INPUT_MUX0 0x4000FC08\r
-#define MMCR_EC_REG_BANK_INPUT_MUX0 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX0))\r
-\r
-#define ADDR_EC_REG_BANK_INPUT_MUX1 0x4000FC0C\r
-#define MMCR_EC_REG_BANK_INPUT_MUX1 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX1))\r
-\r
-#define ADDR_EC_REG_BANK_ID 0x4000FC10\r
-#define MMCR_EC_REG_BANK_ID (*(VUINT8 *)(ADDR_EC_REG_BANK_ID))\r
-\r
-#define ADDR_EC_REG_BANK_AHB_ERROR_CONTROL 0x4000FC14\r
-#define MMCR_EC_REG_BANK_AHB_ERROR_CONTROL (*(VUINT8 *)(ADDR_EC_REG_BANK_AHB_ERROR_CONTROL))\r
-\r
-#define ADDR_EC_REG_BANK_INTERRUPT_CONTROL 0x4000FC18\r
-#define MMCR_EC_REG_BANK_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_INTERRUPT_CONTROL))\r
-\r
-#define ADDR_EC_REG_BANK_ETM_TRACE 0x4000FC1C\r
-#define MMCR_EC_REG_BANK_ETM_TRACE (*(VUINT32 *)(ADDR_EC_REG_BANK_ETM_TRACE))\r
-\r
-#define ADDR_EC_REG_BANK_JTAG_ENABLE 0x4000FC20\r
-#define MMCR_EC_REG_BANK_JTAG_ENABLE (*(VUINT32 *)(ADDR_EC_REG_BANK_JTAG_ENABLE))\r
-\r
-#define ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK 0x4000FC24\r
-#define MMCR_EC_REG_BANK_PRIVATE_KEY_LOCK (*(VUINT32 *)(ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK))\r
-\r
-#define ADDR_EC_REG_BANK_WDT_COUNT 0x4000FC28\r
-#define MMCR_EC_REG_BANK_WDT_COUNT (*(VUINT32 *)(ADDR_EC_REG_BANK_WDT_COUNT))\r
-\r
-#define ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL 0x4000FC2C\r
-#define MMCR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL))\r
-\r
-#define ADDR_EC_REG_BANK_ADC_VREF_TRIM 0x4000FC30\r
-#define MMCR_EC_REG_BANK_ADC_VREF_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_TRIM))\r
-\r
-#define ADDR_EC_REG_BANK_REGULATOR_TRIM 0x4000FC34\r
-#define MMCR_EC_REG_BANK_REGULATOR_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_REGULATOR_TRIM))\r
-\r
-#define ADDR_EC_REG_BANK_ADC_VREF_PD 0x4000FC38\r
-#define MMCR_EC_REG_BANK_ADC_VREF_PD (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_PD))\r
-\r
-#define ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST 0x4000FC3C\r
-#define MMCR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST))\r
-\r
-#define ADDR_EC_REG_BANK_MISC_TRIM 0x4000FC40\r
-#define MMCR_EC_REG_BANK_MISC_TRIM (*(VUINT8 *)(ADDR_EC_REG_BANK_MISC_TRIM))\r
-\r
-/***************************************************************\r
-* PCR\r
-***************************************************************/\r
-#define ADDR_PCR_CHIP_SLEEP_ENABLE 0x40080100\r
-#define MMCR_PCR_CHIP_SLEEP_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_SLEEP_ENABLE))\r
-\r
-#define ADDR_PCR_CHIP_CLOCK_REQUIRED 0x40080104\r
-#define MMCR_PCR_CHIP_CLOCK_REQUIRED (*(VUINT32 *)(ADDR_PCR_CHIP_CLOCK_REQUIRED))\r
-\r
-#define ADDR_PCR_EC_SLEEP_ENABLES 0x40080108\r
-#define MMCR_PCR_EC_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLES))\r
-\r
-#define ADDR_PCR_EC_CLOCK_REQUIRED_STATUS 0x4008010C\r
-#define MMCR_PCR_EC_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_STATUS))\r
-\r
-#define ADDR_PCR_HOST_SLEEP_ENABLES 0x40080110\r
-#define MMCR_PCR_HOST_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_HOST_SLEEP_ENABLES))\r
-\r
-#define ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS 0x40080114\r
-#define MMCR_PCR_HOST_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS))\r
-\r
-#define ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 0x40080118\r
-#define MMCR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 (*(VUINT32 *)(ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0))\r
-\r
-#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120\r
-#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))\r
-\r
-#define ADDR_PCR_EC_SLEEP_ENABLE_2 0x40080124\r
-#define MMCR_PCR_EC_SLEEP_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLE_2))\r
-\r
-#define ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS 0x40080128\r
-#define MMCR_PCR_EC_CLOCK_REQUIRED_2_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS))\r
-\r
-#define ADDR_PCR_SLOW_CLOCK_CONTROL 0x4008012C\r
-#define MMCR_PCR_SLOW_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_SLOW_CLOCK_CONTROL))\r
-\r
-#define ADDR_PCR_OSCILLATOR_ID 0x40080130\r
-#define MMCR_PCR_OSCILLATOR_ID (*(VUINT32 *)(ADDR_PCR_OSCILLATOR_ID))\r
-\r
-#define ADDR_PCR_CHIP_RESET_ENABLE 0x40080138\r
-#define MMCR_PCR_CHIP_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_RESET_ENABLE))\r
-\r
-#define ADDR_PCR_HOST_RESET_ENABLE 0x4008013C\r
-#define MMCR_PCR_HOST_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_HOST_RESET_ENABLE))\r
-\r
-#define ADDR_PCR_EC_RESET_ENABLE 0x40080140\r
-#define MMCR_PCR_EC_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE))\r
-\r
-#define ADDR_PCR_EC_RESET_ENABLE_2 0x40080144\r
-#define MMCR_PCR_EC_RESET_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE_2))\r
-\r
-#define ADDR_PCR_CLOCK_RESET_CONTROL 0x40080148\r
-#define MMCR_PCR_CLOCK_RESET_CONTROL (*(VUINT32 *)(ADDR_PCR_CLOCK_RESET_CONTROL))\r
-\r
-/***************************************************************\r
-* Public Key Crypto Engine\r
-***************************************************************/\r
-#define ADDR_PUBLIC_PK_CONFIGREG 0x4000BD00\r
-#define MMCR_PUBLIC_PK_CONFIGREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONFIGREG))\r
-\r
-#define ADDR_PUBLIC_PK_COMMANDREG 0x4000BD04\r
-#define MMCR_PUBLIC_PK_COMMANDREG (*(VUINT32 *)(ADDR_PUBLIC_PK_COMMANDREG))\r
-\r
-#define ADDR_PUBLIC_PK_CONTROLREG 0x4000BD08\r
-#define MMCR_PUBLIC_PK_CONTROLREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONTROLREG))\r
-\r
-#define ADDR_PUBLIC_PK_STATUSREG 0x4000BD0C\r
-#define MMCR_PUBLIC_PK_STATUSREG (*(VUINT32 *)(ADDR_PUBLIC_PK_STATUSREG))\r
-\r
-#define ADDR_PUBLIC_PK_VERSIONREG 0x4000BD10\r
-#define MMCR_PUBLIC_PK_VERSIONREG (*(VUINT32 *)(ADDR_PUBLIC_PK_VERSIONREG))\r
-\r
-#define ADDR_PUBLIC_PK_LOADMICROCODEREG 0x4000BD14\r
-#define MMCR_PUBLIC_PK_LOADMICROCODEREG (*(VUINT32 *)(ADDR_PUBLIC_PK_LOADMICROCODEREG))\r
-\r
-/***************************************************************\r
-* Non Deterministic Random Number Generator\r
-***************************************************************/\r
-#define ADDR_NON_CONTROLREG 0x4000BE00\r
-#define MMCR_NON_CONTROLREG (*(VUINT32 *)(ADDR_NON_CONTROLREG))\r
-\r
-#define ADDR_NON_FIFOLEVELREG 0x4000BE04\r
-#define MMCR_NON_FIFOLEVELREG (*(VUINT32 *)(ADDR_NON_FIFOLEVELREG))\r
-\r
-#define ADDR_NON_VERSIONREG 0x4000BE08\r
-#define MMCR_NON_VERSIONREG (*(VUINT32 *)(ADDR_NON_VERSIONREG))\r
-\r
-/***************************************************************\r
-* RTC\r
-***************************************************************/\r
-#define ADDR_RTC_SECONDS 0x400F2800\r
-#define MMCR_RTC_SECONDS (*(VUINT8 *)(ADDR_RTC_SECONDS))\r
-\r
-#define ADDR_RTC_SECONDS_ALARM 0x400F2801\r
-#define MMCR_RTC_SECONDS_ALARM (*(VUINT8 *)(ADDR_RTC_SECONDS_ALARM))\r
-\r
-#define ADDR_RTC_MINUTES 0x400F2802\r
-#define MMCR_RTC_MINUTES (*(VUINT8 *)(ADDR_RTC_MINUTES))\r
-\r
-#define ADDR_RTC_MINUTES_ALARM 0x400F2803\r
-#define MMCR_RTC_MINUTES_ALARM (*(VUINT8 *)(ADDR_RTC_MINUTES_ALARM))\r
-\r
-#define ADDR_RTC_HOURS 0x400F2804\r
-#define MMCR_RTC_HOURS (*(VUINT8 *)(ADDR_RTC_HOURS))\r
-\r
-#define ADDR_RTC_HOURS_ALARM 0x400F2805\r
-#define MMCR_RTC_HOURS_ALARM (*(VUINT8 *)(ADDR_RTC_HOURS_ALARM))\r
-\r
-#define ADDR_RTC_DAY_OF_WEEK 0x400F2806\r
-#define MMCR_RTC_DAY_OF_WEEK (*(VUINT8 *)(ADDR_RTC_DAY_OF_WEEK))\r
-\r
-#define ADDR_RTC_DAY_OF_MONTH 0x400F2807\r
-#define MMCR_RTC_DAY_OF_MONTH (*(VUINT8 *)(ADDR_RTC_DAY_OF_MONTH))\r
-\r
-#define ADDR_RTC_MONTH 0x400F2808\r
-#define MMCR_RTC_MONTH (*(VUINT8 *)(ADDR_RTC_MONTH))\r
-\r
-#define ADDR_RTC_YEAR 0x400F2809\r
-#define MMCR_RTC_YEAR (*(VUINT8 *)(ADDR_RTC_YEAR))\r
-\r
-#define ADDR_RTC_A 0x400F280A\r
-#define MMCR_RTC_A (*(VUINT8 *)(ADDR_RTC_A))\r
-\r
-#define ADDR_RTC_B 0x400F280B\r
-#define MMCR_RTC_B (*(VUINT8 *)(ADDR_RTC_B))\r
-\r
-#define ADDR_RTC_C 0x400F280C\r
-#define MMCR_RTC_C (*(VUINT8 *)(ADDR_RTC_C))\r
-\r
-#define ADDR_RTC_D 0x400F280D\r
-#define MMCR_RTC_D (*(VUINT8 *)(ADDR_RTC_D))\r
-\r
-#define ADDR_RTC_CONTROL 0x400F2810\r
-#define MMCR_RTC_CONTROL (*(VUINT8 *)(ADDR_RTC_CONTROL))\r
-\r
-#define ADDR_RTC_WEEK_ALARM 0x400F2814\r
-#define MMCR_RTC_WEEK_ALARM (*(VUINT8 *)(ADDR_RTC_WEEK_ALARM))\r
-\r
-#define ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD 0x400F2818\r
-#define MMCR_RTC_DAYLIGHT_SAVINGS_FORWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD))\r
-\r
-#define ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD 0x400F281C\r
-#define MMCR_RTC_DAYLIGHT_SAVINGS_BACKWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD))\r
-\r
-#define ADDR_RTC_TEST_MODE 0x400F2820\r
-#define MMCR_RTC_TEST_MODE (*(VUINT8 *)(ADDR_RTC_TEST_MODE))\r
-\r
-/***************************************************************\r
-* Analog to Digital Converter (ADC)\r
-***************************************************************/\r
-#define ADDR_ADC_CONTROL 0x40007C00\r
-#define MMCR_ADC_CONTROL (*(VUINT32 *)(ADDR_ADC_CONTROL))\r
-\r
-#define ADDR_ADC_DELAY 0x40007C04\r
-#define MMCR_ADC_DELAY (*(VUINT32 *)(ADDR_ADC_DELAY))\r
-\r
-#define ADDR_ADC_STATUS 0x40007C08\r
-#define MMCR_ADC_STATUS (*(VUINT32 *)(ADDR_ADC_STATUS))\r
-\r
-#define ADDR_ADC_SINGLE 0x40007C0C\r
-#define MMCR_ADC_SINGLE (*(VUINT32 *)(ADDR_ADC_SINGLE))\r
-\r
-#define ADDR_ADC_REPEAT 0x40007C10\r
-#define MMCR_ADC_REPEAT (*(VUINT32 *)(ADDR_ADC_REPEAT))\r
-\r
-#define ADDR_ADC_CHANNEL_0_READINGS 0x40007C14\r
-#define MMCR_ADC_CHANNEL_0_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_0_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_1_READINGS 0x40007C18\r
-#define MMCR_ADC_CHANNEL_1_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_1_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_2_READINGS 0x40007C1C\r
-#define MMCR_ADC_CHANNEL_2_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_2_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_3_READINGS 0x40007C20\r
-#define MMCR_ADC_CHANNEL_3_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_3_READINGS))\r
-\r
-#define ADDR_ADC_CHANNEL_4_READINGS 0x40007C24\r
-#define MMCR_ADC_CHANNEL_4_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_4_READINGS))\r
-\r
-#define ADDR_ADC_DEBUG_FPGA_TEST_MODE 0x40007C54\r
-#define MMCR_ADC_DEBUG_FPGA_TEST_MODE (*(VUINT32 *)(ADDR_ADC_DEBUG_FPGA_TEST_MODE))\r
-\r
-#define ADDR_ADC_TEST 0x40007C78\r
-#define MMCR_ADC_TEST (*(VUINT32 *)(ADDR_ADC_TEST))\r
-\r
-#define ADDR_ADC_CONFIGURATION 0x40007C7C\r
-#define MMCR_ADC_CONFIGURATION (*(VUINT32 *)(ADDR_ADC_CONFIGURATION))\r
-\r
-/***************************************************************\r
-* eFUSE\r
-***************************************************************/\r
-#define ADDR_EFUSE_CONTROL 0x40082000\r
-#define MMCR_EFUSE_CONTROL (*(VUINT8 *)(ADDR_EFUSE_CONTROL))\r
-\r
-#define ADDR_EFUSE_MANUAL_CONTROL 0x40082004\r
-#define MMCR_EFUSE_MANUAL_CONTROL (*(VUINT8 *)(ADDR_EFUSE_MANUAL_CONTROL))\r
-\r
-#define ADDR_EFUSE_MANUAL_MODE_ADDRESS 0x40082006\r
-#define MMCR_EFUSE_MANUAL_MODE_ADDRESS (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_ADDRESS))\r
-\r
-#define ADDR_EFUSE_MANUAL_MODE_DATA 0x4008200C\r
-#define MMCR_EFUSE_MANUAL_MODE_DATA (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_DATA))\r
-\r
-/***************************************************************\r
-* AES Crypto Engine & Hash Function\r
-***************************************************************/\r
-#define ADDR_AES_CONFIGREG 0x4000D200\r
-#define MMCR_AES_CONFIGREG (*(VUINT32 *)(ADDR_AES_CONFIGREG))\r
-\r
-#define ADDR_AES_COMMANDREG 0x4000D204\r
-#define MMCR_AES_COMMANDREG (*(VUINT32 *)(ADDR_AES_COMMANDREG))\r
-\r
-#define ADDR_AES_CONTROLREG 0x4000D208\r
-#define MMCR_AES_CONTROLREG (*(VUINT32 *)(ADDR_AES_CONTROLREG))\r
-\r
-#define ADDR_AES_STATUSREG 0x4000D20C\r
-#define MMCR_AES_STATUSREG (*(VUINT32 *)(ADDR_AES_STATUSREG))\r
-\r
-#define ADDR_AES_VERSIONREG 0x4000D210\r
-#define MMCR_AES_VERSIONREG (*(VUINT32 *)(ADDR_AES_VERSIONREG))\r
-\r
-#define ADDR_AES_NBHEADERREG 0x4000D214\r
-#define MMCR_AES_NBHEADERREG (*(VUINT32 *)(ADDR_AES_NBHEADERREG))\r
-\r
-#define ADDR_AES_LASTHEADERREG 0x4000D218\r
-#define MMCR_AES_LASTHEADERREG (*(VUINT32 *)(ADDR_AES_LASTHEADERREG))\r
-\r
-#define ADDR_AES_NBBLOCKREG 0x4000D21C\r
-#define MMCR_AES_NBBLOCKREG (*(VUINT32 *)(ADDR_AES_NBBLOCKREG))\r
-\r
-#define ADDR_AES_LASTBLOCKREG 0x4000D220\r
-#define MMCR_AES_LASTBLOCKREG (*(VUINT32 *)(ADDR_AES_LASTBLOCKREG))\r
-\r
-#define ADDR_AES_DMAINREG 0x4000D224\r
-#define MMCR_AES_DMAINREG (*(VUINT32 *)(ADDR_AES_DMAINREG))\r
-\r
-#define ADDR_AES_DMAOUTREG 0x4000D228\r
-#define MMCR_AES_DMAOUTREG (*(VUINT32 *)(ADDR_AES_DMAOUTREG))\r
-\r
-#define ADDR_AES_SHAMODE_REGISTER 0x4000D000\r
-#define MMCR_AES_SHAMODE_REGISTER (*(VUINT32 *)(ADDR_AES_SHAMODE_REGISTER))\r
-\r
-#define ADDR_AES_NBBLOCK_REGISTER 0x4000D004\r
-#define MMCR_AES_NBBLOCK_REGISTER (*(VUINT32 *)(ADDR_AES_NBBLOCK_REGISTER))\r
-\r
-#define ADDR_AES_CONTROL 0x4000D008\r
-#define MMCR_AES_CONTROL (*(VUINT32 *)(ADDR_AES_CONTROL))\r
-\r
-#define ADDR_AES_STATUS 0x4000D00C\r
-#define MMCR_AES_STATUS (*(VUINT32 *)(ADDR_AES_STATUS))\r
-\r
-#define ADDR_AES_VERSION 0x4000D010\r
-#define MMCR_AES_VERSION (*(VUINT32 *)(ADDR_AES_VERSION))\r
-\r
-#define ADDR_AES_GENERICVALUE_REGISTER 0x4000D014\r
-#define MMCR_AES_GENERICVALUE_REGISTER (*(VUINT32 *)(ADDR_AES_GENERICVALUE_REGISTER))\r
-\r
-#define ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS 0x4000D018\r
-#define MMCR_AES_INITIAL_HASH_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS))\r
-\r
-#define ADDR_AES_DATA_SOURCE_ADDRESS 0x4000D01C\r
-#define MMCR_AES_DATA_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_DATA_SOURCE_ADDRESS))\r
-\r
-#define ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS 0x4000D020\r
-#define MMCR_AES_HASH_RESULT_DESTINATION_ADDRESS (*(VUINT32 *)(ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS))\r
-\r
-/***************************************************************\r
-* LPC\r
-***************************************************************/\r
-#define ADDR_LPC_ACTIVATE 0x400F3330\r
-#define MMCR_LPC_ACTIVATE (*(VUINT8 *)(ADDR_LPC_ACTIVATE))\r
-\r
-#define ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION 0x400F3340\r
-#define MMCR_LPC_SIRQ0_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION 0x400F3341\r
-#define MMCR_LPC_SIRQ1_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION 0x400F3342\r
-#define MMCR_LPC_SIRQ2_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION 0x400F3343\r
-#define MMCR_LPC_SIRQ3_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION 0x400F3344\r
-#define MMCR_LPC_SIRQ4_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION 0x400F3345\r
-#define MMCR_LPC_SIRQ5_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION 0x400F3346\r
-#define MMCR_LPC_SIRQ6_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION 0x400F3347\r
-#define MMCR_LPC_SIRQ7_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION 0x400F3348\r
-#define MMCR_LPC_SIRQ8_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION 0x400F3349\r
-#define MMCR_LPC_SIRQ9_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION 0x400F334A\r
-#define MMCR_LPC_SIRQ10_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION 0x400F334B\r
-#define MMCR_LPC_SIRQ11_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION 0x400F334C\r
-#define MMCR_LPC_SIRQ12_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION 0x400F334D\r
-#define MMCR_LPC_SIRQ13_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION 0x400F334E\r
-#define MMCR_LPC_SIRQ14_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION 0x400F334F\r
-#define MMCR_LPC_SIRQ15_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION))\r
-\r
-#define ADDR_LPC_INTERFACE_BAR 0x400F3360\r
-#define MMCR_LPC_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_EM_INTERFACE_0_BAR 0x400F3364\r
-#define MMCR_LPC_EM_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_EM_INTERFACE_0_BAR))\r
-\r
-#define ADDR_LPC_UART_0_BAR 0x400F3368\r
-#define MMCR_LPC_UART_0_BAR (*(VUINT32 *)(ADDR_LPC_UART_0_BAR))\r
-\r
-#define ADDR_LPC_KEYBOARD_CONTROLLER_BAR 0x400F3378\r
-#define MMCR_LPC_KEYBOARD_CONTROLLER_BAR (*(VUINT32 *)(ADDR_LPC_KEYBOARD_CONTROLLER_BAR))\r
-\r
-#define ADDR_LPC_ACPI_EC_INTERFACE_0_BAR 0x400F3388\r
-#define MMCR_LPC_ACPI_EC_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_0_BAR))\r
-\r
-#define ADDR_LPC_ACPI_EC_INTERFACE_1_BAR 0x400F338C\r
-#define MMCR_LPC_ACPI_EC_INTERFACE_1_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_1_BAR))\r
-\r
-#define ADDR_LPC_ACPI_PM1_INTERFACE_BAR 0x400F3390\r
-#define MMCR_LPC_ACPI_PM1_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_PM1_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR 0x400F3394\r
-#define MMCR_LPC_LEGACY_GATEA20_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_MAILBOXS_INTERFACE_BAR 0x400F3398\r
-#define MMCR_LPC_MAILBOXS_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_MAILBOXS_INTERFACE_BAR))\r
-\r
-#define ADDR_LPC_BUS_MONITOR 0x400F3104\r
-#define MMCR_LPC_BUS_MONITOR (*(VUINT32 *)(ADDR_LPC_BUS_MONITOR))\r
-\r
-#define ADDR_LPC_HOST_BUS_ERROR 0x400F3108\r
-#define MMCR_LPC_HOST_BUS_ERROR (*(VUINT32 *)(ADDR_LPC_HOST_BUS_ERROR))\r
-\r
-#define ADDR_LPC_EC_SERIRQ 0x400F310C\r
-#define MMCR_LPC_EC_SERIRQ (*(VUINT32 *)(ADDR_LPC_EC_SERIRQ))\r
-\r
-#define ADDR_LPC_EC_CLOCK_CONTROL 0x400F3110\r
-#define MMCR_LPC_EC_CLOCK_CONTROL (*(VUINT32 *)(ADDR_LPC_EC_CLOCK_CONTROL))\r
-\r
-#define ADDR_LPC_BAR_INHIBIT 0x400F3120\r
-#define MMCR_LPC_BAR_INHIBIT (*(VUINT32 *)(ADDR_LPC_BAR_INHIBIT))\r
-\r
-#define ADDR_LPC_BAR_INIT 0x400F3130\r
-#define MMCR_LPC_BAR_INIT (*(VUINT16 *)(ADDR_LPC_BAR_INIT))\r
-\r
-#define ADDR_LPC_MEMORY_HOST_CONFIGURATION 0x400F31FC\r
-#define MMCR_LPC_MEMORY_HOST_CONFIGURATION (*(VUINT32 *)(ADDR_LPC_MEMORY_HOST_CONFIGURATION))\r
-\r
-/***************************************************************\r
-* GPIO\r
-***************************************************************/\r
-#define ADDR_GPIO000_PIN_CONTROL 0x40081000\r
-#define MMCR_GPIO000_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO001_PIN_CONTROL 0x40081004\r
-#define MMCR_GPIO001_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO002_PIN_CONTROL 0x40081008\r
-#define MMCR_GPIO002_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO003_PIN_CONTROL 0x4008100C\r
-#define MMCR_GPIO003_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO004_PIN_CONTROL 0x40081010\r
-#define MMCR_GPIO004_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO005_PIN_CONTROL 0x40081014\r
-#define MMCR_GPIO005_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO006_PIN_CONTROL 0x40081018\r
-#define MMCR_GPIO006_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO007_PIN_CONTROL 0x4008101C\r
-#define MMCR_GPIO007_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO010_PIN_CONTROL 0x40081020\r
-#define MMCR_GPIO010_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO011_PIN_CONTROL 0x40081024\r
-#define MMCR_GPIO011_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO012_PIN_CONTROL 0x40081028\r
-#define MMCR_GPIO012_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO013_PIN_CONTROL 0x4008102C\r
-#define MMCR_GPIO013_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO014_PIN_CONTROL 0x40081030\r
-#define MMCR_GPIO014_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO015_PIN_CONTROL 0x40081034\r
-#define MMCR_GPIO015_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO016_PIN_CONTROL 0x40081038\r
-#define MMCR_GPIO016_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO017_PIN_CONTROL 0x4008103C\r
-#define MMCR_GPIO017_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO020_PIN_CONTROL 0x40081040\r
-#define MMCR_GPIO020_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO021_PIN_CONTROL 0x40081044\r
-#define MMCR_GPIO021_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO022_PIN_CONTROL 0x40081048\r
-#define MMCR_GPIO022_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO023_PIN_CONTROL 0x4008104C\r
-#define MMCR_GPIO023_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO024_PIN_CONTROL 0x40081050\r
-#define MMCR_GPIO024_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO025_PIN_CONTROL 0x40081054\r
-#define MMCR_GPIO025_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO026_PIN_CONTROL 0x40081058\r
-#define MMCR_GPIO026_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO027_PIN_CONTROL 0x4008105C\r
-#define MMCR_GPIO027_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO030_PIN_CONTROL 0x40081060\r
-#define MMCR_GPIO030_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO031_PIN_CONTROL 0x40081064\r
-#define MMCR_GPIO031_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO032_PIN_CONTROL 0x40081068\r
-#define MMCR_GPIO032_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO033_PIN_CONTROL 0x4008106C\r
-#define MMCR_GPIO033_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO034_PIN_CONTROL 0x40081070\r
-#define MMCR_GPIO034_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO035_PIN_CONTROL 0x40081074\r
-#define MMCR_GPIO035_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO036_PIN_CONTROL 0x40081078\r
-#define MMCR_GPIO036_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO040_PIN_CONTROL 0x40081080\r
-#define MMCR_GPIO040_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO041_PIN_CONTROL 0x40081084\r
-#define MMCR_GPIO041_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO042_PIN_CONTROL 0x40081088\r
-#define MMCR_GPIO042_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO043_PIN_CONTROL 0x4008108C\r
-#define MMCR_GPIO043_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO044_PIN_CONTROL 0x40081090\r
-#define MMCR_GPIO044_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO045_PIN_CONTROL 0x40081094\r
-#define MMCR_GPIO045_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO046_PIN_CONTROL 0x40081098\r
-#define MMCR_GPIO046_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO047_PIN_CONTROL 0x4008109C\r
-#define MMCR_GPIO047_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO050_PIN_CONTROL 0x400810A0\r
-#define MMCR_GPIO050_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO051_PIN_CONTROL 0x400810A4\r
-#define MMCR_GPIO051_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO052_PIN_CONTROL 0x400810A8\r
-#define MMCR_GPIO052_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO053_PIN_CONTROL 0x400810AC\r
-#define MMCR_GPIO053_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO054_PIN_CONTROL 0x400810B0\r
-#define MMCR_GPIO054_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO055_PIN_CONTROL 0x400810B4\r
-#define MMCR_GPIO055_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO056_PIN_CONTROL 0x400810B8\r
-#define MMCR_GPIO056_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO057_PIN_CONTROL 0x400810BC\r
-#define MMCR_GPIO057_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO060_PIN_CONTROL 0x400810C0\r
-#define MMCR_GPIO060_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO061_PIN_CONTROL 0x400810C4\r
-#define MMCR_GPIO061_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO062_PIN_CONTROL 0x400810C8\r
-#define MMCR_GPIO062_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO063_PIN_CONTROL 0x400810CC\r
-#define MMCR_GPIO063_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO064_PIN_CONTROL 0x400810D0\r
-#define MMCR_GPIO064_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO065_PIN_CONTROL 0x400810D4\r
-#define MMCR_GPIO065_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO066_PIN_CONTROL 0x400810D8\r
-#define MMCR_GPIO066_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO067_PIN_CONTROL 0x400810DC\r
-#define MMCR_GPIO067_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO100_PIN_CONTROL 0x40081100\r
-#define MMCR_GPIO100_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO101_PIN_CONTROL 0x40081104\r
-#define MMCR_GPIO101_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO102_PIN_CONTROL 0x40081108\r
-#define MMCR_GPIO102_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO103_PIN_CONTROL 0x4008110C\r
-#define MMCR_GPIO103_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO104_PIN_CONTROL 0x40081110\r
-#define MMCR_GPIO104_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO105_PIN_CONTROL 0x40081114\r
-#define MMCR_GPIO105_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO106_PIN_CONTROL 0x40081118\r
-#define MMCR_GPIO106_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO107_PIN_CONTROL 0x4008111C\r
-#define MMCR_GPIO107_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO110_PIN_CONTROL 0x40081120\r
-#define MMCR_GPIO110_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO111_PIN_CONTROL 0x40081124\r
-#define MMCR_GPIO111_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO112_PIN_CONTROL 0x40081128\r
-#define MMCR_GPIO112_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO113_PIN_CONTROL 0x4008112C\r
-#define MMCR_GPIO113_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO114_PIN_CONTROL 0x40081130\r
-#define MMCR_GPIO114_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO115_PIN_CONTROL 0x40081134\r
-#define MMCR_GPIO115_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO116_PIN_CONTROL 0x40081138\r
-#define MMCR_GPIO116_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO117_PIN_CONTROL 0x4008113C\r
-#define MMCR_GPIO117_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO120_PIN_CONTROL 0x40081140\r
-#define MMCR_GPIO120_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO121_PIN_CONTROL 0x40081144\r
-#define MMCR_GPIO121_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO122_PIN_CONTROL 0x40081148\r
-#define MMCR_GPIO122_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO123_PIN_CONTROL 0x4008114C\r
-#define MMCR_GPIO123_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO124_PIN_CONTROL 0x40081150\r
-#define MMCR_GPIO124_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO125_PIN_CONTROL 0x40081154\r
-#define MMCR_GPIO125_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO126_PIN_CONTROL 0x40081158\r
-#define MMCR_GPIO126_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO127_PIN_CONTROL 0x4008115C\r
-#define MMCR_GPIO127_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO130_PIN_CONTROL 0x40081160\r
-#define MMCR_GPIO130_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO131_PIN_CONTROL 0x40081164\r
-#define MMCR_GPIO131_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO132_PIN_CONTROL 0x40081168\r
-#define MMCR_GPIO132_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO133_PIN_CONTROL 0x4008116C\r
-#define MMCR_GPIO133_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO134_PIN_CONTROL 0x40081170\r
-#define MMCR_GPIO134_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO135_PIN_CONTROL 0x40081174\r
-#define MMCR_GPIO135_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO136_PIN_CONTROL 0x40081178\r
-#define MMCR_GPIO136_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO140_PIN_CONTROL 0x40081180\r
-#define MMCR_GPIO140_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO141_PIN_CONTROL 0x40081184\r
-#define MMCR_GPIO141_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO142_PIN_CONTROL 0x40081188\r
-#define MMCR_GPIO142_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO143_PIN_CONTROL 0x4008118C\r
-#define MMCR_GPIO143_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO144_PIN_CONTROL 0x40081190\r
-#define MMCR_GPIO144_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO145_PIN_CONTROL 0x40081194\r
-#define MMCR_GPIO145_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO146_PIN_CONTROL 0x40081198\r
-#define MMCR_GPIO146_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO147_PIN_CONTROL 0x4008119C\r
-#define MMCR_GPIO147_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO150_PIN_CONTROL 0x400811A0\r
-#define MMCR_GPIO150_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO151_PIN_CONTROL 0x400811A4\r
-#define MMCR_GPIO151_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO152_PIN_CONTROL 0x400811A8\r
-#define MMCR_GPIO152_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO153_PIN_CONTROL 0x400811AC\r
-#define MMCR_GPIO153_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO154_PIN_CONTROL 0x400811B0\r
-#define MMCR_GPIO154_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO155_PIN_CONTROL 0x400811B4\r
-#define MMCR_GPIO155_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO156_PIN_CONTROL 0x400811B8\r
-#define MMCR_GPIO156_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO157_PIN_CONTROL 0x400811BC\r
-#define MMCR_GPIO157_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO160_PIN_CONTROL 0x400811C0\r
-#define MMCR_GPIO160_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO161_PIN_CONTROL 0x400811C4\r
-#define MMCR_GPIO161_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO162_PIN_CONTROL 0x400811C8\r
-#define MMCR_GPIO162_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO163_PIN_CONTROL 0x400811CC\r
-#define MMCR_GPIO163_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO164_PIN_CONTROL 0x400811D0\r
-#define MMCR_GPIO164_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO165_PIN_CONTROL 0x400811D4\r
-#define MMCR_GPIO165_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO200_PIN_CONTROL 0x40081200\r
-#define MMCR_GPIO200_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO201_PIN_CONTROL 0x40081204\r
-#define MMCR_GPIO201_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO202_PIN_CONTROL 0x40081208\r
-#define MMCR_GPIO202_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO203_PIN_CONTROL 0x4008120C\r
-#define MMCR_GPIO203_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO204_PIN_CONTROL 0x40081210\r
-#define MMCR_GPIO204_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO206_PIN_CONTROL 0x40081218\r
-#define MMCR_GPIO206_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO210_PIN_CONTROL 0x40081220\r
-#define MMCR_GPIO210_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO211_PIN_CONTROL 0x40081224\r
-#define MMCR_GPIO211_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO212_PIN_CONTROL 0x40081228\r
-#define MMCR_GPIO212_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO213_PIN_CONTROL 0x4008122C\r
-#define MMCR_GPIO213_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_000_036 0x40081280\r
-#define MMCR_GPIO_OUTPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_000_036))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_040_076 0x40081284\r
-#define MMCR_GPIO_OUTPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_040_076))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_100_136 0x40081288\r
-#define MMCR_GPIO_OUTPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_100_136))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_140_176 0x4008128C\r
-#define MMCR_GPIO_OUTPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_140_176))\r
-\r
-#define ADDR_GPIO_OUTPUT_GPIO_200_236 0x40081290\r
-#define MMCR_GPIO_OUTPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_200_236))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_000_036 0x40081300\r
-#define MMCR_GPIO_INPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_000_036))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_040_076 0x40081304\r
-#define MMCR_GPIO_INPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_040_076))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_100_136 0x40081308\r
-#define MMCR_GPIO_INPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_100_136))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_140_176 0x4008130C\r
-#define MMCR_GPIO_INPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_140_176))\r
-\r
-#define ADDR_GPIO_INPUT_GPIO_200_236 0x40081310\r
-#define MMCR_GPIO_INPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_200_236))\r
-\r
-#define ADDR_GPIO_LOCK_4 0x400813EC\r
-#define MMCR_GPIO_LOCK_4 (*(VUINT32 *)(ADDR_GPIO_LOCK_4))\r
-\r
-#define ADDR_GPIO_LOCK_3 0x400813F0\r
-#define MMCR_GPIO_LOCK_3 (*(VUINT32 *)(ADDR_GPIO_LOCK_3))\r
-\r
-#define ADDR_GPIO_LOCK_2 0x400813F4\r
-#define MMCR_GPIO_LOCK_2 (*(VUINT32 *)(ADDR_GPIO_LOCK_2))\r
-\r
-#define ADDR_GPIO_LOCK_1 0x400813F8\r
-#define MMCR_GPIO_LOCK_1 (*(VUINT32 *)(ADDR_GPIO_LOCK_1))\r
-\r
-#define ADDR_GPIO_LOCK_0 0x400813FC\r
-#define MMCR_GPIO_LOCK_0 (*(VUINT32 *)(ADDR_GPIO_LOCK_0))\r
-\r
-#define ADDR_GPIO000_PIN_CONTROL_2 0x40081500\r
-#define MMCR_GPIO000_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO001_PIN_CONTROL_2 0x40081504\r
-#define MMCR_GPIO001_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO002_PIN_CONTROL_2 0x40081508\r
-#define MMCR_GPIO002_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO003_PIN_CONTROL_2 0x4008150C\r
-#define MMCR_GPIO003_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO004_PIN_CONTROL_2 0x40081510\r
-#define MMCR_GPIO004_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO005_PIN_CONTROL_2 0x40081514\r
-#define MMCR_GPIO005_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO006_PIN_CONTROL_2 0x40081518\r
-#define MMCR_GPIO006_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO007_PIN_CONTROL_2 0x4008151C\r
-#define MMCR_GPIO007_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO010_PIN_CONTROL_2 0x40081520\r
-#define MMCR_GPIO010_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO011_PIN_CONTROL_2 0x40081524\r
-#define MMCR_GPIO011_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO012_PIN_CONTROL_2 0x40081528\r
-#define MMCR_GPIO012_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO013_PIN_CONTROL_2 0x4008152C\r
-#define MMCR_GPIO013_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO014_PIN_CONTROL_2 0x40081530\r
-#define MMCR_GPIO014_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO015_PIN_CONTROL_2 0x40081534\r
-#define MMCR_GPIO015_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO016_PIN_CONTROL_2 0x40081538\r
-#define MMCR_GPIO016_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO017_PIN_CONTROL_2 0x4008153C\r
-#define MMCR_GPIO017_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO020_PIN_CONTROL_2 0x40081540\r
-#define MMCR_GPIO020_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO021_PIN_CONTROL_2 0x40081544\r
-#define MMCR_GPIO021_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO022_PIN_CONTROL_2 0x40081548\r
-#define MMCR_GPIO022_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO023_PIN_CONTROL_2 0x4008154C\r
-#define MMCR_GPIO023_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO024_PIN_CONTROL_2 0x40081550\r
-#define MMCR_GPIO024_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO025_PIN_CONTROL_2 0x40081554\r
-#define MMCR_GPIO025_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO026_PIN_CONTROL_2 0x40081558\r
-#define MMCR_GPIO026_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO027_PIN_CONTROL_2 0x4008155C\r
-#define MMCR_GPIO027_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO030_PIN_CONTROL_2 0x40081560\r
-#define MMCR_GPIO030_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO031_PIN_CONTROL_2 0x40081564\r
-#define MMCR_GPIO031_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO032_PIN_CONTROL_2 0x40081568\r
-#define MMCR_GPIO032_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO033_PIN_CONTROL_2 0x4008156C\r
-#define MMCR_GPIO033_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO034_PIN_CONTROL_2 0x40081570\r
-#define MMCR_GPIO034_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO035_PIN_CONTROL_2 0x40081574\r
-#define MMCR_GPIO035_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO036_PIN_CONTROL_2 0x40081578\r
-#define MMCR_GPIO036_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO040_PIN_CONTROL_2 0x40081580\r
-#define MMCR_GPIO040_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO041_PIN_CONTROL_2 0x40081584\r
-#define MMCR_GPIO041_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO042_PIN_CONTROL_2 0x40081588\r
-#define MMCR_GPIO042_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO043_PIN_CONTROL_2 0x4008158C\r
-#define MMCR_GPIO043_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO044_PIN_CONTROL_2 0x40081590\r
-#define MMCR_GPIO044_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO045_PIN_CONTROL_2 0x40081594\r
-#define MMCR_GPIO045_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO046_PIN_CONTROL_2 0x40081598\r
-#define MMCR_GPIO046_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO047_PIN_CONTROL_2 0x4008159C\r
-#define MMCR_GPIO047_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO050_PIN_CONTROL_2 0x400815A0\r
-#define MMCR_GPIO050_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO051_PIN_CONTROL_2 0x400815A4\r
-#define MMCR_GPIO051_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO052_PIN_CONTROL_2 0x400815A8\r
-#define MMCR_GPIO052_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO053_PIN_CONTROL_2 0x400815AC\r
-#define MMCR_GPIO053_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO054_PIN_CONTROL_2 0x400815B0\r
-#define MMCR_GPIO054_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO055_PIN_CONTROL_2 0x400815B4\r
-#define MMCR_GPIO055_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO056_PIN_CONTROL_2 0x400815B8\r
-#define MMCR_GPIO056_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO057_PIN_CONTROL_2 0x400815BC\r
-#define MMCR_GPIO057_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO060_PIN_CONTROL_2 0x400815C0\r
-#define MMCR_GPIO060_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO061_PIN_CONTROL_2 0x400815C4\r
-#define MMCR_GPIO061_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO062_PIN_CONTROL_2 0x400815C8\r
-#define MMCR_GPIO062_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO063_PIN_CONTROL_2 0x400815CC\r
-#define MMCR_GPIO063_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO064_PIN_CONTROL_2 0x400815D0\r
-#define MMCR_GPIO064_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO065_PIN_CONTROL_2 0x400815D4\r
-#define MMCR_GPIO065_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO066_PIN_CONTROL_2 0x400815D8\r
-#define MMCR_GPIO066_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO067_PIN_CONTROL_2 0x400815DC\r
-#define MMCR_GPIO067_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO100_PIN_CONTROL_2 0x400815E0\r
-#define MMCR_GPIO100_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO101_PIN_CONTROL_2 0x400815E4\r
-#define MMCR_GPIO101_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO102_PIN_CONTROL_2 0x400815E8\r
-#define MMCR_GPIO102_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO103_PIN_CONTROL_2 0x400815EC\r
-#define MMCR_GPIO103_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO104_PIN_CONTROL_2 0x400815F0\r
-#define MMCR_GPIO104_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO105_PIN_CONTROL_2 0x400815F4\r
-#define MMCR_GPIO105_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO106_PIN_CONTROL_2 0x400815F8\r
-#define MMCR_GPIO106_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO107_PIN_CONTROL_2 0x400815FC\r
-#define MMCR_GPIO107_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO110_PIN_CONTROL_2 0x40081600\r
-#define MMCR_GPIO110_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO111_PIN_CONTROL_2 0x40081604\r
-#define MMCR_GPIO111_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO112_PIN_CONTROL_2 0x40081608\r
-#define MMCR_GPIO112_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO113_PIN_CONTROL_2 0x4008160C\r
-#define MMCR_GPIO113_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO114_PIN_CONTROL_2 0x40081610\r
-#define MMCR_GPIO114_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO115_PIN_CONTROL_2 0x40081614\r
-#define MMCR_GPIO115_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO116_PIN_CONTROL_2 0x40081618\r
-#define MMCR_GPIO116_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO117_PIN_CONTROL_2 0x4008161C\r
-#define MMCR_GPIO117_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO120_PIN_CONTROL_2 0x40081620\r
-#define MMCR_GPIO120_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO121_PIN_CONTROL_2 0x40081624\r
-#define MMCR_GPIO121_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO122_PIN_CONTROL_2 0x40081628\r
-#define MMCR_GPIO122_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO123_PIN_CONTROL_2 0x4008162C\r
-#define MMCR_GPIO123_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO124_PIN_CONTROL_2 0x40081630\r
-#define MMCR_GPIO124_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO125_PIN_CONTROL_2 0x40081634\r
-#define MMCR_GPIO125_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO126_PIN_CONTROL_2 0x40081638\r
-#define MMCR_GPIO126_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO127_PIN_CONTROL_2 0x4008163C\r
-#define MMCR_GPIO127_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO130_PIN_CONTROL_2 0x40081640\r
-#define MMCR_GPIO130_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO131_PIN_CONTROL_2 0x40081644\r
-#define MMCR_GPIO131_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO132_PIN_CONTROL_2 0x40081648\r
-#define MMCR_GPIO132_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO133_PIN_CONTROL_2 0x4008164C\r
-#define MMCR_GPIO133_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO134_PIN_CONTROL_2 0x40081650\r
-#define MMCR_GPIO134_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO135_PIN_CONTROL_2 0x40081654\r
-#define MMCR_GPIO135_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO136_PIN_CONTROL_2 0x40081658\r
-#define MMCR_GPIO136_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO140_PIN_CONTROL_2 0x40081660\r
-#define MMCR_GPIO140_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO141_PIN_CONTROL_2 0x40081664\r
-#define MMCR_GPIO141_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO142_PIN_CONTROL_2 0x40081668\r
-#define MMCR_GPIO142_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO143_PIN_CONTROL_2 0x4008166C\r
-#define MMCR_GPIO143_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO144_PIN_CONTROL_2 0x40081670\r
-#define MMCR_GPIO144_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO145_PIN_CONTROL_2 0x40081674\r
-#define MMCR_GPIO145_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO146_PIN_CONTROL_2 0x40081678\r
-#define MMCR_GPIO146_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO147_PIN_CONTROL_2 0x4008167C\r
-#define MMCR_GPIO147_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO150_PIN_CONTROL_2 0x40081680\r
-#define MMCR_GPIO150_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO151_PIN_CONTROL_2 0x40081684\r
-#define MMCR_GPIO151_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO152_PIN_CONTROL_2 0x40081688\r
-#define MMCR_GPIO152_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO153_PIN_CONTROL_2 0x4008168C\r
-#define MMCR_GPIO153_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO154_PIN_CONTROL_2 0x40081690\r
-#define MMCR_GPIO154_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO155_PIN_CONTROL_2 0x40081694\r
-#define MMCR_GPIO155_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO156_PIN_CONTROL_2 0x40081698\r
-#define MMCR_GPIO156_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO157_PIN_CONTROL_2 0x4008169C\r
-#define MMCR_GPIO157_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO160_PIN_CONTROL_2 0x400816A0\r
-#define MMCR_GPIO160_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO161_PIN_CONTROL_2 0x400816A4\r
-#define MMCR_GPIO161_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO162_PIN_CONTROL_2 0x400816A8\r
-#define MMCR_GPIO162_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO163_PIN_CONTROL_2 0x400816AC\r
-#define MMCR_GPIO163_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO164_PIN_CONTROL_2 0x400816B0\r
-#define MMCR_GPIO164_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO165_PIN_CONTROL_2 0x400816B4\r
-#define MMCR_GPIO165_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO200_PIN_CONTROL_2 0x40081720\r
-#define MMCR_GPIO200_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO201_PIN_CONTROL_2 0x40081724\r
-#define MMCR_GPIO201_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO202_PIN_CONTROL_2 0x40081728\r
-#define MMCR_GPIO202_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO203_PIN_CONTROL_2 0x4008172C\r
-#define MMCR_GPIO203_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO204_PIN_CONTROL_2 0x40081730\r
-#define MMCR_GPIO204_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO206_PIN_CONTROL_2 0x40081738\r
-#define MMCR_GPIO206_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO210_PIN_CONTROL_2 0x40081740\r
-#define MMCR_GPIO210_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO211_PIN_CONTROL_2 0x40081744\r
-#define MMCR_GPIO211_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO212_PIN_CONTROL_2 0x40081748\r
-#define MMCR_GPIO212_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL_2))\r
-\r
-#define ADDR_GPIO213_PIN_CONTROL_2 0x4008174C\r
-#define MMCR_GPIO213_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL_2))\r
-\r
-/***************************************************************\r
-* DMA\r
-***************************************************************/\r
-#define ADDR_DMA_MAIN_CONTROL 0x40002400\r
-#define MMCR_DMA_MAIN_CONTROL (*(VUINT8 *)(ADDR_DMA_MAIN_CONTROL))\r
-\r
-#define ADDR_DMA_AFIFO_DATA 0x40002404\r
-#define MMCR_DMA_AFIFO_DATA (*(VUINT32 *)(ADDR_DMA_AFIFO_DATA))\r
-\r
-#define ADDR_DMA_MAIN_DEBUG 0x40002408\r
-#define MMCR_DMA_MAIN_DEBUG (*(VUINT8 *)(ADDR_DMA_MAIN_DEBUG))\r
-\r
-#define ADDR_DMA_CH0_ACTIVATE 0x40002410\r
-#define MMCR_DMA_CH0_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH0_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH0_MEMORY_START_ADDRESS 0x40002414\r
-#define MMCR_DMA_CH0_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH0_MEMORY_END_ADDRESS 0x40002418\r
-#define MMCR_DMA_CH0_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH0_AHB_ADDRESS 0x4000241C\r
-#define MMCR_DMA_CH0_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH0_CONTROL 0x40002420\r
-#define MMCR_DMA_CH0_CONTROL (*(VUINT32 *)(ADDR_DMA_CH0_CONTROL))\r
-\r
-#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS 0x40002424\r
-#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE 0x40002428\r
-#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH0_TEST 0x4000242C\r
-#define MMCR_DMA_CH0_TEST (*(VUINT32 *)(ADDR_DMA_CH0_TEST))\r
-\r
-#define ADDR_DMA_CH1_ACTIVATE 0x40002430\r
-#define MMCR_DMA_CH1_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH1_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH1_MEMORY_START_ADDRESS 0x40002434\r
-#define MMCR_DMA_CH1_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH1_MEMORY_END_ADDRESS 0x40002438\r
-#define MMCR_DMA_CH1_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH1_AHB_ADDRESS 0x4000243C\r
-#define MMCR_DMA_CH1_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH1_CONTROL 0x40002440\r
-#define MMCR_DMA_CH1_CONTROL (*(VUINT32 *)(ADDR_DMA_CH1_CONTROL))\r
-\r
-#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS 0x40002444\r
-#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE 0x40002448\r
-#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH1_TEST 0x4000244C\r
-#define MMCR_DMA_CH1_TEST (*(VUINT32 *)(ADDR_DMA_CH1_TEST))\r
-\r
-#define ADDR_DMA_CH10_ACTIVATE 0x40002550\r
-#define MMCR_DMA_CH10_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH10_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH10_MEMORY_START_ADDRESS 0x40002554\r
-#define MMCR_DMA_CH10_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH10_MEMORY_END_ADDRESS 0x40002558\r
-#define MMCR_DMA_CH10_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH10_AHB_ADDRESS 0x4000255C\r
-#define MMCR_DMA_CH10_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH10_CONTROL 0x40002560\r
-#define MMCR_DMA_CH10_CONTROL (*(VUINT32 *)(ADDR_DMA_CH10_CONTROL))\r
-\r
-#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS 0x40002564\r
-#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE 0x40002568\r
-#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH10_TEST 0x4000256C\r
-#define MMCR_DMA_CH10_TEST (*(VUINT32 *)(ADDR_DMA_CH10_TEST))\r
-\r
-#define ADDR_DMA_CH11_ACTIVATE 0x40002570\r
-#define MMCR_DMA_CH11_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH11_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH11_MEMORY_START_ADDRESS 0x40002574\r
-#define MMCR_DMA_CH11_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH11_MEMORY_END_ADDRESS 0x40002578\r
-#define MMCR_DMA_CH11_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH11_AHB_ADDRESS 0x4000257C\r
-#define MMCR_DMA_CH11_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH11_CONTROL 0x40002580\r
-#define MMCR_DMA_CH11_CONTROL (*(VUINT32 *)(ADDR_DMA_CH11_CONTROL))\r
-\r
-#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS 0x40002584\r
-#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE 0x40002588\r
-#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH11_TEST 0x4000258C\r
-#define MMCR_DMA_CH11_TEST (*(VUINT32 *)(ADDR_DMA_CH11_TEST))\r
-\r
-#define ADDR_DMA_CH2_ACTIVATE 0x40002450\r
-#define MMCR_DMA_CH2_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH2_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH2_MEMORY_START_ADDRESS 0x40002454\r
-#define MMCR_DMA_CH2_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH2_MEMORY_END_ADDRESS 0x40002458\r
-#define MMCR_DMA_CH2_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH2_AHB_ADDRESS 0x4000245C\r
-#define MMCR_DMA_CH2_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH2_CONTROL 0x40002460\r
-#define MMCR_DMA_CH2_CONTROL (*(VUINT32 *)(ADDR_DMA_CH2_CONTROL))\r
-\r
-#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS 0x40002464\r
-#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE 0x40002468\r
-#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH2_TEST 0x4000246C\r
-#define MMCR_DMA_CH2_TEST (*(VUINT32 *)(ADDR_DMA_CH2_TEST))\r
-\r
-#define ADDR_DMA_CH3_ACTIVATE 0x40002470\r
-#define MMCR_DMA_CH3_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH3_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH3_MEMORY_START_ADDRESS 0x40002474\r
-#define MMCR_DMA_CH3_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH3_MEMORY_END_ADDRESS 0x40002478\r
-#define MMCR_DMA_CH3_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH3_AHB_ADDRESS 0x4000247C\r
-#define MMCR_DMA_CH3_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH3_CONTROL 0x40002480\r
-#define MMCR_DMA_CH3_CONTROL (*(VUINT32 *)(ADDR_DMA_CH3_CONTROL))\r
-\r
-#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS 0x40002484\r
-#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE 0x40002488\r
-#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH3_TEST 0x4000248C\r
-#define MMCR_DMA_CH3_TEST (*(VUINT32 *)(ADDR_DMA_CH3_TEST))\r
-\r
-#define ADDR_DMA_CH4_ACTIVATE 0x40002490\r
-#define MMCR_DMA_CH4_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH4_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH4_MEMORY_START_ADDRESS 0x40002494\r
-#define MMCR_DMA_CH4_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH4_MEMORY_END_ADDRESS 0x40002498\r
-#define MMCR_DMA_CH4_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH4_AHB_ADDRESS 0x4000249C\r
-#define MMCR_DMA_CH4_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH4_CONTROL 0x400024A0\r
-#define MMCR_DMA_CH4_CONTROL (*(VUINT32 *)(ADDR_DMA_CH4_CONTROL))\r
-\r
-#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS 0x400024A4\r
-#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE 0x400024A8\r
-#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH4_TEST 0x400024AC\r
-#define MMCR_DMA_CH4_TEST (*(VUINT32 *)(ADDR_DMA_CH4_TEST))\r
-\r
-#define ADDR_DMA_CH5_ACTIVATE 0x400024B0\r
-#define MMCR_DMA_CH5_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH5_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH5_MEMORY_START_ADDRESS 0x400024B4\r
-#define MMCR_DMA_CH5_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH5_MEMORY_END_ADDRESS 0x400024B8\r
-#define MMCR_DMA_CH5_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH5_AHB_ADDRESS 0x400024BC\r
-#define MMCR_DMA_CH5_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH5_CONTROL 0x400024C0\r
-#define MMCR_DMA_CH5_CONTROL (*(VUINT32 *)(ADDR_DMA_CH5_CONTROL))\r
-\r
-#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS 0x400024C4\r
-#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE 0x400024C8\r
-#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH5_TEST 0x400024CC\r
-#define MMCR_DMA_CH5_TEST (*(VUINT32 *)(ADDR_DMA_CH5_TEST))\r
-\r
-#define ADDR_DMA_CH6_ACTIVATE 0x400024D0\r
-#define MMCR_DMA_CH6_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH6_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH6_MEMORY_START_ADDRESS 0x400024D4\r
-#define MMCR_DMA_CH6_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH6_MEMORY_END_ADDRESS 0x400024D8\r
-#define MMCR_DMA_CH6_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH6_AHB_ADDRESS 0x400024DC\r
-#define MMCR_DMA_CH6_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH6_CONTROL 0x4.00E+05\r
-#define MMCR_DMA_CH6_CONTROL (*(VUINT32 *)(ADDR_DMA_CH6_CONTROL))\r
-\r
-#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS 0x4.00E+09\r
-#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE 0x4.00E+13\r
-#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH6_TEST 0x400024EC\r
-#define MMCR_DMA_CH6_TEST (*(VUINT32 *)(ADDR_DMA_CH6_TEST))\r
-\r
-#define ADDR_DMA_CH7_ACTIVATE 0x400024F0\r
-#define MMCR_DMA_CH7_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH7_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH7_MEMORY_START_ADDRESS 0x400024F4\r
-#define MMCR_DMA_CH7_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH7_MEMORY_END_ADDRESS 0x400024F8\r
-#define MMCR_DMA_CH7_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH7_AHB_ADDRESS 0x400024FC\r
-#define MMCR_DMA_CH7_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH7_CONTROL 0x40002500\r
-#define MMCR_DMA_CH7_CONTROL (*(VUINT32 *)(ADDR_DMA_CH7_CONTROL))\r
-\r
-#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS 0x40002504\r
-#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE 0x40002508\r
-#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH7_TEST 0x4000250C\r
-#define MMCR_DMA_CH7_TEST (*(VUINT32 *)(ADDR_DMA_CH7_TEST))\r
-\r
-#define ADDR_DMA_CH8_ACTIVATE 0x40002510\r
-#define MMCR_DMA_CH8_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH8_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH8_MEMORY_START_ADDRESS 0x40002514\r
-#define MMCR_DMA_CH8_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH8_MEMORY_END_ADDRESS 0x40002518\r
-#define MMCR_DMA_CH8_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH8_AHB_ADDRESS 0x4000251C\r
-#define MMCR_DMA_CH8_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH8_CONTROL 0x40002520\r
-#define MMCR_DMA_CH8_CONTROL (*(VUINT32 *)(ADDR_DMA_CH8_CONTROL))\r
-\r
-#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS 0x40002524\r
-#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE 0x40002528\r
-#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH8_TEST 0x4000252C\r
-#define MMCR_DMA_CH8_TEST (*(VUINT32 *)(ADDR_DMA_CH8_TEST))\r
-\r
-#define ADDR_DMA_CH9_ACTIVATE 0x40002530\r
-#define MMCR_DMA_CH9_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH9_ACTIVATE))\r
-\r
-#define ADDR_DMA_CH9_MEMORY_START_ADDRESS 0x40002534\r
-#define MMCR_DMA_CH9_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_START_ADDRESS))\r
-\r
-#define ADDR_DMA_CH9_MEMORY_END_ADDRESS 0x40002538\r
-#define MMCR_DMA_CH9_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_END_ADDRESS))\r
-\r
-#define ADDR_DMA_CH9_AHB_ADDRESS 0x4000253C\r
-#define MMCR_DMA_CH9_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_AHB_ADDRESS))\r
-\r
-#define ADDR_DMA_CH9_CONTROL 0x40002540\r
-#define MMCR_DMA_CH9_CONTROL (*(VUINT32 *)(ADDR_DMA_CH9_CONTROL))\r
-\r
-#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS 0x40002544\r
-#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS))\r
-\r
-#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE 0x40002548\r
-#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE))\r
-\r
-#define ADDR_DMA_CH9_TEST 0x4000254C\r
-#define MMCR_DMA_CH9_TEST (*(VUINT32 *)(ADDR_DMA_CH9_TEST))\r
-\r
-#endif /*SMSCMMCR_H_*/\r
+++ /dev/null
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/11/22 06:01:28 $ \r
-$Author: amohandas $\r
-Last Change: Updated with unit testing feedbacks\r
-******************************************************************************/\r
-/** @file btimer.h\r
-* \brief Basic Timer Peripheral Header file\r
-* \author jvasanth\r
-* \r
-* This file is the header file for Basic Timer Peripheral \r
-******************************************************************************/\r
-\r
-/** @defgroup Basic_Timer\r
- * @{\r
- */\r
-\r
-#ifndef _BTIMER_H\r
-#define _BTIMER_H\r
-\r
-/******************************************************************************/\r
-/** Logical Timer ID for APIs.\r
- * This is the timer IDs passed to Basic Timer API function calls \r
- *******************************************************************************/\r
-enum _PID_BTIMER_\r
-{\r
- PID_BTIMER_0,\r
- PID_BTIMER_1,\r
- PID_BTIMER_2,\r
- PID_BTIMER_3,\r
- PID_BTIMER_4,\r
- PID_BTIMER_5,\r
- PID_BTIMER_MAX \r
-};\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Logical flags for Timer Control */\r
-/* ---------------------------------------------------------------------- */\r
-//This is for tmr_cntl parameter in btimer_init function\r
-#define BTIMER_AUTO_RESTART (0x08u)\r
-#define BTIMER_ONE_SHOT (0u)\r
-#define BTIMER_COUNT_UP (0x04u)\r
-#define BTIMER_COUNT_DOWN (0u)\r
-#define BTIMER_INT_EN (0x01u)\r
-#define BTIMER_NO_INT (0u)\r
-/* ---------------------------------------------------------------------- */\r
-\r
-\r
-//Timer Block Hardware Bits and Masks\r
-#define BTIMER_CNTL_HALT (0x80UL)\r
-#define BTIMER_CNTL_RELOAD (0x40UL)\r
-#define BTIMER_CNTL_START (0x20UL)\r
-#define BTIMER_CNTL_SOFT_RESET (0x10UL)\r
-#define BTIMER_CNTL_AUTO_RESTART (0x08UL)\r
-#define BTIMER_CNTL_COUNT_UP (0x04UL)\r
-#define BTIMER_CNTL_ENABLE (0x01UL)\r
-\r
-#define BTIMER_CNTL_HALT_BIT (7U)\r
-#define BTIMER_CNTL_RELOAD_BIT (6U)\r
-#define BTIMER_CNTL_START_BIT (5U)\r
-#define BTIMER_CNTRL_SOFT_RESET_BIT (4U)\r
-#define BTIMER_CNTL_AUTO_RESTART_BIT (3U)\r
-#define BTIMER_CNTL_COUNT_DIR_BIT (2U)\r
-#define BTIMER_CNTL_ENABLE_BIT (0U)\r
-\r
-#define BTIMER_GIRQ MEC_GIRQ23_ID\r
-#define BTIMER_MAX_INSTANCE PID_BTIMER_MAX\r
-\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Basic Timer Intitialization function */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Initialize specified timer\r
- * @param btimer_id Basic Timer ID\r
- * @param tmr_cntl Logical flags for Timer Control\r
- * @param initial_count Initial Count\r
- * @param preload_count Preload Count\r
- * @note Performs a soft reset of the timer before configuration \r
- */\r
-void btimer_init(uint8_t btimer_id, \r
- uint16_t tmr_cntl,\r
- uint16_t prescaler,\r
- uint32_t initial_count,\r
- uint32_t preload_count);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions to program and read the Basic Timer Counter */\r
-/* ---------------------------------------------------------------------- */\r
-/** Program timer's counter register.\r
- * @param btimer_id Basic Timer ID\r
- * @param count new counter value \r
- * @note Timer hardware may implement a 16-bit or 32-bit \r
- * hardware counter. If the timer is 16-bit only the lower\r
- * 16-bits of the count paramter are used.\r
- */\r
-void btimer_count_set(uint8_t btimer_id, uint32_t count);\r
-\r
-/** Return current value of timer's count register.\r
- * @param btimer_id Basic Timer ID. \r
- * @return uint32_t timer count may be 32 or 16 bits depending \r
- * upon the hardware. Timers 0-3 are 16-bit\r
- * and Timers 4-5 are 32-bit.\r
- */\r
-uint32_t btimer_count_get(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Function to reload counter from Preload Register */\r
-/* ---------------------------------------------------------------------- */\r
-/** Force timer to reload counter from preload \r
- * register. \r
- * @param btimer_id Basic Timer ID. \r
- * @note Hardware will only reload counter if timer is running. \r
- */\r
-void btimer_reload(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions for stopping and starting the basic Timer */\r
-/* ---------------------------------------------------------------------- */\r
-/** Start timer counting.\r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_start(uint8_t btimer_id);\r
-\r
-/** Stop timer. \r
- * @param btimer_id Basic Timer ID. \r
- * @note When a stopped timer is started again it will reload \r
- * the count register from preload value.\r
- */\r
-void btimer_stop(uint8_t btimer_id);\r
-\r
-/** Return state of timer's START bit. \r
- * @param btimer_id Basic Timer ID. \r
- * @return uint8_t 0(timer not started), 1 (timer started)\r
- */\r
-uint8_t btimer_is_started(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Function to perform basic timer soft reset */\r
-/* ---------------------------------------------------------------------- */\r
-/** Peform soft reset of specified timer. \r
- * @param btimer_id Basic Timer ID \r
- * @note Soft reset set all registers to POR values.\r
- * Spins 256 times waiting on hardware to clear reset bit. \r
- */\r
-void btimer_reset(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions to halt/unhalt the timer counting */\r
-/* ---------------------------------------------------------------------- */\r
-/** Halt timer counting with no reload on unhalt. \r
- * @param btimer_id Basic Timer ID. \r
- * @note A halted timer will not reload the count register when \r
- * unhalted, it will continue counting from the current\r
- * count value.\r
- */\r
-void btimer_halt(uint8_t btimer_id);\r
-\r
-/** Unhalt timer counting. \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_unhalt(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions for Basic Timer interrupt */\r
-/* ---------------------------------------------------------------------- */\r
-/** Enable specified timer's interrupt from the block. \r
- * @param btimer_id Basic Timer ID.\r
- * @param ien Non-zero enable interrupt in timer block, 0 \r
- * disable.\r
- */\r
-void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien);\r
-\r
-/** Read Timer interrupt status and clear if set \r
- * @param btimer_id Basic Timer ID. \r
- * @return uint8_t 1 (Timer interrupt status set) else 0. \r
- * @note If timer interrupt status is set then clear it before \r
- * returning.\r
- */\r
-uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions for Basic Timer GIRQ */\r
-/* ---------------------------------------------------------------------- */\r
-/** Enables GIRQ enable bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_enable_set(uint8_t btimer_id);\r
-\r
-/** Clears GIRQ enable bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_enable_clr(uint8_t btimer_id);\r
-\r
-/** Returns GIRQ source bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- * @return uint8_t 0(src bit not set), Non-zero (src bit set)\r
- */\r
-uint8_t btimer_girq_src_get(uint8_t btimer_id);\r
-\r
-/** Clears GIRQ source bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_src_clr(uint8_t btimer_id);\r
-\r
-/** Returns GIRQ result bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- * @return uint8_t 0(result bit not set), Non-zero (result bit set)\r
- */\r
-uint8_t btimer_girq_result_get(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions for Basic Timer Sleep */\r
-/* ---------------------------------------------------------------------- */\r
-/** Enable/Disable clock gating on idle of a timer \r
- * @param btimer_id Basic Timer ID.\r
- * @param sleep_en 1 = Sleep enable, 0 = Sleep disable\r
- */\r
-void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en);\r
-\r
-/** Returns clk required status for the timer block\r
- * @param btimer_id Basic Timer ID.\r
- * @return Non-zero if clk required, else 0\r
- */\r
-uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id);\r
-\r
-/** Enable/Disable reset on sleep for the timer block \r
- * @param btimer_id Basic Timer ID.\r
- * @param reset_en 1 to enable, 0 to disable\r
- */\r
-void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to set and read Timer Counter Register */\r
-/* ---------------------------------------------------------------------- */\r
-/** Sets timer counter\r
- * @param btimer_id Basic Timer ID\r
- * @param count - 32-bit counter \r
- */\r
-void p_btimer_count_set(uint8_t btimer_id, uint32_t count);\r
-\r
-/** Read the timer counter\r
- * @param btimer_id Basic Timer ID\r
- * @return count - 32-bit counter \r
- */\r
-uint32_t p_btimer_count_get(uint8_t btimer_id);\r
-\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to program the Preload */\r
-/* ---------------------------------------------------------------------- */\r
-/** Sets preload for the counter\r
- * @param btimer_id Basic Timer ID\r
- * @param preload_count - 32-bit pre-load value \r
- */\r
-void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Functions - Functions for basic timer interrupts */\r
-/* ---------------------------------------------------------------------- */\r
-/** Reads the interrupt status bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- * @return status - 1 if interrupt status set, else 0\r
- */\r
-uint8_t p_btimer_int_status_get(uint8_t btimer_id);\r
-\r
-/** Clears interrupt status bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_status_clr(uint8_t btimer_id);\r
-\r
-/** Sets interrupt enable bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_enable_set(uint8_t btimer_id);\r
-\r
-/** Clears interrupt enable bit for the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_enable_clr(uint8_t btimer_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Functions - Functions for Control Register */\r
-/* ---------------------------------------------------------------------- */\r
-/** Writes the control register 32-bits\r
- * @param btimer_id Basic Timer ID\r
- * @param value - 32-bit value to program\r
- */\r
-void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value);\r
-\r
-/** Reads the control register \r
- * @param btimer_id Basic Timer ID\r
- * @return uint32_t - 32-bit value\r
- */\r
-uint32_t p_btimer_ctrl_read(uint8_t btimer_id);\r
-\r
-/** Clears enable bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_enable_set(uint8_t btimer_id);\r
-\r
-/** Clears enable bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_enable_clr(uint8_t btimer_id);\r
-\r
-/** Sets counter direction bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id);\r
-\r
-/** Clears counter direction bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id);\r
-\r
-/** Sets auto restart bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id);\r
-\r
-/** Clears auto resetart bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id);\r
-\r
-/** Sets soft reset bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id);\r
-\r
-/** Read Soft Reset bit \r
- * @param btimer_id Basic Timer ID\r
- * @return 0 if soft reset status bit cleared; else non-zero value\r
- */\r
-uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id);\r
-\r
-/** Sets start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_start_set(uint8_t btimer_id);\r
-\r
-/** Read start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- * @return 0 if start bit not set; else non-zero value\r
- */\r
-uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id);\r
-\r
-/** Clears start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_start_clr(uint8_t btimer_id);\r
-\r
-/** Sets reload bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_reload_set(uint8_t btimer_id);\r
-\r
-/** Clears reload bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_reload_clr(uint8_t btimer_id);\r
-\r
-/** Sets halt bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_halt_set(uint8_t btimer_id);\r
-\r
-/** Clears halt bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-\r
-void p_btimer_ctrl_halt_clr(uint8_t btimer_id);\r
-\r
-/** Sets prescale value\r
- * @param btimer_id Basic Timer ID\r
- * @param prescaler - 16-bit pre-scale value \r
- */\r
-void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler);\r
-\r
-\r
-#endif // #ifndef _BTIMER_H\r
-\r
-/* end btimer_perphl.c */\r
-\r
-/** @} //Peripherals Basic_Timer\r
- */\r
-\r
+++ /dev/null
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #2 $ \r
-$DateTime: 2015/11/24 06:27:00 $ \r
-$Author: amohandas $\r
-Last Change: Updated for tabs\r
-******************************************************************************/\r
-/** @file btimer_api.c\r
-* \brief Basic Timer APIs Source file\r
-* \author jvasanth\r
-* \r
-* This file implements the Basic Timer API functions \r
-******************************************************************************/\r
-\r
-/** @defgroup Basic_Timer\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "btimer.h"\r
-#include "..\pcr\pcr.h"\r
-\r
-/** Basic Timer Sleep Registers & Bit Positions */\r
-static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = {\r
- PCR_BTIMER0,\r
- PCR_BTIMER1,\r
- PCR_BTIMER2,\r
- PCR_BTIMER3,\r
- PCR_BTIMER4,\r
- PCR_BTIMER5\r
-};\r
-\r
-#ifdef PLIB_BTIMER_CHECK_ID\r
-\r
-/** Local helper that checks if logical Timer ID is valid. \r
- * @param btimer_id Basic Timer ID \r
- * @return uint8_t Non-zero(VALID), 0(Invalid)\r
- */\r
-static uint8_t btmr_valid(uint8_t btimer_id)\r
-{\r
- if ( btimer_id < (PID_BTIMER_MAX ) ) {\r
- return true;\r
- }\r
- return false;\r
-}\r
-\r
-#else\r
-\r
-\r
-/** This version of tmr_valid skips checking always returning 1. \r
- * Compiler may optimize it out.\r
- * @param btimer_id Basic Timer ID \r
- * @return uint8_t 1(VALID) \r
- */\r
-static uint8_t btmr_valid(uint8_t btimer_id) { return 1; }\r
-\r
-#endif\r
-\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Basic Timer Intitialization function */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Initialize specified timer\r
- * @param btimer_id Basic Timer ID\r
- * @param tmr_cntl Logical flags for Timer Control\r
- * @param initial_count Initial Count\r
- * @param preload_count Preload Count\r
- * @note Performs a soft reset of the timer before configuration \r
- */\r
-void btimer_init(uint8_t btimer_id, \r
- uint16_t tmr_cntl,\r
- uint16_t prescaler,\r
- uint32_t initial_count,\r
- uint32_t preload_count)\r
-{ \r
- uint32_t value; \r
-\r
- if (btmr_valid(btimer_id)) {\r
- \r
- btimer_reset(btimer_id); \r
- \r
- // Ungate timer clocks and program prescale\r
- value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE); \r
- p_btimer_ctrl_write(btimer_id, value);\r
- \r
- // Program Preload & initial counter value\r
- p_btimer_preload_set(btimer_id, preload_count);\r
- p_btimer_count_set(btimer_id, initial_count); \r
- \r
- // Program control register, interrupt enable, and clear status\r
- if (tmr_cntl & BTIMER_COUNT_UP) { \r
- p_btimer_ctrl_counter_dir_set(btimer_id); \r
- }\r
- if (tmr_cntl & BTIMER_AUTO_RESTART) {\r
- p_btimer_ctrl_auto_restart_set(btimer_id); \r
- } \r
- if (tmr_cntl & BTIMER_INT_EN) { \r
- p_btimer_int_enable_set(btimer_id); // enable first\r
- p_btimer_int_status_clr(btimer_id); // clear status \r
- }\r
- }\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to program and read the Basic Timer Counter */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Program timer's counter register.\r
- * @param btimer_id Basic Timer ID\r
- * @param count new counter value \r
- * @note Timer hardware may implement a 16-bit or 32-bit \r
- * hardware counter. If the timer is 16-bit only the lower\r
- * 16-bits of the count paramter are used.\r
- */\r
-void btimer_count_set(uint8_t btimer_id, uint32_t count)\r
-{\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- p_btimer_count_set(btimer_id, count); \r
- }\r
-}\r
-\r
-/** Return current value of timer's count register.\r
- * @param btimer_id Basic Timer ID. \r
- * @return uint32_t timer count may be 32 or 16 bits depending \r
- * upon the hardware. Timers 0-3 are 16-bit\r
- * and Timers 4-5 are 32-bit.\r
- */\r
-uint32_t btimer_count_get(uint8_t btimer_id)\r
-{ \r
- uint32_t cnt;\r
- \r
- cnt = 0ul;\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- cnt = p_btimer_count_get(btimer_id); \r
- }\r
- \r
- return cnt;\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to reload counter from Preload Register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Force timer to reload counter from preload \r
- * register. \r
- * @param btimer_id Basic Timer ID. \r
- * @note Hardware will only reload counter if timer is running. \r
- */\r
-void btimer_reload(uint8_t btimer_id)\r
-{\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running\r
- {\r
- p_btimer_ctrl_reload_set(btimer_id);\r
- }\r
- }\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for stopping and starting the basic Timer */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Start timer counting.\r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_start(uint8_t btimer_id)\r
-{\r
- if ( btmr_valid(btimer_id) ) {\r
- \r
- p_btimer_ctrl_start_set(btimer_id);\r
- }\r
-}\r
-\r
-/** Stop timer. \r
- * @param btimer_id Basic Timer ID. \r
- * @note When a stopped timer is started again it will reload \r
- * the count register from preload value.\r
- */\r
-void btimer_stop(uint8_t btimer_id)\r
-{\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- p_btimer_ctrl_start_clr(btimer_id); \r
- \r
- }\r
-}\r
-\r
-/** Return state of timer's START bit. \r
- * @param btimer_id Basic Timer ID. \r
- * @return uint8_t 0(timer not started), 1 (timer started)\r
- */\r
-uint8_t btimer_is_started(uint8_t btimer_id)\r
-{ \r
- uint8_t sts;\r
- \r
- sts = 0;\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- if (p_btimer_ctrl_start_get(btimer_id)) \r
- {\r
- sts = 1;\r
- } \r
- }\r
- return sts;\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to perform basic timer soft reset */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Peform soft reset of specified timer. \r
- * @param btimer_id Basic Timer ID \r
- * @note Soft reset set all registers to POR values.\r
- * Spins 256 times waiting on hardware to clear reset bit. \r
- */\r
-void btimer_reset(uint8_t btimer_id)\r
-{ \r
- uint32_t wait_cnt;\r
- uint8_t soft_reset_sts;\r
-\r
- if (btmr_valid(btimer_id)) { \r
- \r
- p_btimer_ctrl_soft_reset_set(btimer_id); \r
-\r
- wait_cnt = 256ul;\r
- do {\r
- soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id);\r
- \r
- if (0 == soft_reset_sts){ \r
- break;\r
- }\r
- } \r
- while ( wait_cnt-- ); \r
- } \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to halt/unhalt the timer counting */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Halt timer counting with no reload on unhalt. \r
- * @param btimer_id Basic Timer ID. \r
- * @note A halted timer will not reload the count register when \r
- * unhalted, it will continue counting from the current\r
- * count value.\r
- */\r
-void btimer_halt(uint8_t btimer_id)\r
-{\r
- if ( btmr_valid(btimer_id) ) {\r
- \r
- p_btimer_ctrl_halt_set(btimer_id); \r
- }\r
-}\r
-\r
-/** Unhalt timer counting. \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_unhalt(uint8_t btimer_id)\r
-{\r
- if ( btmr_valid(btimer_id) ) { \r
- \r
- p_btimer_ctrl_halt_clr(btimer_id);\r
- }\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for Basic Timer interrupt */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Enable specified timer's interrupt from the block. \r
- * @param btimer_id Basic Timer ID.\r
- * @param ien Non-zero enable interrupt in timer block, 0 \r
- * disable.\r
- */\r
-void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien)\r
-{ \r
- if (btmr_valid(btimer_id)) { \r
- \r
- p_btimer_int_enable_set(btimer_id);\r
-\r
- if (ien) {\r
- p_btimer_int_enable_set(btimer_id);\r
- } else {\r
- p_btimer_int_enable_clr(btimer_id);\r
- }\r
- }\r
-}\r
-\r
-/** Read Timer interrupt status and clear if set \r
- * @param btimer_id Basic Timer ID. \r
- * @return uint8_t 1 (Timer interrupt status set) else 0. \r
- * @note If timer interrupt status is set then clear it before \r
- * returning.\r
- */\r
-uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id)\r
-{ \r
- uint8_t sts;\r
-\r
- sts = 0;\r
- if (btmr_valid(btimer_id)) { \r
- \r
- sts = p_btimer_int_status_get(btimer_id);\r
- if (sts) {\r
- p_btimer_int_status_clr(btimer_id); \r
- }\r
- }\r
- return sts;\r
-}\r
-\r
-#if 0 //Temporary disable until interrupt module\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for Basic Timer GIRQ */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Enables GIRQ enable bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_enable_set(uint8_t btimer_id)\r
-{\r
- if (btmr_valid(btimer_id))\r
- {\r
- //Note: Bit Position is same as Timer ID \r
- p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id);\r
- } \r
-}\r
-\r
-/** Clears GIRQ enable bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_enable_clr(uint8_t btimer_id)\r
-{ \r
- if (btmr_valid(btimer_id))\r
- { \r
- //Note: Bit Position is same as Timer ID \r
- p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id);\r
- } \r
- \r
-}\r
-\r
-/** Returns GIRQ source bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- * @return uint8_t 0(src bit not set), Non-zero (src bit set)\r
- */\r
-uint8_t btimer_girq_src_get(uint8_t btimer_id)\r
-{\r
- uint8_t retVal;\r
-\r
- retVal = 0;\r
- if (btmr_valid(btimer_id))\r
- {\r
- //Note: Bit Position is same as Timer ID \r
- retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id); \r
- }\r
-\r
- return retVal;\r
-}\r
-\r
-/** Clears GIRQ source bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- */\r
-void btimer_girq_src_clr(uint8_t btimer_id)\r
-{\r
- if (btmr_valid(btimer_id))\r
- {\r
- //Note: Bit Position is same as Timer ID \r
- p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id); \r
- } \r
-}\r
-\r
-/** Returns GIRQ result bit for the timer \r
- * @param btimer_id Basic Timer ID.\r
- * @return uint8_t 0(result bit not set), Non-zero (result bit set)\r
- */\r
-uint8_t btimer_girq_result_get(uint8_t btimer_id)\r
-{\r
- uint8_t retVal;\r
-\r
- retVal = 0;\r
- if (btmr_valid(btimer_id))\r
- {\r
- //Note: Bit Position is same as Timer ID \r
- retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id); \r
- }\r
-\r
- return retVal; \r
-}\r
-#endif\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for Basic Timer Sleep */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Enable/Disable clock gating on idle of a timer \r
- * @param btimer_id Basic Timer ID.\r
- * @param sleep_en 1 = Sleep enable, 0 = Sleep disable\r
- */\r
-void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en)\r
-{\r
- uint32_t pcr_blk_id;\r
- \r
- if ( btmr_valid(btimer_id) ) \r
- { \r
- pcr_blk_id = btmr_pcr_id[btimer_id]; \r
- \r
- pcr_sleep_enable(pcr_blk_id, sleep_en); \r
- }\r
-}\r
-\r
-/** Returns clk required status for the timer block\r
- * @param btimer_id Basic Timer ID.\r
- * @return Non-zero if clk required, else 0\r
- */\r
-uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id)\r
-{\r
- uint32_t retVal;\r
- uint32_t pcr_blk_id;\r
- \r
- retVal = 0ul; \r
- if ( btmr_valid(btimer_id) ) \r
- { \r
- pcr_blk_id = btmr_pcr_id[btimer_id];\r
- \r
- retVal = pcr_clock_reqd_status_get(pcr_blk_id); \r
- }\r
- \r
- return retVal;\r
-}\r
-\r
-/** Enable/Disable reset on sleep for the timer block \r
- * @param btimer_id Basic Timer ID.\r
- * @param reset_en 1 to enable, 0 to disable\r
- */\r
-void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en)\r
-{\r
- uint32_t pcr_blk_id; \r
- \r
- if ( btmr_valid(btimer_id) ) \r
- { \r
- pcr_blk_id = btmr_pcr_id[btimer_id];\r
- \r
- pcr_reset_enable(pcr_blk_id, reset_en); \r
- }\r
-}\r
-\r
-/* end btimer_api.c */\r
-\r
-/** @} //Peripheral Basic_Timer\r
- */\r
+++ /dev/null
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #2 $ \r
-$DateTime: 2015/11/24 06:27:00 $ \r
-$Author: amohandas $\r
-Last Change: Updated for tabs\r
-******************************************************************************/\r
-/** @file btimer_perphl.c\r
-* \brief Basic Timer Peripheral Source file\r
-* \author jvasanth\r
-* \r
-* This file implements the Basic Timer Peripheral functions \r
-******************************************************************************/\r
-\r
-/** @defgroup Basic_Timer\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "btimer.h"\r
-\r
-/** Basic Timer Instance base addresses */\r
-static TIMER_16_0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = {\r
- CEC1302_TIMER_16_0,\r
- CEC1302_TIMER_16_1,\r
- CEC1302_TIMER_16_2,\r
- CEC1302_TIMER_16_3,\r
- CEC1302_TIMER_32_0,\r
- CEC1302_TIMER_32_1\r
-};\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to set and read Timer Counter Register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Sets timer counter\r
- * @param btimer_id Basic Timer ID\r
- * @param count - 32-bit counter \r
- */\r
-void p_btimer_count_set(uint8_t btimer_id, uint32_t count)\r
-{\r
- btmr_inst[btimer_id]->COUNT = count; \r
-}\r
-\r
-/** Read the timer counter\r
- * @param btimer_id Basic Timer ID\r
- * @return count - 32-bit counter \r
- */\r
-uint32_t p_btimer_count_get(uint8_t btimer_id)\r
-{ \r
- return btmr_inst[btimer_id]->COUNT; \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to program the Preload */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Sets preload for the counter\r
- * @param btimer_id Basic Timer ID\r
- * @param preload_count - 32-bit pre-load value \r
- */\r
-void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count)\r
-{\r
- btmr_inst[btimer_id]->PRE_LOAD = preload_count; \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for basic timer interrupts */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Reads the interrupt status bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- * @return status - 1 if interrupt status set, else 0\r
- */\r
-uint8_t p_btimer_int_status_get(uint8_t btimer_id)\r
-{\r
- return (uint8_t)(btmr_inst[btimer_id]->INTERRUPT_STATUS);\r
-}\r
-\r
-/** Clears interrupt status bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_status_clr(uint8_t btimer_id)\r
-{\r
- // Write 1 to clear\r
- btmr_inst[btimer_id]->INTERRUPT_STATUS = 1;\r
-}\r
-\r
-/** Sets interrupt enable bit in the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_enable_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->INTERRUPT_ENABLE = 1;\r
-}\r
-\r
-/** Clears interrupt enable bit for the timer block\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_int_enable_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->INTERRUPT_ENABLE = 0;\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for Control Register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Writes the control register 32-bits\r
- * @param btimer_id Basic Timer ID\r
- * @param value - 32-bit value to program\r
- */\r
-void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.w = value;\r
-}\r
-\r
-/** Reads the control register \r
- * @param btimer_id Basic Timer ID\r
- * @return uint32_t - 32-bit value\r
- */\r
-uint32_t p_btimer_ctrl_read(uint8_t btimer_id)\r
-{ \r
- uint32_t retVal;\r
-\r
- retVal = btmr_inst[btimer_id]->CONTROL.w;\r
-\r
- return retVal;\r
-}\r
-\r
-/** Sets enable bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_enable_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE;\r
-}\r
-\r
-/** Clears enable bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_enable_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE;\r
-}\r
-\r
-/** Sets counter direction bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP;\r
-}\r
-\r
-/** Clears counter direction bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP;\r
-}\r
-\r
-/** Sets auto restart bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART;\r
-}\r
-\r
-/** Clears auto resetart bit in the control register\r
- * @param btimer_id Basic Timer ID\r
- */\r
-void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART;\r
-}\r
-\r
-/** Sets soft reset bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET;\r
-}\r
-\r
-/** Read Soft Reset bit \r
- * @param btimer_id Basic Timer ID\r
- * @return 0 if soft reset status bit cleared; else non-zero value\r
- */\r
-uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id)\r
-{ \r
- return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET);\r
-}\r
-\r
-/** Sets start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_start_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START;\r
-}\r
-\r
-/** Read start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- * @return 0 if start bit not set; else non-zero value\r
- */\r
-uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id)\r
-{ \r
- return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START);\r
-}\r
-\r
-/** Clears start bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_start_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START;\r
-}\r
-\r
-/** Sets reload bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_reload_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD;\r
-}\r
-\r
-/** Clears reload bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_reload_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD;\r
-}\r
-\r
-/** Sets halt bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_halt_set(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT;\r
-}\r
-\r
-/** Clears halt bit in the control register\r
- * @param btimer_id Basic Timer ID \r
- */\r
-void p_btimer_ctrl_halt_clr(uint8_t btimer_id)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT;\r
-}\r
-\r
-/** Sets prescale value\r
- * @param btimer_id Basic Timer ID\r
- * @param prescaler - 16-bit pre-scale value \r
- */\r
-void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler)\r
-{ \r
- btmr_inst[btimer_id]->CONTROL.h[1] = prescaler;\r
-}\r
-\r
-\r
-/* end btimer_perphl.c */\r
-\r
-/** @} //Peripheral Basic_Timer\r
- */\r
-\r
+++ /dev/null
-/*\r
- **********************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
- **********************************************************************************\r
- * common.h\r
- * This is the header file including common headers from various modules\r
- **********************************************************************************\r
- * $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $\r
- * Description: added ict module\r
- **********************************************************************************\r
- * #xx\r
- **********************************************************************************\r
- * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common.h $\r
- */\r
-\r
-/*********************************************************************************/\r
-/** @defgroup common common\r
- * @{\r
- */\r
-\r
-/** @file common.h\r
-* \brief header file including common headers from various modules\r
-* \author App Firmware Team\r
-* \r
-**********************************************************************************/\r
-#ifndef _COMMON_H_\r
-#define _COMMON_H_\r
-\r
-// Include common headers from various modules\r
-// !!! The include order is important !!!\r
-#include "cfg.h"\r
-#include "platform.h"\r
-#include "MCHP_CEC1302.h"\r
-#include "ARM_REG.h"\r
-/* Cortex-M4 processor and core peripherals */\r
-#include "core_cm4.h" \r
-#include "MEC1322.h"\r
-\r
-#include "defs.h"\r
-#include "string.h"\r
-\r
-#include "kernel.h"\r
-#include "..\system\system.h"\r
-#include "..\debug\trace.h"\r
-#include "..\interrupt\interrupt.h"\r
-#include "..\timer\timer_app.h"\r
-\r
-#include "cec1302_crypto_api.h"\r
-\r
-#endif /*_COMMON_H_*/\r
-\r
-/** @}\r
- */\r
-\r
-\r
+++ /dev/null
-/*\r
- **********************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
- **********************************************************************************\r
- * common.h\r
- * This is the header file including common headers from various modules\r
- **********************************************************************************\r
- * $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $\r
- * Description: added ict module\r
- **********************************************************************************\r
- * #xx\r
- **********************************************************************************\r
- * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common_lib.h $\r
- */\r
-\r
-/*********************************************************************************/\r
-/** @defgroup common common\r
- * @{\r
- */\r
-\r
-/** @file common.h\r
-* \brief header file including common headers from various modules\r
-* \author App Firmware Team\r
-* \r
-**********************************************************************************/\r
-#ifndef _COMMON_LIB_H_\r
-#define _COMMON_LIB_H_\r
-\r
-// Include common headers from various modules\r
-// !!! The include order is important !!!\r
-#include "platform.h"\r
-#include "ARM_REG.h"\r
-#include "MCHP_CEC1302.h"\r
-/* Cortex-M4 processor and core peripherals */\r
-#include "core_cm4.h" \r
-#include "MEC1322.h"\r
-#include "defs.h"\r
-#include "string.h"\r
-//_RB_#include "build.h"\r
-//_RB_#include "..\system\system.h"\r
-//_RB_#include "..\debug\trace.h"\r
-#include <stdbool.h>\r
-#endif /*_COMMON_LIB_H_*/\r
-\r
-/** @}\r
- */\r
-\r
-\r
+++ /dev/null
-/*\r
- **********************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
- **********************************************************************************\r
- * defs.h\r
- * This is the definition header file for generic usages\r
- **********************************************************************************\r
- * #xx\r
- **********************************************************************************\r
- * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/defs.h $\r
- */\r
-\r
-\r
-/*********************************************************************************/\r
-/** @defgroup defs defs\r
- * @{\r
- */\r
-\r
-/** @file defs.h\r
-* \brief definition header file for generic usages\r
-* \author App Firmware Team\r
-* \r
-**********************************************************************************/\r
-#ifndef _DEFS_H_\r
-#define _DEFS_H_\r
-\r
-/* bit operation MACRO, xvar could be byte, word or dword */\r
-#define mSET_BIT(x, xvar) ( xvar |= x )\r
-#define mCLR_BIT(x, xvar) ( xvar &= ~x )\r
-#define mGET_BIT(x, xvar) ( xvar & x )\r
-#define mCLR_SRC_BIT(x, xvar) ( xvar = x )\r
-#define mTOGGLE_BIT(x, xvar) {if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}}\r
-\r
-#endif /*_DEFS_H_*/\r
-\r
-/** @}\r
- */\r
-\r
+++ /dev/null
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/12/17 01:09:00 $ \r
-$Author: snakka $\r
-Last Change: Updated for peripheral functions prefix p_\r
-******************************************************************************/\r
-/** @file btimer.h\r
-* \brief Hibernation Timer Peripheral Header file\r
-* \author jvasanth\r
-* \r
-* This file is the header file for Hibernation Timer Peripheral \r
-******************************************************************************/\r
-\r
-/** @defgroup Hibernation_Timer\r
- * @{\r
- */\r
-\r
-#ifndef _HTIMER_H\r
-#define _HTIMER_H\r
-\r
-/******************************************************************************/\r
-/** Logical Timer ID for APIs.\r
- * This is the timer IDs passed to Hibernation Timer function calls \r
- *******************************************************************************/\r
-enum _PID_HTIMER_\r
-{\r
- PID_HTIMER_0, \r
- PID_HTIMER_MAX \r
-};\r
-\r
-#define HTIMER_MAX_INSTANCE PID_HTIMER_MAX\r
-\r
-/* -------------------------------------------------------------------- */\r
-/* Hibernation Timer APIs */\r
-/* -------------------------------------------------------------------- */\r
-/** Enables hibernation timer\r
- * @param htimer_id Hibernation Timer ID\r
- * @param preload_value - 16-bit preload value \r
- * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
- * 1 - resolution of 0.125s per LSB\r
- */\r
-void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode);\r
-\r
-/** Disables the hibernation timer by programming the prelaod value as 0\r
- * @param htimer_id Hibernation Timer ID \r
- */\r
-void htimer_disable(uint8_t htimer_id);\r
-\r
-\r
-/** Reloads new preload value for the hibernation timer\r
- * @param htimer_id Hibernation Timer ID\r
- * @param reload_value - 16-bit preload value \r
- */\r
-void htimer_reload(uint8_t htimer_id, uint16_t reload_value);\r
-\r
-\r
-/* -------------------------------------------------------------------- */\r
-/* Hibernation Timer Peripheral Functions */\r
-/* -------------------------------------------------------------------- */\r
-/** Sets hibernation timer preload value\r
- * @param htimer_id Hibernation Timer ID\r
- * @param preload_value - 16-bit preload value \r
- */\r
-void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value);\r
-\r
-/*_RB_ Added by RB. */\r
-uint16_t p_htimer_preload_get(uint8_t htimer_id);\r
-\r
-/** Sets hibernation timer resolution\r
- * @param htimer_id Hibernation Timer ID\r
- * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
- * 1 - resolution of 0.125s per LSB\r
- */\r
-void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode);\r
-\r
-\r
-/** Returns the Hibernation Timer current count value\r
- * @param htimer_id Hibernation Timer ID\r
- * @return 16-bit count value \r
- */\r
-uint16_t p_htimer_count_get(uint8_t htimer_id);\r
-\r
-\r
-#endif // #ifndef _HTIMER_H\r
-\r
-/* end htimer.h */\r
-\r
-/** @} //Peripherals Hibernation_Timer\r
- */\r
-\r
+++ /dev/null
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/12/17 01:09:00 $ \r
-$Author: snakka $\r
-Last Change: Updated for peripheral functions prefix p_\r
-******************************************************************************/\r
-/** @file btimer_perphl.c\r
-* \brief Hibernation Timer API Source file\r
-* \author jvasanth\r
-* \r
-* This file implements Hibernation Timer APIs \r
-******************************************************************************/\r
-\r
-/** @defgroup Hibernation_Timer\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "htimer.h"\r
-\r
-#ifdef PLIB_HTIMER_CHECK_ID\r
-\r
-/** Local helper that checks if logical Timer ID is valid. \r
- * @param htimer_id Hibernation Timer ID \r
- * @return uint8_t Non-zero(VALID), 0(Invalid)\r
- */\r
-static uint8_t htmr_valid(uint8_t htimer_id)\r
-{\r
- if ( htimer_id < (PID_HTIMER_MAX ) ) {\r
- return 1;\r
- }\r
- return 0;\r
-}\r
-\r
-#else\r
-\r
-\r
-/** This version of tmr_valid skips checking always returning 1. \r
- * Compiler may optimize it out.\r
- * @param htimer_id Hibernation Timer ID\r
- * @return uint8_t 1(VALID) \r
- */\r
-static uint8_t htmr_valid(uint8_t htimer_id) { return 1; }\r
-\r
-#endif\r
-\r
-\r
-/** Enables hibernation timer\r
- * @param htimer_id Hibernation Timer ID\r
- * @param preload_value - 16-bit preload value \r
- * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
- * 1 - resolution of 0.125s per LSB\r
- */\r
-void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode)\r
-{\r
- if (htmr_valid(htimer_id)) \r
- {\r
- p_htimer_preload_set(htimer_id, preload_value);\r
- \r
- p_htimer_resolution_set(htimer_id, resolution_mode);\r
- } \r
-}\r
-\r
-/** Disables the hibernation timer by programming the prelaod value as 0\r
- * @param htimer_id Hibernation Timer ID \r
- */\r
-void htimer_disable(uint8_t htimer_id)\r
-{ \r
- if (htmr_valid(htimer_id)) \r
- {\r
- p_htimer_preload_set(htimer_id, 0);\r
- } \r
-}\r
-\r
-/** Reloads new preload value for the hibernation timer\r
- * @param htimer_id Hibernation Timer ID\r
- * @param reload_value - 16-bit preload value \r
- */\r
-void htimer_reload(uint8_t htimer_id, uint16_t reload_value)\r
-{ \r
- if ( htmr_valid(htimer_id)) \r
- {\r
- p_htimer_preload_set(htimer_id, reload_value);\r
- } \r
-}\r
-\r
-/* end htimer_api.c */\r
-\r
-/** @} //APIs Hibernation_Timer\r
- */\r
-\r
+++ /dev/null
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/12/17 01:09:00 $ \r
-$Author: snakka $\r
-Last Change: Updated for peripheral functions prefix p_\r
-******************************************************************************/\r
-/** @file btimer_perphl.c\r
-* \brief Hibernation Timer Peripheral Source file\r
-* \author jvasanth\r
-* \r
-* This file implements Hibernation Timer Peripheral functions \r
-******************************************************************************/\r
-\r
-/** @defgroup Hibernation_Timer\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "htimer.h"\r
-\r
-/** Hibernation Timer Instance base addresses */\r
-static HTM_Type * const htmr_inst[HTIMER_MAX_INSTANCE] = {\r
- CEC1302_HTM \r
-};\r
-\r
-/** Sets hibernation timer preload value\r
- * @param htimer_id Hibernation Timer ID\r
- * @param preload_value - 16-bit preload value \r
- * @note Setting the preload with a non-zero value starts \r
- * the hibernation timer to down count. Setting the preload \r
- * to 0 disables the hibernation counter\r
- */\r
-void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value)\r
-{\r
- htmr_inst[htimer_id]->PRELOAD = preload_value; \r
-}\r
-\r
-/** Sets hibernation timer resolution\r
- * @param htimer_id Hibernation Timer ID\r
- * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
- * 1 - resolution of 0.125s per LSB\r
- */\r
-void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode)\r
-{\r
- htmr_inst[htimer_id]->CONTROL = resolution_mode; \r
-}\r
-\r
-/** Returns the Hibernation Timer current count value\r
- * @param htimer_id Hibernation Timer ID\r
- * @return 16-bit count value \r
- */\r
-uint16_t p_htimer_count_get(uint8_t htimer_id)\r
-{\r
- uint16_t htimer_count;\r
- \r
- htimer_count = htmr_inst[htimer_id]->COUNT;\r
- \r
- return htimer_count;\r
-}\r
-\r
-/*_RB_ Added by RB. */\r
-uint16_t p_htimer_preload_get(uint8_t htimer_id)\r
-{\r
- return htmr_inst[htimer_id]->PRELOAD;\r
-}\r
-\r
-\r
-/* end htimer_perphl.c */\r
-\r
-/** @} //Peripheral Hibernation_Timer\r
- */\r
-\r
+++ /dev/null
-/****************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-*/\r
-\r
-/** @defgroup interrupt interrupt\r
- * @{\r
- */\r
-/** @file interrupt.h\r
- \brief This is the header file for interrupt.c\r
- This program is designed to allow the other C programs to be able to use this component\r
-\r
- There are entry points for all C wrapper API implementation\r
-\r
-<b>Platform:</b> This is ARC-based component \r
-\r
-<b>Toolset:</b> Metaware IDE(8.5.1)\r
-<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
-\r
-/*******************************************************************************\r
- * SMSC version control information (Perforce):\r
- *\r
- * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/kernel/skern/source/interrupt/interrupt.h $\r
- * REVISION: $Revision: #1 $\r
- * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
- * AUTHOR: $Author: akrishnan $\r
- *\r
- * Revision history (latest first):\r
- * #xx\r
- ***********************************************************************************\r
- */\r
-\r
-#ifndef _INTERRUPT_H_\r
-#define _INTERRUPT_H_\r
-\r
-\r
-/* public function prototypes */\r
-void interrupt_block_init(void);\r
-void null_handler(void);\r
-\r
-/* macro for interrupt control */\r
-/* 16-bit timers interrupt control */\r
-#define sbit_TIMER0 ( 1UL << 0UL )\r
-#define sbit_TIMER1 ( 1UL << 1UL )\r
-#define sbit_TIMER2 ( 1UL << 2UL )\r
-#define sbit_TIMER3 ( 1UL << 3Ul )\r
-\r
-#define disable_timer0_irq() mCLR_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_timer0_irq() mSET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_timer0_source() mCLR_SRC_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_timer0_source() mGET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-#define disable_timer1_irq() mCLR_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_timer1_irq() mSET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_timer1_source() mCLR_SRC_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_timer1_source() mGET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-#define disable_timer2_irq() mCLR_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_timer2_irq() mSET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_timer2_source() mCLR_SRC_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_timer2_source() mGET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-#define disable_timer3_irq() mCLR_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_timer3_irq() mSET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_timer3_source() mCLR_SRC_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_timer3_source() mGET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-\r
-/* hibernation timers interrupt control */\r
-#define sbit_HTIMER0 ( 1UL << 20 )\r
-#define sbit_HTIMER1 b_bit14\r
-\r
-#define disable_htimer0_irq() mCLR_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define enable_htimer0_irq() mSET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define clear_htimer0_source() mCLR_SRC_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE)\r
-#define get_htimer0_source() mGET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE)\r
-\r
-#define disable_htimer1_irq() mCLR_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_htimer1_irq() mSET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_htimer1_source() mCLR_SRC_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_htimer1_source() mGET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-/* RTC interrupt control */\r
-#define b_bit18 (1 << 18)\r
-#define b_bit19 (1 << 19)\r
-#define sbit_RTC_INT b_bit18\r
-#define disable_rtc_irq() mCLR_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define enable_rtc_irq() mSET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define clear_rtc_irq_source() mCLR_SRC_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define get_rtc_irq_source() mGET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-/* RTC alarm interrupt control */\r
-#define sbit_RTC_ALM_INT b_bit19\r
-#define disable_rtc_alm_irq() mCLR_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define enable_rtc_alm_irq() mSET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define clear_rtc_irq_alm_source() mCLR_SRC_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-#define get_rtc_irq_alm_source() mGET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
-\r
-/* week timer interrupt control */\r
-#define sbit_WKTIMER b_bit7\r
-\r
-#define disable_wktimer_irq() mCLR_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_wktimer_irq() mSET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_wktimer_source() mCLR_SRC_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_wktimer_source() mGET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-\r
-/* scan matrix interrupt control */\r
-#define sbit_SCANNER b_bit16\r
-#define disable_scanner_irq() mCLR_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define enable_scanner_irq() mSET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define clear_scanner_source() mCLR_SRC_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE)\r
-#define get_scanner_source() mGET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE)\r
-\r
-\r
-/* PS2 interrupt control */\r
-/* PS2 activity interrupt */\r
-#define sbit_PS2_ACT_0 b_bit13\r
-#define sbit_PS2_ACT_1 b_bit14\r
-#define sbit_PS2_ACT_2 b_bit15\r
-/* PS2 wakeup interrupt: detect start bit */\r
-#define sbit_PS2_WK_0A b_bit17\r
-#define sbit_PS2_WK_1B b_bit20\r
-#define sbit_PS2_WK_2 b_bit21\r
-\r
-/* PS2 activity interrupt control */\r
-#define disable_ps2_act_0_irq() mCLR_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_act_0_irq() mSET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_act_0_source() mCLR_SRC_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_act_0_source() mGET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-#define disable_ps2_act_1_irq() mCLR_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_act_1_irq() mSET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_act_1_source() mCLR_SRC_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_act_1_source() mGET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-#define disable_ps2_act_2_irq() mCLR_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_act_2_irq() mSET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_act_2_source() mCLR_SRC_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_act_2_source() mGET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-/* PS2 wakeup interrupt control */\r
-#define disable_ps2_wk_0_irq() mCLR_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_wk_0_irq() mSET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_wk_0_source() mCLR_SRC_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_wk_0_source() mGET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-#define disable_ps2_wk_1_irq() mCLR_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_wk_1_irq() mSET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_wk_1_source() mCLR_SRC_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_wk_1_source() mGET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-#define disable_ps2_wk_2_irq() mCLR_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define enable_ps2_wk_2_irq() mSET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
-#define clear_ps2_wk_2_source() mCLR_SRC_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE)\r
-#define get_ps2_wk_2_source() mGET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE)\r
-\r
-\r
-/* ICT interrupt control */\r
-/* capture 0~5 interrupt */\r
-#define sbit_ICT_CAPTURE0 b_bit17\r
-#define sbit_ICT_CAPTURE1 b_bit18\r
-#define sbit_ICT_CAPTURE2 b_bit19\r
-#define sbit_ICT_CAPTURE3 b_bit20\r
-#define sbit_ICT_CAPTURE4 b_bit21\r
-#define sbit_ICT_CAPTURE5 b_bit22\r
-\r
-/* capture 0 interrupt control */\r
-#define disable_capture0_irq() mCLR_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define enable_capture0_irq() mSET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET)\r
-#define clear_capture0_source() mCLR_SRC_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE)\r
-#define get_capture0_source() mGET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE)\r
-\r
-\r
-/* SMBus interrupt control */\r
-\r
-\r
-/* GPIO interrupt control */\r
-\r
-\r
-/* BC link interrupt control */\r
-/* bclink A~D interrupt */\r
-#define sbit_BCLINK_A_BUSY b_bit0\r
-#define sbit_BCLINK_A_ERR b_bit1\r
-#define sbit_BCLINK_A_INT b_bit2\r
-#define sbit_BCLINK_B_BUSY b_bit3\r
-#define sbit_BCLINK_B_ERR b_bit4\r
-#define sbit_BCLINK_B_INT b_bit5\r
-#define sbit_BCLINK_C_BUSY b_bit6\r
-#define sbit_BCLINK_C_ERR b_bit7\r
-#define sbit_BCLINK_C_INT b_bit8\r
-#define sbit_BCLINK_D_BUSY b_bit9\r
-#define sbit_BCLINK_D_ERR b_bit10\r
-#define sbit_BCLINK_D_INT b_bit11\r
-\r
-/* bclink B interrupt control */\r
-#define disable_bclink_b_busy_irq() mCLR_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define enable_bclink_b_busy_irq() mSET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define clear_bclink_b_busy_source() mCLR_SRC_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE)\r
-#define get_bclink_b_busy_source() mGET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE)\r
-\r
-#define disable_bclink_b_err_irq() mCLR_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define enable_bclink_b_err_irq() mSET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define clear_bclink_b_err_source() mCLR_SRC_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE)\r
-#define get_bclink_b_err_source() mGET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE)\r
-\r
-#define disable_bclink_b_int_irq() mCLR_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define enable_bclink_b_int_irq() mSET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET)\r
-#define clear_bclink_b_int_source() mCLR_SRC_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE)\r
-#define get_bclink_b_int_source() mGET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE)\r
-\r
-/* UART interrupt control */\r
-#define sbit_UART_INT b_bit0\r
-\r
-#define disable_uart_irq() mCLR_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET)\r
-#define enable_uart_irq() mSET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET)\r
-#define clear_uart_irq_source() mCLR_SRC_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE)\r
-#define get_uart_irq_source() mGET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE)\r
-\r
-// GIRQ IDs for EC Interrupt Aggregator\r
-enum MEC_GIRQ_IDS\r
-{\r
- MEC_GIRQ08_ID = 0,\r
- MEC_GIRQ09_ID, \r
- MEC_GIRQ10_ID, \r
- MEC_GIRQ11_ID, \r
- MEC_GIRQ12_ID, \r
- MEC_GIRQ13_ID, \r
- MEC_GIRQ14_ID, \r
- MEC_GIRQ15_ID, \r
- MEC_GIRQ16_ID, \r
- MEC_GIRQ17_ID, \r
- MEC_GIRQ18_ID, \r
- MEC_GIRQ19_ID, \r
- MEC_GIRQ20_ID, \r
- MEC_GIRQ21_ID, \r
- MEC_GIRQ22_ID, \r
- MEC_GIRQ23_ID, \r
- MEC_GIRQ_ID_MAX\r
-};\r
-\r
-//Bitmask of GIRQ in ECIA Block Registers\r
-#define MEC_GIRQ08_BITMASK (1UL << (MEC_GIRQ08_ID + 8))\r
-#define MEC_GIRQ09_BITMASK (1UL << (MEC_GIRQ09_ID + 8)) \r
-#define MEC_GIRQ10_BITMASK (1UL << (MEC_GIRQ10_ID + 8)) \r
-#define MEC_GIRQ11_BITMASK (1UL << (MEC_GIRQ11_ID + 8)) \r
-#define MEC_GIRQ12_BITMASK (1UL << (MEC_GIRQ12_ID + 8)) \r
-#define MEC_GIRQ13_BITMASK (1UL << (MEC_GIRQ13_ID + 8)) \r
-#define MEC_GIRQ14_BITMASK (1UL << (MEC_GIRQ14_ID + 8)) \r
-#define MEC_GIRQ15_BITMASK (1UL << (MEC_GIRQ15_ID + 8)) \r
-#define MEC_GIRQ16_BITMASK (1UL << (MEC_GIRQ16_ID + 8)) \r
-#define MEC_GIRQ17_BITMASK (1UL << (MEC_GIRQ17_ID + 8)) \r
-#define MEC_GIRQ18_BITMASK (1UL << (MEC_GIRQ18_ID + 8)) \r
-#define MEC_GIRQ19_BITMASK (1UL << (MEC_GIRQ19_ID + 8)) \r
-#define MEC_GIRQ20_BITMASK (1UL << (MEC_GIRQ20_ID + 8)) \r
-#define MEC_GIRQ21_BITMASK (1UL << (MEC_GIRQ21_ID + 8)) \r
-#define MEC_GIRQ22_BITMASK (1UL << (MEC_GIRQ22_ID + 8)) \r
-#define MEC_GIRQ23_BITMASK (1UL << (MEC_GIRQ23_ID + 8)) \r
-\r
-#define INTERRUPT_MODE_ALL_AGGREGATED (0u)\r
-#define INTERRUPT_MODE_DIRECT (1u)\r
-\r
-// Bit map of GIRQs whose sources can be directly connected to the NVIC\r
-// GIRQs 12 - 18, 23\r
-#define ECIA_GIRQ_DIRECT_BITMAP (0x0087F000ul)\r
-\r
-/*\r
- * n = b[7:0] = zero-based direct mapped NVIC ID\r
- * m = b[15:8] = zero-based aggregated NVIC ID\r
- * a = b[23:16] = block Aggregator register block ID\r
- * b = b[31:24] = block bit position in Aggregator registers\r
-*/\r
-#define IROUTE(b,a,m,n) (((uint32_t)(n)&0xFFul) + \\r
- (((uint32_t)(m)&0xFFul)<<8u) + \\r
- ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \\r
- (((uint32_t)(b)&0x1Ful)<<24))\r
-\r
-#define ECIA_NVIC_ID_BITPOS (0u)\r
-#define ECIA_IA_NVIC_ID_BITPOS (8u)\r
-#define ECIA_GIRQ_ID_BITPOS (16u)\r
-#define ECIA_GIRQ_BIT_BITPOS (24u)\r
-\r
-//\r
-// GIRQ08\r
-//\r
-#define GPIO_0140_IROUTE IROUTE(0,8,57,57)\r
-#define GPIO_0141_IROUTE IROUTE(1,8,57,57)\r
-#define GPIO_0142_IROUTE IROUTE(2,8,57,57)\r
-#define GPIO_0143_IROUTE IROUTE(3,8,57,57)\r
-#define GPIO_0144_IROUTE IROUTE(4,8,57,57)\r
-#define GPIO_0145_IROUTE IROUTE(5,8,57,57)\r
-#define GPIO_0147_IROUTE IROUTE(7,8,57,57)\r
-//\r
-#define GPIO_0150_IROUTE IROUTE(8,8,57,57)\r
-#define GPIO_0151_IROUTE IROUTE(9,8,57,57)\r
-#define GPIO_0152_IROUTE IROUTE(10,8,57,57)\r
-#define GPIO_0153_IROUTE IROUTE(11,8,57,57)\r
-#define GPIO_0154_IROUTE IROUTE(12,8,57,57)\r
-#define GPIO_0155_IROUTE IROUTE(13,8,57,57)\r
-#define GPIO_0156_IROUTE IROUTE(14,8,57,57)\r
-#define GPIO_0157_IROUTE IROUTE(15,8,57,57)\r
-//\r
-#define GPIO_0160_IROUTE IROUTE(16,8,57,57)\r
-#define GPIO_0161_IROUTE IROUTE(17,8,57,57)\r
-#define GPIO_0162_IROUTE IROUTE(18,8,57,57)\r
-#define GPIO_0163_IROUTE IROUTE(19,8,57,57)\r
-#define GPIO_0164_IROUTE IROUTE(20,8,57,57)\r
-#define GPIO_0165_IROUTE IROUTE(21,8,57,57)\r
-#define GPIO_0166_IROUTE IROUTE(22,8,57,57)\r
-#define GPIO_0167_IROUTE IROUTE(23,8,57,57)\r
-\r
-//\r
-// GIRQ09\r
-//\r
-#define GPIO_0100_IROUTE IROUTE(0,9,58,58)\r
-#define GPIO_0101_IROUTE IROUTE(1,9,58,58)\r
-#define GPIO_0102_IROUTE IROUTE(2,9,58,58)\r
-#define GPIO_0103_IROUTE IROUTE(3,9,58,58)\r
-#define GPIO_0104_IROUTE IROUTE(4,9,58,58)\r
-#define GPIO_0105_IROUTE IROUTE(5,9,58,58)\r
-#define GPIO_0105_IROUTE IROUTE(5,9,58,58)\r
-#define GPIO_0107_IROUTE IROUTE(7,9,58,58)\r
-//\r
-#define GPIO_0110_IROUTE IROUTE(8,9,58,58)\r
-#define GPIO_0111_IROUTE IROUTE(9,9,58,58)\r
-#define GPIO_0112_IROUTE IROUTE(10,9,58,58)\r
-#define GPIO_0113_IROUTE IROUTE(11,9,58,58)\r
-#define GPIO_0114_IROUTE IROUTE(12,9,58,58)\r
-#define GPIO_0115_IROUTE IROUTE(13,9,58,58)\r
-#define GPIO_0116_IROUTE IROUTE(14,9,58,58)\r
-#define GPIO_0117_IROUTE IROUTE(15,9,58,58)\r
-//\r
-#define GPIO_0120_IROUTE IROUTE(16,9,58,58)\r
-#define GPIO_0121_IROUTE IROUTE(17,9,58,58)\r
-#define GPIO_0122_IROUTE IROUTE(18,9,58,58)\r
-#define GPIO_0124_IROUTE IROUTE(20,9,58,58)\r
-#define GPIO_0125_IROUTE IROUTE(21,9,58,58)\r
-#define GPIO_0126_IROUTE IROUTE(22,9,58,58)\r
-#define GPIO_0127_IROUTE IROUTE(23,9,58,58)\r
-//\r
-#define GPIO_0130_IROUTE IROUTE(24,9,58,58)\r
-#define GPIO_0131_IROUTE IROUTE(25,9,58,58)\r
-#define GPIO_0132_IROUTE IROUTE(26,9,58,58)\r
-#define GPIO_0133_IROUTE IROUTE(27,9,58,58)\r
-#define GPIO_0134_IROUTE IROUTE(28,9,58,58)\r
-#define GPIO_0135_IROUTE IROUTE(29,9,58,58)\r
-#define GPIO_0136_IROUTE IROUTE(30,9,58,58)\r
-\r
-//\r
-// GIRQ10\r
-//\r
-#define GPIO_0040_IROUTE IROUTE(0,10,59,59)\r
-#define GPIO_0041_IROUTE IROUTE(1,10,59,59)\r
-#define GPIO_0042_IROUTE IROUTE(2,10,59,59)\r
-#define GPIO_0043_IROUTE IROUTE(3,10,59,59)\r
-#define GPIO_0044_IROUTE IROUTE(4,10,59,59)\r
-#define GPIO_0045_IROUTE IROUTE(5,10,59,59)\r
-#define GPIO_0045_IROUTE IROUTE(5,10,59,59)\r
-#define GPIO_0047_IROUTE IROUTE(7,10,59,59)\r
-//\r
-#define GPIO_0050_IROUTE IROUTE(8,10,59,59)\r
-#define GPIO_0051_IROUTE IROUTE(9,10,59,59)\r
-#define GPIO_0052_IROUTE IROUTE(10,10,59,59)\r
-#define GPIO_0053_IROUTE IROUTE(11,10,59,59)\r
-#define GPIO_0054_IROUTE IROUTE(12,10,59,59)\r
-#define GPIO_0055_IROUTE IROUTE(13,10,59,59)\r
-#define GPIO_0056_IROUTE IROUTE(14,10,59,59)\r
-#define GPIO_0057_IROUTE IROUTE(15,10,59,59)\r
-//\r
-#define GPIO_0060_IROUTE IROUTE(16,10,59,59)\r
-#define GPIO_0061_IROUTE IROUTE(17,10,59,59)\r
-#define GPIO_0062_IROUTE IROUTE(18,10,59,59)\r
-#define GPIO_0063_IROUTE IROUTE(19,10,59,59)\r
-#define GPIO_0064_IROUTE IROUTE(20,10,59,59)\r
-#define GPIO_0065_IROUTE IROUTE(21,10,59,59)\r
-#define GPIO_0066_IROUTE IROUTE(22,10,59,59)\r
-#define GPIO_0067_IROUTE IROUTE(23,10,59,59)\r
-//\r
-#define GPIO_0070_IROUTE IROUTE(24,10,59,59)\r
-#define GPIO_0071_IROUTE IROUTE(25,10,59,59)\r
-#define GPIO_0072_IROUTE IROUTE(26,10,59,59)\r
-#define GPIO_0073_IROUTE IROUTE(27,10,59,59)\r
-#define GPIO_0074_IROUTE IROUTE(28,10,59,59)\r
-#define GPIO_0075_IROUTE IROUTE(29,10,59,59)\r
-#define GPIO_0076_IROUTE IROUTE(30,10,59,59)\r
-\r
-//\r
-// GIRQ11\r
-//\r
-#define GPIO_0000_IROUTE IROUTE(0,11,60,60)\r
-#define GPIO_0001_IROUTE IROUTE(1,11,60,60)\r
-#define GPIO_0002_IROUTE IROUTE(2,11,60,60)\r
-#define GPIO_0003_IROUTE IROUTE(3,11,60,60)\r
-#define GPIO_0004_IROUTE IROUTE(4,11,60,60)\r
-#define GPIO_0005_IROUTE IROUTE(5,11,60,60)\r
-#define GPIO_0006_IROUTE IROUTE(6,11,60,60)\r
-#define GPIO_0007_IROUTE IROUTE(7,11,60,60)\r
-//\r
-#define GPIO_0010_IROUTE IROUTE(8,11,60,60)\r
-#define GPIO_0011_IROUTE IROUTE(9,11,60,60)\r
-#define GPIO_0012_IROUTE IROUTE(10,11,60,60)\r
-#define GPIO_0013_IROUTE IROUTE(11,11,60,60)\r
-#define GPIO_0014_IROUTE IROUTE(12,11,60,60)\r
-#define GPIO_0015_IROUTE IROUTE(13,11,60,60)\r
-#define GPIO_0016_IROUTE IROUTE(14,11,60,60)\r
-#define GPIO_0017_IROUTE IROUTE(15,11,60,60)\r
-//\r
-#define GPIO_0020_IROUTE IROUTE(16,11,60,60)\r
-#define GPIO_0021_IROUTE IROUTE(17,11,60,60)\r
-#define GPIO_0022_IROUTE IROUTE(18,11,60,60)\r
-#define GPIO_0023_IROUTE IROUTE(19,11,60,60)\r
-#define GPIO_0024_IROUTE IROUTE(20,11,60,60)\r
-#define GPIO_0025_IROUTE IROUTE(21,11,60,60)\r
-#define GPIO_0026_IROUTE IROUTE(22,11,60,60)\r
-#define GPIO_0027_IROUTE IROUTE(23,11,60,60)\r
-//\r
-#define GPIO_0030_IROUTE IROUTE(24,11,60,60)\r
-#define GPIO_0031_IROUTE IROUTE(25,11,60,60)\r
-#define GPIO_0032_IROUTE IROUTE(26,11,60,60)\r
-#define GPIO_0033_IROUTE IROUTE(27,11,60,60)\r
-#define GPIO_0034_IROUTE IROUTE(28,11,60,60)\r
-#define GPIO_0035_IROUTE IROUTE(29,11,60,60)\r
-#define GPIO_0036_IROUTE IROUTE(30,11,60,60)\r
-\r
-//\r
-// GIRQ12\r
-//\r
-#define SMB0_IROUTE IROUTE(0,12,61,0)\r
-#define SMB1_IROUTE IROUTE(1,12,61,1)\r
-#define SMB2_IROUTE IROUTE(2,12,61,2)\r
-#define SMB3_IROUTE IROUTE(3,12,61,3)\r
-// SMB wakes have no direct connection to NVIC, always aggregated\r
-#define SMB0_WAKE_IROUTE IROUTE(4,12,61,61)\r
-#define SMB1_WAKE_IROUTE IROUTE(5,12,61,61)\r
-#define SMB2_WAKE_IROUTE IROUTE(6,12,61,61)\r
-#define SMB3_WAKE_IROUTE IROUTE(7,12,61,61)\r
-#define SMB4_WAKE_IROUTE IROUTE(8,12,61,61)\r
-\r
-//\r
-// GIRQ13\r
-//\r
-#define DMA0_IROUTE IROUTE(16,13,62,4)\r
-#define DMA1_IROUTE IROUTE(17,13,62,5)\r
-#define DMA2_IROUTE IROUTE(18,13,62,6)\r
-#define DMA3_IROUTE IROUTE(19,13,62,7)\r
-#define DMA4_IROUTE IROUTE(20,13,62,8)\r
-#define DMA5_IROUTE IROUTE(21,13,62,9)\r
-#define DMA6_IROUTE IROUTE(22,13,62,10)\r
-#define DMA7_IROUTE IROUTE(23,13,62,11)\r
-#define DMA8_IROUTE IROUTE(24,13,62,81)\r
-#define DMA9_IROUTE IROUTE(25,13,62,82)\r
-#define DMA10_IROUTE IROUTE(26,13,62,83)\r
-#define DMA11_IROUTE IROUTE(27,13,62,84)\r
-\r
-//\r
-// GIRQ14\r
-//\r
-#define LPC_BERR_IROUTE IROUTE(2,14,63,12)\r
-\r
-//\r
-// GIRQ15\r
-//\r
-#define UART0_IROUTE IROUTE(0,15,64,13)\r
-#define EMI0_IROUTE IROUTE(2,15,64,14)\r
-#define ACPI_EC0_IBF_IROUTE IROUTE(6,15,64,15)\r
-#define ACPI_EC0_OBF_IROUTE IROUTE(7,15,64,16)\r
-#define ACPI_EC1_IBF_IROUTE IROUTE(8,15,64,17)\r
-#define ACPI_EC1_OBF_IROUTE IROUTE(9,15,64,18)\r
-#define ACPI_PM1_CTL_IROUTE IROUTE(10,15,64,19)\r
-#define ACPI_PM1_EN_IROUTE IROUTE(11,15,64,20)\r
-#define ACPI_PM1_STS_IROUTE IROUTE(12,15,64,21)\r
-#define EM8042_OBF_IROUTE IROUTE(13,15,64,22)\r
-#define EM8042_IBF_IROUTE IROUTE(14,15,64,23)\r
-#define MBOX_IROUTE IROUTE(15,15,64,24)\r
-#define MBOX_DATA_IROUTE IROUTE(16,15,64,40) \r
-\r
-//\r
-// GIRQ16\r
-//\r
-#define PECI_IROUTE IROUTE(3,16,65,25)\r
-\r
-//\r
-// GIRQ17\r
-//\r
-#define TACH0_IROUTE IROUTE(0,17,66,26)\r
-#define TACH1_IROUTE IROUTE(1,17,66,27)\r
-#define PS2_0_WAKE_IROUTE IROUTE(2,17,66,66)\r
-#define PS2_1_WAKE_IROUTE IROUTE(3,17,66,66)\r
-#define PS2_2_WAKE_IROUTE IROUTE(4,17,66,66)\r
-#define PS2_3_WAKE_IROUTE IROUTE(5,17,66,66)\r
-#define BC_WAKE_IROUTE IROUTE(6,17,66,66)\r
-#define ADC_SNGL_IROUTE IROUTE(10,17,66,28)\r
-#define ADC_RPT_IROUTE IROUTE(11,17,66,29)\r
-#define ADC2PWM1_IROUTE IROUTE(12,17,66,30)\r
-#define ADC2PWM2_IROUTE IROUTE(13,17,66,31)\r
-#define PS2_0_IROUTE IROUTE(14,17,66,32)\r
-#define PS2_1_IROUTE IROUTE(15,17,66,33)\r
-#define PS2_2_IROUTE IROUTE(16,17,66,34)\r
-#define PS2_3_IROUTE IROUTE(17,17,66,35)\r
-#define RTC_IROUTE IROUTE(18,17,66,91)\r
-#define RTC_ALARM_IROUTE IROUTE(19,17,66,92)\r
-#define HTIMER_IROUTE IROUTE(20,17,66,38)\r
-#define KSC_IROUTE IROUTE(21,17,66,39)\r
-#define KSC_WAKE_IROUTE IROUTE(22,17,66,66)\r
-#define RPM_STALL_IROUTE IROUTE(23,17,66,41)\r
-#define RPM_SPIN_IROUTE IROUTE(24,17,66,42)\r
-#define PFR_IROUTE IROUTE(25,17,66,43)\r
-#define LED0_IROUTE IROUTE(26,17,66,44)\r
-#define LED1_IROUTE IROUTE(27,17,66,45)\r
-#define LED2_IROUTE IROUTE(28,17,66,46)\r
-#define BCM_ERR_IROUTE IROUTE(29,17,66,47)\r
-#define BCM_BUSY_IROUTE IROUTE(30,17,66,48)\r
-\r
-//\r
-// GIRQ18\r
-//\r
-#define SPI0_TX_IROUTE IROUTE(0,18,67,36)\r
-#define SPI0_RX_IROUTE IROUTE(1,18,67,37)\r
-#define SPI1_TX_IROUTE IROUTE(2,18,67,55)\r
-#define SPI1_RX_IROUTE IROUTE(3,18,67,56)\r
-#define LED3_IROUTE IROUTE(4,18,67,85)\r
-#define PKE_ERR_IROUTE IROUTE(5,18,67,86)\r
-#define PKE_END_IROUTE IROUTE(6,18,67,87)\r
-#define NDRNG_IROUTE IROUTE(7,18,67,88)\r
-#define AES_IROUTE IROUTE(8,18,67,89)\r
-#define HASH_IROUTE IROUTE(9,18,67,90)\r
-\r
-//\r
-// GIRQ19, Aggregated only\r
-//\r
-#define LRESET_IROUTE IROUTE(0,19,68,68)\r
-#define VCC_PWRGD_IROUTE IROUTE(1,19,68,68)\r
-\r
-//\r
-// GIRQ20, Aggregated only\r
-//\r
-#define GPIO_0200_IROUTE IROUTE(0,20,69,69)\r
-#define GPIO_0201_IROUTE IROUTE(1,20,69,69)\r
-#define GPIO_0202_IROUTE IROUTE(2,20,69,69)\r
-#define GPIO_0203_IROUTE IROUTE(3,20,69,69)\r
-#define GPIO_0204_IROUTE IROUTE(4,20,69,69)\r
-#define GPIO_0206_IROUTE IROUTE(6,20,69,69)\r
-//\r
-#define GPIO_0210_IROUTE IROUTE(8,20,69,69)\r
-#define GPIO_0211_IROUTE IROUTE(9,20,69,69)\r
-#define GPIO_0212_IROUTE IROUTE(10,20,69,69)\r
-#define GPIO_0213_IROUTE IROUTE(11,20,69,69)\r
-\r
-//\r
-// GIRQ21\r
-//\r
-// No sources\r
-\r
-//\r
-// GIRQ22\r
-//\r
-// No sources\r
-\r
-//\r
-// GIRQ23\r
-//\r
-#define BTMR0_IROUTE IROUTE(0,23,72,49)\r
-#define BTMR1_IROUTE IROUTE(1,23,72,50)\r
-#define BTMR2_IROUTE IROUTE(2,23,72,51)\r
-#define BTMR3_IROUTE IROUTE(3,23,72,52)\r
-#define BTMR4_IROUTE IROUTE(4,23,72,53)\r
-#define BTMR5_IROUTE IROUTE(5,23,72,54)\r
-\r
-// GIRQ08 Bit Positions \r
-#define GIRQ08_GPIO_0140_BITPOS (0)\r
-#define GIRQ08_GPIO_0141_BITPOS (1)\r
-#define GIRQ08_GPIO_0142_BITPOS (2)\r
-#define GIRQ08_GPIO_0143_BITPOS (3)\r
-#define GIRQ08_GPIO_0144_BITPOS (4)\r
-#define GIRQ08_GPIO_0145_BITPOS (5)\r
-//#define GIRQ08_GPIO_0146_BITPOS (6) RESERVED\r
-#define GIRQ08_GPIO_0147_BITPOS (7)\r
-//\r
-#define GIRQ08_GPIO_0150_BITPOS (8)\r
-#define GIRQ08_GPIO_0151_BITPOS (9)\r
-#define GIRQ08_GPIO_0152_BITPOS (10)\r
-#define GIRQ08_GPIO_0153_BITPOS (11)\r
-#define GIRQ08_GPIO_0154_BITPOS (12)\r
-#define GIRQ08_GPIO_0155_BITPOS (13)\r
-#define GIRQ08_GPIO_0156_BITPOS (14) \r
-#define GIRQ08_GPIO_0157_BITPOS (15)\r
-//\r
-#define GIRQ08_GPIO_0160_BITPOS (16)\r
-#define GIRQ08_GPIO_0161_BITPOS (17)\r
-#define GIRQ08_GPIO_0162_BITPOS (18)\r
-#define GIRQ08_GPIO_0163_BITPOS (19)\r
-#define GIRQ08_GPIO_0164_BITPOS (20)\r
-#define GIRQ08_GPIO_0165_BITPOS (21)\r
-#define GIRQ08_GPIO_0166_BITPOS (22) \r
-#define GIRQ08_GPIO_0167_BITPOS (23)\r
-//\r
-#define GIRQ08_MASK (0x00FFFFBFul)\r
-#define GIRQ08_WAKE_CAPABLE_MASK (0x00FFFFBFul)\r
-//\r
-\r
-// GIRQ09 Bit Positions \r
-#define GIRQ09_GPIO_0100_BITPOS (0)\r
-#define GIRQ09_GPIO_0101_BITPOS (1)\r
-#define GIRQ09_GPIO_0102_BITPOS (2)\r
-#define GIRQ09_GPIO_0103_BITPOS (3)\r
-#define GIRQ09_GPIO_0104_BITPOS (4)\r
-#define GIRQ09_GPIO_0105_BITPOS (5)\r
-#define GIRQ09_GPIO_0106_BITPOS (6) \r
-#define GIRQ09_GPIO_0107_BITPOS (7)\r
-//\r
-#define GIRQ09_GPIO_0110_BITPOS (8)\r
-#define GIRQ09_GPIO_0111_BITPOS (9)\r
-#define GIRQ09_GPIO_0112_BITPOS (10)\r
-#define GIRQ09_GPIO_0113_BITPOS (11)\r
-#define GIRQ09_GPIO_0114_BITPOS (12)\r
-#define GIRQ09_GPIO_0115_BITPOS (13)\r
-#define GIRQ09_GPIO_0116_BITPOS (14) \r
-#define GIRQ09_GPIO_0117_BITPOS (15)\r
-//\r
-#define GIRQ09_GPIO_0120_BITPOS (16)\r
-#define GIRQ09_GPIO_0121_BITPOS (17)\r
-#define GIRQ09_GPIO_0122_BITPOS (18)\r
-//#define GIRQ09_GPIO_0123_BITPOS (19) RESERVED\r
-#define GIRQ09_GPIO_0124_BITPOS (20)\r
-#define GIRQ09_GPIO_0125_BITPOS (21)\r
-#define GIRQ09_GPIO_0126_BITPOS (22) \r
-#define GIRQ09_GPIO_0127_BITPOS (23)\r
-//\r
-#define GIRQ09_GPIO_0130_BITPOS (24)\r
-#define GIRQ09_GPIO_0131_BITPOS (25)\r
-#define GIRQ09_GPIO_0132_BITPOS (26)\r
-#define GIRQ09_GPIO_0133_BITPOS (27)\r
-#define GIRQ09_GPIO_0134_BITPOS (28)\r
-#define GIRQ09_GPIO_0135_BITPOS (29)\r
-#define GIRQ09_GPIO_0136_BITPOS (30) \r
-//#define GIRQ09_GPIO_0137_BITPOS (31) RESERVED\r
-//\r
-#define GIRQ09_MASK (0x7FF7FFFFul)\r
-#define GIRQ09_WAKE_CAPABLE_MASK (0x7FF7FFFFul)\r
-//\r
-\r
-// GIRQ10 Bit Positions \r
-#define GIRQ10_GPIO_0040_BITPOS (0)\r
-#define GIRQ10_GPIO_0041_BITPOS (1)\r
-#define GIRQ10_GPIO_0042_BITPOS (2)\r
-#define GIRQ10_GPIO_0043_BITPOS (3)\r
-#define GIRQ10_GPIO_0044_BITPOS (4)\r
-#define GIRQ10_GPIO_0045_BITPOS (5)\r
-#define GIRQ10_GPIO_0046_BITPOS (6) \r
-#define GIRQ10_GPIO_0047_BITPOS (7)\r
-//\r
-#define GIRQ10_GPIO_0050_BITPOS (8)\r
-#define GIRQ10_GPIO_0051_BITPOS (9)\r
-#define GIRQ10_GPIO_0052_BITPOS (10)\r
-#define GIRQ10_GPIO_0053_BITPOS (11)\r
-#define GIRQ10_GPIO_0054_BITPOS (12)\r
-#define GIRQ10_GPIO_0055_BITPOS (13)\r
-#define GIRQ10_GPIO_0056_BITPOS (14) \r
-#define GIRQ10_GPIO_0057_BITPOS (15)\r
-//\r
-#define GIRQ10_GPIO_0060_BITPOS (16)\r
-#define GIRQ10_GPIO_0061_BITPOS (17)\r
-#define GIRQ10_GPIO_0062_BITPOS (18)\r
-#define GIRQ10_GPIO_0063_BITPOS (19)\r
-#define GIRQ10_GPIO_0064_BITPOS (20)\r
-#define GIRQ10_GPIO_0065_BITPOS (21)\r
-#define GIRQ10_GPIO_0066_BITPOS (22) \r
-#define GIRQ10_GPIO_0067_BITPOS (23)\r
-//\r
-#define GIRQ10_GPIO_0070_BITPOS (24)\r
-#define GIRQ10_GPIO_0071_BITPOS (25)\r
-#define GIRQ10_GPIO_0072_BITPOS (26)\r
-#define GIRQ10_GPIO_0073_BITPOS (27)\r
-#define GIRQ10_GPIO_0074_BITPOS (28)\r
-#define GIRQ10_GPIO_0075_BITPOS (29)\r
-#define GIRQ10_GPIO_0076_BITPOS (30) \r
-//#define GIRQ10_GPIO_0077_BITPOS (31) RESERVED\r
-//\r
-#define GIRQ10_MASK (0x7FFFFFFFul)\r
-#define GIRQ10_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
-//\r
-\r
-// GIRQ11 Bit Positions \r
-#define GIRQ11_GPIO_0000_BITPOS (0)\r
-#define GIRQ11_GPIO_0001_BITPOS (1)\r
-#define GIRQ11_GPIO_0002_BITPOS (2)\r
-#define GIRQ11_GPIO_0003_BITPOS (3)\r
-#define GIRQ11_GPIO_0004_BITPOS (4)\r
-#define GIRQ11_GPIO_0005_BITPOS (5)\r
-#define GIRQ11_GPIO_0006_BITPOS (6) \r
-#define GIRQ11_GPIO_0007_BITPOS (7)\r
-//\r
-#define GIRQ11_GPIO_0010_BITPOS (8)\r
-#define GIRQ11_GPIO_0011_BITPOS (9)\r
-#define GIRQ11_GPIO_0012_BITPOS (10)\r
-#define GIRQ11_GPIO_0013_BITPOS (11)\r
-#define GIRQ11_GPIO_0014_BITPOS (12)\r
-#define GIRQ11_GPIO_0015_BITPOS (13)\r
-#define GIRQ11_GPIO_0016_BITPOS (14) \r
-#define GIRQ11_GPIO_0017_BITPOS (15)\r
-//\r
-#define GIRQ11_GPIO_0020_BITPOS (16)\r
-#define GIRQ11_GPIO_0021_BITPOS (17)\r
-#define GIRQ11_GPIO_0022_BITPOS (18)\r
-#define GIRQ11_GPIO_0023_BITPOS (19)\r
-#define GIRQ11_GPIO_0024_BITPOS (20)\r
-#define GIRQ11_GPIO_0025_BITPOS (21)\r
-#define GIRQ11_GPIO_0026_BITPOS (22) \r
-#define GIRQ11_GPIO_0027_BITPOS (23)\r
-//\r
-#define GIRQ11_GPIO_0030_BITPOS (24)\r
-#define GIRQ11_GPIO_0031_BITPOS (25)\r
-#define GIRQ11_GPIO_0032_BITPOS (26)\r
-#define GIRQ11_GPIO_0033_BITPOS (27)\r
-#define GIRQ11_GPIO_0034_BITPOS (28)\r
-#define GIRQ11_GPIO_0035_BITPOS (29)\r
-#define GIRQ11_GPIO_0036_BITPOS (30) \r
-//#define GIRQ11_GPIO_0037_BITPOS (31) RESERVED\r
-//\r
-#define GIRQ11_MASK (0x7FFFFFFFul)\r
-#define GIRQ11_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
-//\r
-\r
-// GIRQ12 Bit Positions \r
-#define GIRQ12_SMBUS0_BITPOS (0)\r
-#define GIRQ12_SMBUS1_BITPOS (1)\r
-#define GIRQ12_SMBUS2_BITPOS (2)\r
-#define GIRQ12_SMBUS3_BITPOS (3)\r
-#define GIRQ12_SMBUS0_WAKE_BITPOS (4)\r
-#define GIRQ12_SMBUS1_WAKE_BITPOS (5)\r
-#define GIRQ12_SMBUS2_WAKE_BITPOS (6)\r
-#define GIRQ12_SMBUS3_WAKE_BITPOS (7)\r
-#define GIRQ12_SMBUS4_WAKE_BITPOS (8)\r
-// RESERVED bits[31:9]\r
-#define GIRQ12_MASK (0x01FFul)\r
-#define GIRQ12_WAKE_CAPABLE_MASK (0x01F0ul)\r
-//\r
-\r
-// GIRQ13 Bit Positions \r
-#define GIRQ13_DMA0_BITPOS (16)\r
-#define GIRQ13_DMA1_BITPOS (17)\r
-#define GIRQ13_DMA2_BITPOS (18)\r
-#define GIRQ13_DMA3_BITPOS (19)\r
-#define GIRQ13_DMA4_BITPOS (20)\r
-#define GIRQ13_DMA5_BITPOS (21)\r
-#define GIRQ13_DMA6_BITPOS (22)\r
-#define GIRQ13_DMA7_BITPOS (23)\r
-#define GIRQ13_DMA8_BITPOS (24)\r
-#define GIRQ13_DMA9_BITPOS (25)\r
-#define GIRQ13_DMA10_BITPOS (26)\r
-#define GIRQ13_DMA11_BITPOS (27)\r
-//\r
-#define GIRQ13_MASK (0x0FFF0000ul)\r
-#define GIRQ13_WAKE_CAPABLE_MASK (0x00000000ul)\r
-//\r
-\r
-// GIRQ14 Bit Positions \r
-#define GIRQ14_LPC_BITPOS (2)\r
-//\r
-#define GIRQ14_MASK (0x04ul)\r
-#define GIRQ14_WAKE_CAPABLE_MASK (0x00ul)\r
-//\r
-\r
-// GIRQ15 Bit Positions \r
-#define GIRQ15_UART0_BITPOS (0)\r
-#define GIRQ15_IMAP_BITPOS (2)\r
-#define GIRQ15_KBD_K_BITPOS (3)\r
-#define GIRQ15_KBD_M_BITPOS (4)\r
-#define GIRQ15_ACPI0_IBF_BITPOS (6)\r
-#define GIRQ15_ACPI0_OBF_BITPOS (7)\r
-#define GIRQ15_ACPI1_IBF_BITPOS (8)\r
-#define GIRQ15_ACPI1_OBF_BITPOS (9)\r
-#define GIRQ15_ACPI_PM1CTL_BITPOS (10)\r
-#define GIRQ15_ACPI_PM1EN_BITPOS (11)\r
-#define GIRQ15_ACPI_PM1STS_BITPOS (12)\r
-#define GIRQ15_MF8042_OBF_BITPOS (13)\r
-#define GIRQ15_MF8042_IBF_BITPOS (14)\r
-#define GIRQ15_MAILBOX_BITPOS (15)\r
-#define GIRQ15_MAILBOX_DATA_BITPOS (16)\r
-//\r
-#define GIRQ15_MASK (0x01FFDDul)\r
-#define GIRQ15_WAKE_CAPABLE_MASK (0x000000ul)\r
-//\r
-\r
-// GIRQ16 Bit Positions \r
-#define GIRQ16_PECI_BITPOS (3)\r
-//\r
-#define GIRQ16_MASK (0x08ul)\r
-#define GIRQ16_WAKE_CAPABLE_MASK (0x00ul)\r
-//\r
-\r
-// GIRQ17 Bit Positions \r
-#define GIRQ17_TACH0_BITPOS (0)\r
-#define GIRQ17_TACH1_BITPOS (1)\r
-#define GIRQ17_PS2_0_WAKE_BITPOS (2)\r
-#define GIRQ17_PS2_1_WAKE_BITPOS (3)\r
-#define GIRQ17_PS2_2_WAKE_BITPOS (4)\r
-#define GIRQ17_PS2_3_WAKE_BITPOS (5)\r
-#define GIRQ17_BC_WAKE_BITPOS (6)\r
-// RESERVED b[9:7]\r
-#define GIRQ17_ADC_INT0_BITPOS (10)\r
-#define GIRQ17_ADC_INT1_BITPOS (11)\r
-#define GIRQ17_V2P_INT0_BITPOS (12)\r
-#define GIRQ17_V2P_INT1_BITPOS (13)\r
-#define GIRQ17_PS2_0_BITPOS (14)\r
-#define GIRQ17_PS2_1_BITPOS (15)\r
-#define GIRQ17_PS2_2_BITPOS (16)\r
-#define GIRQ17_PS2_3_BITPOS (17)\r
-// RESERVED b[19:18]\r
-#define GIRQ17_HIBTMR_BITPOS (20)\r
-#define GIRQ17_KEY_INT_BITPOS (21)\r
-#define GIRQ17_KEY_INT_WAKE_BITPOS (22)\r
-#define GIRQ17_RPM_STALL_BITPOS (23)\r
-#define GIRQ17_RPM_SPIN_BITPOS (24)\r
-#define GIRQ17_VBAT_BITPOS (25)\r
-#define GIRQ17_LED0_BITPOS (26)\r
-#define GIRQ17_LED1_BITPOS (27)\r
-#define GIRQ17_LED2_BITPOS (28)\r
-#define GIRQ17_MBC_ERR_BITPOS (29)\r
-#define GIRQ17_MBC_BUSY_BITPOS (30)\r
-//\r
-#define GIRQ17_MASK (0x7FF3FC7Ful)\r
-#define GIRQ17_WAKE_CAPABLE_MASK (0x0230007Cul)\r
-//\r
-\r
-// GIRQ18 Bit Positions \r
-#define GIRQ18_SPI0_TX_BITPOS (0)\r
-#define GIRQ18_SPI0_RX_BITPOS (1)\r
-#define GIRQ18_SPI1_TX_BITPOS (2)\r
-#define GIRQ18_SPI1_RX_BITPOS (3)\r
-#define GIRQ18_LED3_BITPOS (4) // NVIC 85\r
-#define GIRQ18_PKE_ERR_BITPOS (5) // NVIC 86\r
-#define GIRQ18_PKE_END_BITPOS (6) // NVIC 87\r
-#define GIRQ18_TRNG_BITPOS (7) // NVIC 88\r
-#define GIRQ18_AES_BITPOS (8) // NVIC 89\r
-#define GIRQ18_HASH_BITPOS (9) // NVIC 90\r
-//\r
-#define GIRQ18_MASK (0x0FFul)\r
-#define GIRQ18_WAKE_CAPABLE_MASK (0x000ul)\r
-//\r
-\r
-// GIRQ19 Bit Positions \r
-#define GIRQ19_LRESET_BITPOS (0)\r
-#define GIRQ19_VCC_PWRGD_BITPOS (1)\r
-//\r
-#define GIRQ19_MASK (0x03ul)\r
-#define GIRQ19_WAKE_CAPABLE_MASK (0x03ul)\r
-//\r
-\r
-// GIRQ20 Bit Positions \r
-#define GIRQ20_GPIO_0200_BITPOS (0)\r
-#define GIRQ20_GPIO_0201_BITPOS (1)\r
-#define GIRQ20_GPIO_0202_BITPOS (2)\r
-#define GIRQ20_GPIO_0203_BITPOS (3)\r
-#define GIRQ20_GPIO_0204_BITPOS (4)\r
-//#define GIRQ20_GPIO_0205_BITPOS (5)\r
-#define GIRQ20_GPIO_0206_BITPOS (6)\r
-//#define GIRQ20_GPIO_0207_BITPOS (7)\r
-//\r
-#define GIRQ20_GPIO_0210_BITPOS (8)\r
-#define GIRQ20_GPIO_0211_BITPOS (9)\r
-#define GIRQ20_GPIO_0212_BITPOS (10)\r
-#define GIRQ20_GPIO_0213_BITPOS (11)\r
-// \r
-#define GIRQ20_MASK (0x0F5Ful)\r
-#define GIRQ20_WAKE_CAPABLE_MASK (0x0F5Ful)\r
-//\r
-\r
-// GIRQ21 Bit Positions \r
-#define GIRQ21_MASK (0x00ul)\r
-#define GIRQ21_WAKE_CAPABLE_MASK (0x00ul)\r
-\r
-// GIRQ22 Bit Positions \r
-#define GIRQ22_MASK (0x00ul)\r
-#define GIRQ22_WAKE_CAPABLE_MASK (0x00ul)\r
-\r
-// GIRQ23 Bit Positions \r
-#define GIRQ23_TMR0_BITPOS (0)\r
-#define GIRQ23_TMR1_BITPOS (1)\r
-#define GIRQ23_TMR2_BITPOS (2)\r
-#define GIRQ23_TMR3_BITPOS (3)\r
-#define GIRQ23_TMR4_BITPOS (4)\r
-#define GIRQ23_TMR5_BITPOS (5)\r
-//\r
-#define GIRQ23_MASK (0x03Ful)\r
-#define GIRQ23_WAKE_CAPABLE_MASK (0x000ul)\r
-//\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* NVIC,ECIA Routing Policy for Direct Mode */\r
-/* ------------------------------------------------------------------------------- */\r
-/* In Direct Mode, some interrupts could be configured to be used as aggregated.\r
- * Configuration:\r
- * 1. Always set ECS Interrupt Direct enable bit. \r
- * 2. If GIRQn aggregated set Block Enable bit.\r
- * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs.\r
- * Switching issues:\r
- * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers.\r
- * Also requires set/clear of individual NVIC Enables.\r
- * \r
- * Note: interrupt_is_girq_direct() internal function uses this policy to detect \r
- * if any interrupt is configured as direct or aggregated\r
-*/\r
-\r
-/** Initialize EC Interrupt Aggregator\r
- * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode \r
- * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated \r
- * This parameter is only applicable in direct mode.\r
- * @note All GPIO's and wake capable sources are always \r
- * aggregated! GPIO's interrupts will still work in direct mode.\r
- * Block wakes are not be routed to the processor in direct \r
- * mode. \r
- * Note2: This function disables and enables global interrupt \r
- */\r
-void interrupt_init(uint8_t mode, uint32_t girq_bitmask);\r
-\r
-/** Set interrupt routing mode to aggregated or direct. \r
- * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated \r
- * @note In direct mode, one could enable certain GIRQs as aggregated using \r
- * p_interrupt_ecia_block_enable_set function\r
- */\r
-void interrupt_mode_set(uint8_t mode);\r
-\r
-/** Clears all individual interrupts Enables and Source in ECIA,\r
- * and Clears all NVIC external enables and pending bits \r
- */\r
-void interrupt_reset(void);\r
-\r
-/** Enables interrupt for a device \r
- * @param dev_iroute - source IROUTING information \r
- * @note This function disables and enables global interrupt \r
- */\r
-void interrupt_device_enable(uint32_t dev_iroute);\r
-\r
-/** Disables interrupt for a device\r
- * @param dev_iroute - source IROUTING information \r
- * @note This function disables and enables global interrupt \r
- */\r
-void interrupt_device_disable(uint32_t dev_iroute);\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* ECIA APIs using device IROUTE() as input */ \r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Clear Source in the ECIA for the device \r
- * @param devi - device IROUTING value \r
- */\r
-void interrupt_device_ecia_source_clear(const uint32_t dev_iroute);\r
-\r
-/** Get the Source bit in the ECIA for the device \r
- * @param devi - device IROUTING value \r
- * @return 0 if source bit not set; else non-zero value\r
- */\r
-uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute);\r
-\r
-/** Get the Result bit in the ECIA for the device \r
- * @param devi - device IROUTING value \r
- * @return 0 if result bit not set; else non-zero value\r
- */\r
-uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute);\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* NVIC APIs using device IROUTE() as input */ \r
-/* ------------------------------------------------------------------------------- */\r
-/* Note that if the device interrupt is aggregated, then these APIs would affect the \r
- * NVIC corresponding to the aggregated GIRQ \r
- */\r
-\r
-/** Enable/Disable the NVIC (in the NVIC controller) for the device\r
- * @param dev_iroute : source IROUTING information (encoded in a uint32_t)\r
- * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ \r
- * @note Recommended to use interrupt_device_enable, interrupt_device_disable\r
- * to enable/disable interrupts for the device, since those APIs configure ECIA as well\r
- */\r
-void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag);\r
-\r
-/** Set NVIC priority for specified peripheral interrupt source\r
- * @param dev_iroute - source IROUTING information (encoded in a uint32_t)\r
- * @param nvic_pri - NVIC Priority\r
- * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt \r
- * sources in the GIRQ. \r
- * 2. This function disables and enables global interrupt \r
- */\r
-void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri);\r
-\r
-/** Return NVIC priority for interrupt source\r
- * @param dev_iroute - source IROUTING information \r
- * @return uint32_t NVIC priority \r
- */\r
-uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute);\r
-\r
-/** Return NVIC pending for interrupt source\r
- * @param dev_iroute - source IROUTING information \r
- * @return uint8_t 0(not pending), 1 (pending in NVIC) \r
- * \r
- */\r
-uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute);\r
-\r
-/** Set NVIC pending for interrupt source\r
- * @param dev_iroute - source IROUTING information \r
- */\r
-void interrupt_device_nvic_pending_set(const uint32_t dev_iroute);\r
-\r
-/** Clears NVIC pending for interrupt source\r
- * @param dev_iroute - source IROUTING information \r
- * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear \r
- * @note This function disables and enables global interrupt \r
- */\r
-uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute);\r
- \r
-/* ------------------------------------------------------------------------------- */\r
-/* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear *\r
- * and Status Register */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Enable specified GIRQ in ECIA block\r
- * @param girq_id - enum MEC_GIRQ_IDS \r
- */\r
- void p_interrupt_ecia_block_enable_set(uint8_t girq_id);\r
- \r
- /** Enable GIRQs in ECIA Block \r
- * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block \r
- */\r
-void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask);\r
-\r
-/** Check if specified GIRQ block enabled or not\r
- * @param girq_id - enum MEC_GIRQ_IDS \r
- * @return retVal - 1 if the particular GIRQ block enabled, else 0\r
- */\r
-uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id);\r
-\r
-/** Set all GIRQ block enables */\r
-void p_interrupt_ecia_block_enable_all_set(void);\r
-\r
-/** Clear specified GIRQ in ECIA Block \r
- * @param girq_id - enum MEC_GIRQ_IDS \r
- */\r
-void p_interrupt_ecia_block_enable_clr(uint8_t girq_id);\r
-\r
-/** Clear GIRQs in ECIA Block \r
- * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block \r
- */\r
-void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask);\r
-\r
-/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */\r
-void p_interrupt_ecia_block_enable_all_clr(void);\r
- \r
- /** Get status of GIRQ in ECIA Block\r
- * @param girq_id - enum MEC_GIRQ_IDS \r
- * @return 0 if status bit not set; else non-zero value\r
- */\r
-uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id);\r
-\r
-/** Reads the Block IRQ Vector Register\r
- * @return 32-bit value\r
- */\r
-uint32_t p_interrupt_ecia_block_irq_all_status_get(void);\r
-\r
-/* ---------------------------------------------------------------------------- */\r
-/* Peripheral Functions - Operations on GIRQx Source, Enable, Result *\r
- * and Enable Registers */\r
-/* ---------------------------------------------------------------------------- */\r
-\r
-/** Clear specified interrupt source bit in GIRQx\r
- * @param girq_id - enum MEC_GIRQ_IDS\r
- * @param bitnum -[0, 31]\r
- */\r
-void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum);\r
-\r
-/** Read the specified interrupt source bit in GIRQx\r
- * @param girq_id - enum MEC_GIRQ_IDS\r
- * @param bitnum -[0, 31]\r
- * @return 0 if source bit not set; else non-zero value\r
- */\r
-uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum);\r
-\r
-/** Enable the specified interrupt in GIRQx\r
- * girq_id - enum MEC_GIRQ_IDS\r
- * bitnum = [0, 31]\r
- */\r
-void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum);\r
-\r
-/** Disable the specified interrupt in GIRQx\r
- * girq_id - enum MEC_GIRQ_IDS\r
- * bitnum = [0, 31]\r
- */\r
-void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum);\r
-\r
-/** Read the status of the specified interrupt in GIRQx\r
- * girq_id - enum MEC_GIRQ_IDS\r
- * bitnum = [0, 31]\r
- * @return 0 if enable bit not set; else non-zero value\r
- */\r
-uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum);\r
-\r
-/** Read the result bit of the interrupt in GIRQx\r
- * @param girq_id - enum MEC_GIRQ_IDS\r
- * @param bitnum -[0, 31]\r
- * @return 0 if enable bit not set; else non-zero value\r
- */\r
-uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum);\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* Peripheral Function - Operations on all GIRQs */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Clear all aggregator GIRQn status registers */\r
-void p_interrupt_ecia_girqs_source_reset(void);\r
-\r
-/** Clear all aggregator GIRQn enables */\r
- void p_interrupt_ecia_girqs_enable_reset(void);\r
- \r
-/* ------------------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to set interrupt control */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Set interrupt control \r
- * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
- */\r
- void p_interrupt_control_set(uint8_t nvic_en_flag);\r
- \r
- /** Read interrupt control \r
- * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
- */\r
-uint8_t p_interrupt_control_get(void);\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* Peripheral Functions - NVIC */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller\r
- * @param nvic_num : NVIC number (see enum IRQn_Type)\r
- * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ\r
- * @note Application should perform this operation\r
- */\r
- void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag);\r
- \r
- /** ecia_nvic_clr_en - Clear all NVIC external enables */ \r
-void p_interrupt_nvic_extEnables_clr(void);\r
-\r
-/** Clear all NVIC external enables and pending bits */\r
-void p_interrupt_nvic_enpend_clr(void);\r
-\r
-/** Set NVIC external priorities to POR value */\r
-void p_interrupt_nvic_priorities_default_set(void);\r
-\r
-/** Set NVIC external priorities to specified priority (0 - 7)\r
- * @param zero-based 3-bit priority value: 0=highest, 7=lowest.\r
- * @note NVIC highest priority is the value 0, lowest is all 1's.\r
- * Each external interrupt has an 8-bit register and the priority \r
- * is left justified in the registers. MECxxx implements 8 priority \r
- * levels or bits [7:5] in the register. Lowest priority = 0xE0\r
- */\r
-void p_interrupt_nvic_priorities_set(uint8_t new_pri);\r
-\r
-#endif /*_INTERRUPT_H_*/\r
-\r
-/** @}\r
- */\r
-\r
-\r
-\r
+++ /dev/null
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/11/24 06:28:28 $ \r
-$Author: amohandas $\r
-Last Change: Updated for tabs\r
-******************************************************************************/\r
-/** @file pcr.h\r
-* \brief Power, Clocks, and Resets Header file\r
-* \author jvasanth\r
-* \r
-* This file is the PCR header file \r
-******************************************************************************/\r
-\r
-/** @defgroup PCR\r
- * @{\r
- */\r
-\r
-#ifndef _PCR_H\r
-#define _PCR_H\r
-\r
-\r
-/******************************************************************************/\r
-/** PCR Register IDS \r
- *******************************************************************************/\r
-enum _PCR_REGSET_ID_\r
-{\r
- PCR_REG_CHIP_SLEEP_ENABLE =0,\r
- PCR_REG_CHIP_CLK_REQD_STS,\r
- PCR_REG_EC_SLEEP_ENABLE,\r
- PCR_REG_EC_CLK_REQD_STS,\r
- PCR_REG_HOST_SLEEP_ENABLE,\r
- PCR_REG_HOST_CLK_REQD_STS,\r
- PCR_REG_SYSTEM_SLEEP_CTRL, \r
- PCR_REG_PROCESSOR_CLK_CTRL = 8,\r
- PCR_REG_EC_SLEEP_ENABLE_2,\r
- PCR_REG_EC_CLK_REQD_STS_2,\r
- PCR_REG_SLOW_CLK_CTRL,\r
- PCR_REG_OSCILLATOR_ID,\r
- PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS,\r
- PCR_REG_CHIP_RESET_ENABLE,\r
- PCR_REG_HOST_RESET_ENABLE,\r
- PCR_REG_EC_RESET_ENABLE,\r
- PCR_REG_EC_RESET_ENABLE_2,\r
- PCR_REG_PWR_RESET_CTRL\r
-};\r
-/* ---------------------------------------------------------------------- */\r
-\r
-// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable\r
-//PCR register group 0 - CHIP\r
-#define PCR0_REGS_CHIP (((uint32_t)(PCR_REG_CHIP_SLEEP_ENABLE) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_CHIP_CLK_REQD_STS) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_CHIP_RESET_ENABLE) & 0xFF)<<16u))\r
-\r
-//PCR register group 1 - EC\r
-#define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))\r
-\r
-//PCR register group 2 - HOST\r
-#define PCR2_REGS_HOST (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))\r
-\r
-//PCR register group 3 - EC 2\r
-#define PCR3_REGS_EC2 (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \\r
- (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \\r
- (((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u))\r
- \r
- \r
-//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
-#define PCR1_EC_INT_BITPOS (0u)\r
-#define PCR1_EC_PECI_BITPOS (1u)\r
-#define PCR1_EC_TACH0_BITPOS (2u)\r
-#define PCR1_EC_PWM0_BITPOS (4u)\r
-#define PCR1_EC_PMC_BITPOS (5u)\r
-#define PCR1_EC_DMA_BITPOS (6u)\r
-#define PCR1_EC_TFDP_BITPOS (7u)\r
-#define PCR1_EC_CPU_BITPOS (8u)\r
-#define PCR1_EC_WDT_BITPOS (9u)\r
-#define PCR1_EC_SMB0_BITPOS (10u)\r
-#define PCR1_EC_TACH1_BITPOS (11u)\r
-#define PCR1_EC_PWM1_BITPOS (20u)\r
-#define PCR1_EC_PWM2_BITPOS (21u)\r
-#define PCR1_EC_PWM3_BITPOS (22u)\r
-#define PCR1_EC_REG_BITPOS (29u)\r
-#define PCR1_EC_BTIMER0_BITPOS (30u)\r
-#define PCR1_EC_BTIMER1_BITPOS (31u)\r
-\r
-//PCR2_HOST -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
-#define PCR2_HOST_LPC_BITPOS (0u)\r
-#define PCR2_HOST_UART0_BITPOS (1u)\r
-#define PCR2_HOST_GLBL_CFG_BITPOS (12u)\r
-#define PCR2_HOST_ACPI_EC0_BITPOS (13u)\r
-#define PCR2_HOST_ACPI_EC1_BITPOS (14u)\r
-#define PCR2_HOST_ACPI_PM1_BITPOS (15u)\r
-#define PCR2_HOST_8042EM_BITPOS (16u)\r
-#define PCR2_HOST_RTC_BITPOS (18u)\r
-\r
-//PCR3_EC2 -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
-#define PCR3_EC2_ADC_BITPOS (3u)\r
-#define PCR3_EC2_PS2_0_BITPOS (5u)\r
-#define PCR3_EC2_PS2_1_BITPOS (6u)\r
-#define PCR3_EC2_PS2_2_BITPOS (7u)\r
-#define PCR3_EC2_PS2_3_BITPOS (8u)\r
-#define PCR3_EC2_SPI0_BITPOS (9u)\r
-#define PCR3_EC2_HTIMER_BITPOS (10u)\r
-#define PCR3_EC2_KEYSCAN_BITPOS (11u)\r
-#define PCR3_EC2_RPM_PWM_BITPOS (12u)\r
-#define PCR3_EC2_SMB1_BITPOS (13u)\r
-#define PCR3_EC2_SMB2_BITPOS (14u)\r
-#define PCR3_EC2_SMB3_BITPOS (15u)\r
-#define PCR3_EC2_LED0_BITPOS (16u)\r
-#define PCR3_EC2_LED1_BITPOS (17u)\r
-#define PCR3_EC2_LED2_BITPOS (18u)\r
-#define PCR3_EC2_BCM_BITPOS (19u)\r
-#define PCR3_EC2_SPI1_BITPOS (20u)\r
-#define PCR3_EC2_BTIMER2_BITPOS (21u)\r
-#define PCR3_EC2_BTIMER3_BITPOS (22u)\r
-#define PCR3_EC2_BTIMER4_BITPOS (23u)\r
-#define PCR3_EC2_BTIMER5_BITPOS (24u)\r
-#define PCR3_EC2_LED3_BITPOS (25u)\r
-\r
-/*\r
- * n = b[7:0] = PCR Reg Bit Position\r
- * m = b[31:8] = PCRx Regs IDs\r
- */\r
-//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul)) \r
-\r
-//PCRx_REGS_BIT positions \r
-#define PCRx_REGS_POS_SLEEP_ENABLE (8u)\r
-#define PCRx_REGS_POS_CLK_REQD_STS (16u)\r
-#define PCRx_REGS_POS_RESET_ENABLE (24u) \r
-\r
-\r
-/******************************************************************************/\r
-/** PCR Block IDS. \r
- * These IDs are used to directly refer to a block \r
- *******************************************************************************/\r
-typedef enum {\r
- PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)), \r
- PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)), \r
- PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)), \r
- PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)), \r
- PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)), \r
- PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)), \r
- PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)), \r
- PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)), \r
- PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)), \r
- PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)), \r
- PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)), \r
- PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)), \r
- PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)), \r
- PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)), \r
- PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)), \r
- PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)), \r
- PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)), \r
- PCR_LPC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_LPC_BITPOS & 0xFFu)),\r
- PCR_UART0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_UART0_BITPOS & 0xFFu)),\r
- PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_GLBL_CFG_BITPOS & 0xFFu)),\r
- PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC0_BITPOS & 0xFFu)),\r
- PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC1_BITPOS & 0xFFu)),\r
- PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_PM1_BITPOS & 0xFFu)),\r
- PCR_8042EM = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_8042EM_BITPOS & 0xFFu)),\r
- PCR_RTC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_RTC_BITPOS & 0xFFu)),\r
- PCR_ADC = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_ADC_BITPOS & 0xFFu)),\r
- PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_0_BITPOS & 0xFFu)), \r
- PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_1_BITPOS & 0xFFu)), \r
- PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_2_BITPOS & 0xFFu)), \r
- PCR_PS2_3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_3_BITPOS & 0xFFu)), \r
- PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI0_BITPOS & 0xFFu)), \r
- PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_HTIMER_BITPOS & 0xFFu)), \r
- PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_KEYSCAN_BITPOS & 0xFFu)), \r
- PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_RPM_PWM_BITPOS & 0xFFu)), \r
- PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB1_BITPOS & 0xFFu)), \r
- PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB2_BITPOS & 0xFFu)), \r
- PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB3_BITPOS & 0xFFu)), \r
- PCR_LED0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED0_BITPOS & 0xFFu)), \r
- PCR_LED1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED1_BITPOS & 0xFFu)), \r
- PCR_LED2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED2_BITPOS & 0xFFu)), \r
- PCR_BCM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BCM_BITPOS & 0xFFu)), \r
- PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI1_BITPOS & 0xFFu)), \r
- PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER2_BITPOS & 0xFFu)), \r
- PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER3_BITPOS & 0xFFu)), \r
- PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER4_BITPOS & 0xFFu)), \r
- PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER5_BITPOS & 0xFFu)), \r
- PCR_LED3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED3_BITPOS & 0xFFu)), \r
-} PCR_BLK_ID;\r
-\r
-\r
-/******************************************************************************/\r
-/** PCR Processor ClK Divide Values \r
- *******************************************************************************/\r
-enum PROCESSOR_CLK_DIVIDE_VALUE\r
-{\r
- PCR_CPU_CLK_DIVIDE_1 = 1,\r
- PCR_CPU_CLK_DIVIDE_4 = 4,\r
- PCR_CPU_CLK_DIVIDE_16 = 16,\r
- PCR_CPU_CLK_DIVIDE_48 = 48 \r
-};\r
-\r
-/******************************************************************************/\r
-/** System Sleep Modes \r
- *******************************************************************************/\r
-enum SYSTEM_SLEEP_MODES\r
-{\r
- SYSTEM_HEAVY_SLEEP_1 = 0, \r
- SYSTEM_HEAVY_SLEEP_3 = 1,\r
- SYSTEM_HEAVY_SLEEP_2 = 2,\r
- SYSTEM_DEEPEST_SLEEP = 5 \r
-};\r
-\r
-/* Bitmask for System Sleep Control Register */\r
-#define PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK (1UL<<0)\r
-#define PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK (1UL<<1)\r
-#define PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK (1UL<<2)\r
-\r
-/* Bitmask for Chip Sub-system Power Reset Status Register */\r
-#define PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK (1UL<<2)\r
-#define PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK (1UL<<3)\r
-#define PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK (1UL<<5)\r
-#define PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK (1UL<<6)\r
-#define PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK (1UL<<10)\r
-#define PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK (1UL<<11)\r
-\r
-/* Bitmask for Processor Clock Control Register */\r
-#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8)\r
-\r
-/* Bitmask for Power Reset Control Register */\r
-#define PCR_iRESET_OUT_BITMASK (1UL<<0)\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions to program Sleep Enable, CLK Reqd Status, *\r
- * Reset Enable for a block *\r
- * ---------------------------------------------------------------------- */\r
- /** Sets or Clears block specific bit in PCR Sleep Enable Register\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register\r
- */\r
-void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);\r
-\r
-/** Get Clock Required Status for the block\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @return uint8_t - 1 if Clock Required Status set, else 0\r
- */\r
-uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id);\r
-\r
-/** Sets or Clears Reset Enable register bit for the block\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register\r
- */\r
-void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* API - Functions for entering low power modes */\r
-/* ---------------------------------------------------------------------- */\r
-/** Instructs all blocks to sleep by setting the Sleep Enable bits */\r
-void pcr_all_blocks_sleep(void);\r
-\r
-/** Clears the Sleep Enable bits for all blocks */\r
-void pcr_all_blocks_wake(void);\r
-\r
-/** Programs required sleep mode in System Sleep Control Register\r
- * @param sleep_mode - see enum SYSTEM_SLEEP_MODES\r
- */\r
-void pcr_system_sleep(uint8_t sleep_mode);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to program and read 32-bit values *\r
- * from PCR Registers *\r
- * ---------------------------------------------------------------------- */\r
- /** Write 32-bit value in the PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param value - 32-bit value\r
- */\r
-void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value);\r
-\r
-/** Reads 32-bit value from the PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @return value - 32-bit value\r
- */\r
-uint32_t p_pcr_reg_read(uint8_t pcr_reg_id);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to set, clr and get bits in *\r
- * PCR Registers * \r
- * ---------------------------------------------------------------------- */\r
- /** Sets bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to set \r
- */\r
-void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask);\r
-\r
-/** Clears bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to clear \r
- */\r
-void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask);\r
-\r
-/** Read bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to read \r
- * @return value - 32-bit value\r
- */\r
-uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask);\r
-\r
-/** Sets or Clears bits in a PCR Register - Helper Function\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to set or clear\r
- * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register\r
- */\r
-void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag);\r
- \r
-//Functions to operate on System Sleep Control Register \r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to operate on System Sleep Control *\r
- * Register * \r
- * ---------------------------------------------------------------------- */\r
-/** Sets/Clears the Ring oscillator power down bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag);\r
-\r
-/** Sets/Clears the Ring oscillator output gate bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag);\r
-\r
-/** Sets/Clears the Core regulator standby bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag);\r
-\r
-/** Writes required sleep mode in System Sleep Control Register\r
- * @param sleep_value - System Sleep control value - [D2, D1, D0]\r
- */\r
-void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value);\r
-\r
-/** Reads the System Sleep Control PCR Register\r
- * @return value - byte 0 of the system sleep control PCR register\r
- */\r
-uint8_t p_pcr_system_sleep_ctrl_read(void);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to program to CLK Divide Value * \r
- * ---------------------------------------------------------------------- */\r
- /** Writes the clock divide value in the Processor Clock Control Register\r
- * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
- */\r
-void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to program the Slow Clock Control *\r
- * Register *\r
- * ---------------------------------------------------------------------- */\r
- /** Write the slow clock divide value in the Slow Clock Control Register\r
- * @param slow_clk_divide_value - slow clk divide value\r
- */\r
-void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Function to read the Oscillator Lock Status */ \r
-/* ---------------------------------------------------------------------- */\r
-/** Reads the Oscillator Lock status bit in the Oscillator ID Register\r
- * @return 1 if Oscillator Lock Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_oscillator_lock_sts_get(void);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions to read various power status in *\r
- * Chip Sub-System register *\r
- * ---------------------------------------------------------------------- */\r
- /** Reads the VCC Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VCC Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void);\r
-\r
-/** Reads the SIO Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if SIO Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void);\r
-\r
-/** Reads the VBAT Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VBAT Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void);\r
-\r
-/** Clears the VBAT Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register \r
- */\r
-void p_pcr_chip_subsystem_vbat_reset_sts_clr(void);\r
-\r
-/** Reads the VCC1 Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VCC1 Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void);\r
-\r
-/** Clears the VCC1 Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register \r
- */\r
-void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void);\r
-\r
-/** Reads the 32K_ACTIVE status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if 32_ACTIVE bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void);\r
-\r
-/** Reads the PCICLK_ACTIVE status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if CICLK_ACTIVE bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void);\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Peripheral Function - Functions for Power Reset Control Register */ \r
-/* ---------------------------------------------------------------------- */\r
-/** Reads the iRESET_OUT bit in the Power Reset Control Register\r
- * @return 1 if iRESET_OUT bit is set, else 0\r
- */\r
-uint8_t p_pcr_iReset_Out_get(void);\r
-\r
-/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register\r
- * @param 1 Set iRESET_OUT bit; 0 - Clear the bit\r
- */\r
-void p_pcr_iReset_Out(uint8_t set_clr_flag);\r
-\r
-#endif // #ifndef _PCR_H\r
-/* end pcr.h */\r
-/** @}\r
- */\r
-\r
-\r
-\r
+++ /dev/null
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/11/24 06:28:28 $ \r
-$Author: amohandas $\r
-Last Change: Updated for tabs\r
-******************************************************************************/\r
-/** @file pcr_api.c\r
-* \brief Power, Clocks, and Resets API Source file\r
-* \author jvasanth\r
-* \r
-* This file implements the PCR APIs \r
-******************************************************************************/\r
-\r
-/** @defgroup PCR\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "pcr.h"\r
-\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Sets or Clears block specific bit in PCR Sleep Enable Register\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register\r
- */\r
-void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)\r
-{\r
- uint32_t bit_mask;\r
- uint8_t pcr_reg_id; \r
- \r
- bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
- pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu);\r
-\r
- p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); \r
-}\r
-\r
-\r
-/** Get Clock Required Status for the block\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @return uint8_t - 1 if Clock Required Status set, else 0\r
- */\r
-uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id)\r
-{\r
- uint32_t bit_mask;\r
- uint8_t pcr_reg_id, retVal; \r
- \r
- bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
- pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu);\r
-\r
- retVal = 0;\r
- if (p_pcr_reg_get(pcr_reg_id, bit_mask))\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal;\r
-}\r
-\r
-/** Sets or Clears Reset Enable register bit for the block\r
- * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
- * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register\r
- */\r
-void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)\r
-{\r
- uint32_t bit_mask;\r
- uint8_t pcr_reg_id; \r
- \r
- bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
- pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu);\r
-\r
- p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); \r
-}\r
-\r
-\r
-/* ------------------------------------------------------------------------------- */\r
-/* Functions for entering low power modes */\r
-/* ------------------------------------------------------------------------------- */\r
-\r
-/** Instructs all blocks to sleep by setting the Sleep Enable bits */\r
-void pcr_all_blocks_sleep(void)\r
-{\r
- p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0xFFFFFFFF);\r
- p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0xFFFFFFFF);\r
- p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0xFFFFFFFF);\r
- p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF); \r
-}\r
-\r
-/** Clears the Sleep Enable bits for all blocks */\r
- void pcr_all_blocks_wake(void)\r
-{\r
- p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0);\r
- p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0);\r
- p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0);\r
- p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0); \r
-}\r
-\r
-/** Programs required sleep mode in System Sleep Control Register\r
- * @param sleep_mode - see enum SYSTEM_SLEEP_MODES\r
- */\r
-void pcr_system_sleep(uint8_t sleep_mode)\r
-{\r
- p_pcr_system_sleep_ctrl_write(sleep_mode);\r
-}\r
-\r
-\r
-/* end pcr_api.c */\r
-/** @}\r
- */\r
+++ /dev/null
-/*****************************************************************************\r
-* © 2015 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-******************************************************************************\r
-\r
-Version Control Information (Perforce)\r
-******************************************************************************\r
-$Revision: #1 $ \r
-$DateTime: 2015/11/24 06:28:28 $ \r
-$Author: amohandas $\r
-Last Change: Updated for tabs\r
-******************************************************************************/\r
-/** @file pcr_perphl.c\r
-* \brief Power, Clocks, and Resets Peripheral Source file\r
-* \author jvasanth\r
-* \r
-* This file implements the PCR Peripheral functions \r
-******************************************************************************/\r
-\r
-/** @defgroup PCR\r
- * @{\r
- */\r
-\r
-#include "common_lib.h"\r
-#include "pcr.h"\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Generic functions to program and read 32-bit values from PCR Registers */\r
-/* ---------------------------------------------------------------------- */\r
-/** Writes 32-bit value in the PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param value - 32-bit value\r
- */\r
-void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE); \r
-\r
- pPCR_Reg += pcr_reg_id;\r
-\r
- *pPCR_Reg = value; \r
-}\r
-\r
-/** Reads 32-bit value from the PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @return value - 32-bit value\r
- */\r
-uint32_t p_pcr_reg_read(uint8_t pcr_reg_id)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint32_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE); \r
-\r
- pPCR_Reg += pcr_reg_id; \r
-\r
- retVal = *pPCR_Reg;\r
-\r
- return retVal;\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to set, clr and get bits in PCR Registers */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Sets bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to set \r
- */\r
-void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE); \r
-\r
- pPCR_Reg += pcr_reg_id;\r
-\r
- *pPCR_Reg |= bit_mask; \r
-}\r
-\r
-/** Clears bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to clear \r
- */\r
-void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE); \r
-\r
- pPCR_Reg += pcr_reg_id;\r
-\r
- *pPCR_Reg &= ~bit_mask; \r
-}\r
-\r
-/** Read bits in a PCR Register\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to read \r
- * @return value - 32-bit value\r
- */\r
-uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint32_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE); \r
-\r
- pPCR_Reg += pcr_reg_id; \r
-\r
- retVal = (*pPCR_Reg) & bit_mask;\r
-\r
- return retVal;\r
-}\r
-\r
-/** Sets or Clears bits in a PCR Register - Helper Function\r
- * @param pcr_reg_id - pcr register id \r
- * @param bit_mask - Bit mask of bits to set or clear\r
- * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register\r
- */\r
-void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag)\r
-{\r
- if (set_clr_flag)\r
- {\r
- p_pcr_reg_set(pcr_reg_id, bit_mask);\r
- }\r
- else\r
- {\r
- p_pcr_reg_clr(pcr_reg_id, bit_mask);\r
- } \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to operate on System Sleep Control Register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/**\r
- * Sets/Clears the Ring oscillator power down bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
- \r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;\r
-\r
- if (set_clr_flag)\r
- {\r
- *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK; \r
- }\r
- else\r
- {\r
- *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK; \r
- }\r
-}\r
-\r
-/** Sets/Clears the Ring oscillator output gate bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
- \r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;\r
-\r
- if (set_clr_flag)\r
- {\r
- *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK; \r
- }\r
- else\r
- {\r
- *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK; \r
- }\r
-}\r
-\r
-/** Sets/Clears the Core regulator standby bit \r
- * in System Sleep Control Register\r
- * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
- */\r
-void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
- \r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;\r
-\r
- if (set_clr_flag)\r
- {\r
- *pPCR_Reg |= PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK; \r
- }\r
- else\r
- {\r
- *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK; \r
- }\r
-}\r
-\r
-/** Writes required sleep mode in System Sleep Control Register\r
- * @param sleep_value - System Sleep control value - [D2, D1, D0]\r
- */\r
-void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
- \r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; \r
-\r
- *pPCR_Reg = (sleep_value & 0x7); \r
-}\r
-\r
-/** Reads the System Sleep Control PCR Register\r
- * @return value - byte 0 of the system sleep control PCR register\r
- */\r
-uint8_t p_pcr_system_sleep_ctrl_read(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
- \r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; \r
-\r
- retVal = (uint8_t)((*pPCR_Reg) & 0xFF);\r
-\r
- return retVal;\r
-}\r
-\r
-\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to program to CLK Divide Value */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Writes the clock divide value in the Processor Clock Control Register\r
- * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
- */\r
-void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL; \r
-\r
- *pPCR_Reg = (clk_divide_value & 0xFF); \r
- \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to program the slow clock divide value */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Write the slow clock divide value in the Slow Clock Control Register\r
- * @param slow_clk_divide_value - slow clk divide value\r
- */\r
-void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL; \r
-\r
- *pPCR_Reg = (slow_clk_divide_value & 0x3FF); \r
-\r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Function to read the Oscillator Lock Status */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Reads the Oscillator Lock status bit in the Oscillator ID Register\r
- * @return 1 if Oscillator Lock Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_oscillator_lock_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal;\r
- \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions to read various power status in Chip Sub-System register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Reads the VCC Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VCC Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal; \r
-}\r
-\r
-/** Reads the SIO Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if SIO Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal; \r
-}\r
-\r
-/** Reads the VBAT Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VBAT Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal; \r
-}\r
-\r
-/** Clears the VBAT Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register \r
- */\r
-void p_pcr_chip_subsystem_vbat_reset_sts_clr(void)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;\r
-\r
- // Write to clear\r
- *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK;\r
- \r
-}\r
-\r
-/** Reads the VCC1 Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if VCC1 Reset Status bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal; \r
-}\r
-\r
-/** Clears the VCC1 Reset Status bit \r
- * in the Chip Subsystem Power Reset Status Register \r
- */\r
-void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;\r
-\r
- // Write to clear\r
- *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK;\r
- \r
-}\r
-\r
-/** Reads the 32K_ACTIVE status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if 32_ACTIVE bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal; \r
-}\r
-\r
-/** Reads the PCICLK_ACTIVE status bit \r
- * in the Chip Subsystem Power Reset Status Register\r
- * @return 1 if CICLK_ACTIVE bit is set, else 0\r
- */\r
-uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK)\r
- {\r
- retVal = 1;\r
- } \r
- return retVal; \r
-}\r
-\r
-/* ---------------------------------------------------------------------- */\r
-/* Functions for Power Reset Control Register */\r
-/* ---------------------------------------------------------------------- */\r
-\r
-/** Reads the iRESET_OUT bit in the Power Reset Control Register\r
- * @return 1 if iRESET_OUT bit is set, else 0\r
- */\r
-uint8_t p_pcr_iReset_Out_get(void)\r
-{\r
- __IO uint32_t *pPCR_Reg;\r
- uint8_t retVal;\r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; \r
-\r
- retVal = 0;\r
- if (*pPCR_Reg & PCR_iRESET_OUT_BITMASK)\r
- {\r
- retVal = 1;\r
- }\r
- \r
- return retVal;\r
- \r
-}\r
-\r
-/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register\r
- * @param 1 Set iRESET_OUT bit; 0 - Clear the bit\r
- */\r
-void p_pcr_iReset_Out(uint8_t set_clr_flag)\r
-{\r
- __IO uint32_t *pPCR_Reg; \r
-\r
- pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;\r
-\r
- *pPCR_Reg = (set_clr_flag & 0x1); \r
-}\r
-\r
-\r
-/* end pcr_perphl.c */\r
-/** @}\r
- */\r
+++ /dev/null
-/****************************************************************************\r
-* © 2013 Microchip Technology Inc. and its subsidiaries.\r
-* You may use this software and any derivatives exclusively with\r
-* Microchip products.\r
-* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
-* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
-* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
-* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
-* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
-* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
-* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
-* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
-* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
-* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
-* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
-* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
-* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
-* OF THESE TERMS.\r
-*/\r
-\r
-/** @defgroup pwm pwm_c_wrapper\r
- * @{\r
- */\r
-/** @file pwm_c_wrapper.cpp\r
- \brief the pwm component C wrapper \r
- This program is designed to allow the other C programs to be able to use this component\r
-\r
- There are entry points for all C wrapper API implementation\r
-\r
-<b>Platform:</b> This is ARC-based component \r
-\r
-<b>Toolset:</b> Metaware IDE(8.5.1)\r
-<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
-\r
-/*******************************************************************************\r
- * SMSC version control information (Perforce):\r
- *\r
- * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/platform.h $\r
- * REVISION: $Revision: #1 $\r
- * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
- * AUTHOR: $Author: akrishnan $\r
- *\r
- * Revision history (latest first):\r
- * #xx\r
- ***********************************************************************************\r
- */\r
-\r
-#ifndef _PLATFORM_H_\r
-#define _PLATFORM_H_\r
-#include <stdint.h>\r
-/* Platform Configuration PreProcessor Conditions */\r
-#define TOOLKEIL 1\r
-#define TOOLPC 2\r
-#define TOOLMW 3\r
-#define TOOLMDK 4\r
-\r
-#define PCLINT 9 //added to satisfy PC Lint's need for a value here\r
-\r
-#ifdef __CC_ARM // Keil ARM MDK\r
-#define TOOLSET TOOLMDK\r
-#endif\r
-\r
-#if 0\r
-#ifdef _WIN32 //always defined by visual c++\r
-#define TOOLSET TOOLPC\r
-#endif\r
-\r
-#ifdef __WIN32__ //always defined by borland\r
-#define TOOLSET TOOLPC\r
-#endif\r
-#endif\r
-\r
-\r
-#ifdef _ARC\r
-#define TOOLSET TOOLMW // ARC Metaware\r
-#endif\r
-\r
-#ifndef TOOLSET\r
-//#error "ERROR: cfg.h TOOLSET not defined!"\r
-#endif\r
-\r
-#if TOOLSET == TOOLMDK\r
-#define _KEIL_ARM_ 1 /* Make 1 for Keil MDK Compiler */\r
-#define _KEIL_ 0 /* Make 1 for Keil Compiler */\r
-#define _PC_ 0 \r
-#define _ARC_CORE_ 0\r
-#endif\r
-\r
-#if TOOLSET == TOOLKEIL\r
-#define _KEIL_ARM_ 0\r
-#define _KEIL_ 1 /* Make 1 for Keil Compiler */\r
-#define _PC_ 0 \r
-#define _ARC_CORE_ 0\r
-#endif\r
-\r
-#if TOOLSET == TOOLPC\r
-#define _KEIL_ARM_ 0\r
-#define _KEIL_ 0 \r
-#define _PC_ 1 /* Make 1 for PC Environment */\r
-#define _ARC_CORE_ 0\r
-#endif\r
-\r
-#if TOOLSET == TOOLMW\r
-#define _KEIL_ARM_ 0\r
-#define _KEIL_ 0\r
-#define _PC_ 0\r
-#define _ARC_CORE_ 1\r
-#endif\r
-\r
-/* Short form for Standard Data Types */\r
-typedef unsigned char UINT8;\r
-typedef unsigned short UINT16;\r
-typedef unsigned long UINT32;\r
-\r
-typedef volatile unsigned char REG8;\r
-\r
-typedef unsigned char BYTE;\r
-typedef unsigned short WORD;\r
-typedef unsigned long DWORD;\r
-\r
-typedef unsigned char UCHAR;\r
-typedef unsigned short USHORT;\r
-typedef unsigned long ULONG;\r
-\r
-typedef unsigned char BOOL;\r
-typedef unsigned int UINT;\r
-\r
-/* signed types */\r
-typedef signed char INT8;\r
-typedef signed short INT16;\r
-typedef signed long INT32;\r
-\r
-typedef void VOID;\r
-\r
-/* union types */\r
-typedef union _BITS_8\r
-{\r
- UINT8 byte;\r
- struct\r
- {\r
- UINT8 bit0: 1;\r
- UINT8 bit1: 1;\r
- UINT8 bit2: 1;\r
- UINT8 bit3: 1;\r
- UINT8 bit4: 1;\r
- UINT8 bit5: 1;\r
- UINT8 bit6: 1;\r
- UINT8 bit7: 1;\r
- }bit;\r
-}BITS_8;\r
-\r
-\r
-/* MACROS FOR Platform Portability */\r
-\r
-/* macro for defining MMCR register */\r
-/* add MMCRARRAY() & EXTERNMMCRARRAY() */\r
-#if _KEIL_\r
-#define MMCR(name,address) volatile unsigned char xdata name _at_ address\r
-#define MMCRARRAY(name,length,address) volatile unsigned char xdata name[length] _at_ address\r
-#define MMCRTYPE(name,dtype,address) volatile dtype xdata name _at_ address\r
-#define EXTERNMMCR(name) extern volatile unsigned char xdata name\r
-#define EXTERNMMCRARRAY(name) extern volatile unsigned char xdata name[]\r
-#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype xdata name\r
-#define SFR(name,address) sfr name = address\r
-#define SFRBIT(name,address) sbit name = address\r
-#define EXTERNSFR(name) \r
-#define BITADDRESSTYPE(name) bit name\r
-#define XDATA xdata\r
-#define CODE code\r
-#define DATA data\r
-#define IDATA idata\r
-#define INTERRUPT(x) interrupt x\r
-#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;)\r
-#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;)\r
-#define NULLPTR (char *)(0)\r
-#define PLATFORM_TRIM_OSC() // TODO\r
-#define PNOP() \r
-#define DISABLE_INTERRUPTS() sfrIE_EAbit=0\r
-#define ENABLE_INTERRUPTS() sfrIE_EAbit=1\r
-#define SAVE_DIS_INTERRUPTS(x) { x=sfrIE_EAbit; sfrIE_EAbit=0; }\r
-#define RESTORE_INTERRUPTS(x) { sfrIE_EAbit=x; }\r
-#define ATOMIC_CPU_SLEEP()\r
-#define NUM_IRQ_VECTORS 12 // DW-8051\r
-#define IRQ_VECTOR_SIZE 8 \r
-#define USE_INLINE_PATCHER 1\r
-#define IRQ_VECTABLE_IN_RAM 0\r
-#define PLAT_ROM_IRQ_VECTOR_BASE 0x03 // ROM start\r
-#define PLAT_IRQ_VECTOR_BASE 0x1003 // RAM start\r
-#define FUNC_NEVER_RETURNS\r
-#define BEGIN_SMALL_DATA_BLOCK(x)\r
-#define END_SMALL_DATA_BLOCK()\r
-UINT32 soft_norm(UINT32 val);\r
-#define NORM(x) soft_norm(x)\r
-//\r
-#define USE_FUNC_REPLACEMENT 0\r
-#endif\r
-\r
-#if _PC_\r
-#define MMCR(name,address) volatile unsigned char name\r
-#define MMCRARRAY(name,length,address) volatile unsigned char name[length]\r
-#define MMCRTYPE(name,dtype,address) volatile dtype name\r
-#define EXTERNMMCR(name) extern volatile unsigned char name\r
-#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]\r
-#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name\r
-#define SFR(name,address) volatile unsigned char name\r
-#define SFRBIT(name,address) volatile unsigned char name\r
-#define EXTERNSFR(name) extern volatile unsigned char name\r
-#define BITADDRESSTYPE(name) volatile unsigned char name\r
-#define XDATA\r
-#define CODE \r
-#define DATA\r
-#define IDATA\r
-#define INTERRUPT(x)\r
-#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;)\r
-#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;)\r
-#define NULLPTR (char *)(0)\r
-#define PLATFORM_TRIM_OSC() // TODO\r
-#define PNOP() \r
-#define DISABLE_INTERRUPTS() \r
-#define ENABLE_INTERRUPTS()\r
-#define SAVE_DIS_INTERRUPTS(x) \r
-#define RESTORE_INTERRUPTS(x) \r
-#define ATOMIC_CPU_SLEEP()\r
-#define NUM_IRQ_VECTORS 24\r
-#define IRQ_VECTOR_SIZE 8\r
-#define USE_INLINE_PATCHER 1\r
-#define IRQ_VECTABLE_IN_RAM 0\r
-#define FUNC_NEVER_RETURNS\r
-#define BEGIN_SMALL_DATA_BLOCK(x)\r
-#define END_SMALL_DATA_BLOCK()\r
-UINT32 soft_norm(UINT32 val);\r
-#define NORM(x) soft_norm(x)\r
-//\r
-#define USE_FUNC_REPLACEMENT 0\r
-#endif\r
-\r
-#if _ARC_CORE_\r
-// ARC C has no equivalent operator to specify address of a variable\r
-// ARC MMCR's are 32-bit registers\r
-#define MMCR(name,address) volatile unsigned char name\r
-#define MMCRARRAY(name,length,address) volatile unsigned char name[length]\r
-#define MMCRTYPE(name,dtype,address) volatile dtype name \r
-#define EXTERNMMCR(name) extern volatile unsigned char name\r
-#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]\r
-#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name\r
-#define SFR(name,address) volatile unsigned char name \r
-#define SFRBIT(name,address) volatile unsigned char name \r
-#define EXTERNSFR(name) extern volatile unsigned char name \r
-#define BITADDRESSTYPE(name) \r
-#define XDATA\r
-#define CODE \r
-#define DATA\r
-#define IDATA\r
-#define INTERRUPT(x)\r
-#define SET_GLOBAL_INTR_ENABLE() (_enable())\r
-#define CLR_GLOBAL_INTR_ENABLE() (_disable())\r
-#define NULLPTR (char *)(0)\r
-#define NULLVOIDPTR (void *)(0)\r
-#define NULLFPTR (void (*)(void))0\r
-#define PLATFORM_TRIM_OSC() // TODO\r
-#define PNOP() _nop()\r
-#define DISABLE_INTERRUPTS() _disable()\r
-#define ENABLE_INTERRUPTS() _enable()\r
-#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); }\r
-#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); }\r
-#define ATOMIC_CPU_SLEEP() _flag(6);_sleep();_nop();_nop();\r
-#define NUM_IRQ_VECTORS 24\r
-#define IRQ_VECTOR_SIZE 8\r
-#define USE_INLINE_PATCHER 0\r
-#define DCCM_CODE_ALIAS_ADDR 0x00060000\r
-#define PLAT_ROM_IRQ_VECTOR_BASE 0\r
-#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR)\r
-/// y #define IRQ_VECTABLE_IN_RAM 1\r
-#define IRQ_VECTABLE_IN_RAM 0\r
-#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS)\r
-#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x)\r
-#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data()\r
-#define NORM(x) _norm(x)\r
-\r
-#define INLINE_FUNCTION(x) #pragma On_inline(x)\r
-\r
-//\r
-#define USE_FUNC_REPLACEMENT 0\r
-#endif\r
-\r
-#if _KEIL_ARM_\r
-// For ARM MDK compiler\r
-// ARM MMCR's are 32-bit registers\r
-#define MMCR(name,address) volatile unsigned char name\r
-#define MMCRARRAY(name,length,address) volatile unsigned char name[length]\r
-#define MMCRTYPE(name,dtype,address) volatile dtype name \r
-#define EXTERNMMCR(name) extern volatile unsigned char name\r
-#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]\r
-#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name\r
-#define SFR(name,address) volatile unsigned char name \r
-#define SFRBIT(name,address) volatile unsigned char name \r
-#define EXTERNSFR(name) extern volatile unsigned char name \r
-#define BITADDRESSTYPE(name) \r
-#define XDATA\r
-#define CODE \r
-#define DATA\r
-#define IDATA\r
-#define INTERRUPT(x)\r
-#define SET_GLOBAL_INTR_ENABLE() (__enable_irq())\r
-#define CLR_GLOBAL_INTR_ENABLE() (__disable_irq())\r
-#define NULLPTR (char *)(0)\r
-#define NULLVOIDPTR (void *)(0)\r
-#define NULLFPTR (void (*)(void))0\r
-#define PLATFORM_TRIM_OSC() // TODO\r
-#define PNOP() __NOP()\r
-#define DISABLE_INTERRUPTS() __disable_irq()\r
-#define ENABLE_INTERRUPTS() __enable_irq()\r
-#define ATOMIC_CPU_SLEEP() __wfi();__nop();__nop();\r
-\r
-#if 0 /* need further efforts if needed */\r
-#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); }\r
-#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); }\r
-#define NUM_IRQ_VECTORS 24\r
-#define IRQ_VECTOR_SIZE 8\r
-#define USE_INLINE_PATCHER 0\r
-#define DCCM_CODE_ALIAS_ADDR 0x00060000\r
-#define PLAT_ROM_IRQ_VECTOR_BASE 0\r
-#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR)\r
-/// y #define IRQ_VECTABLE_IN_RAM 1\r
-#define IRQ_VECTABLE_IN_RAM 0\r
-#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x)\r
-#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data()\r
-#define INLINE_FUNCTION(x) #pragma On_inline(x)\r
-#define USE_FUNC_REPLACEMENT 0\r
-#endif\r
-\r
-#if 0\r
-#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS)\r
-#define NORM(x) _norm(x)\r
-#else\r
-/* for ARM MDK */\r
-#define FUNC_NEVER_RETURNS\r
-UINT32 soft_norm(UINT32 val);\r
-#define NORM(x) soft_norm(x)\r
-#endif\r
-#endif\r
-\r
-/* General Constants */\r
-#define FALSE 0x00\r
-#define TRUE !FALSE\r
-\r
-#define BIT_n_MASK(n) (1U << (n))\r
-#define BIT_0_MASK (1<<0)\r
-#define BIT_1_MASK (1<<1)\r
-#define BIT_2_MASK (1<<2)\r
-#define BIT_3_MASK (1<<3)\r
-#define BIT_4_MASK (1<<4)\r
-#define BIT_5_MASK (1<<5)\r
-#define BIT_6_MASK (1<<6)\r
-#define BIT_7_MASK (1<<7)\r
-#define BIT_8_MASK ((UINT16)1<<8)\r
-#define BIT_9_MASK ((UINT16)1<<9)\r
-#define BIT_10_MASK ((UINT16)1<<10)\r
-#define BIT_11_MASK ((UINT16)1<<11)\r
-#define BIT_12_MASK ((UINT16)1<<12)\r
-#define BIT_13_MASK ((UINT16)1<<13)\r
-#define BIT_14_MASK ((UINT16)1<<14)\r
-#define BIT_15_MASK ((UINT16)1<<15)\r
-#define BIT_16_MASK ((UINT32)1<<16)\r
-#define BIT_17_MASK ((UINT32)1<<17)\r
-#define BIT_18_MASK ((UINT32)1<<18)\r
-#define BIT_19_MASK ((UINT32)1<<19)\r
-#define BIT_20_MASK ((UINT32)1<<20)\r
-#define BIT_21_MASK ((UINT32)1<<21)\r
-#define BIT_22_MASK ((UINT32)1<<22)\r
-#define BIT_23_MASK ((UINT32)1<<23)\r
-#define BIT_24_MASK ((UINT32)1<<24)\r
-#define BIT_25_MASK ((UINT32)1<<25)\r
-#define BIT_26_MASK ((UINT32)1<<26)\r
-#define BIT_27_MASK ((UINT32)1<<27)\r
-#define BIT_28_MASK ((UINT32)1<<28)\r
-#define BIT_29_MASK ((UINT32)1<<29)\r
-#define BIT_30_MASK ((UINT32)1<<30)\r
-#define BIT_31_MASK ((UINT32)1<<31)\r
-\r
-\r
-/* For CEC application */\r
-#define ON 1\r
-#define OFF 0\r
-\r
-#endif /*_PLATFORM_H_*/\r
-\r
-/** @}\r
- */\r
-\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armcc.h\r
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CMSIS_ARMCC_H\r
+#define __CMSIS_ARMCC_H\r
+\r
+\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePriMax __ASM("basepri_max");\r
+ __regBasePriMax = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() do {\\r
+ __schedule_barrier();\\r
+ __isb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() do {\\r
+ __schedule_barrier();\\r
+ __dsb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() do {\\r
+ __schedule_barrier();\\r
+ __dmb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in integer value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in two unsigned short values.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+/**\r
+ \brief Reverse byte order in signed short value\r
+ \details Reverses the byte order in a signed short value with sign extension to integer.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+ #define __RBIT __rbit\r
+#else\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+#else\r
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXB(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXH(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXW(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
+{\r
+ rrx r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRBT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRHT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRT(value, ptr) __strt(value, ptr)\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */\r
+\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
+ ((int64_t)(ARG3) << 32U) ) >> 32U))\r
+\r
+#endif /* (__CORTEX_M >= 0x04) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_gcc.h\r
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
+ * @version V5.00\r
+ * @date 02. March 2016\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * http://www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
+ (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) )\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
+ (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */\r
+\r
+\r
+#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U))\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ uint32_t result;\r
+\r
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ __ASM volatile ("");\r
+ return(result);\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+ __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in integer value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in two unsigned short values.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order in signed short value\r
+ \details Reverses the byte order in a signed short value with sign extension to integer.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (short)__builtin_bswap16(value);\r
+#else\r
+ int32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
+ (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) )\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __builtin_clz\r
+\r
+\r
+#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
+ (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) )\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \\r
+ (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U))\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic pop\r
+#endif\r
+\r
+#endif /* __CMSIS_GCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M4\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x04U) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "core_cmInstr.h" /* Core Instruction Access */\r
+#include "core_cmFunc.h" /* Core Function Access */\r
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000U\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M4 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1U)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable External Interrupt\r
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable External Interrupt\r
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of an external interrupt.\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of an external interrupt.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in NVIC and returns the active bit.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of an interrupt.\r
+ \note The priority cannot be set for every core interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of an interrupt.\r
+ The interrupt number can be positive to specify an external (device specific) interrupt,\r
+ or negative to specify an internal (core) interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmSimd.h\r
+ * @brief CMSIS Cortex-M SIMD Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMSIMD_H\r
+#define __CORE_CMSIMD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CMSIMD_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+/* Set configCREATE_LOW_POWER_DEMO to one to run the simple blinky demo low power\r
+example, or 1 to run the more comprehensive test and demo application. See\r
+the comments at the top of main.c for more information. */\r
+#define configCREATE_LOW_POWER_DEMO 1\r
+\r
+/* Some configuration is dependent on the demo being built. */\r
+#if( configCREATE_LOW_POWER_DEMO == 1 )\r
+\r
+ /* The low power demo uses a slow low power clock, so the SysTick clock,\r
+ which is used by default by Cortex-M ports, is not used to generate the\r
+ tick interrupt. */\r
+ #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 1\r
+\r
+ /* The slow clock used to generate the tick interrupt in the low power demo\r
+ runs at 32768Hz. Ensure the clock is a multiple of the tick rate. */\r
+ #define configTICK_RATE_HZ ( 128 )\r
+\r
+ /* The low power demo uses the tickless idle feature. */\r
+ #define configUSE_TICKLESS_IDLE 1\r
+\r
+#else\r
+\r
+ /* Some of the standard demo test tasks assume a tick rate of 1KHz, even\r
+ though that is faster than would normally be warranted by a real\r
+ application. */\r
+ #define configTICK_RATE_HZ ( 1000 )\r
+\r
+ /* The full demo always has tasks to run so the tick will never be turned\r
+ off. The blinky demo will use the default tickless idle implementation to\r
+ turn the tick off. */\r
+ #define configUSE_TICKLESS_IDLE 0\r
+\r
+#endif\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\r
+#define configUSE_QUEUE_SETS 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 1\r
+#define configCPU_CLOCK_HZ 48000000\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 28 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configSUPPORT_STATIC_ALLOCATION 1\r
+\r
+/* Run time stats gathering definitions. */\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+#define portGET_RUN_TIME_COUNTER_VALUE()\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+format the raw data provided by the uxTaskGetSystemState() function in to human\r
+readable ASCII form. See the notes in the implementation of vTaskList() within\r
+FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 3 /* 7 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x7\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0UL ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* LED not used at present, so just increment a variable to keep a count of the\r
+number of times the LED would otherwise have been toggled. */\r
+#define configTOGGLE_LED() ulLED++\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+\r
+T220C 000:298 SEGGER J-Link V4.98e Log File (0000ms, 0270ms total)\r
+T220C 000:298 DLL Compiled: May 5 2015 11:00:52 (0000ms, 0270ms total)\r
+T220C 000:298 Logging started @ 2016-01-08 12:24 (0000ms, 0270ms total)\r
+T220C 000:298 JLINK_SetWarnOutHandler(...) (0000ms, 0270ms total)\r
+T220C 000:298 JLINK_OpenEx(...)
+Firmware: J-Link V9 compiled Oct 9 2015 20:34:47
+Hardware: V9.10
+S/N: 59101789
+Feature(s): GDB, JFlash returns O.K. (0266ms, 0536ms total)\r
+T220C 000:564 JLINK_SetErrorOutHandler(...) (0000ms, 0536ms total)\r
+T220C 000:564 JLINK_ExecCommand("ProjectFile = "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M4F_CEC1302_Clicker_2\Keil_Specific\JLinkSettings.ini"", ...)Device "UNSPECIFIED" selected. returns 0x00 (0002ms, 0538ms total)\r
+T220C 000:566 JLINK_ExecCommand("Device = ARMCM4_FP", ...)Device "UNSPECIFIED" selected. returns 0x00 (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetCompileDateTime() (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0001ms, 0539ms total)\r
+T220C 000:567 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0003ms, 0542ms total)\r
+T220C 000:570 JLINK_SetSpeed(5000) (0000ms, 0542ms total)\r
+T220C 000:570 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 4, IRPrint = 0x01 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x48 JTAG> >0x78 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG>Found Cortex-M4 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC)\r
+ -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0)\r
+ -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)\r
+ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM ScanLen=4 NumDevices=1 aId[0]=0x4BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0026ms, 0568ms total)\r
+T220C 000:596 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x4BA00477 (0000ms, 0568ms total)\r
+T220C 000:596 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0000ms, 0568ms total)\r
+T220C 000:596 JLINK_GetDLLVersion() returns 49805 (0000ms, 0568ms total)\r
+T220C 000:596 JLINK_CORE_GetFound() returns 0xE0000FF (0000ms, 0568ms total)\r
+T220C 000:596 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003 returns 0x00 (0000ms, 0568ms total)\r
+T220C 000:596 JLINK_ReadMem (0xE00FF000, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 03 10 F0 FF ... returns 0x00 (0001ms, 0569ms total)\r
+T220C 000:597 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0570ms total)\r
+T220C 000:598 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0571ms total)\r
+T220C 000:599 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0571ms total)\r
+T220C 000:599 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0572ms total)\r
+T220C 000:600 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0573ms total)\r
+T220C 000:601 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0573ms total)\r
+T220C 000:601 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0574ms total)\r
+T220C 000:602 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0574ms total)\r
+T220C 000:602 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0575ms total)\r
+T220C 000:603 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0576ms total)\r
+T220C 000:604 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0576ms total)\r
+T220C 000:604 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0577ms total)\r
+T220C 000:605 JLINK_ReadMemU32(0xE000EF40, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF40) - Data: 21 00 11 10 returns 0x01 (0001ms, 0578ms total)\r
+T220C 000:606 JLINK_ReadMemU32(0xE000EF44, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF44) - Data: 11 00 00 11 returns 0x01 (0000ms, 0578ms total)\r
+T220C 000:606 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 41 C2 0F 41 returns 0x01 (0001ms, 0579ms total)\r
+T220C 000:607 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0579ms total)\r
+T220C 000:607 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048)\r
+ -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1225ms total)\r
+T220C 001:253 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1225ms total)\r
+T220C 001:253 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1225ms total)\r
+T220C 001:253 JLINK_Halt() returns 0x00 (0000ms, 1225ms total)\r
+T220C 001:253 JLINK_IsHalted() returns TRUE (0000ms, 1225ms total)\r
+T220C 001:253 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 1226ms total)\r
+T220C 001:254 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0000ms, 1226ms total)\r
+T220C 001:254 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 1227ms total)\r
+T220C 001:255 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_GetSpeed() returns 0x1388 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0001ms, 1228ms total)\r
+T220C 001:257 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 1229ms total)\r
+T220C 001:258 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 1230ms total)\r
+T220C 001:259 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1230ms total)\r
+T220C 001:259 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1230ms total)\r
+T220C 001:270 JLINK_WriteMem(0x00100000, 0x02AC Bytes, ...) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... -- CPU_WriteMem(684 bytes @ 0x00100000) returns 0x2AC (0003ms, 1233ms total)\r
+T220C 001:273 JLINK_ReadMem (0x00100000, 0x02AC Bytes, ...) -- CPU_ReadMem(684 bytes @ 0x00100000) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... returns 0x00 (0003ms, 1236ms total)\r
+T220C 001:330 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1236ms total)\r
+T220C 001:330 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1882ms total)\r
+T220C 001:977 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1882ms total)\r
+T220C 001:977 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1882ms total)\r
+T220C 001:977 JLINK_ReadMem (0x00118000, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x00118000) - Data: FE E7 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... returns 0x00 (0001ms, 1883ms total)\r
+T220C 002:517 JLINK_ReadMem (0x001001DA, 0x0002 Bytes, ...) -- CPU_ReadMem(2 bytes @ 0x001001DA) - Data: 00 47 returns 0x00 (0001ms, 1884ms total)\r
+T220C 002:518 JLINK_ReadMem (0x001001DC, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x001001DC) - Data: 4F F0 01 07 FE E7 4F F0 02 07 FE E7 4F F0 03 07 ... returns 0x00 (0001ms, 1885ms total)\r
+T220C 002:601 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1885ms total)\r
+T220C 002:601 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 2531ms total)\r
+T220C 003:248 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2531ms total)\r
+T220C 003:249 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2531ms total)\r
+T220C 003:249 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00 returns 0x01 (0000ms, 2531ms total)\r
+T1854 003:277 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0001ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(FPSCR) returns 0x00000000 (0005ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:292 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2537ms total)\r
+T1854 003:292 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total)\r
+T1854 003:292 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS8) returns 0x00000000 (0001ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R12) returns 0x00000000 (0001ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2539ms total)\r
+T220C 003:312 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) - Data: 00 00 00 00 returns 0x01 (0000ms, 2539ms total)\r
+T220C 027:508 JLINK_Close() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001004) >0x78 JTAG> >0x08 JTAG> (0005ms, 2544ms total)\r
+T220C 027:508 (0005ms, 2544ms total)\r
+T220C 027:508 Closed (0005ms, 2544ms total)\r
--- /dev/null
+[BREAKPOINTS]\r
+ForceImpTypeAny = 0\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 1\r
+Device="Unspecified"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectGui xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_guix.xsd">
+
+ <SchemaVersion>-5.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <ViewPool/>
+
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+ </View>
+ <View>
+ <WinId>204</WinId>
+ <ViewName>Performance Analyzer</ViewName>
+ <TableColWidths>1028 154 154 210</TableColWidths>
+ </View>
+ </SECTreeCtrl>
+
+ <TreeListPane>
+ <View>
+ <WinId>1506</WinId>
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+ <UserString></UserString>
+ <TableColWidths>70 70 70</TableColWidths>
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+ <View>
+ <WinId>1936</WinId>
+ <ViewName>Watch 1</ViewName>
+ <UserString></UserString>
+ <TableColWidths>154 184 70</TableColWidths>
+ </View>
+ <View>
+ <WinId>1937</WinId>
+ <ViewName>Watch 2</ViewName>
+ <UserString></UserString>
+ <TableColWidths>70 70 70</TableColWidths>
+ </View>
+ <View>
+ <WinId>1935</WinId>
+ <ViewName>Call Stack + Locals</ViewName>
+ <UserString></UserString>
+ <TableColWidths>235 70 70</TableColWidths>
+ </View>
+ <View>
+ <WinId>2506</WinId>
+ <ViewName>Trace Data</ViewName>
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+ <TableColWidths>75 135 130 95 70 230 200 150</TableColWidths>
+ </View>
+ </TreeListPane>
+
+ <WindowSettings>
+ <LogicAnalizer>
+ <ShowLACursor>0</ShowLACursor>
+ <ShowSignalInfo>0</ShowSignalInfo>
+ <ShowCycles>0</ShowCycles>
+ <LeftSideBarSize>50</LeftSideBarSize>
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+ </LogicAnalizer>
+ </WindowSettings>
+
+ <WinLayoutEx>
+ <sActiveDebugView></sActiveDebugView>
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+ </MDITabState>
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--- /dev/null
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--- /dev/null
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+ <Header>### uVision Project, (C) Keil Software</Header>
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+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>1</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>1</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M4"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>1</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>1</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>0</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-mfloat-abi=softfp -mfpu=fpv4-sp-d16 -ffunction-sections -fdata-sections -O0 -g</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..;..\..\..\Source\include;..\..\..\Source\portable\GCC\ARM_CM4F;..\..\Common\include;..\peripheral_library;..\CMSIS;..\main_full</IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>1</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>0</enaGarb>
+ <noStart>1</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>1</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc>-Xlinker --gc-sections</Misc>
+ <ScatterFile>.\sections.ld</ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system.c</FilePath>
+ </File>
+ <File>
+ <FileName>startup_ARMCM4.S</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_ARMCM4.S</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>main_and_config</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\FreeRTOSConfig.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS_Source</GroupName>
+ <Files>
+ <File>
+ <FileName>event_groups.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\event_groups.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\MemMang\heap_4.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\GCC\ARM_CM4F\port.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>main_low_power</GroupName>
+ <Files>
+ <File>
+ <FileName>main_low_power.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main_low_power\main_low_power.c</FilePath>
+ </File>
+ <File>
+ <FileName>low_power_tick_config.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main_low_power\low_power_tick_config.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>main_full</GroupName>
+ <Files>
+ <File>
+ <FileName>main_full.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main_full\main_full.c</FilePath>
+ </File>
+ <File>
+ <FileName>RegTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\RegTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>flop.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\flop.c</FilePath>
+ </File>
+ <File>
+ <FileName>EventGroupsDemo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\EventGroupsDemo.c</FilePath>
+ </File>
+ <File>
+ <FileName>TaskNotify.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\TaskNotify.c</FilePath>
+ </File>
+ <File>
+ <FileName>blocktim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\blocktim.c</FilePath>
+ </File>
+ <File>
+ <FileName>dynamic.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\dynamic.c</FilePath>
+ </File>
+ <File>
+ <FileName>GenQTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\GenQTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>TimerDemo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\TimerDemo.c</FilePath>
+ </File>
+ <File>
+ <FileName>IntQueue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\IntQueue.c</FilePath>
+ </File>
+ <File>
+ <FileName>IntQueueTimer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main_full\IntQueueTimer.c</FilePath>
+ </File>
+ <File>
+ <FileName>countsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\countsem.c</FilePath>
+ </File>
+ <File>
+ <FileName>semtest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\semtest.c</FilePath>
+ </File>
+ <File>
+ <FileName>death.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\death.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>peripheral_library</GroupName>
+ <Files>
+ <File>
+ <FileName>btimer_api.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\basic_timer\btimer_api.c</FilePath>
+ </File>
+ <File>
+ <FileName>btimer_perphl.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\basic_timer\btimer_perphl.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register maintains its expected value for the lifetime of the\r
+ * task. Each task uses a different set of values. The reg test tasks execute\r
+ * with a very low priority, so get preempted very frequently. A register\r
+ * containing an unexpected value is indicative of an error in the context\r
+ * switching mechanism.\r
+ */\r
+\r
+void vRegTest1Implementation( void ) __attribute__ ((naked));\r
+void vRegTest2Implementation( void ) __attribute__ ((naked));\r
+\r
+void vRegTest1Implementation( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ ".extern ulRegTest1LoopCounter \n"\r
+ "/* Fill the core registers with known values. */ \n"\r
+ "mov r0, #100 \n"\r
+ "mov r1, #101 \n"\r
+ "mov r2, #102 \n"\r
+ "mov r3, #103 \n"\r
+ "mov r4, #104 \n"\r
+ "mov r5, #105 \n"\r
+ "mov r6, #106 \n"\r
+ "mov r7, #107 \n"\r
+ "mov r8, #108 \n"\r
+ "mov r9, #109 \n"\r
+ "mov r10, #110 \n"\r
+ "mov r11, #111 \n"\r
+ "mov r12, #112 \n"\r
+\r
+ "/* Fill the VFP registers with known values. */ \n"\r
+ "vmov d0, r0, r1 \n"\r
+ "vmov d1, r2, r3 \n"\r
+ "vmov d2, r4, r5 \n"\r
+ "vmov d3, r6, r7 \n"\r
+ "vmov d4, r8, r9 \n"\r
+ "vmov d5, r10, r11 \n"\r
+ "vmov d6, r0, r1 \n"\r
+ "vmov d7, r2, r3 \n"\r
+ "vmov d8, r4, r5 \n"\r
+ "vmov d9, r6, r7 \n"\r
+ "vmov d10, r8, r9 \n"\r
+ "vmov d11, r10, r11 \n"\r
+ "vmov d12, r0, r1 \n"\r
+ "vmov d13, r2, r3 \n"\r
+ "vmov d14, r4, r5 \n"\r
+ "vmov d15, r6, r7 \n"\r
+\r
+ "reg1_loop: \n"\r
+ "/* Check all the VFP registers still contain the values set above. \n"\r
+ "First save registers that are clobbered by the test. */ \n"\r
+ "push { r0-r1 } \n"\r
+\r
+ "vmov r0, r1, d0 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d1 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d2 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d3 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d4 \n"\r
+ "cmp r0, #108 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #109 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d5 \n"\r
+ "cmp r0, #110 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #111 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d6 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d7 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d8 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d9 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d10 \n"\r
+ "cmp r0, #108 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #109 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d11 \n"\r
+ "cmp r0, #110 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #111 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d12 \n"\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d13 \n"\r
+ "cmp r0, #102 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #103 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d14 \n"\r
+ "cmp r0, #104 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #105 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "vmov r0, r1, d15 \n"\r
+ "cmp r0, #106 \n"\r
+ "bne reg1_error_loopf \n"\r
+ "cmp r1, #107 \n"\r
+ "bne reg1_error_loopf \n"\r
+\r
+ "/* Restore the registers that were clobbered by the test. */ \n"\r
+ "pop {r0-r1} \n"\r
+\r
+ "/* VFP register test passed. Jump to the core register test. */ \n"\r
+ "b reg1_loopf_pass \n"\r
+\r
+ "reg1_error_loopf: \n"\r
+ "/* If this line is hit then a VFP register value was found to be incorrect. */ \n"\r
+ "b reg1_error_loopf \n"\r
+\r
+ "reg1_loopf_pass: \n"\r
+\r
+ "cmp r0, #100 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r1, #101 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r2, #102 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r3, #103 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r4, #104 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r5, #105 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r6, #106 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r7, #107 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r8, #108 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r9, #109 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r10, #110 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r11, #111 \n"\r
+ "bne reg1_error_loop \n"\r
+ "cmp r12, #112 \n"\r
+ "bne reg1_error_loop \n"\r
+\r
+ "/* Everything passed, increment the loop counter. */ \n"\r
+ "push { r0-r1 } \n"\r
+ "ldr r0, =ulRegTest1LoopCounter \n"\r
+ "ldr r1, [r0] \n"\r
+ "adds r1, r1, #1 \n"\r
+ "str r1, [r0] \n"\r
+ "pop { r0-r1 } \n"\r
+\r
+ "/* Start again. */ \n"\r
+ "b reg1_loop \n"\r
+\r
+ "reg1_error_loop: \n"\r
+ "/* If this line is hit then there was an error in a core register value. \n"\r
+ "The loop ensures the loop counter stops incrementing. */ \n"\r
+ "b reg1_error_loop \n"\r
+ "nop "\r
+ ); /* __asm volatile. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegTest2Implementation( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ ".extern ulRegTest2LoopCounter \n"\r
+ "/* Set all the core registers to known values. */ \n"\r
+ "mov r0, #-1 \n"\r
+ "mov r1, #1 \n"\r
+ "mov r2, #2 \n"\r
+ "mov r3, #3 \n"\r
+ "mov r4, #4 \n"\r
+ "mov r5, #5 \n"\r
+ "mov r6, #6 \n"\r
+ "mov r7, #7 \n"\r
+ "mov r8, #8 \n"\r
+ "mov r9, #9 \n"\r
+ "mov r10, #10 \n"\r
+ "mov r11, #11 \n"\r
+ "mov r12, #12 \n"\r
+\r
+ "/* Set all the VFP to known values. */ \n"\r
+ "vmov d0, r0, r1 \n"\r
+ "vmov d1, r2, r3 \n"\r
+ "vmov d2, r4, r5 \n"\r
+ "vmov d3, r6, r7 \n"\r
+ "vmov d4, r8, r9 \n"\r
+ "vmov d5, r10, r11 \n"\r
+ "vmov d6, r0, r1 \n"\r
+ "vmov d7, r2, r3 \n"\r
+ "vmov d8, r4, r5 \n"\r
+ "vmov d9, r6, r7 \n"\r
+ "vmov d10, r8, r9 \n"\r
+ "vmov d11, r10, r11 \n"\r
+ "vmov d12, r0, r1 \n"\r
+ "vmov d13, r2, r3 \n"\r
+ "vmov d14, r4, r5 \n"\r
+ "vmov d15, r6, r7 \n"\r
+\r
+ "reg2_loop: \n"\r
+\r
+ "/* Check all the VFP registers still contain the values set above. \n"\r
+ "First save registers that are clobbered by the test. */ \n"\r
+ "push { r0-r1 } \n"\r
+\r
+ "vmov r0, r1, d0 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d1 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d2 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d3 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d4 \n"\r
+ "cmp r0, #8 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #9 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d5 \n"\r
+ "cmp r0, #10 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #11 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d6 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d7 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d8 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d9 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d10 \n"\r
+ "cmp r0, #8 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #9 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d11 \n"\r
+ "cmp r0, #10 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #11 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d12 \n"\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d13 \n"\r
+ "cmp r0, #2 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #3 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d14 \n"\r
+ "cmp r0, #4 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #5 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "vmov r0, r1, d15 \n"\r
+ "cmp r0, #6 \n"\r
+ "bne reg2_error_loopf \n"\r
+ "cmp r1, #7 \n"\r
+ "bne reg2_error_loopf \n"\r
+\r
+ "/* Restore the registers that were clobbered by the test. */ \n"\r
+ "pop {r0-r1} \n"\r
+\r
+ "/* VFP register test passed. Jump to the core register test. */ \n"\r
+ "b reg2_loopf_pass \n"\r
+\r
+ "reg2_error_loopf: \n"\r
+ "/* If this line is hit then a VFP register value was found to be \n"\r
+ "incorrect. */ \n"\r
+ "b reg2_error_loopf \n"\r
+\r
+ "reg2_loopf_pass: \n"\r
+\r
+ "cmp r0, #-1 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r1, #1 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r2, #2 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r3, #3 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r4, #4 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r5, #5 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r6, #6 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r7, #7 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r8, #8 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r9, #9 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r10, #10 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r11, #11 \n"\r
+ "bne reg2_error_loop \n"\r
+ "cmp r12, #12 \n"\r
+ "bne reg2_error_loop \n"\r
+\r
+ "/* Increment the loop counter to indicate this test is still functioning \n"\r
+ "correctly. */ \n"\r
+ "push { r0-r1 } \n"\r
+ "ldr r0, =ulRegTest2LoopCounter \n"\r
+ "ldr r1, [r0] \n"\r
+ "adds r1, r1, #1 \n"\r
+ "str r1, [r0] \n"\r
+\r
+ "/* Yield to increase test coverage. */ \n"\r
+ "movs r0, #0x01 \n"\r
+ "ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ \n"\r
+ "lsl r0, r0, #28 /* Shift to PendSV bit */ \n"\r
+ "str r0, [r1] \n"\r
+ "dsb \n"\r
+\r
+ "pop { r0-r1 } \n"\r
+\r
+ "/* Start again. */ \n"\r
+ "b reg2_loop \n"\r
+\r
+ "reg2_error_loop: \n"\r
+ "/* If this line is hit then there was an error in a core register value. \n"\r
+ "This loop ensures the loop counter variable stops incrementing. */ \n"\r
+ "b reg2_error_loop \n"\r
+ ); /* __asm volatile */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+//Initialization file for the application code\r
+RESET\r
+T\r
+T\r
+T\r
+//eval PC = *(&(__isr_vector) + 1) ; // startup code loc to the Jump routine\r
+eval PC = Reset_Handler;\r
+T\r
--- /dev/null
+/*\r
+ * Memory Spaces Definitions.\r
+ *\r
+ * Need modifying for a specific board. \r
+ * FLASH.ORIGIN: starting address of flash\r
+ * FLASH.LENGTH: length of flash\r
+ * RAM.ORIGIN: starting address of RAM bank 0\r
+ * RAM.LENGTH: length of RAM bank 0\r
+ *\r
+ * The values below can be addressed in further linker scripts\r
+ * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.\r
+ */\r
+\r
+MEMORY\r
+{\r
+ ROM (rx) : ORIGIN = 0x100000, LENGTH = 0x18000\r
+ RAM (rw) : ORIGIN = 0x118000, LENGTH = 0x8000\r
+}\r
+\r
--- /dev/null
+/*\r
+ * Default linker script for GCC MEC1322\r
+ * Based upon linker scripts from GNU ARM Eclipse plug-in\r
+ */\r
+\r
+INCLUDE mem.ld\r
+\r
+/*\r
+ * The '__stack' definition is required by crt0, do not remove it.\r
+ */\r
+/* Place top of stack immediate before ROM Log\r
+ *__stack = ORIGIN(RAM) + LENGTH(RAM);\r
+ */\r
+__stack = ORIGIN(RAM) + LENGTH(RAM);\r
+\r
+_estack = __stack;\r
+\r
+/*\r
+ * Default stack sizes.\r
+ * These are used by the startup in order to allocate stacks\r
+ * for the different modes.\r
+ */\r
+\r
+__Main_Stack_Size = 2048 ;\r
+\r
+PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ;\r
+\r
+__Main_Stack_Limit = __stack - __Main_Stack_Size ;\r
+\r
+/*"PROVIDE" allows to easily override these values from an object file or the command line. */\r
+PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ;\r
+\r
+/*\r
+ * There will be a link error if there is not this amount of\r
+ * RAM free at the end.\r
+ */\r
+_Minimum_Stack_Size = 256 ;\r
+\r
+/*\r
+ * Default heap definitions.\r
+ * The heap start immediately after the last statically allocated\r
+ * .sbss/.noinit section, and extends up to the main stack limit.\r
+ */\r
+PROVIDE ( _Heap_Begin = _end_noinit ) ;\r
+PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ;\r
+\r
+/*\r
+ * The entry point is informative, for debuggers and simulators,\r
+ * since the Cortex-M vector points to it anyway.\r
+ */\r
+ENTRY(_start)\r
+\r
+/* Sections Definitions */\r
+\r
+SECTIONS\r
+{\r
+ /*\r
+ * For Cortex-M devices, the beginning of the startup code is stored in\r
+ * the .isr_vector section, which goes to ROM\r
+ */\r
+ \r
+ .isr_vector :\r
+ {\r
+ . = ALIGN(4);\r
+ _isr_vector = .;\r
+ KEEP(*(.isr_vector))\r
+ . = ALIGN(4);\r
+ } >ROM\r
+ \r
+ \r
+ .text :\r
+ {\r
+ . = ALIGN(4);\r
+\r
+ /*\r
+ * This section is here for convenience, to store the\r
+ * startup code at the beginning of the flash area, hoping that\r
+ * this will increase the readability of the listing.\r
+ */\r
+ KEEP(*(.after_vectors .after_vectors.*)) /* Startup code and ISR */\r
+\r
+ . = ALIGN(4);\r
+\r
+ /*\r
+ * These are the old initialisation sections, intended to contain\r
+ * naked code, with the prologue/epilogue added by crti.o/crtn.o\r
+ * when linking with startup files. The standalone startup code\r
+ * currently does not run these, better use the init arrays below.\r
+ */\r
+ KEEP(*(.init))\r
+ KEEP(*(.fini))\r
+\r
+ . = ALIGN(4);\r
+\r
+ /*\r
+ * The preinit code, i.e. an array of pointers to initialisation\r
+ * functions to be performed before constructors.\r
+ */\r
+ PROVIDE_HIDDEN (__preinit_array_start = .);\r
+\r
+ /*\r
+ * Used to run the SystemInit() before anything else.\r
+ */\r
+ KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))\r
+\r
+ /*\r
+ * Used for other platform inits.\r
+ */\r
+ KEEP(*(.preinit_array_platform .preinit_array_platform.*))\r
+\r
+ /*\r
+ * The application inits. If you need to enforce some order in\r
+ * execution, create new sections, as before.\r
+ */\r
+ KEEP(*(.preinit_array .preinit_array.*))\r
+\r
+ PROVIDE_HIDDEN (__preinit_array_end = .);\r
+\r
+ . = ALIGN(4);\r
+\r
+ /*\r
+ * The init code, i.e. an array of pointers to static constructors.\r
+ */\r
+ PROVIDE_HIDDEN (__init_array_start = .);\r
+ KEEP(*(SORT(.init_array.*)))\r
+ KEEP(*(.init_array))\r
+ PROVIDE_HIDDEN (__init_array_end = .);\r
+\r
+ . = ALIGN(4);\r
+\r
+ /*\r
+ * The fini code, i.e. an array of pointers to static destructors.\r
+ */\r
+ PROVIDE_HIDDEN (__fini_array_start = .);\r
+ KEEP(*(SORT(.fini_array.*)))\r
+ KEEP(*(.fini_array))\r
+ PROVIDE_HIDDEN (__fini_array_end = .);\r
+ . = ALIGN(4);\r
+\r
+ . = ALIGN(4);\r
+\r
+ *(.text*) /* all remaining code */\r
+\r
+ *(vtable) /* C++ virtual tables */\r
+\r
+ } >ROM\r
+\r
+ .rodata :\r
+ {\r
+ *(.rodata*) /* read-only data (constants) */\r
+ } >ROM\r
+\r
+ .glue :\r
+ {\r
+ KEEP(*(.eh_frame*))\r
+\r
+ /*\r
+ * Stub sections generated by the linker, to glue together\r
+ * ARM and Thumb code. .glue_7 is used for ARM code calling\r
+ * Thumb code, and .glue_7t is used for Thumb code calling\r
+ * ARM code. Apparently always generated by the linker, for some\r
+ * architectures, so better leave them here.\r
+ */\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ } >ROM\r
+\r
+ /* ARM magic sections */\r
+ .ARM.extab :\r
+ {\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ } > ROM\r
+\r
+ __exidx_start = .;\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > ROM\r
+ __exidx_end = .;\r
+\r
+ . = ALIGN(4);\r
+ _etext = .;\r
+ __etext = .;\r
+\r
+ /*\r
+ * This address is used by the startup code to\r
+ * initialise the .data section.\r
+ */\r
+ _sidata = _etext;\r
+\r
+ /* MEMORY_ARRAY */\r
+ /*\r
+ .ROarraySection :\r
+ {\r
+ *(.ROarraySection .ROarraySection.*)\r
+ } >MEMORY_ARRAY\r
+ */\r
+ /*\r
+ * The initialised data section.\r
+ * The program executes knowing that the data is in the RAM\r
+ * but the loader puts the initial values in the ROM (inidata).\r
+ * It is one task of the startup to copy the initial values from\r
+ * ROM to RAM.\r
+ */\r
+ .data : AT ( _sidata )\r
+ {\r
+ . = ALIGN(4);\r
+\r
+ /* This is used by the startup code to initialise the .data section */\r
+ _sdata = . ; /* STM specific definition */\r
+ __data_start__ = . ;\r
+ *(.data_begin .data_begin.*)\r
+\r
+ *(.data .data.*)\r
+\r
+ *(.data_end .data_end.*)\r
+ . = ALIGN(4);\r
+\r
+ /* This is used by the startup code to initialise the .data section */\r
+ _edata = . ; /* STM specific definition */\r
+ __data_end__ = . ;\r
+\r
+ } >RAM\r
+\r
+\r
+ /*\r
+ * The uninitialised data section. NOLOAD is used to avoid\r
+ * the "section `.bss' type changed to PROGBITS" warning\r
+ */\r
+ .bss (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ __bss_start__ = .; /* standard newlib definition */\r
+ _sbss = .; /* STM specific definition */\r
+ *(.bss_begin .bss_begin.*)\r
+\r
+ *(.bss .bss.*)\r
+ *(COMMON)\r
+\r
+ *(.bss_end .bss_end.*)\r
+ . = ALIGN(4);\r
+ __bss_end__ = .; /* standard newlib definition */\r
+ _ebss = . ; /* STM specific definition */\r
+ } >RAM\r
+\r
+ .noinit (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ _noinit = .;\r
+\r
+ *(.noinit .noinit.*)\r
+\r
+ . = ALIGN(4) ;\r
+ _end_noinit = .;\r
+ } > RAM\r
+\r
+ /* Mandatory to be word aligned, _sbrk assumes this */\r
+ PROVIDE ( end = _end_noinit ); /* was _ebss */\r
+ PROVIDE ( _end = _end_noinit );\r
+ PROVIDE ( __end = _end_noinit );\r
+ PROVIDE ( __end__ = _end_noinit );\r
+ PROVIDE ( ROM_DATA_START = __data_start__ );\r
+\r
+ /*\r
+ * Used for validation only, do not allocate anything here!\r
+ *\r
+ * This is just to check that there is enough RAM left for the Main\r
+ * stack. It should generate an error if it's full.\r
+ */\r
+ ._check_stack :\r
+ {\r
+ . = ALIGN(4);\r
+\r
+ . = . + _Minimum_Stack_Size ;\r
+\r
+ . = ALIGN(4);\r
+ } >RAM\r
+\r
+ ._check_rom_log :\r
+ {\r
+ . = ALIGN(4);\r
+\r
+/* . = . + __ROM_Log_Size ; */\r
+\r
+ . = ALIGN(4);\r
+ } >RAM\r
+\r
+/*\r
+ .bss_CCMRAM : ALIGN(4)\r
+ {\r
+ *(.bss.CCMRAM .bss.CCMRAM.*)\r
+ } > CCMRAM\r
+*/\r
+ /*\r
+ * The ROM Bank1.\r
+ * The C or assembly source must explicitly place the code\r
+ * or data there using the "section" attribute.\r
+ */\r
+\r
+\r
+ /* remaining code */\r
+ /* read-only data (constants) */\r
+/*\r
+ .b1text :\r
+ {\r
+ *(.b1text)\r
+ *(.b1rodata)\r
+ *(.b1rodata.*)\r
+ } >ROMB1\r
+*/\r
+ /*\r
+ * The EXTMEM.\r
+ * The C or assembly source must explicitly place the code or data there\r
+ * using the "section" attribute.\r
+ */\r
+\r
+ /* EXTMEM Bank0 */\r
+/*\r
+ .eb0text :\r
+ {\r
+ *(.eb0text)\r
+ *(.eb0rodata)\r
+ *(.eb0rodata.*)\r
+ } >EXTMEMB0\r
+*/\r
+ /* EXTMEM Bank1 */\r
+/*\r
+ .eb1text :\r
+ {\r
+ *(.eb1text)\r
+ *(.eb1rodata)\r
+ *(.eb1rodata.*)\r
+ } >EXTMEMB1\r
+*/\r
+ /* EXTMEM Bank2 */\r
+/*\r
+ .eb2text :\r
+ {\r
+ *(.eb2text)\r
+ *(.eb2rodata)\r
+ *(.eb2rodata.*)\r
+ } >EXTMEMB2\r
+*/\r
+ /* EXTMEM Bank0 */\r
+/*\r
+ .eb3text :\r
+ {\r
+ *(.eb3text)\r
+ *(.eb3rodata)\r
+ *(.eb3rodata.*)\r
+ } >EXTMEMB3\r
+*/\r
+\r
+ /* After that there are only debugging sections. */\r
+\r
+ /* This can remove the debugging information from the standard libraries */\r
+ /*\r
+ DISCARD :\r
+ {\r
+ libc.a ( * )\r
+ libm.a ( * )\r
+ libgcc.a ( * )\r
+ }\r
+ */\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /*\r
+ * DWARF debug sections.\r
+ * Symbols in the DWARF debugging sections are relative to the beginning\r
+ * of the section so we begin them at 0.\r
+ */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
--- /dev/null
+/* File: startup_ARMCM4.S
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V2.0
+ * Date: 16 August 2013
+ *
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+ .syntax unified
+ .arch armv7e-m
+
+ .section .stack
+ .align 3
+
+ .equ ulMainStackSize, 200 * 4
+ .equ Stack_Size, 0x004
+ .globl __StackTop
+ .globl __StackLimit
+ .extern ulMainStack
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector,"a",%progbits
+ .global __Vectors
+ .type __Vectors, %object
+ .size __Vectors, .-__Vectors
+__Vectors:
+ .long ulMainStack + ulMainStackSize /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long NVIC_Handler_I2C0
+ .long NVIC_Handler_I2C1
+ .long NVIC_Handler_I2C2
+ .long NVIC_Handler_I2C3
+ .long NVIC_Handler_DMA0
+ .long NVIC_Handler_DMA1
+ .long NVIC_Handler_DMA2
+ .long NVIC_Handler_DMA3
+ .long NVIC_Handler_DMA4
+ .long NVIC_Handler_DMA5
+ .long NVIC_Handler_DMA6
+ .long NVIC_Handler_DMA7
+ .long NVIC_Handler_LPCBERR
+ .long NVIC_Handler_UART0
+ .long NVIC_Handler_IMAP0
+ .long NVIC_Handler_EC0_IBF
+ .long NVIC_Handler_EC0_OBF
+ .long NVIC_Handler_EC1_IBF
+ .long NVIC_Handler_EC1_OBF
+ .long NVIC_Handler_PM1_CTL
+ .long NVIC_Handler_PM1_EN
+ .long NVIC_Handler_PM1_STS
+ .long NVIC_Handler_MIF8042_OBF
+ .long NVIC_Handler_MIF8042_IBF
+ .long NVIC_Handler_MAILBOX
+ .long NVIC_Handler_PECI
+ .long NVIC_Handler_TACH0
+ .long NVIC_Handler_TACH1
+ .long NVIC_Handler_ADC_SNGL
+ .long NVIC_Handler_ADC_RPT
+ .long NVIC_Handler_V2P_INT0
+ .long NVIC_Handler_V2P_INT1
+ .long NVIC_Handler_PS2_CH0
+ .long NVIC_Handler_PS2_CH1
+ .long NVIC_Handler_PS2_CH2
+ .long NVIC_Handler_PS2_CH3
+ .long NVIC_Handler_SPI0_TX
+ .long NVIC_Handler_SPI0_RX
+ .long NVIC_Handler_HIB_TMR
+ .long NVIC_Handler_KEY_INT
+ .long NVIC_Handler_KEY_WAKE
+ .long NVIC_Handler_RPM_STALL
+ .long NVIC_Handler_RPM_SPIN
+ .long NVIC_Handler_VBAT
+ .long NVIC_Handler_LED0
+ .long NVIC_Handler_LED1
+ .long NVIC_Handler_LED2
+ .long NVIC_Handler_MBC_ERR
+ .long NVIC_Handler_MBC_BUSY
+ .long NVIC_Handler_TMR0
+ .long NVIC_Handler_TMR1
+ .long NVIC_Handler_TMR2
+ .long NVIC_Handler_TMR3
+ .long NVIC_Handler_TMR4
+ .long NVIC_Handler_TMR5
+ .long NVIC_Handler_SPI1_TX
+ .long NVIC_Handler_SPI1_RX
+ .long NVIC_Handler_GIRQ08
+ .long NVIC_Handler_GIRQ09
+ .long NVIC_Handler_GIRQ10
+ .long NVIC_Handler_GIRQ11
+ ;.long NVIC_Handler_GIRQ12
+ .long interrupt_irq12
+ ;.long NVIC_Handler_GIRQ13
+ .long NVIC_Handler_GIRQ13
+ .long NVIC_Handler_GIRQ14
+ .long NVIC_Handler_GIRQ15
+ .long NVIC_Handler_GIRQ16
+ .long NVIC_Handler_GIRQ17
+ .long NVIC_Handler_GIRQ18
+ .long NVIC_Handler_GIRQ19
+ .long NVIC_Handler_GIRQ20
+ .long NVIC_Handler_GIRQ21
+ .long NVIC_Handler_GIRQ22
+ .long NVIC_Handler_GIRQ23
+ .long NVIC_Handler_073
+ .long NVIC_Handler_074
+ .long NVIC_Handler_075
+ .long NVIC_Handler_076
+ .long NVIC_Handler_077
+ .long NVIC_Handler_078
+ .long NVIC_Handler_079
+ .long NVIC_Handler_080
+ .long NVIC_Handler_DMA8
+ .long NVIC_Handler_DMA9
+ .long NVIC_Handler_DMA10
+ .long NVIC_Handler_DMA11
+ .long NVIC_Handler_LED3
+ .long NVIC_Handler_PKE_ERR
+ .long NVIC_Handler_PKE_END
+ .long NVIC_Handler_TRNG
+ .long NVIC_Handler_AES
+ .long NVIC_Handler_HASH
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl _start
+ .extern main
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+_start:
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr sp, =ulMainStack + ulMainStackSize
+ sub sp, sp, #4
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+
+ /* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+
+#ifndef __NO_SYSTEM_INIT
+/* bl SystemInit */
+#endif
+
+ bl main
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+/* def_irq_handler SVC_Handler */
+ def_irq_handler DebugMon_Handler
+/* def_irq_handler PendSV_Handler */
+/* def_irq_handler SysTick_Handler */
+ def_irq_handler DEF_IRQHandler
+
+ def_irq_handler NVIC_Handler_I2C0
+ def_irq_handler NVIC_Handler_I2C1
+ def_irq_handler NVIC_Handler_I2C2
+ def_irq_handler NVIC_Handler_I2C3
+ def_irq_handler NVIC_Handler_DMA0
+ def_irq_handler NVIC_Handler_DMA1
+ def_irq_handler NVIC_Handler_DMA2
+ def_irq_handler NVIC_Handler_DMA3
+ def_irq_handler NVIC_Handler_DMA4
+ def_irq_handler NVIC_Handler_DMA5
+ def_irq_handler NVIC_Handler_DMA6
+ def_irq_handler NVIC_Handler_DMA7
+ def_irq_handler NVIC_Handler_LPCBERR
+ def_irq_handler NVIC_Handler_UART0
+ def_irq_handler NVIC_Handler_IMAP0
+ def_irq_handler NVIC_Handler_EC0_IBF
+ def_irq_handler NVIC_Handler_EC0_OBF
+ def_irq_handler NVIC_Handler_EC1_IBF
+ def_irq_handler NVIC_Handler_EC1_OBF
+ def_irq_handler NVIC_Handler_PM1_CTL
+ def_irq_handler NVIC_Handler_PM1_EN
+ def_irq_handler NVIC_Handler_PM1_STS
+ def_irq_handler NVIC_Handler_MIF8042_OBF
+ def_irq_handler NVIC_Handler_MIF8042_IBF
+ def_irq_handler NVIC_Handler_MAILBOX
+ def_irq_handler NVIC_Handler_PECI
+ def_irq_handler NVIC_Handler_TACH0
+ def_irq_handler NVIC_Handler_TACH1
+ def_irq_handler NVIC_Handler_ADC_SNGL
+ def_irq_handler NVIC_Handler_ADC_RPT
+ def_irq_handler NVIC_Handler_V2P_INT0
+ def_irq_handler NVIC_Handler_V2P_INT1
+ def_irq_handler NVIC_Handler_PS2_CH0
+ def_irq_handler NVIC_Handler_PS2_CH1
+ def_irq_handler NVIC_Handler_PS2_CH2
+ def_irq_handler NVIC_Handler_PS2_CH3
+ def_irq_handler NVIC_Handler_SPI0_TX
+ def_irq_handler NVIC_Handler_SPI0_RX
+ def_irq_handler NVIC_Handler_HIB_TMR
+ def_irq_handler NVIC_Handler_KEY_INT
+ def_irq_handler NVIC_Handler_KEY_WAKE
+ def_irq_handler NVIC_Handler_RPM_STALL
+ def_irq_handler NVIC_Handler_RPM_SPIN
+ def_irq_handler NVIC_Handler_VBAT
+ def_irq_handler NVIC_Handler_LED0
+ def_irq_handler NVIC_Handler_LED1
+ def_irq_handler NVIC_Handler_LED2
+ def_irq_handler NVIC_Handler_MBC_ERR
+ def_irq_handler NVIC_Handler_MBC_BUSY
+ def_irq_handler NVIC_Handler_TMR0
+ def_irq_handler NVIC_Handler_TMR1
+ def_irq_handler NVIC_Handler_TMR2
+ def_irq_handler NVIC_Handler_TMR3
+ def_irq_handler NVIC_Handler_TMR4
+ def_irq_handler NVIC_Handler_TMR5
+ def_irq_handler NVIC_Handler_SPI1_TX
+ def_irq_handler NVIC_Handler_SPI1_RX
+ def_irq_handler NVIC_Handler_GIRQ08
+ def_irq_handler NVIC_Handler_GIRQ09
+ def_irq_handler NVIC_Handler_GIRQ10
+ def_irq_handler NVIC_Handler_GIRQ11
+ ;def_irq_handler NVIC_Handler_GIRQ12
+ def_irq_handler interrupt_irq12
+ ;def_irq_handler NVIC_Handler_GIRQ13
+ def_irq_handler interrupt_irq13
+ def_irq_handler NVIC_Handler_GIRQ14
+ def_irq_handler NVIC_Handler_GIRQ15
+ def_irq_handler NVIC_Handler_GIRQ16
+ def_irq_handler NVIC_Handler_GIRQ17
+ def_irq_handler NVIC_Handler_GIRQ18
+ def_irq_handler NVIC_Handler_GIRQ19
+ def_irq_handler NVIC_Handler_GIRQ20
+ def_irq_handler NVIC_Handler_GIRQ21
+ def_irq_handler NVIC_Handler_GIRQ22
+ def_irq_handler NVIC_Handler_GIRQ23
+ def_irq_handler NVIC_Handler_073
+ def_irq_handler NVIC_Handler_074
+ def_irq_handler NVIC_Handler_075
+ def_irq_handler NVIC_Handler_076
+ def_irq_handler NVIC_Handler_077
+ def_irq_handler NVIC_Handler_078
+ def_irq_handler NVIC_Handler_079
+ def_irq_handler NVIC_Handler_080
+ def_irq_handler NVIC_Handler_DMA8
+ def_irq_handler NVIC_Handler_DMA9
+ def_irq_handler NVIC_Handler_DMA10
+ def_irq_handler NVIC_Handler_DMA11
+ def_irq_handler NVIC_Handler_LED3
+ def_irq_handler NVIC_Handler_PKE_ERR
+ def_irq_handler NVIC_Handler_PKE_END
+ def_irq_handler NVIC_Handler_TRNG
+ def_irq_handler NVIC_Handler_AES
+ def_irq_handler NVIC_Handler_HASH
+
+ .end
--- /dev/null
+/****************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+*/\r
+\r
+/** @defgroup pwm pwm_c_wrapper\r
+ * @{\r
+ */\r
+/** @file pwm_c_wrapper.cpp\r
+ \brief the pwm component C wrapper \r
+ This program is designed to allow the other C programs to be able to use this component\r
+\r
+ There are entry points for all C wrapper API implementation\r
+\r
+<b>Platform:</b> This is ARC-based component \r
+\r
+<b>Toolset:</b> Metaware IDE(8.5.1)\r
+<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
+\r
+/*******************************************************************************\r
+ * SMSC version control information (Perforce):\r
+ *\r
+ * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/system/system.c $\r
+ * REVISION: $Revision: #1 $\r
+ * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
+ * AUTHOR: $Author: akrishnan $\r
+ *\r
+ * Revision history (latest first):\r
+ * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1) \r
+ * #2 2011/03/25 martin_y support FPGA build 058 apps\r
+ * #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200\r
+ ***********************************************************************************\r
+ */\r
+/* Imported Header File */\r
+//#include "common.h"\r
+//#include "build.h"\r
+#include <stdint.h>\r
+\r
+#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120\r
+#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))\r
+#define CPU_CLOCK_DIVIDER 1\r
+\r
+/* The start up code is configured to use the following array as the stack used\r
+by main(), which will then also get used by FreeRTOS interrupt handlers after \r
+the scheduler has been started. */\r
+#warning If the array size is modified here then ulMainStackSize must also be modified in startup_ARMCM4.S.\r
+volatile uint32_t ulMainStack[ 200 ];\r
+\r
+/******************************************************************************/\r
+/** system_set_ec_clock\r
+* Set CPU speed\r
+* @param void\r
+* @return void\r
+*******************************************************************************/\r
+\r
+void system_set_ec_clock(void)\r
+{\r
+\r
+ /* Set ARC CPU Clock Divider to determine the CPU speed */\r
+ /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */\r
+ MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER;\r
+\r
+} /* End system_set_ec_clock() */\r
+\r
--- /dev/null
+\r
+T220C 000:298 SEGGER J-Link V4.98e Log File (0000ms, 0270ms total)\r
+T220C 000:298 DLL Compiled: May 5 2015 11:00:52 (0000ms, 0270ms total)\r
+T220C 000:298 Logging started @ 2016-01-08 12:24 (0000ms, 0270ms total)\r
+T220C 000:298 JLINK_SetWarnOutHandler(...) (0000ms, 0270ms total)\r
+T220C 000:298 JLINK_OpenEx(...)
+Firmware: J-Link V9 compiled Oct 9 2015 20:34:47
+Hardware: V9.10
+S/N: 59101789
+Feature(s): GDB, JFlash returns O.K. (0266ms, 0536ms total)\r
+T220C 000:564 JLINK_SetErrorOutHandler(...) (0000ms, 0536ms total)\r
+T220C 000:564 JLINK_ExecCommand("ProjectFile = "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M4F_CEC1302_Clicker_2\Keil_Specific\JLinkSettings.ini"", ...)Device "UNSPECIFIED" selected. returns 0x00 (0002ms, 0538ms total)\r
+T220C 000:566 JLINK_ExecCommand("Device = ARMCM4_FP", ...)Device "UNSPECIFIED" selected. returns 0x00 (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetCompileDateTime() (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total)\r
+T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0001ms, 0539ms total)\r
+T220C 000:567 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0003ms, 0542ms total)\r
+T220C 000:570 JLINK_SetSpeed(5000) (0000ms, 0542ms total)\r
+T220C 000:570 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 4, IRPrint = 0x01 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x48 JTAG> >0x78 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG>Found Cortex-M4 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC)\r
+ -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0)\r
+ -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)\r
+ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM ScanLen=4 NumDevices=1 aId[0]=0x4BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0026ms, 0568ms total)\r
+T220C 000:596 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x4BA00477 (0000ms, 0568ms total)\r
+T220C 000:596 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0000ms, 0568ms total)\r
+T220C 000:596 JLINK_GetDLLVersion() returns 49805 (0000ms, 0568ms total)\r
+T220C 000:596 JLINK_CORE_GetFound() returns 0xE0000FF (0000ms, 0568ms total)\r
+T220C 000:596 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003 returns 0x00 (0000ms, 0568ms total)\r
+T220C 000:596 JLINK_ReadMem (0xE00FF000, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 03 10 F0 FF ... returns 0x00 (0001ms, 0569ms total)\r
+T220C 000:597 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0570ms total)\r
+T220C 000:598 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0571ms total)\r
+T220C 000:599 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0571ms total)\r
+T220C 000:599 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0572ms total)\r
+T220C 000:600 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0573ms total)\r
+T220C 000:601 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0573ms total)\r
+T220C 000:601 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0574ms total)\r
+T220C 000:602 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0574ms total)\r
+T220C 000:602 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0575ms total)\r
+T220C 000:603 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0576ms total)\r
+T220C 000:604 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0576ms total)\r
+T220C 000:604 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0577ms total)\r
+T220C 000:605 JLINK_ReadMemU32(0xE000EF40, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF40) - Data: 21 00 11 10 returns 0x01 (0001ms, 0578ms total)\r
+T220C 000:606 JLINK_ReadMemU32(0xE000EF44, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF44) - Data: 11 00 00 11 returns 0x01 (0000ms, 0578ms total)\r
+T220C 000:606 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 41 C2 0F 41 returns 0x01 (0001ms, 0579ms total)\r
+T220C 000:607 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0579ms total)\r
+T220C 000:607 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048)\r
+ -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1225ms total)\r
+T220C 001:253 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1225ms total)\r
+T220C 001:253 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1225ms total)\r
+T220C 001:253 JLINK_Halt() returns 0x00 (0000ms, 1225ms total)\r
+T220C 001:253 JLINK_IsHalted() returns TRUE (0000ms, 1225ms total)\r
+T220C 001:253 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 1226ms total)\r
+T220C 001:254 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0000ms, 1226ms total)\r
+T220C 001:254 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 1227ms total)\r
+T220C 001:255 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_GetSpeed() returns 0x1388 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0000ms, 1227ms total)\r
+T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0001ms, 1228ms total)\r
+T220C 001:257 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 1229ms total)\r
+T220C 001:258 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 1230ms total)\r
+T220C 001:259 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1230ms total)\r
+T220C 001:259 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1230ms total)\r
+T220C 001:270 JLINK_WriteMem(0x00100000, 0x02AC Bytes, ...) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... -- CPU_WriteMem(684 bytes @ 0x00100000) returns 0x2AC (0003ms, 1233ms total)\r
+T220C 001:273 JLINK_ReadMem (0x00100000, 0x02AC Bytes, ...) -- CPU_ReadMem(684 bytes @ 0x00100000) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... returns 0x00 (0003ms, 1236ms total)\r
+T220C 001:330 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1236ms total)\r
+T220C 001:330 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1882ms total)\r
+T220C 001:977 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1882ms total)\r
+T220C 001:977 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1882ms total)\r
+T220C 001:977 JLINK_ReadMem (0x00118000, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x00118000) - Data: FE E7 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... returns 0x00 (0001ms, 1883ms total)\r
+T220C 002:517 JLINK_ReadMem (0x001001DA, 0x0002 Bytes, ...) -- CPU_ReadMem(2 bytes @ 0x001001DA) - Data: 00 47 returns 0x00 (0001ms, 1884ms total)\r
+T220C 002:518 JLINK_ReadMem (0x001001DC, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x001001DC) - Data: 4F F0 01 07 FE E7 4F F0 02 07 FE E7 4F F0 03 07 ... returns 0x00 (0001ms, 1885ms total)\r
+T220C 002:601 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1885ms total)\r
+T220C 002:601 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)\r
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 2531ms total)\r
+T220C 003:248 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2531ms total)\r
+T220C 003:249 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2531ms total)\r
+T220C 003:249 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00 returns 0x01 (0000ms, 2531ms total)\r
+T1854 003:277 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0001ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2532ms total)\r
+T1854 003:278 JLINK_ReadReg(FPSCR) returns 0x00000000 (0005ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:283 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:284 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:292 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2537ms total)\r
+T1854 003:292 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total)\r
+T1854 003:292 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total)\r
+T1854 003:293 JLINK_ReadReg(FPS8) returns 0x00000000 (0001ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:294 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2538ms total)\r
+T1854 003:297 JLINK_ReadReg(R12) returns 0x00000000 (0001ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2539ms total)\r
+T1854 003:298 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2539ms total)\r
+T220C 003:312 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) - Data: 00 00 00 00 returns 0x01 (0000ms, 2539ms total)\r
+T220C 027:508 JLINK_Close() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001004) >0x78 JTAG> >0x08 JTAG> (0005ms, 2544ms total)\r
+T220C 027:508 (0005ms, 2544ms total)\r
+T220C 027:508 Closed (0005ms, 2544ms total)\r
--- /dev/null
+[BREAKPOINTS]\r
+ForceImpTypeAny = 0\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 1\r
+Device="Unspecified"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+; *************************************************************\r
+; *** Scatter-Loading Description File generated by uVision ***\r
+; *************************************************************\r
+\r
+\r
+LR_IROM1 0x00100000 0x00020000 { ; load region size_region\r
+ ER_IROM1 0x00000000 0x00000000 { ; load address = execution address\r
+ }\r
+ RW_IRAM1 0x00100000 0x00020000 { ; RW data\r
+ *.o (RESET, +First)\r
+ *(InRoot$$Sections)\r
+ .ANY (+RO)\r
+ .ANY (+RW +ZI)\r
+ }\r
+}\r
+\r
+\r
+;LR_IROM1 0x00100000 0x00018000 { ; load region size_region\r
+; ER_IROM1 0x00100000 0x00018000 { ; load address = execution address\r
+; *.o (RESET, +First)\r
+; *(InRoot$$Sections)\r
+; .ANY (+RO)\r
+; }\r
+; RW_IRAM1 0x00118000 0x00008000 { ; RW data\r
+; .ANY (+RW +ZI)\r
+; }\r
+;}\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ <nMigrate>0</nMigrate>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>RTOSDemo</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>48000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\Listings\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>0</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>1</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile>init_app.ini</tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGUARM</Key>
+ <Name>(105=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMRTXEVENTFLAGS</Key>
+ <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGTARM</Key>
+ <Name>(1010=1231,224,1641,767,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UV1115SAE -O2983 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0100000 -FL018000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <WatchWindow1>
+ <Ww>
+ <count>0</count>
+ <WinNumber>1</WinNumber>
+ <ItemText>ulLED,0x0A</ItemText>
+ </Ww>
+ </WatchWindow1>
+ <MemoryWindow1>
+ <Mm>
+ <WinNumber>1</WinNumber>
+ <SubType>2</SubType>
+ <ItemText>0xe000e284</ItemText>
+ <AccSizeX>4</AccSizeX>
+ </Mm>
+ </MemoryWindow1>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ <Lin2Executable></Lin2Executable>
+ <Lin2ConfigFile></Lin2ConfigFile>
+ <bLin2Auto>0</bLin2Auto>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>System</GroupName>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_CEC1302.s</PathWithFileName>
+ <FilenameWithoutPath>startup_CEC1302.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\system.c</PathWithFileName>
+ <FilenameWithoutPath>system.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>main_and_config</GroupName>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>5</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\FreeRTOSConfig.h</PathWithFileName>
+ <FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>FreeRTOS_Source</GroupName>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\Source\event_groups.c</PathWithFileName>
+ <FilenameWithoutPath>event_groups.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>6</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\Source\list.c</PathWithFileName>
+ <FilenameWithoutPath>list.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>7</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\Source\queue.c</PathWithFileName>
+ <FilenameWithoutPath>queue.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>8</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\Source\tasks.c</PathWithFileName>
+ <FilenameWithoutPath>tasks.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>9</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\Source\timers.c</PathWithFileName>
+ <FilenameWithoutPath>timers.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>10</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\Source\portable\MemMang\heap_4.c</PathWithFileName>
+ <FilenameWithoutPath>heap_4.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>11</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>1</tvExp>
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--- /dev/null
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+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..;..\..\..\Source\include;..\..\..\Source\portable\RVDS\ARM_CM4F;..\..\Common\include;..\peripheral_library;..\CMSIS;..\main_full</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile>RTOSDemo.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_CEC1302.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_CEC1302.s</FilePath>
+ </File>
+ <File>
+ <FileName>system.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>main_and_config</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\FreeRTOSConfig.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS_Source</GroupName>
+ <GroupOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <GroupArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>2</interw>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <thumb>2</thumb>
+ <SplitLS>2</SplitLS>
+ <SwStkChk>2</SwStkChk>
+ <NoWarn>2</NoWarn>
+ <uSurpInc>2</uSurpInc>
+ <useXO>2</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ </GroupArmAds>
+ </GroupOption>
+ <Files>
+ <File>
+ <FileName>event_groups.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\event_groups.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\MemMang\heap_4.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>main_low_power</GroupName>
+ <Files>
+ <File>
+ <FileName>main_low_power.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main_low_power\main_low_power.c</FilePath>
+ </File>
+ <File>
+ <FileName>low_power_tick_config.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main_low_power\low_power_tick_config.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>main_full</GroupName>
+ <Files>
+ <File>
+ <FileName>main_full.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main_full\main_full.c</FilePath>
+ </File>
+ <File>
+ <FileName>RegTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\RegTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>flop.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\flop.c</FilePath>
+ </File>
+ <File>
+ <FileName>EventGroupsDemo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\EventGroupsDemo.c</FilePath>
+ </File>
+ <File>
+ <FileName>TaskNotify.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\TaskNotify.c</FilePath>
+ </File>
+ <File>
+ <FileName>blocktim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\blocktim.c</FilePath>
+ </File>
+ <File>
+ <FileName>dynamic.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\dynamic.c</FilePath>
+ </File>
+ <File>
+ <FileName>GenQTest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\GenQTest.c</FilePath>
+ </File>
+ <File>
+ <FileName>TimerDemo.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\TimerDemo.c</FilePath>
+ </File>
+ <File>
+ <FileName>IntQueue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\IntQueue.c</FilePath>
+ </File>
+ <File>
+ <FileName>IntQueueTimer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\main_full\IntQueueTimer.c</FilePath>
+ </File>
+ <File>
+ <FileName>countsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\countsem.c</FilePath>
+ </File>
+ <File>
+ <FileName>semtest.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\semtest.c</FilePath>
+ </File>
+ <File>
+ <FileName>death.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Common\Minimal\death.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>peripheral_library</GroupName>
+ <Files>
+ <File>
+ <FileName>btimer_api.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\basic_timer\btimer_api.c</FilePath>
+ </File>
+ <File>
+ <FileName>btimer_perphl.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\basic_timer\btimer_perphl.c</FilePath>
+ </File>
+ <File>
+ <FileName>pcr_perphl.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\pcr\pcr_perphl.c</FilePath>
+ </File>
+ <File>
+ <FileName>pcr_api.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\peripheral_library\pcr\pcr_api.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register maintains its expected value for the lifetime of the\r
+ * task. Each task uses a different set of values. The reg test tasks execute\r
+ * with a very low priority, so get preempted very frequently. A register\r
+ * containing an unexpected value is indicative of an error in the context\r
+ * switching mechanism.\r
+ */\r
+ \r
+ \r
+__asm void vRegTest1Implementation( void )\r
+{\r
+ PRESERVE8\r
+ IMPORT ulRegTest1LoopCounter\r
+\r
+ /* Fill the core registers with known values. */\r
+ mov r0, #100\r
+ mov r1, #101\r
+ mov r2, #102\r
+ mov r3, #103\r
+ mov r4, #104\r
+ mov r5, #105\r
+ mov r6, #106\r
+ mov r7, #107\r
+ mov r8, #108\r
+ mov r9, #109\r
+ mov r10, #110\r
+ mov r11, #111\r
+ mov r12, #112\r
+\r
+ /* Fill the VFP registers with known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg1_loop\r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #108\r
+ bne reg1_error_loopf\r
+ cmp r1, #109\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #110\r
+ bne reg1_error_loopf\r
+ cmp r1, #111\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #100\r
+ bne reg1_error_loopf\r
+ cmp r1, #101\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #102\r
+ bne reg1_error_loopf\r
+ cmp r1, #103\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #104\r
+ bne reg1_error_loopf\r
+ cmp r1, #105\r
+ bne reg1_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #106\r
+ bne reg1_error_loopf\r
+ cmp r1, #107\r
+ bne reg1_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg1_loopf_pass\r
+\r
+reg1_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg1_error_loopf\r
+\r
+reg1_loopf_pass\r
+\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ cmp r8, #108\r
+ bne reg1_error_loop\r
+ cmp r9, #109\r
+ bne reg1_error_loop\r
+ cmp r10, #110\r
+ bne reg1_error_loop\r
+ cmp r11, #111\r
+ bne reg1_error_loop\r
+ cmp r12, #112\r
+ bne reg1_error_loop\r
+ \r
+ /* Everything passed, increment the loop counter. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__asm void vRegTest2Implementation( void )\r
+{\r
+ PRESERVE8\r
+ IMPORT ulRegTest2LoopCounter\r
+\r
+ /* Set all the core registers to known values. */\r
+ mov r0, #-1\r
+ mov r1, #1\r
+ mov r2, #2\r
+ mov r3, #3\r
+ mov r4, #4\r
+ mov r5, #5\r
+ mov r6, #6\r
+ mov r7, #7\r
+ mov r8, #8\r
+ mov r9, #9\r
+ mov r10, #10\r
+ mov r11, #11\r
+ mov r12, #12\r
+\r
+ /* Set all the VFP to known values. */\r
+ vmov d0, r0, r1\r
+ vmov d1, r2, r3\r
+ vmov d2, r4, r5\r
+ vmov d3, r6, r7\r
+ vmov d4, r8, r9\r
+ vmov d5, r10, r11\r
+ vmov d6, r0, r1\r
+ vmov d7, r2, r3\r
+ vmov d8, r4, r5\r
+ vmov d9, r6, r7\r
+ vmov d10, r8, r9\r
+ vmov d11, r10, r11\r
+ vmov d12, r0, r1\r
+ vmov d13, r2, r3\r
+ vmov d14, r4, r5\r
+ vmov d15, r6, r7\r
+\r
+reg2_loop\r
+ \r
+ /* Check all the VFP registers still contain the values set above.\r
+ First save registers that are clobbered by the test. */\r
+ push { r0-r1 }\r
+ \r
+ vmov r0, r1, d0\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d1\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d2\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d3\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d4\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d5\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d6\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d7\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d8\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d9\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d10\r
+ cmp r0, #8\r
+ bne reg2_error_loopf\r
+ cmp r1, #9\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d11\r
+ cmp r0, #10\r
+ bne reg2_error_loopf\r
+ cmp r1, #11\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d12\r
+ cmp r0, #-1\r
+ bne reg2_error_loopf\r
+ cmp r1, #1\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d13\r
+ cmp r0, #2\r
+ bne reg2_error_loopf\r
+ cmp r1, #3\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d14\r
+ cmp r0, #4\r
+ bne reg2_error_loopf\r
+ cmp r1, #5\r
+ bne reg2_error_loopf\r
+ vmov r0, r1, d15\r
+ cmp r0, #6\r
+ bne reg2_error_loopf\r
+ cmp r1, #7\r
+ bne reg2_error_loopf\r
+ \r
+ /* Restore the registers that were clobbered by the test. */\r
+ pop {r0-r1}\r
+ \r
+ /* VFP register test passed. Jump to the core register test. */\r
+ b reg2_loopf_pass\r
+\r
+reg2_error_loopf\r
+ /* If this line is hit then a VFP register value was found to be\r
+ incorrect. */\r
+ b reg2_error_loopf\r
+\r
+reg2_loopf_pass\r
+\r
+ cmp r0, #-1\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ cmp r8, #8\r
+ bne reg2_error_loop\r
+ cmp r9, #9\r
+ bne reg2_error_loop\r
+ cmp r10, #10\r
+ bne reg2_error_loop\r
+ cmp r11, #11\r
+ bne reg2_error_loop\r
+ cmp r12, #12\r
+ bne reg2_error_loop\r
+ \r
+ /* Increment the loop counter to indicate this test is still functioning\r
+ correctly. */\r
+ push { r0-r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ \r
+ /* Yield to increase test coverage. */\r
+ movs r0, #0x01\r
+ ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */\r
+ lsl r0, r0, #28 /* Shift to PendSV bit */\r
+ str r0, [r1]\r
+ dsb\r
+ \r
+ pop { r0-r1 }\r
+ \r
+ /* Start again. */\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ This loop ensures the loop counter variable stops incrementing. */\r
+ b reg2_error_loop\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+//Initialization file for the application code\r
+RESET\r
+T\r
+T\r
+T\r
+eval PC = *(&(__Vectors) + 1) ; // startup code loc to the Jump routine\r
+T\r
--- /dev/null
+;/*\r
+;******************************************************************************\r
+;* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+;* You may use this software and any derivatives exclusively with\r
+;* Microchip products.\r
+;* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+;* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+;* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+;* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+;* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+;* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+;* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+;* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+;* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+;* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+;* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+;* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+;* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+;* OF THESE TERMS.\r
+;******************************************************************************\r
+; */\r
+;/** @file startup_MEC1322.s\r
+; *MEC1322 API Test: startup and vector table\r
+; */\r
+;/** @defgroup startup_MEC1322\r
+; * @{\r
+; */\r
+\r
+ IMPORT __main\r
+ IMPORT |Image$$RW_IRAM1$$Base|\r
+ IMPORT |Image$$RW_IRAM1$$Limit|\r
+ IMPORT |Image$$RW_IRAM1$$Length|\r
+ IMPORT |Image$$RW_IRAM1$$ZI$$Base|\r
+ IMPORT |Image$$RW_IRAM1$$ZI$$Limit|\r
+ IMPORT |Image$$ER_IROM1$$Base|\r
+ IMPORT |Image$$ER_IROM1$$Limit|\r
+ IMPORT main\r
+ IMPORT system_set_ec_clock\r
+\r
+ EXPORT Reset_Handler\r
+\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000800\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+ EXPORT __stack_bottom\r
+__stack_bottom\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000000 \r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __tx_vectors\r
+__tx_vectors\r
+__Vectors DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ ; MEC1322 External Interrupts\r
+ DCD NVIC_Handler_I2C0 ; 40h: 0, I2C/SMBus 0\r
+ DCD NVIC_Handler_I2C1 ; 44h: 1, I2C/SMBus 1\r
+ DCD NVIC_Handler_I2C2 ; 48h: 2, I2C/SMBus 2\r
+ DCD NVIC_Handler_I2C3 ; 4Ch: 3, I2C/SMBus 3\r
+ DCD NVIC_Handler_DMA0 ; 50h: 4, DMA Channel 0\r
+ DCD NVIC_Handler_DMA1 ; 54h: 5, DMA Channel 1\r
+ DCD NVIC_Handler_DMA2 ; 58h: 6, DMA Channel 2\r
+ DCD NVIC_Handler_DMA3 ; 5Ch: 7, DMA Channel 3\r
+ DCD NVIC_Handler_DMA4 ; 60h: 8, DMA Channel 4\r
+ DCD NVIC_Handler_DMA5 ; 64h: 9, DMA Channel 5\r
+ DCD NVIC_Handler_DMA6 ; 68h: 10, DMA Channel 6\r
+ DCD NVIC_Handler_DMA7 ; 6Ch: 11, DMA Channel 7\r
+ DCD NVIC_Handler_LPCBERR ; 70h: 12, LPC Bus Error\r
+ DCD NVIC_Handler_UART0 ; 74h: 13, UART0\r
+ DCD NVIC_Handler_IMAP0 ; 78h: 14, IMAP0\r
+ DCD NVIC_Handler_EC0_IBF ; 7Ch: 15, ACPI_EC0_IBF\r
+ DCD NVIC_Handler_EC0_OBF ; 80h: 16, ACPI_EC0_OBF\r
+ DCD NVIC_Handler_EC1_IBF ; 84h: 17, ACPI_EC1_IBF\r
+ DCD NVIC_Handler_EC1_OBF ; 88h: 18, ACPI_EC1_OBF\r
+ DCD NVIC_Handler_PM1_CTL ; 8Ch: 19, ACPI_PM1_CTL\r
+ DCD NVIC_Handler_PM1_EN ; 90h: 20, ACPI_PM1_EN\r
+ DCD NVIC_Handler_PM1_STS ; 94h: 21, ACPI_PM1_STS\r
+ DCD NVIC_Handler_MIF8042_OBF ; 98h: 22, MIF8042_OBF\r
+ DCD NVIC_Handler_MIF8042_IBF ; 9Ch: 23, MIF8042_IBF\r
+ DCD NVIC_Handler_MAILBOX ; A0h: 24, Mailbox\r
+ DCD NVIC_Handler_PECI ; A4h: 25, PECI\r
+ DCD NVIC_Handler_TACH0 ; A8h: 26, TACH0\r
+ DCD NVIC_Handler_TACH1 ; ACh: 27, TACH1\r
+ DCD NVIC_Handler_ADC_SNGL ; B0h: 28, ADC_SNGL\r
+ DCD NVIC_Handler_ADC_RPT ; B4h: 29, ADC_RPT\r
+ DCD NVIC_Handler_V2P_INT0 ; B8h: 30, V2P_INT0\r
+ DCD NVIC_Handler_V2P_INT1 ; BCh: 31, V2P_INT1\r
+ DCD NVIC_Handler_PS2_CH0 ; C0h: 32, PS2_0\r
+ DCD NVIC_Handler_PS2_CH1 ; C4h: 33, PS2_1\r
+ DCD NVIC_Handler_PS2_CH2 ; C8h: 34, PS2_2\r
+ DCD NVIC_Handler_PS2_CH3 ; CCh: 35, PS2_3\r
+ DCD NVIC_Handler_SPI0_TX ; D0h: 36, SPI0_TX\r
+ DCD NVIC_Handler_SPI0_RX ; D4h: 37, SPI0_RX\r
+ DCD NVIC_Handler_HIB_TMR ; D8h: 38, HIB_TMR\r
+ DCD NVIC_Handler_KEY_INT ; DCh: 39, KEY_INT\r
+ DCD NVIC_Handler_KEY_WAKE ; E0h: 40, KEY_WAKE\r
+ DCD NVIC_Handler_RPM_STALL ; E4h: 41, RPM_STALL\r
+ DCD NVIC_Handler_RPM_SPIN ; E8h: 42, RPM_SPIN\r
+ DCD NVIC_Handler_VBAT ; ECh: 43, VBAT\r
+ DCD NVIC_Handler_LED0 ; F0h: 44, LED0\r
+ DCD NVIC_Handler_LED1 ; F4h: 45, LED1\r
+ DCD NVIC_Handler_LED2 ; F8h: 46, LED2\r
+ DCD NVIC_Handler_MBC_ERR ; FCh: 47, MBC_ERR\r
+ DCD NVIC_Handler_MBC_BUSY ; 100h: 48, MBC_BUSY\r
+ DCD NVIC_Handler_TMR0 ; 104h: 49, TMR0\r
+ DCD NVIC_Handler_TMR1 ; 108h: 50, TMR1\r
+ DCD NVIC_Handler_TMR2 ; 10Ch: 51, TMR2\r
+ DCD NVIC_Handler_TMR3 ; 110h: 52, TMR3\r
+ DCD NVIC_Handler_TMR4 ; 114h: 53, TMR4\r
+ DCD NVIC_Handler_TMR5 ; 118h: 54, TMR5\r
+ DCD NVIC_Handler_SPI1_TX ; 11Ch: 55, SPI1_TX\r
+ DCD NVIC_Handler_SPI1_RX ; 120h: 56, SPI1_RX\r
+ DCD NVIC_Handler_GIRQ08 ; 124h: 57, GIRQ08\r
+ DCD NVIC_Handler_GIRQ09 ; 128h: 58, GIRQ09\r
+ DCD NVIC_Handler_GIRQ10 ; 12Ch: 59, GIRQ10\r
+ DCD NVIC_Handler_GIRQ11 ; 130h: 60, GIRQ11\r
+ DCD NVIC_Handler_GIRQ12 ; 134h: 61, GIRQ12\r
+ DCD NVIC_Handler_GIRQ13 ; 138h: 62, GIRQ13\r
+ DCD NVIC_Handler_GIRQ14 ; 13Ch: 63, GIRQ14\r
+ DCD NVIC_Handler_GIRQ15 ; 140h: 64, GIRQ15\r
+ DCD NVIC_Handler_GIRQ16 ; 144h: 65, GIRQ16\r
+ DCD NVIC_Handler_GIRQ17 ; 148h: 66, GIRQ17\r
+ DCD NVIC_Handler_GIRQ18 ; 14Ch: 67, GIRQ18\r
+ DCD NVIC_Handler_GIRQ19 ; 150h: 68, GIRQ19\r
+ DCD NVIC_Handler_GIRQ20 ; 154h: 69, GIRQ20\r
+ DCD NVIC_Handler_GIRQ21 ; 158h: 70, GIRQ21\r
+ DCD NVIC_Handler_GIRQ22 ; 15Ch: 71, GIRQ22\r
+ DCD NVIC_Handler_GIRQ23 ; 160h: 72, GIRQ23\r
+ DCD NVIC_Handler_073 ; 164h: 73, unknown\r
+ DCD NVIC_Handler_074 ; 168h: 74, unknown\r
+ DCD NVIC_Handler_075 ; 16Ch: 75, unknown\r
+ DCD NVIC_Handler_076 ; 170h: 76, unknown\r
+ DCD NVIC_Handler_077 ; 174h: 77, unknown\r
+ DCD NVIC_Handler_078 ; 178h: 78, unknown\r
+ DCD NVIC_Handler_079 ; 17Ch: 79, unknown\r
+ DCD NVIC_Handler_080 ; 180h: 80, unknown\r
+ DCD NVIC_Handler_DMA8 ; 184h: 81, DMA CH8\r
+ DCD NVIC_Handler_DMA9 ; 188h: 82, DMA CH9\r
+ DCD NVIC_Handler_DMA10 ; 18Ch: 83, DMA CH10\r
+ DCD NVIC_Handler_DMA11 ; 190h: 84, DMA CH11\r
+ DCD NVIC_Handler_LED3 ; 194h: 85, LED3\r
+ DCD NVIC_Handler_PKE_ERR ; 198h: 86, PKE Error\r
+ DCD NVIC_Handler_PKE_END ; 19Ch: 87, PKE End\r
+ DCD NVIC_Handler_TRNG ; 1A0h: 88, TRandom Num Gen\r
+ DCD NVIC_Handler_AES ; 1A4h: 89, AES \r
+ DCD NVIC_Handler_HASH ; 1A8h: 90, HASH\r
+ \r
+\r
+ AREA ROMTABLE, CODE, READONLY\r
+ THUMB\r
+; ---------- ROM API ----------\r
+; Jump table to ROM API C functions\r
+;\r
+;\r
+; ---------- ROM API End ------\r
+; Reset Handler\r
+\r
+ AREA |.text|, CODE, READONLY\r
+ THUMB\r
+\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+\r
+ CPSID i\r
+ \r
+ ; support code is loaded from ROM loader\r
+ LDR SP, =__initial_sp\r
+ ; configure CPU speed \r
+ LDR R0, =system_set_ec_clock\r
+ BLX R0\r
+\r
+ LDR SP, =__initial_sp\r
+\r
+ ; support FPU\r
+ IF {CPU} = "Cortex-M4.fp"\r
+ LDR R0, =0xE000ED88 ; Enable CP10,CP11\r
+ LDR R1,[R0]\r
+ ORR R1,R1,#(0xF << 20)\r
+ STR R1,[R0]\r
+ ENDIF\r
+\r
+ ; Enter Keil startup code which calls our main\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ MOV R7,#1\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ MOV R7,#2\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ MOV R7,#3\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ MOV R7,#4\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ MOV R7,#5\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ MOV R7,#6\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ MOV R7,#7\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ MOV R7,#8\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ MOV R7,#9\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ ; External MEC1322 NVIC Interrupt Inputs\r
+ EXPORT NVIC_Handler_I2C0 [WEAK]\r
+ EXPORT NVIC_Handler_I2C1 [WEAK]\r
+ EXPORT NVIC_Handler_I2C2 [WEAK]\r
+ EXPORT NVIC_Handler_I2C3 [WEAK]\r
+ EXPORT NVIC_Handler_DMA0 [WEAK]\r
+ EXPORT NVIC_Handler_DMA1 [WEAK]\r
+ EXPORT NVIC_Handler_DMA2 [WEAK]\r
+ EXPORT NVIC_Handler_DMA3 [WEAK]\r
+ EXPORT NVIC_Handler_DMA4 [WEAK]\r
+ EXPORT NVIC_Handler_DMA5 [WEAK]\r
+ EXPORT NVIC_Handler_DMA6 [WEAK]\r
+ EXPORT NVIC_Handler_DMA7 [WEAK]\r
+ EXPORT NVIC_Handler_LPCBERR [WEAK]\r
+ EXPORT NVIC_Handler_UART0 [WEAK]\r
+ EXPORT NVIC_Handler_IMAP0 [WEAK]\r
+ EXPORT NVIC_Handler_EC0_IBF [WEAK]\r
+ EXPORT NVIC_Handler_EC0_OBF [WEAK]\r
+ EXPORT NVIC_Handler_EC1_IBF [WEAK]\r
+ EXPORT NVIC_Handler_EC1_OBF [WEAK]\r
+ EXPORT NVIC_Handler_PM1_CTL [WEAK]\r
+ EXPORT NVIC_Handler_PM1_EN [WEAK]\r
+ EXPORT NVIC_Handler_PM1_STS [WEAK]\r
+ EXPORT NVIC_Handler_MIF8042_OBF [WEAK]\r
+ EXPORT NVIC_Handler_MIF8042_IBF [WEAK]\r
+ EXPORT NVIC_Handler_MAILBOX [WEAK]\r
+ EXPORT NVIC_Handler_PECI [WEAK]\r
+ EXPORT NVIC_Handler_TACH0 [WEAK]\r
+ EXPORT NVIC_Handler_TACH1 [WEAK]\r
+ EXPORT NVIC_Handler_ADC_SNGL [WEAK]\r
+ EXPORT NVIC_Handler_ADC_RPT [WEAK]\r
+ EXPORT NVIC_Handler_V2P_INT0 [WEAK]\r
+ EXPORT NVIC_Handler_V2P_INT1 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_CH0 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_CH1 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_CH2 [WEAK]\r
+ EXPORT NVIC_Handler_PS2_CH3 [WEAK]\r
+ EXPORT NVIC_Handler_SPI0_TX [WEAK]\r
+ EXPORT NVIC_Handler_SPI0_RX [WEAK]\r
+ EXPORT NVIC_Handler_HIB_TMR [WEAK]\r
+ EXPORT NVIC_Handler_KEY_INT [WEAK]\r
+ EXPORT NVIC_Handler_KEY_WAKE [WEAK]\r
+ EXPORT NVIC_Handler_RPM_STALL [WEAK]\r
+ EXPORT NVIC_Handler_RPM_SPIN [WEAK]\r
+ EXPORT NVIC_Handler_VBAT [WEAK]\r
+ EXPORT NVIC_Handler_LED0 [WEAK]\r
+ EXPORT NVIC_Handler_LED1 [WEAK]\r
+ EXPORT NVIC_Handler_LED2 [WEAK]\r
+ EXPORT NVIC_Handler_MBC_ERR [WEAK]\r
+ EXPORT NVIC_Handler_MBC_BUSY [WEAK]\r
+ EXPORT NVIC_Handler_TMR0 [WEAK]\r
+ EXPORT NVIC_Handler_TMR1 [WEAK]\r
+ EXPORT NVIC_Handler_TMR2 [WEAK]\r
+ EXPORT NVIC_Handler_TMR3 [WEAK]\r
+ EXPORT NVIC_Handler_TMR4 [WEAK]\r
+ EXPORT NVIC_Handler_TMR5 [WEAK]\r
+ EXPORT NVIC_Handler_SPI1_TX [WEAK]\r
+ EXPORT NVIC_Handler_SPI1_RX [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ08 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ09 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ10 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ11 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ12 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ13 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ14 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ15 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ16 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ17 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ18 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ19 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ20 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ21 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ22 [WEAK]\r
+ EXPORT NVIC_Handler_GIRQ23 [WEAK]\r
+ EXPORT NVIC_Handler_073 [WEAK]\r
+ EXPORT NVIC_Handler_074 [WEAK]\r
+ EXPORT NVIC_Handler_075 [WEAK]\r
+ EXPORT NVIC_Handler_076 [WEAK]\r
+ EXPORT NVIC_Handler_077 [WEAK]\r
+ EXPORT NVIC_Handler_078 [WEAK]\r
+ EXPORT NVIC_Handler_079 [WEAK]\r
+ EXPORT NVIC_Handler_080 [WEAK]\r
+ EXPORT NVIC_Handler_DMA8 [WEAK]\r
+ EXPORT NVIC_Handler_DMA9 [WEAK]\r
+ EXPORT NVIC_Handler_DMA10 [WEAK]\r
+ EXPORT NVIC_Handler_DMA11 [WEAK]\r
+ EXPORT NVIC_Handler_LED3 [WEAK]\r
+ EXPORT NVIC_Handler_PKE_ERR [WEAK]\r
+ EXPORT NVIC_Handler_PKE_END [WEAK]\r
+ EXPORT NVIC_Handler_TRNG [WEAK]\r
+ EXPORT NVIC_Handler_AES [WEAK]\r
+ EXPORT NVIC_Handler_HASH [WEAK]\r
+\r
+NVIC_Handler_I2C0\r
+NVIC_Handler_I2C1\r
+NVIC_Handler_I2C2\r
+NVIC_Handler_I2C3\r
+NVIC_Handler_DMA0\r
+NVIC_Handler_DMA1\r
+NVIC_Handler_DMA2\r
+NVIC_Handler_DMA3\r
+NVIC_Handler_DMA4\r
+NVIC_Handler_DMA5\r
+NVIC_Handler_DMA6\r
+NVIC_Handler_DMA7\r
+NVIC_Handler_LPCBERR\r
+NVIC_Handler_UART0\r
+NVIC_Handler_IMAP0\r
+NVIC_Handler_EC0_IBF\r
+NVIC_Handler_EC0_OBF\r
+NVIC_Handler_EC1_IBF\r
+NVIC_Handler_EC1_OBF\r
+NVIC_Handler_PM1_CTL\r
+NVIC_Handler_PM1_EN\r
+NVIC_Handler_PM1_STS\r
+NVIC_Handler_MIF8042_OBF\r
+NVIC_Handler_MIF8042_IBF\r
+NVIC_Handler_MAILBOX\r
+NVIC_Handler_PECI\r
+NVIC_Handler_TACH0\r
+NVIC_Handler_TACH1\r
+NVIC_Handler_ADC_SNGL\r
+NVIC_Handler_ADC_RPT\r
+NVIC_Handler_V2P_INT0\r
+NVIC_Handler_V2P_INT1\r
+NVIC_Handler_PS2_CH0\r
+NVIC_Handler_PS2_CH1\r
+NVIC_Handler_PS2_CH2\r
+NVIC_Handler_PS2_CH3\r
+NVIC_Handler_SPI0_TX\r
+NVIC_Handler_SPI0_RX\r
+NVIC_Handler_HIB_TMR\r
+NVIC_Handler_KEY_INT\r
+NVIC_Handler_KEY_WAKE\r
+NVIC_Handler_RPM_STALL\r
+NVIC_Handler_RPM_SPIN\r
+NVIC_Handler_VBAT\r
+NVIC_Handler_LED0\r
+NVIC_Handler_LED1\r
+NVIC_Handler_LED2\r
+NVIC_Handler_MBC_ERR\r
+NVIC_Handler_MBC_BUSY\r
+NVIC_Handler_TMR0\r
+NVIC_Handler_TMR1\r
+NVIC_Handler_TMR2\r
+NVIC_Handler_TMR3\r
+NVIC_Handler_TMR4\r
+NVIC_Handler_TMR5\r
+NVIC_Handler_SPI1_TX\r
+NVIC_Handler_SPI1_RX\r
+NVIC_Handler_GIRQ08\r
+NVIC_Handler_GIRQ09\r
+NVIC_Handler_GIRQ10\r
+NVIC_Handler_GIRQ11\r
+NVIC_Handler_GIRQ12\r
+NVIC_Handler_GIRQ13\r
+NVIC_Handler_GIRQ14\r
+NVIC_Handler_GIRQ15\r
+NVIC_Handler_GIRQ16\r
+NVIC_Handler_GIRQ17\r
+NVIC_Handler_GIRQ18\r
+NVIC_Handler_GIRQ19\r
+NVIC_Handler_GIRQ20\r
+NVIC_Handler_GIRQ21\r
+NVIC_Handler_GIRQ22\r
+NVIC_Handler_GIRQ23\r
+NVIC_Handler_073\r
+NVIC_Handler_074\r
+NVIC_Handler_075\r
+NVIC_Handler_076\r
+NVIC_Handler_077\r
+NVIC_Handler_078\r
+NVIC_Handler_079\r
+NVIC_Handler_080\r
+NVIC_Handler_DMA8\r
+NVIC_Handler_DMA9\r
+NVIC_Handler_DMA10\r
+NVIC_Handler_DMA11\r
+NVIC_Handler_LED3\r
+NVIC_Handler_PKE_ERR\r
+NVIC_Handler_PKE_END\r
+NVIC_Handler_TRNG\r
+NVIC_Handler_AES\r
+NVIC_Handler_HASH\r
+ B .\r
+\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+; User Initial Stack & Heap\r
+\r
+ IF :DEF:__MICROLIB\r
+ \r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+ EXPORT __stack_bottom\r
+\r
+ ELSE\r
+ \r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+ END\r
+\r
+;/** @}\r
+; */\r
--- /dev/null
+/****************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+*/\r
+\r
+/** @defgroup pwm pwm_c_wrapper\r
+ * @{\r
+ */\r
+/** @file pwm_c_wrapper.cpp\r
+ \brief the pwm component C wrapper \r
+ This program is designed to allow the other C programs to be able to use this component\r
+\r
+ There are entry points for all C wrapper API implementation\r
+\r
+<b>Platform:</b> This is ARC-based component \r
+\r
+<b>Toolset:</b> Metaware IDE(8.5.1)\r
+<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
+\r
+/*******************************************************************************\r
+ * SMSC version control information (Perforce):\r
+ *\r
+ * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/system/system.c $\r
+ * REVISION: $Revision: #1 $\r
+ * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
+ * AUTHOR: $Author: akrishnan $\r
+ *\r
+ * Revision history (latest first):\r
+ * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1) \r
+ * #2 2011/03/25 martin_y support FPGA build 058 apps\r
+ * #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200\r
+ ***********************************************************************************\r
+ */\r
+/* Imported Header File */\r
+//#include "common.h"\r
+//#include "build.h"\r
+#include <stdint.h>\r
+\r
+#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120\r
+#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))\r
+#define CPU_CLOCK_DIVIDER 1\r
+\r
+/******************************************************************************/\r
+/** system_set_ec_clock\r
+* Set CPU speed\r
+* @param void\r
+* @return void\r
+*******************************************************************************/\r
+\r
+void system_set_ec_clock(void)\r
+{\r
+\r
+ /* Set ARC CPU Clock Divider to determine the CPU speed */\r
+ /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */\r
+ MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER;\r
+\r
+} /* End system_set_ec_clock() */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project\r
+ * that demonstrates low power tickless functionality, and a more comprehensive\r
+ * test and demo application. The configCREATE_LOW_POWER_DEMO setting, which is\r
+ * defined in FreeRTOSConfig.h, is used to select between the two. The simply\r
+ * blinky low power demo is implemented and described in main_low_power.c. The\r
+ * more comprehensive test and demo application is implemented and described in\r
+ * main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and standard FreeRTOS hook functions.\r
+ *\r
+ * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON\r
+ * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO\r
+ * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!\r
+ *\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Hardware register addresses. */\r
+#define mainVTOR ( * ( uint32_t * ) 0xE000ED08 )\r
+#define mainNVIC_AUX_ACTLR ( * ( uint32_t * ) 0xE000E008 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware as necessary to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1.\r
+ * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0.\r
+ */\r
+#if( configCREATE_LOW_POWER_DEMO == 1 )\r
+\r
+ extern void main_low_power( void );\r
+\r
+#else\r
+\r
+ extern void main_full( void );\r
+\r
+ /* Some of the tests and examples executed as part of the full demo make use\r
+ of the tick hook to call API functions from an interrupt context. */\r
+ extern void vFullDemoTickHook( void );\r
+\r
+#endif /* #if configCREATE_LOW_POWER_DEMO == 1 */\r
+\r
+/* Prototypes for the standard FreeRTOS callback/hook functions implemented\r
+within this file. */\r
+void vApplicationMallocFailedHook( void );\r
+void vApplicationIdleHook( void );\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
+void vApplicationTickHook( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The variable that is incremented to represent each LED toggle. On the\r
+clicker hardware the LED state is set to the value of the least significant bit\r
+of this variable. On other hardware, where an LED is not used, the LED just\r
+keeps a count of the number of times the LED would otherwise have been toggled.\r
+See the comments in main_low_power.c and main_full.c for information on the\r
+expected LED toggle rate). */\r
+volatile uint32_t ulLED = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Configure the hardware ready to run the demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The configCREATE_LOW_POWER_DEMO setting is described at the top\r
+ of this file. */\r
+ #if( configCREATE_LOW_POWER_DEMO == 1 )\r
+ {\r
+ main_low_power();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+extern void system_set_ec_clock( void );\r
+extern unsigned long __Vectors[];\r
+ \r
+ /* Disable M4 write buffer: fix MEC1322 hardware bug. */\r
+ mainNVIC_AUX_ACTLR |= 0x07;\r
+\r
+ system_set_ec_clock();\r
+ \r
+ /* Assuming downloading code via the debugger - so ensure the hardware\r
+ is using the vector table downloaded with the application. */\r
+ mainVTOR = ( uint32_t ) __Vectors;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* Called if a call to pvPortMalloc() fails because there is insufficient\r
+ free memory available in the FreeRTOS heap. pvPortMalloc() is called\r
+ internally by FreeRTOS API functions that create tasks, queues, software\r
+ timers, and semaphores. The size of the FreeRTOS heap is set by the\r
+ configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+\r
+ /* Force an assert. */\r
+ configASSERT( ( volatile void * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+volatile size_t xFreeHeapSpace;\r
+\r
+ /* This is just a trivial example of an idle hook. It is called on each\r
+ cycle of the idle task. It must *NOT* attempt to block. In this case the\r
+ idle task just queries the amount of FreeRTOS heap that remains. See the\r
+ memory management section on the http://www.FreeRTOS.org web site for memory\r
+ management options. If there is a lot of heap memory free then the\r
+ configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up\r
+ RAM. */\r
+ xFreeHeapSpace = xPortGetFreeHeapSize();\r
+\r
+ /* Remove compiler warning about xFreeHeapSpace being set but never used. */\r
+ ( void ) xFreeHeapSpace;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* The full demo includes tests that run from the tick hook. */\r
+ #if( configCREATE_LOW_POWER_DEMO == 0 )\r
+ {\r
+ /* Some of the tests and demo tasks executed by the full demo include\r
+ interaction from an interrupt - for which the tick interrupt is used\r
+ via the tick hook function. */\r
+ vFullDemoTickHook();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
+implementation of vApplicationGetIdleTaskMemory() to provide the memory that is\r
+used by the Idle task. */\r
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )\r
+{\r
+/* If the buffers to be provided to the Idle task are declared inside this\r
+function then they must be declared static - otherwise they will be allocated on\r
+the stack and so not exists after this function exits. */\r
+static StaticTask_t xIdleTaskTCB;\r
+static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle task's\r
+ state will be stored. */\r
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Idle task's stack. */\r
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
+ Note that, as the array is necessarily of type StackType_t,\r
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the\r
+application must provide an implementation of vApplicationGetTimerTaskMemory()\r
+to provide the memory that is used by the Timer service task. */\r
+void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )\r
+{\r
+/* If the buffers to be provided to the Timer task are declared inside this\r
+function then they must be declared static - otherwise they will be allocated on\r
+the stack and so not exists after this function exits. */\r
+static StaticTask_t xTimerTaskTCB;\r
+static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
+ task's state will be stored. */\r
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Timer task's stack. */\r
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
+ Note that, as the array is necessarily of type StackType_t,\r
+ configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*\r
+ * This file initialises three timers as follows:\r
+ *\r
+ * Basic timer channels 0 and 1 provide the interrupts that are used with the\r
+ * IntQ standard demo tasks, which test interrupt nesting and using queues from\r
+ * interrupts. The interrupts use slightly different frequencies so will\r
+ * occasionally nest.\r
+ *\r
+ * Basic timer channel 2 provides a much higher frequency timer that tests the\r
+ * nesting of interrupts that don't use the FreeRTOS API.\r
+ *\r
+ * All the timers can nest with the tick interrupt - creating a maximum\r
+ * interrupt nesting depth of 4 (which is shown as a max nest count of 3 as the\r
+ * tick interrupt does not increment the nesting count variable).\r
+ *\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "IntQueueTimer.h"\r
+#include "IntQueue.h"\r
+\r
+/* Library includes. */\r
+#include "common_lib.h"\r
+#include "peripheral_library/interrupt/interrupt.h"\r
+#include "peripheral_library/basic_timer/btimer.h"\r
+\r
+/* The frequencies at which the first two timers expire are slightly offset to\r
+ensure they don't remain synchronised. The frequency of the highest priority\r
+interrupt is 20 times faster so really hammers the interrupt entry and exit\r
+code. */\r
+#define tmrTIMER_0_FREQUENCY ( 2000UL )\r
+#define tmrTIMER_1_FREQUENCY ( 2003UL )\r
+#define tmrTIMER_2_FREQUENCY ( 20000UL )\r
+\r
+/* The basic timer channels used for generating the three interrupts. */\r
+#define tmrTIMER_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */\r
+#define tmrTIMER_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */\r
+#define tmrTIMER_CHANNEL_2 2 /* At tmrTIMER_2_FREQUENCY */\r
+\r
+/* The high frequency interrupt is given a priority above the maximum at which\r
+interrupt safe FreeRTOS calls can be made. The priority of the lower frequency\r
+timers must still be above the tick interrupt priority. */\r
+#define tmrLOWER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1 )\r
+#define tmrMEDIUM_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 )\r
+#define tmrHIGHER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )\r
+\r
+/* Hardware register locations. */\r
+#define tmrGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 )\r
+#define tmrMMCR_EC_INTERRUPT_CONTROL ( * ( volatile uint8_t * ) 0x4000FC18 )\r
+\r
+#define tmrRECORD_NESTING_DEPTH() \\r
+ ulNestingDepth++; \\r
+ if( ulNestingDepth > ulMaxRecordedNestingDepth ) \\r
+ { \\r
+ ulMaxRecordedNestingDepth = ulNestingDepth; \\r
+ }\r
+\r
+/* Used to count the nesting depth, and record the maximum nesting depth. */\r
+volatile uint32_t ulNestingDepth = 0, ulMaxRecordedNestingDepth = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vInitialiseTimerForIntQueueTest( void )\r
+{\r
+const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY;\r
+const uint32_t ulTimer1Count = configCPU_CLOCK_HZ / tmrTIMER_1_FREQUENCY;\r
+const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;\r
+\r
+ tmrGIRQ23_ENABLE_SET = 0x03;\r
+ tmrMMCR_EC_INTERRUPT_CONTROL = 1; \r
+ \r
+ /* Initialise the three timers as described at the top of this file, and \r
+ enable their interrupts in the NVIC. */\r
+ btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );\r
+ btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 ); \r
+ enable_timer0_irq();\r
+ NVIC_SetPriority( TIMER0_IRQn, tmrLOWER_PRIORITY ); //0xc0 into 0xe000e431\r
+ NVIC_ClearPendingIRQ( TIMER0_IRQn );\r
+ NVIC_EnableIRQ( TIMER0_IRQn );\r
+ btimer_start( tmrTIMER_CHANNEL_0 );\r
+\r
+ btimer_init( tmrTIMER_CHANNEL_1, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer1Count, ulTimer1Count );\r
+ btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_1 );\r
+ enable_timer1_irq();\r
+ NVIC_SetPriority( TIMER1_IRQn, tmrMEDIUM_PRIORITY ); //0xa0 into 0xe000e432\r
+ NVIC_ClearPendingIRQ( TIMER1_IRQn );\r
+ NVIC_EnableIRQ( TIMER1_IRQn );\r
+ btimer_start( tmrTIMER_CHANNEL_1 );\r
+\r
+ btimer_init( tmrTIMER_CHANNEL_2, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer2Count, ulTimer2Count );\r
+ btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_2 );\r
+ enable_timer2_irq();\r
+ NVIC_SetPriority( TIMER2_IRQn, tmrHIGHER_PRIORITY );\r
+ NVIC_ClearPendingIRQ( TIMER2_IRQn );\r
+ NVIC_EnableIRQ( TIMER2_IRQn );\r
+ btimer_start( tmrTIMER_CHANNEL_2 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The TMR0 interrupt is used for different purposes by the low power and full\r
+demos respectively. */\r
+#if( configCREATE_LOW_POWER_DEMO == 0 )\r
+\r
+ void NVIC_Handler_TMR0( void )\r
+ {\r
+ tmrRECORD_NESTING_DEPTH();\r
+\r
+ /* Call the IntQ test function for this channel. */\r
+ portYIELD_FROM_ISR( xFirstTimerHandler() );\r
+\r
+ ulNestingDepth--;\r
+ }\r
+\r
+#endif /* configCREATE_LOW_POWER_DEMO */\r
+/*-----------------------------------------------------------*/\r
+\r
+void NVIC_Handler_TMR1( void )\r
+{\r
+ tmrRECORD_NESTING_DEPTH();\r
+\r
+ /* Just testing the xPortIsInsideInterrupt() functionality. */\r
+ configASSERT( xPortIsInsideInterrupt() == pdTRUE );\r
+\r
+ /* Call the IntQ test function for this channel. */\r
+ portYIELD_FROM_ISR( xSecondTimerHandler() );\r
+\r
+ ulNestingDepth--;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void NVIC_Handler_TMR2( void )\r
+{\r
+ tmrRECORD_NESTING_DEPTH();\r
+ ulNestingDepth--;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+#ifndef INT_QUEUE_TIMER_H\r
+#define INT_QUEUE_TIMER_H\r
+\r
+void vInitialiseTimerForIntQueueTest( void );\r
+BaseType_t xTimer0Handler( void );\r
+BaseType_t xTimer1Handler( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project that demonstrates the tickless low power features of FreeRTOS, and a\r
+ * more comprehensive test and demo application. The configCREATE_LOW_POWER_DEMO\r
+ * setting in FreeRTOSConifg.h is used to select between the two. See the notes\r
+ * on using conifgCREATE_LOW_POWER_DEMO in main.c. This file implements the\r
+ * comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ *\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and software timers, then\r
+ * starts the scheduler. The web documentation provides more details of the\r
+ * standard demo application tasks, which provide no particular functionality,\r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" task - The check task period is initially set to three seconds. The\r
+ * task checks that all the standard demo tasks, and the register check tasks,\r
+ * are not only still executing, but are executing without reporting any errors.\r
+ * If the check task discovers that a task has either stalled, or reported an\r
+ * error, then it changes its own execution period from the initial three\r
+ * seconds, to just 200ms. The check task also toggles an LED each time it is\r
+ * called. This provides a visual indication of the system status: If the LED\r
+ * toggles every three seconds, then no issues have been discovered. If the LED\r
+ * toggles every 200ms, then an issue has been discovered with at least one\r
+ * task.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "flop.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "death.h"\r
+#include "TimerDemo.h"\r
+#include "IntQueue.h"\r
+#include "EventGroupsDemo.h"\r
+#include "TaskNotify.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period of the check task, in ms, provided no errors have been reported by\r
+any of the standard demo tasks. ms are converted to the equivalent in ticks\r
+using the pdMS_TO_TICKS() macro constant. */\r
+#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL )\r
+\r
+/* The period of the check task, in ms, if an error has been reported in one of\r
+the standard demo tasks. ms are converted to the equivalent in ticks using the\r
+pdMS_TO_TICKS() macro. */\r
+#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL )\r
+\r
+/* Parameters that are passed into the register check tasks solely for the\r
+purpose of ensuring parameters are passed into tasks correctly. */\r
+#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )\r
+#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )\r
+\r
+/* The base period used by the timer test tasks. */\r
+#define mainTIMER_TEST_PERIOD ( 50 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main() to run the full demo (as opposed to the blinky demo) when\r
+ * configCREATE_LOW_POWER_DEMO is set to 0.\r
+ */\r
+void main_full( void );\r
+\r
+/*\r
+ * The check task, as described at the top of this file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Some of the tests and demo tasks executed by the full demo include\r
+ * interaction from an interrupt - for which the tick interrupt is used via the\r
+ * tick hook function.\r
+ */\r
+void vFullDemoTickHook( void );\r
+\r
+/*\r
+ * Register check tasks, and the tasks used to write over and check the contents\r
+ * of the FPU registers, as described at the top of this file. The nature of\r
+ * these files necessitates that they are written in an assembly file, but the\r
+ * entry points are kept in the C file for the convenience of checking the task\r
+ * parameter.\r
+ */\r
+static void prvRegTestTaskEntry1( void *pvParameters );\r
+extern void vRegTest1Implementation( void );\r
+static void prvRegTestTaskEntry2( void *pvParameters );\r
+extern void vRegTest2Implementation( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check task. If the variables keep incrementing,\r
+then the register check tasks have not discovered any errors. If a variable\r
+stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/* The variable that is incremented to represent each LED toggle. On the\r
+clicker hardware the LED state is set to the value of the least significant bit\r
+of this variable. On other hardware, where an LED is not used, the LED just\r
+keeps a count of the number of times the LED would otherwise have been toggled.\r
+See the comments at the top of this file for information on the expected LED\r
+toggle rate. */\r
+extern volatile uint32_t ulLED;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+ /* Start all the other standard demo/test tasks. They have no particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartDynamicPriorityTasks();\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );\r
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );\r
+ vStartEventGroupTasks();\r
+ vStartTaskNotifyTask();\r
+ vStartInterruptQueueTasks();\r
+\r
+ /* Create the register check tasks, as described at the top of this file */\r
+ xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the task that performs the 'check' functionality, as described at\r
+ the top of this file. */\r
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* The set of tasks created by the following function call have to be\r
+ created last as they keep account of the number of tasks they expect to see\r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was insufficient FreeRTOS heap memory available for the Idle and/or\r
+ timer tasks to be created. See the memory management section on the\r
+ FreeRTOS web site for more details on the FreeRTOS heap\r
+ http://www.freertos.org/a00111.html. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;\r
+TickType_t xLastExecutionTime;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Just to stop compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
+ works correctly. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ /* Cycle for ever, delaying then checking all the other tasks are still\r
+ operating without error. The onboard LED is toggled on each iteration.\r
+ If an error is detected then the delay period is decreased from\r
+ mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the\r
+ effect of increasing the rate at which the onboard LED toggles, and in so\r
+ doing gives visual feedback of the system status. */\r
+ for( ;; )\r
+ {\r
+ /* Delay until it is time to execute again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+ if( xAreIntQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 0UL;\r
+ }\r
+\r
+ if( xAreMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 1UL;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 2UL;\r
+ }\r
+\r
+ if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 4UL;\r
+ }\r
+\r
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 5UL;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 7UL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 8UL;\r
+ }\r
+\r
+ if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 9UL;\r
+ }\r
+\r
+ if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = 1UL << 10UL;\r
+ }\r
+\r
+ if( xAreEventGroupTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 12UL;\r
+ }\r
+\r
+ if( xAreTaskNotificationTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound = 1UL << 14UL;\r
+ }\r
+\r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound = 1UL << 15UL;\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound = 1UL << 16UL;\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ configTOGGLE_LED();\r
+\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ /* An error has been detected in one of the tasks - flash the LED\r
+ at a higher frequency to give visible feedback that something has\r
+ gone wrong (it might just be that the loop back connector required\r
+ by the comtest tasks has not been fitted). */\r
+ xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
+ }\r
+\r
+ configASSERT( ulErrorFound == pdFALSE );\r
+\r
+ /* Just testing the xPortIsInsideInterrupt() functionality. */\r
+ configASSERT( xPortIsInsideInterrupt() == pdFALSE );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTestTaskEntry1( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )\r
+ {\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest1Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check task will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRegTestTaskEntry2( void *pvParameters )\r
+{\r
+ /* Although the regtest task is written in assembler, its entry point is\r
+ written in C for convenience of checking the task parameter is being passed\r
+ in correctly. */\r
+ if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )\r
+ {\r
+ /* Start the part of the test that is written in assembler. */\r
+ vRegTest2Implementation();\r
+ }\r
+\r
+ /* The following line will only execute if the task parameter is found to\r
+ be incorrect. The check task will detect that the regtest loop counter is\r
+ not being incremented and flag an error. */\r
+ vTaskDelete( NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vFullDemoTickHook( void )\r
+{\r
+ /* Some of the tests and demo tasks executed by the full demo include\r
+ interaction from an interrupt - for which the tick interrupt is used via\r
+ the tick hook function. */\r
+\r
+ /* The full demo includes a software timer demo/test that requires\r
+ prodding periodically from the tick interrupt. */\r
+ vTimerPeriodicISRTests();\r
+\r
+ /* Call the periodic event group from ISR demo. */\r
+ vPeriodicEventGroupsProcessing();\r
+\r
+ /* Call the code that 'gives' a task notification from an ISR. */\r
+ xNotifyTaskFromISR();\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <limits.h>\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Library includes. */\r
+#include "common_lib.h"\r
+\r
+/* This file contains functions that will override the default implementations\r
+in the RTOS port layer. Therefore only build this file if the low power demo\r
+is being built. */\r
+#if( configCREATE_LOW_POWER_DEMO == 1 )\r
+\r
+/* ID of the hibernation timer used to generate the tick. */\r
+#define mainTICK_HTIMER_ID 0\r
+\r
+/* Written to the hibernation timer control register to configure the timer for\r
+its higher resolution. */\r
+#define mainHTIMER_HIGH_RESOLUTION 0\r
+\r
+/* The frequency of the hibernation timer when it is running at its higher\r
+resolution and low resolution respectively. */\r
+#define mainHIGHER_RESOLUTION_TIMER_HZ ( 32787UL ) /* (1000000us / 30.5us) as each LSB is 30.5us. */\r
+#define mainLOW_RESOLUTION_TIMER_HZ ( 8UL ) /* ( 1000ms / 125ms ) as each LSB is 0.125s. */\r
+\r
+/* When lpINCLUDE_TEST_TIMER is set to 1 a basic timer is used to generate\r
+interrupts at a low frequency. The purpose being to bring the CPU out of its\r
+sleep mode by an interrupt other than the tick interrupt, and therefore\r
+allowing an additional paths through the code to be tested. */\r
+#define lpINCLUDE_TEST_TIMER 0\r
+\r
+/* Some registers are accessed directly as the library is not compatible with\r
+all the compilers used. */\r
+#define lpHTIMER_PRELOAD_REGISTER ( * ( volatile uint16_t * ) 0x40009800 )\r
+#define lpHTIMER_CONTROL_REGISTER ( * ( volatile uint16_t * ) 0x40009804 )\r
+#define lpHTIMER_COUNT_REGISTER ( * ( volatile uint16_t * ) 0x40009808 )\r
+#define lpEC_GIRQ17_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C0B8 )\r
+#define lpHTIMER_INTERRUPT_CONTROL_BIT ( 1UL << 20UL )\r
+\r
+/*\r
+ * The low power demo does not use the SysTick, so override the\r
+ * vPortSetupTickInterrupt() function with an implementation that configures\r
+ * the low power clock. NOTE: This function name must not be changed as it\r
+ * is called from the RTOS portable layer.\r
+ */\r
+void vPortSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * To fully test the low power tick processing it is necessary to sometimes\r
+ * bring the MCU out of its sleep state by a method other than the tick\r
+ * interrupt. Interrupts generated from a basic timer are used for this\r
+ * purpose.\r
+ */\r
+#if( lpINCLUDE_TEST_TIMER == 1 )\r
+ static void prvSetupBasicTimer( void );\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The reload value to use in the timer to generate the tick interrupt -\r
+assumes the timer is running at its higher resolution. */\r
+static const uint32_t ulHighResolutionReloadValue = ( mainHIGHER_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ );\r
+\r
+/* Calculate how many clock increments make up a single tick period. */\r
+static const uint32_t ulReloadValueForOneHighResolutionTick = ( mainHIGHER_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ );\r
+//static const uint32_t usReloadValueForOneLowResolutionTick = ( mainLOW_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ );\r
+\r
+/* Calculate the maximum number of ticks that can be suppressed when using the\r
+high resolution clock and low resolution clock respectively. */\r
+static uint32_t ulMaximumPossibleSuppressedHighResolutionTicks = 0;\r
+//static const uint16_t usMaximumPossibleSuppressedLowResolutionTicks = USHRT_MAX / usReloadValueForOneLowResolutionTick;\r
+\r
+/* As the clock is only 2KHz, it is likely a value of 1 will be too much, so\r
+use zero - but leave the value here to assist porting to different clock\r
+speeds. */\r
+static const uint32_t ulStoppedTimerCompensation = 0UL;\r
+\r
+/* Flag set from the tick interrupt to allow the sleep processing to know if\r
+sleep mode was exited because of an timer interrupt or a different interrupt. */\r
+static volatile uint32_t ulTickFlag = pdFALSE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void NVIC_Handler_HIB_TMR( void )\r
+{\r
+ lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue;\r
+\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* A context switch is required. Context switching is performed in\r
+ the PendSV interrupt. Pend the PendSV interrupt. */\r
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+ }\r
+\r
+ /* The CPU woke because of a tick. */\r
+ ulTickFlag = pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( lpINCLUDE_TEST_TIMER == 1 )\r
+\r
+ #define GIRQ23_ENABLE_SET ( * ( uint32_t * ) 0x4000C130 )\r
+\r
+ static void prvSetupBasicTimer( void )\r
+ {\r
+ const uint8_t ucTimerChannel = 0;\r
+ const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / 10;\r
+\r
+ GIRQ23_ENABLE_SET = 0x03;\r
+ *(unsigned int*)0x4000FC18 = 1;\r
+\r
+ /* To fully test the low power tick processing it is necessary to sometimes\r
+ bring the MCU out of its sleep state by a method other than the tick\r
+ interrupt. Interrupts generated from a basic timer are used for this\r
+ purpose. */\r
+ btimer_init( ucTimerChannel, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );\r
+ btimer_interrupt_status_get_clr( ucTimerChannel );\r
+ enable_timer0_irq();\r
+ NVIC_SetPriority( TIMER0_IRQn, ucTimerChannel );\r
+ NVIC_ClearPendingIRQ( TIMER0_IRQn );\r
+ NVIC_EnableIRQ( TIMER0_IRQn );\r
+ btimer_start( ucTimerChannel );\r
+ }\r
+\r
+#endif /* lpINCLUDE_TEST_TIMER */\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSetupTimerInterrupt( void )\r
+{\r
+ ulMaximumPossibleSuppressedHighResolutionTicks = ( ( uint32_t ) USHRT_MAX ) / ulReloadValueForOneHighResolutionTick;\r
+\r
+ /* Set up the hibernation timer to start at the value required by the\r
+ tick interrupt. Equivalent to the following libarary call. The library\r
+ is not used as it is not compatible with all the compilers used:\r
+ htimer_enable( mainTICK_HTIMER_ID, ulHighResolutionReloadValue, mainHTIMER_HIGH_RESOLUTION ); */\r
+ lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue;\r
+ lpHTIMER_CONTROL_REGISTER = mainHTIMER_HIGH_RESOLUTION;\r
+\r
+ /* Enable the HTIMER interrupt. Equivalent to enable_htimer0_irq(); */\r
+ lpEC_GIRQ17_ENABLE_SET |= lpHTIMER_INTERRUPT_CONTROL_BIT;\r
+\r
+ /* The hibernation timer is not an auto-reload timer, so gets reset\r
+ from within the ISR itself. For that reason it's interrupt is set\r
+ to the highest possible priority to ensure clock slippage is minimised. */\r
+ NVIC_SetPriority( HTIMER_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );\r
+ NVIC_ClearPendingIRQ( HTIMER_IRQn );\r
+ NVIC_EnableIRQ( HTIMER_IRQn );\r
+\r
+ /* A basic timer is also started, purely for test purposes. Its only\r
+ purpose is to bring the CPU out of its sleep mode by an interrupt other\r
+ than the tick interrupt in order to get more code test coverage. */\r
+ #if( lpINCLUDE_TEST_TIMER == 1 )\r
+ {\r
+ prvSetupBasicTimer();\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Override the default definition of vPortSuppressTicksAndSleep() that is\r
+weakly defined in the FreeRTOS Cortex-M port layer with a version that manages\r
+the hibernation timer, as the tick is generated from the low power hibernation\r
+timer and not the SysTick as would normally be the case on a Cortex-M. */\r
+void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
+{\r
+uint32_t ulCompleteTickPeriods, ulReloadValue, ulCompletedTimerDecrements, ulCountAfterSleep, ulCountBeforeSleep;\r
+eSleepModeStatus eSleepAction;\r
+TickType_t xModifiableIdleTime;\r
+\r
+ /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */\r
+\r
+ /* Make sure the hibernation timer reload value does not overflow the\r
+ counter. */\r
+ if( xExpectedIdleTime > ( TickType_t ) ulMaximumPossibleSuppressedHighResolutionTicks )\r
+ {\r
+ xExpectedIdleTime = ( TickType_t ) ulMaximumPossibleSuppressedHighResolutionTicks;\r
+ }\r
+\r
+ /* Stop the timer momentarily. The time the timer is stopped for is\r
+ accounted for as best it can be, but using the tickless mode will\r
+ inevitably result in some tiny drift of the time maintained by the kernel\r
+ with respect to calendar time. Take the count value first as clearing\r
+ the preload value also seems to clear the count. */\r
+ ulCountBeforeSleep = ( uint32_t ) lpHTIMER_COUNT_REGISTER;\r
+ lpHTIMER_PRELOAD_REGISTER = 0;\r
+\r
+ /* Calculate the reload value required to wait xExpectedIdleTime tick\r
+ periods. -1 is used as the current time slice will already be part way\r
+ through, the part value coming from the current timer count value. */\r
+ ulReloadValue = ulCountBeforeSleep + ( ulReloadValueForOneHighResolutionTick * ( xExpectedIdleTime - 1UL ) );\r
+\r
+ if( ulReloadValue > ulStoppedTimerCompensation )\r
+ {\r
+ /* Compensate for the fact that the timer is going to be stopped\r
+ momentarily. */\r
+ ulReloadValue -= ulStoppedTimerCompensation;\r
+ }\r
+\r
+ /* Enter a critical section but don't use the taskENTER_CRITICAL() method as\r
+ that will mask interrupts that should exit sleep mode. */\r
+ __asm volatile( "cpsid i" );\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "isb" );\r
+\r
+ /* The tick flag is set to false before sleeping. If it is true when sleep\r
+ mode is exited then sleep mode was probably exited because the tick was\r
+ suppressed for the entire xExpectedIdleTime period. */\r
+ ulTickFlag = pdFALSE;\r
+\r
+ /* If a context switch is pending then abandon the low power entry as\r
+ the context switch might have been pended by an external interrupt that\r
+ requires processing. */\r
+ eSleepAction = eTaskConfirmSleepModeStatus();\r
+ if( eSleepAction == eAbortSleep )\r
+ {\r
+ /* Resetart the timer from whatever remains in the counter register,\r
+ but 0 is not a valid value. */\r
+ ulReloadValue = ulCountBeforeSleep - ulStoppedTimerCompensation;\r
+\r
+ if( ulReloadValue == 0 )\r
+ {\r
+ ulReloadValue = ulReloadValueForOneHighResolutionTick;\r
+ ulCompleteTickPeriods = 1UL;\r
+ }\r
+ else\r
+ {\r
+ ulCompleteTickPeriods = 0UL;\r
+ }\r
+\r
+ lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue;\r
+\r
+ /* Re-enable interrupts - see comments above the cpsid instruction()\r
+ above. */\r
+ __asm volatile( "cpsie i" );\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "isb" );\r
+ }\r
+ else\r
+ {\r
+ /* Write the calculated reload value, which will also start the\r
+ timer. */\r
+ lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue;\r
+\r
+ /* Allow the application to define some pre-sleep processing. */\r
+ xModifiableIdleTime = xExpectedIdleTime;\r
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
+\r
+ /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()\r
+ means the application defined code has already executed the sleep\r
+ instructions. */\r
+ if( xModifiableIdleTime > 0 )\r
+ {\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "wfi" );\r
+ __asm volatile( "isb" );\r
+ }\r
+\r
+ /* Allow the application to define some post sleep processing. */\r
+ configPOST_SLEEP_PROCESSING( xModifiableIdleTime );\r
+\r
+ /* Stop the hibernation timer. Again, the time the tiemr is stopped\r
+ for is accounted for as best it can be, but using the tickless mode\r
+ will inevitably result in some tiny drift of the time maintained by the\r
+ kernel with respect to calendar time. Take the count value first as\r
+ setting the preload to zero also seems to clear the count. */\r
+ ulCountAfterSleep = lpHTIMER_COUNT_REGISTER;\r
+ lpHTIMER_PRELOAD_REGISTER = 0;\r
+\r
+ /* Re-enable interrupts - see comments above the cpsid instruction()\r
+ above. */\r
+ __asm volatile( "cpsie i" );\r
+ __asm volatile( "dsb" );\r
+ __asm volatile( "isb" );\r
+\r
+ if( ulTickFlag != pdFALSE )\r
+ {\r
+ /* The tick interrupt has already executed, although because this\r
+ function is called with the scheduler suspended the actual tick\r
+ processing will not occur until after this function has exited.\r
+ The timer has already been reloaded to count in ticks, and can just\r
+ continue counting down from its current value. */\r
+ ulReloadValue = ulCountAfterSleep;\r
+\r
+ /* Sanity check that the timer's reload value has indeed been\r
+ reset. */\r
+ configASSERT( ( uint32_t ) lpHTIMER_PRELOAD_REGISTER == ulReloadValueForOneHighResolutionTick );\r
+\r
+ /* The tick interrupt handler will already have pended the tick\r
+ processing in the kernel. As the pending tick will be processed as\r
+ soon as this function exits, the tick value maintained by the tick\r
+ is stepped forward by one less than the time spent sleeping. The\r
+ actual stepping of the tick appears later in this function. */\r
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
+ }\r
+ else\r
+ {\r
+ /* Something other than the tick interrupt ended the sleep. How\r
+ many complete tick periods passed while the processor was\r
+ sleeping? */\r
+ ulCompletedTimerDecrements = ulReloadValue - ulCountAfterSleep;\r
+\r
+ /* Undo the adjustment that was made to the reload value to account\r
+ for the fact that a time slice was part way through when this\r
+ function was called before working out how many complete tick\r
+ periods this represents. (could have used [ulExpectedIdleTime *\r
+ ulReloadValueForOneHighResolutionTick] instead of ulReloadValue on\r
+ the previous line, but this way avoids the multiplication). */\r
+ ulCompletedTimerDecrements += ( ulReloadValueForOneHighResolutionTick - ulCountBeforeSleep );\r
+ ulCompleteTickPeriods = ulCompletedTimerDecrements / ulReloadValueForOneHighResolutionTick;\r
+\r
+ /* The reload value is set to whatever fraction of a single tick\r
+ period remains. */\r
+ ulReloadValue = ( ( ulCompleteTickPeriods + 1UL ) * ulReloadValueForOneHighResolutionTick ) - ulCompletedTimerDecrements;\r
+ }\r
+\r
+ /* Cannot use a reload value of 0 - it will not start the timer. */\r
+ if( ulReloadValue == 0 )\r
+ {\r
+ /* There is no fraction remaining. */\r
+ ulReloadValue = ulReloadValueForOneHighResolutionTick;\r
+ ulCompleteTickPeriods++;\r
+ }\r
+\r
+ /* Restart the timer so it runs down from the reload value. The reload\r
+ value will get set to the value required to generate exactly one tick\r
+ period the next time the tick interrupt executes. */\r
+ lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue;\r
+ }\r
+\r
+ /* Wind the tick forward by the number of tick periods that the CPU\r
+ remained in a low power state. */\r
+ vTaskStepTick( ulCompleteTickPeriods );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void NVIC_Handler_TMR0( void )\r
+{\r
+ /* This timer is used for test purposes. Its only function is to\r
+ generate interrupts while the MCU is sleeping, so the MCU is sometimes\r
+ brought out of sleep by a means other than the tick interrupt. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+#endif /* configCREATE_LOW_POWER_DEMO */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky demo\r
+ * that demonstrates tickless low power operation, and a more comprehensive\r
+ * test and demo application. The configCREATE_LOW_POWER_DEMO setting in\r
+ * FreeRTOSConfig.h is used to select between the two. See the notes on using\r
+ * configCREATE_LOW_POWER_DEMO in main.c. This file implements the low power\r
+ * version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * low power demo. Generic functions, such FreeRTOS hook functions, and\r
+ * functions required to configure the hardware are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_low_power() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. It sends the value 100 to the queue every second.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() blocks on the queue, blipping (quickly\r
+ * turn on then off again) the LED each time it received the value 100 from the\r
+ * queue send task. The queue send task writes to the queue every second, so\r
+ * the LED will blip once a second.\r
+ *\r
+ * The RTOS tick is turned off when the queue send task and queue receive task\r
+ * are both in the Blocked state.\r
+ *\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_PERIOD_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 1000 )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Called by main when configCREATE_LOW_POWER_DEMO is set to 1 in\r
+ * main.c.\r
+ */\r
+void main_low_power( void );\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static QueueHandle_t xQueue = NULL;\r
+\r
+/* The variable that is incremented to represent each LED toggle. On the\r
+clicker hardware the LED state is set to the value of the least significant bit\r
+of this variable. On other hardware, where an LED is not used, the LED just\r
+keeps a count of the number of times the LED would otherwise have been toggled.\r
+See the comments at the top of this file for information on the expected LED\r
+toggle rate. */\r
+extern volatile uint32_t ulLED;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_low_power( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ NULL, /* The parameter passed to the task - not used in this case. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was insufficient FreeRTOS heap memory available for the Idle and/or\r
+ timer tasks to be created. See the memory management section on the\r
+ FreeRTOS web site for more details on the FreeRTOS heap\r
+ http://www.freertos.org/a00111.html. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+TickType_t xNextWakeTime;\r
+const uint32_t ulValueToSend = 100UL;\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+uint32_t ulReceivedValue;\r
+const uint32_t ulExpectedValue = 100UL;\r
+const TickType_t xShortDelay = pdMS_TO_TICKS( 10 );\r
+\r
+ /* Remove compiler warning about unused parameter. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == ulExpectedValue )\r
+ {\r
+ /* Blip the LED briefly to show the demo is running, but without\r
+ leaving the LED on too long as energy is being conserved. */\r
+ configTOGGLE_LED();\r
+ vTaskDelay( xShortDelay );\r
+ configTOGGLE_LED();\r
+\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ **********************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+ **********************************************************************************\r
+ * ARM_REG.h\r
+ * This is the header to define Cortex-M3 system control & status registers\r
+ **********************************************************************************\r
+ * SMSC version control information (Perforce):\r
+ *\r
+ * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/ARM_REG.h $\r
+ * REVISION: $Revision: #1 $\r
+ * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
+ * AUTHOR: $Author: akrishnan $\r
+ *\r
+ * Revision history (latest first):\r
+ * #xx\r
+ ***********************************************************************************\r
+ */\r
+\r
+/******************************************************************************/\r
+/** @defgroup ARM_REG ARM_REG\r
+ * @{\r
+ */\r
+\r
+/** @file ARM_REG.h\r
+* \brief ARM Cortex-M3 registers header file\r
+* \author KBCEC Team\r
+* \r
+* This file contains ARM Cortex-M3 system control & status registers.\r
+******************************************************************************/ \r
+#ifndef ARM_REG_H_\r
+#define ARM_REG_H_\r
+\r
+#define REG8(x) (*((volatile unsigned char *)(x)))\r
+#define REG16(x) (*((volatile unsigned short *)(x)))\r
+#define REG32(x) (*((volatile unsigned long *)(x)))\r
+\r
+/* NVIC Registers */\r
+#define NVIC_INT_TYPE REG32(0xE000E004)\r
+#define NVIC_AUX_ACTLR REG32(0xE000E008)\r
+ #define WR_BUF_DISABLE (1 << 1)\r
+#define NVIC_ST_CTRL REG32(0xE000E010)\r
+ #define ST_ENABLE (1 << 0)\r
+ #define ST_TICKINT (1 << 1)\r
+ #define ST_CLKSOURCE (1 << 2)\r
+ #define ST_COUNTFLAG (1 << 3)\r
+#define NVIC_ST_RELOAD REG32(0xE000E014)\r
+#define NVIC_ST_CURRENT REG32(0xE000E018)\r
+#define NVIC_ST_CALIB REG32(0xE000E01C)\r
+#define NVIC_ENABLE0 REG32(0xE000E100)\r
+#define NVIC_ENABLE1 REG32(0xE000E104)\r
+#define NVIC_ENABLE2 REG32(0xE000E108)\r
+#define NVIC_ENABLE3 REG32(0xE000E10C)\r
+#define NVIC_ENABLE4 REG32(0xE000E110)\r
+#define NVIC_ENABLE5 REG32(0xE000E114)\r
+#define NVIC_ENABLE6 REG32(0xE000E118)\r
+#define NVIC_ENABLE7 REG32(0xE000E11C)\r
+#define NVIC_DISABLE0 REG32(0xE000E180)\r
+#define NVIC_DISABLE1 REG32(0xE000E184)\r
+#define NVIC_DISABLE2 REG32(0xE000E188)\r
+#define NVIC_DISABLE3 REG32(0xE000E18C)\r
+#define NVIC_DISABLE4 REG32(0xE000E190)\r
+#define NVIC_DISABLE5 REG32(0xE000E194)\r
+#define NVIC_DISABLE6 REG32(0xE000E198)\r
+#define NVIC_DISABLE7 REG32(0xE000E19C)\r
+#define NVIC_PEND0 REG32(0xE000E200)\r
+#define NVIC_PEND1 REG32(0xE000E204)\r
+#define NVIC_PEND2 REG32(0xE000E208)\r
+#define NVIC_PEND3 REG32(0xE000E20C)\r
+#define NVIC_PEND4 REG32(0xE000E210)\r
+#define NVIC_PEND5 REG32(0xE000E214)\r
+#define NVIC_PEND6 REG32(0xE000E218)\r
+#define NVIC_PEND7 REG32(0xE000E21C)\r
+#define NVIC_UNPEND0 REG32(0xE000E280)\r
+#define NVIC_UNPEND1 REG32(0xE000E284)\r
+#define NVIC_UNPEND2 REG32(0xE000E288)\r
+#define NVIC_UNPEND3 REG32(0xE000E28C)\r
+#define NVIC_UNPEND4 REG32(0xE000E290)\r
+#define NVIC_UNPEND5 REG32(0xE000E294)\r
+#define NVIC_UNPEND6 REG32(0xE000E298)\r
+#define NVIC_UNPEND7 REG32(0xE000E29C)\r
+#define NVIC_ACTIVE0 REG32(0xE000E300)\r
+#define NVIC_ACTIVE1 REG32(0xE000E304)\r
+#define NVIC_ACTIVE2 REG32(0xE000E308)\r
+#define NVIC_ACTIVE3 REG32(0xE000E30C)\r
+#define NVIC_ACTIVE4 REG32(0xE000E310)\r
+#define NVIC_ACTIVE5 REG32(0xE000E314)\r
+#define NVIC_ACTIVE6 REG32(0xE000E318)\r
+#define NVIC_ACTIVE7 REG32(0xE000E31C)\r
+#define NVIC_PRI0 REG32(0xE000E400)\r
+#define NVIC_PRI1 REG32(0xE000E404)\r
+#define NVIC_PRI2 REG32(0xE000E408)\r
+#define NVIC_PRI3 REG32(0xE000E40C)\r
+#define NVIC_PRI4 REG32(0xE000E410)\r
+#define NVIC_PRI5 REG32(0xE000E414)\r
+#define NVIC_PRI6 REG32(0xE000E418)\r
+#define NVIC_PRI7 REG32(0xE000E41C)\r
+#define NVIC_PRI8 REG32(0xE000E420)\r
+#define NVIC_PRI9 REG32(0xE000E424)\r
+#define NVIC_PRI10 REG32(0xE000E428)\r
+#define NVIC_PRI11 REG32(0xE000E42C)\r
+#define NVIC_PRI12 REG32(0xE000E430)\r
+#define NVIC_PRI13 REG32(0xE000E434)\r
+#define NVIC_PRI14 REG32(0xE000E438)\r
+#define NVIC_PRI15 REG32(0xE000E43C)\r
+#define NVIC_PRI16 REG32(0xE000E440)\r
+#define NVIC_PRI17 REG32(0xE000E444)\r
+#define NVIC_PRI18 REG32(0xE000E448)\r
+#define NVIC_PRI19 REG32(0xE000E44C)\r
+#define NVIC_PRI20 REG32(0xE000E450)\r
+#define NVIC_PRI21 REG32(0xE000E454)\r
+#define NVIC_PRI22 REG32(0xE000E458)\r
+#define NVIC_PRI23 REG32(0xE000E45C)\r
+#define NVIC_PRI24 REG32(0xE000E460)\r
+#define NVIC_PRI25 REG32(0xE000E464)\r
+#define NVIC_PRI26 REG32(0xE000E468)\r
+#define NVIC_PRI27 REG32(0xE000E46C)\r
+#define NVIC_PRI28 REG32(0xE000E470)\r
+#define NVIC_PRI29 REG32(0xE000E474)\r
+#define NVIC_PRI30 REG32(0xE000E478)\r
+#define NVIC_PRI31 REG32(0xE000E47C)\r
+#define NVIC_PRI32 REG32(0xE000E480)\r
+#define NVIC_PRI33 REG32(0xE000E484)\r
+#define NVIC_PRI34 REG32(0xE000E488)\r
+#define NVIC_PRI35 REG32(0xE000E48C)\r
+#define NVIC_PRI36 REG32(0xE000E490)\r
+#define NVIC_PRI37 REG32(0xE000E494)\r
+#define NVIC_PRI38 REG32(0xE000E498)\r
+#define NVIC_PRI39 REG32(0xE000E49C)\r
+#define NVIC_PRI40 REG32(0xE000E4A0)\r
+#define NVIC_PRI41 REG32(0xE000E4A4)\r
+#define NVIC_PRI42 REG32(0xE000E4A8)\r
+#define NVIC_PRI43 REG32(0xE000E4AC)\r
+#define NVIC_PRI44 REG32(0xE000E4B0)\r
+#define NVIC_PRI45 REG32(0xE000E4B4)\r
+#define NVIC_PRI46 REG32(0xE000E4B8)\r
+#define NVIC_PRI47 REG32(0xE000E4BC)\r
+#define NVIC_PRI48 REG32(0xE000E4C0)\r
+#define NVIC_PRI49 REG32(0xE000E4C4)\r
+#define NVIC_PRI50 REG32(0xE000E4C8)\r
+#define NVIC_PRI51 REG32(0xE000E4CC)\r
+#define NVIC_PRI52 REG32(0xE000E4D0)\r
+#define NVIC_PRI53 REG32(0xE000E4D4)\r
+#define NVIC_PRI54 REG32(0xE000E4D8)\r
+#define NVIC_PRI55 REG32(0xE000E4DC)\r
+#define NVIC_PRI56 REG32(0xE000E4E0)\r
+#define NVIC_PRI57 REG32(0xE000E4E4)\r
+#define NVIC_PRI58 REG32(0xE000E4E8)\r
+#define NVIC_PRI59 REG32(0xE000E4EC)\r
+#define NVIC_CPUID REG32(0xE000ED00)\r
+#define NVIC_INT_CTRL REG32(0xE000ED04)\r
+#define NVIC_VECT_TABLE REG32(0xE000ED08)\r
+#define NVIC_AP_INT_RST REG32(0xE000ED0C)\r
+#define NVIC_SYS_CTRL REG32(0xE000ED10)\r
+#define NVIC_CFG_CTRL REG32(0xE000ED14)\r
+#define NVIC_SYS_H_PRI1 REG32(0xE000ED18)\r
+#define NVIC_SYS_H_PRI2 REG32(0xE000ED1C)\r
+#define NVIC_SYS_H_PRI3 REG32(0xE000ED20)\r
+#define NVIC_SYS_H_CTRL REG32(0xE000ED24)\r
+#define NVIC_FAULT_STA REG32(0xE000ED28)\r
+#define NVIC_HARD_F_STA REG32(0xE000ED2C)\r
+#define NVIC_DBG_F_STA REG32(0xE000ED30)\r
+#define NVIC_MM_F_ADR REG32(0xE000ED34)\r
+#define NVIC_BUS_F_ADR REG32(0xE000ED38)\r
+#define NVIC_SW_TRIG REG32(0xE000EF00)\r
+\r
+/* MPU Registers */\r
+#define MPU_TYPE REG32(0xE000ED90)\r
+#define MPU_CTRL REG32(0xE000ED94)\r
+#define MPU_RG_NUM REG32(0xE000ED98)\r
+#define MPU_RG_ADDR REG32(0xE000ED9C)\r
+#define MPU_RG_AT_SZ REG32(0xE000EDA0)\r
+\r
+\r
+#endif /* #ifndef ARM_REG_H_ */\r
+\r
+/** @}\r
+ */\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+*****************************************************************************/\r
+\r
+\r
+\r
+#ifndef INCLUDE_CEC1302_CRYPTO_API_H_\r
+#define INCLUDE_CEC1302_CRYPTO_API_H_\r
+\r
+#include <stdint.h>\r
+#include <stdbool.h>\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Misc. */\r
+\r
+/* RNG */\r
+/**\r
+ * \rng_power\r
+ * \r
+ * \param [in] pwr_on Power On?\r
+ * \return none\r
+ * \r
+ * \details Gate clocks on/off to NDRNG block\r
+ */\r
+extern void\r
+rng_power(bool pwr_on);\r
+\r
+\r
+/**\r
+ * \rng_reset\r
+ * \r
+ * \return Reset NDRNG block\r
+ * \r
+ * \details \r
+ */\r
+extern void\r
+rng_reset(void);\r
+\r
+\r
+/**\r
+ * \rng_mode\r
+ * \r
+ * \param [in] mode tmode_pseudo 0(asynchronous/true random mode), \r
+ * Non-zero(pseudo-random mode)\r
+ * \return None\r
+ * \r
+ * \details Set NDRNG random number generation mode\r
+ */\r
+extern void\r
+rng_mode(uint8_t mode);\r
+\r
+\r
+/**\r
+ * \rng_is_on\r
+ * \r
+ * \return is NDRNG Block powered on? True if yes, false otherwise\r
+ * \r
+ * \details Check if NDRNG block is powered on.\r
+ */\r
+extern bool\r
+rng_is_on(void);\r
+\r
+\r
+/**\r
+ * \rng_start\r
+ * \r
+ * \return None\r
+ * \r
+ * \details Start NDRNG engine\r
+ */\r
+extern void\r
+rng_start(void);\r
+\r
+/**\r
+ * \rng_stop\r
+ * \r
+ * \return Void\r
+ * \r
+ * \details Stop NDRNG engine\r
+ */\r
+extern void\r
+rng_stop(void);\r
+\r
+\r
+/**\r
+ * \rng_get_fifo_level\r
+ * \r
+ * \return actual number of 32-bit words in the NDRNG FIFO.\r
+ * \r
+ * \details return the number of 32-bit words of random data \r
+ * currently in the FIFO.\r
+ */\r
+extern uint32_t\r
+rng_get_fifo_level(void);\r
+\r
+\r
+/**\r
+ * \rng_get_bytes\r
+ * \r
+ * \param [in] pbuff Output Buffer\r
+ * \param [in] nbytes Number of bytes to be read\r
+ * \return Number of bytes retrieved\r
+ * \r
+ * \details read bytes from the NDRNG FIFO\r
+ */\r
+extern uint32_t\r
+rng_get_bytes(uint8_t* pbuff, uint32_t nbytes);\r
+\r
+\r
+/**\r
+ * \rng_get_words\r
+ * \r
+ * \param [in] pwords Pointer to output buffer\r
+ * \param [in] nwords Number of words to read\r
+ * \return actual number of words read\r
+ * \r
+ * \details Details\r
+ */\r
+extern uint32_t\r
+rng_get_words(uint32_t* pwords, uint32_t nwords);\r
+\r
+\r
+/* AES */\r
+/**\r
+ * \aes_hash_power\r
+ * \r
+ * \param [in] pwr_on Gate/Ungate clocks to block\r
+ * \return None\r
+ * \r
+ * \details Enable/Disable AES and HASH H/W Block\r
+ */\r
+extern void\r
+aes_hash_power(uint8_t pwr_on);\r
+\r
+/**\r
+ * \aes_hash_reset\r
+ * \r
+ * \return None\r
+ * \r
+ * \details Stop AES and HASH\r
+ */\r
+extern void\r
+aes_hash_reset(void);\r
+\r
+/**\r
+ * \aes_busy\r
+ * \r
+ * \return Is AES Block Running? True if yes, false Otherwise.\r
+ * \r
+ * \details Is AES Block Running?\r
+ */\r
+extern bool\r
+aes_busy(void);\r
+\r
+\r
+/**\r
+ * \aes_status\r
+ * \r
+ * \return Status of AES Block\r
+ * \r
+ * \details Returns the Status of AES Block\r
+ */\r
+extern uint32_t\r
+aes_status(void);\r
+\r
+/**\r
+ * \aes_done_status\r
+ * \r
+ * \param [in] hw_status Pointer to where the status value will be updated\r
+ * \return True if done, false otherwise\r
+ * \r
+ * \details Returns the done status of AES block\r
+ */\r
+extern bool\r
+aes_done_status(uint32_t* hw_status);\r
+\r
+/**\r
+ * \aes_stop\r
+ * \r
+ * \return Return aes_busy() Status\r
+ * \r
+ * \details Stop AES Operations\r
+ */\r
+extern bool\r
+aes_stop(void);\r
+\r
+/**\r
+ * \aes_start\r
+ * \r
+ * \param [in] ien Enable interrupts?\r
+ * \return None\r
+ * \r
+ * \details Start AES block with or without interrupts\r
+ */\r
+extern void\r
+aes_start(bool ien);\r
+\r
+/**\r
+ * \aes_iclr\r
+ * \r
+ * \return Status of the AES Block\r
+ * \r
+ * \details Clears AES Hash Interrupts\r
+ */\r
+extern uint32_t\r
+aes_iclr(void);\r
+\r
+\r
+/**\r
+ * \brief Brief\r
+ * \r
+ * \param [in] pkey Aligned buffer with AES Key\r
+ * \param [in] piv Aligned buffer with AES initialization\r
+ * \param [in] key_len AES_KEYLEN_128, AES_KEYLEN_192, AES_KEYLEN_256\r
+ * \param [in] msbf Most Significant Byte order first?\r
+ * \return AES_ERR_BAD_POINTER, AES_ERR_BAD_KEY_LEN, AES_OK\r
+ * \r
+ * \details Load AES Accelerator with key and optional Initialization vector\r
+ */\r
+extern uint8_t\r
+aes_set_key(const uint32_t* pkey,\r
+ const uint32_t* piv,\r
+ uint8_t key_len, bool msbf);\r
+\r
+/**\r
+ * \aes_crypt\r
+ * \r
+ * \param [in] data_in Aligned input data Buffer\r
+ * \param [in] data_out Aligned output data buffer\r
+ * \param [in] num_128bit_blocks Size of input in 16-byte blocks\r
+ * \param [in] mode AES Encryption/Decryption Mode\r
+ * \return AES_OK, AES_ERR_BAD_POINTER, \r
+ * \r
+ * \details Program specified AES Operation using currently programmed key\r
+ */\r
+extern uint8_t\r
+aes_crypt(const uint32_t* data_in,\r
+ uint32_t* data_out,\r
+ uint32_t num_128bit_blocks, uint8_t mode);\r
+\r
+\r
+/* SHA */\r
+#define SHA1_BLEN (20u)\r
+#define SHA1_WLEN (5u)\r
+#define SHA2_BLEN (32u)\r
+#define SHA2_WLEN (8u)\r
+#define SHA12_BLOCK_BLEN (64u)\r
+#define SHA12_BLOCK_WLEN (16u)\r
+#define SHA3_BLEN (48u)\r
+#define SHA3_WLEN (12u)\r
+#define SHA5_BLEN (64u)\r
+#define SHA5_WLEN (16u)\r
+\r
+/* return values */\r
+#define SHA_RET_OK (0) /* OK */\r
+#define SHA_RET_START (1) /* OK, SHA Engine started */\r
+#define SHA_RET_ERROR (0x80) /* b[7]==1 indicates an error */\r
+#define SHA_RET_ERR_BUSY (0x80)\r
+#define SHA_RET_ERR_BAD_ADDR (0x81)\r
+#define SHA_RET_ERR_TIMEOUT (0x82)\r
+#define SHA_RET_ERR_MAX_LEN (0x83)\r
+#define SHA_RET_ERR_UNSUPPORTED (0x84)\r
+\r
+#define SHA_MODE_MD5 (0) // Not supported by HW\r
+#define SHA_MODE_1 (1)\r
+#define SHA_MODE_224 (2) // Not supported by HW\r
+#define SHA_MODE_256 (3)\r
+#define SHA_MODE_384 (4) // Not supported by HW\r
+#define SHA_MODE_512 (5) // Not supported by HW\r
+\r
+#define HASH_START_IEN (1u)\r
+#define HASH_START_NOIEN (0u)\r
+\r
+typedef union {\r
+ uint32_t w[SHA2_WLEN];\r
+ uint8_t b[SHA2_BLEN];\r
+} SHA12_DIGEST_U;\r
+\r
+\r
+/*\r
+ * !!! SHA-1 & SHA-256\r
+ * HW Engine requires alignment >= 4-byte boundary !!!\r
+ */\r
+typedef struct sha12_context_s SHA12_CONTEXT_T;\r
+struct sha12_context_s {\r
+ SHA12_DIGEST_U hash;\r
+ union {\r
+ uint32_t w[(SHA12_BLOCK_WLEN) * 2];\r
+ uint8_t b[(SHA12_BLOCK_BLEN) * 2];\r
+ } block;\r
+ uint8_t mode;\r
+ uint8_t block_len;\r
+ uint8_t rsvd[2];\r
+ uint32_t total_msg_len;\r
+};\r
+\r
+\r
+/**\r
+ * \hash_busy\r
+ * \r
+ * \return is busy? True if yes, Flase other wise\r
+ * \r
+ * \details returns the busy status of Hash Block\r
+ */\r
+extern bool hash_busy(void);\r
+\r
+/**\r
+ * \hash_start\r
+ * \r
+ * \param [in] ien enable/disable interrupts\r
+ * \return None\r
+ * \r
+ * \details start hash block\r
+ */\r
+extern void\r
+hash_start(bool ien);\r
+\r
+/**\r
+ * \hash_done_status\r
+ * \r
+ * \param [in] hw_status Hash Status Register Value\r
+ * \return true if done, false otherwise\r
+ * \r
+ * \details reflects the done status of HASH black and updates\r
+ * status regsiter value into the input variable\r
+ */\r
+extern bool\r
+hash_done_status(uint32_t* hw_status);\r
+\r
+/**\r
+ * \sha12_init\r
+ * \r
+ * \param [in] psha12_ctx Data Structure for Input data and Output Digest\r
+ * \param [in] mode SHA_MODE_1 or SHA_MODE_256\r
+ * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_UNSPPORTED ,SHA_RET_OK\r
+ * \r
+ * \details Initializes the Data structure provided\r
+ */\r
+extern uint8_t\r
+sha12_init(SHA12_CONTEXT_T* psha12_ctx, uint8_t mode);\r
+\r
+/**\r
+ * \sha12_update\r
+ * \r
+ * \param [in] psha12_ctx Data Structure for Input data and Output Digest\r
+ * \param [in] pdata Input Data to Hash Block\r
+ * \param [in] num_bytes Byte length of input data\r
+ * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY, SHA_RET_ERR_MAX_LEN, SHA_RET_OK \r
+ * \r
+ * \details Run hash block on data and if data greater than block size, put remaining bytes back into the data structure \r
+ */\r
+extern uint8_t\r
+sha12_update(SHA12_CONTEXT_T* psha12_ctx,\r
+ const uint32_t* pdata, uint32_t num_bytes);\r
+\r
+/**\r
+ * \sha12_finalize\r
+ * \r
+ * \param [in] psha12_ctx Data Structure for Input data and Output Digest\r
+ * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START \r
+ * \r
+ * \details Apply FIPS padding to SHA256 and perform final hash calculation.\r
+ */\r
+extern uint8_t\r
+sha12_finalize(SHA12_CONTEXT_T* psha12_ctx);\r
+\r
+/**\r
+ * \sha256_pad_fill\r
+ * \r
+ * \param [in] pblock64 Aligned Memory buffer of atleast 64 bytes\r
+ * \param [in] msg_byte_len Length of Message in bytes\r
+ * \return None\r
+ * \r
+ * \details Zero and fill a 64-byte SHA256 pad block with FIP padding values\r
+ */\r
+extern void\r
+sha256_pad_fill(uint32_t* pblock64, uint32_t msg_byte_len);\r
+\r
+\r
+/**\r
+ * \sha256_raw\r
+ * \r
+ * \param [in] pdata Input Message\r
+ * \param [in] pdigest Pointer to biffer where digest will be written\r
+ * \param [in] num64byte_blocks size of input data in blocks\r
+ * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START \r
+ * \r
+ * \details Calculate SHA256 on data\r
+ */\r
+extern uint8_t\r
+sha256_raw(uint32_t* pdata, uint32_t* pdigest, uint32_t num64byte_blocks);\r
+\r
+/**\r
+ * \sha256_raw_init\r
+ * \r
+ * \param [in] psha256_digest Pointer to buffer where digest will be written\r
+ * \return None\r
+ * \r
+ * \details Initialize the SHA256 Digest data block\r
+ */\r
+extern void\r
+sha256_raw_init(uint32_t* psha256_digest);\r
+\r
+/**\r
+ * \sha256_raw_update\r
+ * \r
+ * \param [in] pdata Message on which HASH block is to be called\r
+ * \param [in] pdigest Pointer to where the digest will be stored\r
+ * \param [in] num64byte_blocks size of input data in blocks\r
+ * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START\r
+ * \r
+ * \details run Hash block on data\r
+ */\r
+extern uint8_t\r
+sha256_raw_update(uint32_t* pdata,\r
+ uint32_t* pdigest, uint32_t num64byte_blocks);\r
+\r
+/**\r
+ * \hash_iclr\r
+ * \r
+ * \return Hash Block status\r
+ * \r
+ * \details Clear Hash Interrupt\r
+ */\r
+extern uint32_t\r
+hash_iclr(void);\r
+\r
+\r
+/**\r
+ * \sha_init\r
+ * \r
+ * \param [in] mode SHA_MODE_1, SHA_MODE_256, SHA_MODE_512\r
+ * \param [in] pdigest Address where digest will be stored\r
+ * \return * 0 = Success \r
+ * 1 = Hash Engine busy \r
+ * 2 = Unsupported SHA operation \r
+ * 3 = Bad digest pointer, NULL or mis-aligned. \r
+ * \details Initialize Hash engine for SHA operation.\r
+ * Programs supported SHA operation's initial value, digest address, \r
+ * and operation\r
+ */\r
+extern uint8_t\r
+sha_init(uint8_t mode, uint32_t* pdigest);\r
+\r
+\r
+/**\r
+ * \sha_update\r
+ * \r
+ * \param [in] pdata Input Data\r
+ * \param [in] nblocks Size in blocks\r
+ * \param [in] flags bit(0) - Clear Status?, bit(1) - Enable Interrupts?, bit(2) - Start?\r
+ * \return 0 - OK, 1 - Hash Busy, 2 - bad address for data, 3 - Buffer not aligned\r
+ * \r
+ * \details Run Hash block on data\r
+ */\r
+extern uint8_t\r
+sha_update(uint32_t* pdata, uint16_t nblocks, uint8_t flags);\r
+\r
+\r
+/**\r
+ * \sha_final\r
+ * \r
+ * \param [in] padbuf Buffer for padding (Twice block size)\r
+ * \param [in] total_msg_len Message length in bytes\r
+ * \param [in] prem Parameter_Description\r
+ * \param [in] flags bit(0) - Clear Status?, bit(1) - Enable Interrupts?, bit(2) - Start?\r
+ * \return 0 - OK, 1 - Hash Busy, 2 - bad address for data, 3 - Buffer not aligned\r
+ * \r
+ * \details Run final SHA Calculations and add padding\r
+ */\r
+extern uint8_t\r
+sha_final(uint32_t* padbuf, uint32_t total_msg_len,\r
+ const uint8_t* prem, uint8_t flags);\r
+\r
+\r
+/* PKE Miscellaneous */\r
+\r
+#define PKE_RET_STARTED (0)\r
+#define PKE_RET_OK (0)\r
+#define PKE_RET_ERR_BUSY (1)\r
+#define PKE_RET_ERR_BAD_PARAM (2)\r
+#define PKE_RET_ERR_BAD_ADDR (3)\r
+#define PKE_RET_ERR_UNKNOWN_OP (4)\r
+#define PKE_RET_ERR_INVALID_BIT_LENGTH (5)\r
+#define PKE_RET_ERR_INVALID_MSG_LENGTH (6)\r
+\r
+\r
+/**\r
+ * \pke_power\r
+ * \r
+ * \param [in] pwr_on power on? \r
+ * \return None\r
+ * \r
+ * \details Gate or Ungate power to PKE block\r
+ */\r
+extern void\r
+pke_power(bool pwr_on);\r
+\r
+\r
+/**\r
+ * \brief pke_reset\r
+ * \r
+ * \return None\r
+ * \r
+ * \details Reset PKE Block\r
+ */\r
+extern void\r
+pke_reset(void);\r
+\r
+/**\r
+ * \pke_status\r
+ * \r
+ * \return Return PKE Status register value\r
+ * \r
+ * \details Details\r
+ */\r
+extern uint32_t\r
+pke_status(void);\r
+\r
+/**\r
+ * \pke_done_status\r
+ * \r
+ * \param [in] hw_status POinter where PKE Status is updated\r
+ * \return True if done, false otherwise\r
+ * \r
+ * \details Returns the done status of PKE block\r
+ */\r
+extern bool\r
+pke_done_status(uint32_t* hw_status);\r
+\r
+/**\r
+ * \pke_start\r
+ * \r
+ * \param [in] ien Interrupt Enable?\r
+ * \return None\r
+ * \r
+ * \details Start PKE Block\r
+ */\r
+extern void\r
+pke_start(bool ien);\r
+\r
+\r
+/**\r
+ * \pke_busy\r
+ * \r
+ * \return Busy? True if busy, false otherwise\r
+ * \r
+ * \details Details\r
+ */\r
+extern bool\r
+pke_busy(void);\r
+\r
+\r
+/**\r
+ * \pke_clear_scm\r
+ * \r
+ * \return None\r
+ * \r
+ * \details Clear the Shared Crypto memory\r
+ */\r
+extern void\r
+pke_clear_scm(void);\r
+\r
+/**\r
+ * \pke_scm_clear_slot\r
+ * \r
+ * \param [in] slot_num Slot number in Shared Crypto Memory\r
+ * \return None\r
+ * \r
+ * \details Clear the specified slot in Shared Crypto Memory\r
+ */\r
+extern void\r
+pke_scm_clear_slot(uint8_t slot_num);\r
+\r
+/**\r
+ * \pke_read_scm \r
+ * \r
+ * \param [in] dest Pointer to where the data is to be read\r
+ * \param [in] nbytes Number of bytes to be read\r
+ * \param [in] slot_num Slot number from which data is to be read\r
+ * \param [in] reverse_byte_order Reverse Byte order? True if yes, false otherwise\r
+ * \return Number of bytes Read\r
+ * \r
+ * \details Read data from specified slot number in Shared Crypto memory\r
+ */\r
+extern uint16_t\r
+pke_read_scm(uint8_t* dest, uint16_t nbytes,\r
+ uint8_t slot_num, bool reverse_byte_order);\r
+\r
+\r
+/**\r
+ * \pke_write_scm \r
+ * \r
+ * \param [in] pdata Data to be written\r
+ * \param [in] num_bytes Number of bytes to be written\r
+ * \param [in] slot_num Slot number to which data ought to be written\r
+ * \param [in] reverse_byte_order Reverse Byte order? True if yes, false otherwise\r
+ * \return None\r
+ * \r
+ * \details Write data provided to specified slot in Shared Crypto Memory\r
+ */\r
+extern void\r
+pke_write_scm(const void* pdata, uint16_t num_bytes,\r
+ uint8_t slot_num, uint8_t reverse_byte_order);\r
+\r
+/* PKE RSA */\r
+\r
+/**\r
+ * \ rsa_load_key\r
+ * \r
+ * \param [in] rsa_bit_len 1024, 2048\r
+ * \param [in] private_exponent Pointer to private exponent\r
+ * \param [in] public_modulus Pointer to Public modulus\r
+ * \param [in] public_exponent Pointer to Public Exponent\r
+ * \param [in] public_exponent_byte_len Length in bytes of Public Exponent\r
+ * \param [in] msbf Reverse Byte order? True if yes, false otherwise\r
+ * \return PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK\r
+ * \r
+ * \details Load RSA keys into Crypto memory\r
+ */\r
+extern uint8_t\r
+rsa_load_key(uint16_t rsa_bit_len,\r
+ const uint8_t* private_exponent,\r
+ const uint8_t* public_modulus,\r
+ const uint8_t* public_exponent,\r
+ uint16_t public_exponent_byte_len,\r
+ bool msbf);\r
+\r
+ \r
+/**\r
+ * \ rsa_encrypt\r
+ * \r
+ * \param [in] rsa_bit_len 1024, 2048\r
+ * \param [in] mesg Message to be encrypted\r
+ * \param [in] mlen length of message\r
+ * \param [in] flags bit[0]=0(do not start), 1(start after programming), bit[4] = byte order: 0 = Least significant byte first, 1 = Most significant byte first, bit[1]=0(do not enable interrupt), 1(enable interrupt before starting) \r
+ * \return PKE_RET_ERR_BAD_ADDR, PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_MSG_LENGTH, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK\r
+ * \r
+ * \details Encrypt provided message. Load Keys before this function is called\r
+ */\r
+extern uint8_t\r
+rsa_encrypt(uint16_t rsa_bit_len,\r
+ const uint8_t* mesg,\r
+ uint16_t mlen,\r
+ uint8_t flags);\r
+ \r
+\r
+\r
+/**\r
+ * \ rsa_decrypt\r
+ * \r
+ * \param [in] rsa_bit_len 1024, 2048\r
+ * \param [in] encrypted_mesg Encrypted data\r
+ * \param [in] mlen length of encrypted message\r
+ * \param [in] flags flags bit[0]=0(do not start), 1(start after programming), bit[4] = byte order: 0 = Least significant byte first, 1 = Most significant byte first, bit[1]=0(do not enable interrupt), 1(enable interrupt before starting)\r
+ * \return PKE_RET_ERR_BAD_ADDR, PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_MSG_LENGTH, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK\r
+ * \r
+ * \details Perform decryption on provided encrypted message. load keys before calling this function\r
+ */\r
+extern uint8_t\r
+rsa_decrypt(uint16_t rsa_bit_len,\r
+ const uint8_t* encrypted_mesg,\r
+ uint16_t mlen,\r
+ uint8_t flags);\r
+\r
+ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* INCLUDE_CEC1302_CRYPTO_API_H_ */\r
--- /dev/null
+\r
+/****************************************************************************************************//**\r
+ * @file MCHP_CEC1302.h\r
+ *\r
+ * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for\r
+ * MCHP_CEC1302 from Microchip Technology Inc..\r
+ *\r
+ * @version V1.1\r
+ * @date 6. November 2015\r
+ *\r
+ * @note Generated with SVDConv V2.87e \r
+ * from CMSIS SVD File 'MCHP_CEC1302.svd' Version 1.1,\r
+ *\r
+ * @par ARM Limited (ARM) is supplying this software for use with Cortex-M processor based \r
+ * microcontroller, but can be equally used for other suitable processor architectures.\r
+ * This file can be freely distributed. Modifications to this file shall be clearly marked.\r
+ * \r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. \r
+ *\r
+ *******************************************************************************************************/\r
+\r
+\r
+\r
+/** @addtogroup Microchip Technology Inc.\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup MCHP_CEC1302\r
+ * @{\r
+ */\r
+\r
+#ifndef MCHP_CEC1302_H\r
+#define MCHP_CEC1302_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/* ------------------------- Interrupt Number Definition ------------------------ */\r
+\r
+typedef enum {\r
+/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */\r
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */\r
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation\r
+ and No Match */\r
+ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory\r
+ related Fault */\r
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */\r
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */\r
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */\r
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */\r
+/* ------------------- MCHP_CEC1302 Specific Interrupt Numbers ------------------ */\r
+ I2C0_IRQn = 0, /*!< 0 I2C0 / SMB0 Interrupt ................. Also see GIRQ 12.0 */\r
+ I2C1_IRQn = 1, /*!< 1 I2C1 / SMB1 Interrupt ................. Also see GIRQ 12.1 */\r
+ I2C2_IRQn = 2, /*!< 2 I2C2 / SMB2 Interrupt ................. Also see GIRQ 12.2 */\r
+ I2C3_IRQn = 3, /*!< 3 I2C3 / SMB3 Interrupt ................. Also see GIRQ 12.3 */\r
+ DMA0_IRQn = 4, /*!< 4 DMA_CH0 Interrupt ..................... Also see GIRQ 13.16 */\r
+ DMA1_IRQn = 5, /*!< 5 DMA_CH1 Interrupt ..................... Also see GIRQ 13.17 */\r
+ DMA2_IRQn = 6, /*!< 6 DMA_CH2 Interrupt ..................... Also see GIRQ 13.18 */\r
+ DMA3_IRQn = 7, /*!< 7 DMA_CH3 Interrupt ..................... Also see GIRQ 13.19 */\r
+ DMA4_IRQn = 8, /*!< 8 DMA_CH4 Interrupt ..................... Also see GIRQ 13.20 */\r
+ DMA5_IRQn = 9, /*!< 9 DMA_CH5 Interrupt ..................... Also see GIRQ 13.21 */\r
+ DMA6_IRQn = 10, /*!< 10 DMA_CH6 Interrupt ..................... Also see GIRQ 13.22 */\r
+ DMA7_IRQn = 11, /*!< 11 DMA_CH7 Interrupt ..................... Also see GIRQ 13.23 */\r
+ LPC_IRQn = 12, /*!< 12 LPC Interrupt ......................... Also see GIRQ 14.2 */\r
+ UART_IRQn = 13, /*!< 13 UART Interrupt ........................ Also see GIRQ 15.0 */\r
+ EMI_0_IRQn = 14, /*!< 14 EMI_0 (IMAP) Interrupt ................ Also see GIRQ 15.2 */\r
+ ACPIEC0_IBF_IRQn = 15, /*!< 15 ACPIEC[0] IBF Interrupt ............... Also see GIRQ 15.6 */\r
+ ACPIEC0_OBF_IRQn = 16, /*!< 16 ACPIEC[0] OBF Interrupt ............... Also see GIRQ 15.7 */\r
+ ACPIEC1_IBF_IRQn = 17, /*!< 17 ACPIEC[1] IBF Interrupt ............... Also see GIRQ 15.8 */\r
+ ACPIEC1_OBF_IRQn = 18, /*!< 18 ACPIEC[1] OBF Interrupt ............... Also see GIRQ 15.9 */\r
+ ACPIPM1_CTL_IRQn = 19, /*!< 19 ACPIPM1_CTL Interrupt ................. Also see GIRQ 15.10 */\r
+ ACPIPM1_EN_IRQn = 20, /*!< 20 ACPIPM1_EN Interrupt .................. Also see GIRQ 15.11 */\r
+ ACPIPM1_STS_IRQn = 21, /*!< 21 ACPIPM1_STS Interrupt ................. Also see GIRQ 15.12 */\r
+ KBC8042_OBF_IRQn = 22, /*!< 22 8042EM OBF Interrupt .................. Also see GIRQ 15.13 */\r
+ KBC8042_IBF_IRQn = 23, /*!< 23 8042EM IBF Interrupt .................. Also see GIRQ 15.14 */\r
+ MAILBOX_IRQn = 24, /*!< 24 MAILBOX Interrupt ..................... Also see GIRQ 15.15 */\r
+ PECIHOST_IRQn = 25, /*!< 25 PECIHOST Interrupt .................... Also see GIRQ 16.3 */\r
+ TACH_0_IRQn = 26, /*!< 26 TACH_0 Interrupt ...................... Also see GIRQ 17.0 */\r
+ TACH_1_IRQn = 27, /*!< 27 TACH_1 Interrupt ...................... Also see GIRQ 17.1 */\r
+ ADC_SNGL_IRQn = 28, /*!< 28 ADC_SNGL Interrupt .................... Also see GIRQ 17.10 */\r
+ ADC_RPT_IRQn = 29, /*!< 29 ADC_RPT Interrupt ..................... Also see GIRQ 17.11 */\r
+ ADC2PWM_N1_IRQn = 30, /*!< 30 MCHP Reserved ADC2PWM_INT_N1 .......... Also see GIRQ 17.12 */\r
+ ADC2PWM_N2_IRQn = 31, /*!< 31 MCHP Reserved ADC2PWM_INT_N2 .......... Also see GIRQ 17.13 */\r
+ PS2_0_IRQn = 32, /*!< 32 PS2_0 Interrupt ....................... Also see GIRQ 17.14 */\r
+ PS2_1_IRQn = 33, /*!< 33 PS2_1 Interrupt ....................... Also see GIRQ 17.15 */\r
+ PS2_2_IRQn = 34, /*!< 34 PS2_2 Interrupt ....................... Also see GIRQ 17.16 */\r
+ PS2_3_IRQn = 35, /*!< 35 PS2_3 Interrupt ....................... Also see GIRQ 17.17 */\r
+ SPI0_TX_IRQn = 36, /*!< 36 SPI0 TX Interrupt ..................... Also see GIRQ 18.0 */\r
+ SPI0_RX_IRQn = 37, /*!< 37 SPI0 RX Interrupt ..................... Also see GIRQ 18.1 */\r
+ HTIMER_IRQn = 38, /*!< 38 HTIMER Interrupt ...................... Also see GIRQ 17.20 */\r
+ KEYSCAN_IRQn = 39, /*!< 39 KSC Interrupt ......................... Also see GIRQ 17.21 */\r
+ MAILBOX_DATA_IRQn = 40, /*!< 40 MAILBOX DATA Interrupt ................ Also see GIRQ 15.16 */\r
+ RPM_STALL_IRQn = 41, /*!< 41 RPM_INT Stall Interrupt ............... Also see GIRQ 17.23 */\r
+ RPM_SPIN_IRQn = 42, /*!< 42 RPM_INT Spin Interrupt ................ Also see GIRQ 17.24 */\r
+ PFR_STS_IRQn = 43, /*!< 43 PFR_STS Interrupt ..................... Also see GIRQ 17.25 */\r
+ PWM_WDT0_IRQn = 44, /*!< 44 PWM_WDT0 Interrupt .................... Also see GIRQ 17.26 */\r
+ PWM_WDT1_IRQn = 45, /*!< 45 PWM_WDT1 Interrupt .................... Also see GIRQ 17.27 */\r
+ PWM_WDT2_IRQn = 46, /*!< 46 PWM_WDT2 Interrupt .................... Also see GIRQ 17.28 */\r
+ BCM_ERR_IRQn = 47, /*!< 47 BCM_INT Err Interrupt ................. Also see GIRQ 17.29 */\r
+ BCM_BUSY_IRQn = 48, /*!< 48 BCM_INT Busy Interrupt ................ Also see GIRQ 17.30 */\r
+ TIMER0_IRQn = 49, /*!< 49 TIMER_16_0 Interrupt .................. Also see GIRQ 23.0 */\r
+ TIMER1_IRQn = 50, /*!< 50 TIMER_16_1 Interrupt .................. Also see GIRQ 23.1 */\r
+ TIMER2_IRQn = 51, /*!< 51 TIMER_16_2 Interrupt .................. Also see GIRQ 23.2 */\r
+ TIMER3_IRQn = 52, /*!< 52 TIMER_16_3 Interrupt .................. Also see GIRQ 23.3 */\r
+ TIMER4_IRQn = 53, /*!< 53 TIMER_32_0 Interrupt .................. Also see GIRQ 23.4 */\r
+ TIMER5_IRQn = 54, /*!< 54 TIMER_32_1 Interrupt .................. Also see GIRQ 23.5 */\r
+ SPI1_TX_IRQn = 55, /*!< 55 SPI1 TX Interrupt ..................... Also see GIRQ 18.2 */\r
+ SPI1_RX_IRQn = 56, /*!< 56 SPI1 RX Interrupt ..................... Also see GIRQ 18.3 */\r
+ GIRQ08_IRQn = 57, /*!< 57 GIRQ08 ................................ Interrupt Aggregator */\r
+ GIRQ09_IRQn = 58, /*!< 58 GIRQ09 ................................ Interrupt Aggregator */\r
+ GIRQ10_IRQn = 59, /*!< 59 GIRQ10 ................................ Interrupt Aggregator */\r
+ GIRQ11_IRQn = 60, /*!< 60 GIRQ11 ................................ Interrupt Aggregator */\r
+ GIRQ12_IRQn = 61, /*!< 61 GIRQ12 ................................ Interrupt Aggregator */\r
+ GIRQ13_IRQn = 62, /*!< 62 GIRQ13 ................................ Interrupt Aggregator */\r
+ GIRQ14_IRQn = 63, /*!< 63 GIRQ14 ................................ Interrupt Aggregator */\r
+ GIRQ15_IRQn = 64, /*!< 64 GIRQ15 ................................ Interrupt Aggregator */\r
+ GIRQ16_IRQn = 65, /*!< 65 GIRQ16 ................................ Interrupt Aggregator */\r
+ GIRQ17_IRQn = 66, /*!< 66 GIRQ17 ................................ Interrupt Aggregator */\r
+ GIRQ18_IRQn = 67, /*!< 67 GIRQ18 ................................ Interrupt Aggregator */\r
+ GIRQ19_IRQn = 68, /*!< 68 GIRQ19 ................................ Interrupt Aggregator */\r
+ GIRQ20_IRQn = 69, /*!< 69 GIRQ20 ................................ Interrupt Aggregator */\r
+ GIRQ21_IRQn = 70, /*!< 70 GIRQ21 ................................ Interrupt Aggregator */\r
+ GIRQ22_IRQn = 71, /*!< 71 GIRQ22 ................................ Interrupt Aggregator */\r
+ GIRQ23_IRQn = 72, /*!< 72 GIRQ23 ................................ Interrupt Aggregator */\r
+ DMA8_IRQn = 81, /*!< 81 DMA_CH8 Interrupt ..................... Also see GIRQ 13.24 */\r
+ DMA9_IRQn = 82, /*!< 82 DMA_CH9 Interrupt ..................... Also see GIRQ 13.25 */\r
+ DMA10_IRQn = 83, /*!< 83 DMA_CH10 Interrupt .................... Also see GIRQ 13.26 */\r
+ DMA11_IRQn = 84, /*!< 84 DMA_CH11 Interrupt .................... Also see GIRQ 13.27 */\r
+ PWM_WDT3_IRQn = 85, /*!< 85 PWM_WDT3 Interrupt .................... Also see GIRQ 18.4 */\r
+ RTC_IRQn = 91, /*!< 91 RTC Interrupt ......................... Also see GIRQ 17.18 */\r
+ RTC_ALARM_IRQn = 92, /*!< 92 RTC ALARM Interrupt ................... Also see GIRQ 17.19 */\r
+ MAX_IRQn\r
+} IRQn_Type;\r
+\r
+\r
+/** @addtogroup Configuration_of_CMSIS\r
+ * @{\r
+ */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Processor and Core Peripheral Section ================ */\r
+/* ================================================================================ */\r
+\r
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */\r
+#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1 /*!< FPU present or not */\r
+/** @} */ /* End of group Configuration_of_CMSIS */\r
+\r
+#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */\r
+\r
+/* ================================================================================ */\r
+/* ================ Custom Defines (added manually) ================ */\r
+/* ================================================================================ */\r
+\r
+/* Register Union */\r
+typedef union\r
+{\r
+ uint32_t w;\r
+ uint16_t h[2];\r
+ uint8_t b[4];\r
+} REG32_U;\r
+\r
+/* ================================================================================ */\r
+/* ================ Device Specific Peripheral Section ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/** @addtogroup Device_Peripheral_Registers\r
+ * @{\r
+ */\r
+\r
+\r
+/* ------------------- Start of section using anonymous unions ------------------ */\r
+#if defined(__CC_ARM)\r
+ #pragma push\r
+ #pragma anon_unions\r
+#elif defined(__ICCARM__)\r
+ #pragma language=extended\r
+#elif defined(__GNUC__)\r
+ /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+/* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+ #pragma warning 586\r
+#else\r
+ #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+typedef struct {\r
+ union {\r
+ __IO uint16_t CR; /*!< MEM_BAR Control [15:0] */\r
+ \r
+ struct {\r
+ __IO uint16_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
+ __IO uint16_t FRAME : 6; /*!< Specify a logical device frame number */\r
+ uint16_t : 1;\r
+ __IO uint16_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
+ } CR_b; /*!< BitSize */\r
+ };\r
+ __IO uint16_t HOST_LO_ADDR; /*!< HOST_ADDRESS[15:0] */\r
+ __IO uint16_t HOST_HI_ADDR; /*!< HOST_ADDRESS[31:16] */\r
+} LPC_CONFIG_MEM_BAR_Type;\r
+\r
+typedef struct {\r
+ __IO uint32_t SOURCE; /*!< GIRQx Source Register(R/WC) */\r
+ __IO uint32_t ENABLE_SET; /*!< GIRQx Enable Set Register (R/WS) */\r
+ __I uint32_t RESULT; /*!< GIRQx Result Register */\r
+ __IO uint32_t ENABLE_CLEAR; /*!< GIRQx Enable Clear Register. */\r
+ __I uint32_t RESERVED;\r
+} INTR_IRQ_Type;\r
+\r
+typedef struct {\r
+ union {\r
+ __IO uint8_t ACTIVATE; /*!< Enable this channel for operation. */\r
+ \r
+ struct {\r
+ __IO uint8_t EN : 1; /*!< Enable this channel for operation. */\r
+ } ACTIVATE_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED1[3];\r
+ __IO uint32_t MEM_START_ADDR; /*!< starting address for the Memory device. */\r
+ __IO uint32_t MEM_END_ADDR; /*!< ending address for the Memory device. */\r
+ __IO uint32_t DEVICE_ADDR; /*!< This is the Master Device address. */\r
+ \r
+ union {\r
+ __IO uint32_t CONTROL; /*!< DMA Channel N Control */\r
+ \r
+ struct {\r
+ __IO uint32_t RUN : 1; /*!< 1= enabled and will service transfer requests */\r
+ __I uint32_t REQUEST : 1; /*!< 1= transfer request from the Master Device */\r
+ __I uint32_t DONE : 1; /*!< status signal. 1=Channel is done */\r
+ __I uint32_t STATUS : 2; /*!< 3: Error,2/1: ext/locally done,0:Disabled */\r
+ __IO uint32_t BUSY : 1; /*!< 1=Channel is busy (FSM is not IDLE) */\r
+ uint32_t : 2;\r
+ __IO uint32_t TX_DIRECTION: 1; /*!< direction of Transfer. 1=Memory to Device */\r
+ __IO uint32_t HARDWARE_FLOW_CONTROL_DEVICE: 7;/*!< device as its Hardware Flow Control master. */\r
+ __IO uint32_t INCREMENT_MEM_ADDR: 1; /*!< auto-increment DMA Channel Memory Address. */\r
+ __IO uint32_t INCREMENT_DEVICE_ADDR: 1; /*!< auto-increment DMA Channel Device Address. */\r
+ __IO uint32_t LOCK : 1; /*!< lock the arbitration of Channel Arbiter */\r
+ __IO uint32_t DISABLE_HW_FLOW_CONTROL: 1; /*!< Disable the Hardware Flow Control. */\r
+ __IO uint32_t TRANSFER_SIZE: 3; /*!< transfer size in Bytes of each Data Packet */\r
+ uint32_t : 1;\r
+ __IO uint32_t TRANSFER_GO: 1; /*!< Firmware Flow Control DMA transfer. */\r
+ __IO uint32_t TRANSFER_ABORT: 1; /*!< abort the current transfer */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint8_t INT_STATUS; /*!< DMA Channel N Interrupt Status */\r
+ \r
+ struct {\r
+ __IO uint8_t BUS_ERROR : 1; /*!< interrupt source. 1: Error detected.(R/WC) */\r
+ __IO uint8_t FLOW_CONTROL: 1; /*!< Intr source.1=HW Flow Ctrl is requesting */\r
+ __IO uint8_t DONE : 1; /*!< intr source. 1= Start Address equals End */\r
+ } INT_STATUS_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED2[3];\r
+ \r
+ union {\r
+ __IO uint8_t INT_EN; /*!< DMA CHANNEL N INTERRUPT ENABLE */\r
+ \r
+ struct {\r
+ __IO uint8_t BUS_ERROR : 1; /*!< 1=enable Interrupt:Status AMBA Bus Error. */\r
+ __IO uint8_t FLOW_CONTROL: 1; /*!< 1=enable Interrupt:Status Flow Control Error. */\r
+ __IO uint8_t DONE : 1; /*!< 1=enable Interrupt:Status Done.\r
+ */\r
+ } INT_EN_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED3[7];\r
+} DMA_CH_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PCR ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The Power, Clocks, and Resets (PCR) chapter identifies all the power supplies,\r
+ clock sources, and reset inputs to the chip and defines all the derived power, clock, and reset signals. (PCR)\r
+ */\r
+\r
+typedef struct { /*!< PCR Structure */\r
+ __IO uint32_t CHIP_SLP_EN; /*!< Chip Sleep Enable Register. (MCHP Reserved) */\r
+ __I uint32_t CHIP_CLK_REQ_STS; /*!< Chip Clock Required Status. (MCHP Reserved) */\r
+ \r
+ union {\r
+ __IO uint32_t EC_SLP_EN; /*!< EC Sleep Enable Register (EC_SLP_EN) */\r
+ \r
+ struct {\r
+ __IO uint32_t INT_SLP_EN : 1; /*!< INT Sleep Enable (INT_SLP_EN) */\r
+ __IO uint32_t PECI_SLP_EN: 1; /*!< PECI Sleep Enable (PECI_SLP_EN) */\r
+ __IO uint32_t TACH0_SLP_EN: 1; /*!< TACH0 Sleep Enable (TACH0_SLP_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t PWM0_SLP_EN: 1; /*!< PWM0 Sleep Enable (PWM0_SLP_EN) */\r
+ __IO uint32_t PMC_SLP_EN : 1; /*!< PMC Sleep Enable (PMC_SLP_EN) */\r
+ __IO uint32_t DMA_SLP_EN : 1; /*!< DMA Sleep Enable (DMA_SLP_EN) */\r
+ __IO uint32_t TFDP_SLP_EN: 1; /*!< TFDP Sleep Enable (TFDP_SLP_EN) */\r
+ __IO uint32_t PROCESSOR_SLP_EN: 1; /*!< PROCESSOR Sleep Enable (PROCESSOR_SLP_EN) */\r
+ __IO uint32_t WDT_SLP_EN : 1; /*!< WDT Sleep Enable (WDT_SLP_EN) */\r
+ __IO uint32_t SMB0_SLP_EN: 1; /*!< SMB0 Sleep Enable (SMB0_SLP_EN) */\r
+ __IO uint32_t TACH1_SLP_EN: 1; /*!< TACH1 Sleep Enable (TACH1_SLP_EN) */\r
+ uint32_t : 8;\r
+ __IO uint32_t PWM1_SLP_EN: 1; /*!< PWM1 Sleep Enable (PWM1_SLP_EN) */\r
+ __IO uint32_t PWM2_SLP_EN: 1; /*!< PWM2 Sleep Enable (PWM2_SLP_EN) */\r
+ __IO uint32_t PWM3_SLP_EN: 1; /*!< PWM3 Sleep Enable (PWM3_SLP_EN) */\r
+ uint32_t : 6;\r
+ __IO uint32_t EC_REG_BANK_SLP_EN: 1; /*!< EC_REG_BANK Sleep Enable (EC_REG_BANK_SLP_EN) */\r
+ __IO uint32_t TIMER16_0_SLP_EN: 1; /*!< TIMER16_0 Sleep Enable (TIMER16_0_SLP_EN) */\r
+ __IO uint32_t TIMER16_1_SLP_EN: 1; /*!< TIMER16_1 Sleep Enable (TIMER16_1_SLP_EN) */\r
+ } EC_SLP_EN_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __I uint32_t EC_CLK_REQ_STS; /*!< EC Clock Required Status Registers */\r
+ \r
+ struct {\r
+ __I uint32_t INT_CLK_REQ: 1; /*!< INT Clock Required (INT_CLK_REQ) */\r
+ __I uint32_t PECI_CLK_REQ: 1; /*!< PECI Clock Required (PECI_CLK_REQ) */\r
+ __I uint32_t TACH0_CLK_REQ: 1; /*!< TACH0 Clock Required (TACH0_CLK_REQ) */\r
+ uint32_t : 1;\r
+ __I uint32_t PWM0_CLK_REQ: 1; /*!< PWM0 Clock Required (PWM0_CLK_REQ) */\r
+ __I uint32_t PMC_CLK_REQ: 1; /*!< PMC Clock Required (PMC_CLK_REQ) */\r
+ __I uint32_t DMA_CLK_REQ: 1; /*!< DMA Clock Required (DMA_CLK_REQ) */\r
+ __I uint32_t TFDP_CLK_REQ: 1; /*!< TFDP Clock Required (TFDP_CLK_REQ) */\r
+ __I uint32_t PROCESSOR_CLK_REQ: 1; /*!< PROCESSOR Clock Required (PROCESSOR_CLK_REQ) */\r
+ __I uint32_t WDT_CLK_REQ: 1; /*!< WDT Clock Required (WDT_CLK_REQ) */\r
+ __I uint32_t SMB0_CLK_REQ: 1; /*!< SMB0 Clock Required (SMB0_CLK_REQ) */\r
+ __I uint32_t TACH1_CLK_REQ: 1; /*!< TACH1 Clock Required (TACH1_CLK_REQ) */\r
+ uint32_t : 8;\r
+ __I uint32_t PWM1_CLK_REQ: 1; /*!< PWM1 Clock Required (PWM1_CLK_REQ) */\r
+ __I uint32_t PWM2_CLK_REQ: 1; /*!< PWM2 Clock Required (PWM2_CLK_REQ) */\r
+ __I uint32_t PWM3_CLK_REQ: 1; /*!< PWM3 Clock Required (PWM3_CLK_REQ) */\r
+ uint32_t : 6;\r
+ __I uint32_t EC_REG_BANK_CLK_REQ: 1; /*!< EC_REG_BANK Clock Required (EC_REG_BANK_CLK_REQ) */\r
+ __I uint32_t TIMER16_0_CLK_REQ: 1; /*!< TIMER16_0 Clock Required (TIMER16_0_CLK_REQ) */\r
+ __I uint32_t TIMER16_1_CLK_REQ: 1; /*!< TIMER16_1 Clock Required (TIMER16_1_CLK_REQ) */\r
+ } EC_CLK_REQ_STS_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t HOST_SLP_EN; /*!< Host Sleep Enable Register (HOST_SLP_EN) */\r
+ \r
+ struct {\r
+ __IO uint32_t LPC_SLP_EN : 1; /*!< LPC Sleep Enable (LPC_SLP_EN) */\r
+ __IO uint32_t UART_0_SLP_EN: 1; /*!< UART 0 Sleep Enable (UART_0_SLP_EN) */\r
+ uint32_t : 10;\r
+ __IO uint32_t GLBL_CFG_SLP_EN: 1; /*!< GLBL_CFG (GLBL_CFG_SLP_EN) */\r
+ __IO uint32_t ACPI_EC_0_SLP_EN: 1; /*!< ACPI EC 0 Sleep Enable (ACPI_EC_0_SLP_EN) */\r
+ __IO uint32_t ACPI_EC_1_SLP_EN: 1; /*!< ACPI EC 1 Sleep Enable (ACPI_EC_1_SLP_EN) */\r
+ __IO uint32_t ACPI_PM1_SLP_EN: 1; /*!< ACPI PM1 Sleep Enable (ACPI_PM1_SLP_EN) */\r
+ __IO uint32_t KBCEM_SLP_EN: 1; /*!< 8042EM Sleep Enable (8042EM_SLP_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t RTC_SLP_EN : 1; /*!< RTC Sleep Enable (RTC_SLP_EN) */\r
+ } HOST_SLP_EN_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __I uint32_t HOST_CLK_REQ; /*!< Host Clock Required Status Registers */\r
+ \r
+ struct {\r
+ __I uint32_t LPC_CLK_REQ: 1; /*!< LPC Clock Required (LPC_CLK_REQ) */\r
+ __I uint32_t UART_0_CLK_REQ: 1; /*!< UART 0 Clock Required (UART_0_CLK_REQ) */\r
+ uint32_t : 10;\r
+ __I uint32_t GLBL_CFG_CLK_REQ: 1; /*!< GLBL_CFG Clock Required (GLBL_CFG_CLK_REQ) */\r
+ __I uint32_t ACPI_EC_0_CLK_REQ: 1; /*!< ACPI EC 0 Clock Required (ACPI_EC_0_CLK_REQ) */\r
+ __I uint32_t ACPI_EC_1_CLK_REQ: 1; /*!< ACPI EC 1 Clock Required (ACPI_EC_1_CLK_REQ) */\r
+ __I uint32_t ACPI_PM1_CLK_REQ: 1; /*!< ACPI PM1 Clock Required (ACPI_PM1_CLK_REQ) */\r
+ __I uint32_t KBCEM_CLK_REQ: 1; /*!< 8042EM Clock Required (8042EM_CLK_REQ) */\r
+ uint32_t : 1;\r
+ __I uint32_t RTC_CLK_REQ: 1; /*!< RTC Clock Required (RTC_CLK_REQ) */\r
+ } HOST_CLK_REQ_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t SYS_SLP_CNTRL; /*!< System Sleep Control Register */\r
+ \r
+ struct {\r
+ __IO uint32_t ROSC_PD : 1; /*!< Ring oscillator power down (ROSC_PD) */\r
+ __IO uint32_t ROSC_GATE : 1; /*!< Ring oscillator output gate (ROSC_GATE) */\r
+ __IO uint32_t REGULATOR_STDBY: 1; /*!< Core regulator standby */\r
+ } SYS_SLP_CNTRL_b; /*!< BitSize */\r
+ };\r
+ __I uint32_t RESERVED;\r
+ __IO uint32_t PROC_CLK_CNTRL; /*!< Processor Clock Control Register (PROC_CLK_CNTRL) [7:0] Processor\r
+ Clock Divide Value (PROC_DIV)\r
+ 1: divide 48 MHz Ring Oscillator by 1.\r
+ 4: divide 48 MHz Ring Oscillator by 4.(default)\r
+ 16: divide 48 MHz Ring Oscillator by 16.\r
+ 48: divide 48 MHz Ring Oscillator by 48.\r
+ No other values are supported \r
+ --------------------------------------------------------- */\r
+ \r
+ union {\r
+ __IO uint32_t EC_SLP_EN2; /*!< EC Sleep Enable 2 Register (EC_SLP_EN2) */\r
+ \r
+ struct {\r
+ uint32_t : 3;\r
+ __IO uint32_t ADC_SLP_EN : 1; /*!< ADC Sleep Enable (ADC_SLP_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t PS2_0_SLP_EN: 1; /*!< PS2_0 Sleep Enable (PS2_0_SLP_EN) */\r
+ __IO uint32_t PS2_1_SLP_EN: 1; /*!< PS2_1 Sleep Enable (PS2_1_SLP_EN) */\r
+ __IO uint32_t PS2_2_SLP_EN: 1; /*!< PS2_2 Sleep Enable (PS2_2_SLP_EN) */\r
+ __IO uint32_t PS2_3_SLP_EN: 1; /*!< PS2_3 Sleep Enable (PS2_3_SLP_EN) */\r
+ __IO uint32_t SPI0_SLP_EN: 1; /*!< SPI0 Sleep Enable (SPI0_SLP_EN) */\r
+ __IO uint32_t HTIMER_SLP_EN: 1; /*!< HTIMER Sleep Enable (HTIMER_SLP_EN) */\r
+ __IO uint32_t KEYSCAN_SLP_EN: 1; /*!< KEYSCAN Sleep Enable (KEYSCAN_SLP_EN) */\r
+ __IO uint32_t RPMPWM_SLP_EN: 1; /*!< RPM-PWM Sleep Enable (RPMPWM_SLP_EN) */\r
+ __IO uint32_t SMB1_SLP_EN: 1; /*!< SMB1 Sleep Enable (SMB1_SLP_EN) */\r
+ __IO uint32_t SMB2_SLP_EN: 1; /*!< SMB2 Sleep Enable (SMB2_SLP_EN) */\r
+ __IO uint32_t SMB3_SLP_EN: 1; /*!< SMB3 Sleep Enable (SMB3_SLP_EN) */\r
+ __IO uint32_t LED0_SLP_EN: 1; /*!< LED0 Sleep Enable (LED0_SLP_EN) */\r
+ __IO uint32_t LED1_SLP_EN: 1; /*!< LED1 Sleep Enable (LED1_SLP_EN) */\r
+ __IO uint32_t LED2_SLP_EN: 1; /*!< LED2 Sleep Enable (LED2_SLP_EN) */\r
+ __IO uint32_t BCM_SLP_EN : 1; /*!< BCM Sleep Enable (BCM_SLP_EN) */\r
+ __IO uint32_t SPI1_SLP_EN: 1; /*!< SPI1 Sleep Enable (SPI1_SLP_EN) */\r
+ __IO uint32_t TIMER16_2_SLP_EN: 1; /*!< TIMER16_2_Sleep Enable (TIMER16_2_SLP_EN) */\r
+ __IO uint32_t TIMER16_3_SLP_EN: 1; /*!< TIMER16_3 Sleep Enable (TIMER16_3_SLP_EN) */\r
+ __IO uint32_t TIMER32_0_SLP_EN: 1; /*!< TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN) */\r
+ __IO uint32_t TIMER32_1_SLP_EN: 1; /*!< TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN) */\r
+ __IO uint32_t LED3_SLP_EN: 1; /*!< LED3 Sleep Enable (LED3_SLP_EN) */\r
+ } EC_SLP_EN2_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __I uint32_t EC_CLK_REQ2_STS; /*!< EC Clock Required 2 Status Register */\r
+ \r
+ struct {\r
+ uint32_t : 3;\r
+ __I uint32_t ADC_CLK_REQ: 1; /*!< ADC Clock Required (ADC_CLK_REQ) */\r
+ uint32_t : 1;\r
+ __I uint32_t PS2_0_SLP_CLK_REQ: 1; /*!< PS2_0 Clock Required (PS2_0_SLP_CLK_REQ) */\r
+ __I uint32_t PS2_1_SLP_CLK_REQ: 1; /*!< PS2_1 Clock Required (PS2_1_SLP_CLK_REQ) */\r
+ __I uint32_t PS2_2_SLP_CLK_REQ: 1; /*!< PS2_2 Clock Required (PS2_2_SLP_CLK_REQ) */\r
+ __I uint32_t PS2_3_SLP_CLK_REQ: 1; /*!< PS2_3 Clock Required (PS2_3_SLP_CLK_REQ) */\r
+ __I uint32_t SPI0_SLP_CLK_REQ: 1; /*!< SPI0 Clock Required (SPI0_SLP_CLK_REQ) */\r
+ __I uint32_t HTIMER_SLP_CLK_REQ: 1; /*!< HTIMER Clock Required (HTIMER_SLP_CLK_REQ) */\r
+ __I uint32_t KEYSCAN_SLP_CLK_REQ: 1; /*!< KEYSCAN Clock Required (KEYSCAN_SLP_CLK_REQ) */\r
+ __I uint32_t RPMPWM_SLP_CLK_REQ: 1; /*!< RPM-PWM Clock Required (RPMPWM_SLP_CLK_REQ) */\r
+ __I uint32_t SMB1_SLP_CLK_REQ: 1; /*!< SMB1 Clock Required (SMB1_SLP_CLK_REQ) */\r
+ __I uint32_t SMB2_SLP_CLK_REQ: 1; /*!< SMB2 Clock Required (SMB2_SLP_CLK_REQ) */\r
+ __I uint32_t SMB3_SLP_CLK_REQ: 1; /*!< SMB3 Clock Required (SMB3_SLP_CLK_REQ) */\r
+ __I uint32_t LED0_SLP_CLK_REQ: 1; /*!< LED0 Clock Required (LED0_SLP_CLK_REQ) */\r
+ __I uint32_t LED1_SLP_CLK_REQ: 1; /*!< LED1 Clock Required (LED1_SLP_CLK_REQ) */\r
+ __I uint32_t LED2_SLP_CLK_REQ: 1; /*!< LED2 Clock Required (LED2_SLP_CLK_REQ) */\r
+ __I uint32_t BCM_SLP_CLK_REQ: 1; /*!< BCM Clock Required (BCM_SLP_CLK_REQ) */\r
+ __I uint32_t SPI1_SLP_CLK_REQ: 1; /*!< SPI1 Clock Required (SPI1_SLP_CLK_REQ) */\r
+ __I uint32_t TIMER16_2_SLP_CLK_REQ: 1; /*!< TIMER16_2_Clock Required (TIMER16_2_SLP_CLK_REQ) */\r
+ __I uint32_t TIMER16_3_SLP_CLK_REQ: 1; /*!< TIMER16_3 Clock Required (TIMER16_3_SLP_CLK_REQ) */\r
+ __I uint32_t TIMER32_0_SLP_CLK_REQ: 1; /*!< TIMER32_0 Clock Required (TIMER32_0_SLP_CLK_REQ) */\r
+ __I uint32_t TIMER32_1_SLP_CLK_REQ: 1; /*!< TIMER32_1 Clock Required (TIMER32_1_SLP_CLK_REQ) */\r
+ __I uint32_t LED3_SLP_CLK_REQ: 1; /*!< LED3 Clock Required (LED3_SLP_CLK_REQ) */\r
+ } EC_CLK_REQ2_STS_b; /*!< BitSize */\r
+ };\r
+ __IO uint32_t SLOW_CLK_CNTRL; /*!< Slow Clock Control Register (SLOW_CLK_CNTRL) Slow Clock (100\r
+ kHz) Divide Value (slow_div) Configures the 100kHz_Clk.\r
+ 0: Clock off \r
+ n: divide by n.\r
+ Note: The default setting is for 100 kHz. \r
+ --------------------------------------------------------- */\r
+ \r
+ union {\r
+ __I uint32_t CHIP_OSC_ID; /*!< Oscillator ID Register (CHIP_OSC_ID) */\r
+ \r
+ struct {\r
+ uint32_t : 8;\r
+ __I uint32_t OSC_LOCK : 1; /*!< OSC_LOCK (OSC_LOCK) */\r
+ } CHIP_OSC_ID_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t CHIP_PWR_RST_STS; /*!< PCR chip sub-system power reset status */\r
+ \r
+ struct {\r
+ uint32_t : 2;\r
+ __I uint32_t VCC_nRST : 1; /*!< 0=active, 1=not active (PWRGD asserted). */\r
+ __I uint32_t SIO_nRST : 1; /*!< nSIO_RESET. 0=active, 1=not active. */\r
+ uint32_t : 1;\r
+ __IO uint32_t VBAT_RST : 1; /*!< VBAT: 0=No reset, 1=reset occurred.(R/WC) */\r
+ __IO uint32_t VCC1_RST : 1; /*!< VCC1: 0=No reset, 1=reset occurred.(R/WC) */\r
+ uint32_t : 3;\r
+ __I uint32_t _32K_ACTIVE: 1; /*!< 32K_ACTIVE (32K_ACTIVE) */\r
+ __I uint32_t PCICLK_ACTIVE: 1; /*!< PCICLK_ACTIVE (PCICLK_ACTIVE) */\r
+ } CHIP_PWR_RST_STS_b; /*!< BitSize */\r
+ };\r
+ __IO uint32_t CHIP_RST_EN; /*!< Chip Reset Enable (MCHP Reserved) */\r
+ \r
+ union {\r
+ __IO uint32_t HOST_RST_EN; /*!< Host Reset Enable Register */\r
+ \r
+ struct {\r
+ __IO uint32_t LPC_RST_EN : 1; /*!< LPC Reset Enable (LPC_RST_EN) */\r
+ __IO uint32_t UART_0_RST_EN: 1; /*!< UART 0 Reset Enable */\r
+ uint32_t : 10;\r
+ __IO uint32_t GLBL_CFG_RST_EN: 1; /*!< GLBL_CFG Reset Enable */\r
+ __IO uint32_t ACPI_EC_0_RST_EN: 1; /*!< ACPI EC 0 Reset Enable */\r
+ __IO uint32_t ACPI_EC_1_RST_EN: 1; /*!< ACPI EC 1 Reset Enable */\r
+ __IO uint32_t ACPI_PM1_RST_EN: 1; /*!< ACPI PM1 Reset Enable */\r
+ __IO uint32_t KBCEM_RST_EN: 1; /*!< 8042EM Reset Enable */\r
+ uint32_t : 1;\r
+ __IO uint32_t RTC_RST_EN : 1; /*!< RTC Reset Enable (RTC_RST_EN) */\r
+ } HOST_RST_EN_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t EC_RST_EN; /*!< EC Reset Enable Register */\r
+ \r
+ struct {\r
+ __IO uint32_t INT_RST_EN : 1; /*!< INT Reset Enable (INT_RST_EN) */\r
+ __IO uint32_t PECI_RST_EN: 1; /*!< PECI Reset Enable (PECI_RST_EN) */\r
+ __IO uint32_t TACH0_RST_EN: 1; /*!< TACH0 Reset Enable (TACH0_RST_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t PWM0_RST_EN: 1; /*!< PWM0 Reset Enable (PWM0_RST_EN) */\r
+ __IO uint32_t PMC_RST_EN : 1; /*!< PMC Reset Enable (PMC_RST_EN) */\r
+ __IO uint32_t DMA_RST_EN : 1; /*!< DMA Reset Enable (DMA_RST_EN) */\r
+ __IO uint32_t TFDP_RST_EN: 1; /*!< TFDP Reset Enable (TFDP_RST_EN) */\r
+ __IO uint32_t PROCESSOR_RST_EN: 1; /*!< PROCESSOR Sleep Enable (PROCESSOR_RST_EN) */\r
+ __IO uint32_t WDT_RST_EN : 1; /*!< WDT Reset Enable (WDT_RST_EN) */\r
+ __IO uint32_t SMB0_RST_EN: 1; /*!< SMB0 Reset Enable (SMB0_RST_EN) */\r
+ __IO uint32_t TACH1_RST_EN: 1; /*!< TACH1 Reset Enable (TACH1_RST_EN) */\r
+ uint32_t : 8;\r
+ __IO uint32_t PWM1_RST_EN: 1; /*!< PWM1 Reset Enable (PWM1_RST_EN) */\r
+ __IO uint32_t PWM2_RST_EN: 1; /*!< PWM2 Reset Enable (PWM2_RST_EN) */\r
+ __IO uint32_t PWM3_RST_EN: 1; /*!< PWM3 Reset Enable (PWM3_RST_EN) */\r
+ uint32_t : 6;\r
+ __IO uint32_t EC_REG_BANK_RST_EN: 1; /*!< EC_REG_BANK Reset Enable (EC_REG_BANK_RST_EN) */\r
+ __IO uint32_t TIMER16_0_RST_EN: 1; /*!< TIMER16_0 Reset Enable (TIMER16_0_RST_EN) */\r
+ __IO uint32_t TIMER16_1_RST_EN: 1; /*!< TIMER16_1 Reset Enable (TIMER16_1_RST_EN) */\r
+ } EC_RST_EN_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t EC_RST_EN2; /*!< EC Reset Enable 2 Register */\r
+ \r
+ struct {\r
+ uint32_t : 3;\r
+ __IO uint32_t ADC_RST_EN : 1; /*!< ADC Reset Enable (ADC_RST_EN) */\r
+ uint32_t : 1;\r
+ __IO uint32_t PS2_0_RST_EN: 1; /*!< PS2_0 Reset Enable (PS2_0_RST_EN) */\r
+ __IO uint32_t PS2_1_RST_EN: 1; /*!< PS2_1 Reset Enable (PS2_1_RST_EN) */\r
+ __IO uint32_t PS2_2_RST_EN: 1; /*!< PS2_2 Reset Enable (PS2_2_RST_EN) */\r
+ __IO uint32_t PS2_3_RST_EN: 1; /*!< PS2_3 Reset Enable (PS2_3_RST_EN) */\r
+ __IO uint32_t SPI0_SLP_EN: 1; /*!< SPI0 Reset Enable (SPI0_SLP_EN) */\r
+ __IO uint32_t HTIMER_RST_EN: 1; /*!< HTIMER Reset Enable (HTIMER_RST_EN) */\r
+ __IO uint32_t KEYSCAN_RST_EN: 1; /*!< KEYSCAN Reset Enable (KEYSCAN_RST_EN) */\r
+ __IO uint32_t RPMPWM_RST_EN: 1; /*!< RPM-PWM Reset Enable (RPMPWM_RST_EN) */\r
+ __IO uint32_t SMB1_RST_EN: 1; /*!< SMB1 Reset Enable (SMB1_RST_EN) */\r
+ __IO uint32_t SMB2_RST_EN: 1; /*!< SMB2 Reset Enable (SMB2_RST_EN) */\r
+ __IO uint32_t SMB3_RST_EN: 1; /*!< SMB3 Reset Enable (SMB3_RST_EN) */\r
+ __IO uint32_t LED0_RST_EN: 1; /*!< LED0 Reset Enable (LED0_RST_EN) */\r
+ __IO uint32_t LED1_RST_EN: 1; /*!< LED1 Reset Enable (LED1_RST_EN) */\r
+ __IO uint32_t LED2_RST_EN: 1; /*!< LED2 Reset Enable (LED2_RST_EN) */\r
+ __IO uint32_t BCM_RST_EN : 1; /*!< BCM Reset Enable (BCM_RST_EN) */\r
+ __IO uint32_t SPI1_RST_EN: 1; /*!< SPI1 Reset Enable (SPI1_RST_EN) */\r
+ __IO uint32_t TIMER16_2_RST_EN: 1; /*!< TIMER16_2_Reset Enable (TIMER16_2_RST_EN) */\r
+ __IO uint32_t TIMER16_3_RST_EN: 1; /*!< TIMER16_3 Reset Enable (TIMER16_3_RST_EN) */\r
+ __IO uint32_t TIMER32_0_RST_EN: 1; /*!< TIMER32_0 Reset Enable (TIMER32_0_RST_EN) */\r
+ __IO uint32_t TIMER32_1_RST_EN: 1; /*!< TIMER32_1 Reset Enable (TIMER32_1_RST_EN) */\r
+ __IO uint32_t LED3_RST_EN: 1; /*!< LED3 Reset Enable (LED3_RST_EN) */\r
+ } EC_RST_EN2_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t PWR_RST_CTRL; /*!< Power Reset Control (PWR_RST_CTRL) Register */\r
+ \r
+ struct {\r
+ __IO uint32_t IRESET_OUT : 1; /*!< iRESET_OUT (IRESET_OUT) */\r
+ } PWR_RST_CTRL_b; /*!< BitSize */\r
+ };\r
+} PCR_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ VBAT ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The VBAT Register Bank block is a block implemented for aggregating miscellaneous battery-backed registers \r
+ required the host and by the Embedded Controller (EC) Subsystem that are not unique to a block implemented in the EC subsystem.\r
+ The VBAT Powered RAM provides a 64 Byte Random Accessed Memory that is operational while the main power rail is operational, \r
+ and will retain its values powered by battery power while the main rail is unpowered. (VBAT)\r
+ */\r
+\r
+typedef struct { /*!< VBAT Structure */\r
+ \r
+ union {\r
+ __IO uint8_t PFR_STS; /*!< Power-Fail and Reset Status Register */\r
+ \r
+ struct {\r
+ __I uint8_t DET32K_IN : 1; /*!< XTAL[1:2] 0=No clock, 1= Clock detected */\r
+ uint8_t : 4;\r
+ __IO uint8_t WDT : 1; /*!< 1=Watch-Dog Timer Forced Reset (R/WC). */\r
+ uint8_t : 1;\r
+ __IO uint8_t VBAT_RST : 1; /*!< 1=VBAT_POR is detected.(R/WC) */\r
+ } PFR_STS_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED[7];\r
+ \r
+ union {\r
+ __IO uint32_t CLOCK_EN; /*!< CLOCK ENABLE Control */\r
+ \r
+ struct {\r
+ __IO uint32_t XOSEL : 1; /*!< 32KHz, 1=single-ended, 0=crystal (default). */\r
+ __IO uint32_t _32K_EN : 1; /*!< 1=32K_ON, 0=OFF (VBAT_POR default) */\r
+ } CLOCK_EN_b; /*!< BitSize */\r
+ };\r
+} VBAT_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ LPC ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Section 5.10, "EC-Only Registers"and Section 5.11, "Runtime Registers". (LPC)\r
+ */\r
+\r
+typedef struct { /*!< LPC Structure */\r
+ __IO uint8_t INDEX; /*!< A pointer to a Configuration Reg. Address. */\r
+ __IO uint8_t DATA_REG; /*!< To rd/wt data with the INDEX Register. */\r
+ __I uint16_t RESERVED[129];\r
+ \r
+ union {\r
+ __I uint32_t BUS_MONITOR; /*!< LPC BUS MONITOR REGISTER */\r
+ \r
+ struct {\r
+ uint32_t : 1;\r
+ __I uint32_t LRESET_STATUS: 1; /*!< Reflects the inverse state of LRESET# pin. */\r
+ } BUS_MONITOR_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t HOST_BUS_ERROR; /*!< Host Bus Error Register */\r
+ \r
+ struct {\r
+ __IO uint32_t LPC_ERR : 1; /*!< A BAR conflict or an internal bus error. (R/WC) */\r
+ __IO uint32_t EN_ERR : 1; /*!< Internal bus errors. (R/WC) */\r
+ __IO uint32_t BAR_ERR : 1; /*!< a BAR conflict occurs on an LPC address. (R/WC) */\r
+ __IO uint32_t RUNTIME_ERR: 1; /*!< A BAR is misconfigured. (R/WC) */\r
+ __IO uint32_t CONFIG_ERR : 1; /*!< LPC Config access causes a bus error.(R/WC) */\r
+ __IO uint32_t DMA_ERR : 1; /*!< LPC DMA access causes a bus error. (R/WC) */\r
+ uint32_t : 2;\r
+ __I uint32_t ERR_ADDR : 24; /*!< 24-bit internal addr. of LPC transaction */\r
+ } HOST_BUS_ERROR_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t EC_SERIRQ; /*!< the interrupt source of EC SERIRQ */\r
+ \r
+ struct {\r
+ __IO uint32_t EC_IRQ : 1; /*!< interrupt source of a LPC Logical Device */\r
+ } EC_SERIRQ_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t CLK_CTRL; /*!< Controls throughput of LPC transactions. */\r
+ \r
+ struct {\r
+ __IO uint32_t CR : 2; /*!< controls ring oscillator to be shut down. */\r
+ __IO uint32_t HANDSHAKE : 1; /*!< controls throughput of LPC transactions. */\r
+ } CLK_CTRL_b; /*!< BitSize */\r
+ };\r
+ __I uint32_t RESERVED1[3];\r
+ __IO uint32_t BAR_INHIBIT; /*!< The BAR for Logical Device i is disabled */\r
+ __I uint32_t RESERVED2[3];\r
+ __IO uint32_t BAR_INIT; /*!< Init value of LPC BAR at offset 60h on nSIO_RESET. */\r
+} LPC_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ LPC_CONFIG ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief LPC Configuration Registers. See Section 5.9 (LPC_CONFIG)\r
+ */\r
+\r
+typedef struct { /*!< LPC_CONFIG Structure */\r
+ __I uint32_t RESERVED[12];\r
+ __IO uint8_t ACTIVATE; /*!< 1=LPC Logical Device is powered/functional */\r
+ __I uint8_t RESERVED1[15];\r
+ \r
+ union {\r
+ __IO uint8_t SIRQ[16]; /*!< 16 SIRQ channels */\r
+ \r
+ struct {\r
+ __IO uint8_t FRAME : 6; /*!< Six bits select the Logical Device. */\r
+ __IO uint8_t DEVICE : 1; /*!< Set to 0 in order to enable a SERIRQ. */\r
+ __IO uint8_t SELECT : 1; /*!< 1: 1st LD's intr is selected,0: 2nd intr. */\r
+ } SIRQ_b[16]; /*!< BitSize */\r
+ };\r
+ __I uint32_t RESERVED2[4];\r
+ \r
+ union {\r
+ __IO uint32_t LPC_BAR; /*!< LPC Interface BAR Register */\r
+ \r
+ struct {\r
+ __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
+ __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
+ __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
+ __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
+ __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
+ } LPC_BAR_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t EM_BAR; /*!< EM Interface 0 BAR */\r
+ \r
+ struct {\r
+ __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
+ __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
+ __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
+ __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
+ __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
+ } EM_BAR_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t UART_BAR; /*!< UART 0 BAR Register */\r
+ \r
+ struct {\r
+ __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
+ __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
+ __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
+ __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
+ __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
+ } UART_BAR_b; /*!< BitSize */\r
+ };\r
+ __I uint32_t RESERVED3[3];\r
+ \r
+ union {\r
+ __IO uint32_t KBC_BAR; /*!< Keyboard Controller (8042) BAR */\r
+ \r
+ struct {\r
+ __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
+ __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
+ __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
+ __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
+ __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
+ } KBC_BAR_b; /*!< BitSize */\r
+ };\r
+ __I uint32_t RESERVED4[3];\r
+ \r
+ union {\r
+ __IO uint32_t EC0_BAR; /*!< ACPI EC Interface 0 BAR */\r
+ \r
+ struct {\r
+ __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
+ __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
+ __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
+ __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
+ __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
+ } EC0_BAR_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t EC1_BAR; /*!< ACPI EC Interface 1 BAR */\r
+ \r
+ struct {\r
+ __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
+ __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
+ __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
+ __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
+ __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
+ } EC1_BAR_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t PM1_BAR; /*!< ACPI PM1 Interface BAR */\r
+ \r
+ struct {\r
+ __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
+ __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
+ __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
+ __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
+ __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
+ } PM1_BAR_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t LGC_BAR; /*!< Legacy (GATEA20) Interface BAR */\r
+ \r
+ struct {\r
+ __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
+ __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
+ __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
+ __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
+ __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
+ } LGC_BAR_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t MBX_BAR; /*!< Mailbox Registers Interface BAR */\r
+ \r
+ struct {\r
+ __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
+ __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
+ __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
+ __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
+ __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
+ } MBX_BAR_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t RTC_BAR; /*!< RTC Registers Interface BAR */\r
+ \r
+ struct {\r
+ __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */\r
+ __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */\r
+ __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */\r
+ __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */\r
+ __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */\r
+ } RTC_BAR_b; /*!< BitSize */\r
+ };\r
+ __I uint32_t RESERVED5[8];\r
+ \r
+ union {\r
+ LPC_CONFIG_MEM_BAR_Type MBX_MEM_BAR; /*!< Mailbox Registers I/F Memory BAR */\r
+ LPC_CONFIG_MEM_BAR_Type MEM_BAR; /*!< Mailbox Registers I/F Memory BAR */\r
+ };\r
+ LPC_CONFIG_MEM_BAR_Type EC0_MEM_BAR; /*!< ACPI EC Interface 0 Memory BAR */\r
+ LPC_CONFIG_MEM_BAR_Type EC1_MEM_BAR; /*!< ACPI EC Interface 1 Memory BAR */\r
+ LPC_CONFIG_MEM_BAR_Type EMI_MEM_BAR; /*!< EM Interface 0 Memory BAR */\r
+} LPC_CONFIG_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ GCR ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The Logical Device Configuration registers support motherboard designs in which the resources required \r
+ by their components are known and assigned by the BIOS at POST. (GCR)\r
+ */\r
+\r
+typedef struct { /*!< GCR Structure */\r
+ __I uint8_t RESERVED[7];\r
+ __IO uint8_t LOGICAL_DEVICE_NUMBER; /*!< Selects the current logical device. */\r
+ __I uint32_t RESERVED1[6];\r
+ __I uint8_t DEVICE_ID; /*!< provides device identification. */\r
+ __I uint8_t DEVICE_REVISION; /*!< provides device revision information. */\r
+} GCR_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ EMI ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The Embedded Memory Interface (EMI) provides a standard run-time mechanism for the system host \r
+ to communicate with the Embedded Controller (EC) and other logical components. (EMI)\r
+ */\r
+\r
+typedef struct { /*!< EMI Structure */\r
+ __IO uint8_t HOST_EC_MBX; /*!< Host-to-EC Mailbox Register */\r
+ __IO uint8_t EC_HOST_MBX; /*!< EC-to-Host Mailbox Register (R/WC) */\r
+ \r
+ union {\r
+ __IO uint16_t EC_ADDRESS; /*!< EC Address Access Control Register */\r
+ \r
+ struct {\r
+ __IO uint16_t ACCESS_TYPE: 2; /*!< defines the type of EC Data rd/wt access */\r
+ __IO uint16_t EC_ADDRESS : 13; /*!< defines bits[14:2] of EC_Address [15:0]. */\r
+ __IO uint16_t REGION : 1; /*!< Selector of two segments. */\r
+ } EC_ADDRESS_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t EC_DATA; /*!< EC Data Register */\r
+ __IO uint8_t EC_DATA_BYTE[4]; /*!< EC Data Byte Register */\r
+ };\r
+ \r
+ union {\r
+ __IO uint16_t EC_SWI; /*!< Notification of EC Software Interrupt */\r
+ \r
+ struct {\r
+ __I uint16_t EC_WR : 1; /*!< EC Mailbox Write. */\r
+ __IO uint16_t NOTIFICATION: 15; /*!< EC to notify the host of an event(R/WC) */\r
+ } EC_SWI_b; /*!< BitSize */\r
+ };\r
+ __IO uint16_t EC_SWI_EN; /*!< [15:1] enables generation of Event interrupts */\r
+ __IO uint8_t APPLICATION_ID; /*!< Application ID Register */\r
+ __I uint8_t RESERVED[243];\r
+ __IO uint8_t HOST2EC_MBX; /*!< Host-to-EC Mailbox Register(R/WC) */\r
+ __IO uint8_t EC2HOST_MBX; /*!< EC-to-Host Mailbox Register */\r
+ __I uint16_t RESERVED1;\r
+ __IO uint32_t MEMORY_BASE_ADDRESS_0; /*!< [31:2] defines the beginning of region 0 */\r
+ __IO uint16_t MEMORY_READ_LIMIT_0; /*!< [14:2]Memory Read Limit 0 Register */\r
+ __IO uint16_t MEMORY_WRITE_LIMIT_0; /*!< [14:2] Memory Write Limit 0 Register */\r
+ __IO uint32_t MEMORY_BASE_ADDRESS_1; /*!< [31:2] defines the beginning of region 1 */\r
+ __IO uint16_t MEMORY_READ_LIMIT_1; /*!< [14:2]Memory Read Limit 1 Register */\r
+ __IO uint16_t MEMORY_WRITE_LIMIT_1; /*!< [14:2] Memory Write Limit 1 Register */\r
+ __IO uint16_t EC_SWI_SET; /*!< [15:1] Interrupt Set Register */\r
+ __IO uint16_t EC_SWI_CLR; /*!< [15:1] Host Clear Enable Register */\r
+} EMI_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ ACPI_EC0 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The ACPI Embedded Controller Interface (ACPI-ECI) provides a four byte full duplex data interface \r
+ which is a superset of the standard ACPI Embedded Controller Interface (ACPI-ECI) one byte data interface. The\r
+ ACPI Embedded Controller Interface (ACPI-ECI) defaults to the standard one byte interface. (ACPI_EC0)\r
+ */\r
+\r
+typedef struct { /*!< ACPI_EC0 Structure */\r
+ \r
+ union {\r
+ __IO uint32_t OS_DATA; /*!< ACPI OS Data Register */\r
+ __IO uint8_t OS_DATA_BYTE[4]; /*!< aliased to the OS2EC DATA BYTES[n]. */\r
+ };\r
+ \r
+ union {\r
+ union {\r
+ __I uint8_t OS_STATUS; /*!< aliased to the EC STATUS Register */\r
+ \r
+ struct {\r
+ __I uint8_t OBF : 1; /*!< Output Buffer Full bit */\r
+ __I uint8_t IBF : 1; /*!< Input Buffer Full bit */\r
+ __I uint8_t UD1B : 1; /*!< User Defined */\r
+ __I uint8_t CMD : 1; /*!< OS2EC Data contains a command byte */\r
+ __I uint8_t BURST : 1; /*!< set when the ACPI_EC is in Burst Mode */\r
+ __I uint8_t SCI_EVT : 1; /*!< set when an SCI event is pending */\r
+ __I uint8_t SMI_EVT : 1; /*!< set when an SMI event is pending */\r
+ __I uint8_t UD0B : 1; /*!< User Defined */\r
+ } OS_STATUS_b; /*!< BitSize */\r
+ };\r
+ __O uint8_t OS_COMMAND; /*!< aliased to the OS2EC Data Byte0 */\r
+ };\r
+ __I uint8_t OS_BYTE_CONTROL; /*!< OS Control [0:0] FOUR_BYTE_ACCESS */\r
+ __I uint16_t RESERVED[125];\r
+ \r
+ union {\r
+ __IO uint32_t EC2OS_DATA; /*!< EC2OS Data */\r
+ __IO uint8_t EC2OS_DATA_BYTE[4]; /*!< EC2OS Data Bytes */\r
+ };\r
+ \r
+ union {\r
+ __IO uint8_t EC_STATUS; /*!< EC STATUS */\r
+ \r
+ struct {\r
+ __I uint8_t OBF : 1; /*!< Output Buffer Full bit */\r
+ __I uint8_t IBF : 1; /*!< Input Buffer Full bit */\r
+ __I uint8_t UD1A : 1; /*!< User Defined */\r
+ __I uint8_t CMD : 1; /*!< OS2EC Data contains a command byte */\r
+ __IO uint8_t BURST : 1; /*!< set when the ACPI_EC is in Burst Mode */\r
+ __IO uint8_t SCI_EVT : 1; /*!< set when an SCI event is pending */\r
+ __IO uint8_t SMI_EVT : 1; /*!< set when an SMI event is pending */\r
+ __IO uint8_t UD0A : 1; /*!< User Defined */\r
+ } EC_STATUS_b; /*!< BitSize */\r
+ };\r
+ __IO uint8_t EC_BYTE_CONTROL; /*!< OS Control [0:0] FOUR_BYTE_ACCESS */\r
+ __I uint16_t RESERVED1;\r
+ \r
+ union {\r
+ __IO uint32_t OS2EC_DATA; /*!< OS2EC Data EC-Register */\r
+ __IO uint8_t OS2EC_DATA_BYTE[4]; /*!< OS2EC Data Bytes */\r
+ };\r
+} ACPI_EC0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ KBC ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The CEC1302 keyboard controller uses the EC to produce a superset of the\r
+ features provided by the industry-standard 8042 keyboard controller. The 8042 Emulated\r
+ Keyboard Controller is a Host/EC Message Interface with hardware assists to emulate 8042\r
+ behavior and provide Legacy GATEA20 support. (KBC)\r
+ */\r
+\r
+typedef struct { /*!< KBC Structure */\r
+ \r
+ union {\r
+ __O uint8_t WT_PORT60_DATA; /*!< Host_EC Data Register (=Host Write 60h) */\r
+ __I uint8_t RD_PORT60_DATA; /*!< EC_Host Data/Aux Register (=Host Read 60h) */\r
+ };\r
+ __I uint8_t RESERVED[3];\r
+ \r
+ union {\r
+ union {\r
+ __I uint8_t RD_PORT64_STATUS; /*!< Keyboard Status Register (=Host Read 64h) */\r
+ \r
+ struct {\r
+ __I uint8_t OBF : 1; /*!< Output Buffer Full. */\r
+ __I uint8_t IBF : 1; /*!< Input Buffer Full. */\r
+ __I uint8_t UD0 : 1; /*!< User-defined data. */\r
+ __I uint8_t CMDnDATA : 1; /*!< data register contains data(0) or command(1) */\r
+ __I uint8_t UD1 : 1; /*!< User-defined data. */\r
+ __I uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */\r
+ __I uint8_t UD2 : 2; /*!< User-defined data. */\r
+ } RD_PORT64_STATUS_b; /*!< BitSize */\r
+ };\r
+ __O uint8_t WT_PORT64_CMD; /*!< Host_EC Command Register (=Host Write 64h) */\r
+ };\r
+ __I uint8_t RESERVED1[251];\r
+ \r
+ union {\r
+ __O uint8_t EC_DATA; /*!< EC2Host Data Register */\r
+ __I uint8_t HOST2EC_DATA; /*!< Host2EC Data/Cmd Register */\r
+ };\r
+ __I uint8_t RESERVED2[3];\r
+ \r
+ union {\r
+ __IO uint8_t STATUS; /*!< EC KEYBOARD STATUS REGISTER */\r
+ \r
+ struct {\r
+ __I uint8_t OBF : 1; /*!< Output Buffer Full. */\r
+ __I uint8_t IBF : 1; /*!< Input Buffer Full. */\r
+ __IO uint8_t UD0 : 1; /*!< User-defined data. */\r
+ __I uint8_t CMDnDATA : 1; /*!< data register contains data(0) or command(1) */\r
+ __IO uint8_t UD1 : 1; /*!< User-defined data. */\r
+ __IO uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */\r
+ __IO uint8_t UD2 : 2; /*!< User-defined data. */\r
+ } STATUS_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED3[3];\r
+ \r
+ union {\r
+ __IO uint8_t CONTROL; /*!< Keyboard Control Register */\r
+ \r
+ struct {\r
+ __IO uint8_t UD3 : 1; /*!< User-defined data. */\r
+ __IO uint8_t SAEN : 1; /*!< Software-assist enable. */\r
+ __IO uint8_t PCOBFEN : 1; /*!< 1=write to PCOBF, 0=writes to EC Data Reg. */\r
+ __IO uint8_t UD4 : 2; /*!< User-defined data. */\r
+ __IO uint8_t OBFEN : 1; /*!< 1=KIRQ is driven by PCOBF and MIRQ */\r
+ __IO uint8_t UD5 : 1; /*!< User-defined data. */\r
+ __IO uint8_t AUXH : 1; /*!< AUX in Hardware. */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED4[3];\r
+ __O uint8_t AUX_DATA; /*!< EC_Host Aux Register */\r
+ __I uint8_t RESERVED5[7];\r
+ __IO uint8_t PCOBF; /*!< [0:0] PCOBF Register */\r
+ __I uint8_t RESERVED6[539];\r
+ __IO uint8_t ACTIVATE; /*!< [0:0] 1=8042 I/F is powered/functional */\r
+} KBC_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PORT92 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The registers listed in the Configuration Register Summary table are for a \r
+ single instance of the Legacy Port92 and GATEA20 logic. (PORT92)\r
+ */\r
+\r
+typedef struct { /*!< PORT92 Structure */\r
+ \r
+ union {\r
+ __IO uint8_t PORT92; /*!< Support GATE_A20 CPU_RESET control */\r
+ \r
+ struct {\r
+ __IO uint8_t ALT_CPU_RESET: 1; /*!< provides to generate a CPU_RESET pulse. */\r
+ __IO uint8_t ALT_GATE_A20: 1; /*!< provides system to control GATEA20 pin. */\r
+ } PORT92_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED[255];\r
+ __IO uint8_t GATEA20; /*!< [0:0] 0=GATEA20 output low, 1=outputn high */\r
+ __I uint8_t RESERVED1[7];\r
+ __O uint8_t SETGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */\r
+ __I uint8_t RESERVED2[3];\r
+ __IO uint8_t RSTGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */\r
+ __I uint8_t RESERVED3[547];\r
+ __IO uint8_t PORT92_ENABLE; /*!< [0:0] 1= Port92h Register is enabled. */\r
+} PORT92_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ MBX ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The Mailbox provides a standard run-time mechanism for the host to\r
+ communicate with the Embedded Controller (EC) (MBX)\r
+ */\r
+\r
+typedef struct { /*!< MBX Structure */\r
+ __IO uint8_t INDEX; /*!< MBX_Index Register */\r
+ __IO uint8_t DATA_REG; /*!< MBX_Data_Register */\r
+ __I uint16_t RESERVED[127];\r
+ __IO uint8_t HOST_TO_EC; /*!< HOST-to-EC Mailbox Register */\r
+ __I uint8_t RESERVED1[3];\r
+ __IO uint8_t EC_TO_HOST; /*!< EC-to-Host Mailbox Register */\r
+ __I uint8_t RESERVED2[3];\r
+ \r
+ union {\r
+ __IO uint8_t SMI_SOURCE; /*!< SMI Interrupt Source Register */\r
+ \r
+ struct {\r
+ __I uint8_t EC_WR : 1; /*!< EC Mailbox Write (flag). */\r
+ __IO uint8_t EC_SMI : 7; /*!< EC Software Interrupt source control */\r
+ } SMI_SOURCE_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED3[3];\r
+ \r
+ union {\r
+ __IO uint8_t SMI_MASK; /*!< SMI Interrupt Mask Register */\r
+ \r
+ struct {\r
+ __IO uint8_t EC_WR_EN : 1; /*!< EC Mailbox Write Interrupt Enable. */\r
+ __IO uint8_t EC_SMI_EN : 7; /*!< EC Software Interrupt Enable. */\r
+ } SMI_MASK_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED4[3];\r
+ __IO uint8_t REG[42]; /*!< Mailbox Register */\r
+} MBX_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PM1 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The CEC1302 implements the ACPI fixed registers but includes only those bits that apply to the power\r
+ button sleep button and RTC alarm events. The ACPI WAK_STS, SLP_TYP, and SLP_EN bits are also supported. (PM1)\r
+ */\r
+\r
+typedef struct { /*!< PM1 Structure */\r
+ __I uint8_t RESERVED;\r
+ \r
+ union {\r
+ __IO uint8_t STS2; /*!< PM1 Status 2 */\r
+ \r
+ struct {\r
+ __IO uint8_t PWRBTN_STS : 1; /*!< simulate a Power button status (R/WC) */\r
+ __IO uint8_t SLPBTN_STS : 1; /*!< simulate a Sleep button status (R/WC) */\r
+ __IO uint8_t RTC_STS : 1; /*!< simulate a RTC status. (R/WC) */\r
+ __IO uint8_t PWRBTNOR_STS: 1; /*!< simulate a Power button override status(R/WC) */\r
+ uint8_t : 3;\r
+ __IO uint8_t WAK_STS : 1; /*!< Host writing a one to this bit. (R/WC) */\r
+ } STS2_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED1;\r
+ \r
+ union {\r
+ __IO uint8_t EN2; /*!< PM1 Enable 2 */\r
+ \r
+ struct {\r
+ __IO uint8_t PWRBTN_EN : 1; /*!< Controlled by Host. read by the EC. */\r
+ __IO uint8_t SLPBTN_EN : 1; /*!< Controlled by Host. read by the EC. */\r
+ __IO uint8_t RTC_EN : 1; /*!< Controlled by Host. read by the EC. */\r
+ } EN2_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED2;\r
+ \r
+ union {\r
+ __IO uint8_t CTRL2; /*!< PM1 Control 2 */\r
+ \r
+ struct {\r
+ uint8_t : 1;\r
+ __IO uint8_t PWRBTNOR_EN: 1; /*!< Controlled by Host. read by the EC. */\r
+ __IO uint8_t SLP_TYP : 3; /*!< Controlled by Host. read by the EC. */\r
+ __IO uint8_t SLP_EN : 1; /*!< Host Wt 1 to set, EC wt 1 to Clr */\r
+ } CTRL2_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED3[251];\r
+ \r
+ union {\r
+ __IO uint8_t STS_2; /*!< PM1 Status 2 */\r
+ \r
+ struct {\r
+ __IO uint8_t PWRBTN_STS : 1; /*!< simulate a Power button status (R/WC) */\r
+ __IO uint8_t SLPBTN_STS : 1; /*!< simulate a Sleep button status (R/WC) */\r
+ __IO uint8_t RTC_STS : 1; /*!< simulate a RTC status. (R/WC) */\r
+ __IO uint8_t PWRBTNOR_STS: 1; /*!< simulate a Power button override status(R/WC) */\r
+ uint8_t : 3;\r
+ __IO uint8_t WAK_STS : 1; /*!< Host writing a one to this bit. (R/WC) */\r
+ } STS_2_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED4;\r
+ \r
+ union {\r
+ __IO uint8_t EN_2; /*!< PM1 Enable 2 */\r
+ \r
+ struct {\r
+ __IO uint8_t PWRBTN_EN : 1; /*!< Controlled by Host. read by the EC. */\r
+ __IO uint8_t SLPBTN_EN : 1; /*!< Controlled by Host. read by the EC. */\r
+ __IO uint8_t RTC_EN : 1; /*!< Controlled by Host. read by the EC. */\r
+ } EN_2_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED5;\r
+ \r
+ union {\r
+ __IO uint8_t CTRL_2; /*!< PM1 Control 2 */\r
+ \r
+ struct {\r
+ uint8_t : 1;\r
+ __IO uint8_t PWRBTNOR_EN: 1; /*!< Controlled by Host. read by the EC. */\r
+ __IO uint8_t SLP_TYP : 3; /*!< Controlled by Host. read by the EC. */\r
+ __IO uint8_t SLP_EN : 1; /*!< Host Wt 1 to set, EC wt 1 to Clr */\r
+ } CTRL_2_b; /*!< BitSize */\r
+ };\r
+ __I uint16_t RESERVED6[5];\r
+ __IO uint8_t PM_STS; /*!< [0:0]wt 1 interrupt is generated on EC_SCI# */\r
+} PM1_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ UART ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The 16550 UART (Universal Asynchronous Receiver/Transmitter) is a full-function\r
+ Two Pin Serial Port that supports the standard RS-232 Interface. (UART)\r
+ */\r
+\r
+typedef struct { /*!< UART Structure */\r
+ \r
+ union {\r
+ __O uint8_t TX_DATA; /*!< UART Transmit Buffer Register */\r
+ __I uint8_t RX_DATA; /*!< UART Receive Buffer Register */\r
+ __IO uint8_t BAUDRATE_LSB; /*!< Programmable BAUD Rate Generator (LSB) Reg. */\r
+ };\r
+ \r
+ union {\r
+ union {\r
+ __IO uint8_t INT_EN; /*!< UART Interrupt Enable Register */\r
+ \r
+ struct {\r
+ __IO uint8_t ERDAI : 1; /*!< enables Received Data Available Interrupt */\r
+ __IO uint8_t ETHREI : 1; /*!< enables Transmitter Holding Empty Interrupt */\r
+ __IO uint8_t ELSI : 1; /*!< enables Received Line Status Interrupt */\r
+ __IO uint8_t EMSI : 1; /*!< enables the MODEM Status Interrupt */\r
+ } INT_EN_b; /*!< BitSize */\r
+ };\r
+ __IO uint8_t BAUDRATE_MSB; /*!< [6:0]BAUD_RATE_DIVISOR_MSB [7]BAUD_CLK_SEL */\r
+ };\r
+ \r
+ union {\r
+ union {\r
+ __I uint8_t INT_ID; /*!< UART Interrupt Identification Register */\r
+ \r
+ struct {\r
+ __I uint8_t IPEND : 1; /*!< indicate whether an interrupt is pending. */\r
+ __I uint8_t INTID : 3; /*!< highest priority interrupt pending */\r
+ uint8_t : 2;\r
+ __I uint8_t FIFO_EN : 2; /*!< two bits are set when FIFO CONTROL bit 0=1 */\r
+ } INT_ID_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __O uint8_t FIFO_CR; /*!< UART FIFO Control Register */\r
+ \r
+ struct {\r
+ __O uint8_t EXRF : 1; /*!< Enable XMIT and RECV FIFO. */\r
+ __O uint8_t CLEAR_RECV_FIFO: 1; /*!< clears all bytes in RCVR FIFO, resets counter */\r
+ __O uint8_t CLEAR_XMIT_FIFO: 1; /*!< clears all bytes in XMIT FIFO, resets counter */\r
+ __IO uint8_t DMA_MODE_SELECT: 1; /*!< RXRDY,TXRDY pins functions are reserved. */\r
+ uint8_t : 2;\r
+ __IO uint8_t RECV_FIFO_TRIGGER_LEVEL: 2; /*!< set trigger level for RCVR FIFO Intr */\r
+ } FIFO_CR_b; /*!< BitSize */\r
+ };\r
+ };\r
+ \r
+ union {\r
+ __IO uint8_t LINE_CR; /*!< UART Line Control Register */\r
+ \r
+ struct {\r
+ __IO uint8_t WORD_LENGTH: 2; /*!< number of bits in transmitted or received */\r
+ __IO uint8_t STOP_BITS : 1; /*!< number of stop bits in transmitted or received */\r
+ __IO uint8_t ENABLE_PARITY: 1; /*!< Parity Enable bit. */\r
+ __IO uint8_t PARITY_SELECT: 1; /*!< Even Parity Select bit. */\r
+ __IO uint8_t STICK_PARITY: 1; /*!< Stick Parity bit. */\r
+ __IO uint8_t BREAK_CONTROL: 1; /*!< Set Break Control bit */\r
+ __IO uint8_t DLAB : 1; /*!< DLAB Divisor Latch Access Bit (DLAB). */\r
+ } LINE_CR_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint8_t MODEM_CR; /*!< UART Modem Control Register */\r
+ \r
+ struct {\r
+ __IO uint8_t DTR : 1; /*!< Data Terminal Ready (nDTR) output. */\r
+ __IO uint8_t RTS : 1; /*!< Request To Send (nRTS) output. */\r
+ __IO uint8_t OUT1 : 1; /*!< controls the Output 1 (OUT1) bit. */\r
+ __IO uint8_t OUT2 : 1; /*!< enable an UART interrupt. */\r
+ __IO uint8_t LOOPBACK : 1; /*!< provides loopback for diagnostic */\r
+ } MODEM_CR_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __I uint8_t LINE_STS; /*!< UART Line Status Register */\r
+ \r
+ struct {\r
+ __I uint8_t DATA_READY : 1; /*!< 1= data into Rx Buffer Register or FIFO */\r
+ __I uint8_t OVERRUN : 1; /*!< OVERRUN Overrun Error. */\r
+ __I uint8_t PE : 1; /*!< PARITY ERROR Parity Error. */\r
+ __I uint8_t FRAME_ERROR: 1; /*!< FRAME_ERROR Framing Error. */\r
+ __I uint8_t BREAK_INTERRUPT: 1; /*!< BREAK_INTERRUPT Break Interrupt. */\r
+ __I uint8_t TRANSMIT_EMPTY: 1; /*!< Transmitter Holding Register Empty */\r
+ __I uint8_t TRANSMIT_ERROR: 1; /*!< Transmitter Holding/Shift are both empty. */\r
+ __I uint8_t FIFO_ERROR : 1; /*!< FIFO_ERROR */\r
+ } LINE_STS_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __I uint8_t MODEM_STS; /*!< UART Modem Status Register */\r
+ \r
+ struct {\r
+ __I uint8_t CTS : 1; /*!< CTS Delta Clear To Send (DCTS). */\r
+ __I uint8_t DSR : 1; /*!< DSR Delta Data Set Ready (DDSR). */\r
+ __I uint8_t RI : 1; /*!< Trailing Edge of Ring Indicator (TERI). */\r
+ __I uint8_t DCD : 1; /*!< DCD Delta Data Carrier Detect (DDCD). */\r
+ __IO uint8_t nCTS : 1; /*!< complement of Clear To Send (nCTS) input. */\r
+ __IO uint8_t nDSR : 1; /*!< complement of Data Set Ready (nDSR) input. */\r
+ __IO uint8_t nRI : 1; /*!< complement of Ring Indicator (nRI) input. */\r
+ __IO uint8_t nDCD : 1; /*!< complement of Data Carrier Detect (nDCD) input. */\r
+ } MODEM_STS_b; /*!< BitSize */\r
+ };\r
+ __IO uint8_t SCRATCHPAD; /*!< as a scratchpad reg. be used by programmer */\r
+ __I uint32_t RESERVED[202];\r
+ __IO uint8_t ACTIVATE; /*!< [0:0] 1= UART is powered/functional. */\r
+ __I uint8_t RESERVED1[191];\r
+ \r
+ union {\r
+ __IO uint8_t CONFIG; /*!< UART Config Select Register */\r
+ \r
+ struct {\r
+ __IO uint8_t CLK_SRC : 1; /*!< 1=Baud Clock from external clock, 0=internal */\r
+ __IO uint8_t POWER : 1; /*!< 1=reset from nSIO_RESET, 0=VCC1_RESET */\r
+ __IO uint8_t POLARITY : 1; /*!< 1=UART_TX and UART_RX pins are inverted */\r
+ } CONFIG_b; /*!< BitSize */\r
+ };\r
+} UART_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ INTR ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The interrupt generation logic is made of 16 groups of signals, each of which\r
+ consist of a Status register, a Enable register and a Result register. The Status and Enable\r
+ are latched registers. The Result register is a bit by bit AND function of the Source and Enable\r
+ registers. All the bits of the Result register are OR'ed together and AND'ed with the corresponding\r
+ bit in the Block Select register to form the interrupt signal that is routed to the ARM interrupt controller. (INTR)\r
+ */\r
+\r
+typedef struct { /*!< INTR Structure */\r
+ INTR_IRQ_Type IRQ[16]; /*!< DEFINITIONS FOR GIRQi SOURCE/ENABLE/RESULT */\r
+ __I uint32_t RESERVED[48];\r
+ __IO uint32_t BLOCK_ENABLE_SET; /*!< [23:8] IRQ Vector Enable Set */\r
+ __IO uint32_t BLOCK_ENABLE_CLEAR; /*!< [23:8] IRQ Vector Enable Clear */\r
+ __I uint32_t IRQ_VECTOR_STATE; /*!< [23:8] reflects current state of IRQi */\r
+} INTR_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ WDT ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The function of the Watchdog Timer is to provide a mechanism to detect if the\r
+ internal embedded controller has failed. When enabled, the Watchdog Timer (WDT) circuit will generate\r
+ a WDT Event if the user program fails to reload the WDT within a specified length of time known as the WDT Interval. (WDT)\r
+ */\r
+\r
+typedef struct { /*!< WDT Structure */\r
+ __IO uint16_t LOAD; /*!< Writing to reload Watch Dog Timer counter */\r
+ __I uint16_t RESERVED;\r
+ \r
+ union {\r
+ __IO uint8_t CONTROL; /*!< WDT Control Register */\r
+ \r
+ struct {\r
+ __IO uint8_t ENABLE : 1; /*!< WDT Block enabled */\r
+ __IO uint8_t STATUS : 1; /*!< last reset was caused by an underflow (R/WC) */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED1[3];\r
+ __O uint8_t KICK; /*!< Writes to reload and start decrementing */\r
+ __I uint8_t RESERVED2[3];\r
+ __I uint16_t COUNT; /*!< current WDT count. */\r
+} WDT_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ TIMER_16_0 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief This timer block offers a simple mechanism for firmware to maintain a time\r
+ base. This timer may be instantiated as 16 bits or 32 bits. (TIMER_16_0)\r
+ */\r
+\r
+typedef struct { /*!< TIMER_16_0 Structure */\r
+ __IO uint32_t COUNT; /*!< Timer counter. may be set by Firmware. */\r
+ __IO uint32_t PRE_LOAD; /*!< Timer pre-load for counter upon restart. */\r
+ __IO uint32_t INTERRUPT_STATUS; /*!< [0:0] Interrupt status (R/WC) */\r
+ __IO uint32_t INTERRUPT_ENABLE; /*!< [0:0] interrupt enable */\r
+ \r
+ union {\r
+ __IO REG32_U CONTROL; /*!< Timer Control Register */\r
+ \r
+ struct {\r
+ __IO uint32_t ENABLE : 1; /*!< This enables the block for operation. */\r
+ uint32_t : 1;\r
+ __IO uint32_t COUNT_UP : 1; /*!< This selects the counter direction. */\r
+ __IO uint32_t AUTO_RESTART: 1; /*!< select action taken upon completing a count. */\r
+ __IO uint32_t SOFT_RESET : 1; /*!< soft reset. self clearing 1 cycle. */\r
+ __IO uint32_t START : 1; /*!< This bit triggers the timer counter. */\r
+ __IO uint32_t RELOAD : 1; /*!< reloads counter without interrupting. */\r
+ __IO uint32_t HALT : 1; /*!< halt bit. */\r
+ uint32_t : 8;\r
+ __IO uint32_t PRE_SCALE : 16; /*!< to divide down system clock */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+} TIMER_16_0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ HTM ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The Hibernation Timer can generate a wake event to the Embedded Controller (EC)\r
+ when it is in a hibernation mode. This block supports wake events up to 2 hours in duration. \r
+ The timer is a 16-bit binary count-down timer that can be programmed in 30.5us and 0.125 second \r
+ increments for period ranges of 30.5us to 2s or 0.125s to 136.5 minutes, respectively. (HTM)\r
+ */\r
+\r
+typedef struct { /*!< HTM Structure */\r
+ __IO uint16_t PRELOAD; /*!< [15:0] set Hibernation Timer Preload value */\r
+ __I uint16_t RESERVED;\r
+ __IO uint16_t CONTROL; /*!< [0:0] 1= resolution 0.125s, 0= 30.5us */\r
+ __I uint16_t RESERVED1;\r
+ __I uint16_t COUNT; /*!< Count of the Hibernation Timer. */\r
+} HTM_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ RTC ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief This is the set of registers that are automatically counted by hardware\r
+ every 1 second while the block is enabled to run and to update. These registers are:\r
+ Seconds, Minutes, Hours, Day of Week, Day of Month, Month, and Year. (RTC)\r
+ */\r
+\r
+typedef struct { /*!< RTC Structure */\r
+ __IO uint8_t SEC; /*!< Seconds Register */\r
+ __IO uint8_t SEC_ALARM; /*!< Seconds Alarm Register */\r
+ __IO uint8_t MIN; /*!< Minutes Register */\r
+ __IO uint8_t MIN_ALARM; /*!< Minutes Alarm Register */\r
+ __IO uint8_t HR; /*!< Hours Register */\r
+ __IO uint8_t HR_ALARM; /*!< Hours Alarm Register */\r
+ __IO uint8_t DAY_WEEK; /*!< Day of Week Register */\r
+ __IO uint8_t DAY_MONTH; /*!< Day of Month Register */\r
+ __IO uint8_t MONTH; /*!< Month Register */\r
+ __IO uint8_t YEAR; /*!< Year Register */\r
+ __IO uint8_t REG_A; /*!< Register A */\r
+ __IO uint8_t REG_B; /*!< Register B */\r
+ __IO uint8_t REG_C; /*!< Register C */\r
+ __IO uint8_t REG_D; /*!< Register D */\r
+ __I uint16_t RESERVED;\r
+ \r
+ union {\r
+ __IO uint8_t CONTROL; /*!< RTC Control Register */\r
+ \r
+ struct {\r
+ __IO uint8_t BLOCK_ENABLE: 1; /*!< 1= block to function internally */\r
+ __IO uint8_t SOFT_RESET : 1; /*!< 1= RTC_RST reset (self-clearing no waiting) */\r
+ uint8_t : 1;\r
+ __IO uint8_t ALARM_ENABLE: 1; /*!< 1=Enables Alarm, 0=Disables */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED1[3];\r
+ __IO uint8_t WEEK_ALARM; /*!< Set value in range 1-7 */\r
+ __I uint8_t RESERVED2[3];\r
+ \r
+ union {\r
+ __IO uint32_t DAYLIGHT_SAVINGS_FORWARD; /*!< Daylight Savings Forward Register */\r
+ \r
+ struct {\r
+ __IO uint32_t DST_MONTH : 8; /*!< This field matches the Month Register. */\r
+ __IO uint32_t DST_DAY_OF_WEEK: 3; /*!< matches the Day of Week Register bits[2:0]. */\r
+ uint32_t : 5;\r
+ __IO uint32_t DST_WEEK : 3; /*!< week number (1,,5) within current month. */\r
+ uint32_t : 5;\r
+ __IO uint32_t DST_HOUR : 7; /*!< matching value for bits[6:0] of Hours register */\r
+ __IO uint32_t DST_AM_PM : 1; /*!< This bit selects AM vs. PM. */\r
+ } DAYLIGHT_SAVINGS_FORWARD_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t DAYLIGHT_SAVINGS_BACKWARD; /*!< Daylight Savings Backward Register */\r
+ \r
+ struct {\r
+ __IO uint32_t DST_MONTH : 8; /*!< This field matches the Month Register. */\r
+ __IO uint32_t DST_DAY_OF_WEEK: 3; /*!< matches the Day of Week Register bits[2:0]. */\r
+ uint32_t : 5;\r
+ __IO uint32_t DST_WEEK : 3; /*!< week number (1,,5) within current month. */\r
+ uint32_t : 5;\r
+ __IO uint32_t DST_HOUR : 7; /*!< matching value for bits[6:0] of Hours register */\r
+ __IO uint32_t DST_AM_PM : 1; /*!< This bit selects AM vs. PM. */\r
+ } DAYLIGHT_SAVINGS_BACKWARD_b; /*!< BitSize */\r
+ };\r
+} RTC_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ GPIO ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The CEC1302/24 GPIO Interface provides general purpose input monitoring and output control,\r
+ as well as managing many aspects of pin functionality; including, multi-function Pin Multiplexing Control, GPIO\r
+ Direction control, PU/PD (PU_PD) resistors, asynchronous wakeup and synchronous Interrupt Detection (int_det),\r
+ GPIO Direction, and Polarity control, as well as control of pin drive strength and slew rate. (GPIO)\r
+ */\r
+\r
+typedef struct { /*!< GPIO Structure */\r
+ \r
+ union {\r
+ __IO uint32_t PIN_CONTROL[160]; /*!< 1st Pin Control Register */\r
+ \r
+ struct {\r
+ __IO uint32_t PU_PD : 2; /*!< 01= Pull Up, 10= Pull Down, 11/00= None */\r
+ __IO uint32_t PWR : 2; /*!< 00= VCC1, 01= VCC2 Power Rail 1x = Reserved */\r
+ __IO uint32_t INT_DET : 3; /*!< \r
+ [7654] --------------------------------------------\r
+ 0 000 = Low Level Sensitive \r
+ 0 001 = High Level Sensitive\r
+ 0 100 = Interrupt events are disabled\r
+ 1 101 = Rising Edge Triggered \r
+ 1 110 = Falling Edge Triggered \r
+ 1 111 = Either edge triggered \r
+ --------------------------------------------------- */\r
+ __IO uint32_t EDGE_EN : 1; /*!< 1= Edge detection enabled */\r
+ __IO uint32_t BUFFER : 1; /*!< Output Buffer Type. 0 = Push-Pull, 1 = Open Drain */\r
+ __IO uint32_t DIR : 1; /*!< GPIO Direction. 0 = Input, 1 = Output */\r
+ __IO uint32_t OUTPUT_WRITE_EN: 1; /*!< 0= Alternative GPIO data write enabled */\r
+ __IO uint32_t POLARITY : 1; /*!< 0 = Non-inverted, 1 = Inverted */\r
+ __IO uint32_t MUX : 2; /*!< 00= GPIO Function, 01/10/11=Func 1/2/3 */\r
+ uint32_t : 2;\r
+ __IO uint32_t OUTPUT : 1; /*!< 0: GPIO[x] out = '0', 1: GPIO[x] out = '1' */\r
+ uint32_t : 7;\r
+ __I uint32_t INPUT : 1; /*!< reflects the state of GPIO input */\r
+ } PIN_CONTROL_b[160]; /*!< BitSize */\r
+ };\r
+ __IO uint32_t OUTPUT[5]; /*!< Group 0: GPIO[x] out =0, 1: =1 */\r
+ __I uint32_t RESERVED[27];\r
+ __IO uint32_t INPUT[5]; /*!< Group GPIO Input Registers */\r
+ __I uint32_t RESERVED1[123];\r
+ \r
+ union {\r
+ __IO uint32_t CONTROL2_000_067[56]; /*!< PIN CONTROL REGISTER 2, from 000 - 067 */\r
+ \r
+ struct {\r
+ __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */\r
+ uint32_t : 3;\r
+ __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */\r
+ } CONTROL2_000_067_b[56]; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t CONTROL2_100_167[56]; /*!< PIN CONTROL REGISTER 2, from 100 - 167 */\r
+ \r
+ struct {\r
+ __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */\r
+ uint32_t : 3;\r
+ __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */\r
+ } CONTROL2_100_167_b[56]; /*!< BitSize */\r
+ };\r
+ __I uint32_t RESERVED2[24];\r
+ \r
+ union {\r
+ __IO uint32_t CONTROL2_200_267[56]; /*!< PIN CONTROL REGISTER 2, from 200 - 267 */\r
+ \r
+ struct {\r
+ __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */\r
+ uint32_t : 3;\r
+ __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */\r
+ } CONTROL2_200_267_b[56]; /*!< BitSize */\r
+ };\r
+} GPIO_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ DMA ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The Internal DMA Controller transfers data to/from the source from/to the\r
+ destination. The firmware is responsible for setting up each channel. Afterwards either the\r
+ firmware or the hardware may perform the flow control. The hardware flow control exists entirely\r
+ inside the source device. Each transfer may be 1, 2, or 4 bytes in size, so long as the device\r
+ supports a transfer of that size. Every device must be on the internal 32-bit address space. (DMA)\r
+ */\r
+\r
+typedef struct { /*!< DMA Structure */\r
+ \r
+ union {\r
+ __IO uint8_t CONTROL; /*!< Soft reset. Enable the blocks operation. */\r
+ \r
+ struct {\r
+ __IO uint8_t ACTIVATE : 1; /*!< Enable the blocks operation. (R/WS) */\r
+ __O uint8_t SOFT_RESET : 1; /*!< Soft reset entire module. self-clearing. */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED[3];\r
+ __I uint32_t DATA_PACKET; /*!< data from currently active transfer source */\r
+ __I uint32_t RESERVED1[2];\r
+ DMA_CH_Type CH[12]; /*!< registers to determine channel's operation. */\r
+} DMA_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ SMB0 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface. (SMB0)\r
+ */\r
+\r
+typedef struct { /*!< SMB0 Structure */\r
+ \r
+ union {\r
+ union {\r
+ __I uint8_t STATUS; /*!< Status Register */\r
+ \r
+ struct {\r
+ __I uint8_t nBB : 1; /*!< 0= Bus Busy */\r
+ __I uint8_t LAB : 1; /*!< Lost Arbitration Bit */\r
+ __I uint8_t AAS : 1; /*!< Addressed As Slave */\r
+ __I uint8_t LRB_AD0 : 1; /*!< "Last Received Bit"/Address 0 (general call) */\r
+ __I uint8_t BER : 1; /*!< Bus Error (BER) */\r
+ __I uint8_t STS : 1; /*!< 1=ext generated STOP condition is detected. */\r
+ __I uint8_t SAD : 1; /*!< SMBus Address Decoded (SAD) */\r
+ __I uint8_t PIN : 1; /*!< Pending Interrupt bit */\r
+ } STATUS_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __O uint8_t CONTROL; /*!< Control Register */\r
+ \r
+ struct {\r
+ __IO uint8_t ACK : 1; /*!< 1= send an acknowledge automatically */\r
+ __IO uint8_t STO : 1; /*!< See STA description */\r
+ __IO uint8_t STA : 1; /*!< generation of repeated Start and Stop condition */\r
+ __IO uint8_t ENI : 1; /*!< Enable Interrupt bit */\r
+ uint8_t : 2;\r
+ __IO uint8_t ESO : 1; /*!< enables/disables SMB serial data output */\r
+ __IO uint8_t PIN : 1; /*!< Pending Interrupt Not (PIN) software reset */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ };\r
+ __I uint8_t RESERVED[3];\r
+ \r
+ union {\r
+ __IO uint16_t OWN; /*!< Own Address Reg. wt 55h= AAh addr */\r
+ \r
+ struct {\r
+ __IO uint16_t ADDRESS_1 : 7; /*!< Own Address 1 addressed as a slave. */\r
+ uint16_t : 1;\r
+ __IO uint16_t ADDRESS_2 : 7; /*!< Own Address 2 addressed as a slave. */\r
+ } OWN_b; /*!< BitSize */\r
+ };\r
+ __I uint16_t RESERVED1;\r
+ __IO uint8_t DATA_REG; /*!< Data */\r
+ __I uint8_t RESERVED2[3];\r
+ \r
+ union {\r
+ __IO uint32_t MASTER_COMMAND; /*!< SMBus Master Command Register */\r
+ \r
+ struct {\r
+ __IO uint32_t MRUN : 1; /*!< 1= transfer bytes over SMBus. */\r
+ __IO uint32_t MPROCEED : 1; /*!< 1:WAIT-BUSBUSY and MRUN-RECEIVE */\r
+ uint32_t : 6;\r
+ __IO uint32_t START0 : 1; /*!< 1: send a Start bit on the SMBus */\r
+ __IO uint32_t STARTN : 1; /*!< 1: send a Start before the last byte */\r
+ __IO uint32_t STOP : 1; /*!< 1: send a Stop bit after transaction completes */\r
+ __IO uint32_t PEC_TERM : 1; /*!< 1: PEC is transmitted when WriteCount is 0. */\r
+ __IO uint32_t READM : 1; /*!< 1: ReadCount field is replaced by byte */\r
+ __IO uint32_t READ_PEC : 1; /*!< 1: reading when ReadCount is 0 for one more byte */\r
+ uint32_t : 2;\r
+ __IO uint32_t WRITECOUNT : 8; /*!< number of Master Transmit Buffer bytes */\r
+ __IO uint32_t READCOUNT : 8; /*!< number of Master Receive Buffer bytes */\r
+ } MASTER_COMMAND_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t SLAVE_COMMAND; /*!< SMBus Slave Command Register */\r
+ \r
+ struct {\r
+ __IO uint32_t SRUN : 1; /*!< 1:enables the Slave State Machine to operate */\r
+ __IO uint32_t SPROCEED : 1; /*!< Slave to START_WAIT/RECEIVE/TRANSMIT states */\r
+ __IO uint32_t SLAVE_PEC : 1; /*!< 1:PEC is copied to the DATA register */\r
+ uint32_t : 5;\r
+ __IO uint32_t SLAVE_WRITECOUNT: 8; /*!< number bytes software expects to send to Master */\r
+ __IO uint32_t SLAVE_READCOUNT: 8; /*!< number copied from DATA to Slave Receive Buffer */\r
+ } SLAVE_COMMAND_b; /*!< BitSize */\r
+ };\r
+ __IO uint8_t PEC; /*!< PEC byte */\r
+ __I uint8_t RESERVED3[3];\r
+ __IO uint8_t DATA_TIMING2; /*!< HOLD TIME (clock) START BIT */\r
+ __I uint8_t RESERVED4[7];\r
+ \r
+ union {\r
+ __IO uint32_t COMPLETION; /*!< Completion Register */\r
+ \r
+ struct {\r
+ uint32_t : 2;\r
+ __IO uint32_t DTEN : 1; /*!< 1: Device Time-out checking is enabled. */\r
+ __IO uint32_t MCEN : 1; /*!< 1: enable Master Cumulative Time-Out checking */\r
+ __IO uint32_t SCEN : 1; /*!< 1:enable Slave Cumulative Time-Out checking */\r
+ __IO uint32_t BIDEN : 1; /*!< 1:Bus Idle Detect Time-Out checking is enabled */\r
+ __I uint32_t TIMERR : 1; /*!< 1:timeout error detect status are asserted. */\r
+ uint32_t : 1;\r
+ __IO uint32_t DTO : 1; /*!< DTO is the Device Time-out bit. (R/WC) */\r
+ __IO uint32_t MCTO : 1; /*!< Master Cumulative Time-out bit. (R/WC) */\r
+ __IO uint32_t SCTO : 1; /*!< SCTO is the Slave Cumulative Time-out bit(R/WC) */\r
+ __IO uint32_t CHDL : 1; /*!< CHDL is the clock high time-out detect bit(R/WC) */\r
+ __IO uint32_t CHDH : 1; /*!< CHDH is the bus idle time-out detect bit(R/WC) */\r
+ __IO uint32_t BER : 1; /*!< 1: BER in Status was set (R/WC) */\r
+ __IO uint32_t LAB : 1; /*!< 1: LAB in Status was set (R/WC) */\r
+ uint32_t : 1;\r
+ __IO uint32_t SNAKR : 1; /*!< 1: Slave sent NACK to transmitting Master */\r
+ __I uint32_t STR : 1; /*!< 0: finished receive, 1:finished transmit phase */\r
+ uint32_t : 1;\r
+ __IO uint32_t SPROT : 1; /*!< 1: WriteCount in Slave counted down to 0(R/WC) */\r
+ __IO uint32_t REPEAT_READ: 1; /*!< 1: Slave stopped because a Repeat Start for Rd */\r
+ __IO uint32_t REPEAT_WRITE: 1; /*!< 1: Slave stopped because a Repeat Start for Wt */\r
+ uint32_t : 2;\r
+ __IO uint32_t MNAKX : 1; /*!< 1: Master received a NACK while transmitting */\r
+ __I uint32_t MTR : 1; /*!< Master finished 0: receive 1: transmit */\r
+ uint32_t : 3;\r
+ __IO uint32_t IDLE : 1; /*!< 1: I2C bus becomes idle (R/WC) */\r
+ __IO uint32_t MDONE : 1; /*!< 1: Master completed operation (R/WC) */\r
+ __IO uint32_t SDONE : 1; /*!< 1: Slave completed operation (R/WC) */\r
+ } COMPLETION_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t IDLE_SCALING; /*!< Idle Scaling Register */\r
+ \r
+ struct {\r
+ __IO uint32_t FAIR_BUS_IDLE_MIN: 12; /*!< number ticks to satisfy the fairness protocol */\r
+ uint32_t : 4;\r
+ __IO uint32_t FAIR_IDLE_DELAY: 12; /*!< number ticks to program the delay */\r
+ } IDLE_SCALING_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t CONFIGURATION; /*!< Configuration Register */\r
+ \r
+ struct {\r
+ __IO uint32_t PORT_SEL : 4; /*!< determine one of 16 bus ports apply to SDAT/SCLK */\r
+ __IO uint32_t TCEN : 1; /*!< 1: Bus Time-Outs are enabled */\r
+ __I uint32_t SLOW_CLOCK : 1; /*!< 1: Bus Clock multiplied by 4, thus frequency/4 */\r
+ uint32_t : 1;\r
+ __IO uint32_t PECEN : 1; /*!< 1: Hardware PEC Support is enabled */\r
+ __IO uint32_t DFEN : 1; /*!< 1: Digital Filter is enabled. 0: bypassed. */\r
+ __IO uint32_t RESET : 1; /*!< 1: initialized to power-on default state. */\r
+ __IO uint32_t ENAB : 1; /*!< 1: normal operation, 0: lowest power */\r
+ __IO uint32_t DSA : 1; /*!< 0: Slave Address I2C Compatibility, 1: SMBus */\r
+ __IO uint32_t FAIR : 1; /*!< 1: MCTP Fairness protocol is in effect. */\r
+ uint32_t : 1;\r
+ __I uint32_t GC_DIS : 1; /*!< General Call address 0: enabled, 1: disabled */\r
+ uint32_t : 1;\r
+ __O uint32_t FLUSH_SXBUF: 1; /*!< 1: Slave Transmit Buffer to be marked empty. */\r
+ __O uint32_t FLUSH_SRBUF: 1; /*!< 1: Slave Receive Buffer to be marked empty. */\r
+ __O uint32_t FLUSH_MXBUF: 1; /*!< 1: Master Transmit Buffer to be marked empty. */\r
+ __O uint32_t FLUSH_MRBUF: 1; /*!< 1: Master Receive Buffer to be marked empty. */\r
+ uint32_t : 8;\r
+ __I uint32_t EN_AAS : 1; /*!< 0: Disable AAS Interrupt, 1: Enable */\r
+ __IO uint32_t ENIDI : 1; /*!< 1: Idle interrupt is enabled. 0: disabled. */\r
+ __IO uint32_t ENMI : 1; /*!< 1: Master Done interrupt is enabled. 0: disabled */\r
+ __IO uint32_t ENSI : 1; /*!< 1: Slave Done interrupt is enabled. 0: disabled */\r
+ } CONFIGURATION_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint16_t BUS_CLOCK; /*!< Bus Clock Register */\r
+ \r
+ struct {\r
+ __IO uint16_t LOW_PERIOD : 8; /*!< number of I2C Baud Clock to make up low phase */\r
+ __IO uint16_t HIGH_PERIOD: 8; /*!< number of I2C Baud Clock to make up high phase */\r
+ } BUS_CLOCK_b; /*!< BitSize */\r
+ };\r
+ __I uint16_t RESERVED5;\r
+ __I uint8_t BLOCK_ID; /*!< Block ID Register */\r
+ __I uint8_t RESERVED6[3];\r
+ __I uint8_t REVISION; /*!< Revision Register */\r
+ __I uint8_t RESERVED7[3];\r
+ \r
+ union {\r
+ __IO uint8_t BIT_BANG_CONTROL; /*!< Bit-Bang Control Register */\r
+ \r
+ struct {\r
+ __IO uint8_t BBEN : 1; /*!< 1: Bit-Bang Mode Enable. */\r
+ __IO uint8_t CLDIR : 1; /*!< Bit-Bang Clock Direction. 0 - Input, 1 - Output */\r
+ __IO uint8_t DADIR : 1; /*!< Bit-Bang Data Direction. 0 - Input. 1 - Output */\r
+ __IO uint8_t BBCLK : 1; /*!< controls state of SCLK when BBEN = CLDIR = 1 */\r
+ __IO uint8_t BBDAT : 1; /*!< controls state of SDAT when BBEN = DADIR = 1 */\r
+ __I uint8_t BBCLKI : 1; /*!< Bit-Bang Clock In. returns the state of SCLK. */\r
+ __I uint8_t BBDATI : 1; /*!< Bit-Bang Data In. returns the state of SDAT */\r
+ } BIT_BANG_CONTROL_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED8[7];\r
+ \r
+ union {\r
+ __IO uint32_t DATA_TIMING; /*!< Data Timing Register */\r
+ \r
+ struct {\r
+ __IO uint32_t DATA_HOLD : 8; /*!< SDAT hold time following SCLK driven low. */\r
+ __IO uint32_t RESTART_SETUP: 8; /*!< SDAT setup time for a repeated START condition. */\r
+ __IO uint32_t STOP_SETUP : 8; /*!< SDAT setup time for a STOP condition. */\r
+ __IO uint32_t START_HOLD : 8; /*!< SCLK hold time during a START condition. */\r
+ } DATA_TIMING_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t TIME_OUT_SCALING; /*!< Time-Out Scaling Register */\r
+ \r
+ struct {\r
+ __IO uint32_t CLOCK_HIGH : 8; /*!< = Clock High Time-Out x Baud_Clock_Period x 2 */\r
+ __IO uint32_t SLAVE_CUM : 8; /*!< = Slave Cum Time-Out x Baud_Clock_Period x 1024 */\r
+ __IO uint32_t MASTER_CUM : 8; /*!< = Master Cum Time-Out x Baud_Clock_Periodx 512 */\r
+ __IO uint32_t BUS_IDLE_MIN: 8; /*!< = Bus Idle Min [7:0] x Baud_Clock_Period */\r
+ } TIME_OUT_SCALING_b; /*!< BitSize */\r
+ };\r
+ __IO uint8_t SLAVE_TRANSMIT_BUFFER; /*!< SMBus Slave Transmit Buffer Register */\r
+ __I uint8_t RESERVED9[3];\r
+ __IO uint8_t SLAVE_RECEIVE_BUFFER; /*!< SMBus Slave Receive Buffer Register */\r
+ __I uint8_t RESERVED10[3];\r
+ __IO uint8_t MASTER_TRANSMIT_BUFER; /*!< SMBus Master Transmit Bufer Register */\r
+ __I uint8_t RESERVED11[3];\r
+ __IO uint8_t MASTER_RECEIVE_BUFFER; /*!< SMBus Master Receive Buffer Register */\r
+} SMB0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PECI ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The CEC1302 includes a PECI Interface to allow the EC to retrieve temperature readings from PECI-compliant devices. (PECI)\r
+ */\r
+\r
+typedef struct { /*!< PECI Structure */\r
+ __IO uint8_t WRITE_DATA; /*!< Tprovides access to a 32-byte Transmit FIFO. */\r
+ __I uint8_t RESERVED[3];\r
+ __IO uint8_t READ_DATA; /*!< provides access to a 32-byte Receive FIFO. */\r
+ __I uint8_t RESERVED1[3];\r
+ \r
+ union {\r
+ __IO uint8_t CONTROL; /*!< Control Register */\r
+ \r
+ struct {\r
+ __IO uint8_t PD : 1; /*!< Power Down controls Power Management Interface */\r
+ uint8_t : 2;\r
+ __IO uint8_t RST : 1; /*!< RST indicates that the PECI Core should be reset. */\r
+ uint8_t : 1;\r
+ __IO uint8_t FRST : 1; /*!< FRST is the FIFO Reset bit. */\r
+ __IO uint8_t TXEN : 1; /*!< TXEN is the Transmit Enable bit. */\r
+ __IO uint8_t MIEN : 1; /*!< MIEN is the Master Interrupt Enable */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED2[3];\r
+ \r
+ union {\r
+ __IO uint8_t STATUS1; /*!< Status Register 1 */\r
+ \r
+ struct {\r
+ __IO uint8_t BOF : 1; /*!< PECI begins Address Timing Negotiation(R/WC) */\r
+ __IO uint8_t nEOF : 1; /*!< End of Frame asserted following Message Stop(R/WC) */\r
+ __I uint8_t ERR : 1; /*!< error for current transaction has been detected */\r
+ __I uint8_t RDY : 1; /*!< state of the READY signal function */\r
+ __IO uint8_t RDYLO : 1; /*!< 1: falling edge of the READY signal function(R/WC) */\r
+ __IO uint8_t RDYHI : 1; /*!< 1: rising edge of the READY signal function (R/WC) */\r
+ uint8_t : 1;\r
+ __I uint8_t MINT : 1; /*!< asserted when any interrupt status is asserted. */\r
+ } STATUS1_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED3[3];\r
+ \r
+ union {\r
+ __I uint8_t STATUS2; /*!< Status Register 2 */\r
+ \r
+ struct {\r
+ __I uint8_t WFF : 1; /*!< Write Data Register FIFO is full. No interrupt. */\r
+ __I uint8_t WFE : 1; /*!< Write Data Register FIFO is empty. */\r
+ __I uint8_t RFF : 1; /*!< RFF indicates Read Data Register FIFO is full. */\r
+ __I uint8_t RFE : 1; /*!< Read Data Register FIFO is empty. No interrupt. */\r
+ uint8_t : 3;\r
+ __I uint8_t IDLE : 1; /*!< SST/PECI bus is idle, a new transaction may begin */\r
+ } STATUS2_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED4[3];\r
+ \r
+ union {\r
+ __IO uint8_t ERROR; /*!< Error Register */\r
+ \r
+ struct {\r
+ __IO uint8_t FERR : 1; /*!< FERR (Frame Check Sequence Error). (R/WC) */\r
+ __IO uint8_t BERR : 1; /*!< reads value different from it has driven (R/WC) */\r
+ uint8_t : 1;\r
+ __IO uint8_t REQERR : 1; /*!< READY is not asserted when counts down to zero */\r
+ __IO uint8_t WROV : 1; /*!< WROV (Write Overrun). (R/WC) */\r
+ __IO uint8_t WRUN : 1; /*!< WRUN (Write Underrun). (R/WC) */\r
+ __IO uint8_t RDOV : 1; /*!< indicates read buffer has overflowed (R/WC) */\r
+ __IO uint8_t CLKERR : 1; /*!< READY de-asserted in middle of a transaction(R/WC) */\r
+ } ERROR_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED5[3];\r
+ \r
+ union {\r
+ __IO uint8_t INT_EN1; /*!< Interrupt Enable 1 Register */\r
+ \r
+ struct {\r
+ __IO uint8_t BIEN : 1; /*!< '1' the BOF interrupt is enabled. */\r
+ __IO uint8_t EIEN : 1; /*!< '1' the EOF interrupt is enabled. */\r
+ __IO uint8_t EREN : 1; /*!< '1' the ERR interrupt is enabled. */\r
+ uint8_t : 1;\r
+ __IO uint8_t RLEN : 1; /*!< '1' the RDYLO interrupt is enabled. */\r
+ __IO uint8_t RHEN : 1; /*!< '1' the RDYHI interrupt is enabled. */\r
+ } INT_EN1_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED6[3];\r
+ \r
+ union {\r
+ __IO uint8_t INT_EN2; /*!< Interrupt Enable 2 Register */\r
+ \r
+ struct {\r
+ uint8_t : 1;\r
+ __IO uint8_t ENWFE : 1; /*!< '1' the WFE interrupt is enabled. */\r
+ __IO uint8_t ENRFF : 1; /*!< '1' the RFF interrupt is enabled. */\r
+ } INT_EN2_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED7[3];\r
+ __IO uint8_t OBT1; /*!< Optimal Bit Time Register (Low Byte) */\r
+ __I uint8_t RESERVED8[3];\r
+ __IO uint8_t OBT2; /*!< Optimal Bit Time Register (High Byte) */\r
+ __I uint8_t RESERVED9[27];\r
+ __IO uint32_t ID; /*!< Block ID Register */\r
+ __IO uint32_t REV; /*!< Revision Register */\r
+} PECI_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ TACH_0 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief This block monitors TACH output signals (or locked rotor signals) from\r
+ various types of fans, and determines their speed. (TACH_0)\r
+ */\r
+\r
+typedef struct { /*!< TACH_0 Structure */\r
+ \r
+ union {\r
+ __IO uint32_t CONTROL; /*!< TACHx Control Register */\r
+ \r
+ struct {\r
+ __IO uint32_t OUT_LIMIT_ENABLE: 1; /*!< 1=Enable interrupt output from Tach block */\r
+ __IO uint32_t TACH_EN : 1; /*!< 1= TACH Monitoring/ clock enabled, 0= TACH Idle */\r
+ uint32_t : 6;\r
+ __IO uint32_t FILTER_EN : 1; /*!< remove high frequency glitches. 1=Filter enabled */\r
+ uint32_t : 1;\r
+ __IO uint32_t MODE_SELECT: 1; /*!< 1=Counter is incremented on rising edge */\r
+ __IO uint32_t EDGES : 2; /*!< 00/01/10/11: 2/3/5/9 Tach edges */\r
+ uint32_t : 1;\r
+ __IO uint32_t READY_INT_EN: 1; /*!< 1=Enable Count Ready interrupt, 0=Disable */\r
+ __IO uint32_t INPUT_INT_EN: 1; /*!< 1=Enable Tach Input toggle interrupt, 0=Disable */\r
+ __I uint32_t COUNTER : 16; /*!< latched value of the internal Tach pulse counter */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t STATUS; /*!< TACHx Status Register */\r
+ \r
+ struct {\r
+ __IO uint32_t OUT_LIMIT : 1; /*!< 1=Tach is outside of limits (R/WC) */\r
+ __I uint32_t PIN : 1; /*!< 1= Tach Input is high, 0= Input is low */\r
+ __IO uint32_t TOGGLE : 1; /*!< 1=Tach Input changed state, 0= stable (R/WC) */\r
+ __IO uint32_t COUNT_READY: 1; /*!< 1=Reading ready, 0=Reading not ready */\r
+ } STATUS_b; /*!< BitSize */\r
+ };\r
+ __IO uint16_t HIGH_LIMIT; /*!< value is compared with TACHX_COUNTER field. */\r
+ __I uint16_t RESERVED;\r
+ __IO uint16_t LOW_LIMIT; /*!< value is compared with TACHX_COUNTER field. */\r
+} TACH_0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PWM_0 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief This block generates a PWM output that can be used to control 4-wire fans, blinking LEDs, and \r
+ other similar devices. Each PWM can generate an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz. \r
+ The PWM controller can also used to generate the PROCHOT output and Speaker output. (PWM_0)\r
+ */\r
+\r
+typedef struct { /*!< PWM_0 Structure */\r
+ __IO uint32_t COUNTER_ON_TIME; /*!< determine both frequency and duty cycle */\r
+ __IO uint32_t COUNTER_OFF_TIME; /*!< determine both frequency and duty cycle */\r
+ \r
+ union {\r
+ __IO uint32_t CONFIG; /*!< PWMx CONFIGURATION REGISTER */\r
+ \r
+ struct {\r
+ __IO uint32_t EN : 1; /*!< 1=Enabled (default), 0=Disabled */\r
+ __IO uint32_t CLK_SELECT : 1; /*!< determines clock source, 1=CLOCK_LOW, 0=HIGH */\r
+ __IO uint32_t INVERT : 1; /*!< 1= PWM_OUTPUT ON State is active low, 0=high */\r
+ __IO uint32_t CLK_PRE_DIVIDER: 4; /*!< Clock source is divided by Pre-Divider+1 */\r
+ } CONFIG_b; /*!< BitSize */\r
+ };\r
+} PWM_0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ RPM_FAN ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The RPM-PWM Interface is an RPM based Fan Control Algorithm that monitors\r
+ the fan's speed and automatically adjusts the drive to maintain the desired fan speed. This\r
+ RPM based Fan Control Algorithm controls a PWM output based on a tachometer input. (RPM_FAN)\r
+ */\r
+\r
+typedef struct { /*!< RPM_FAN Structure */\r
+ __IO uint8_t SETTING; /*!< Drive = (FAN_SETTING VALUE/255) x 100%. */\r
+ __IO uint8_t PWM_DIVIDE; /*!< PWM_Frequency = base_clk / PWM_DIVIDE */\r
+ \r
+ union {\r
+ __IO uint16_t CONFIGURATION; /*!< general operation of Fan Control Algorithm */\r
+ \r
+ struct {\r
+ __IO uint16_t UPDATE : 3; /*!< Determines base time between fan driver updates */\r
+ __IO uint16_t EDGES : 2; /*!< minimum number of edges that must be detected */\r
+ __IO uint16_t RANGE : 2; /*!< Adjusts the range of tachometer reading values. */\r
+ __IO uint16_t EN_ALGO : 1; /*!< Enables the RPM based Fan Control Algorithm. */\r
+ __IO uint16_t POLARITY : 1; /*!< 1: The Polarity of the PWM driver is inverted. */\r
+ __IO uint16_t ERR_RNG : 2; /*!< Control advanced options that affect error window. */\r
+ __IO uint16_t DER_OPT : 2; /*!< Control portion of RPM fan control algorithm */\r
+ __IO uint16_t DIS_GLITCH : 1; /*!< 1: The glitch filter is disabled. */\r
+ __IO uint16_t EN_RRC : 1; /*!< Enables the ramp rate control circuitry */\r
+ } CONFIGURATION_b; /*!< BitSize */\r
+ };\r
+ __I uint8_t RESERVED;\r
+ \r
+ union {\r
+ __IO uint8_t GAIN; /*!< gain for proportional/integral portion */\r
+ \r
+ struct {\r
+ __IO uint8_t GAINP : 2; /*!< derivative gain term */\r
+ __IO uint8_t GAINI : 2; /*!< derivative gain term */\r
+ __IO uint8_t GAIND : 2; /*!< derivative gain term */\r
+ } GAIN_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint8_t SPIN_UP_CONFIGURATION; /*!< settings of Spin Up Routine. */\r
+ \r
+ struct {\r
+ __IO uint8_t SPINUP_TIME: 2; /*!< maximum Spin Time that Spin Up Routine run */\r
+ __IO uint8_t SPIN_LVL : 3; /*!< final drive level used by the Spin Up Routine */\r
+ __IO uint8_t NOKICK : 1; /*!< 1: Spin Routine will not drive fan to 100% */\r
+ __IO uint8_t DRIVE_FAIL_CNT: 2; /*!< update cycles are used for Drive Fail detection */\r
+ } SPIN_UP_CONFIGURATION_b; /*!< BitSize */\r
+ };\r
+ __IO uint8_t STEP; /*!< max step driver take between update */\r
+ __IO uint8_t MINIMUM_DRIVE; /*!< minimum drive setting for Fan Algorithm. */\r
+ __IO uint8_t VALID_TACH_COUNT; /*!< max value to indicate fan spin properly */\r
+ __IO uint16_t DRIVE_FAIL_BAND; /*!< [15:3]counts for Drive Fail circuitry */\r
+ __IO uint16_t TACH_TARGET; /*!< [12:0] The target tachometer value. */\r
+ __IO uint8_t TACH_READING; /*!< [15:3]current tachometer reading value. */\r
+ __I uint8_t RESERVED1;\r
+ __IO uint8_t DRIVER_BASE_FREQUENCY; /*!< [1:0]frequency range of the PWM fan driver */\r
+ \r
+ union {\r
+ __IO uint8_t STATUS; /*!< The bits are routed to interrupts */\r
+ \r
+ struct {\r
+ __IO uint8_t FAN_STALL : 1; /*!< 1 - Stalled fan detected. (R/WC) */\r
+ __IO uint8_t FAN_SPIN : 1; /*!< 1: Spin up Routine not detect a valid tachometer */\r
+ uint8_t : 3;\r
+ __IO uint8_t DRIVE_FAIL : 1; /*!< 1- cannot drive to target setting (R/WC) */\r
+ } STATUS_b; /*!< BitSize */\r
+ };\r
+} RPM_FAN_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ SPI_0 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The General Purpose Serial Peripheral Interface (GP-SPI) may be used\r
+ to communicate with various peripheral devices, e.g., EEPROMS, DACs, ADCs, that use a\r
+ standard Serial Peripheral Interface. (SPI_0)\r
+ */\r
+\r
+typedef struct { /*!< SPI_0 Structure */\r
+ __IO uint32_t ENABLE; /*!< [0:0] 1=Enabled. device is fully operational */\r
+ \r
+ union {\r
+ __IO uint32_t CONTROL; /*!< SPI Control */\r
+ \r
+ struct {\r
+ __IO uint32_t LSBF : 1; /*!< Least Significant Bit First */\r
+ __IO uint32_t BIOEN : 1; /*!< Bidirectional Output Enable control. */\r
+ __IO uint32_t SPDIN_SELECT: 2; /*!< [3:2]1xb=SPDIN1,SPDIN2. Select Dual Mode */\r
+ __IO uint32_t SOFT_RESET : 1; /*!< Wt 1 to Soft Reset. self-clearing */\r
+ __IO uint32_t AUTO_READ : 1; /*!< Auto Read Enable. */\r
+ __IO uint32_t CE : 1; /*!< SPI Chip Select Enable. */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __I uint32_t STATUS; /*!< SPI Status */\r
+ \r
+ struct {\r
+ __I uint32_t TXBE : 1; /*!< 1=TX_Data buffer is empty */\r
+ __I uint32_t RXBF : 1; /*!< 1=RX_Data buffer is full */\r
+ __I uint32_t ACTIVE : 1; /*!< ACTIVE status */\r
+ } STATUS_b; /*!< BitSize */\r
+ };\r
+ __IO uint32_t TX_DATA; /*!< [7:0]wt to initiate a SPI transaction. */\r
+ __IO uint32_t RX_DATA; /*!< [7:0]read value returned by ext SPI device */\r
+ \r
+ union {\r
+ __IO uint32_t CLOCK_Control; /*!< SPI Clock Control. */\r
+ \r
+ struct {\r
+ __IO uint32_t TCLKPH : 1; /*!< Valid data is clocked out on 1st SPI_CLK */\r
+ __IO uint32_t RCLKPH : 1; /*!< Valid data is expected after 1st SPI_CLK edge */\r
+ __IO uint32_t CLKPOL : 1; /*!< SPI_CLK is high when 1st clock edge falling */\r
+ uint32_t : 1;\r
+ __IO uint32_t CLKSRC : 1; /*!< 1=2MHz, 0=48 MHz Ring Oscillator */\r
+ } CLOCK_Control_b; /*!< BitSize */\r
+ };\r
+ __IO uint32_t CLOCK_GENERATOR; /*!< [5:0] PRELOAD SPI Clock Generator Preload value. */\r
+} SPI_0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ LED_0 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The blinking/breathing hardware is implemented using a PWM. The PWM can be\r
+ driven either by the 48 MHz clock or by a 32.768 KHz clock input. When driven by the 48 MHz clock,\r
+ the PWM can be used as a standard 8-bit PWM in order to control a fan. When used to drive blinking\r
+ or breathing LEDs, the 32.768 KHz clock source is used. (LED_0)\r
+ */\r
+\r
+typedef struct { /*!< LED_0 Structure */\r
+ \r
+ union {\r
+ __IO uint32_t CONFIG; /*!< LED Configuration */\r
+ \r
+ struct {\r
+ __IO uint32_t CONTROL : 2; /*!< 3=on,2=blinking,1=breathing,0=off */\r
+ __IO uint32_t CLOCK_SOURCE: 1; /*!< 1=48MHz, 0=32.768 KHz clock */\r
+ __IO uint32_t SYNCHRONIZE: 1; /*!< 1: all LEDs are reset to initial values. */\r
+ __IO uint32_t PWM_SIZE : 2; /*!< 3:reserved, 2:6bit, 1:7bit,0:8bit PWM */\r
+ __IO uint32_t ENABLE_UPDATE: 1; /*!< ENABLE_UPDATE */\r
+ __O uint32_t RESET : 1; /*!< 1 resets PWM to default values self clearing */\r
+ __IO uint32_t WDT_RELOAD : 8; /*!< PWM Watchdog Timer counter reload value */\r
+ __IO uint32_t SYMMETRY : 1; /*!< 1=rising/falling ramp are in Asymmetric mode */\r
+ } CONFIG_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t LIMITS; /*!< LED Limits */\r
+ \r
+ struct {\r
+ __IO uint32_t MINIMUM : 8; /*!< wait in breathing if current cycle less this value */\r
+ __IO uint32_t MAXIMUM : 8; /*!< wait, breathing if current cycle great this value */\r
+ } LIMITS_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t DELAY; /*!< LED Delay */\r
+ \r
+ struct {\r
+ __IO uint32_t LOWPULSE : 12; /*!< number to wait before updating current cycle */\r
+ __IO uint32_t HIGHPULSE : 12; /*!< number to wait before updating current cycle */\r
+ } DELAY_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t UPDATE_STEPSIZE; /*!< provide amount duty cycle to adjust */\r
+ \r
+ struct {\r
+ __IO uint32_t STEP0 : 4; /*!< when the segment index is equal to 000. */\r
+ __IO uint32_t STEP1 : 4; /*!< when the segment index is equal to 001. */\r
+ __IO uint32_t STEP2 : 4; /*!< when the segment index is equal to 010. */\r
+ __IO uint32_t STEP3 : 4; /*!< when the segment index is equal to 011. */\r
+ __IO uint32_t STEP4 : 4; /*!< when the segment index is equal to 100. */\r
+ __IO uint32_t STEP5 : 4; /*!< when the segment index is equal to 101 */\r
+ __IO uint32_t STEP6 : 4; /*!< when the segment index is equal to 110. */\r
+ __IO uint32_t STEP7 : 4; /*!< when the segment index is equal to 111. */\r
+ } UPDATE_STEPSIZE_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t UPDATE_INTERVAL; /*!< LED Update Interval */\r
+ \r
+ struct {\r
+ __IO uint32_t INTERVAL0 : 4; /*!< when the segment index is equal to 000b. */\r
+ __IO uint32_t INTERVAL1 : 4; /*!< when the segment index is equal to 001b. */\r
+ __IO uint32_t INTERVAL2 : 4; /*!< when the segment index is equal to 010b. */\r
+ __IO uint32_t INTERVAL3 : 4; /*!< when the segment index is equal to 011b. */\r
+ __IO uint32_t INTERVAL4 : 4; /*!< when the segment index is equal to 100b. */\r
+ __IO uint32_t INTERVAL5 : 4; /*!< when the segment index is equal to 101b. */\r
+ __IO uint32_t INTERVAL6 : 4; /*!< when the segment index is equal to 110b. */\r
+ __IO uint32_t INTERVAL7 : 4; /*!< when the segment index is equal to 111b. */\r
+ } UPDATE_INTERVAL_b; /*!< BitSize */\r
+ };\r
+} LED_0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PS2_0 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief There are four PS/2 Ports in the MEC1320 which are directly controlled\r
+ by the EC. The hardware implementation eliminates the need to bit bang I/O ports to generate\r
+ PS/2 traffic, however bit banging is available via the associated GPIO pins. (PS2_0)\r
+ */\r
+\r
+typedef struct { /*!< PS2_0 Structure */\r
+ \r
+ union {\r
+ __I uint32_t RX_DATA; /*!< Data received from a peripheral */\r
+ __O uint32_t TX_DATA; /*!< Writes to start a transmission */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t CONTROL; /*!< PS2 Control Register */\r
+ \r
+ struct {\r
+ __IO uint32_t TR : 1; /*!< PS/2 1:Transmit, 0:Receive data */\r
+ __IO uint32_t EN : 1; /*!< 1: PS/2 Enable */\r
+ __IO uint32_t PARITY : 2; /*!< 00b=Receiver expects Odd Parity (default). */\r
+ __IO uint32_t STOP : 2; /*!< 00b=Receiver expects an active high stop bit */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t STATUS; /*!< PS2 Status Register */\r
+ \r
+ struct {\r
+ __I uint32_t RDATA_RDY : 1; /*!< Data Ready. Reading Receive data to clears */\r
+ __IO uint32_t REC_TIMEOUT: 1; /*!< REC_TIMEOUT is cleared when Status is read */\r
+ __IO uint32_t PE : 1; /*!< Parity Error */\r
+ __IO uint32_t FE : 1; /*!< Framing Error */\r
+ __I uint32_t XMIT_IDLE : 1; /*!< 0=actively transmitting PS/2 data. 1=Idle */\r
+ __IO uint32_t XMIT_TIME_OUT: 1; /*!< Transmitter Time-out */\r
+ __I uint32_t RX_BUSY : 1; /*!< 0=actively receiving PS/2 data, 1=Idle */\r
+ __IO uint32_t XMIT_START_TIMEOUT: 1; /*!< Transmit Start Timeout (over 25 ms) */\r
+ } STATUS_b; /*!< BitSize */\r
+ };\r
+} PS2_0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ KEYSCAN ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The Keyboard Scan Interface block provides a register interface to the EC\r
+ to directly scan an external keyboard matrix of size up to 18x8. (KEYSCAN)\r
+ */\r
+\r
+typedef struct { /*!< KEYSCAN Structure */\r
+ __I uint32_t RESERVED;\r
+ \r
+ union {\r
+ __IO uint32_t CONTROL; /*!< KSO Select and control */\r
+ \r
+ struct {\r
+ __IO uint32_t SELECT : 5; /*!< selects a KSO line (00000b=KSO[0] etc.) */\r
+ __IO uint32_t ALL : 1; /*!< 0=KSO_SELECT set KSO, 1=KSO[x] driven high */\r
+ __IO uint32_t KSEN : 1; /*!< 0=Keyboard scan enabled, 1=disabled. */\r
+ __IO uint32_t INVERT : 1; /*!< 0=KSO[x] driven low, 1=high when selected. */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ __I uint32_t KSI; /*!< [7:0]returns the current state of KSI pins */\r
+ __IO uint32_t STATUS; /*!< [7:0]set on falling edge of KSI */\r
+ __IO uint32_t INT_EN; /*!< [7:0]enables int due to H2L on a KSI */\r
+ __IO uint32_t EXTENDED_CONTROL; /*!< [0:0] 1=Enable predrive on KSO pins. */\r
+} KEYSCAN_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ BC_LINK ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief This block provides BC-Link connectivity to a slave device. The BC-Link protocol\r
+ includes a start bit to signal the beginning of a message and a turnaround (TAR) period\r
+ for bus transfer between the Master and Companion devices. (BC_LINK)\r
+ */\r
+\r
+typedef struct { /*!< BC_LINK Structure */\r
+ \r
+ union {\r
+ __IO uint32_t STATUS; /*!< BC-Link Status */\r
+ \r
+ struct {\r
+ __I uint32_t BUSY : 1; /*!< 1: BC is transferring data and on reset */\r
+ uint32_t : 3;\r
+ __IO uint32_t BUSY_CLR_INT_EN: 1; /*!< enable for generating an interrupt */\r
+ __IO uint32_t ERR_INT_EN : 1; /*!< enable interrupt when BC_ERR bit set */\r
+ __IO uint32_t ERROR : 1; /*!< indicates a BC Bus Error has occurred. (R/WC) */\r
+ __IO uint32_t RESET : 1; /*!< 1: Reset BC_Link Master Interface */\r
+ } STATUS_b; /*!< BitSize */\r
+ };\r
+ __IO uint32_t ADDRESS; /*!< Address in Companion for BC-Link */\r
+ __IO uint32_t DATA_REG; /*!< hold data used in a BC-Link transaction. */\r
+ __IO uint32_t CLOCK_SELECT; /*!< [7:0] DIVIDER 48MHz/ (Divider +1). */\r
+} BC_LINK_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ TFDP ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The TFDP serially transmits Embedded Controller (EC)-originated \r
+ diagnostic vectors to an external debug trace system. (TFDP)\r
+ */\r
+\r
+typedef struct { /*!< TFDP Structure */\r
+ __IO uint8_t DATA_REG; /*!< Debug data to be shifted out on TFDP port */\r
+ __I uint8_t RESERVED[3];\r
+ \r
+ union {\r
+ __IO uint8_t CONTROL; /*!< Debug Control Register */\r
+ \r
+ struct {\r
+ __IO uint8_t EN : 1; /*!< 1=Clock enabled, 0=Clock is disabled (Default) */\r
+ __IO uint8_t EDGE_SEL : 1; /*!< 1= shifted out on falling edge, 0= rising */\r
+ __IO uint8_t DIVSEL : 2; /*!< Clock Divider Select. */\r
+ __IO uint8_t IP_DELAY : 3; /*!< Inter-packet Delay. */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+} TFDP_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ ADC ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief This block is designed to convert external analog voltage readings into digital values. (ADC)\r
+ */\r
+\r
+typedef struct { /*!< ADC Structure */\r
+ \r
+ union {\r
+ __IO uint32_t CONTROL; /*!< control behavior of ADC */\r
+ \r
+ struct {\r
+ __IO uint32_t ACTIVATE : 1; /*!< 1: ADC is enabled for operation. */\r
+ __IO uint32_t START_SINGLE: 1; /*!< 1: ADC Single Mode is enabled. self-clearing */\r
+ __IO uint32_t START_REPEAT: 1; /*!< 1: ADC Repeat Mode is enabled. */\r
+ __IO uint32_t POWER_SAVER_DIS: 1; /*!< 0: Power saving enabled. 1: disabled. */\r
+ __IO uint32_t SOFT_RESET : 1; /*!< 1: reset of ADC */\r
+ uint32_t : 1;\r
+ __IO uint32_t REPEAT_DONE_STAT: 1; /*!< 1: ADC repeat conversion is completed.(R/WC) */\r
+ __IO uint32_t SINGLE_DONE_STAT: 1; /*!< 1: ADC single conversion is completed.(R/WC) */\r
+ } CONTROL_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t DELAY; /*!< delay fm set Start_Repeat and conversion */\r
+ \r
+ struct {\r
+ __IO uint32_t START : 16; /*!< start delay before conv. when Start_Repeat=1 */\r
+ __IO uint32_t REPEAT : 16; /*!< interval between conversion when Start_Repeat=1 */\r
+ } DELAY_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t STATUS; /*!< 1: conversion is complete (R/WC) */\r
+ \r
+ struct {\r
+ __IO uint32_t CH0 : 1; /*!< ADC_Ch0_Status */\r
+ __IO uint32_t CH1 : 1; /*!< ADC_Ch1_Status */\r
+ __IO uint32_t CH2 : 1; /*!< ADC_Ch2_Status */\r
+ __IO uint32_t CH3 : 1; /*!< ADC_Ch3_Status */\r
+ __IO uint32_t CH4 : 1; /*!< ADC_Ch4_Status */\r
+ } STATUS_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t SINGLE_EN; /*!< ADC Single-Sample conversion control */\r
+ \r
+ struct {\r
+ __IO uint32_t CH0 : 1; /*!< Ch0 single conversions, 1:enabled/0:disabled */\r
+ __IO uint32_t CH1 : 1; /*!< Ch1 single conversions, 1:enabled/0:disabled */\r
+ __IO uint32_t CH2 : 1; /*!< Ch2 single conversions, 1:enabled/0:disabled */\r
+ __IO uint32_t CH3 : 1; /*!< Ch3 single conversions, 1:enabled/0:disabled */\r
+ __IO uint32_t CH4 : 1; /*!< Ch4 single conversions, 1:enabled/0:disabled */\r
+ } SINGLE_EN_b; /*!< BitSize */\r
+ };\r
+ \r
+ union {\r
+ __IO uint32_t REPEAT; /*!< ADC channels repeat conversion control */\r
+ \r
+ struct {\r
+ __IO uint32_t CH0 : 1; /*!< Ch0 repeat conversions, 1:enabled/0:disabled */\r
+ __IO uint32_t CH1 : 1; /*!< Ch1 repeat conversions, 1:enabled/0:disabled */\r
+ __IO uint32_t CH2 : 1; /*!< Ch2 repeat conversions, 1:enabled/0:disabled */\r
+ __IO uint32_t CH3 : 1; /*!< Ch3 repeat conversions, 1:enabled/0:disabled */\r
+ __IO uint32_t CH4 : 1; /*!< Ch4 repeat conversions, 1:enabled/0:disabled */\r
+ } REPEAT_b; /*!< BitSize */\r
+ };\r
+ __IO uint32_t READING[5]; /*!< ADC channels 32-bit reading register. */\r
+} ADC_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ EC_REG_BANK ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief This block is designed to be accessed internally by the EC via the register interface. (EC_REG_BANK)\r
+ */\r
+\r
+typedef struct { /*!< EC_REG_BANK Structure */\r
+ __I uint32_t RESERVED[5];\r
+ __IO uint8_t AHB_ERROR_CONTROL; /*!< 1: EC memory exceptions are disabled. */\r
+ __I uint8_t RESERVED1[3];\r
+ __IO uint32_t INTERRUPT_CONTROL; /*!< 1= Alternate NVIC vectors enabled */\r
+ __IO uint32_t ETM_TRACE_ENABLE; /*!< 1= ARM TRACE port enabled */\r
+ __IO uint32_t JTAG_Enable; /*!< 1= JTAG port enabled. */\r
+ __I uint32_t RESERVED2;\r
+ __IO uint32_t WDT_EVENT_COUNT; /*!< [3:0]EC Rd/Wt are cleared to 0 on VCC1 POR */\r
+ __I uint32_t RESERVED3[3];\r
+ __IO uint32_t ADC_VREF_PD; /*!< [0:0] ADC VREF Power down. 0=on 1=off */\r
+} EC_REG_BANK_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ JTAG ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief The Controller, which is an IEEE compliant JTAG Port, has implemented all\r
+ the mandatory JTAG instructions. This interface may be used to access the embedded controller's\r
+ test access port (TAP). (JTAG)\r
+ */\r
+\r
+typedef struct { /*!< JTAG Structure */\r
+ __IO uint32_t MESSAGE_OBF; /*!< JTAG Message OBF */\r
+ __IO uint32_t MESSAGE_IBF; /*!< JTAG Message IBF */\r
+ __IO uint8_t OBF_STATUS; /*!< JTAG OBF Status */\r
+ __IO uint8_t IBF_STATUS; /*!< JTAG IBF Status */\r
+ __I uint16_t RESERVED;\r
+ __IO uint32_t DBG_CTRL; /*!< JTAG DBG Ctrl */\r
+} JTAG_Type;\r
+\r
+\r
+/*------------- Public Key Encryption Subsystem (PKE) -----------------------------*/\r
+/** @addtogroup MEC1322_PKE Public Key Encryption (PKE)\r
+ @{\r
+*/\r
+typedef struct\r
+{\r
+ __IO uint32_t CONFIG; /*!< Offset: 0x0000 Configuration */\r
+ __IO uint32_t COMMAND; /*!< Offset: 0x0004 Command */\r
+ __IO uint32_t CONTROL; /*!< Offset: 0x0008 Control */\r
+ __I uint32_t STATUS; /*!< Offset: 0x000C Status */\r
+ __I uint32_t VERSION; /*!< Offset: 0x0010 Version */\r
+ __IO uint32_t LOAD_MICRO_CODE; /*!< Offset: 0x0014 Load Micro Code */\r
+} PKE_TypeDef;\r
+/*@}*/ /* end of group MEC1322_PKE */\r
+\r
+/*------------- Random Number Generator Subsystem (TRNG) -----------------------------*/\r
+/** @addtogroup MEC1322_TRNG Random Number Generator (TRNG)\r
+ @{\r
+*/\r
+typedef struct\r
+{\r
+ __IO uint32_t CONTROL; /*!< Offset: 0x0000 Control */\r
+ __I uint32_t FIFO_LEVEL; /*!< Offset: 0x0004 FIFO Level */\r
+ __I uint32_t VERSION; /*!< Offset: 0x0008 Version */\r
+} TRNG_TypeDef;\r
+/*@}*/ /* end of group MEC1322_TRNG */\r
+\r
+/*------------- Hash Subsystem (HASH) -----------------------------*/\r
+/** @addtogroup MEC1322_HASH Hash Security (HASH)\r
+ @{\r
+*/\r
+typedef struct\r
+{\r
+ __IO uint32_t SHA_MODE; /*!< Offset: 0x0000 SHA Mode */\r
+ __IO uint32_t NB_BLOCK; /*!< Offset: 0x0004 NbBlock */\r
+ __IO uint32_t CONTROL; /*!< Offset: 0x0008 Config */\r
+ __I uint32_t STATUS; /*!< Offset: 0x000C Status, Read to clear interrupt */\r
+ __I uint32_t VERSION; /*!< Offset: 0x0010 Version */\r
+ __I uint32_t GENERIC_VALUE; /*!< Offset: 0x0014 Generic Value */\r
+ __IO uint32_t INIT_HASH_ADDR; /*!< Offset: 0x0018 Initial Hash value Address */\r
+ __IO uint32_t DATA_SOURCE_ADDR; /*!< Offset: 0x001C Data to hash Address */\r
+ __IO uint32_t HASH_RESULT_ADDR; /*!< Offset: 0x0020 Hash result address */\r
+} HASH_TypeDef;\r
+/*@}*/ /* end of group MEC1322_HASH */\r
+\r
+\r
+\r
+/*------------- Advanced Encryption Subsystem (AES) -----------------------------*/\r
+/** @addtogroup MEC1322_AES Advanced Encryption Subsys (AES)\r
+ @{\r
+*/\r
+\r
+#define AES_MAX_KEY_WLEN (8)\r
+#define AES_MAX_IV_WLEN (4)\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CONFIG; /*!< Offset: 0x0000 Configuration */\r
+ __IO uint32_t COMMAND; /*!< Offset: 0x0004 Command */\r
+ __IO uint32_t CONTROL; /*!< Offset: 0x0008 Control */\r
+ __I uint32_t STATUS; /*!< Offset: 0x000C Status */\r
+ __I uint32_t VERSION; /*!< Offset: 0x0010 Version */\r
+ __IO uint32_t NB_HEADER; /*!< Offset: 0x0014 Number of Headers */\r
+ __IO uint32_t LAST_HEADER; /*!< Offset: 0x0018 Last Header */\r
+ __IO uint32_t NB_BLOCK; /*!< Offset: 0x001C Number of Blocks */\r
+ __IO uint32_t LAST_BLOCK; /*!< Offset: 0x0020 Last Block */\r
+ __IO uint32_t DMA_IN; /*!< Offset: 0x0024 DMA Input Address */\r
+ __IO uint32_t DMA_OUT; /*!< Offset: 0x0028 DMA Output Address */\r
+ uint32_t RESERVEDA[(0xFC - 0x2C)/4 + 1];\r
+ __IO uint32_t KEY1[AES_MAX_KEY_WLEN];/*!< Offset: 0x0100 KeyIn1[159:128] \r
+ !< Offset: 0x0104 KeyIn1[191:160] \r
+ !< Offset: 0x0108 KeyIn1[223:192] \r
+ !< Offset: 0x010C KeyIn1[255:224] \r
+ !< Offset: 0x0110 KeyIn1[31:0] \r
+ !< Offset: 0x0114 KeyIn1[63:32] \r
+ !< Offset: 0x0118 KeyIn1[95:64] \r
+ !< Offset: 0x011C KeyIn1[127:96] */\r
+ __IO uint32_t IV[AES_MAX_IV_WLEN]; /*!< Offset: 0x0120 IV[31:0] \r
+ !< Offset: 0x0124 IV[63:32] \r
+ !< Offset: 0x0128 IV[95:64] \r
+ !< Offset: 0x012C IV[127:96] */\r
+ uint32_t RESERVEDB[4];\r
+ __IO uint32_t KEY2[AES_MAX_KEY_WLEN];/*!< Offset: 0x0140 KeyIn1[159:128] \r
+ !< Offset: 0x0144 KeyIn1[191:160] \r
+ !< Offset: 0x0148 KeyIn1[223:192] \r
+ !< Offset: 0x014C KeyIn1[255:224] \r
+ !< Offset: 0x0150 KeyIn1[31:0] \r
+ !< Offset: 0x0154 KeyIn1[63:32] \r
+ !< Offset: 0x0158 KeyIn1[95:64] \r
+ !< Offset: 0x015C KeyIn1[127:96] */\r
+} AES_TypeDef;\r
+/*@}*/ /* end of group MEC1322_AES */\r
+\r
+/* -------------------- End of section using anonymous unions ------------------- */\r
+#if defined(__CC_ARM)\r
+ #pragma pop\r
+#elif defined(__ICCARM__)\r
+ /* leave anonymous unions enabled */\r
+#elif defined(__GNUC__)\r
+ /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+ /* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+ #pragma warning restore\r
+#else\r
+ #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PCR' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PCR_EC_SLP_EN ------------------------------- */\r
+#define PCR_EC_SLP_EN_INT_SLP_EN_Pos (0UL) /*!< PCR EC_SLP_EN: INT_SLP_EN (Bit 0) */\r
+#define PCR_EC_SLP_EN_INT_SLP_EN_Msk (0x1UL) /*!< PCR EC_SLP_EN: INT_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_PECI_SLP_EN_Pos (1UL) /*!< PCR EC_SLP_EN: PECI_SLP_EN (Bit 1) */\r
+#define PCR_EC_SLP_EN_PECI_SLP_EN_Msk (0x2UL) /*!< PCR EC_SLP_EN: PECI_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_TACH0_SLP_EN_Pos (2UL) /*!< PCR EC_SLP_EN: TACH0_SLP_EN (Bit 2) */\r
+#define PCR_EC_SLP_EN_TACH0_SLP_EN_Msk (0x4UL) /*!< PCR EC_SLP_EN: TACH0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_PWM0_SLP_EN_Pos (4UL) /*!< PCR EC_SLP_EN: PWM0_SLP_EN (Bit 4) */\r
+#define PCR_EC_SLP_EN_PWM0_SLP_EN_Msk (0x10UL) /*!< PCR EC_SLP_EN: PWM0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_PMC_SLP_EN_Pos (5UL) /*!< PCR EC_SLP_EN: PMC_SLP_EN (Bit 5) */\r
+#define PCR_EC_SLP_EN_PMC_SLP_EN_Msk (0x20UL) /*!< PCR EC_SLP_EN: PMC_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_DMA_SLP_EN_Pos (6UL) /*!< PCR EC_SLP_EN: DMA_SLP_EN (Bit 6) */\r
+#define PCR_EC_SLP_EN_DMA_SLP_EN_Msk (0x40UL) /*!< PCR EC_SLP_EN: DMA_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_TFDP_SLP_EN_Pos (7UL) /*!< PCR EC_SLP_EN: TFDP_SLP_EN (Bit 7) */\r
+#define PCR_EC_SLP_EN_TFDP_SLP_EN_Msk (0x80UL) /*!< PCR EC_SLP_EN: TFDP_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_PROCESSOR_SLP_EN_Pos (8UL) /*!< PCR EC_SLP_EN: PROCESSOR_SLP_EN (Bit 8) */\r
+#define PCR_EC_SLP_EN_PROCESSOR_SLP_EN_Msk (0x100UL) /*!< PCR EC_SLP_EN: PROCESSOR_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_WDT_SLP_EN_Pos (9UL) /*!< PCR EC_SLP_EN: WDT_SLP_EN (Bit 9) */\r
+#define PCR_EC_SLP_EN_WDT_SLP_EN_Msk (0x200UL) /*!< PCR EC_SLP_EN: WDT_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_SMB0_SLP_EN_Pos (10UL) /*!< PCR EC_SLP_EN: SMB0_SLP_EN (Bit 10) */\r
+#define PCR_EC_SLP_EN_SMB0_SLP_EN_Msk (0x400UL) /*!< PCR EC_SLP_EN: SMB0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_TACH1_SLP_EN_Pos (11UL) /*!< PCR EC_SLP_EN: TACH1_SLP_EN (Bit 11) */\r
+#define PCR_EC_SLP_EN_TACH1_SLP_EN_Msk (0x800UL) /*!< PCR EC_SLP_EN: TACH1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_PWM1_SLP_EN_Pos (20UL) /*!< PCR EC_SLP_EN: PWM1_SLP_EN (Bit 20) */\r
+#define PCR_EC_SLP_EN_PWM1_SLP_EN_Msk (0x100000UL) /*!< PCR EC_SLP_EN: PWM1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_PWM2_SLP_EN_Pos (21UL) /*!< PCR EC_SLP_EN: PWM2_SLP_EN (Bit 21) */\r
+#define PCR_EC_SLP_EN_PWM2_SLP_EN_Msk (0x200000UL) /*!< PCR EC_SLP_EN: PWM2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_PWM3_SLP_EN_Pos (22UL) /*!< PCR EC_SLP_EN: PWM3_SLP_EN (Bit 22) */\r
+#define PCR_EC_SLP_EN_PWM3_SLP_EN_Msk (0x400000UL) /*!< PCR EC_SLP_EN: PWM3_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_EC_REG_BANK_SLP_EN_Pos (29UL) /*!< PCR EC_SLP_EN: EC_REG_BANK_SLP_EN (Bit 29) */\r
+#define PCR_EC_SLP_EN_EC_REG_BANK_SLP_EN_Msk (0x20000000UL) /*!< PCR EC_SLP_EN: EC_REG_BANK_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_TIMER16_0_SLP_EN_Pos (30UL) /*!< PCR EC_SLP_EN: TIMER16_0_SLP_EN (Bit 30) */\r
+#define PCR_EC_SLP_EN_TIMER16_0_SLP_EN_Msk (0x40000000UL) /*!< PCR EC_SLP_EN: TIMER16_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN_TIMER16_1_SLP_EN_Pos (31UL) /*!< PCR EC_SLP_EN: TIMER16_1_SLP_EN (Bit 31) */\r
+#define PCR_EC_SLP_EN_TIMER16_1_SLP_EN_Msk (0x80000000UL) /*!< PCR EC_SLP_EN: TIMER16_1_SLP_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* ----------------------------- PCR_EC_CLK_REQ_STS ----------------------------- */\r
+#define PCR_EC_CLK_REQ_STS_INT_CLK_REQ_Pos (0UL) /*!< PCR EC_CLK_REQ_STS: INT_CLK_REQ (Bit 0) */\r
+#define PCR_EC_CLK_REQ_STS_INT_CLK_REQ_Msk (0x1UL) /*!< PCR EC_CLK_REQ_STS: INT_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_PECI_CLK_REQ_Pos (1UL) /*!< PCR EC_CLK_REQ_STS: PECI_CLK_REQ (Bit 1) */\r
+#define PCR_EC_CLK_REQ_STS_PECI_CLK_REQ_Msk (0x2UL) /*!< PCR EC_CLK_REQ_STS: PECI_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_TACH0_CLK_REQ_Pos (2UL) /*!< PCR EC_CLK_REQ_STS: TACH0_CLK_REQ (Bit 2) */\r
+#define PCR_EC_CLK_REQ_STS_TACH0_CLK_REQ_Msk (0x4UL) /*!< PCR EC_CLK_REQ_STS: TACH0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_PWM0_CLK_REQ_Pos (4UL) /*!< PCR EC_CLK_REQ_STS: PWM0_CLK_REQ (Bit 4) */\r
+#define PCR_EC_CLK_REQ_STS_PWM0_CLK_REQ_Msk (0x10UL) /*!< PCR EC_CLK_REQ_STS: PWM0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_PMC_CLK_REQ_Pos (5UL) /*!< PCR EC_CLK_REQ_STS: PMC_CLK_REQ (Bit 5) */\r
+#define PCR_EC_CLK_REQ_STS_PMC_CLK_REQ_Msk (0x20UL) /*!< PCR EC_CLK_REQ_STS: PMC_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_DMA_CLK_REQ_Pos (6UL) /*!< PCR EC_CLK_REQ_STS: DMA_CLK_REQ (Bit 6) */\r
+#define PCR_EC_CLK_REQ_STS_DMA_CLK_REQ_Msk (0x40UL) /*!< PCR EC_CLK_REQ_STS: DMA_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_TFDP_CLK_REQ_Pos (7UL) /*!< PCR EC_CLK_REQ_STS: TFDP_CLK_REQ (Bit 7) */\r
+#define PCR_EC_CLK_REQ_STS_TFDP_CLK_REQ_Msk (0x80UL) /*!< PCR EC_CLK_REQ_STS: TFDP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_PROCESSOR_CLK_REQ_Pos (8UL) /*!< PCR EC_CLK_REQ_STS: PROCESSOR_CLK_REQ (Bit 8) */\r
+#define PCR_EC_CLK_REQ_STS_PROCESSOR_CLK_REQ_Msk (0x100UL) /*!< PCR EC_CLK_REQ_STS: PROCESSOR_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_WDT_CLK_REQ_Pos (9UL) /*!< PCR EC_CLK_REQ_STS: WDT_CLK_REQ (Bit 9) */\r
+#define PCR_EC_CLK_REQ_STS_WDT_CLK_REQ_Msk (0x200UL) /*!< PCR EC_CLK_REQ_STS: WDT_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_SMB0_CLK_REQ_Pos (10UL) /*!< PCR EC_CLK_REQ_STS: SMB0_CLK_REQ (Bit 10) */\r
+#define PCR_EC_CLK_REQ_STS_SMB0_CLK_REQ_Msk (0x400UL) /*!< PCR EC_CLK_REQ_STS: SMB0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_TACH1_CLK_REQ_Pos (11UL) /*!< PCR EC_CLK_REQ_STS: TACH1_CLK_REQ (Bit 11) */\r
+#define PCR_EC_CLK_REQ_STS_TACH1_CLK_REQ_Msk (0x800UL) /*!< PCR EC_CLK_REQ_STS: TACH1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_PWM1_CLK_REQ_Pos (20UL) /*!< PCR EC_CLK_REQ_STS: PWM1_CLK_REQ (Bit 20) */\r
+#define PCR_EC_CLK_REQ_STS_PWM1_CLK_REQ_Msk (0x100000UL) /*!< PCR EC_CLK_REQ_STS: PWM1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_PWM2_CLK_REQ_Pos (21UL) /*!< PCR EC_CLK_REQ_STS: PWM2_CLK_REQ (Bit 21) */\r
+#define PCR_EC_CLK_REQ_STS_PWM2_CLK_REQ_Msk (0x200000UL) /*!< PCR EC_CLK_REQ_STS: PWM2_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_PWM3_CLK_REQ_Pos (22UL) /*!< PCR EC_CLK_REQ_STS: PWM3_CLK_REQ (Bit 22) */\r
+#define PCR_EC_CLK_REQ_STS_PWM3_CLK_REQ_Msk (0x400000UL) /*!< PCR EC_CLK_REQ_STS: PWM3_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_EC_REG_BANK_CLK_REQ_Pos (29UL) /*!< PCR EC_CLK_REQ_STS: EC_REG_BANK_CLK_REQ (Bit 29) */\r
+#define PCR_EC_CLK_REQ_STS_EC_REG_BANK_CLK_REQ_Msk (0x20000000UL) /*!< PCR EC_CLK_REQ_STS: EC_REG_BANK_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_TIMER16_0_CLK_REQ_Pos (30UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_0_CLK_REQ (Bit 30) */\r
+#define PCR_EC_CLK_REQ_STS_TIMER16_0_CLK_REQ_Msk (0x40000000UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ_STS_TIMER16_1_CLK_REQ_Pos (31UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_1_CLK_REQ (Bit 31) */\r
+#define PCR_EC_CLK_REQ_STS_TIMER16_1_CLK_REQ_Msk (0x80000000UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- PCR_HOST_SLP_EN ------------------------------ */\r
+#define PCR_HOST_SLP_EN_LPC_SLP_EN_Pos (0UL) /*!< PCR HOST_SLP_EN: LPC_SLP_EN (Bit 0) */\r
+#define PCR_HOST_SLP_EN_LPC_SLP_EN_Msk (0x1UL) /*!< PCR HOST_SLP_EN: LPC_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_SLP_EN_UART_0_SLP_EN_Pos (1UL) /*!< PCR HOST_SLP_EN: UART_0_SLP_EN (Bit 1) */\r
+#define PCR_HOST_SLP_EN_UART_0_SLP_EN_Msk (0x2UL) /*!< PCR HOST_SLP_EN: UART_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_SLP_EN_GLBL_CFG_SLP_EN_Pos (12UL) /*!< PCR HOST_SLP_EN: GLBL_CFG_SLP_EN (Bit 12) */\r
+#define PCR_HOST_SLP_EN_GLBL_CFG_SLP_EN_Msk (0x1000UL) /*!< PCR HOST_SLP_EN: GLBL_CFG_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_SLP_EN_ACPI_EC_0_SLP_EN_Pos (13UL) /*!< PCR HOST_SLP_EN: ACPI_EC_0_SLP_EN (Bit 13) */\r
+#define PCR_HOST_SLP_EN_ACPI_EC_0_SLP_EN_Msk (0x2000UL) /*!< PCR HOST_SLP_EN: ACPI_EC_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_SLP_EN_ACPI_EC_1_SLP_EN_Pos (14UL) /*!< PCR HOST_SLP_EN: ACPI_EC_1_SLP_EN (Bit 14) */\r
+#define PCR_HOST_SLP_EN_ACPI_EC_1_SLP_EN_Msk (0x4000UL) /*!< PCR HOST_SLP_EN: ACPI_EC_1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_SLP_EN_ACPI_PM1_SLP_EN_Pos (15UL) /*!< PCR HOST_SLP_EN: ACPI_PM1_SLP_EN (Bit 15) */\r
+#define PCR_HOST_SLP_EN_ACPI_PM1_SLP_EN_Msk (0x8000UL) /*!< PCR HOST_SLP_EN: ACPI_PM1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_SLP_EN_KBCEM_SLP_EN_Pos (16UL) /*!< PCR HOST_SLP_EN: KBCEM_SLP_EN (Bit 16) */\r
+#define PCR_HOST_SLP_EN_KBCEM_SLP_EN_Msk (0x10000UL) /*!< PCR HOST_SLP_EN: KBCEM_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_SLP_EN_RTC_SLP_EN_Pos (18UL) /*!< PCR HOST_SLP_EN: RTC_SLP_EN (Bit 18) */\r
+#define PCR_HOST_SLP_EN_RTC_SLP_EN_Msk (0x40000UL) /*!< PCR HOST_SLP_EN: RTC_SLP_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ PCR_HOST_CLK_REQ ------------------------------ */\r
+#define PCR_HOST_CLK_REQ_LPC_CLK_REQ_Pos (0UL) /*!< PCR HOST_CLK_REQ: LPC_CLK_REQ (Bit 0) */\r
+#define PCR_HOST_CLK_REQ_LPC_CLK_REQ_Msk (0x1UL) /*!< PCR HOST_CLK_REQ: LPC_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_CLK_REQ_UART_0_CLK_REQ_Pos (1UL) /*!< PCR HOST_CLK_REQ: UART_0_CLK_REQ (Bit 1) */\r
+#define PCR_HOST_CLK_REQ_UART_0_CLK_REQ_Msk (0x2UL) /*!< PCR HOST_CLK_REQ: UART_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_CLK_REQ_GLBL_CFG_CLK_REQ_Pos (12UL) /*!< PCR HOST_CLK_REQ: GLBL_CFG_CLK_REQ (Bit 12) */\r
+#define PCR_HOST_CLK_REQ_GLBL_CFG_CLK_REQ_Msk (0x1000UL) /*!< PCR HOST_CLK_REQ: GLBL_CFG_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_CLK_REQ_ACPI_EC_0_CLK_REQ_Pos (13UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_0_CLK_REQ (Bit 13) */\r
+#define PCR_HOST_CLK_REQ_ACPI_EC_0_CLK_REQ_Msk (0x2000UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_0_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_CLK_REQ_ACPI_EC_1_CLK_REQ_Pos (14UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_1_CLK_REQ (Bit 14) */\r
+#define PCR_HOST_CLK_REQ_ACPI_EC_1_CLK_REQ_Msk (0x4000UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_CLK_REQ_ACPI_PM1_CLK_REQ_Pos (15UL) /*!< PCR HOST_CLK_REQ: ACPI_PM1_CLK_REQ (Bit 15) */\r
+#define PCR_HOST_CLK_REQ_ACPI_PM1_CLK_REQ_Msk (0x8000UL) /*!< PCR HOST_CLK_REQ: ACPI_PM1_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_CLK_REQ_KBCEM_CLK_REQ_Pos (16UL) /*!< PCR HOST_CLK_REQ: KBCEM_CLK_REQ (Bit 16) */\r
+#define PCR_HOST_CLK_REQ_KBCEM_CLK_REQ_Msk (0x10000UL) /*!< PCR HOST_CLK_REQ: KBCEM_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_CLK_REQ_RTC_CLK_REQ_Pos (18UL) /*!< PCR HOST_CLK_REQ: RTC_CLK_REQ (Bit 18) */\r
+#define PCR_HOST_CLK_REQ_RTC_CLK_REQ_Msk (0x40000UL) /*!< PCR HOST_CLK_REQ: RTC_CLK_REQ (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ PCR_SYS_SLP_CNTRL ----------------------------- */\r
+#define PCR_SYS_SLP_CNTRL_ROSC_PD_Pos (0UL) /*!< PCR SYS_SLP_CNTRL: ROSC_PD (Bit 0) */\r
+#define PCR_SYS_SLP_CNTRL_ROSC_PD_Msk (0x1UL) /*!< PCR SYS_SLP_CNTRL: ROSC_PD (Bitfield-Mask: 0x01) */\r
+#define PCR_SYS_SLP_CNTRL_ROSC_GATE_Pos (1UL) /*!< PCR SYS_SLP_CNTRL: ROSC_GATE (Bit 1) */\r
+#define PCR_SYS_SLP_CNTRL_ROSC_GATE_Msk (0x2UL) /*!< PCR SYS_SLP_CNTRL: ROSC_GATE (Bitfield-Mask: 0x01) */\r
+#define PCR_SYS_SLP_CNTRL_REGULATOR_STDBY_Pos (2UL) /*!< PCR SYS_SLP_CNTRL: REGULATOR_STDBY (Bit 2) */\r
+#define PCR_SYS_SLP_CNTRL_REGULATOR_STDBY_Msk (0x4UL) /*!< PCR SYS_SLP_CNTRL: REGULATOR_STDBY (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- PCR_EC_SLP_EN2 ------------------------------- */\r
+#define PCR_EC_SLP_EN2_ADC_SLP_EN_Pos (3UL) /*!< PCR EC_SLP_EN2: ADC_SLP_EN (Bit 3) */\r
+#define PCR_EC_SLP_EN2_ADC_SLP_EN_Msk (0x8UL) /*!< PCR EC_SLP_EN2: ADC_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_PS2_0_SLP_EN_Pos (5UL) /*!< PCR EC_SLP_EN2: PS2_0_SLP_EN (Bit 5) */\r
+#define PCR_EC_SLP_EN2_PS2_0_SLP_EN_Msk (0x20UL) /*!< PCR EC_SLP_EN2: PS2_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_PS2_1_SLP_EN_Pos (6UL) /*!< PCR EC_SLP_EN2: PS2_1_SLP_EN (Bit 6) */\r
+#define PCR_EC_SLP_EN2_PS2_1_SLP_EN_Msk (0x40UL) /*!< PCR EC_SLP_EN2: PS2_1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_PS2_2_SLP_EN_Pos (7UL) /*!< PCR EC_SLP_EN2: PS2_2_SLP_EN (Bit 7) */\r
+#define PCR_EC_SLP_EN2_PS2_2_SLP_EN_Msk (0x80UL) /*!< PCR EC_SLP_EN2: PS2_2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_PS2_3_SLP_EN_Pos (8UL) /*!< PCR EC_SLP_EN2: PS2_3_SLP_EN (Bit 8) */\r
+#define PCR_EC_SLP_EN2_PS2_3_SLP_EN_Msk (0x100UL) /*!< PCR EC_SLP_EN2: PS2_3_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_SPI0_SLP_EN_Pos (9UL) /*!< PCR EC_SLP_EN2: SPI0_SLP_EN (Bit 9) */\r
+#define PCR_EC_SLP_EN2_SPI0_SLP_EN_Msk (0x200UL) /*!< PCR EC_SLP_EN2: SPI0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_HTIMER_SLP_EN_Pos (10UL) /*!< PCR EC_SLP_EN2: HTIMER_SLP_EN (Bit 10) */\r
+#define PCR_EC_SLP_EN2_HTIMER_SLP_EN_Msk (0x400UL) /*!< PCR EC_SLP_EN2: HTIMER_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_KEYSCAN_SLP_EN_Pos (11UL) /*!< PCR EC_SLP_EN2: KEYSCAN_SLP_EN (Bit 11) */\r
+#define PCR_EC_SLP_EN2_KEYSCAN_SLP_EN_Msk (0x800UL) /*!< PCR EC_SLP_EN2: KEYSCAN_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_RPMPWM_SLP_EN_Pos (12UL) /*!< PCR EC_SLP_EN2: RPMPWM_SLP_EN (Bit 12) */\r
+#define PCR_EC_SLP_EN2_RPMPWM_SLP_EN_Msk (0x1000UL) /*!< PCR EC_SLP_EN2: RPMPWM_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_SMB1_SLP_EN_Pos (13UL) /*!< PCR EC_SLP_EN2: SMB1_SLP_EN (Bit 13) */\r
+#define PCR_EC_SLP_EN2_SMB1_SLP_EN_Msk (0x2000UL) /*!< PCR EC_SLP_EN2: SMB1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_SMB2_SLP_EN_Pos (14UL) /*!< PCR EC_SLP_EN2: SMB2_SLP_EN (Bit 14) */\r
+#define PCR_EC_SLP_EN2_SMB2_SLP_EN_Msk (0x4000UL) /*!< PCR EC_SLP_EN2: SMB2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_SMB3_SLP_EN_Pos (15UL) /*!< PCR EC_SLP_EN2: SMB3_SLP_EN (Bit 15) */\r
+#define PCR_EC_SLP_EN2_SMB3_SLP_EN_Msk (0x8000UL) /*!< PCR EC_SLP_EN2: SMB3_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_LED0_SLP_EN_Pos (16UL) /*!< PCR EC_SLP_EN2: LED0_SLP_EN (Bit 16) */\r
+#define PCR_EC_SLP_EN2_LED0_SLP_EN_Msk (0x10000UL) /*!< PCR EC_SLP_EN2: LED0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_LED1_SLP_EN_Pos (17UL) /*!< PCR EC_SLP_EN2: LED1_SLP_EN (Bit 17) */\r
+#define PCR_EC_SLP_EN2_LED1_SLP_EN_Msk (0x20000UL) /*!< PCR EC_SLP_EN2: LED1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_LED2_SLP_EN_Pos (18UL) /*!< PCR EC_SLP_EN2: LED2_SLP_EN (Bit 18) */\r
+#define PCR_EC_SLP_EN2_LED2_SLP_EN_Msk (0x40000UL) /*!< PCR EC_SLP_EN2: LED2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_BCM_SLP_EN_Pos (19UL) /*!< PCR EC_SLP_EN2: BCM_SLP_EN (Bit 19) */\r
+#define PCR_EC_SLP_EN2_BCM_SLP_EN_Msk (0x80000UL) /*!< PCR EC_SLP_EN2: BCM_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_SPI1_SLP_EN_Pos (20UL) /*!< PCR EC_SLP_EN2: SPI1_SLP_EN (Bit 20) */\r
+#define PCR_EC_SLP_EN2_SPI1_SLP_EN_Msk (0x100000UL) /*!< PCR EC_SLP_EN2: SPI1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_TIMER16_2_SLP_EN_Pos (21UL) /*!< PCR EC_SLP_EN2: TIMER16_2_SLP_EN (Bit 21) */\r
+#define PCR_EC_SLP_EN2_TIMER16_2_SLP_EN_Msk (0x200000UL) /*!< PCR EC_SLP_EN2: TIMER16_2_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_TIMER16_3_SLP_EN_Pos (22UL) /*!< PCR EC_SLP_EN2: TIMER16_3_SLP_EN (Bit 22) */\r
+#define PCR_EC_SLP_EN2_TIMER16_3_SLP_EN_Msk (0x400000UL) /*!< PCR EC_SLP_EN2: TIMER16_3_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_TIMER32_0_SLP_EN_Pos (23UL) /*!< PCR EC_SLP_EN2: TIMER32_0_SLP_EN (Bit 23) */\r
+#define PCR_EC_SLP_EN2_TIMER32_0_SLP_EN_Msk (0x800000UL) /*!< PCR EC_SLP_EN2: TIMER32_0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_TIMER32_1_SLP_EN_Pos (24UL) /*!< PCR EC_SLP_EN2: TIMER32_1_SLP_EN (Bit 24) */\r
+#define PCR_EC_SLP_EN2_TIMER32_1_SLP_EN_Msk (0x1000000UL) /*!< PCR EC_SLP_EN2: TIMER32_1_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_SLP_EN2_LED3_SLP_EN_Pos (25UL) /*!< PCR EC_SLP_EN2: LED3_SLP_EN (Bit 25) */\r
+#define PCR_EC_SLP_EN2_LED3_SLP_EN_Msk (0x2000000UL) /*!< PCR EC_SLP_EN2: LED3_SLP_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* ----------------------------- PCR_EC_CLK_REQ2_STS ---------------------------- */\r
+#define PCR_EC_CLK_REQ2_STS_ADC_CLK_REQ_Pos (3UL) /*!< PCR EC_CLK_REQ2_STS: ADC_CLK_REQ (Bit 3) */\r
+#define PCR_EC_CLK_REQ2_STS_ADC_CLK_REQ_Msk (0x8UL) /*!< PCR EC_CLK_REQ2_STS: ADC_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_PS2_0_SLP_CLK_REQ_Pos (5UL) /*!< PCR EC_CLK_REQ2_STS: PS2_0_SLP_CLK_REQ (Bit 5) */\r
+#define PCR_EC_CLK_REQ2_STS_PS2_0_SLP_CLK_REQ_Msk (0x20UL) /*!< PCR EC_CLK_REQ2_STS: PS2_0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_PS2_1_SLP_CLK_REQ_Pos (6UL) /*!< PCR EC_CLK_REQ2_STS: PS2_1_SLP_CLK_REQ (Bit 6) */\r
+#define PCR_EC_CLK_REQ2_STS_PS2_1_SLP_CLK_REQ_Msk (0x40UL) /*!< PCR EC_CLK_REQ2_STS: PS2_1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_PS2_2_SLP_CLK_REQ_Pos (7UL) /*!< PCR EC_CLK_REQ2_STS: PS2_2_SLP_CLK_REQ (Bit 7) */\r
+#define PCR_EC_CLK_REQ2_STS_PS2_2_SLP_CLK_REQ_Msk (0x80UL) /*!< PCR EC_CLK_REQ2_STS: PS2_2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_PS2_3_SLP_CLK_REQ_Pos (8UL) /*!< PCR EC_CLK_REQ2_STS: PS2_3_SLP_CLK_REQ (Bit 8) */\r
+#define PCR_EC_CLK_REQ2_STS_PS2_3_SLP_CLK_REQ_Msk (0x100UL) /*!< PCR EC_CLK_REQ2_STS: PS2_3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_SPI0_SLP_CLK_REQ_Pos (9UL) /*!< PCR EC_CLK_REQ2_STS: SPI0_SLP_CLK_REQ (Bit 9) */\r
+#define PCR_EC_CLK_REQ2_STS_SPI0_SLP_CLK_REQ_Msk (0x200UL) /*!< PCR EC_CLK_REQ2_STS: SPI0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_HTIMER_SLP_CLK_REQ_Pos (10UL) /*!< PCR EC_CLK_REQ2_STS: HTIMER_SLP_CLK_REQ (Bit 10) */\r
+#define PCR_EC_CLK_REQ2_STS_HTIMER_SLP_CLK_REQ_Msk (0x400UL) /*!< PCR EC_CLK_REQ2_STS: HTIMER_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_KEYSCAN_SLP_CLK_REQ_Pos (11UL) /*!< PCR EC_CLK_REQ2_STS: KEYSCAN_SLP_CLK_REQ (Bit 11) */\r
+#define PCR_EC_CLK_REQ2_STS_KEYSCAN_SLP_CLK_REQ_Msk (0x800UL) /*!< PCR EC_CLK_REQ2_STS: KEYSCAN_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_RPMPWM_SLP_CLK_REQ_Pos (12UL) /*!< PCR EC_CLK_REQ2_STS: RPMPWM_SLP_CLK_REQ (Bit 12) */\r
+#define PCR_EC_CLK_REQ2_STS_RPMPWM_SLP_CLK_REQ_Msk (0x1000UL) /*!< PCR EC_CLK_REQ2_STS: RPMPWM_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_SMB1_SLP_CLK_REQ_Pos (13UL) /*!< PCR EC_CLK_REQ2_STS: SMB1_SLP_CLK_REQ (Bit 13) */\r
+#define PCR_EC_CLK_REQ2_STS_SMB1_SLP_CLK_REQ_Msk (0x2000UL) /*!< PCR EC_CLK_REQ2_STS: SMB1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_SMB2_SLP_CLK_REQ_Pos (14UL) /*!< PCR EC_CLK_REQ2_STS: SMB2_SLP_CLK_REQ (Bit 14) */\r
+#define PCR_EC_CLK_REQ2_STS_SMB2_SLP_CLK_REQ_Msk (0x4000UL) /*!< PCR EC_CLK_REQ2_STS: SMB2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_SMB3_SLP_CLK_REQ_Pos (15UL) /*!< PCR EC_CLK_REQ2_STS: SMB3_SLP_CLK_REQ (Bit 15) */\r
+#define PCR_EC_CLK_REQ2_STS_SMB3_SLP_CLK_REQ_Msk (0x8000UL) /*!< PCR EC_CLK_REQ2_STS: SMB3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_LED0_SLP_CLK_REQ_Pos (16UL) /*!< PCR EC_CLK_REQ2_STS: LED0_SLP_CLK_REQ (Bit 16) */\r
+#define PCR_EC_CLK_REQ2_STS_LED0_SLP_CLK_REQ_Msk (0x10000UL) /*!< PCR EC_CLK_REQ2_STS: LED0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_LED1_SLP_CLK_REQ_Pos (17UL) /*!< PCR EC_CLK_REQ2_STS: LED1_SLP_CLK_REQ (Bit 17) */\r
+#define PCR_EC_CLK_REQ2_STS_LED1_SLP_CLK_REQ_Msk (0x20000UL) /*!< PCR EC_CLK_REQ2_STS: LED1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_LED2_SLP_CLK_REQ_Pos (18UL) /*!< PCR EC_CLK_REQ2_STS: LED2_SLP_CLK_REQ (Bit 18) */\r
+#define PCR_EC_CLK_REQ2_STS_LED2_SLP_CLK_REQ_Msk (0x40000UL) /*!< PCR EC_CLK_REQ2_STS: LED2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_BCM_SLP_CLK_REQ_Pos (19UL) /*!< PCR EC_CLK_REQ2_STS: BCM_SLP_CLK_REQ (Bit 19) */\r
+#define PCR_EC_CLK_REQ2_STS_BCM_SLP_CLK_REQ_Msk (0x80000UL) /*!< PCR EC_CLK_REQ2_STS: BCM_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_SPI1_SLP_CLK_REQ_Pos (20UL) /*!< PCR EC_CLK_REQ2_STS: SPI1_SLP_CLK_REQ (Bit 20) */\r
+#define PCR_EC_CLK_REQ2_STS_SPI1_SLP_CLK_REQ_Msk (0x100000UL) /*!< PCR EC_CLK_REQ2_STS: SPI1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_TIMER16_2_SLP_CLK_REQ_Pos (21UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_2_SLP_CLK_REQ (Bit 21) */\r
+#define PCR_EC_CLK_REQ2_STS_TIMER16_2_SLP_CLK_REQ_Msk (0x200000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_TIMER16_3_SLP_CLK_REQ_Pos (22UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_3_SLP_CLK_REQ (Bit 22) */\r
+#define PCR_EC_CLK_REQ2_STS_TIMER16_3_SLP_CLK_REQ_Msk (0x400000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_TIMER32_0_SLP_CLK_REQ_Pos (23UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_0_SLP_CLK_REQ (Bit 23) */\r
+#define PCR_EC_CLK_REQ2_STS_TIMER32_0_SLP_CLK_REQ_Msk (0x800000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_TIMER32_1_SLP_CLK_REQ_Pos (24UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_1_SLP_CLK_REQ (Bit 24) */\r
+#define PCR_EC_CLK_REQ2_STS_TIMER32_1_SLP_CLK_REQ_Msk (0x1000000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_CLK_REQ2_STS_LED3_SLP_CLK_REQ_Pos (25UL) /*!< PCR EC_CLK_REQ2_STS: LED3_SLP_CLK_REQ (Bit 25) */\r
+#define PCR_EC_CLK_REQ2_STS_LED3_SLP_CLK_REQ_Msk (0x2000000UL) /*!< PCR EC_CLK_REQ2_STS: LED3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- PCR_CHIP_OSC_ID ------------------------------ */\r
+#define PCR_CHIP_OSC_ID_OSC_LOCK_Pos (8UL) /*!< PCR CHIP_OSC_ID: OSC_LOCK (Bit 8) */\r
+#define PCR_CHIP_OSC_ID_OSC_LOCK_Msk (0x100UL) /*!< PCR CHIP_OSC_ID: OSC_LOCK (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------- PCR_CHIP_PWR_RST_STS ---------------------------- */\r
+#define PCR_CHIP_PWR_RST_STS_VCC_nRST_Pos (2UL) /*!< PCR CHIP_PWR_RST_STS: VCC_nRST (Bit 2) */\r
+#define PCR_CHIP_PWR_RST_STS_VCC_nRST_Msk (0x4UL) /*!< PCR CHIP_PWR_RST_STS: VCC_nRST (Bitfield-Mask: 0x01) */\r
+#define PCR_CHIP_PWR_RST_STS_SIO_nRST_Pos (3UL) /*!< PCR CHIP_PWR_RST_STS: SIO_nRST (Bit 3) */\r
+#define PCR_CHIP_PWR_RST_STS_SIO_nRST_Msk (0x8UL) /*!< PCR CHIP_PWR_RST_STS: SIO_nRST (Bitfield-Mask: 0x01) */\r
+#define PCR_CHIP_PWR_RST_STS_VBAT_RST_Pos (5UL) /*!< PCR CHIP_PWR_RST_STS: VBAT_RST (Bit 5) */\r
+#define PCR_CHIP_PWR_RST_STS_VBAT_RST_Msk (0x20UL) /*!< PCR CHIP_PWR_RST_STS: VBAT_RST (Bitfield-Mask: 0x01) */\r
+#define PCR_CHIP_PWR_RST_STS_VCC1_RST_Pos (6UL) /*!< PCR CHIP_PWR_RST_STS: VCC1_RST (Bit 6) */\r
+#define PCR_CHIP_PWR_RST_STS_VCC1_RST_Msk (0x40UL) /*!< PCR CHIP_PWR_RST_STS: VCC1_RST (Bitfield-Mask: 0x01) */\r
+#define PCR_CHIP_PWR_RST_STS__32K_ACTIVE_Pos (10UL) /*!< PCR CHIP_PWR_RST_STS: _32K_ACTIVE (Bit 10) */\r
+#define PCR_CHIP_PWR_RST_STS__32K_ACTIVE_Msk (0x400UL) /*!< PCR CHIP_PWR_RST_STS: _32K_ACTIVE (Bitfield-Mask: 0x01) */\r
+#define PCR_CHIP_PWR_RST_STS_PCICLK_ACTIVE_Pos (11UL) /*!< PCR CHIP_PWR_RST_STS: PCICLK_ACTIVE (Bit 11) */\r
+#define PCR_CHIP_PWR_RST_STS_PCICLK_ACTIVE_Msk (0x800UL) /*!< PCR CHIP_PWR_RST_STS: PCICLK_ACTIVE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- PCR_HOST_RST_EN ------------------------------ */\r
+#define PCR_HOST_RST_EN_LPC_RST_EN_Pos (0UL) /*!< PCR HOST_RST_EN: LPC_RST_EN (Bit 0) */\r
+#define PCR_HOST_RST_EN_LPC_RST_EN_Msk (0x1UL) /*!< PCR HOST_RST_EN: LPC_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_RST_EN_UART_0_RST_EN_Pos (1UL) /*!< PCR HOST_RST_EN: UART_0_RST_EN (Bit 1) */\r
+#define PCR_HOST_RST_EN_UART_0_RST_EN_Msk (0x2UL) /*!< PCR HOST_RST_EN: UART_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_RST_EN_GLBL_CFG_RST_EN_Pos (12UL) /*!< PCR HOST_RST_EN: GLBL_CFG_RST_EN (Bit 12) */\r
+#define PCR_HOST_RST_EN_GLBL_CFG_RST_EN_Msk (0x1000UL) /*!< PCR HOST_RST_EN: GLBL_CFG_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_RST_EN_ACPI_EC_0_RST_EN_Pos (13UL) /*!< PCR HOST_RST_EN: ACPI_EC_0_RST_EN (Bit 13) */\r
+#define PCR_HOST_RST_EN_ACPI_EC_0_RST_EN_Msk (0x2000UL) /*!< PCR HOST_RST_EN: ACPI_EC_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_RST_EN_ACPI_EC_1_RST_EN_Pos (14UL) /*!< PCR HOST_RST_EN: ACPI_EC_1_RST_EN (Bit 14) */\r
+#define PCR_HOST_RST_EN_ACPI_EC_1_RST_EN_Msk (0x4000UL) /*!< PCR HOST_RST_EN: ACPI_EC_1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_RST_EN_ACPI_PM1_RST_EN_Pos (15UL) /*!< PCR HOST_RST_EN: ACPI_PM1_RST_EN (Bit 15) */\r
+#define PCR_HOST_RST_EN_ACPI_PM1_RST_EN_Msk (0x8000UL) /*!< PCR HOST_RST_EN: ACPI_PM1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_RST_EN_KBCEM_RST_EN_Pos (16UL) /*!< PCR HOST_RST_EN: KBCEM_RST_EN (Bit 16) */\r
+#define PCR_HOST_RST_EN_KBCEM_RST_EN_Msk (0x10000UL) /*!< PCR HOST_RST_EN: KBCEM_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_HOST_RST_EN_RTC_RST_EN_Pos (18UL) /*!< PCR HOST_RST_EN: RTC_RST_EN (Bit 18) */\r
+#define PCR_HOST_RST_EN_RTC_RST_EN_Msk (0x40000UL) /*!< PCR HOST_RST_EN: RTC_RST_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PCR_EC_RST_EN ------------------------------- */\r
+#define PCR_EC_RST_EN_INT_RST_EN_Pos (0UL) /*!< PCR EC_RST_EN: INT_RST_EN (Bit 0) */\r
+#define PCR_EC_RST_EN_INT_RST_EN_Msk (0x1UL) /*!< PCR EC_RST_EN: INT_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_PECI_RST_EN_Pos (1UL) /*!< PCR EC_RST_EN: PECI_RST_EN (Bit 1) */\r
+#define PCR_EC_RST_EN_PECI_RST_EN_Msk (0x2UL) /*!< PCR EC_RST_EN: PECI_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_TACH0_RST_EN_Pos (2UL) /*!< PCR EC_RST_EN: TACH0_RST_EN (Bit 2) */\r
+#define PCR_EC_RST_EN_TACH0_RST_EN_Msk (0x4UL) /*!< PCR EC_RST_EN: TACH0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_PWM0_RST_EN_Pos (4UL) /*!< PCR EC_RST_EN: PWM0_RST_EN (Bit 4) */\r
+#define PCR_EC_RST_EN_PWM0_RST_EN_Msk (0x10UL) /*!< PCR EC_RST_EN: PWM0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_PMC_RST_EN_Pos (5UL) /*!< PCR EC_RST_EN: PMC_RST_EN (Bit 5) */\r
+#define PCR_EC_RST_EN_PMC_RST_EN_Msk (0x20UL) /*!< PCR EC_RST_EN: PMC_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_DMA_RST_EN_Pos (6UL) /*!< PCR EC_RST_EN: DMA_RST_EN (Bit 6) */\r
+#define PCR_EC_RST_EN_DMA_RST_EN_Msk (0x40UL) /*!< PCR EC_RST_EN: DMA_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_TFDP_RST_EN_Pos (7UL) /*!< PCR EC_RST_EN: TFDP_RST_EN (Bit 7) */\r
+#define PCR_EC_RST_EN_TFDP_RST_EN_Msk (0x80UL) /*!< PCR EC_RST_EN: TFDP_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_PROCESSOR_RST_EN_Pos (8UL) /*!< PCR EC_RST_EN: PROCESSOR_RST_EN (Bit 8) */\r
+#define PCR_EC_RST_EN_PROCESSOR_RST_EN_Msk (0x100UL) /*!< PCR EC_RST_EN: PROCESSOR_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_WDT_RST_EN_Pos (9UL) /*!< PCR EC_RST_EN: WDT_RST_EN (Bit 9) */\r
+#define PCR_EC_RST_EN_WDT_RST_EN_Msk (0x200UL) /*!< PCR EC_RST_EN: WDT_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_SMB0_RST_EN_Pos (10UL) /*!< PCR EC_RST_EN: SMB0_RST_EN (Bit 10) */\r
+#define PCR_EC_RST_EN_SMB0_RST_EN_Msk (0x400UL) /*!< PCR EC_RST_EN: SMB0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_TACH1_RST_EN_Pos (11UL) /*!< PCR EC_RST_EN: TACH1_RST_EN (Bit 11) */\r
+#define PCR_EC_RST_EN_TACH1_RST_EN_Msk (0x800UL) /*!< PCR EC_RST_EN: TACH1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_PWM1_RST_EN_Pos (20UL) /*!< PCR EC_RST_EN: PWM1_RST_EN (Bit 20) */\r
+#define PCR_EC_RST_EN_PWM1_RST_EN_Msk (0x100000UL) /*!< PCR EC_RST_EN: PWM1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_PWM2_RST_EN_Pos (21UL) /*!< PCR EC_RST_EN: PWM2_RST_EN (Bit 21) */\r
+#define PCR_EC_RST_EN_PWM2_RST_EN_Msk (0x200000UL) /*!< PCR EC_RST_EN: PWM2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_PWM3_RST_EN_Pos (22UL) /*!< PCR EC_RST_EN: PWM3_RST_EN (Bit 22) */\r
+#define PCR_EC_RST_EN_PWM3_RST_EN_Msk (0x400000UL) /*!< PCR EC_RST_EN: PWM3_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_EC_REG_BANK_RST_EN_Pos (29UL) /*!< PCR EC_RST_EN: EC_REG_BANK_RST_EN (Bit 29) */\r
+#define PCR_EC_RST_EN_EC_REG_BANK_RST_EN_Msk (0x20000000UL) /*!< PCR EC_RST_EN: EC_REG_BANK_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_TIMER16_0_RST_EN_Pos (30UL) /*!< PCR EC_RST_EN: TIMER16_0_RST_EN (Bit 30) */\r
+#define PCR_EC_RST_EN_TIMER16_0_RST_EN_Msk (0x40000000UL) /*!< PCR EC_RST_EN: TIMER16_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN_TIMER16_1_RST_EN_Pos (31UL) /*!< PCR EC_RST_EN: TIMER16_1_RST_EN (Bit 31) */\r
+#define PCR_EC_RST_EN_TIMER16_1_RST_EN_Msk (0x80000000UL) /*!< PCR EC_RST_EN: TIMER16_1_RST_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- PCR_EC_RST_EN2 ------------------------------- */\r
+#define PCR_EC_RST_EN2_ADC_RST_EN_Pos (3UL) /*!< PCR EC_RST_EN2: ADC_RST_EN (Bit 3) */\r
+#define PCR_EC_RST_EN2_ADC_RST_EN_Msk (0x8UL) /*!< PCR EC_RST_EN2: ADC_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_PS2_0_RST_EN_Pos (5UL) /*!< PCR EC_RST_EN2: PS2_0_RST_EN (Bit 5) */\r
+#define PCR_EC_RST_EN2_PS2_0_RST_EN_Msk (0x20UL) /*!< PCR EC_RST_EN2: PS2_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_PS2_1_RST_EN_Pos (6UL) /*!< PCR EC_RST_EN2: PS2_1_RST_EN (Bit 6) */\r
+#define PCR_EC_RST_EN2_PS2_1_RST_EN_Msk (0x40UL) /*!< PCR EC_RST_EN2: PS2_1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_PS2_2_RST_EN_Pos (7UL) /*!< PCR EC_RST_EN2: PS2_2_RST_EN (Bit 7) */\r
+#define PCR_EC_RST_EN2_PS2_2_RST_EN_Msk (0x80UL) /*!< PCR EC_RST_EN2: PS2_2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_PS2_3_RST_EN_Pos (8UL) /*!< PCR EC_RST_EN2: PS2_3_RST_EN (Bit 8) */\r
+#define PCR_EC_RST_EN2_PS2_3_RST_EN_Msk (0x100UL) /*!< PCR EC_RST_EN2: PS2_3_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_SPI0_SLP_EN_Pos (9UL) /*!< PCR EC_RST_EN2: SPI0_SLP_EN (Bit 9) */\r
+#define PCR_EC_RST_EN2_SPI0_SLP_EN_Msk (0x200UL) /*!< PCR EC_RST_EN2: SPI0_SLP_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_HTIMER_RST_EN_Pos (10UL) /*!< PCR EC_RST_EN2: HTIMER_RST_EN (Bit 10) */\r
+#define PCR_EC_RST_EN2_HTIMER_RST_EN_Msk (0x400UL) /*!< PCR EC_RST_EN2: HTIMER_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_KEYSCAN_RST_EN_Pos (11UL) /*!< PCR EC_RST_EN2: KEYSCAN_RST_EN (Bit 11) */\r
+#define PCR_EC_RST_EN2_KEYSCAN_RST_EN_Msk (0x800UL) /*!< PCR EC_RST_EN2: KEYSCAN_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_RPMPWM_RST_EN_Pos (12UL) /*!< PCR EC_RST_EN2: RPMPWM_RST_EN (Bit 12) */\r
+#define PCR_EC_RST_EN2_RPMPWM_RST_EN_Msk (0x1000UL) /*!< PCR EC_RST_EN2: RPMPWM_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_SMB1_RST_EN_Pos (13UL) /*!< PCR EC_RST_EN2: SMB1_RST_EN (Bit 13) */\r
+#define PCR_EC_RST_EN2_SMB1_RST_EN_Msk (0x2000UL) /*!< PCR EC_RST_EN2: SMB1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_SMB2_RST_EN_Pos (14UL) /*!< PCR EC_RST_EN2: SMB2_RST_EN (Bit 14) */\r
+#define PCR_EC_RST_EN2_SMB2_RST_EN_Msk (0x4000UL) /*!< PCR EC_RST_EN2: SMB2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_SMB3_RST_EN_Pos (15UL) /*!< PCR EC_RST_EN2: SMB3_RST_EN (Bit 15) */\r
+#define PCR_EC_RST_EN2_SMB3_RST_EN_Msk (0x8000UL) /*!< PCR EC_RST_EN2: SMB3_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_LED0_RST_EN_Pos (16UL) /*!< PCR EC_RST_EN2: LED0_RST_EN (Bit 16) */\r
+#define PCR_EC_RST_EN2_LED0_RST_EN_Msk (0x10000UL) /*!< PCR EC_RST_EN2: LED0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_LED1_RST_EN_Pos (17UL) /*!< PCR EC_RST_EN2: LED1_RST_EN (Bit 17) */\r
+#define PCR_EC_RST_EN2_LED1_RST_EN_Msk (0x20000UL) /*!< PCR EC_RST_EN2: LED1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_LED2_RST_EN_Pos (18UL) /*!< PCR EC_RST_EN2: LED2_RST_EN (Bit 18) */\r
+#define PCR_EC_RST_EN2_LED2_RST_EN_Msk (0x40000UL) /*!< PCR EC_RST_EN2: LED2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_BCM_RST_EN_Pos (19UL) /*!< PCR EC_RST_EN2: BCM_RST_EN (Bit 19) */\r
+#define PCR_EC_RST_EN2_BCM_RST_EN_Msk (0x80000UL) /*!< PCR EC_RST_EN2: BCM_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_SPI1_RST_EN_Pos (20UL) /*!< PCR EC_RST_EN2: SPI1_RST_EN (Bit 20) */\r
+#define PCR_EC_RST_EN2_SPI1_RST_EN_Msk (0x100000UL) /*!< PCR EC_RST_EN2: SPI1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_TIMER16_2_RST_EN_Pos (21UL) /*!< PCR EC_RST_EN2: TIMER16_2_RST_EN (Bit 21) */\r
+#define PCR_EC_RST_EN2_TIMER16_2_RST_EN_Msk (0x200000UL) /*!< PCR EC_RST_EN2: TIMER16_2_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_TIMER16_3_RST_EN_Pos (22UL) /*!< PCR EC_RST_EN2: TIMER16_3_RST_EN (Bit 22) */\r
+#define PCR_EC_RST_EN2_TIMER16_3_RST_EN_Msk (0x400000UL) /*!< PCR EC_RST_EN2: TIMER16_3_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_TIMER32_0_RST_EN_Pos (23UL) /*!< PCR EC_RST_EN2: TIMER32_0_RST_EN (Bit 23) */\r
+#define PCR_EC_RST_EN2_TIMER32_0_RST_EN_Msk (0x800000UL) /*!< PCR EC_RST_EN2: TIMER32_0_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_TIMER32_1_RST_EN_Pos (24UL) /*!< PCR EC_RST_EN2: TIMER32_1_RST_EN (Bit 24) */\r
+#define PCR_EC_RST_EN2_TIMER32_1_RST_EN_Msk (0x1000000UL) /*!< PCR EC_RST_EN2: TIMER32_1_RST_EN (Bitfield-Mask: 0x01) */\r
+#define PCR_EC_RST_EN2_LED3_RST_EN_Pos (25UL) /*!< PCR EC_RST_EN2: LED3_RST_EN (Bit 25) */\r
+#define PCR_EC_RST_EN2_LED3_RST_EN_Msk (0x2000000UL) /*!< PCR EC_RST_EN2: LED3_RST_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ PCR_PWR_RST_CTRL ------------------------------ */\r
+#define PCR_PWR_RST_CTRL_IRESET_OUT_Pos (0UL) /*!< PCR PWR_RST_CTRL: IRESET_OUT (Bit 0) */\r
+#define PCR_PWR_RST_CTRL_IRESET_OUT_Msk (0x1UL) /*!< PCR PWR_RST_CTRL: IRESET_OUT (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'VBAT' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- VBAT_PFR_STS -------------------------------- */\r
+#define VBAT_PFR_STS_DET32K_IN_Pos (0UL) /*!< VBAT PFR_STS: DET32K_IN (Bit 0) */\r
+#define VBAT_PFR_STS_DET32K_IN_Msk (0x1UL) /*!< VBAT PFR_STS: DET32K_IN (Bitfield-Mask: 0x01) */\r
+#define VBAT_PFR_STS_WDT_Pos (5UL) /*!< VBAT PFR_STS: WDT (Bit 5) */\r
+#define VBAT_PFR_STS_WDT_Msk (0x20UL) /*!< VBAT PFR_STS: WDT (Bitfield-Mask: 0x01) */\r
+#define VBAT_PFR_STS_VBAT_RST_Pos (7UL) /*!< VBAT PFR_STS: VBAT_RST (Bit 7) */\r
+#define VBAT_PFR_STS_VBAT_RST_Msk (0x80UL) /*!< VBAT PFR_STS: VBAT_RST (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- VBAT_CLOCK_EN ------------------------------- */\r
+#define VBAT_CLOCK_EN_XOSEL_Pos (0UL) /*!< VBAT CLOCK_EN: XOSEL (Bit 0) */\r
+#define VBAT_CLOCK_EN_XOSEL_Msk (0x1UL) /*!< VBAT CLOCK_EN: XOSEL (Bitfield-Mask: 0x01) */\r
+#define VBAT_CLOCK_EN__32K_EN_Pos (1UL) /*!< VBAT CLOCK_EN: _32K_EN (Bit 1) */\r
+#define VBAT_CLOCK_EN__32K_EN_Msk (0x2UL) /*!< VBAT CLOCK_EN: _32K_EN (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'LPC' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------- LPC_BUS_MONITOR ------------------------------ */\r
+#define LPC_BUS_MONITOR_LRESET_STATUS_Pos (1UL) /*!< LPC BUS_MONITOR: LRESET_STATUS (Bit 1) */\r
+#define LPC_BUS_MONITOR_LRESET_STATUS_Msk (0x2UL) /*!< LPC BUS_MONITOR: LRESET_STATUS (Bitfield-Mask: 0x01) */\r
+\r
+/* ----------------------------- LPC_HOST_BUS_ERROR ----------------------------- */\r
+#define LPC_HOST_BUS_ERROR_LPC_ERR_Pos (0UL) /*!< LPC HOST_BUS_ERROR: LPC_ERR (Bit 0) */\r
+#define LPC_HOST_BUS_ERROR_LPC_ERR_Msk (0x1UL) /*!< LPC HOST_BUS_ERROR: LPC_ERR (Bitfield-Mask: 0x01) */\r
+#define LPC_HOST_BUS_ERROR_EN_ERR_Pos (1UL) /*!< LPC HOST_BUS_ERROR: EN_ERR (Bit 1) */\r
+#define LPC_HOST_BUS_ERROR_EN_ERR_Msk (0x2UL) /*!< LPC HOST_BUS_ERROR: EN_ERR (Bitfield-Mask: 0x01) */\r
+#define LPC_HOST_BUS_ERROR_BAR_ERR_Pos (2UL) /*!< LPC HOST_BUS_ERROR: BAR_ERR (Bit 2) */\r
+#define LPC_HOST_BUS_ERROR_BAR_ERR_Msk (0x4UL) /*!< LPC HOST_BUS_ERROR: BAR_ERR (Bitfield-Mask: 0x01) */\r
+#define LPC_HOST_BUS_ERROR_RUNTIME_ERR_Pos (3UL) /*!< LPC HOST_BUS_ERROR: RUNTIME_ERR (Bit 3) */\r
+#define LPC_HOST_BUS_ERROR_RUNTIME_ERR_Msk (0x8UL) /*!< LPC HOST_BUS_ERROR: RUNTIME_ERR (Bitfield-Mask: 0x01) */\r
+#define LPC_HOST_BUS_ERROR_CONFIG_ERR_Pos (4UL) /*!< LPC HOST_BUS_ERROR: CONFIG_ERR (Bit 4) */\r
+#define LPC_HOST_BUS_ERROR_CONFIG_ERR_Msk (0x10UL) /*!< LPC HOST_BUS_ERROR: CONFIG_ERR (Bitfield-Mask: 0x01) */\r
+#define LPC_HOST_BUS_ERROR_DMA_ERR_Pos (5UL) /*!< LPC HOST_BUS_ERROR: DMA_ERR (Bit 5) */\r
+#define LPC_HOST_BUS_ERROR_DMA_ERR_Msk (0x20UL) /*!< LPC HOST_BUS_ERROR: DMA_ERR (Bitfield-Mask: 0x01) */\r
+#define LPC_HOST_BUS_ERROR_ERR_ADDR_Pos (8UL) /*!< LPC HOST_BUS_ERROR: ERR_ADDR (Bit 8) */\r
+#define LPC_HOST_BUS_ERROR_ERR_ADDR_Msk (0xffffff00UL) /*!< LPC HOST_BUS_ERROR: ERR_ADDR (Bitfield-Mask: 0xffffff) */\r
+\r
+/* -------------------------------- LPC_EC_SERIRQ ------------------------------- */\r
+#define LPC_EC_SERIRQ_EC_IRQ_Pos (0UL) /*!< LPC EC_SERIRQ: EC_IRQ (Bit 0) */\r
+#define LPC_EC_SERIRQ_EC_IRQ_Msk (0x1UL) /*!< LPC EC_SERIRQ: EC_IRQ (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- LPC_CLK_CTRL -------------------------------- */\r
+#define LPC_CLK_CTRL_CR_Pos (0UL) /*!< LPC CLK_CTRL: CR (Bit 0) */\r
+#define LPC_CLK_CTRL_CR_Msk (0x3UL) /*!< LPC CLK_CTRL: CR (Bitfield-Mask: 0x03) */\r
+#define LPC_CLK_CTRL_HANDSHAKE_Pos (2UL) /*!< LPC CLK_CTRL: HANDSHAKE (Bit 2) */\r
+#define LPC_CLK_CTRL_HANDSHAKE_Msk (0x4UL) /*!< LPC CLK_CTRL: HANDSHAKE (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'LPC_CONFIG' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------- LPC_CONFIG_SIRQ ------------------------------ */\r
+#define LPC_CONFIG_SIRQ_FRAME_Pos (0UL) /*!< LPC_CONFIG SIRQ: FRAME (Bit 0) */\r
+#define LPC_CONFIG_SIRQ_FRAME_Msk (0x3fUL) /*!< LPC_CONFIG SIRQ: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_SIRQ_DEVICE_Pos (6UL) /*!< LPC_CONFIG SIRQ: DEVICE (Bit 6) */\r
+#define LPC_CONFIG_SIRQ_DEVICE_Msk (0x40UL) /*!< LPC_CONFIG SIRQ: DEVICE (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_SIRQ_SELECT_Pos (7UL) /*!< LPC_CONFIG SIRQ: SELECT (Bit 7) */\r
+#define LPC_CONFIG_SIRQ_SELECT_Msk (0x80UL) /*!< LPC_CONFIG SIRQ: SELECT (Bitfield-Mask: 0x01) */\r
+\r
+/* ----------------------------- LPC_CONFIG_LPC_BAR ----------------------------- */\r
+#define LPC_CONFIG_LPC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG LPC_BAR: MASK (Bit 0) */\r
+#define LPC_CONFIG_LPC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG LPC_BAR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_LPC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG LPC_BAR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_LPC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG LPC_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_LPC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG LPC_BAR: DEVICE (Bit 14) */\r
+#define LPC_CONFIG_LPC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG LPC_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_LPC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG LPC_BAR: VALID (Bit 15) */\r
+#define LPC_CONFIG_LPC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG LPC_BAR: VALID (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_LPC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG LPC_BAR: LPC_HOST_ADDR (Bit 16) */\r
+#define LPC_CONFIG_LPC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG LPC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
+\r
+/* ------------------------------ LPC_CONFIG_EM_BAR ----------------------------- */\r
+#define LPC_CONFIG_EM_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EM_BAR: MASK (Bit 0) */\r
+#define LPC_CONFIG_EM_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EM_BAR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_EM_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EM_BAR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_EM_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EM_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_EM_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EM_BAR: DEVICE (Bit 14) */\r
+#define LPC_CONFIG_EM_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EM_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_EM_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EM_BAR: VALID (Bit 15) */\r
+#define LPC_CONFIG_EM_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EM_BAR: VALID (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_EM_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EM_BAR: LPC_HOST_ADDR (Bit 16) */\r
+#define LPC_CONFIG_EM_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EM_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
+\r
+/* ----------------------------- LPC_CONFIG_UART_BAR ---------------------------- */\r
+#define LPC_CONFIG_UART_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG UART_BAR: MASK (Bit 0) */\r
+#define LPC_CONFIG_UART_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG UART_BAR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_UART_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG UART_BAR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_UART_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG UART_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_UART_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG UART_BAR: DEVICE (Bit 14) */\r
+#define LPC_CONFIG_UART_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG UART_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_UART_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG UART_BAR: VALID (Bit 15) */\r
+#define LPC_CONFIG_UART_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG UART_BAR: VALID (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_UART_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG UART_BAR: LPC_HOST_ADDR (Bit 16) */\r
+#define LPC_CONFIG_UART_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG UART_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
+\r
+/* ----------------------------- LPC_CONFIG_KBC_BAR ----------------------------- */\r
+#define LPC_CONFIG_KBC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG KBC_BAR: MASK (Bit 0) */\r
+#define LPC_CONFIG_KBC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG KBC_BAR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_KBC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG KBC_BAR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_KBC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG KBC_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_KBC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG KBC_BAR: DEVICE (Bit 14) */\r
+#define LPC_CONFIG_KBC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG KBC_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_KBC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG KBC_BAR: VALID (Bit 15) */\r
+#define LPC_CONFIG_KBC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG KBC_BAR: VALID (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_KBC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG KBC_BAR: LPC_HOST_ADDR (Bit 16) */\r
+#define LPC_CONFIG_KBC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG KBC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
+\r
+/* ----------------------------- LPC_CONFIG_EC0_BAR ----------------------------- */\r
+#define LPC_CONFIG_EC0_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EC0_BAR: MASK (Bit 0) */\r
+#define LPC_CONFIG_EC0_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EC0_BAR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_EC0_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EC0_BAR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_EC0_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EC0_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_EC0_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EC0_BAR: DEVICE (Bit 14) */\r
+#define LPC_CONFIG_EC0_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EC0_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_EC0_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EC0_BAR: VALID (Bit 15) */\r
+#define LPC_CONFIG_EC0_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EC0_BAR: VALID (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_EC0_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EC0_BAR: LPC_HOST_ADDR (Bit 16) */\r
+#define LPC_CONFIG_EC0_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EC0_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
+\r
+/* ----------------------------- LPC_CONFIG_EC1_BAR ----------------------------- */\r
+#define LPC_CONFIG_EC1_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EC1_BAR: MASK (Bit 0) */\r
+#define LPC_CONFIG_EC1_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EC1_BAR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_EC1_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EC1_BAR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_EC1_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EC1_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_EC1_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EC1_BAR: DEVICE (Bit 14) */\r
+#define LPC_CONFIG_EC1_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EC1_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_EC1_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EC1_BAR: VALID (Bit 15) */\r
+#define LPC_CONFIG_EC1_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EC1_BAR: VALID (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_EC1_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EC1_BAR: LPC_HOST_ADDR (Bit 16) */\r
+#define LPC_CONFIG_EC1_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EC1_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
+\r
+/* ----------------------------- LPC_CONFIG_PM1_BAR ----------------------------- */\r
+#define LPC_CONFIG_PM1_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG PM1_BAR: MASK (Bit 0) */\r
+#define LPC_CONFIG_PM1_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG PM1_BAR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_PM1_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG PM1_BAR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_PM1_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG PM1_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_PM1_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG PM1_BAR: DEVICE (Bit 14) */\r
+#define LPC_CONFIG_PM1_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG PM1_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_PM1_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG PM1_BAR: VALID (Bit 15) */\r
+#define LPC_CONFIG_PM1_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG PM1_BAR: VALID (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_PM1_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG PM1_BAR: LPC_HOST_ADDR (Bit 16) */\r
+#define LPC_CONFIG_PM1_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG PM1_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
+\r
+/* ----------------------------- LPC_CONFIG_LGC_BAR ----------------------------- */\r
+#define LPC_CONFIG_LGC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG LGC_BAR: MASK (Bit 0) */\r
+#define LPC_CONFIG_LGC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG LGC_BAR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_LGC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG LGC_BAR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_LGC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG LGC_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_LGC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG LGC_BAR: DEVICE (Bit 14) */\r
+#define LPC_CONFIG_LGC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG LGC_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_LGC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG LGC_BAR: VALID (Bit 15) */\r
+#define LPC_CONFIG_LGC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG LGC_BAR: VALID (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_LGC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG LGC_BAR: LPC_HOST_ADDR (Bit 16) */\r
+#define LPC_CONFIG_LGC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG LGC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
+\r
+/* ----------------------------- LPC_CONFIG_MBX_BAR ----------------------------- */\r
+#define LPC_CONFIG_MBX_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG MBX_BAR: MASK (Bit 0) */\r
+#define LPC_CONFIG_MBX_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG MBX_BAR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_MBX_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG MBX_BAR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_MBX_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG MBX_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_MBX_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG MBX_BAR: DEVICE (Bit 14) */\r
+#define LPC_CONFIG_MBX_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG MBX_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_MBX_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG MBX_BAR: VALID (Bit 15) */\r
+#define LPC_CONFIG_MBX_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG MBX_BAR: VALID (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_MBX_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG MBX_BAR: LPC_HOST_ADDR (Bit 16) */\r
+#define LPC_CONFIG_MBX_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG MBX_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
+\r
+/* ----------------------------- LPC_CONFIG_RTC_BAR ----------------------------- */\r
+#define LPC_CONFIG_RTC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG RTC_BAR: MASK (Bit 0) */\r
+#define LPC_CONFIG_RTC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG RTC_BAR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_RTC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG RTC_BAR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_RTC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG RTC_BAR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_RTC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG RTC_BAR: DEVICE (Bit 14) */\r
+#define LPC_CONFIG_RTC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG RTC_BAR: DEVICE (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_RTC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG RTC_BAR: VALID (Bit 15) */\r
+#define LPC_CONFIG_RTC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG RTC_BAR: VALID (Bitfield-Mask: 0x01) */\r
+#define LPC_CONFIG_RTC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG RTC_BAR: LPC_HOST_ADDR (Bit 16) */\r
+#define LPC_CONFIG_RTC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG RTC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'MEM_BAR' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- MEM_BAR_CR --------------------------------- */\r
+#define MEM_BAR_CR_MASK_Pos (0UL) /*!< MEM_BAR CR: MASK (Bit 0) */\r
+#define MEM_BAR_CR_MASK_Msk (0xffUL) /*!< MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */\r
+#define MEM_BAR_CR_FRAME_Pos (8UL) /*!< MEM_BAR CR: FRAME (Bit 8) */\r
+#define MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define MEM_BAR_CR_VALID_Pos (15UL) /*!< MEM_BAR CR: VALID (Bit 15) */\r
+#define MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'MBX_MEM_BAR' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------- LPC_CONFIG_MBX_MEM_BAR_CR ------------------------- */\r
+#define LPC_CONFIG_MBX_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: MASK (Bit 0) */\r
+#define LPC_CONFIG_MBX_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_MBX_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_MBX_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_MBX_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: VALID (Bit 15) */\r
+#define LPC_CONFIG_MBX_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'EC0_MEM_BAR' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------- LPC_CONFIG_EC0_MEM_BAR_CR ------------------------- */\r
+#define LPC_CONFIG_EC0_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: MASK (Bit 0) */\r
+#define LPC_CONFIG_EC0_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_EC0_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_EC0_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_EC0_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: VALID (Bit 15) */\r
+#define LPC_CONFIG_EC0_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'EC1_MEM_BAR' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------- LPC_CONFIG_EC1_MEM_BAR_CR ------------------------- */\r
+#define LPC_CONFIG_EC1_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: MASK (Bit 0) */\r
+#define LPC_CONFIG_EC1_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_EC1_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_EC1_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_EC1_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: VALID (Bit 15) */\r
+#define LPC_CONFIG_EC1_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'EMI_MEM_BAR' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------- LPC_CONFIG_EMI_MEM_BAR_CR ------------------------- */\r
+#define LPC_CONFIG_EMI_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: MASK (Bit 0) */\r
+#define LPC_CONFIG_EMI_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */\r
+#define LPC_CONFIG_EMI_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: FRAME (Bit 8) */\r
+#define LPC_CONFIG_EMI_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */\r
+#define LPC_CONFIG_EMI_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: VALID (Bit 15) */\r
+#define LPC_CONFIG_EMI_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'EMI' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------- EMI_EC_ADDRESS ------------------------------- */\r
+#define EMI_EC_ADDRESS_ACCESS_TYPE_Pos (0UL) /*!< EMI EC_ADDRESS: ACCESS_TYPE (Bit 0) */\r
+#define EMI_EC_ADDRESS_ACCESS_TYPE_Msk (0x3UL) /*!< EMI EC_ADDRESS: ACCESS_TYPE (Bitfield-Mask: 0x03) */\r
+#define EMI_EC_ADDRESS_EC_ADDRESS_Pos (2UL) /*!< EMI EC_ADDRESS: EC_ADDRESS (Bit 2) */\r
+#define EMI_EC_ADDRESS_EC_ADDRESS_Msk (0x7ffcUL) /*!< EMI EC_ADDRESS: EC_ADDRESS (Bitfield-Mask: 0x1fff) */\r
+#define EMI_EC_ADDRESS_REGION_Pos (15UL) /*!< EMI EC_ADDRESS: REGION (Bit 15) */\r
+#define EMI_EC_ADDRESS_REGION_Msk (0x8000UL) /*!< EMI EC_ADDRESS: REGION (Bitfield-Mask: 0x01) */\r
+\r
+/* --------------------------------- EMI_EC_SWI --------------------------------- */\r
+#define EMI_EC_SWI_EC_WR_Pos (0UL) /*!< EMI EC_SWI: EC_WR (Bit 0) */\r
+#define EMI_EC_SWI_EC_WR_Msk (0x1UL) /*!< EMI EC_SWI: EC_WR (Bitfield-Mask: 0x01) */\r
+#define EMI_EC_SWI_NOTIFICATION_Pos (1UL) /*!< EMI EC_SWI: NOTIFICATION (Bit 1) */\r
+#define EMI_EC_SWI_NOTIFICATION_Msk (0xfffeUL) /*!< EMI EC_SWI: NOTIFICATION (Bitfield-Mask: 0x7fff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'ACPI_EC0' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------- ACPI_EC0_OS_STATUS ----------------------------- */\r
+#define ACPI_EC0_OS_STATUS_OBF_Pos (0UL) /*!< ACPI_EC0 OS_STATUS: OBF (Bit 0) */\r
+#define ACPI_EC0_OS_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC0 OS_STATUS: OBF (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_OS_STATUS_IBF_Pos (1UL) /*!< ACPI_EC0 OS_STATUS: IBF (Bit 1) */\r
+#define ACPI_EC0_OS_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC0 OS_STATUS: IBF (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_OS_STATUS_UD1B_Pos (2UL) /*!< ACPI_EC0 OS_STATUS: UD1B (Bit 2) */\r
+#define ACPI_EC0_OS_STATUS_UD1B_Msk (0x4UL) /*!< ACPI_EC0 OS_STATUS: UD1B (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_OS_STATUS_CMD_Pos (3UL) /*!< ACPI_EC0 OS_STATUS: CMD (Bit 3) */\r
+#define ACPI_EC0_OS_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC0 OS_STATUS: CMD (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_OS_STATUS_BURST_Pos (4UL) /*!< ACPI_EC0 OS_STATUS: BURST (Bit 4) */\r
+#define ACPI_EC0_OS_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC0 OS_STATUS: BURST (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_OS_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC0 OS_STATUS: SCI_EVT (Bit 5) */\r
+#define ACPI_EC0_OS_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC0 OS_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_OS_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC0 OS_STATUS: SMI_EVT (Bit 6) */\r
+#define ACPI_EC0_OS_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC0 OS_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_OS_STATUS_UD0B_Pos (7UL) /*!< ACPI_EC0 OS_STATUS: UD0B (Bit 7) */\r
+#define ACPI_EC0_OS_STATUS_UD0B_Msk (0x80UL) /*!< ACPI_EC0 OS_STATUS: UD0B (Bitfield-Mask: 0x01) */\r
+\r
+/* ----------------------------- ACPI_EC0_EC_STATUS ----------------------------- */\r
+#define ACPI_EC0_EC_STATUS_OBF_Pos (0UL) /*!< ACPI_EC0 EC_STATUS: OBF (Bit 0) */\r
+#define ACPI_EC0_EC_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC0 EC_STATUS: OBF (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_EC_STATUS_IBF_Pos (1UL) /*!< ACPI_EC0 EC_STATUS: IBF (Bit 1) */\r
+#define ACPI_EC0_EC_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC0 EC_STATUS: IBF (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_EC_STATUS_UD1A_Pos (2UL) /*!< ACPI_EC0 EC_STATUS: UD1A (Bit 2) */\r
+#define ACPI_EC0_EC_STATUS_UD1A_Msk (0x4UL) /*!< ACPI_EC0 EC_STATUS: UD1A (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_EC_STATUS_CMD_Pos (3UL) /*!< ACPI_EC0 EC_STATUS: CMD (Bit 3) */\r
+#define ACPI_EC0_EC_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC0 EC_STATUS: CMD (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_EC_STATUS_BURST_Pos (4UL) /*!< ACPI_EC0 EC_STATUS: BURST (Bit 4) */\r
+#define ACPI_EC0_EC_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC0 EC_STATUS: BURST (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_EC_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC0 EC_STATUS: SCI_EVT (Bit 5) */\r
+#define ACPI_EC0_EC_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC0 EC_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_EC_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC0 EC_STATUS: SMI_EVT (Bit 6) */\r
+#define ACPI_EC0_EC_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC0 EC_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC0_EC_STATUS_UD0A_Pos (7UL) /*!< ACPI_EC0 EC_STATUS: UD0A (Bit 7) */\r
+#define ACPI_EC0_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC0 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'ACPI_EC1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------- ACPI_EC1_OS_STATUS ----------------------------- */\r
+#define ACPI_EC1_OS_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bit 0) */\r
+#define ACPI_EC1_OS_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_OS_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bit 1) */\r
+#define ACPI_EC1_OS_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_OS_STATUS_UD1B_Pos (2UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bit 2) */\r
+#define ACPI_EC1_OS_STATUS_UD1B_Msk (0x4UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_OS_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bit 3) */\r
+#define ACPI_EC1_OS_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_OS_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bit 4) */\r
+#define ACPI_EC1_OS_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_OS_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bit 5) */\r
+#define ACPI_EC1_OS_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_OS_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bit 6) */\r
+#define ACPI_EC1_OS_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_OS_STATUS_UD0B_Pos (7UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bit 7) */\r
+#define ACPI_EC1_OS_STATUS_UD0B_Msk (0x80UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bitfield-Mask: 0x01) */\r
+\r
+/* ----------------------------- ACPI_EC1_EC_STATUS ----------------------------- */\r
+#define ACPI_EC1_EC_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bit 0) */\r
+#define ACPI_EC1_EC_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_EC_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bit 1) */\r
+#define ACPI_EC1_EC_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_EC_STATUS_UD1A_Pos (2UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bit 2) */\r
+#define ACPI_EC1_EC_STATUS_UD1A_Msk (0x4UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_EC_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bit 3) */\r
+#define ACPI_EC1_EC_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_EC_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bit 4) */\r
+#define ACPI_EC1_EC_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_EC_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bit 5) */\r
+#define ACPI_EC1_EC_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_EC_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bit 6) */\r
+#define ACPI_EC1_EC_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */\r
+#define ACPI_EC1_EC_STATUS_UD0A_Pos (7UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bit 7) */\r
+#define ACPI_EC1_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'KBC' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------- KBC_RD_PORT64_STATUS ---------------------------- */\r
+#define KBC_RD_PORT64_STATUS_OBF_Pos (0UL) /*!< KBC RD_PORT64_STATUS: OBF (Bit 0) */\r
+#define KBC_RD_PORT64_STATUS_OBF_Msk (0x1UL) /*!< KBC RD_PORT64_STATUS: OBF (Bitfield-Mask: 0x01) */\r
+#define KBC_RD_PORT64_STATUS_IBF_Pos (1UL) /*!< KBC RD_PORT64_STATUS: IBF (Bit 1) */\r
+#define KBC_RD_PORT64_STATUS_IBF_Msk (0x2UL) /*!< KBC RD_PORT64_STATUS: IBF (Bitfield-Mask: 0x01) */\r
+#define KBC_RD_PORT64_STATUS_UD0_Pos (2UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bit 2) */\r
+#define KBC_RD_PORT64_STATUS_UD0_Msk (0x4UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bitfield-Mask: 0x01) */\r
+#define KBC_RD_PORT64_STATUS_CMDnDATA_Pos (3UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bit 3) */\r
+#define KBC_RD_PORT64_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bitfield-Mask: 0x01) */\r
+#define KBC_RD_PORT64_STATUS_UD1_Pos (4UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bit 4) */\r
+#define KBC_RD_PORT64_STATUS_UD1_Msk (0x10UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bitfield-Mask: 0x01) */\r
+#define KBC_RD_PORT64_STATUS_AUXOBF_Pos (5UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bit 5) */\r
+#define KBC_RD_PORT64_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bitfield-Mask: 0x01) */\r
+#define KBC_RD_PORT64_STATUS_UD2_Pos (6UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bit 6) */\r
+#define KBC_RD_PORT64_STATUS_UD2_Msk (0xc0UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bitfield-Mask: 0x03) */\r
+\r
+/* --------------------------------- KBC_STATUS --------------------------------- */\r
+#define KBC_STATUS_OBF_Pos (0UL) /*!< KBC STATUS: OBF (Bit 0) */\r
+#define KBC_STATUS_OBF_Msk (0x1UL) /*!< KBC STATUS: OBF (Bitfield-Mask: 0x01) */\r
+#define KBC_STATUS_IBF_Pos (1UL) /*!< KBC STATUS: IBF (Bit 1) */\r
+#define KBC_STATUS_IBF_Msk (0x2UL) /*!< KBC STATUS: IBF (Bitfield-Mask: 0x01) */\r
+#define KBC_STATUS_UD0_Pos (2UL) /*!< KBC STATUS: UD0 (Bit 2) */\r
+#define KBC_STATUS_UD0_Msk (0x4UL) /*!< KBC STATUS: UD0 (Bitfield-Mask: 0x01) */\r
+#define KBC_STATUS_CMDnDATA_Pos (3UL) /*!< KBC STATUS: CMDnDATA (Bit 3) */\r
+#define KBC_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC STATUS: CMDnDATA (Bitfield-Mask: 0x01) */\r
+#define KBC_STATUS_UD1_Pos (4UL) /*!< KBC STATUS: UD1 (Bit 4) */\r
+#define KBC_STATUS_UD1_Msk (0x10UL) /*!< KBC STATUS: UD1 (Bitfield-Mask: 0x01) */\r
+#define KBC_STATUS_AUXOBF_Pos (5UL) /*!< KBC STATUS: AUXOBF (Bit 5) */\r
+#define KBC_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC STATUS: AUXOBF (Bitfield-Mask: 0x01) */\r
+#define KBC_STATUS_UD2_Pos (6UL) /*!< KBC STATUS: UD2 (Bit 6) */\r
+#define KBC_STATUS_UD2_Msk (0xc0UL) /*!< KBC STATUS: UD2 (Bitfield-Mask: 0x03) */\r
+\r
+/* --------------------------------- KBC_CONTROL -------------------------------- */\r
+#define KBC_CONTROL_UD3_Pos (0UL) /*!< KBC CONTROL: UD3 (Bit 0) */\r
+#define KBC_CONTROL_UD3_Msk (0x1UL) /*!< KBC CONTROL: UD3 (Bitfield-Mask: 0x01) */\r
+#define KBC_CONTROL_SAEN_Pos (1UL) /*!< KBC CONTROL: SAEN (Bit 1) */\r
+#define KBC_CONTROL_SAEN_Msk (0x2UL) /*!< KBC CONTROL: SAEN (Bitfield-Mask: 0x01) */\r
+#define KBC_CONTROL_PCOBFEN_Pos (2UL) /*!< KBC CONTROL: PCOBFEN (Bit 2) */\r
+#define KBC_CONTROL_PCOBFEN_Msk (0x4UL) /*!< KBC CONTROL: PCOBFEN (Bitfield-Mask: 0x01) */\r
+#define KBC_CONTROL_UD4_Pos (3UL) /*!< KBC CONTROL: UD4 (Bit 3) */\r
+#define KBC_CONTROL_UD4_Msk (0x18UL) /*!< KBC CONTROL: UD4 (Bitfield-Mask: 0x03) */\r
+#define KBC_CONTROL_OBFEN_Pos (5UL) /*!< KBC CONTROL: OBFEN (Bit 5) */\r
+#define KBC_CONTROL_OBFEN_Msk (0x20UL) /*!< KBC CONTROL: OBFEN (Bitfield-Mask: 0x01) */\r
+#define KBC_CONTROL_UD5_Pos (6UL) /*!< KBC CONTROL: UD5 (Bit 6) */\r
+#define KBC_CONTROL_UD5_Msk (0x40UL) /*!< KBC CONTROL: UD5 (Bitfield-Mask: 0x01) */\r
+#define KBC_CONTROL_AUXH_Pos (7UL) /*!< KBC CONTROL: AUXH (Bit 7) */\r
+#define KBC_CONTROL_AUXH_Msk (0x80UL) /*!< KBC CONTROL: AUXH (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PORT92' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PORT92_PORT92 ------------------------------- */\r
+#define PORT92_PORT92_ALT_CPU_RESET_Pos (0UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bit 0) */\r
+#define PORT92_PORT92_ALT_CPU_RESET_Msk (0x1UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bitfield-Mask: 0x01) */\r
+#define PORT92_PORT92_ALT_GATE_A20_Pos (1UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bit 1) */\r
+#define PORT92_PORT92_ALT_GATE_A20_Msk (0x2UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'MBX' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------- MBX_SMI_SOURCE ------------------------------- */\r
+#define MBX_SMI_SOURCE_EC_WR_Pos (0UL) /*!< MBX SMI_SOURCE: EC_WR (Bit 0) */\r
+#define MBX_SMI_SOURCE_EC_WR_Msk (0x1UL) /*!< MBX SMI_SOURCE: EC_WR (Bitfield-Mask: 0x01) */\r
+#define MBX_SMI_SOURCE_EC_SMI_Pos (1UL) /*!< MBX SMI_SOURCE: EC_SMI (Bit 1) */\r
+#define MBX_SMI_SOURCE_EC_SMI_Msk (0xfeUL) /*!< MBX SMI_SOURCE: EC_SMI (Bitfield-Mask: 0x7f) */\r
+\r
+/* -------------------------------- MBX_SMI_MASK -------------------------------- */\r
+#define MBX_SMI_MASK_EC_WR_EN_Pos (0UL) /*!< MBX SMI_MASK: EC_WR_EN (Bit 0) */\r
+#define MBX_SMI_MASK_EC_WR_EN_Msk (0x1UL) /*!< MBX SMI_MASK: EC_WR_EN (Bitfield-Mask: 0x01) */\r
+#define MBX_SMI_MASK_EC_SMI_EN_Pos (1UL) /*!< MBX SMI_MASK: EC_SMI_EN (Bit 1) */\r
+#define MBX_SMI_MASK_EC_SMI_EN_Msk (0xfeUL) /*!< MBX SMI_MASK: EC_SMI_EN (Bitfield-Mask: 0x7f) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PM1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------- PM1_STS2 ---------------------------------- */\r
+#define PM1_STS2_PWRBTN_STS_Pos (0UL) /*!< PM1 STS2: PWRBTN_STS (Bit 0) */\r
+#define PM1_STS2_PWRBTN_STS_Msk (0x1UL) /*!< PM1 STS2: PWRBTN_STS (Bitfield-Mask: 0x01) */\r
+#define PM1_STS2_SLPBTN_STS_Pos (1UL) /*!< PM1 STS2: SLPBTN_STS (Bit 1) */\r
+#define PM1_STS2_SLPBTN_STS_Msk (0x2UL) /*!< PM1 STS2: SLPBTN_STS (Bitfield-Mask: 0x01) */\r
+#define PM1_STS2_RTC_STS_Pos (2UL) /*!< PM1 STS2: RTC_STS (Bit 2) */\r
+#define PM1_STS2_RTC_STS_Msk (0x4UL) /*!< PM1 STS2: RTC_STS (Bitfield-Mask: 0x01) */\r
+#define PM1_STS2_PWRBTNOR_STS_Pos (3UL) /*!< PM1 STS2: PWRBTNOR_STS (Bit 3) */\r
+#define PM1_STS2_PWRBTNOR_STS_Msk (0x8UL) /*!< PM1 STS2: PWRBTNOR_STS (Bitfield-Mask: 0x01) */\r
+#define PM1_STS2_WAK_STS_Pos (7UL) /*!< PM1 STS2: WAK_STS (Bit 7) */\r
+#define PM1_STS2_WAK_STS_Msk (0x80UL) /*!< PM1 STS2: WAK_STS (Bitfield-Mask: 0x01) */\r
+\r
+/* ----------------------------------- PM1_EN2 ---------------------------------- */\r
+#define PM1_EN2_PWRBTN_EN_Pos (0UL) /*!< PM1 EN2: PWRBTN_EN (Bit 0) */\r
+#define PM1_EN2_PWRBTN_EN_Msk (0x1UL) /*!< PM1 EN2: PWRBTN_EN (Bitfield-Mask: 0x01) */\r
+#define PM1_EN2_SLPBTN_EN_Pos (1UL) /*!< PM1 EN2: SLPBTN_EN (Bit 1) */\r
+#define PM1_EN2_SLPBTN_EN_Msk (0x2UL) /*!< PM1 EN2: SLPBTN_EN (Bitfield-Mask: 0x01) */\r
+#define PM1_EN2_RTC_EN_Pos (2UL) /*!< PM1 EN2: RTC_EN (Bit 2) */\r
+#define PM1_EN2_RTC_EN_Msk (0x4UL) /*!< PM1 EN2: RTC_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------------- PM1_CTRL2 --------------------------------- */\r
+#define PM1_CTRL2_PWRBTNOR_EN_Pos (1UL) /*!< PM1 CTRL2: PWRBTNOR_EN (Bit 1) */\r
+#define PM1_CTRL2_PWRBTNOR_EN_Msk (0x2UL) /*!< PM1 CTRL2: PWRBTNOR_EN (Bitfield-Mask: 0x01) */\r
+#define PM1_CTRL2_SLP_TYP_Pos (2UL) /*!< PM1 CTRL2: SLP_TYP (Bit 2) */\r
+#define PM1_CTRL2_SLP_TYP_Msk (0x1cUL) /*!< PM1 CTRL2: SLP_TYP (Bitfield-Mask: 0x07) */\r
+#define PM1_CTRL2_SLP_EN_Pos (5UL) /*!< PM1 CTRL2: SLP_EN (Bit 5) */\r
+#define PM1_CTRL2_SLP_EN_Msk (0x20UL) /*!< PM1 CTRL2: SLP_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------------- PM1_STS_2 --------------------------------- */\r
+#define PM1_STS_2_PWRBTN_STS_Pos (0UL) /*!< PM1 STS_2: PWRBTN_STS (Bit 0) */\r
+#define PM1_STS_2_PWRBTN_STS_Msk (0x1UL) /*!< PM1 STS_2: PWRBTN_STS (Bitfield-Mask: 0x01) */\r
+#define PM1_STS_2_SLPBTN_STS_Pos (1UL) /*!< PM1 STS_2: SLPBTN_STS (Bit 1) */\r
+#define PM1_STS_2_SLPBTN_STS_Msk (0x2UL) /*!< PM1 STS_2: SLPBTN_STS (Bitfield-Mask: 0x01) */\r
+#define PM1_STS_2_RTC_STS_Pos (2UL) /*!< PM1 STS_2: RTC_STS (Bit 2) */\r
+#define PM1_STS_2_RTC_STS_Msk (0x4UL) /*!< PM1 STS_2: RTC_STS (Bitfield-Mask: 0x01) */\r
+#define PM1_STS_2_PWRBTNOR_STS_Pos (3UL) /*!< PM1 STS_2: PWRBTNOR_STS (Bit 3) */\r
+#define PM1_STS_2_PWRBTNOR_STS_Msk (0x8UL) /*!< PM1 STS_2: PWRBTNOR_STS (Bitfield-Mask: 0x01) */\r
+#define PM1_STS_2_WAK_STS_Pos (7UL) /*!< PM1 STS_2: WAK_STS (Bit 7) */\r
+#define PM1_STS_2_WAK_STS_Msk (0x80UL) /*!< PM1 STS_2: WAK_STS (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------------- PM1_EN_2 ---------------------------------- */\r
+#define PM1_EN_2_PWRBTN_EN_Pos (0UL) /*!< PM1 EN_2: PWRBTN_EN (Bit 0) */\r
+#define PM1_EN_2_PWRBTN_EN_Msk (0x1UL) /*!< PM1 EN_2: PWRBTN_EN (Bitfield-Mask: 0x01) */\r
+#define PM1_EN_2_SLPBTN_EN_Pos (1UL) /*!< PM1 EN_2: SLPBTN_EN (Bit 1) */\r
+#define PM1_EN_2_SLPBTN_EN_Msk (0x2UL) /*!< PM1 EN_2: SLPBTN_EN (Bitfield-Mask: 0x01) */\r
+#define PM1_EN_2_RTC_EN_Pos (2UL) /*!< PM1 EN_2: RTC_EN (Bit 2) */\r
+#define PM1_EN_2_RTC_EN_Msk (0x4UL) /*!< PM1 EN_2: RTC_EN (Bitfield-Mask: 0x01) */\r
+\r
+/* --------------------------------- PM1_CTRL_2 --------------------------------- */\r
+#define PM1_CTRL_2_PWRBTNOR_EN_Pos (1UL) /*!< PM1 CTRL_2: PWRBTNOR_EN (Bit 1) */\r
+#define PM1_CTRL_2_PWRBTNOR_EN_Msk (0x2UL) /*!< PM1 CTRL_2: PWRBTNOR_EN (Bitfield-Mask: 0x01) */\r
+#define PM1_CTRL_2_SLP_TYP_Pos (2UL) /*!< PM1 CTRL_2: SLP_TYP (Bit 2) */\r
+#define PM1_CTRL_2_SLP_TYP_Msk (0x1cUL) /*!< PM1 CTRL_2: SLP_TYP (Bitfield-Mask: 0x07) */\r
+#define PM1_CTRL_2_SLP_EN_Pos (5UL) /*!< PM1 CTRL_2: SLP_EN (Bit 5) */\r
+#define PM1_CTRL_2_SLP_EN_Msk (0x20UL) /*!< PM1 CTRL_2: SLP_EN (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'UART' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- UART_INT_EN -------------------------------- */\r
+#define UART_INT_EN_ERDAI_Pos (0UL) /*!< UART INT_EN: ERDAI (Bit 0) */\r
+#define UART_INT_EN_ERDAI_Msk (0x1UL) /*!< UART INT_EN: ERDAI (Bitfield-Mask: 0x01) */\r
+#define UART_INT_EN_ETHREI_Pos (1UL) /*!< UART INT_EN: ETHREI (Bit 1) */\r
+#define UART_INT_EN_ETHREI_Msk (0x2UL) /*!< UART INT_EN: ETHREI (Bitfield-Mask: 0x01) */\r
+#define UART_INT_EN_ELSI_Pos (2UL) /*!< UART INT_EN: ELSI (Bit 2) */\r
+#define UART_INT_EN_ELSI_Msk (0x4UL) /*!< UART INT_EN: ELSI (Bitfield-Mask: 0x01) */\r
+#define UART_INT_EN_EMSI_Pos (3UL) /*!< UART INT_EN: EMSI (Bit 3) */\r
+#define UART_INT_EN_EMSI_Msk (0x8UL) /*!< UART INT_EN: EMSI (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- UART_FIFO_CR -------------------------------- */\r
+#define UART_FIFO_CR_EXRF_Pos (0UL) /*!< UART FIFO_CR: EXRF (Bit 0) */\r
+#define UART_FIFO_CR_EXRF_Msk (0x1UL) /*!< UART FIFO_CR: EXRF (Bitfield-Mask: 0x01) */\r
+#define UART_FIFO_CR_CLEAR_RECV_FIFO_Pos (1UL) /*!< UART FIFO_CR: CLEAR_RECV_FIFO (Bit 1) */\r
+#define UART_FIFO_CR_CLEAR_RECV_FIFO_Msk (0x2UL) /*!< UART FIFO_CR: CLEAR_RECV_FIFO (Bitfield-Mask: 0x01) */\r
+#define UART_FIFO_CR_CLEAR_XMIT_FIFO_Pos (2UL) /*!< UART FIFO_CR: CLEAR_XMIT_FIFO (Bit 2) */\r
+#define UART_FIFO_CR_CLEAR_XMIT_FIFO_Msk (0x4UL) /*!< UART FIFO_CR: CLEAR_XMIT_FIFO (Bitfield-Mask: 0x01) */\r
+#define UART_FIFO_CR_DMA_MODE_SELECT_Pos (3UL) /*!< UART FIFO_CR: DMA_MODE_SELECT (Bit 3) */\r
+#define UART_FIFO_CR_DMA_MODE_SELECT_Msk (0x8UL) /*!< UART FIFO_CR: DMA_MODE_SELECT (Bitfield-Mask: 0x01) */\r
+#define UART_FIFO_CR_RECV_FIFO_TRIGGER_LEVEL_Pos (6UL) /*!< UART FIFO_CR: RECV_FIFO_TRIGGER_LEVEL (Bit 6) */\r
+#define UART_FIFO_CR_RECV_FIFO_TRIGGER_LEVEL_Msk (0xc0UL) /*!< UART FIFO_CR: RECV_FIFO_TRIGGER_LEVEL (Bitfield-Mask: 0x03) */\r
+\r
+/* --------------------------------- UART_INT_ID -------------------------------- */\r
+#define UART_INT_ID_IPEND_Pos (0UL) /*!< UART INT_ID: IPEND (Bit 0) */\r
+#define UART_INT_ID_IPEND_Msk (0x1UL) /*!< UART INT_ID: IPEND (Bitfield-Mask: 0x01) */\r
+#define UART_INT_ID_INTID_Pos (1UL) /*!< UART INT_ID: INTID (Bit 1) */\r
+#define UART_INT_ID_INTID_Msk (0xeUL) /*!< UART INT_ID: INTID (Bitfield-Mask: 0x07) */\r
+#define UART_INT_ID_FIFO_EN_Pos (6UL) /*!< UART INT_ID: FIFO_EN (Bit 6) */\r
+#define UART_INT_ID_FIFO_EN_Msk (0xc0UL) /*!< UART INT_ID: FIFO_EN (Bitfield-Mask: 0x03) */\r
+\r
+/* -------------------------------- UART_LINE_CR -------------------------------- */\r
+#define UART_LINE_CR_WORD_LENGTH_Pos (0UL) /*!< UART LINE_CR: WORD_LENGTH (Bit 0) */\r
+#define UART_LINE_CR_WORD_LENGTH_Msk (0x3UL) /*!< UART LINE_CR: WORD_LENGTH (Bitfield-Mask: 0x03) */\r
+#define UART_LINE_CR_STOP_BITS_Pos (2UL) /*!< UART LINE_CR: STOP_BITS (Bit 2) */\r
+#define UART_LINE_CR_STOP_BITS_Msk (0x4UL) /*!< UART LINE_CR: STOP_BITS (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_CR_ENABLE_PARITY_Pos (3UL) /*!< UART LINE_CR: ENABLE_PARITY (Bit 3) */\r
+#define UART_LINE_CR_ENABLE_PARITY_Msk (0x8UL) /*!< UART LINE_CR: ENABLE_PARITY (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_CR_PARITY_SELECT_Pos (4UL) /*!< UART LINE_CR: PARITY_SELECT (Bit 4) */\r
+#define UART_LINE_CR_PARITY_SELECT_Msk (0x10UL) /*!< UART LINE_CR: PARITY_SELECT (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_CR_STICK_PARITY_Pos (5UL) /*!< UART LINE_CR: STICK_PARITY (Bit 5) */\r
+#define UART_LINE_CR_STICK_PARITY_Msk (0x20UL) /*!< UART LINE_CR: STICK_PARITY (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_CR_BREAK_CONTROL_Pos (6UL) /*!< UART LINE_CR: BREAK_CONTROL (Bit 6) */\r
+#define UART_LINE_CR_BREAK_CONTROL_Msk (0x40UL) /*!< UART LINE_CR: BREAK_CONTROL (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_CR_DLAB_Pos (7UL) /*!< UART LINE_CR: DLAB (Bit 7) */\r
+#define UART_LINE_CR_DLAB_Msk (0x80UL) /*!< UART LINE_CR: DLAB (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- UART_MODEM_CR ------------------------------- */\r
+#define UART_MODEM_CR_DTR_Pos (0UL) /*!< UART MODEM_CR: DTR (Bit 0) */\r
+#define UART_MODEM_CR_DTR_Msk (0x1UL) /*!< UART MODEM_CR: DTR (Bitfield-Mask: 0x01) */\r
+#define UART_MODEM_CR_RTS_Pos (1UL) /*!< UART MODEM_CR: RTS (Bit 1) */\r
+#define UART_MODEM_CR_RTS_Msk (0x2UL) /*!< UART MODEM_CR: RTS (Bitfield-Mask: 0x01) */\r
+#define UART_MODEM_CR_OUT1_Pos (2UL) /*!< UART MODEM_CR: OUT1 (Bit 2) */\r
+#define UART_MODEM_CR_OUT1_Msk (0x4UL) /*!< UART MODEM_CR: OUT1 (Bitfield-Mask: 0x01) */\r
+#define UART_MODEM_CR_OUT2_Pos (3UL) /*!< UART MODEM_CR: OUT2 (Bit 3) */\r
+#define UART_MODEM_CR_OUT2_Msk (0x8UL) /*!< UART MODEM_CR: OUT2 (Bitfield-Mask: 0x01) */\r
+#define UART_MODEM_CR_LOOPBACK_Pos (4UL) /*!< UART MODEM_CR: LOOPBACK (Bit 4) */\r
+#define UART_MODEM_CR_LOOPBACK_Msk (0x10UL) /*!< UART MODEM_CR: LOOPBACK (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- UART_LINE_STS ------------------------------- */\r
+#define UART_LINE_STS_DATA_READY_Pos (0UL) /*!< UART LINE_STS: DATA_READY (Bit 0) */\r
+#define UART_LINE_STS_DATA_READY_Msk (0x1UL) /*!< UART LINE_STS: DATA_READY (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_STS_OVERRUN_Pos (1UL) /*!< UART LINE_STS: OVERRUN (Bit 1) */\r
+#define UART_LINE_STS_OVERRUN_Msk (0x2UL) /*!< UART LINE_STS: OVERRUN (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_STS_PE_Pos (2UL) /*!< UART LINE_STS: PE (Bit 2) */\r
+#define UART_LINE_STS_PE_Msk (0x4UL) /*!< UART LINE_STS: PE (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_STS_FRAME_ERROR_Pos (3UL) /*!< UART LINE_STS: FRAME_ERROR (Bit 3) */\r
+#define UART_LINE_STS_FRAME_ERROR_Msk (0x8UL) /*!< UART LINE_STS: FRAME_ERROR (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_STS_BREAK_INTERRUPT_Pos (4UL) /*!< UART LINE_STS: BREAK_INTERRUPT (Bit 4) */\r
+#define UART_LINE_STS_BREAK_INTERRUPT_Msk (0x10UL) /*!< UART LINE_STS: BREAK_INTERRUPT (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_STS_TRANSMIT_EMPTY_Pos (5UL) /*!< UART LINE_STS: TRANSMIT_EMPTY (Bit 5) */\r
+#define UART_LINE_STS_TRANSMIT_EMPTY_Msk (0x20UL) /*!< UART LINE_STS: TRANSMIT_EMPTY (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_STS_TRANSMIT_ERROR_Pos (6UL) /*!< UART LINE_STS: TRANSMIT_ERROR (Bit 6) */\r
+#define UART_LINE_STS_TRANSMIT_ERROR_Msk (0x40UL) /*!< UART LINE_STS: TRANSMIT_ERROR (Bitfield-Mask: 0x01) */\r
+#define UART_LINE_STS_FIFO_ERROR_Pos (7UL) /*!< UART LINE_STS: FIFO_ERROR (Bit 7) */\r
+#define UART_LINE_STS_FIFO_ERROR_Msk (0x80UL) /*!< UART LINE_STS: FIFO_ERROR (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- UART_MODEM_STS ------------------------------- */\r
+#define UART_MODEM_STS_CTS_Pos (0UL) /*!< UART MODEM_STS: CTS (Bit 0) */\r
+#define UART_MODEM_STS_CTS_Msk (0x1UL) /*!< UART MODEM_STS: CTS (Bitfield-Mask: 0x01) */\r
+#define UART_MODEM_STS_DSR_Pos (1UL) /*!< UART MODEM_STS: DSR (Bit 1) */\r
+#define UART_MODEM_STS_DSR_Msk (0x2UL) /*!< UART MODEM_STS: DSR (Bitfield-Mask: 0x01) */\r
+#define UART_MODEM_STS_RI_Pos (2UL) /*!< UART MODEM_STS: RI (Bit 2) */\r
+#define UART_MODEM_STS_RI_Msk (0x4UL) /*!< UART MODEM_STS: RI (Bitfield-Mask: 0x01) */\r
+#define UART_MODEM_STS_DCD_Pos (3UL) /*!< UART MODEM_STS: DCD (Bit 3) */\r
+#define UART_MODEM_STS_DCD_Msk (0x8UL) /*!< UART MODEM_STS: DCD (Bitfield-Mask: 0x01) */\r
+#define UART_MODEM_STS_nCTS_Pos (4UL) /*!< UART MODEM_STS: nCTS (Bit 4) */\r
+#define UART_MODEM_STS_nCTS_Msk (0x10UL) /*!< UART MODEM_STS: nCTS (Bitfield-Mask: 0x01) */\r
+#define UART_MODEM_STS_nDSR_Pos (5UL) /*!< UART MODEM_STS: nDSR (Bit 5) */\r
+#define UART_MODEM_STS_nDSR_Msk (0x20UL) /*!< UART MODEM_STS: nDSR (Bitfield-Mask: 0x01) */\r
+#define UART_MODEM_STS_nRI_Pos (6UL) /*!< UART MODEM_STS: nRI (Bit 6) */\r
+#define UART_MODEM_STS_nRI_Msk (0x40UL) /*!< UART MODEM_STS: nRI (Bitfield-Mask: 0x01) */\r
+#define UART_MODEM_STS_nDCD_Pos (7UL) /*!< UART MODEM_STS: nDCD (Bit 7) */\r
+#define UART_MODEM_STS_nDCD_Msk (0x80UL) /*!< UART MODEM_STS: nDCD (Bitfield-Mask: 0x01) */\r
+\r
+/* --------------------------------- UART_CONFIG -------------------------------- */\r
+#define UART_CONFIG_CLK_SRC_Pos (0UL) /*!< UART CONFIG: CLK_SRC (Bit 0) */\r
+#define UART_CONFIG_CLK_SRC_Msk (0x1UL) /*!< UART CONFIG: CLK_SRC (Bitfield-Mask: 0x01) */\r
+#define UART_CONFIG_POWER_Pos (1UL) /*!< UART CONFIG: POWER (Bit 1) */\r
+#define UART_CONFIG_POWER_Msk (0x2UL) /*!< UART CONFIG: POWER (Bitfield-Mask: 0x01) */\r
+#define UART_CONFIG_POLARITY_Pos (2UL) /*!< UART CONFIG: POLARITY (Bit 2) */\r
+#define UART_CONFIG_POLARITY_Msk (0x4UL) /*!< UART CONFIG: POLARITY (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'WDT' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- WDT_CONTROL -------------------------------- */\r
+#define WDT_CONTROL_ENABLE_Pos (0UL) /*!< WDT CONTROL: ENABLE (Bit 0) */\r
+#define WDT_CONTROL_ENABLE_Msk (0x1UL) /*!< WDT CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define WDT_CONTROL_STATUS_Pos (1UL) /*!< WDT CONTROL: STATUS (Bit 1) */\r
+#define WDT_CONTROL_STATUS_Msk (0x2UL) /*!< WDT CONTROL: STATUS (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER_16_0' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------- TIMER_16_0_CONTROL ----------------------------- */\r
+#define TIMER_16_0_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_0 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER_16_0_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_0 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_0_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_0 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER_16_0_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_0 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_0_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_0 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER_16_0_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_0 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_0 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER_16_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_0_CONTROL_START_Pos (5UL) /*!< TIMER_16_0 CONTROL: START (Bit 5) */\r
+#define TIMER_16_0_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_0 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_0_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_0 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER_16_0_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_0 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_0_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_0 CONTROL: HALT (Bit 7) */\r
+#define TIMER_16_0_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_0 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_0_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_0 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER_16_0_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_0 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER_16_1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------- TIMER_16_1_CONTROL ----------------------------- */\r
+#define TIMER_16_1_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_1 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER_16_1_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_1 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_1_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_1 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER_16_1_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_1 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_1_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_1 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER_16_1_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_1 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_1 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER_16_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_1_CONTROL_START_Pos (5UL) /*!< TIMER_16_1 CONTROL: START (Bit 5) */\r
+#define TIMER_16_1_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_1 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_1_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_1 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER_16_1_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_1 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_1_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_1 CONTROL: HALT (Bit 7) */\r
+#define TIMER_16_1_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_1 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_1_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_1 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER_16_1_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_1 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER_16_2' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------- TIMER_16_2_CONTROL ----------------------------- */\r
+#define TIMER_16_2_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_2 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER_16_2_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_2 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_2_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_2 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER_16_2_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_2 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_2_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_2 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER_16_2_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_2 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_2_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_2 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER_16_2_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_2 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_2_CONTROL_START_Pos (5UL) /*!< TIMER_16_2 CONTROL: START (Bit 5) */\r
+#define TIMER_16_2_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_2 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_2_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_2 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER_16_2_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_2 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_2_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_2 CONTROL: HALT (Bit 7) */\r
+#define TIMER_16_2_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_2 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_2_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_2 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER_16_2_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_2 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER_16_3' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------- TIMER_16_3_CONTROL ----------------------------- */\r
+#define TIMER_16_3_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_3 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER_16_3_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_3 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_3_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_3 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER_16_3_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_3 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_3_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_3 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER_16_3_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_3 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_3_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_3 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER_16_3_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_3 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_3_CONTROL_START_Pos (5UL) /*!< TIMER_16_3 CONTROL: START (Bit 5) */\r
+#define TIMER_16_3_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_3 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_3_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_3 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER_16_3_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_3 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_3_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_3 CONTROL: HALT (Bit 7) */\r
+#define TIMER_16_3_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_3 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER_16_3_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_3 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER_16_3_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_3 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER_32_0' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------- TIMER_32_0_CONTROL ----------------------------- */\r
+#define TIMER_32_0_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_32_0 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER_32_0_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_32_0 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_0_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_32_0 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER_32_0_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_32_0 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_0_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_32_0 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER_32_0_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_32_0 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_32_0 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER_32_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_32_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_0_CONTROL_START_Pos (5UL) /*!< TIMER_32_0 CONTROL: START (Bit 5) */\r
+#define TIMER_32_0_CONTROL_START_Msk (0x20UL) /*!< TIMER_32_0 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_0_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_32_0 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER_32_0_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_32_0 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_0_CONTROL_HALT_Pos (7UL) /*!< TIMER_32_0 CONTROL: HALT (Bit 7) */\r
+#define TIMER_32_0_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_32_0 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_0_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_32_0 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER_32_0_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_32_0 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TIMER_32_1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------- TIMER_32_1_CONTROL ----------------------------- */\r
+#define TIMER_32_1_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_32_1 CONTROL: ENABLE (Bit 0) */\r
+#define TIMER_32_1_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_32_1 CONTROL: ENABLE (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_1_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_32_1 CONTROL: COUNT_UP (Bit 2) */\r
+#define TIMER_32_1_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_32_1 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_1_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_32_1 CONTROL: AUTO_RESTART (Bit 3) */\r
+#define TIMER_32_1_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_32_1 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_32_1 CONTROL: SOFT_RESET (Bit 4) */\r
+#define TIMER_32_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_32_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_1_CONTROL_START_Pos (5UL) /*!< TIMER_32_1 CONTROL: START (Bit 5) */\r
+#define TIMER_32_1_CONTROL_START_Msk (0x20UL) /*!< TIMER_32_1 CONTROL: START (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_1_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_32_1 CONTROL: RELOAD (Bit 6) */\r
+#define TIMER_32_1_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_32_1 CONTROL: RELOAD (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_1_CONTROL_HALT_Pos (7UL) /*!< TIMER_32_1 CONTROL: HALT (Bit 7) */\r
+#define TIMER_32_1_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_32_1 CONTROL: HALT (Bitfield-Mask: 0x01) */\r
+#define TIMER_32_1_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_32_1 CONTROL: PRE_SCALE (Bit 16) */\r
+#define TIMER_32_1_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_32_1 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'RTC' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- RTC_CONTROL -------------------------------- */\r
+#define RTC_CONTROL_BLOCK_ENABLE_Pos (0UL) /*!< RTC CONTROL: BLOCK_ENABLE (Bit 0) */\r
+#define RTC_CONTROL_BLOCK_ENABLE_Msk (0x1UL) /*!< RTC CONTROL: BLOCK_ENABLE (Bitfield-Mask: 0x01) */\r
+#define RTC_CONTROL_SOFT_RESET_Pos (1UL) /*!< RTC CONTROL: SOFT_RESET (Bit 1) */\r
+#define RTC_CONTROL_SOFT_RESET_Msk (0x2UL) /*!< RTC CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define RTC_CONTROL_ALARM_ENABLE_Pos (3UL) /*!< RTC CONTROL: ALARM_ENABLE (Bit 3) */\r
+#define RTC_CONTROL_ALARM_ENABLE_Msk (0x8UL) /*!< RTC CONTROL: ALARM_ENABLE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------ RTC_DAYLIGHT_SAVINGS_FORWARD ------------------------ */\r
+#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_MONTH_Pos (0UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_MONTH (Bit 0) */\r
+#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_MONTH_Msk (0xffUL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_MONTH (Bitfield-Mask: 0xff) */\r
+#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_DAY_OF_WEEK_Pos (8UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_DAY_OF_WEEK (Bit 8) */\r
+#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_DAY_OF_WEEK_Msk (0x700UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_DAY_OF_WEEK (Bitfield-Mask: 0x07) */\r
+#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_WEEK_Pos (16UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_WEEK (Bit 16) */\r
+#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_WEEK_Msk (0x70000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_WEEK (Bitfield-Mask: 0x07) */\r
+#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_HOUR_Pos (24UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_HOUR (Bit 24) */\r
+#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_HOUR_Msk (0x7f000000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_HOUR (Bitfield-Mask: 0x7f) */\r
+#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_AM_PM_Pos (31UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_AM_PM (Bit 31) */\r
+#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_AM_PM_Msk (0x80000000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_AM_PM (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------ RTC_DAYLIGHT_SAVINGS_BACKWARD ----------------------- */\r
+#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_MONTH_Pos (0UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_MONTH (Bit 0) */\r
+#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_MONTH_Msk (0xffUL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_MONTH (Bitfield-Mask: 0xff) */\r
+#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_DAY_OF_WEEK_Pos (8UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_DAY_OF_WEEK (Bit 8) */\r
+#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_DAY_OF_WEEK_Msk (0x700UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_DAY_OF_WEEK (Bitfield-Mask: 0x07) */\r
+#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_WEEK_Pos (16UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_WEEK (Bit 16) */\r
+#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_WEEK_Msk (0x70000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_WEEK (Bitfield-Mask: 0x07) */\r
+#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_HOUR_Pos (24UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_HOUR (Bit 24) */\r
+#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_HOUR_Msk (0x7f000000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_HOUR (Bitfield-Mask: 0x7f) */\r
+#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_AM_PM_Pos (31UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_AM_PM (Bit 31) */\r
+#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_AM_PM_Msk (0x80000000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_AM_PM (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'GPIO' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------ GPIO_PIN_CONTROL ------------------------------ */\r
+#define GPIO_PIN_CONTROL_PU_PD_Pos (0UL) /*!< GPIO PIN_CONTROL: PU_PD (Bit 0) */\r
+#define GPIO_PIN_CONTROL_PU_PD_Msk (0x3UL) /*!< GPIO PIN_CONTROL: PU_PD (Bitfield-Mask: 0x03) */\r
+#define GPIO_PIN_CONTROL_PWR_Pos (2UL) /*!< GPIO PIN_CONTROL: PWR (Bit 2) */\r
+#define GPIO_PIN_CONTROL_PWR_Msk (0xcUL) /*!< GPIO PIN_CONTROL: PWR (Bitfield-Mask: 0x03) */\r
+#define GPIO_PIN_CONTROL_INT_DET_Pos (4UL) /*!< GPIO PIN_CONTROL: INT_DET (Bit 4) */\r
+#define GPIO_PIN_CONTROL_INT_DET_Msk (0x70UL) /*!< GPIO PIN_CONTROL: INT_DET (Bitfield-Mask: 0x07) */\r
+#define GPIO_PIN_CONTROL_EDGE_EN_Pos (7UL) /*!< GPIO PIN_CONTROL: EDGE_EN (Bit 7) */\r
+#define GPIO_PIN_CONTROL_EDGE_EN_Msk (0x80UL) /*!< GPIO PIN_CONTROL: EDGE_EN (Bitfield-Mask: 0x01) */\r
+#define GPIO_PIN_CONTROL_BUFFER_Pos (8UL) /*!< GPIO PIN_CONTROL: BUFFER (Bit 8) */\r
+#define GPIO_PIN_CONTROL_BUFFER_Msk (0x100UL) /*!< GPIO PIN_CONTROL: BUFFER (Bitfield-Mask: 0x01) */\r
+#define GPIO_PIN_CONTROL_DIR_Pos (9UL) /*!< GPIO PIN_CONTROL: DIR (Bit 9) */\r
+#define GPIO_PIN_CONTROL_DIR_Msk (0x200UL) /*!< GPIO PIN_CONTROL: DIR (Bitfield-Mask: 0x01) */\r
+#define GPIO_PIN_CONTROL_OUTPUT_WRITE_EN_Pos (10UL) /*!< GPIO PIN_CONTROL: OUTPUT_WRITE_EN (Bit 10) */\r
+#define GPIO_PIN_CONTROL_OUTPUT_WRITE_EN_Msk (0x400UL) /*!< GPIO PIN_CONTROL: OUTPUT_WRITE_EN (Bitfield-Mask: 0x01) */\r
+#define GPIO_PIN_CONTROL_POLARITY_Pos (11UL) /*!< GPIO PIN_CONTROL: POLARITY (Bit 11) */\r
+#define GPIO_PIN_CONTROL_POLARITY_Msk (0x800UL) /*!< GPIO PIN_CONTROL: POLARITY (Bitfield-Mask: 0x01) */\r
+#define GPIO_PIN_CONTROL_MUX_Pos (12UL) /*!< GPIO PIN_CONTROL: MUX (Bit 12) */\r
+#define GPIO_PIN_CONTROL_MUX_Msk (0x3000UL) /*!< GPIO PIN_CONTROL: MUX (Bitfield-Mask: 0x03) */\r
+#define GPIO_PIN_CONTROL_OUTPUT_Pos (16UL) /*!< GPIO PIN_CONTROL: OUTPUT (Bit 16) */\r
+#define GPIO_PIN_CONTROL_OUTPUT_Msk (0x10000UL) /*!< GPIO PIN_CONTROL: OUTPUT (Bitfield-Mask: 0x01) */\r
+#define GPIO_PIN_CONTROL_INPUT_Pos (24UL) /*!< GPIO PIN_CONTROL: INPUT (Bit 24) */\r
+#define GPIO_PIN_CONTROL_INPUT_Msk (0x1000000UL) /*!< GPIO PIN_CONTROL: INPUT (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------- GPIO_CONTROL2_000_067 --------------------------- */\r
+#define GPIO_CONTROL2_000_067_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_000_067: SLEW_RATE (Bit 0) */\r
+#define GPIO_CONTROL2_000_067_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_000_067: SLEW_RATE (Bitfield-Mask: 0x01) */\r
+#define GPIO_CONTROL2_000_067_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_000_067: DRIVE_STRENGTH (Bit 4) */\r
+#define GPIO_CONTROL2_000_067_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_000_067: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */\r
+\r
+/* ---------------------------- GPIO_CONTROL2_100_167 --------------------------- */\r
+#define GPIO_CONTROL2_100_167_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_100_167: SLEW_RATE (Bit 0) */\r
+#define GPIO_CONTROL2_100_167_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_100_167: SLEW_RATE (Bitfield-Mask: 0x01) */\r
+#define GPIO_CONTROL2_100_167_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_100_167: DRIVE_STRENGTH (Bit 4) */\r
+#define GPIO_CONTROL2_100_167_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_100_167: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */\r
+\r
+/* ---------------------------- GPIO_CONTROL2_200_267 --------------------------- */\r
+#define GPIO_CONTROL2_200_267_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_200_267: SLEW_RATE (Bit 0) */\r
+#define GPIO_CONTROL2_200_267_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_200_267: SLEW_RATE (Bitfield-Mask: 0x01) */\r
+#define GPIO_CONTROL2_200_267_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_200_267: DRIVE_STRENGTH (Bit 4) */\r
+#define GPIO_CONTROL2_200_267_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_200_267: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'DMA' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- DMA_CONTROL -------------------------------- */\r
+#define DMA_CONTROL_ACTIVATE_Pos (0UL) /*!< DMA CONTROL: ACTIVATE (Bit 0) */\r
+#define DMA_CONTROL_ACTIVATE_Msk (0x1UL) /*!< DMA CONTROL: ACTIVATE (Bitfield-Mask: 0x01) */\r
+#define DMA_CONTROL_SOFT_RESET_Pos (1UL) /*!< DMA CONTROL: SOFT_RESET (Bit 1) */\r
+#define DMA_CONTROL_SOFT_RESET_Msk (0x2UL) /*!< DMA CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'CH' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- CH_ACTIVATE -------------------------------- */\r
+#define CH_ACTIVATE_EN_Pos (0UL) /*!< CH ACTIVATE: EN (Bit 0) */\r
+#define CH_ACTIVATE_EN_Msk (0x1UL) /*!< CH ACTIVATE: EN (Bitfield-Mask: 0x01) */\r
+\r
+/* --------------------------------- CH_CONTROL --------------------------------- */\r
+#define CH_CONTROL_RUN_Pos (0UL) /*!< CH CONTROL: RUN (Bit 0) */\r
+#define CH_CONTROL_RUN_Msk (0x1UL) /*!< CH CONTROL: RUN (Bitfield-Mask: 0x01) */\r
+#define CH_CONTROL_REQUEST_Pos (1UL) /*!< CH CONTROL: REQUEST (Bit 1) */\r
+#define CH_CONTROL_REQUEST_Msk (0x2UL) /*!< CH CONTROL: REQUEST (Bitfield-Mask: 0x01) */\r
+#define CH_CONTROL_DONE_Pos (2UL) /*!< CH CONTROL: DONE (Bit 2) */\r
+#define CH_CONTROL_DONE_Msk (0x4UL) /*!< CH CONTROL: DONE (Bitfield-Mask: 0x01) */\r
+#define CH_CONTROL_STATUS_Pos (3UL) /*!< CH CONTROL: STATUS (Bit 3) */\r
+#define CH_CONTROL_STATUS_Msk (0x18UL) /*!< CH CONTROL: STATUS (Bitfield-Mask: 0x03) */\r
+#define CH_CONTROL_BUSY_Pos (5UL) /*!< CH CONTROL: BUSY (Bit 5) */\r
+#define CH_CONTROL_BUSY_Msk (0x20UL) /*!< CH CONTROL: BUSY (Bitfield-Mask: 0x01) */\r
+#define CH_CONTROL_TX_DIRECTION_Pos (8UL) /*!< CH CONTROL: TX_DIRECTION (Bit 8) */\r
+#define CH_CONTROL_TX_DIRECTION_Msk (0x100UL) /*!< CH CONTROL: TX_DIRECTION (Bitfield-Mask: 0x01) */\r
+#define CH_CONTROL_HARDWARE_FLOW_CONTROL_DEVICE_Pos (9UL) /*!< CH CONTROL: HARDWARE_FLOW_CONTROL_DEVICE (Bit 9) */\r
+#define CH_CONTROL_HARDWARE_FLOW_CONTROL_DEVICE_Msk (0xfe00UL) /*!< CH CONTROL: HARDWARE_FLOW_CONTROL_DEVICE (Bitfield-Mask: 0x7f) */\r
+#define CH_CONTROL_INCREMENT_MEM_ADDR_Pos (16UL) /*!< CH CONTROL: INCREMENT_MEM_ADDR (Bit 16) */\r
+#define CH_CONTROL_INCREMENT_MEM_ADDR_Msk (0x10000UL) /*!< CH CONTROL: INCREMENT_MEM_ADDR (Bitfield-Mask: 0x01) */\r
+#define CH_CONTROL_INCREMENT_DEVICE_ADDR_Pos (17UL) /*!< CH CONTROL: INCREMENT_DEVICE_ADDR (Bit 17) */\r
+#define CH_CONTROL_INCREMENT_DEVICE_ADDR_Msk (0x20000UL) /*!< CH CONTROL: INCREMENT_DEVICE_ADDR (Bitfield-Mask: 0x01) */\r
+#define CH_CONTROL_LOCK_Pos (18UL) /*!< CH CONTROL: LOCK (Bit 18) */\r
+#define CH_CONTROL_LOCK_Msk (0x40000UL) /*!< CH CONTROL: LOCK (Bitfield-Mask: 0x01) */\r
+#define CH_CONTROL_DISABLE_HW_FLOW_CONTROL_Pos (19UL) /*!< CH CONTROL: DISABLE_HW_FLOW_CONTROL (Bit 19) */\r
+#define CH_CONTROL_DISABLE_HW_FLOW_CONTROL_Msk (0x80000UL) /*!< CH CONTROL: DISABLE_HW_FLOW_CONTROL (Bitfield-Mask: 0x01) */\r
+#define CH_CONTROL_TRANSFER_SIZE_Pos (20UL) /*!< CH CONTROL: TRANSFER_SIZE (Bit 20) */\r
+#define CH_CONTROL_TRANSFER_SIZE_Msk (0x700000UL) /*!< CH CONTROL: TRANSFER_SIZE (Bitfield-Mask: 0x07) */\r
+#define CH_CONTROL_TRANSFER_GO_Pos (24UL) /*!< CH CONTROL: TRANSFER_GO (Bit 24) */\r
+#define CH_CONTROL_TRANSFER_GO_Msk (0x1000000UL) /*!< CH CONTROL: TRANSFER_GO (Bitfield-Mask: 0x01) */\r
+#define CH_CONTROL_TRANSFER_ABORT_Pos (25UL) /*!< CH CONTROL: TRANSFER_ABORT (Bit 25) */\r
+#define CH_CONTROL_TRANSFER_ABORT_Msk (0x2000000UL) /*!< CH CONTROL: TRANSFER_ABORT (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- CH_INT_STATUS ------------------------------- */\r
+#define CH_INT_STATUS_BUS_ERROR_Pos (0UL) /*!< CH INT_STATUS: BUS_ERROR (Bit 0) */\r
+#define CH_INT_STATUS_BUS_ERROR_Msk (0x1UL) /*!< CH INT_STATUS: BUS_ERROR (Bitfield-Mask: 0x01) */\r
+#define CH_INT_STATUS_FLOW_CONTROL_Pos (1UL) /*!< CH INT_STATUS: FLOW_CONTROL (Bit 1) */\r
+#define CH_INT_STATUS_FLOW_CONTROL_Msk (0x2UL) /*!< CH INT_STATUS: FLOW_CONTROL (Bitfield-Mask: 0x01) */\r
+#define CH_INT_STATUS_DONE_Pos (2UL) /*!< CH INT_STATUS: DONE (Bit 2) */\r
+#define CH_INT_STATUS_DONE_Msk (0x4UL) /*!< CH INT_STATUS: DONE (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------------- CH_INT_EN --------------------------------- */\r
+#define CH_INT_EN_BUS_ERROR_Pos (0UL) /*!< CH INT_EN: BUS_ERROR (Bit 0) */\r
+#define CH_INT_EN_BUS_ERROR_Msk (0x1UL) /*!< CH INT_EN: BUS_ERROR (Bitfield-Mask: 0x01) */\r
+#define CH_INT_EN_FLOW_CONTROL_Pos (1UL) /*!< CH INT_EN: FLOW_CONTROL (Bit 1) */\r
+#define CH_INT_EN_FLOW_CONTROL_Msk (0x2UL) /*!< CH INT_EN: FLOW_CONTROL (Bitfield-Mask: 0x01) */\r
+#define CH_INT_EN_DONE_Pos (2UL) /*!< CH INT_EN: DONE (Bit 2) */\r
+#define CH_INT_EN_DONE_Msk (0x4UL) /*!< CH INT_EN: DONE (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SMB0' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- SMB0_CONTROL -------------------------------- */\r
+#define SMB0_CONTROL_ACK_Pos (0UL) /*!< SMB0 CONTROL: ACK (Bit 0) */\r
+#define SMB0_CONTROL_ACK_Msk (0x1UL) /*!< SMB0 CONTROL: ACK (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONTROL_STO_Pos (1UL) /*!< SMB0 CONTROL: STO (Bit 1) */\r
+#define SMB0_CONTROL_STO_Msk (0x2UL) /*!< SMB0 CONTROL: STO (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONTROL_STA_Pos (2UL) /*!< SMB0 CONTROL: STA (Bit 2) */\r
+#define SMB0_CONTROL_STA_Msk (0x4UL) /*!< SMB0 CONTROL: STA (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONTROL_ENI_Pos (3UL) /*!< SMB0 CONTROL: ENI (Bit 3) */\r
+#define SMB0_CONTROL_ENI_Msk (0x8UL) /*!< SMB0 CONTROL: ENI (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONTROL_ESO_Pos (6UL) /*!< SMB0 CONTROL: ESO (Bit 6) */\r
+#define SMB0_CONTROL_ESO_Msk (0x40UL) /*!< SMB0 CONTROL: ESO (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONTROL_PIN_Pos (7UL) /*!< SMB0 CONTROL: PIN (Bit 7) */\r
+#define SMB0_CONTROL_PIN_Msk (0x80UL) /*!< SMB0 CONTROL: PIN (Bitfield-Mask: 0x01) */\r
+\r
+/* --------------------------------- SMB0_STATUS -------------------------------- */\r
+#define SMB0_STATUS_nBB_Pos (0UL) /*!< SMB0 STATUS: nBB (Bit 0) */\r
+#define SMB0_STATUS_nBB_Msk (0x1UL) /*!< SMB0 STATUS: nBB (Bitfield-Mask: 0x01) */\r
+#define SMB0_STATUS_LAB_Pos (1UL) /*!< SMB0 STATUS: LAB (Bit 1) */\r
+#define SMB0_STATUS_LAB_Msk (0x2UL) /*!< SMB0 STATUS: LAB (Bitfield-Mask: 0x01) */\r
+#define SMB0_STATUS_AAS_Pos (2UL) /*!< SMB0 STATUS: AAS (Bit 2) */\r
+#define SMB0_STATUS_AAS_Msk (0x4UL) /*!< SMB0 STATUS: AAS (Bitfield-Mask: 0x01) */\r
+#define SMB0_STATUS_LRB_AD0_Pos (3UL) /*!< SMB0 STATUS: LRB_AD0 (Bit 3) */\r
+#define SMB0_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB0 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */\r
+#define SMB0_STATUS_BER_Pos (4UL) /*!< SMB0 STATUS: BER (Bit 4) */\r
+#define SMB0_STATUS_BER_Msk (0x10UL) /*!< SMB0 STATUS: BER (Bitfield-Mask: 0x01) */\r
+#define SMB0_STATUS_STS_Pos (5UL) /*!< SMB0 STATUS: STS (Bit 5) */\r
+#define SMB0_STATUS_STS_Msk (0x20UL) /*!< SMB0 STATUS: STS (Bitfield-Mask: 0x01) */\r
+#define SMB0_STATUS_SAD_Pos (6UL) /*!< SMB0 STATUS: SAD (Bit 6) */\r
+#define SMB0_STATUS_SAD_Msk (0x40UL) /*!< SMB0 STATUS: SAD (Bitfield-Mask: 0x01) */\r
+#define SMB0_STATUS_PIN_Pos (7UL) /*!< SMB0 STATUS: PIN (Bit 7) */\r
+#define SMB0_STATUS_PIN_Msk (0x80UL) /*!< SMB0 STATUS: PIN (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------------- SMB0_OWN ---------------------------------- */\r
+#define SMB0_OWN_ADDRESS_1_Pos (0UL) /*!< SMB0 OWN: ADDRESS_1 (Bit 0) */\r
+#define SMB0_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB0 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */\r
+#define SMB0_OWN_ADDRESS_2_Pos (8UL) /*!< SMB0 OWN: ADDRESS_2 (Bit 8) */\r
+#define SMB0_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB0 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */\r
+\r
+/* ----------------------------- SMB0_MASTER_COMMAND ---------------------------- */\r
+#define SMB0_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB0 MASTER_COMMAND: MRUN (Bit 0) */\r
+#define SMB0_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB0 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */\r
+#define SMB0_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB0 MASTER_COMMAND: MPROCEED (Bit 1) */\r
+#define SMB0_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB0 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */\r
+#define SMB0_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB0 MASTER_COMMAND: START0 (Bit 8) */\r
+#define SMB0_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB0 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */\r
+#define SMB0_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB0 MASTER_COMMAND: STARTN (Bit 9) */\r
+#define SMB0_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB0 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */\r
+#define SMB0_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB0 MASTER_COMMAND: STOP (Bit 10) */\r
+#define SMB0_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB0 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */\r
+#define SMB0_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB0 MASTER_COMMAND: PEC_TERM (Bit 11) */\r
+#define SMB0_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB0 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */\r
+#define SMB0_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB0 MASTER_COMMAND: READM (Bit 12) */\r
+#define SMB0_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB0 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */\r
+#define SMB0_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB0 MASTER_COMMAND: READ_PEC (Bit 13) */\r
+#define SMB0_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB0 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */\r
+#define SMB0_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB0 MASTER_COMMAND: WRITECOUNT (Bit 16) */\r
+#define SMB0_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB0 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */\r
+#define SMB0_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB0 MASTER_COMMAND: READCOUNT (Bit 24) */\r
+#define SMB0_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB0 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */\r
+\r
+/* ----------------------------- SMB0_SLAVE_COMMAND ----------------------------- */\r
+#define SMB0_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB0 SLAVE_COMMAND: SRUN (Bit 0) */\r
+#define SMB0_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB0 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */\r
+#define SMB0_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB0 SLAVE_COMMAND: SPROCEED (Bit 1) */\r
+#define SMB0_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB0 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */\r
+#define SMB0_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */\r
+#define SMB0_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */\r
+#define SMB0_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */\r
+#define SMB0_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */\r
+#define SMB0_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */\r
+#define SMB0_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */\r
+\r
+/* ------------------------------- SMB0_COMPLETION ------------------------------ */\r
+#define SMB0_COMPLETION_DTEN_Pos (2UL) /*!< SMB0 COMPLETION: DTEN (Bit 2) */\r
+#define SMB0_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB0 COMPLETION: DTEN (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_MCEN_Pos (3UL) /*!< SMB0 COMPLETION: MCEN (Bit 3) */\r
+#define SMB0_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB0 COMPLETION: MCEN (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_SCEN_Pos (4UL) /*!< SMB0 COMPLETION: SCEN (Bit 4) */\r
+#define SMB0_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB0 COMPLETION: SCEN (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_BIDEN_Pos (5UL) /*!< SMB0 COMPLETION: BIDEN (Bit 5) */\r
+#define SMB0_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB0 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_TIMERR_Pos (6UL) /*!< SMB0 COMPLETION: TIMERR (Bit 6) */\r
+#define SMB0_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB0 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_DTO_Pos (8UL) /*!< SMB0 COMPLETION: DTO (Bit 8) */\r
+#define SMB0_COMPLETION_DTO_Msk (0x100UL) /*!< SMB0 COMPLETION: DTO (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_MCTO_Pos (9UL) /*!< SMB0 COMPLETION: MCTO (Bit 9) */\r
+#define SMB0_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB0 COMPLETION: MCTO (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_SCTO_Pos (10UL) /*!< SMB0 COMPLETION: SCTO (Bit 10) */\r
+#define SMB0_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB0 COMPLETION: SCTO (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_CHDL_Pos (11UL) /*!< SMB0 COMPLETION: CHDL (Bit 11) */\r
+#define SMB0_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB0 COMPLETION: CHDL (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_CHDH_Pos (12UL) /*!< SMB0 COMPLETION: CHDH (Bit 12) */\r
+#define SMB0_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB0 COMPLETION: CHDH (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_BER_Pos (13UL) /*!< SMB0 COMPLETION: BER (Bit 13) */\r
+#define SMB0_COMPLETION_BER_Msk (0x2000UL) /*!< SMB0 COMPLETION: BER (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_LAB_Pos (14UL) /*!< SMB0 COMPLETION: LAB (Bit 14) */\r
+#define SMB0_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB0 COMPLETION: LAB (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_SNAKR_Pos (16UL) /*!< SMB0 COMPLETION: SNAKR (Bit 16) */\r
+#define SMB0_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB0 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_STR_Pos (17UL) /*!< SMB0 COMPLETION: STR (Bit 17) */\r
+#define SMB0_COMPLETION_STR_Msk (0x20000UL) /*!< SMB0 COMPLETION: STR (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_SPROT_Pos (19UL) /*!< SMB0 COMPLETION: SPROT (Bit 19) */\r
+#define SMB0_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB0 COMPLETION: SPROT (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB0 COMPLETION: REPEAT_READ (Bit 20) */\r
+#define SMB0_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB0 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB0 COMPLETION: REPEAT_WRITE (Bit 21) */\r
+#define SMB0_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB0 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_MNAKX_Pos (24UL) /*!< SMB0 COMPLETION: MNAKX (Bit 24) */\r
+#define SMB0_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB0 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_MTR_Pos (25UL) /*!< SMB0 COMPLETION: MTR (Bit 25) */\r
+#define SMB0_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB0 COMPLETION: MTR (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_IDLE_Pos (29UL) /*!< SMB0 COMPLETION: IDLE (Bit 29) */\r
+#define SMB0_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB0 COMPLETION: IDLE (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_MDONE_Pos (30UL) /*!< SMB0 COMPLETION: MDONE (Bit 30) */\r
+#define SMB0_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB0 COMPLETION: MDONE (Bitfield-Mask: 0x01) */\r
+#define SMB0_COMPLETION_SDONE_Pos (31UL) /*!< SMB0 COMPLETION: SDONE (Bit 31) */\r
+#define SMB0_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB0 COMPLETION: SDONE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ SMB0_IDLE_SCALING ----------------------------- */\r
+#define SMB0_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB0 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */\r
+#define SMB0_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB0 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */\r
+#define SMB0_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB0 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */\r
+#define SMB0_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB0 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */\r
+\r
+/* ----------------------------- SMB0_CONFIGURATION ----------------------------- */\r
+#define SMB0_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB0 CONFIGURATION: PORT_SEL (Bit 0) */\r
+#define SMB0_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB0 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */\r
+#define SMB0_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB0 CONFIGURATION: TCEN (Bit 4) */\r
+#define SMB0_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB0 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB0 CONFIGURATION: SLOW_CLOCK (Bit 5) */\r
+#define SMB0_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB0 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB0 CONFIGURATION: PECEN (Bit 7) */\r
+#define SMB0_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB0 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB0 CONFIGURATION: DFEN (Bit 8) */\r
+#define SMB0_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB0 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_RESET_Pos (9UL) /*!< SMB0 CONFIGURATION: RESET (Bit 9) */\r
+#define SMB0_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB0 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB0 CONFIGURATION: ENAB (Bit 10) */\r
+#define SMB0_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB0 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_DSA_Pos (11UL) /*!< SMB0 CONFIGURATION: DSA (Bit 11) */\r
+#define SMB0_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB0 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB0 CONFIGURATION: FAIR (Bit 12) */\r
+#define SMB0_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB0 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB0 CONFIGURATION: GC_DIS (Bit 14) */\r
+#define SMB0_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB0 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB0 CONFIGURATION: FLUSH_SXBUF (Bit 16) */\r
+#define SMB0_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB0 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB0 CONFIGURATION: FLUSH_SRBUF (Bit 17) */\r
+#define SMB0_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB0 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB0 CONFIGURATION: FLUSH_MXBUF (Bit 18) */\r
+#define SMB0_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB0 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB0 CONFIGURATION: FLUSH_MRBUF (Bit 19) */\r
+#define SMB0_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB0 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB0 CONFIGURATION: EN_AAS (Bit 28) */\r
+#define SMB0_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB0 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB0 CONFIGURATION: ENIDI (Bit 29) */\r
+#define SMB0_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB0 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB0 CONFIGURATION: ENMI (Bit 30) */\r
+#define SMB0_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB0 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */\r
+#define SMB0_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB0 CONFIGURATION: ENSI (Bit 31) */\r
+#define SMB0_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB0 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- SMB0_BUS_CLOCK ------------------------------- */\r
+#define SMB0_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB0 BUS_CLOCK: LOW_PERIOD (Bit 0) */\r
+#define SMB0_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB0 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */\r
+#define SMB0_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB0 BUS_CLOCK: HIGH_PERIOD (Bit 8) */\r
+#define SMB0_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB0 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */\r
+\r
+/* ---------------------------- SMB0_BIT_BANG_CONTROL --------------------------- */\r
+#define SMB0_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB0 BIT_BANG_CONTROL: BBEN (Bit 0) */\r
+#define SMB0_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB0 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */\r
+#define SMB0_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB0 BIT_BANG_CONTROL: CLDIR (Bit 1) */\r
+#define SMB0_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB0 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */\r
+#define SMB0_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB0 BIT_BANG_CONTROL: DADIR (Bit 2) */\r
+#define SMB0_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB0 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */\r
+#define SMB0_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLK (Bit 3) */\r
+#define SMB0_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */\r
+#define SMB0_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB0 BIT_BANG_CONTROL: BBDAT (Bit 4) */\r
+#define SMB0_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB0 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */\r
+#define SMB0_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLKI (Bit 5) */\r
+#define SMB0_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */\r
+#define SMB0_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB0 BIT_BANG_CONTROL: BBDATI (Bit 6) */\r
+#define SMB0_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB0 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ SMB0_DATA_TIMING ------------------------------ */\r
+#define SMB0_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB0 DATA_TIMING: DATA_HOLD (Bit 0) */\r
+#define SMB0_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB0 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */\r
+#define SMB0_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB0 DATA_TIMING: RESTART_SETUP (Bit 8) */\r
+#define SMB0_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB0 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */\r
+#define SMB0_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB0 DATA_TIMING: STOP_SETUP (Bit 16) */\r
+#define SMB0_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB0 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */\r
+#define SMB0_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB0 DATA_TIMING: START_HOLD (Bit 24) */\r
+#define SMB0_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB0 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */\r
+\r
+/* ---------------------------- SMB0_TIME_OUT_SCALING --------------------------- */\r
+#define SMB0_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB0 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */\r
+#define SMB0_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB0 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */\r
+#define SMB0_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB0 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */\r
+#define SMB0_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB0 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */\r
+#define SMB0_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB0 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */\r
+#define SMB0_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB0 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */\r
+#define SMB0_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB0 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */\r
+#define SMB0_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB0 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SMB1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- SMB1_STATUS -------------------------------- */\r
+#define SMB1_STATUS_nBB_Pos (0UL) /*!< SMB1 STATUS: nBB (Bit 0) */\r
+#define SMB1_STATUS_nBB_Msk (0x1UL) /*!< SMB1 STATUS: nBB (Bitfield-Mask: 0x01) */\r
+#define SMB1_STATUS_LAB_Pos (1UL) /*!< SMB1 STATUS: LAB (Bit 1) */\r
+#define SMB1_STATUS_LAB_Msk (0x2UL) /*!< SMB1 STATUS: LAB (Bitfield-Mask: 0x01) */\r
+#define SMB1_STATUS_AAS_Pos (2UL) /*!< SMB1 STATUS: AAS (Bit 2) */\r
+#define SMB1_STATUS_AAS_Msk (0x4UL) /*!< SMB1 STATUS: AAS (Bitfield-Mask: 0x01) */\r
+#define SMB1_STATUS_LRB_AD0_Pos (3UL) /*!< SMB1 STATUS: LRB_AD0 (Bit 3) */\r
+#define SMB1_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB1 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */\r
+#define SMB1_STATUS_BER_Pos (4UL) /*!< SMB1 STATUS: BER (Bit 4) */\r
+#define SMB1_STATUS_BER_Msk (0x10UL) /*!< SMB1 STATUS: BER (Bitfield-Mask: 0x01) */\r
+#define SMB1_STATUS_STS_Pos (5UL) /*!< SMB1 STATUS: STS (Bit 5) */\r
+#define SMB1_STATUS_STS_Msk (0x20UL) /*!< SMB1 STATUS: STS (Bitfield-Mask: 0x01) */\r
+#define SMB1_STATUS_SAD_Pos (6UL) /*!< SMB1 STATUS: SAD (Bit 6) */\r
+#define SMB1_STATUS_SAD_Msk (0x40UL) /*!< SMB1 STATUS: SAD (Bitfield-Mask: 0x01) */\r
+#define SMB1_STATUS_PIN_Pos (7UL) /*!< SMB1 STATUS: PIN (Bit 7) */\r
+#define SMB1_STATUS_PIN_Msk (0x80UL) /*!< SMB1 STATUS: PIN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- SMB1_CONTROL -------------------------------- */\r
+#define SMB1_CONTROL_ACK_Pos (0UL) /*!< SMB1 CONTROL: ACK (Bit 0) */\r
+#define SMB1_CONTROL_ACK_Msk (0x1UL) /*!< SMB1 CONTROL: ACK (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONTROL_STO_Pos (1UL) /*!< SMB1 CONTROL: STO (Bit 1) */\r
+#define SMB1_CONTROL_STO_Msk (0x2UL) /*!< SMB1 CONTROL: STO (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONTROL_STA_Pos (2UL) /*!< SMB1 CONTROL: STA (Bit 2) */\r
+#define SMB1_CONTROL_STA_Msk (0x4UL) /*!< SMB1 CONTROL: STA (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONTROL_ENI_Pos (3UL) /*!< SMB1 CONTROL: ENI (Bit 3) */\r
+#define SMB1_CONTROL_ENI_Msk (0x8UL) /*!< SMB1 CONTROL: ENI (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONTROL_ESO_Pos (6UL) /*!< SMB1 CONTROL: ESO (Bit 6) */\r
+#define SMB1_CONTROL_ESO_Msk (0x40UL) /*!< SMB1 CONTROL: ESO (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONTROL_PIN_Pos (7UL) /*!< SMB1 CONTROL: PIN (Bit 7) */\r
+#define SMB1_CONTROL_PIN_Msk (0x80UL) /*!< SMB1 CONTROL: PIN (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------------- SMB1_OWN ---------------------------------- */\r
+#define SMB1_OWN_ADDRESS_1_Pos (0UL) /*!< SMB1 OWN: ADDRESS_1 (Bit 0) */\r
+#define SMB1_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB1 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */\r
+#define SMB1_OWN_ADDRESS_2_Pos (8UL) /*!< SMB1 OWN: ADDRESS_2 (Bit 8) */\r
+#define SMB1_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB1 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */\r
+\r
+/* ----------------------------- SMB1_MASTER_COMMAND ---------------------------- */\r
+#define SMB1_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB1 MASTER_COMMAND: MRUN (Bit 0) */\r
+#define SMB1_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB1 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */\r
+#define SMB1_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB1 MASTER_COMMAND: MPROCEED (Bit 1) */\r
+#define SMB1_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB1 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */\r
+#define SMB1_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB1 MASTER_COMMAND: START0 (Bit 8) */\r
+#define SMB1_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB1 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */\r
+#define SMB1_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB1 MASTER_COMMAND: STARTN (Bit 9) */\r
+#define SMB1_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB1 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */\r
+#define SMB1_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB1 MASTER_COMMAND: STOP (Bit 10) */\r
+#define SMB1_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB1 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */\r
+#define SMB1_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB1 MASTER_COMMAND: PEC_TERM (Bit 11) */\r
+#define SMB1_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB1 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */\r
+#define SMB1_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB1 MASTER_COMMAND: READM (Bit 12) */\r
+#define SMB1_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB1 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */\r
+#define SMB1_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB1 MASTER_COMMAND: READ_PEC (Bit 13) */\r
+#define SMB1_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB1 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */\r
+#define SMB1_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB1 MASTER_COMMAND: WRITECOUNT (Bit 16) */\r
+#define SMB1_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB1 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */\r
+#define SMB1_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB1 MASTER_COMMAND: READCOUNT (Bit 24) */\r
+#define SMB1_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB1 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */\r
+\r
+/* ----------------------------- SMB1_SLAVE_COMMAND ----------------------------- */\r
+#define SMB1_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB1 SLAVE_COMMAND: SRUN (Bit 0) */\r
+#define SMB1_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB1 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */\r
+#define SMB1_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB1 SLAVE_COMMAND: SPROCEED (Bit 1) */\r
+#define SMB1_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB1 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */\r
+#define SMB1_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */\r
+#define SMB1_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */\r
+#define SMB1_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */\r
+#define SMB1_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */\r
+#define SMB1_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */\r
+#define SMB1_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */\r
+\r
+/* ------------------------------- SMB1_COMPLETION ------------------------------ */\r
+#define SMB1_COMPLETION_DTEN_Pos (2UL) /*!< SMB1 COMPLETION: DTEN (Bit 2) */\r
+#define SMB1_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB1 COMPLETION: DTEN (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_MCEN_Pos (3UL) /*!< SMB1 COMPLETION: MCEN (Bit 3) */\r
+#define SMB1_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB1 COMPLETION: MCEN (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_SCEN_Pos (4UL) /*!< SMB1 COMPLETION: SCEN (Bit 4) */\r
+#define SMB1_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB1 COMPLETION: SCEN (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_BIDEN_Pos (5UL) /*!< SMB1 COMPLETION: BIDEN (Bit 5) */\r
+#define SMB1_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB1 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_TIMERR_Pos (6UL) /*!< SMB1 COMPLETION: TIMERR (Bit 6) */\r
+#define SMB1_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB1 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_DTO_Pos (8UL) /*!< SMB1 COMPLETION: DTO (Bit 8) */\r
+#define SMB1_COMPLETION_DTO_Msk (0x100UL) /*!< SMB1 COMPLETION: DTO (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_MCTO_Pos (9UL) /*!< SMB1 COMPLETION: MCTO (Bit 9) */\r
+#define SMB1_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB1 COMPLETION: MCTO (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_SCTO_Pos (10UL) /*!< SMB1 COMPLETION: SCTO (Bit 10) */\r
+#define SMB1_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB1 COMPLETION: SCTO (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_CHDL_Pos (11UL) /*!< SMB1 COMPLETION: CHDL (Bit 11) */\r
+#define SMB1_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB1 COMPLETION: CHDL (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_CHDH_Pos (12UL) /*!< SMB1 COMPLETION: CHDH (Bit 12) */\r
+#define SMB1_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB1 COMPLETION: CHDH (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_BER_Pos (13UL) /*!< SMB1 COMPLETION: BER (Bit 13) */\r
+#define SMB1_COMPLETION_BER_Msk (0x2000UL) /*!< SMB1 COMPLETION: BER (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_LAB_Pos (14UL) /*!< SMB1 COMPLETION: LAB (Bit 14) */\r
+#define SMB1_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB1 COMPLETION: LAB (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_SNAKR_Pos (16UL) /*!< SMB1 COMPLETION: SNAKR (Bit 16) */\r
+#define SMB1_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB1 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_STR_Pos (17UL) /*!< SMB1 COMPLETION: STR (Bit 17) */\r
+#define SMB1_COMPLETION_STR_Msk (0x20000UL) /*!< SMB1 COMPLETION: STR (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_SPROT_Pos (19UL) /*!< SMB1 COMPLETION: SPROT (Bit 19) */\r
+#define SMB1_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB1 COMPLETION: SPROT (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB1 COMPLETION: REPEAT_READ (Bit 20) */\r
+#define SMB1_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB1 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB1 COMPLETION: REPEAT_WRITE (Bit 21) */\r
+#define SMB1_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB1 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_MNAKX_Pos (24UL) /*!< SMB1 COMPLETION: MNAKX (Bit 24) */\r
+#define SMB1_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB1 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_MTR_Pos (25UL) /*!< SMB1 COMPLETION: MTR (Bit 25) */\r
+#define SMB1_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB1 COMPLETION: MTR (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_IDLE_Pos (29UL) /*!< SMB1 COMPLETION: IDLE (Bit 29) */\r
+#define SMB1_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB1 COMPLETION: IDLE (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_MDONE_Pos (30UL) /*!< SMB1 COMPLETION: MDONE (Bit 30) */\r
+#define SMB1_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB1 COMPLETION: MDONE (Bitfield-Mask: 0x01) */\r
+#define SMB1_COMPLETION_SDONE_Pos (31UL) /*!< SMB1 COMPLETION: SDONE (Bit 31) */\r
+#define SMB1_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB1 COMPLETION: SDONE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ SMB1_IDLE_SCALING ----------------------------- */\r
+#define SMB1_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB1 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */\r
+#define SMB1_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB1 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */\r
+#define SMB1_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB1 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */\r
+#define SMB1_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB1 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */\r
+\r
+/* ----------------------------- SMB1_CONFIGURATION ----------------------------- */\r
+#define SMB1_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB1 CONFIGURATION: PORT_SEL (Bit 0) */\r
+#define SMB1_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB1 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */\r
+#define SMB1_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB1 CONFIGURATION: TCEN (Bit 4) */\r
+#define SMB1_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB1 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB1 CONFIGURATION: SLOW_CLOCK (Bit 5) */\r
+#define SMB1_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB1 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB1 CONFIGURATION: PECEN (Bit 7) */\r
+#define SMB1_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB1 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB1 CONFIGURATION: DFEN (Bit 8) */\r
+#define SMB1_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB1 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_RESET_Pos (9UL) /*!< SMB1 CONFIGURATION: RESET (Bit 9) */\r
+#define SMB1_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB1 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB1 CONFIGURATION: ENAB (Bit 10) */\r
+#define SMB1_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB1 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_DSA_Pos (11UL) /*!< SMB1 CONFIGURATION: DSA (Bit 11) */\r
+#define SMB1_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB1 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB1 CONFIGURATION: FAIR (Bit 12) */\r
+#define SMB1_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB1 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB1 CONFIGURATION: GC_DIS (Bit 14) */\r
+#define SMB1_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB1 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB1 CONFIGURATION: FLUSH_SXBUF (Bit 16) */\r
+#define SMB1_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB1 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB1 CONFIGURATION: FLUSH_SRBUF (Bit 17) */\r
+#define SMB1_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB1 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB1 CONFIGURATION: FLUSH_MXBUF (Bit 18) */\r
+#define SMB1_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB1 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB1 CONFIGURATION: FLUSH_MRBUF (Bit 19) */\r
+#define SMB1_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB1 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB1 CONFIGURATION: EN_AAS (Bit 28) */\r
+#define SMB1_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB1 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB1 CONFIGURATION: ENIDI (Bit 29) */\r
+#define SMB1_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB1 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB1 CONFIGURATION: ENMI (Bit 30) */\r
+#define SMB1_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB1 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */\r
+#define SMB1_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB1 CONFIGURATION: ENSI (Bit 31) */\r
+#define SMB1_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB1 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- SMB1_BUS_CLOCK ------------------------------- */\r
+#define SMB1_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB1 BUS_CLOCK: LOW_PERIOD (Bit 0) */\r
+#define SMB1_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB1 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */\r
+#define SMB1_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB1 BUS_CLOCK: HIGH_PERIOD (Bit 8) */\r
+#define SMB1_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB1 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */\r
+\r
+/* ---------------------------- SMB1_BIT_BANG_CONTROL --------------------------- */\r
+#define SMB1_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB1 BIT_BANG_CONTROL: BBEN (Bit 0) */\r
+#define SMB1_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB1 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */\r
+#define SMB1_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB1 BIT_BANG_CONTROL: CLDIR (Bit 1) */\r
+#define SMB1_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB1 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */\r
+#define SMB1_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB1 BIT_BANG_CONTROL: DADIR (Bit 2) */\r
+#define SMB1_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB1 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */\r
+#define SMB1_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLK (Bit 3) */\r
+#define SMB1_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */\r
+#define SMB1_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB1 BIT_BANG_CONTROL: BBDAT (Bit 4) */\r
+#define SMB1_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB1 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */\r
+#define SMB1_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLKI (Bit 5) */\r
+#define SMB1_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */\r
+#define SMB1_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB1 BIT_BANG_CONTROL: BBDATI (Bit 6) */\r
+#define SMB1_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB1 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ SMB1_DATA_TIMING ------------------------------ */\r
+#define SMB1_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB1 DATA_TIMING: DATA_HOLD (Bit 0) */\r
+#define SMB1_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB1 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */\r
+#define SMB1_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB1 DATA_TIMING: RESTART_SETUP (Bit 8) */\r
+#define SMB1_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB1 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */\r
+#define SMB1_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB1 DATA_TIMING: STOP_SETUP (Bit 16) */\r
+#define SMB1_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB1 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */\r
+#define SMB1_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB1 DATA_TIMING: START_HOLD (Bit 24) */\r
+#define SMB1_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB1 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */\r
+\r
+/* ---------------------------- SMB1_TIME_OUT_SCALING --------------------------- */\r
+#define SMB1_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB1 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */\r
+#define SMB1_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB1 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */\r
+#define SMB1_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB1 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */\r
+#define SMB1_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB1 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */\r
+#define SMB1_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB1 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */\r
+#define SMB1_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB1 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */\r
+#define SMB1_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB1 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */\r
+#define SMB1_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB1 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SMB2' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- SMB2_STATUS -------------------------------- */\r
+#define SMB2_STATUS_nBB_Pos (0UL) /*!< SMB2 STATUS: nBB (Bit 0) */\r
+#define SMB2_STATUS_nBB_Msk (0x1UL) /*!< SMB2 STATUS: nBB (Bitfield-Mask: 0x01) */\r
+#define SMB2_STATUS_LAB_Pos (1UL) /*!< SMB2 STATUS: LAB (Bit 1) */\r
+#define SMB2_STATUS_LAB_Msk (0x2UL) /*!< SMB2 STATUS: LAB (Bitfield-Mask: 0x01) */\r
+#define SMB2_STATUS_AAS_Pos (2UL) /*!< SMB2 STATUS: AAS (Bit 2) */\r
+#define SMB2_STATUS_AAS_Msk (0x4UL) /*!< SMB2 STATUS: AAS (Bitfield-Mask: 0x01) */\r
+#define SMB2_STATUS_LRB_AD0_Pos (3UL) /*!< SMB2 STATUS: LRB_AD0 (Bit 3) */\r
+#define SMB2_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB2 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */\r
+#define SMB2_STATUS_BER_Pos (4UL) /*!< SMB2 STATUS: BER (Bit 4) */\r
+#define SMB2_STATUS_BER_Msk (0x10UL) /*!< SMB2 STATUS: BER (Bitfield-Mask: 0x01) */\r
+#define SMB2_STATUS_STS_Pos (5UL) /*!< SMB2 STATUS: STS (Bit 5) */\r
+#define SMB2_STATUS_STS_Msk (0x20UL) /*!< SMB2 STATUS: STS (Bitfield-Mask: 0x01) */\r
+#define SMB2_STATUS_SAD_Pos (6UL) /*!< SMB2 STATUS: SAD (Bit 6) */\r
+#define SMB2_STATUS_SAD_Msk (0x40UL) /*!< SMB2 STATUS: SAD (Bitfield-Mask: 0x01) */\r
+#define SMB2_STATUS_PIN_Pos (7UL) /*!< SMB2 STATUS: PIN (Bit 7) */\r
+#define SMB2_STATUS_PIN_Msk (0x80UL) /*!< SMB2 STATUS: PIN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- SMB2_CONTROL -------------------------------- */\r
+#define SMB2_CONTROL_ACK_Pos (0UL) /*!< SMB2 CONTROL: ACK (Bit 0) */\r
+#define SMB2_CONTROL_ACK_Msk (0x1UL) /*!< SMB2 CONTROL: ACK (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONTROL_STO_Pos (1UL) /*!< SMB2 CONTROL: STO (Bit 1) */\r
+#define SMB2_CONTROL_STO_Msk (0x2UL) /*!< SMB2 CONTROL: STO (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONTROL_STA_Pos (2UL) /*!< SMB2 CONTROL: STA (Bit 2) */\r
+#define SMB2_CONTROL_STA_Msk (0x4UL) /*!< SMB2 CONTROL: STA (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONTROL_ENI_Pos (3UL) /*!< SMB2 CONTROL: ENI (Bit 3) */\r
+#define SMB2_CONTROL_ENI_Msk (0x8UL) /*!< SMB2 CONTROL: ENI (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONTROL_ESO_Pos (6UL) /*!< SMB2 CONTROL: ESO (Bit 6) */\r
+#define SMB2_CONTROL_ESO_Msk (0x40UL) /*!< SMB2 CONTROL: ESO (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONTROL_PIN_Pos (7UL) /*!< SMB2 CONTROL: PIN (Bit 7) */\r
+#define SMB2_CONTROL_PIN_Msk (0x80UL) /*!< SMB2 CONTROL: PIN (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------------- SMB2_OWN ---------------------------------- */\r
+#define SMB2_OWN_ADDRESS_1_Pos (0UL) /*!< SMB2 OWN: ADDRESS_1 (Bit 0) */\r
+#define SMB2_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB2 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */\r
+#define SMB2_OWN_ADDRESS_2_Pos (8UL) /*!< SMB2 OWN: ADDRESS_2 (Bit 8) */\r
+#define SMB2_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB2 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */\r
+\r
+/* ----------------------------- SMB2_MASTER_COMMAND ---------------------------- */\r
+#define SMB2_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB2 MASTER_COMMAND: MRUN (Bit 0) */\r
+#define SMB2_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB2 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */\r
+#define SMB2_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB2 MASTER_COMMAND: MPROCEED (Bit 1) */\r
+#define SMB2_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB2 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */\r
+#define SMB2_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB2 MASTER_COMMAND: START0 (Bit 8) */\r
+#define SMB2_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB2 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */\r
+#define SMB2_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB2 MASTER_COMMAND: STARTN (Bit 9) */\r
+#define SMB2_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB2 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */\r
+#define SMB2_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB2 MASTER_COMMAND: STOP (Bit 10) */\r
+#define SMB2_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB2 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */\r
+#define SMB2_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB2 MASTER_COMMAND: PEC_TERM (Bit 11) */\r
+#define SMB2_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB2 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */\r
+#define SMB2_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB2 MASTER_COMMAND: READM (Bit 12) */\r
+#define SMB2_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB2 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */\r
+#define SMB2_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB2 MASTER_COMMAND: READ_PEC (Bit 13) */\r
+#define SMB2_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB2 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */\r
+#define SMB2_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB2 MASTER_COMMAND: WRITECOUNT (Bit 16) */\r
+#define SMB2_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB2 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */\r
+#define SMB2_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB2 MASTER_COMMAND: READCOUNT (Bit 24) */\r
+#define SMB2_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB2 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */\r
+\r
+/* ----------------------------- SMB2_SLAVE_COMMAND ----------------------------- */\r
+#define SMB2_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB2 SLAVE_COMMAND: SRUN (Bit 0) */\r
+#define SMB2_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB2 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */\r
+#define SMB2_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB2 SLAVE_COMMAND: SPROCEED (Bit 1) */\r
+#define SMB2_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB2 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */\r
+#define SMB2_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */\r
+#define SMB2_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */\r
+#define SMB2_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */\r
+#define SMB2_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */\r
+#define SMB2_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */\r
+#define SMB2_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */\r
+\r
+/* ------------------------------- SMB2_COMPLETION ------------------------------ */\r
+#define SMB2_COMPLETION_DTEN_Pos (2UL) /*!< SMB2 COMPLETION: DTEN (Bit 2) */\r
+#define SMB2_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB2 COMPLETION: DTEN (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_MCEN_Pos (3UL) /*!< SMB2 COMPLETION: MCEN (Bit 3) */\r
+#define SMB2_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB2 COMPLETION: MCEN (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_SCEN_Pos (4UL) /*!< SMB2 COMPLETION: SCEN (Bit 4) */\r
+#define SMB2_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB2 COMPLETION: SCEN (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_BIDEN_Pos (5UL) /*!< SMB2 COMPLETION: BIDEN (Bit 5) */\r
+#define SMB2_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB2 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_TIMERR_Pos (6UL) /*!< SMB2 COMPLETION: TIMERR (Bit 6) */\r
+#define SMB2_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB2 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_DTO_Pos (8UL) /*!< SMB2 COMPLETION: DTO (Bit 8) */\r
+#define SMB2_COMPLETION_DTO_Msk (0x100UL) /*!< SMB2 COMPLETION: DTO (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_MCTO_Pos (9UL) /*!< SMB2 COMPLETION: MCTO (Bit 9) */\r
+#define SMB2_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB2 COMPLETION: MCTO (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_SCTO_Pos (10UL) /*!< SMB2 COMPLETION: SCTO (Bit 10) */\r
+#define SMB2_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB2 COMPLETION: SCTO (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_CHDL_Pos (11UL) /*!< SMB2 COMPLETION: CHDL (Bit 11) */\r
+#define SMB2_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB2 COMPLETION: CHDL (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_CHDH_Pos (12UL) /*!< SMB2 COMPLETION: CHDH (Bit 12) */\r
+#define SMB2_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB2 COMPLETION: CHDH (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_BER_Pos (13UL) /*!< SMB2 COMPLETION: BER (Bit 13) */\r
+#define SMB2_COMPLETION_BER_Msk (0x2000UL) /*!< SMB2 COMPLETION: BER (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_LAB_Pos (14UL) /*!< SMB2 COMPLETION: LAB (Bit 14) */\r
+#define SMB2_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB2 COMPLETION: LAB (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_SNAKR_Pos (16UL) /*!< SMB2 COMPLETION: SNAKR (Bit 16) */\r
+#define SMB2_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB2 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_STR_Pos (17UL) /*!< SMB2 COMPLETION: STR (Bit 17) */\r
+#define SMB2_COMPLETION_STR_Msk (0x20000UL) /*!< SMB2 COMPLETION: STR (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_SPROT_Pos (19UL) /*!< SMB2 COMPLETION: SPROT (Bit 19) */\r
+#define SMB2_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB2 COMPLETION: SPROT (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB2 COMPLETION: REPEAT_READ (Bit 20) */\r
+#define SMB2_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB2 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB2 COMPLETION: REPEAT_WRITE (Bit 21) */\r
+#define SMB2_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB2 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_MNAKX_Pos (24UL) /*!< SMB2 COMPLETION: MNAKX (Bit 24) */\r
+#define SMB2_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB2 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_MTR_Pos (25UL) /*!< SMB2 COMPLETION: MTR (Bit 25) */\r
+#define SMB2_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB2 COMPLETION: MTR (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_IDLE_Pos (29UL) /*!< SMB2 COMPLETION: IDLE (Bit 29) */\r
+#define SMB2_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB2 COMPLETION: IDLE (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_MDONE_Pos (30UL) /*!< SMB2 COMPLETION: MDONE (Bit 30) */\r
+#define SMB2_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB2 COMPLETION: MDONE (Bitfield-Mask: 0x01) */\r
+#define SMB2_COMPLETION_SDONE_Pos (31UL) /*!< SMB2 COMPLETION: SDONE (Bit 31) */\r
+#define SMB2_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB2 COMPLETION: SDONE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ SMB2_IDLE_SCALING ----------------------------- */\r
+#define SMB2_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB2 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */\r
+#define SMB2_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB2 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */\r
+#define SMB2_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB2 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */\r
+#define SMB2_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB2 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */\r
+\r
+/* ----------------------------- SMB2_CONFIGURATION ----------------------------- */\r
+#define SMB2_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB2 CONFIGURATION: PORT_SEL (Bit 0) */\r
+#define SMB2_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB2 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */\r
+#define SMB2_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB2 CONFIGURATION: TCEN (Bit 4) */\r
+#define SMB2_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB2 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB2 CONFIGURATION: SLOW_CLOCK (Bit 5) */\r
+#define SMB2_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB2 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB2 CONFIGURATION: PECEN (Bit 7) */\r
+#define SMB2_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB2 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB2 CONFIGURATION: DFEN (Bit 8) */\r
+#define SMB2_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB2 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_RESET_Pos (9UL) /*!< SMB2 CONFIGURATION: RESET (Bit 9) */\r
+#define SMB2_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB2 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB2 CONFIGURATION: ENAB (Bit 10) */\r
+#define SMB2_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB2 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_DSA_Pos (11UL) /*!< SMB2 CONFIGURATION: DSA (Bit 11) */\r
+#define SMB2_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB2 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB2 CONFIGURATION: FAIR (Bit 12) */\r
+#define SMB2_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB2 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB2 CONFIGURATION: GC_DIS (Bit 14) */\r
+#define SMB2_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB2 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB2 CONFIGURATION: FLUSH_SXBUF (Bit 16) */\r
+#define SMB2_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB2 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB2 CONFIGURATION: FLUSH_SRBUF (Bit 17) */\r
+#define SMB2_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB2 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB2 CONFIGURATION: FLUSH_MXBUF (Bit 18) */\r
+#define SMB2_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB2 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB2 CONFIGURATION: FLUSH_MRBUF (Bit 19) */\r
+#define SMB2_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB2 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB2 CONFIGURATION: EN_AAS (Bit 28) */\r
+#define SMB2_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB2 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB2 CONFIGURATION: ENIDI (Bit 29) */\r
+#define SMB2_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB2 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB2 CONFIGURATION: ENMI (Bit 30) */\r
+#define SMB2_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB2 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */\r
+#define SMB2_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB2 CONFIGURATION: ENSI (Bit 31) */\r
+#define SMB2_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB2 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- SMB2_BUS_CLOCK ------------------------------- */\r
+#define SMB2_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB2 BUS_CLOCK: LOW_PERIOD (Bit 0) */\r
+#define SMB2_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB2 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */\r
+#define SMB2_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB2 BUS_CLOCK: HIGH_PERIOD (Bit 8) */\r
+#define SMB2_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB2 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */\r
+\r
+/* ---------------------------- SMB2_BIT_BANG_CONTROL --------------------------- */\r
+#define SMB2_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB2 BIT_BANG_CONTROL: BBEN (Bit 0) */\r
+#define SMB2_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB2 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */\r
+#define SMB2_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB2 BIT_BANG_CONTROL: CLDIR (Bit 1) */\r
+#define SMB2_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB2 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */\r
+#define SMB2_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB2 BIT_BANG_CONTROL: DADIR (Bit 2) */\r
+#define SMB2_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB2 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */\r
+#define SMB2_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLK (Bit 3) */\r
+#define SMB2_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */\r
+#define SMB2_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB2 BIT_BANG_CONTROL: BBDAT (Bit 4) */\r
+#define SMB2_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB2 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */\r
+#define SMB2_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLKI (Bit 5) */\r
+#define SMB2_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */\r
+#define SMB2_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB2 BIT_BANG_CONTROL: BBDATI (Bit 6) */\r
+#define SMB2_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB2 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ SMB2_DATA_TIMING ------------------------------ */\r
+#define SMB2_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB2 DATA_TIMING: DATA_HOLD (Bit 0) */\r
+#define SMB2_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB2 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */\r
+#define SMB2_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB2 DATA_TIMING: RESTART_SETUP (Bit 8) */\r
+#define SMB2_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB2 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */\r
+#define SMB2_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB2 DATA_TIMING: STOP_SETUP (Bit 16) */\r
+#define SMB2_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB2 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */\r
+#define SMB2_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB2 DATA_TIMING: START_HOLD (Bit 24) */\r
+#define SMB2_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB2 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */\r
+\r
+/* ---------------------------- SMB2_TIME_OUT_SCALING --------------------------- */\r
+#define SMB2_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB2 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */\r
+#define SMB2_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB2 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */\r
+#define SMB2_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB2 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */\r
+#define SMB2_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB2 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */\r
+#define SMB2_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB2 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */\r
+#define SMB2_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB2 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */\r
+#define SMB2_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB2 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */\r
+#define SMB2_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB2 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SMB3' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- SMB3_STATUS -------------------------------- */\r
+#define SMB3_STATUS_nBB_Pos (0UL) /*!< SMB3 STATUS: nBB (Bit 0) */\r
+#define SMB3_STATUS_nBB_Msk (0x1UL) /*!< SMB3 STATUS: nBB (Bitfield-Mask: 0x01) */\r
+#define SMB3_STATUS_LAB_Pos (1UL) /*!< SMB3 STATUS: LAB (Bit 1) */\r
+#define SMB3_STATUS_LAB_Msk (0x2UL) /*!< SMB3 STATUS: LAB (Bitfield-Mask: 0x01) */\r
+#define SMB3_STATUS_AAS_Pos (2UL) /*!< SMB3 STATUS: AAS (Bit 2) */\r
+#define SMB3_STATUS_AAS_Msk (0x4UL) /*!< SMB3 STATUS: AAS (Bitfield-Mask: 0x01) */\r
+#define SMB3_STATUS_LRB_AD0_Pos (3UL) /*!< SMB3 STATUS: LRB_AD0 (Bit 3) */\r
+#define SMB3_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB3 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */\r
+#define SMB3_STATUS_BER_Pos (4UL) /*!< SMB3 STATUS: BER (Bit 4) */\r
+#define SMB3_STATUS_BER_Msk (0x10UL) /*!< SMB3 STATUS: BER (Bitfield-Mask: 0x01) */\r
+#define SMB3_STATUS_STS_Pos (5UL) /*!< SMB3 STATUS: STS (Bit 5) */\r
+#define SMB3_STATUS_STS_Msk (0x20UL) /*!< SMB3 STATUS: STS (Bitfield-Mask: 0x01) */\r
+#define SMB3_STATUS_SAD_Pos (6UL) /*!< SMB3 STATUS: SAD (Bit 6) */\r
+#define SMB3_STATUS_SAD_Msk (0x40UL) /*!< SMB3 STATUS: SAD (Bitfield-Mask: 0x01) */\r
+#define SMB3_STATUS_PIN_Pos (7UL) /*!< SMB3 STATUS: PIN (Bit 7) */\r
+#define SMB3_STATUS_PIN_Msk (0x80UL) /*!< SMB3 STATUS: PIN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- SMB3_CONTROL -------------------------------- */\r
+#define SMB3_CONTROL_ACK_Pos (0UL) /*!< SMB3 CONTROL: ACK (Bit 0) */\r
+#define SMB3_CONTROL_ACK_Msk (0x1UL) /*!< SMB3 CONTROL: ACK (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONTROL_STO_Pos (1UL) /*!< SMB3 CONTROL: STO (Bit 1) */\r
+#define SMB3_CONTROL_STO_Msk (0x2UL) /*!< SMB3 CONTROL: STO (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONTROL_STA_Pos (2UL) /*!< SMB3 CONTROL: STA (Bit 2) */\r
+#define SMB3_CONTROL_STA_Msk (0x4UL) /*!< SMB3 CONTROL: STA (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONTROL_ENI_Pos (3UL) /*!< SMB3 CONTROL: ENI (Bit 3) */\r
+#define SMB3_CONTROL_ENI_Msk (0x8UL) /*!< SMB3 CONTROL: ENI (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONTROL_ESO_Pos (6UL) /*!< SMB3 CONTROL: ESO (Bit 6) */\r
+#define SMB3_CONTROL_ESO_Msk (0x40UL) /*!< SMB3 CONTROL: ESO (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONTROL_PIN_Pos (7UL) /*!< SMB3 CONTROL: PIN (Bit 7) */\r
+#define SMB3_CONTROL_PIN_Msk (0x80UL) /*!< SMB3 CONTROL: PIN (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------------- SMB3_OWN ---------------------------------- */\r
+#define SMB3_OWN_ADDRESS_1_Pos (0UL) /*!< SMB3 OWN: ADDRESS_1 (Bit 0) */\r
+#define SMB3_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB3 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */\r
+#define SMB3_OWN_ADDRESS_2_Pos (8UL) /*!< SMB3 OWN: ADDRESS_2 (Bit 8) */\r
+#define SMB3_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB3 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */\r
+\r
+/* ----------------------------- SMB3_MASTER_COMMAND ---------------------------- */\r
+#define SMB3_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB3 MASTER_COMMAND: MRUN (Bit 0) */\r
+#define SMB3_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB3 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */\r
+#define SMB3_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB3 MASTER_COMMAND: MPROCEED (Bit 1) */\r
+#define SMB3_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB3 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */\r
+#define SMB3_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB3 MASTER_COMMAND: START0 (Bit 8) */\r
+#define SMB3_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB3 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */\r
+#define SMB3_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB3 MASTER_COMMAND: STARTN (Bit 9) */\r
+#define SMB3_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB3 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */\r
+#define SMB3_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB3 MASTER_COMMAND: STOP (Bit 10) */\r
+#define SMB3_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB3 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */\r
+#define SMB3_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB3 MASTER_COMMAND: PEC_TERM (Bit 11) */\r
+#define SMB3_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB3 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */\r
+#define SMB3_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB3 MASTER_COMMAND: READM (Bit 12) */\r
+#define SMB3_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB3 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */\r
+#define SMB3_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB3 MASTER_COMMAND: READ_PEC (Bit 13) */\r
+#define SMB3_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB3 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */\r
+#define SMB3_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB3 MASTER_COMMAND: WRITECOUNT (Bit 16) */\r
+#define SMB3_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB3 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */\r
+#define SMB3_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB3 MASTER_COMMAND: READCOUNT (Bit 24) */\r
+#define SMB3_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB3 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */\r
+\r
+/* ----------------------------- SMB3_SLAVE_COMMAND ----------------------------- */\r
+#define SMB3_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB3 SLAVE_COMMAND: SRUN (Bit 0) */\r
+#define SMB3_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB3 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */\r
+#define SMB3_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB3 SLAVE_COMMAND: SPROCEED (Bit 1) */\r
+#define SMB3_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB3 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */\r
+#define SMB3_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */\r
+#define SMB3_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */\r
+#define SMB3_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */\r
+#define SMB3_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */\r
+#define SMB3_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */\r
+#define SMB3_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */\r
+\r
+/* ------------------------------- SMB3_COMPLETION ------------------------------ */\r
+#define SMB3_COMPLETION_DTEN_Pos (2UL) /*!< SMB3 COMPLETION: DTEN (Bit 2) */\r
+#define SMB3_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB3 COMPLETION: DTEN (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_MCEN_Pos (3UL) /*!< SMB3 COMPLETION: MCEN (Bit 3) */\r
+#define SMB3_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB3 COMPLETION: MCEN (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_SCEN_Pos (4UL) /*!< SMB3 COMPLETION: SCEN (Bit 4) */\r
+#define SMB3_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB3 COMPLETION: SCEN (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_BIDEN_Pos (5UL) /*!< SMB3 COMPLETION: BIDEN (Bit 5) */\r
+#define SMB3_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB3 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_TIMERR_Pos (6UL) /*!< SMB3 COMPLETION: TIMERR (Bit 6) */\r
+#define SMB3_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB3 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_DTO_Pos (8UL) /*!< SMB3 COMPLETION: DTO (Bit 8) */\r
+#define SMB3_COMPLETION_DTO_Msk (0x100UL) /*!< SMB3 COMPLETION: DTO (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_MCTO_Pos (9UL) /*!< SMB3 COMPLETION: MCTO (Bit 9) */\r
+#define SMB3_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB3 COMPLETION: MCTO (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_SCTO_Pos (10UL) /*!< SMB3 COMPLETION: SCTO (Bit 10) */\r
+#define SMB3_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB3 COMPLETION: SCTO (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_CHDL_Pos (11UL) /*!< SMB3 COMPLETION: CHDL (Bit 11) */\r
+#define SMB3_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB3 COMPLETION: CHDL (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_CHDH_Pos (12UL) /*!< SMB3 COMPLETION: CHDH (Bit 12) */\r
+#define SMB3_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB3 COMPLETION: CHDH (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_BER_Pos (13UL) /*!< SMB3 COMPLETION: BER (Bit 13) */\r
+#define SMB3_COMPLETION_BER_Msk (0x2000UL) /*!< SMB3 COMPLETION: BER (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_LAB_Pos (14UL) /*!< SMB3 COMPLETION: LAB (Bit 14) */\r
+#define SMB3_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB3 COMPLETION: LAB (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_SNAKR_Pos (16UL) /*!< SMB3 COMPLETION: SNAKR (Bit 16) */\r
+#define SMB3_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB3 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_STR_Pos (17UL) /*!< SMB3 COMPLETION: STR (Bit 17) */\r
+#define SMB3_COMPLETION_STR_Msk (0x20000UL) /*!< SMB3 COMPLETION: STR (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_SPROT_Pos (19UL) /*!< SMB3 COMPLETION: SPROT (Bit 19) */\r
+#define SMB3_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB3 COMPLETION: SPROT (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB3 COMPLETION: REPEAT_READ (Bit 20) */\r
+#define SMB3_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB3 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB3 COMPLETION: REPEAT_WRITE (Bit 21) */\r
+#define SMB3_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB3 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_MNAKX_Pos (24UL) /*!< SMB3 COMPLETION: MNAKX (Bit 24) */\r
+#define SMB3_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB3 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_MTR_Pos (25UL) /*!< SMB3 COMPLETION: MTR (Bit 25) */\r
+#define SMB3_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB3 COMPLETION: MTR (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_IDLE_Pos (29UL) /*!< SMB3 COMPLETION: IDLE (Bit 29) */\r
+#define SMB3_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB3 COMPLETION: IDLE (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_MDONE_Pos (30UL) /*!< SMB3 COMPLETION: MDONE (Bit 30) */\r
+#define SMB3_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB3 COMPLETION: MDONE (Bitfield-Mask: 0x01) */\r
+#define SMB3_COMPLETION_SDONE_Pos (31UL) /*!< SMB3 COMPLETION: SDONE (Bit 31) */\r
+#define SMB3_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB3 COMPLETION: SDONE (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ SMB3_IDLE_SCALING ----------------------------- */\r
+#define SMB3_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB3 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */\r
+#define SMB3_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB3 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */\r
+#define SMB3_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB3 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */\r
+#define SMB3_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB3 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */\r
+\r
+/* ----------------------------- SMB3_CONFIGURATION ----------------------------- */\r
+#define SMB3_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB3 CONFIGURATION: PORT_SEL (Bit 0) */\r
+#define SMB3_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB3 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */\r
+#define SMB3_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB3 CONFIGURATION: TCEN (Bit 4) */\r
+#define SMB3_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB3 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB3 CONFIGURATION: SLOW_CLOCK (Bit 5) */\r
+#define SMB3_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB3 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB3 CONFIGURATION: PECEN (Bit 7) */\r
+#define SMB3_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB3 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB3 CONFIGURATION: DFEN (Bit 8) */\r
+#define SMB3_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB3 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_RESET_Pos (9UL) /*!< SMB3 CONFIGURATION: RESET (Bit 9) */\r
+#define SMB3_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB3 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB3 CONFIGURATION: ENAB (Bit 10) */\r
+#define SMB3_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB3 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_DSA_Pos (11UL) /*!< SMB3 CONFIGURATION: DSA (Bit 11) */\r
+#define SMB3_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB3 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB3 CONFIGURATION: FAIR (Bit 12) */\r
+#define SMB3_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB3 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB3 CONFIGURATION: GC_DIS (Bit 14) */\r
+#define SMB3_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB3 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB3 CONFIGURATION: FLUSH_SXBUF (Bit 16) */\r
+#define SMB3_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB3 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB3 CONFIGURATION: FLUSH_SRBUF (Bit 17) */\r
+#define SMB3_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB3 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB3 CONFIGURATION: FLUSH_MXBUF (Bit 18) */\r
+#define SMB3_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB3 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB3 CONFIGURATION: FLUSH_MRBUF (Bit 19) */\r
+#define SMB3_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB3 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB3 CONFIGURATION: EN_AAS (Bit 28) */\r
+#define SMB3_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB3 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB3 CONFIGURATION: ENIDI (Bit 29) */\r
+#define SMB3_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB3 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB3 CONFIGURATION: ENMI (Bit 30) */\r
+#define SMB3_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB3 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */\r
+#define SMB3_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB3 CONFIGURATION: ENSI (Bit 31) */\r
+#define SMB3_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB3 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------- SMB3_BUS_CLOCK ------------------------------- */\r
+#define SMB3_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB3 BUS_CLOCK: LOW_PERIOD (Bit 0) */\r
+#define SMB3_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB3 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */\r
+#define SMB3_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB3 BUS_CLOCK: HIGH_PERIOD (Bit 8) */\r
+#define SMB3_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB3 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */\r
+\r
+/* ---------------------------- SMB3_BIT_BANG_CONTROL --------------------------- */\r
+#define SMB3_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB3 BIT_BANG_CONTROL: BBEN (Bit 0) */\r
+#define SMB3_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB3 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */\r
+#define SMB3_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB3 BIT_BANG_CONTROL: CLDIR (Bit 1) */\r
+#define SMB3_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB3 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */\r
+#define SMB3_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB3 BIT_BANG_CONTROL: DADIR (Bit 2) */\r
+#define SMB3_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB3 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */\r
+#define SMB3_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLK (Bit 3) */\r
+#define SMB3_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */\r
+#define SMB3_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB3 BIT_BANG_CONTROL: BBDAT (Bit 4) */\r
+#define SMB3_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB3 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */\r
+#define SMB3_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLKI (Bit 5) */\r
+#define SMB3_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */\r
+#define SMB3_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB3 BIT_BANG_CONTROL: BBDATI (Bit 6) */\r
+#define SMB3_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB3 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */\r
+\r
+/* ------------------------------ SMB3_DATA_TIMING ------------------------------ */\r
+#define SMB3_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB3 DATA_TIMING: DATA_HOLD (Bit 0) */\r
+#define SMB3_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB3 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */\r
+#define SMB3_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB3 DATA_TIMING: RESTART_SETUP (Bit 8) */\r
+#define SMB3_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB3 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */\r
+#define SMB3_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB3 DATA_TIMING: STOP_SETUP (Bit 16) */\r
+#define SMB3_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB3 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */\r
+#define SMB3_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB3 DATA_TIMING: START_HOLD (Bit 24) */\r
+#define SMB3_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB3 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */\r
+\r
+/* ---------------------------- SMB3_TIME_OUT_SCALING --------------------------- */\r
+#define SMB3_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB3 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */\r
+#define SMB3_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB3 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */\r
+#define SMB3_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB3 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */\r
+#define SMB3_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB3 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */\r
+#define SMB3_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB3 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */\r
+#define SMB3_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB3 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */\r
+#define SMB3_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB3 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */\r
+#define SMB3_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB3 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PECI' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PECI_CONTROL -------------------------------- */\r
+#define PECI_CONTROL_PD_Pos (0UL) /*!< PECI CONTROL: PD (Bit 0) */\r
+#define PECI_CONTROL_PD_Msk (0x1UL) /*!< PECI CONTROL: PD (Bitfield-Mask: 0x01) */\r
+#define PECI_CONTROL_RST_Pos (3UL) /*!< PECI CONTROL: RST (Bit 3) */\r
+#define PECI_CONTROL_RST_Msk (0x8UL) /*!< PECI CONTROL: RST (Bitfield-Mask: 0x01) */\r
+#define PECI_CONTROL_FRST_Pos (5UL) /*!< PECI CONTROL: FRST (Bit 5) */\r
+#define PECI_CONTROL_FRST_Msk (0x20UL) /*!< PECI CONTROL: FRST (Bitfield-Mask: 0x01) */\r
+#define PECI_CONTROL_TXEN_Pos (6UL) /*!< PECI CONTROL: TXEN (Bit 6) */\r
+#define PECI_CONTROL_TXEN_Msk (0x40UL) /*!< PECI CONTROL: TXEN (Bitfield-Mask: 0x01) */\r
+#define PECI_CONTROL_MIEN_Pos (7UL) /*!< PECI CONTROL: MIEN (Bit 7) */\r
+#define PECI_CONTROL_MIEN_Msk (0x80UL) /*!< PECI CONTROL: MIEN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PECI_STATUS1 -------------------------------- */\r
+#define PECI_STATUS1_BOF_Pos (0UL) /*!< PECI STATUS1: BOF (Bit 0) */\r
+#define PECI_STATUS1_BOF_Msk (0x1UL) /*!< PECI STATUS1: BOF (Bitfield-Mask: 0x01) */\r
+#define PECI_STATUS1_EOF_Pos (1UL) /*!< PECI STATUS1: EOF (Bit 1) */\r
+#define PECI_STATUS1_EOF_Msk (0x2UL) /*!< PECI STATUS1: EOF (Bitfield-Mask: 0x01) */\r
+#define PECI_STATUS1_ERR_Pos (2UL) /*!< PECI STATUS1: ERR (Bit 2) */\r
+#define PECI_STATUS1_ERR_Msk (0x4UL) /*!< PECI STATUS1: ERR (Bitfield-Mask: 0x01) */\r
+#define PECI_STATUS1_RDY_Pos (3UL) /*!< PECI STATUS1: RDY (Bit 3) */\r
+#define PECI_STATUS1_RDY_Msk (0x8UL) /*!< PECI STATUS1: RDY (Bitfield-Mask: 0x01) */\r
+#define PECI_STATUS1_RDYLO_Pos (4UL) /*!< PECI STATUS1: RDYLO (Bit 4) */\r
+#define PECI_STATUS1_RDYLO_Msk (0x10UL) /*!< PECI STATUS1: RDYLO (Bitfield-Mask: 0x01) */\r
+#define PECI_STATUS1_RDYHI_Pos (5UL) /*!< PECI STATUS1: RDYHI (Bit 5) */\r
+#define PECI_STATUS1_RDYHI_Msk (0x20UL) /*!< PECI STATUS1: RDYHI (Bitfield-Mask: 0x01) */\r
+#define PECI_STATUS1_MINT_Pos (7UL) /*!< PECI STATUS1: MINT (Bit 7) */\r
+#define PECI_STATUS1_MINT_Msk (0x80UL) /*!< PECI STATUS1: MINT (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PECI_STATUS2 -------------------------------- */\r
+#define PECI_STATUS2_WFF_Pos (0UL) /*!< PECI STATUS2: WFF (Bit 0) */\r
+#define PECI_STATUS2_WFF_Msk (0x1UL) /*!< PECI STATUS2: WFF (Bitfield-Mask: 0x01) */\r
+#define PECI_STATUS2_WFE_Pos (1UL) /*!< PECI STATUS2: WFE (Bit 1) */\r
+#define PECI_STATUS2_WFE_Msk (0x2UL) /*!< PECI STATUS2: WFE (Bitfield-Mask: 0x01) */\r
+#define PECI_STATUS2_RFF_Pos (2UL) /*!< PECI STATUS2: RFF (Bit 2) */\r
+#define PECI_STATUS2_RFF_Msk (0x4UL) /*!< PECI STATUS2: RFF (Bitfield-Mask: 0x01) */\r
+#define PECI_STATUS2_RFE_Pos (3UL) /*!< PECI STATUS2: RFE (Bit 3) */\r
+#define PECI_STATUS2_RFE_Msk (0x8UL) /*!< PECI STATUS2: RFE (Bitfield-Mask: 0x01) */\r
+#define PECI_STATUS2_IDLE_Pos (7UL) /*!< PECI STATUS2: IDLE (Bit 7) */\r
+#define PECI_STATUS2_IDLE_Msk (0x80UL) /*!< PECI STATUS2: IDLE (Bitfield-Mask: 0x01) */\r
+\r
+/* --------------------------------- PECI_ERROR --------------------------------- */\r
+#define PECI_ERROR_FERR_Pos (0UL) /*!< PECI ERROR: FERR (Bit 0) */\r
+#define PECI_ERROR_FERR_Msk (0x1UL) /*!< PECI ERROR: FERR (Bitfield-Mask: 0x01) */\r
+#define PECI_ERROR_BERR_Pos (1UL) /*!< PECI ERROR: BERR (Bit 1) */\r
+#define PECI_ERROR_BERR_Msk (0x2UL) /*!< PECI ERROR: BERR (Bitfield-Mask: 0x01) */\r
+#define PECI_ERROR_REQERR_Pos (3UL) /*!< PECI ERROR: REQERR (Bit 3) */\r
+#define PECI_ERROR_REQERR_Msk (0x8UL) /*!< PECI ERROR: REQERR (Bitfield-Mask: 0x01) */\r
+#define PECI_ERROR_WROV_Pos (4UL) /*!< PECI ERROR: WROV (Bit 4) */\r
+#define PECI_ERROR_WROV_Msk (0x10UL) /*!< PECI ERROR: WROV (Bitfield-Mask: 0x01) */\r
+#define PECI_ERROR_WRUN_Pos (5UL) /*!< PECI ERROR: WRUN (Bit 5) */\r
+#define PECI_ERROR_WRUN_Msk (0x20UL) /*!< PECI ERROR: WRUN (Bitfield-Mask: 0x01) */\r
+#define PECI_ERROR_RDOV_Pos (6UL) /*!< PECI ERROR: RDOV (Bit 6) */\r
+#define PECI_ERROR_RDOV_Msk (0x40UL) /*!< PECI ERROR: RDOV (Bitfield-Mask: 0x01) */\r
+#define PECI_ERROR_CLKERR_Pos (7UL) /*!< PECI ERROR: CLKERR (Bit 7) */\r
+#define PECI_ERROR_CLKERR_Msk (0x80UL) /*!< PECI ERROR: CLKERR (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PECI_INT_EN1 -------------------------------- */\r
+#define PECI_INT_EN1_BIEN_Pos (0UL) /*!< PECI INT_EN1: BIEN (Bit 0) */\r
+#define PECI_INT_EN1_BIEN_Msk (0x1UL) /*!< PECI INT_EN1: BIEN (Bitfield-Mask: 0x01) */\r
+#define PECI_INT_EN1_EIEN_Pos (1UL) /*!< PECI INT_EN1: EIEN (Bit 1) */\r
+#define PECI_INT_EN1_EIEN_Msk (0x2UL) /*!< PECI INT_EN1: EIEN (Bitfield-Mask: 0x01) */\r
+#define PECI_INT_EN1_EREN_Pos (2UL) /*!< PECI INT_EN1: EREN (Bit 2) */\r
+#define PECI_INT_EN1_EREN_Msk (0x4UL) /*!< PECI INT_EN1: EREN (Bitfield-Mask: 0x01) */\r
+#define PECI_INT_EN1_RLEN_Pos (4UL) /*!< PECI INT_EN1: RLEN (Bit 4) */\r
+#define PECI_INT_EN1_RLEN_Msk (0x10UL) /*!< PECI INT_EN1: RLEN (Bitfield-Mask: 0x01) */\r
+#define PECI_INT_EN1_RHEN_Pos (5UL) /*!< PECI INT_EN1: RHEN (Bit 5) */\r
+#define PECI_INT_EN1_RHEN_Msk (0x20UL) /*!< PECI INT_EN1: RHEN (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- PECI_INT_EN2 -------------------------------- */\r
+#define PECI_INT_EN2_ENWFE_Pos (1UL) /*!< PECI INT_EN2: ENWFE (Bit 1) */\r
+#define PECI_INT_EN2_ENWFE_Msk (0x2UL) /*!< PECI INT_EN2: ENWFE (Bitfield-Mask: 0x01) */\r
+#define PECI_INT_EN2_ENRFF_Pos (2UL) /*!< PECI INT_EN2: ENRFF (Bit 2) */\r
+#define PECI_INT_EN2_ENRFF_Msk (0x4UL) /*!< PECI INT_EN2: ENRFF (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TACH_0' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------- TACH_0_CONTROL ------------------------------- */\r
+#define TACH_0_CONTROL_OUT_LIMIT_ENABLE_Pos (0UL) /*!< TACH_0 CONTROL: OUT_LIMIT_ENABLE (Bit 0) */\r
+#define TACH_0_CONTROL_OUT_LIMIT_ENABLE_Msk (0x1UL) /*!< TACH_0 CONTROL: OUT_LIMIT_ENABLE (Bitfield-Mask: 0x01) */\r
+#define TACH_0_CONTROL_TACH_EN_Pos (1UL) /*!< TACH_0 CONTROL: TACH_EN (Bit 1) */\r
+#define TACH_0_CONTROL_TACH_EN_Msk (0x2UL) /*!< TACH_0 CONTROL: TACH_EN (Bitfield-Mask: 0x01) */\r
+#define TACH_0_CONTROL_FILTER_EN_Pos (8UL) /*!< TACH_0 CONTROL: FILTER_EN (Bit 8) */\r
+#define TACH_0_CONTROL_FILTER_EN_Msk (0x100UL) /*!< TACH_0 CONTROL: FILTER_EN (Bitfield-Mask: 0x01) */\r
+#define TACH_0_CONTROL_MODE_SELECT_Pos (10UL) /*!< TACH_0 CONTROL: MODE_SELECT (Bit 10) */\r
+#define TACH_0_CONTROL_MODE_SELECT_Msk (0x400UL) /*!< TACH_0 CONTROL: MODE_SELECT (Bitfield-Mask: 0x01) */\r
+#define TACH_0_CONTROL_EDGES_Pos (11UL) /*!< TACH_0 CONTROL: EDGES (Bit 11) */\r
+#define TACH_0_CONTROL_EDGES_Msk (0x1800UL) /*!< TACH_0 CONTROL: EDGES (Bitfield-Mask: 0x03) */\r
+#define TACH_0_CONTROL_READY_INT_EN_Pos (14UL) /*!< TACH_0 CONTROL: READY_INT_EN (Bit 14) */\r
+#define TACH_0_CONTROL_READY_INT_EN_Msk (0x4000UL) /*!< TACH_0 CONTROL: READY_INT_EN (Bitfield-Mask: 0x01) */\r
+#define TACH_0_CONTROL_INPUT_INT_EN_Pos (15UL) /*!< TACH_0 CONTROL: INPUT_INT_EN (Bit 15) */\r
+#define TACH_0_CONTROL_INPUT_INT_EN_Msk (0x8000UL) /*!< TACH_0 CONTROL: INPUT_INT_EN (Bitfield-Mask: 0x01) */\r
+#define TACH_0_CONTROL_COUNTER_Pos (16UL) /*!< TACH_0 CONTROL: COUNTER (Bit 16) */\r
+#define TACH_0_CONTROL_COUNTER_Msk (0xffff0000UL) /*!< TACH_0 CONTROL: COUNTER (Bitfield-Mask: 0xffff) */\r
+\r
+/* -------------------------------- TACH_0_STATUS ------------------------------- */\r
+#define TACH_0_STATUS_OUT_LIMIT_Pos (0UL) /*!< TACH_0 STATUS: OUT_LIMIT (Bit 0) */\r
+#define TACH_0_STATUS_OUT_LIMIT_Msk (0x1UL) /*!< TACH_0 STATUS: OUT_LIMIT (Bitfield-Mask: 0x01) */\r
+#define TACH_0_STATUS_PIN_Pos (1UL) /*!< TACH_0 STATUS: PIN (Bit 1) */\r
+#define TACH_0_STATUS_PIN_Msk (0x2UL) /*!< TACH_0 STATUS: PIN (Bitfield-Mask: 0x01) */\r
+#define TACH_0_STATUS_TOGGLE_Pos (2UL) /*!< TACH_0 STATUS: TOGGLE (Bit 2) */\r
+#define TACH_0_STATUS_TOGGLE_Msk (0x4UL) /*!< TACH_0 STATUS: TOGGLE (Bitfield-Mask: 0x01) */\r
+#define TACH_0_STATUS_COUNT_READY_Pos (3UL) /*!< TACH_0 STATUS: COUNT_READY (Bit 3) */\r
+#define TACH_0_STATUS_COUNT_READY_Msk (0x8UL) /*!< TACH_0 STATUS: COUNT_READY (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TACH_1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------- TACH_1_CONTROL ------------------------------- */\r
+#define TACH_1_CONTROL_OUT_LIMIT_ENABLE_Pos (0UL) /*!< TACH_1 CONTROL: OUT_LIMIT_ENABLE (Bit 0) */\r
+#define TACH_1_CONTROL_OUT_LIMIT_ENABLE_Msk (0x1UL) /*!< TACH_1 CONTROL: OUT_LIMIT_ENABLE (Bitfield-Mask: 0x01) */\r
+#define TACH_1_CONTROL_TACH_EN_Pos (1UL) /*!< TACH_1 CONTROL: TACH_EN (Bit 1) */\r
+#define TACH_1_CONTROL_TACH_EN_Msk (0x2UL) /*!< TACH_1 CONTROL: TACH_EN (Bitfield-Mask: 0x01) */\r
+#define TACH_1_CONTROL_FILTER_EN_Pos (8UL) /*!< TACH_1 CONTROL: FILTER_EN (Bit 8) */\r
+#define TACH_1_CONTROL_FILTER_EN_Msk (0x100UL) /*!< TACH_1 CONTROL: FILTER_EN (Bitfield-Mask: 0x01) */\r
+#define TACH_1_CONTROL_MODE_SELECT_Pos (10UL) /*!< TACH_1 CONTROL: MODE_SELECT (Bit 10) */\r
+#define TACH_1_CONTROL_MODE_SELECT_Msk (0x400UL) /*!< TACH_1 CONTROL: MODE_SELECT (Bitfield-Mask: 0x01) */\r
+#define TACH_1_CONTROL_EDGES_Pos (11UL) /*!< TACH_1 CONTROL: EDGES (Bit 11) */\r
+#define TACH_1_CONTROL_EDGES_Msk (0x1800UL) /*!< TACH_1 CONTROL: EDGES (Bitfield-Mask: 0x03) */\r
+#define TACH_1_CONTROL_READY_INT_EN_Pos (14UL) /*!< TACH_1 CONTROL: READY_INT_EN (Bit 14) */\r
+#define TACH_1_CONTROL_READY_INT_EN_Msk (0x4000UL) /*!< TACH_1 CONTROL: READY_INT_EN (Bitfield-Mask: 0x01) */\r
+#define TACH_1_CONTROL_INPUT_INT_EN_Pos (15UL) /*!< TACH_1 CONTROL: INPUT_INT_EN (Bit 15) */\r
+#define TACH_1_CONTROL_INPUT_INT_EN_Msk (0x8000UL) /*!< TACH_1 CONTROL: INPUT_INT_EN (Bitfield-Mask: 0x01) */\r
+#define TACH_1_CONTROL_COUNTER_Pos (16UL) /*!< TACH_1 CONTROL: COUNTER (Bit 16) */\r
+#define TACH_1_CONTROL_COUNTER_Msk (0xffff0000UL) /*!< TACH_1 CONTROL: COUNTER (Bitfield-Mask: 0xffff) */\r
+\r
+/* -------------------------------- TACH_1_STATUS ------------------------------- */\r
+#define TACH_1_STATUS_OUT_LIMIT_Pos (0UL) /*!< TACH_1 STATUS: OUT_LIMIT (Bit 0) */\r
+#define TACH_1_STATUS_OUT_LIMIT_Msk (0x1UL) /*!< TACH_1 STATUS: OUT_LIMIT (Bitfield-Mask: 0x01) */\r
+#define TACH_1_STATUS_PIN_Pos (1UL) /*!< TACH_1 STATUS: PIN (Bit 1) */\r
+#define TACH_1_STATUS_PIN_Msk (0x2UL) /*!< TACH_1 STATUS: PIN (Bitfield-Mask: 0x01) */\r
+#define TACH_1_STATUS_TOGGLE_Pos (2UL) /*!< TACH_1 STATUS: TOGGLE (Bit 2) */\r
+#define TACH_1_STATUS_TOGGLE_Msk (0x4UL) /*!< TACH_1 STATUS: TOGGLE (Bitfield-Mask: 0x01) */\r
+#define TACH_1_STATUS_COUNT_READY_Pos (3UL) /*!< TACH_1 STATUS: COUNT_READY (Bit 3) */\r
+#define TACH_1_STATUS_COUNT_READY_Msk (0x8UL) /*!< TACH_1 STATUS: COUNT_READY (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PWM_0' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PWM_0_CONFIG -------------------------------- */\r
+#define PWM_0_CONFIG_EN_Pos (0UL) /*!< PWM_0 CONFIG: EN (Bit 0) */\r
+#define PWM_0_CONFIG_EN_Msk (0x1UL) /*!< PWM_0 CONFIG: EN (Bitfield-Mask: 0x01) */\r
+#define PWM_0_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_0 CONFIG: CLK_SELECT (Bit 1) */\r
+#define PWM_0_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_0 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */\r
+#define PWM_0_CONFIG_INVERT_Pos (2UL) /*!< PWM_0 CONFIG: INVERT (Bit 2) */\r
+#define PWM_0_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_0 CONFIG: INVERT (Bitfield-Mask: 0x01) */\r
+#define PWM_0_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_0 CONFIG: CLK_PRE_DIVIDER (Bit 3) */\r
+#define PWM_0_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_0 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PWM_1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PWM_1_CONFIG -------------------------------- */\r
+#define PWM_1_CONFIG_EN_Pos (0UL) /*!< PWM_1 CONFIG: EN (Bit 0) */\r
+#define PWM_1_CONFIG_EN_Msk (0x1UL) /*!< PWM_1 CONFIG: EN (Bitfield-Mask: 0x01) */\r
+#define PWM_1_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_1 CONFIG: CLK_SELECT (Bit 1) */\r
+#define PWM_1_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_1 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */\r
+#define PWM_1_CONFIG_INVERT_Pos (2UL) /*!< PWM_1 CONFIG: INVERT (Bit 2) */\r
+#define PWM_1_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_1 CONFIG: INVERT (Bitfield-Mask: 0x01) */\r
+#define PWM_1_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_1 CONFIG: CLK_PRE_DIVIDER (Bit 3) */\r
+#define PWM_1_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_1 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PWM_2' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PWM_2_CONFIG -------------------------------- */\r
+#define PWM_2_CONFIG_EN_Pos (0UL) /*!< PWM_2 CONFIG: EN (Bit 0) */\r
+#define PWM_2_CONFIG_EN_Msk (0x1UL) /*!< PWM_2 CONFIG: EN (Bitfield-Mask: 0x01) */\r
+#define PWM_2_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_2 CONFIG: CLK_SELECT (Bit 1) */\r
+#define PWM_2_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_2 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */\r
+#define PWM_2_CONFIG_INVERT_Pos (2UL) /*!< PWM_2 CONFIG: INVERT (Bit 2) */\r
+#define PWM_2_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_2 CONFIG: INVERT (Bitfield-Mask: 0x01) */\r
+#define PWM_2_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_2 CONFIG: CLK_PRE_DIVIDER (Bit 3) */\r
+#define PWM_2_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_2 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PWM_3' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PWM_3_CONFIG -------------------------------- */\r
+#define PWM_3_CONFIG_EN_Pos (0UL) /*!< PWM_3 CONFIG: EN (Bit 0) */\r
+#define PWM_3_CONFIG_EN_Msk (0x1UL) /*!< PWM_3 CONFIG: EN (Bitfield-Mask: 0x01) */\r
+#define PWM_3_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_3 CONFIG: CLK_SELECT (Bit 1) */\r
+#define PWM_3_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_3 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */\r
+#define PWM_3_CONFIG_INVERT_Pos (2UL) /*!< PWM_3 CONFIG: INVERT (Bit 2) */\r
+#define PWM_3_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_3 CONFIG: INVERT (Bitfield-Mask: 0x01) */\r
+#define PWM_3_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_3 CONFIG: CLK_PRE_DIVIDER (Bit 3) */\r
+#define PWM_3_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_3 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'RPM_FAN' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------- RPM_FAN_CONFIGURATION --------------------------- */\r
+#define RPM_FAN_CONFIGURATION_UPDATE_Pos (0UL) /*!< RPM_FAN CONFIGURATION: UPDATE (Bit 0) */\r
+#define RPM_FAN_CONFIGURATION_UPDATE_Msk (0x7UL) /*!< RPM_FAN CONFIGURATION: UPDATE (Bitfield-Mask: 0x07) */\r
+#define RPM_FAN_CONFIGURATION_EDGES_Pos (3UL) /*!< RPM_FAN CONFIGURATION: EDGES (Bit 3) */\r
+#define RPM_FAN_CONFIGURATION_EDGES_Msk (0x18UL) /*!< RPM_FAN CONFIGURATION: EDGES (Bitfield-Mask: 0x03) */\r
+#define RPM_FAN_CONFIGURATION_RANGE_Pos (5UL) /*!< RPM_FAN CONFIGURATION: RANGE (Bit 5) */\r
+#define RPM_FAN_CONFIGURATION_RANGE_Msk (0x60UL) /*!< RPM_FAN CONFIGURATION: RANGE (Bitfield-Mask: 0x03) */\r
+#define RPM_FAN_CONFIGURATION_EN_ALGO_Pos (7UL) /*!< RPM_FAN CONFIGURATION: EN_ALGO (Bit 7) */\r
+#define RPM_FAN_CONFIGURATION_EN_ALGO_Msk (0x80UL) /*!< RPM_FAN CONFIGURATION: EN_ALGO (Bitfield-Mask: 0x01) */\r
+#define RPM_FAN_CONFIGURATION_POLARITY_Pos (8UL) /*!< RPM_FAN CONFIGURATION: POLARITY (Bit 8) */\r
+#define RPM_FAN_CONFIGURATION_POLARITY_Msk (0x100UL) /*!< RPM_FAN CONFIGURATION: POLARITY (Bitfield-Mask: 0x01) */\r
+#define RPM_FAN_CONFIGURATION_ERR_RNG_Pos (9UL) /*!< RPM_FAN CONFIGURATION: ERR_RNG (Bit 9) */\r
+#define RPM_FAN_CONFIGURATION_ERR_RNG_Msk (0x600UL) /*!< RPM_FAN CONFIGURATION: ERR_RNG (Bitfield-Mask: 0x03) */\r
+#define RPM_FAN_CONFIGURATION_DER_OPT_Pos (11UL) /*!< RPM_FAN CONFIGURATION: DER_OPT (Bit 11) */\r
+#define RPM_FAN_CONFIGURATION_DER_OPT_Msk (0x1800UL) /*!< RPM_FAN CONFIGURATION: DER_OPT (Bitfield-Mask: 0x03) */\r
+#define RPM_FAN_CONFIGURATION_DIS_GLITCH_Pos (13UL) /*!< RPM_FAN CONFIGURATION: DIS_GLITCH (Bit 13) */\r
+#define RPM_FAN_CONFIGURATION_DIS_GLITCH_Msk (0x2000UL) /*!< RPM_FAN CONFIGURATION: DIS_GLITCH (Bitfield-Mask: 0x01) */\r
+#define RPM_FAN_CONFIGURATION_EN_RRC_Pos (14UL) /*!< RPM_FAN CONFIGURATION: EN_RRC (Bit 14) */\r
+#define RPM_FAN_CONFIGURATION_EN_RRC_Msk (0x4000UL) /*!< RPM_FAN CONFIGURATION: EN_RRC (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- RPM_FAN_GAIN -------------------------------- */\r
+#define RPM_FAN_GAIN_GAINP_Pos (0UL) /*!< RPM_FAN GAIN: GAINP (Bit 0) */\r
+#define RPM_FAN_GAIN_GAINP_Msk (0x3UL) /*!< RPM_FAN GAIN: GAINP (Bitfield-Mask: 0x03) */\r
+#define RPM_FAN_GAIN_GAINI_Pos (2UL) /*!< RPM_FAN GAIN: GAINI (Bit 2) */\r
+#define RPM_FAN_GAIN_GAINI_Msk (0xcUL) /*!< RPM_FAN GAIN: GAINI (Bitfield-Mask: 0x03) */\r
+#define RPM_FAN_GAIN_GAIND_Pos (4UL) /*!< RPM_FAN GAIN: GAIND (Bit 4) */\r
+#define RPM_FAN_GAIN_GAIND_Msk (0x30UL) /*!< RPM_FAN GAIN: GAIND (Bitfield-Mask: 0x03) */\r
+\r
+/* ------------------------ RPM_FAN_SPIN_UP_CONFIGURATION ----------------------- */\r
+#define RPM_FAN_SPIN_UP_CONFIGURATION_SPINUP_TIME_Pos (0UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPINUP_TIME (Bit 0) */\r
+#define RPM_FAN_SPIN_UP_CONFIGURATION_SPINUP_TIME_Msk (0x3UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPINUP_TIME (Bitfield-Mask: 0x03) */\r
+#define RPM_FAN_SPIN_UP_CONFIGURATION_SPIN_LVL_Pos (2UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPIN_LVL (Bit 2) */\r
+#define RPM_FAN_SPIN_UP_CONFIGURATION_SPIN_LVL_Msk (0x1cUL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPIN_LVL (Bitfield-Mask: 0x07) */\r
+#define RPM_FAN_SPIN_UP_CONFIGURATION_NOKICK_Pos (5UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: NOKICK (Bit 5) */\r
+#define RPM_FAN_SPIN_UP_CONFIGURATION_NOKICK_Msk (0x20UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: NOKICK (Bitfield-Mask: 0x01) */\r
+#define RPM_FAN_SPIN_UP_CONFIGURATION_DRIVE_FAIL_CNT_Pos (6UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: DRIVE_FAIL_CNT (Bit 6) */\r
+#define RPM_FAN_SPIN_UP_CONFIGURATION_DRIVE_FAIL_CNT_Msk (0xc0UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: DRIVE_FAIL_CNT (Bitfield-Mask: 0x03) */\r
+\r
+/* ------------------------------- RPM_FAN_STATUS ------------------------------- */\r
+#define RPM_FAN_STATUS_FAN_STALL_Pos (0UL) /*!< RPM_FAN STATUS: FAN_STALL (Bit 0) */\r
+#define RPM_FAN_STATUS_FAN_STALL_Msk (0x1UL) /*!< RPM_FAN STATUS: FAN_STALL (Bitfield-Mask: 0x01) */\r
+#define RPM_FAN_STATUS_FAN_SPIN_Pos (1UL) /*!< RPM_FAN STATUS: FAN_SPIN (Bit 1) */\r
+#define RPM_FAN_STATUS_FAN_SPIN_Msk (0x2UL) /*!< RPM_FAN STATUS: FAN_SPIN (Bitfield-Mask: 0x01) */\r
+#define RPM_FAN_STATUS_DRIVE_FAIL_Pos (5UL) /*!< RPM_FAN STATUS: DRIVE_FAIL (Bit 5) */\r
+#define RPM_FAN_STATUS_DRIVE_FAIL_Msk (0x20UL) /*!< RPM_FAN STATUS: DRIVE_FAIL (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SPI_0' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- SPI_0_CONTROL ------------------------------- */\r
+#define SPI_0_CONTROL_LSBF_Pos (0UL) /*!< SPI_0 CONTROL: LSBF (Bit 0) */\r
+#define SPI_0_CONTROL_LSBF_Msk (0x1UL) /*!< SPI_0 CONTROL: LSBF (Bitfield-Mask: 0x01) */\r
+#define SPI_0_CONTROL_BIOEN_Pos (1UL) /*!< SPI_0 CONTROL: BIOEN (Bit 1) */\r
+#define SPI_0_CONTROL_BIOEN_Msk (0x2UL) /*!< SPI_0 CONTROL: BIOEN (Bitfield-Mask: 0x01) */\r
+#define SPI_0_CONTROL_SPDIN_SELECT_Pos (2UL) /*!< SPI_0 CONTROL: SPDIN_SELECT (Bit 2) */\r
+#define SPI_0_CONTROL_SPDIN_SELECT_Msk (0xcUL) /*!< SPI_0 CONTROL: SPDIN_SELECT (Bitfield-Mask: 0x03) */\r
+#define SPI_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< SPI_0 CONTROL: SOFT_RESET (Bit 4) */\r
+#define SPI_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< SPI_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define SPI_0_CONTROL_AUTO_READ_Pos (5UL) /*!< SPI_0 CONTROL: AUTO_READ (Bit 5) */\r
+#define SPI_0_CONTROL_AUTO_READ_Msk (0x20UL) /*!< SPI_0 CONTROL: AUTO_READ (Bitfield-Mask: 0x01) */\r
+#define SPI_0_CONTROL_CE_Pos (6UL) /*!< SPI_0 CONTROL: CE (Bit 6) */\r
+#define SPI_0_CONTROL_CE_Msk (0x40UL) /*!< SPI_0 CONTROL: CE (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- SPI_0_STATUS -------------------------------- */\r
+#define SPI_0_STATUS_TXBE_Pos (0UL) /*!< SPI_0 STATUS: TXBE (Bit 0) */\r
+#define SPI_0_STATUS_TXBE_Msk (0x1UL) /*!< SPI_0 STATUS: TXBE (Bitfield-Mask: 0x01) */\r
+#define SPI_0_STATUS_RXBF_Pos (1UL) /*!< SPI_0 STATUS: RXBF (Bit 1) */\r
+#define SPI_0_STATUS_RXBF_Msk (0x2UL) /*!< SPI_0 STATUS: RXBF (Bitfield-Mask: 0x01) */\r
+#define SPI_0_STATUS_ACTIVE_Pos (2UL) /*!< SPI_0 STATUS: ACTIVE (Bit 2) */\r
+#define SPI_0_STATUS_ACTIVE_Msk (0x4UL) /*!< SPI_0 STATUS: ACTIVE (Bitfield-Mask: 0x01) */\r
+\r
+/* ----------------------------- SPI_0_CLOCK_Control ---------------------------- */\r
+#define SPI_0_CLOCK_Control_TCLKPH_Pos (0UL) /*!< SPI_0 CLOCK_Control: TCLKPH (Bit 0) */\r
+#define SPI_0_CLOCK_Control_TCLKPH_Msk (0x1UL) /*!< SPI_0 CLOCK_Control: TCLKPH (Bitfield-Mask: 0x01) */\r
+#define SPI_0_CLOCK_Control_RCLKPH_Pos (1UL) /*!< SPI_0 CLOCK_Control: RCLKPH (Bit 1) */\r
+#define SPI_0_CLOCK_Control_RCLKPH_Msk (0x2UL) /*!< SPI_0 CLOCK_Control: RCLKPH (Bitfield-Mask: 0x01) */\r
+#define SPI_0_CLOCK_Control_CLKPOL_Pos (2UL) /*!< SPI_0 CLOCK_Control: CLKPOL (Bit 2) */\r
+#define SPI_0_CLOCK_Control_CLKPOL_Msk (0x4UL) /*!< SPI_0 CLOCK_Control: CLKPOL (Bitfield-Mask: 0x01) */\r
+#define SPI_0_CLOCK_Control_CLKSRC_Pos (4UL) /*!< SPI_0 CLOCK_Control: CLKSRC (Bit 4) */\r
+#define SPI_0_CLOCK_Control_CLKSRC_Msk (0x10UL) /*!< SPI_0 CLOCK_Control: CLKSRC (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SPI_1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- SPI_1_CONTROL ------------------------------- */\r
+#define SPI_1_CONTROL_LSBF_Pos (0UL) /*!< SPI_1 CONTROL: LSBF (Bit 0) */\r
+#define SPI_1_CONTROL_LSBF_Msk (0x1UL) /*!< SPI_1 CONTROL: LSBF (Bitfield-Mask: 0x01) */\r
+#define SPI_1_CONTROL_BIOEN_Pos (1UL) /*!< SPI_1 CONTROL: BIOEN (Bit 1) */\r
+#define SPI_1_CONTROL_BIOEN_Msk (0x2UL) /*!< SPI_1 CONTROL: BIOEN (Bitfield-Mask: 0x01) */\r
+#define SPI_1_CONTROL_SPDIN_SELECT_Pos (2UL) /*!< SPI_1 CONTROL: SPDIN_SELECT (Bit 2) */\r
+#define SPI_1_CONTROL_SPDIN_SELECT_Msk (0xcUL) /*!< SPI_1 CONTROL: SPDIN_SELECT (Bitfield-Mask: 0x03) */\r
+#define SPI_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< SPI_1 CONTROL: SOFT_RESET (Bit 4) */\r
+#define SPI_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< SPI_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define SPI_1_CONTROL_AUTO_READ_Pos (5UL) /*!< SPI_1 CONTROL: AUTO_READ (Bit 5) */\r
+#define SPI_1_CONTROL_AUTO_READ_Msk (0x20UL) /*!< SPI_1 CONTROL: AUTO_READ (Bitfield-Mask: 0x01) */\r
+#define SPI_1_CONTROL_CE_Pos (6UL) /*!< SPI_1 CONTROL: CE (Bit 6) */\r
+#define SPI_1_CONTROL_CE_Msk (0x40UL) /*!< SPI_1 CONTROL: CE (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- SPI_1_STATUS -------------------------------- */\r
+#define SPI_1_STATUS_TXBE_Pos (0UL) /*!< SPI_1 STATUS: TXBE (Bit 0) */\r
+#define SPI_1_STATUS_TXBE_Msk (0x1UL) /*!< SPI_1 STATUS: TXBE (Bitfield-Mask: 0x01) */\r
+#define SPI_1_STATUS_RXBF_Pos (1UL) /*!< SPI_1 STATUS: RXBF (Bit 1) */\r
+#define SPI_1_STATUS_RXBF_Msk (0x2UL) /*!< SPI_1 STATUS: RXBF (Bitfield-Mask: 0x01) */\r
+#define SPI_1_STATUS_ACTIVE_Pos (2UL) /*!< SPI_1 STATUS: ACTIVE (Bit 2) */\r
+#define SPI_1_STATUS_ACTIVE_Msk (0x4UL) /*!< SPI_1 STATUS: ACTIVE (Bitfield-Mask: 0x01) */\r
+\r
+/* ----------------------------- SPI_1_CLOCK_Control ---------------------------- */\r
+#define SPI_1_CLOCK_Control_TCLKPH_Pos (0UL) /*!< SPI_1 CLOCK_Control: TCLKPH (Bit 0) */\r
+#define SPI_1_CLOCK_Control_TCLKPH_Msk (0x1UL) /*!< SPI_1 CLOCK_Control: TCLKPH (Bitfield-Mask: 0x01) */\r
+#define SPI_1_CLOCK_Control_RCLKPH_Pos (1UL) /*!< SPI_1 CLOCK_Control: RCLKPH (Bit 1) */\r
+#define SPI_1_CLOCK_Control_RCLKPH_Msk (0x2UL) /*!< SPI_1 CLOCK_Control: RCLKPH (Bitfield-Mask: 0x01) */\r
+#define SPI_1_CLOCK_Control_CLKPOL_Pos (2UL) /*!< SPI_1 CLOCK_Control: CLKPOL (Bit 2) */\r
+#define SPI_1_CLOCK_Control_CLKPOL_Msk (0x4UL) /*!< SPI_1 CLOCK_Control: CLKPOL (Bitfield-Mask: 0x01) */\r
+#define SPI_1_CLOCK_Control_CLKSRC_Pos (4UL) /*!< SPI_1 CLOCK_Control: CLKSRC (Bit 4) */\r
+#define SPI_1_CLOCK_Control_CLKSRC_Msk (0x10UL) /*!< SPI_1 CLOCK_Control: CLKSRC (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'LED_0' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- LED_0_CONFIG -------------------------------- */\r
+#define LED_0_CONFIG_CONTROL_Pos (0UL) /*!< LED_0 CONFIG: CONTROL (Bit 0) */\r
+#define LED_0_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_0 CONFIG: CONTROL (Bitfield-Mask: 0x03) */\r
+#define LED_0_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_0 CONFIG: CLOCK_SOURCE (Bit 2) */\r
+#define LED_0_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_0 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */\r
+#define LED_0_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_0 CONFIG: SYNCHRONIZE (Bit 3) */\r
+#define LED_0_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_0 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */\r
+#define LED_0_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_0 CONFIG: PWM_SIZE (Bit 4) */\r
+#define LED_0_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_0 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */\r
+#define LED_0_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_0 CONFIG: ENABLE_UPDATE (Bit 6) */\r
+#define LED_0_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_0 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */\r
+#define LED_0_CONFIG_RESET_Pos (7UL) /*!< LED_0 CONFIG: RESET (Bit 7) */\r
+#define LED_0_CONFIG_RESET_Msk (0x80UL) /*!< LED_0 CONFIG: RESET (Bitfield-Mask: 0x01) */\r
+#define LED_0_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_0 CONFIG: WDT_RELOAD (Bit 8) */\r
+#define LED_0_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_0 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */\r
+#define LED_0_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_0 CONFIG: SYMMETRY (Bit 16) */\r
+#define LED_0_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_0 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- LED_0_LIMITS -------------------------------- */\r
+#define LED_0_LIMITS_MINIMUM_Pos (0UL) /*!< LED_0 LIMITS: MINIMUM (Bit 0) */\r
+#define LED_0_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_0 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */\r
+#define LED_0_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_0 LIMITS: MAXIMUM (Bit 8) */\r
+#define LED_0_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_0 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */\r
+\r
+/* --------------------------------- LED_0_DELAY -------------------------------- */\r
+#define LED_0_DELAY_LOW_Pos (0UL) /*!< LED_0 DELAY: LOW (Bit 0) */\r
+#define LED_0_DELAY_LOW_Msk (0xfffUL) /*!< LED_0 DELAY: LOW (Bitfield-Mask: 0xfff) */\r
+#define LED_0_DELAY_HIGH_Pos (12UL) /*!< LED_0 DELAY: HIGH (Bit 12) */\r
+#define LED_0_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_0 DELAY: HIGH (Bitfield-Mask: 0xfff) */\r
+\r
+/* ---------------------------- LED_0_UPDATE_STEPSIZE --------------------------- */\r
+#define LED_0_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_0 UPDATE_STEPSIZE: STEP0 (Bit 0) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_0 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_0 UPDATE_STEPSIZE: STEP1 (Bit 4) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_0 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_0 UPDATE_STEPSIZE: STEP2 (Bit 8) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_0 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_0 UPDATE_STEPSIZE: STEP3 (Bit 12) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_0 UPDATE_STEPSIZE: STEP4 (Bit 16) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_0 UPDATE_STEPSIZE: STEP5 (Bit 20) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_0 UPDATE_STEPSIZE: STEP6 (Bit 24) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_0 UPDATE_STEPSIZE: STEP7 (Bit 28) */\r
+#define LED_0_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */\r
+\r
+/* ---------------------------- LED_0_UPDATE_INTERVAL --------------------------- */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */\r
+#define LED_0_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'LED_1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- LED_1_CONFIG -------------------------------- */\r
+#define LED_1_CONFIG_CONTROL_Pos (0UL) /*!< LED_1 CONFIG: CONTROL (Bit 0) */\r
+#define LED_1_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_1 CONFIG: CONTROL (Bitfield-Mask: 0x03) */\r
+#define LED_1_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_1 CONFIG: CLOCK_SOURCE (Bit 2) */\r
+#define LED_1_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_1 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */\r
+#define LED_1_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_1 CONFIG: SYNCHRONIZE (Bit 3) */\r
+#define LED_1_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_1 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */\r
+#define LED_1_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_1 CONFIG: PWM_SIZE (Bit 4) */\r
+#define LED_1_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_1 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */\r
+#define LED_1_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_1 CONFIG: ENABLE_UPDATE (Bit 6) */\r
+#define LED_1_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_1 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */\r
+#define LED_1_CONFIG_RESET_Pos (7UL) /*!< LED_1 CONFIG: RESET (Bit 7) */\r
+#define LED_1_CONFIG_RESET_Msk (0x80UL) /*!< LED_1 CONFIG: RESET (Bitfield-Mask: 0x01) */\r
+#define LED_1_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_1 CONFIG: WDT_RELOAD (Bit 8) */\r
+#define LED_1_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_1 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */\r
+#define LED_1_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_1 CONFIG: SYMMETRY (Bit 16) */\r
+#define LED_1_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_1 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- LED_1_LIMITS -------------------------------- */\r
+#define LED_1_LIMITS_MINIMUM_Pos (0UL) /*!< LED_1 LIMITS: MINIMUM (Bit 0) */\r
+#define LED_1_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_1 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */\r
+#define LED_1_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_1 LIMITS: MAXIMUM (Bit 8) */\r
+#define LED_1_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_1 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */\r
+\r
+/* --------------------------------- LED_1_DELAY -------------------------------- */\r
+#define LED_1_DELAY_LOW_Pos (0UL) /*!< LED_1 DELAY: LOW (Bit 0) */\r
+#define LED_1_DELAY_LOW_Msk (0xfffUL) /*!< LED_1 DELAY: LOW (Bitfield-Mask: 0xfff) */\r
+#define LED_1_DELAY_HIGH_Pos (12UL) /*!< LED_1 DELAY: HIGH (Bit 12) */\r
+#define LED_1_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_1 DELAY: HIGH (Bitfield-Mask: 0xfff) */\r
+\r
+/* ---------------------------- LED_1_UPDATE_STEPSIZE --------------------------- */\r
+#define LED_1_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_1 UPDATE_STEPSIZE: STEP0 (Bit 0) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_1 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_1 UPDATE_STEPSIZE: STEP1 (Bit 4) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_1 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_1 UPDATE_STEPSIZE: STEP2 (Bit 8) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_1 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_1 UPDATE_STEPSIZE: STEP3 (Bit 12) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_1 UPDATE_STEPSIZE: STEP4 (Bit 16) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_1 UPDATE_STEPSIZE: STEP5 (Bit 20) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_1 UPDATE_STEPSIZE: STEP6 (Bit 24) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_1 UPDATE_STEPSIZE: STEP7 (Bit 28) */\r
+#define LED_1_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */\r
+\r
+/* ---------------------------- LED_1_UPDATE_INTERVAL --------------------------- */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */\r
+#define LED_1_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'LED_2' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- LED_2_CONFIG -------------------------------- */\r
+#define LED_2_CONFIG_CONTROL_Pos (0UL) /*!< LED_2 CONFIG: CONTROL (Bit 0) */\r
+#define LED_2_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_2 CONFIG: CONTROL (Bitfield-Mask: 0x03) */\r
+#define LED_2_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_2 CONFIG: CLOCK_SOURCE (Bit 2) */\r
+#define LED_2_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_2 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */\r
+#define LED_2_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_2 CONFIG: SYNCHRONIZE (Bit 3) */\r
+#define LED_2_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_2 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */\r
+#define LED_2_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_2 CONFIG: PWM_SIZE (Bit 4) */\r
+#define LED_2_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_2 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */\r
+#define LED_2_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_2 CONFIG: ENABLE_UPDATE (Bit 6) */\r
+#define LED_2_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_2 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */\r
+#define LED_2_CONFIG_RESET_Pos (7UL) /*!< LED_2 CONFIG: RESET (Bit 7) */\r
+#define LED_2_CONFIG_RESET_Msk (0x80UL) /*!< LED_2 CONFIG: RESET (Bitfield-Mask: 0x01) */\r
+#define LED_2_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_2 CONFIG: WDT_RELOAD (Bit 8) */\r
+#define LED_2_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_2 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */\r
+#define LED_2_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_2 CONFIG: SYMMETRY (Bit 16) */\r
+#define LED_2_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_2 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- LED_2_LIMITS -------------------------------- */\r
+#define LED_2_LIMITS_MINIMUM_Pos (0UL) /*!< LED_2 LIMITS: MINIMUM (Bit 0) */\r
+#define LED_2_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_2 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */\r
+#define LED_2_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_2 LIMITS: MAXIMUM (Bit 8) */\r
+#define LED_2_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_2 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */\r
+\r
+/* --------------------------------- LED_2_DELAY -------------------------------- */\r
+#define LED_2_DELAY_LOW_Pos (0UL) /*!< LED_2 DELAY: LOW (Bit 0) */\r
+#define LED_2_DELAY_LOW_Msk (0xfffUL) /*!< LED_2 DELAY: LOW (Bitfield-Mask: 0xfff) */\r
+#define LED_2_DELAY_HIGH_Pos (12UL) /*!< LED_2 DELAY: HIGH (Bit 12) */\r
+#define LED_2_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_2 DELAY: HIGH (Bitfield-Mask: 0xfff) */\r
+\r
+/* ---------------------------- LED_2_UPDATE_STEPSIZE --------------------------- */\r
+#define LED_2_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_2 UPDATE_STEPSIZE: STEP0 (Bit 0) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_2 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_2 UPDATE_STEPSIZE: STEP1 (Bit 4) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_2 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_2 UPDATE_STEPSIZE: STEP2 (Bit 8) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_2 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_2 UPDATE_STEPSIZE: STEP3 (Bit 12) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_2 UPDATE_STEPSIZE: STEP4 (Bit 16) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_2 UPDATE_STEPSIZE: STEP5 (Bit 20) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_2 UPDATE_STEPSIZE: STEP6 (Bit 24) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_2 UPDATE_STEPSIZE: STEP7 (Bit 28) */\r
+#define LED_2_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */\r
+\r
+/* ---------------------------- LED_2_UPDATE_INTERVAL --------------------------- */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */\r
+#define LED_2_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'LED_3' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- LED_3_CONFIG -------------------------------- */\r
+#define LED_3_CONFIG_CONTROL_Pos (0UL) /*!< LED_3 CONFIG: CONTROL (Bit 0) */\r
+#define LED_3_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_3 CONFIG: CONTROL (Bitfield-Mask: 0x03) */\r
+#define LED_3_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_3 CONFIG: CLOCK_SOURCE (Bit 2) */\r
+#define LED_3_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_3 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */\r
+#define LED_3_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_3 CONFIG: SYNCHRONIZE (Bit 3) */\r
+#define LED_3_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_3 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */\r
+#define LED_3_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_3 CONFIG: PWM_SIZE (Bit 4) */\r
+#define LED_3_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_3 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */\r
+#define LED_3_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_3 CONFIG: ENABLE_UPDATE (Bit 6) */\r
+#define LED_3_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_3 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */\r
+#define LED_3_CONFIG_RESET_Pos (7UL) /*!< LED_3 CONFIG: RESET (Bit 7) */\r
+#define LED_3_CONFIG_RESET_Msk (0x80UL) /*!< LED_3 CONFIG: RESET (Bitfield-Mask: 0x01) */\r
+#define LED_3_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_3 CONFIG: WDT_RELOAD (Bit 8) */\r
+#define LED_3_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_3 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */\r
+#define LED_3_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_3 CONFIG: SYMMETRY (Bit 16) */\r
+#define LED_3_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_3 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- LED_3_LIMITS -------------------------------- */\r
+#define LED_3_LIMITS_MINIMUM_Pos (0UL) /*!< LED_3 LIMITS: MINIMUM (Bit 0) */\r
+#define LED_3_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_3 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */\r
+#define LED_3_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_3 LIMITS: MAXIMUM (Bit 8) */\r
+#define LED_3_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_3 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */\r
+\r
+/* --------------------------------- LED_3_DELAY -------------------------------- */\r
+#define LED_3_DELAY_LOW_Pos (0UL) /*!< LED_3 DELAY: LOW (Bit 0) */\r
+#define LED_3_DELAY_LOW_Msk (0xfffUL) /*!< LED_3 DELAY: LOW (Bitfield-Mask: 0xfff) */\r
+#define LED_3_DELAY_HIGH_Pos (12UL) /*!< LED_3 DELAY: HIGH (Bit 12) */\r
+#define LED_3_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_3 DELAY: HIGH (Bitfield-Mask: 0xfff) */\r
+\r
+/* ---------------------------- LED_3_UPDATE_STEPSIZE --------------------------- */\r
+#define LED_3_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_3 UPDATE_STEPSIZE: STEP0 (Bit 0) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_3 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_3 UPDATE_STEPSIZE: STEP1 (Bit 4) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_3 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_3 UPDATE_STEPSIZE: STEP2 (Bit 8) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_3 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_3 UPDATE_STEPSIZE: STEP3 (Bit 12) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_3 UPDATE_STEPSIZE: STEP4 (Bit 16) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_3 UPDATE_STEPSIZE: STEP5 (Bit 20) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_3 UPDATE_STEPSIZE: STEP6 (Bit 24) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_3 UPDATE_STEPSIZE: STEP7 (Bit 28) */\r
+#define LED_3_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */\r
+\r
+/* ---------------------------- LED_3_UPDATE_INTERVAL --------------------------- */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */\r
+#define LED_3_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PS2_0' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PS2_0_CONTROL ------------------------------- */\r
+#define PS2_0_CONTROL_TR_Pos (0UL) /*!< PS2_0 CONTROL: TR (Bit 0) */\r
+#define PS2_0_CONTROL_TR_Msk (0x1UL) /*!< PS2_0 CONTROL: TR (Bitfield-Mask: 0x01) */\r
+#define PS2_0_CONTROL_EN_Pos (1UL) /*!< PS2_0 CONTROL: EN (Bit 1) */\r
+#define PS2_0_CONTROL_EN_Msk (0x2UL) /*!< PS2_0 CONTROL: EN (Bitfield-Mask: 0x01) */\r
+#define PS2_0_CONTROL_PARITY_Pos (2UL) /*!< PS2_0 CONTROL: PARITY (Bit 2) */\r
+#define PS2_0_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_0 CONTROL: PARITY (Bitfield-Mask: 0x03) */\r
+#define PS2_0_CONTROL_STOP_Pos (4UL) /*!< PS2_0 CONTROL: STOP (Bit 4) */\r
+#define PS2_0_CONTROL_STOP_Msk (0x30UL) /*!< PS2_0 CONTROL: STOP (Bitfield-Mask: 0x03) */\r
+\r
+/* -------------------------------- PS2_0_STATUS -------------------------------- */\r
+#define PS2_0_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_0 STATUS: RDATA_RDY (Bit 0) */\r
+#define PS2_0_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_0 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */\r
+#define PS2_0_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_0 STATUS: REC_TIMEOUT (Bit 1) */\r
+#define PS2_0_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_0 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */\r
+#define PS2_0_STATUS_PE_Pos (2UL) /*!< PS2_0 STATUS: PE (Bit 2) */\r
+#define PS2_0_STATUS_PE_Msk (0x4UL) /*!< PS2_0 STATUS: PE (Bitfield-Mask: 0x01) */\r
+#define PS2_0_STATUS_FE_Pos (3UL) /*!< PS2_0 STATUS: FE (Bit 3) */\r
+#define PS2_0_STATUS_FE_Msk (0x8UL) /*!< PS2_0 STATUS: FE (Bitfield-Mask: 0x01) */\r
+#define PS2_0_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_0 STATUS: XMIT_IDLE (Bit 4) */\r
+#define PS2_0_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_0 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */\r
+#define PS2_0_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_0 STATUS: XMIT_TIME_OUT (Bit 5) */\r
+#define PS2_0_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_0 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */\r
+#define PS2_0_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_0 STATUS: RX_BUSY (Bit 6) */\r
+#define PS2_0_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_0 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */\r
+#define PS2_0_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_0 STATUS: XMIT_START_TIMEOUT (Bit 7) */\r
+#define PS2_0_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_0 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PS2_1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PS2_1_CONTROL ------------------------------- */\r
+#define PS2_1_CONTROL_TR_Pos (0UL) /*!< PS2_1 CONTROL: TR (Bit 0) */\r
+#define PS2_1_CONTROL_TR_Msk (0x1UL) /*!< PS2_1 CONTROL: TR (Bitfield-Mask: 0x01) */\r
+#define PS2_1_CONTROL_EN_Pos (1UL) /*!< PS2_1 CONTROL: EN (Bit 1) */\r
+#define PS2_1_CONTROL_EN_Msk (0x2UL) /*!< PS2_1 CONTROL: EN (Bitfield-Mask: 0x01) */\r
+#define PS2_1_CONTROL_PARITY_Pos (2UL) /*!< PS2_1 CONTROL: PARITY (Bit 2) */\r
+#define PS2_1_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_1 CONTROL: PARITY (Bitfield-Mask: 0x03) */\r
+#define PS2_1_CONTROL_STOP_Pos (4UL) /*!< PS2_1 CONTROL: STOP (Bit 4) */\r
+#define PS2_1_CONTROL_STOP_Msk (0x30UL) /*!< PS2_1 CONTROL: STOP (Bitfield-Mask: 0x03) */\r
+\r
+/* -------------------------------- PS2_1_STATUS -------------------------------- */\r
+#define PS2_1_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_1 STATUS: RDATA_RDY (Bit 0) */\r
+#define PS2_1_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_1 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */\r
+#define PS2_1_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_1 STATUS: REC_TIMEOUT (Bit 1) */\r
+#define PS2_1_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_1 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */\r
+#define PS2_1_STATUS_PE_Pos (2UL) /*!< PS2_1 STATUS: PE (Bit 2) */\r
+#define PS2_1_STATUS_PE_Msk (0x4UL) /*!< PS2_1 STATUS: PE (Bitfield-Mask: 0x01) */\r
+#define PS2_1_STATUS_FE_Pos (3UL) /*!< PS2_1 STATUS: FE (Bit 3) */\r
+#define PS2_1_STATUS_FE_Msk (0x8UL) /*!< PS2_1 STATUS: FE (Bitfield-Mask: 0x01) */\r
+#define PS2_1_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_1 STATUS: XMIT_IDLE (Bit 4) */\r
+#define PS2_1_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_1 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */\r
+#define PS2_1_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_1 STATUS: XMIT_TIME_OUT (Bit 5) */\r
+#define PS2_1_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_1 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */\r
+#define PS2_1_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_1 STATUS: RX_BUSY (Bit 6) */\r
+#define PS2_1_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_1 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */\r
+#define PS2_1_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_1 STATUS: XMIT_START_TIMEOUT (Bit 7) */\r
+#define PS2_1_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_1 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PS2_2' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PS2_2_CONTROL ------------------------------- */\r
+#define PS2_2_CONTROL_TR_Pos (0UL) /*!< PS2_2 CONTROL: TR (Bit 0) */\r
+#define PS2_2_CONTROL_TR_Msk (0x1UL) /*!< PS2_2 CONTROL: TR (Bitfield-Mask: 0x01) */\r
+#define PS2_2_CONTROL_EN_Pos (1UL) /*!< PS2_2 CONTROL: EN (Bit 1) */\r
+#define PS2_2_CONTROL_EN_Msk (0x2UL) /*!< PS2_2 CONTROL: EN (Bitfield-Mask: 0x01) */\r
+#define PS2_2_CONTROL_PARITY_Pos (2UL) /*!< PS2_2 CONTROL: PARITY (Bit 2) */\r
+#define PS2_2_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_2 CONTROL: PARITY (Bitfield-Mask: 0x03) */\r
+#define PS2_2_CONTROL_STOP_Pos (4UL) /*!< PS2_2 CONTROL: STOP (Bit 4) */\r
+#define PS2_2_CONTROL_STOP_Msk (0x30UL) /*!< PS2_2 CONTROL: STOP (Bitfield-Mask: 0x03) */\r
+\r
+/* -------------------------------- PS2_2_STATUS -------------------------------- */\r
+#define PS2_2_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_2 STATUS: RDATA_RDY (Bit 0) */\r
+#define PS2_2_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_2 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */\r
+#define PS2_2_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_2 STATUS: REC_TIMEOUT (Bit 1) */\r
+#define PS2_2_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_2 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */\r
+#define PS2_2_STATUS_PE_Pos (2UL) /*!< PS2_2 STATUS: PE (Bit 2) */\r
+#define PS2_2_STATUS_PE_Msk (0x4UL) /*!< PS2_2 STATUS: PE (Bitfield-Mask: 0x01) */\r
+#define PS2_2_STATUS_FE_Pos (3UL) /*!< PS2_2 STATUS: FE (Bit 3) */\r
+#define PS2_2_STATUS_FE_Msk (0x8UL) /*!< PS2_2 STATUS: FE (Bitfield-Mask: 0x01) */\r
+#define PS2_2_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_2 STATUS: XMIT_IDLE (Bit 4) */\r
+#define PS2_2_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_2 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */\r
+#define PS2_2_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_2 STATUS: XMIT_TIME_OUT (Bit 5) */\r
+#define PS2_2_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_2 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */\r
+#define PS2_2_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_2 STATUS: RX_BUSY (Bit 6) */\r
+#define PS2_2_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_2 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */\r
+#define PS2_2_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_2 STATUS: XMIT_START_TIMEOUT (Bit 7) */\r
+#define PS2_2_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_2 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PS2_3' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PS2_3_CONTROL ------------------------------- */\r
+#define PS2_3_CONTROL_TR_Pos (0UL) /*!< PS2_3 CONTROL: TR (Bit 0) */\r
+#define PS2_3_CONTROL_TR_Msk (0x1UL) /*!< PS2_3 CONTROL: TR (Bitfield-Mask: 0x01) */\r
+#define PS2_3_CONTROL_EN_Pos (1UL) /*!< PS2_3 CONTROL: EN (Bit 1) */\r
+#define PS2_3_CONTROL_EN_Msk (0x2UL) /*!< PS2_3 CONTROL: EN (Bitfield-Mask: 0x01) */\r
+#define PS2_3_CONTROL_PARITY_Pos (2UL) /*!< PS2_3 CONTROL: PARITY (Bit 2) */\r
+#define PS2_3_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_3 CONTROL: PARITY (Bitfield-Mask: 0x03) */\r
+#define PS2_3_CONTROL_STOP_Pos (4UL) /*!< PS2_3 CONTROL: STOP (Bit 4) */\r
+#define PS2_3_CONTROL_STOP_Msk (0x30UL) /*!< PS2_3 CONTROL: STOP (Bitfield-Mask: 0x03) */\r
+\r
+/* -------------------------------- PS2_3_STATUS -------------------------------- */\r
+#define PS2_3_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_3 STATUS: RDATA_RDY (Bit 0) */\r
+#define PS2_3_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_3 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */\r
+#define PS2_3_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_3 STATUS: REC_TIMEOUT (Bit 1) */\r
+#define PS2_3_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_3 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */\r
+#define PS2_3_STATUS_PE_Pos (2UL) /*!< PS2_3 STATUS: PE (Bit 2) */\r
+#define PS2_3_STATUS_PE_Msk (0x4UL) /*!< PS2_3 STATUS: PE (Bitfield-Mask: 0x01) */\r
+#define PS2_3_STATUS_FE_Pos (3UL) /*!< PS2_3 STATUS: FE (Bit 3) */\r
+#define PS2_3_STATUS_FE_Msk (0x8UL) /*!< PS2_3 STATUS: FE (Bitfield-Mask: 0x01) */\r
+#define PS2_3_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_3 STATUS: XMIT_IDLE (Bit 4) */\r
+#define PS2_3_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_3 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */\r
+#define PS2_3_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_3 STATUS: XMIT_TIME_OUT (Bit 5) */\r
+#define PS2_3_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_3 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */\r
+#define PS2_3_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_3 STATUS: RX_BUSY (Bit 6) */\r
+#define PS2_3_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_3 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */\r
+#define PS2_3_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_3 STATUS: XMIT_START_TIMEOUT (Bit 7) */\r
+#define PS2_3_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_3 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'KEYSCAN' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------- KEYSCAN_CONTROL ------------------------------ */\r
+#define KEYSCAN_CONTROL_SELECT_Pos (0UL) /*!< KEYSCAN CONTROL: SELECT (Bit 0) */\r
+#define KEYSCAN_CONTROL_SELECT_Msk (0x1fUL) /*!< KEYSCAN CONTROL: SELECT (Bitfield-Mask: 0x1f) */\r
+#define KEYSCAN_CONTROL_ALL_Pos (5UL) /*!< KEYSCAN CONTROL: ALL (Bit 5) */\r
+#define KEYSCAN_CONTROL_ALL_Msk (0x20UL) /*!< KEYSCAN CONTROL: ALL (Bitfield-Mask: 0x01) */\r
+#define KEYSCAN_CONTROL_KSEN_Pos (6UL) /*!< KEYSCAN CONTROL: KSEN (Bit 6) */\r
+#define KEYSCAN_CONTROL_KSEN_Msk (0x40UL) /*!< KEYSCAN CONTROL: KSEN (Bitfield-Mask: 0x01) */\r
+#define KEYSCAN_CONTROL_INVERT_Pos (7UL) /*!< KEYSCAN CONTROL: INVERT (Bit 7) */\r
+#define KEYSCAN_CONTROL_INVERT_Msk (0x80UL) /*!< KEYSCAN CONTROL: INVERT (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'BC_LINK' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------- BC_LINK_STATUS ------------------------------- */\r
+#define BC_LINK_STATUS_BUSY_Pos (0UL) /*!< BC_LINK STATUS: BUSY (Bit 0) */\r
+#define BC_LINK_STATUS_BUSY_Msk (0x1UL) /*!< BC_LINK STATUS: BUSY (Bitfield-Mask: 0x01) */\r
+#define BC_LINK_STATUS_BUSY_CLR_INT_EN_Pos (4UL) /*!< BC_LINK STATUS: BUSY_CLR_INT_EN (Bit 4) */\r
+#define BC_LINK_STATUS_BUSY_CLR_INT_EN_Msk (0x10UL) /*!< BC_LINK STATUS: BUSY_CLR_INT_EN (Bitfield-Mask: 0x01) */\r
+#define BC_LINK_STATUS_ERR_INT_EN_Pos (5UL) /*!< BC_LINK STATUS: ERR_INT_EN (Bit 5) */\r
+#define BC_LINK_STATUS_ERR_INT_EN_Msk (0x20UL) /*!< BC_LINK STATUS: ERR_INT_EN (Bitfield-Mask: 0x01) */\r
+#define BC_LINK_STATUS_ERROR_Pos (6UL) /*!< BC_LINK STATUS: ERROR (Bit 6) */\r
+#define BC_LINK_STATUS_ERROR_Msk (0x40UL) /*!< BC_LINK STATUS: ERROR (Bitfield-Mask: 0x01) */\r
+#define BC_LINK_STATUS_RESET_Pos (7UL) /*!< BC_LINK STATUS: RESET (Bit 7) */\r
+#define BC_LINK_STATUS_RESET_Msk (0x80UL) /*!< BC_LINK STATUS: RESET (Bitfield-Mask: 0x01) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'TFDP' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- TFDP_CONTROL -------------------------------- */\r
+#define TFDP_CONTROL_EN_Pos (0UL) /*!< TFDP CONTROL: EN (Bit 0) */\r
+#define TFDP_CONTROL_EN_Msk (0x1UL) /*!< TFDP CONTROL: EN (Bitfield-Mask: 0x01) */\r
+#define TFDP_CONTROL_EDGE_SEL_Pos (1UL) /*!< TFDP CONTROL: EDGE_SEL (Bit 1) */\r
+#define TFDP_CONTROL_EDGE_SEL_Msk (0x2UL) /*!< TFDP CONTROL: EDGE_SEL (Bitfield-Mask: 0x01) */\r
+#define TFDP_CONTROL_DIVSEL_Pos (2UL) /*!< TFDP CONTROL: DIVSEL (Bit 2) */\r
+#define TFDP_CONTROL_DIVSEL_Msk (0xcUL) /*!< TFDP CONTROL: DIVSEL (Bitfield-Mask: 0x03) */\r
+#define TFDP_CONTROL_IP_DELAY_Pos (4UL) /*!< TFDP CONTROL: IP_DELAY (Bit 4) */\r
+#define TFDP_CONTROL_IP_DELAY_Msk (0x70UL) /*!< TFDP CONTROL: IP_DELAY (Bitfield-Mask: 0x07) */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'ADC' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- ADC_CONTROL -------------------------------- */\r
+#define ADC_CONTROL_ACTIVATE_Pos (0UL) /*!< ADC CONTROL: ACTIVATE (Bit 0) */\r
+#define ADC_CONTROL_ACTIVATE_Msk (0x1UL) /*!< ADC CONTROL: ACTIVATE (Bitfield-Mask: 0x01) */\r
+#define ADC_CONTROL_START_SINGLE_Pos (1UL) /*!< ADC CONTROL: START_SINGLE (Bit 1) */\r
+#define ADC_CONTROL_START_SINGLE_Msk (0x2UL) /*!< ADC CONTROL: START_SINGLE (Bitfield-Mask: 0x01) */\r
+#define ADC_CONTROL_START_REPEAT_Pos (2UL) /*!< ADC CONTROL: START_REPEAT (Bit 2) */\r
+#define ADC_CONTROL_START_REPEAT_Msk (0x4UL) /*!< ADC CONTROL: START_REPEAT (Bitfield-Mask: 0x01) */\r
+#define ADC_CONTROL_POWER_SAVER_DIS_Pos (3UL) /*!< ADC CONTROL: POWER_SAVER_DIS (Bit 3) */\r
+#define ADC_CONTROL_POWER_SAVER_DIS_Msk (0x8UL) /*!< ADC CONTROL: POWER_SAVER_DIS (Bitfield-Mask: 0x01) */\r
+#define ADC_CONTROL_SOFT_RESET_Pos (4UL) /*!< ADC CONTROL: SOFT_RESET (Bit 4) */\r
+#define ADC_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< ADC CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */\r
+#define ADC_CONTROL_REPEAT_DONE_STAT_Pos (6UL) /*!< ADC CONTROL: REPEAT_DONE_STAT (Bit 6) */\r
+#define ADC_CONTROL_REPEAT_DONE_STAT_Msk (0x40UL) /*!< ADC CONTROL: REPEAT_DONE_STAT (Bitfield-Mask: 0x01) */\r
+#define ADC_CONTROL_SINGLE_DONE_STAT_Pos (7UL) /*!< ADC CONTROL: SINGLE_DONE_STAT (Bit 7) */\r
+#define ADC_CONTROL_SINGLE_DONE_STAT_Msk (0x80UL) /*!< ADC CONTROL: SINGLE_DONE_STAT (Bitfield-Mask: 0x01) */\r
+\r
+/* ---------------------------------- ADC_DELAY --------------------------------- */\r
+#define ADC_DELAY_START_Pos (0UL) /*!< ADC DELAY: START (Bit 0) */\r
+#define ADC_DELAY_START_Msk (0xffffUL) /*!< ADC DELAY: START (Bitfield-Mask: 0xffff) */\r
+#define ADC_DELAY_REPEAT_Pos (16UL) /*!< ADC DELAY: REPEAT (Bit 16) */\r
+#define ADC_DELAY_REPEAT_Msk (0xffff0000UL) /*!< ADC DELAY: REPEAT (Bitfield-Mask: 0xffff) */\r
+\r
+/* --------------------------------- ADC_STATUS --------------------------------- */\r
+#define ADC_STATUS_CH0_Pos (0UL) /*!< ADC STATUS: CH0 (Bit 0) */\r
+#define ADC_STATUS_CH0_Msk (0x1UL) /*!< ADC STATUS: CH0 (Bitfield-Mask: 0x01) */\r
+#define ADC_STATUS_CH1_Pos (1UL) /*!< ADC STATUS: CH1 (Bit 1) */\r
+#define ADC_STATUS_CH1_Msk (0x2UL) /*!< ADC STATUS: CH1 (Bitfield-Mask: 0x01) */\r
+#define ADC_STATUS_CH2_Pos (2UL) /*!< ADC STATUS: CH2 (Bit 2) */\r
+#define ADC_STATUS_CH2_Msk (0x4UL) /*!< ADC STATUS: CH2 (Bitfield-Mask: 0x01) */\r
+#define ADC_STATUS_CH3_Pos (3UL) /*!< ADC STATUS: CH3 (Bit 3) */\r
+#define ADC_STATUS_CH3_Msk (0x8UL) /*!< ADC STATUS: CH3 (Bitfield-Mask: 0x01) */\r
+#define ADC_STATUS_CH4_Pos (4UL) /*!< ADC STATUS: CH4 (Bit 4) */\r
+#define ADC_STATUS_CH4_Msk (0x10UL) /*!< ADC STATUS: CH4 (Bitfield-Mask: 0x01) */\r
+\r
+/* -------------------------------- ADC_SINGLE_EN ------------------------------- */\r
+#define ADC_SINGLE_EN_CH0_Pos (0UL) /*!< ADC SINGLE_EN: CH0 (Bit 0) */\r
+#define ADC_SINGLE_EN_CH0_Msk (0x1UL) /*!< ADC SINGLE_EN: CH0 (Bitfield-Mask: 0x01) */\r
+#define ADC_SINGLE_EN_CH1_Pos (1UL) /*!< ADC SINGLE_EN: CH1 (Bit 1) */\r
+#define ADC_SINGLE_EN_CH1_Msk (0x2UL) /*!< ADC SINGLE_EN: CH1 (Bitfield-Mask: 0x01) */\r
+#define ADC_SINGLE_EN_CH2_Pos (2UL) /*!< ADC SINGLE_EN: CH2 (Bit 2) */\r
+#define ADC_SINGLE_EN_CH2_Msk (0x4UL) /*!< ADC SINGLE_EN: CH2 (Bitfield-Mask: 0x01) */\r
+#define ADC_SINGLE_EN_CH3_Pos (3UL) /*!< ADC SINGLE_EN: CH3 (Bit 3) */\r
+#define ADC_SINGLE_EN_CH3_Msk (0x8UL) /*!< ADC SINGLE_EN: CH3 (Bitfield-Mask: 0x01) */\r
+#define ADC_SINGLE_EN_CH4_Pos (4UL) /*!< ADC SINGLE_EN: CH4 (Bit 4) */\r
+#define ADC_SINGLE_EN_CH4_Msk (0x10UL) /*!< ADC SINGLE_EN: CH4 (Bitfield-Mask: 0x01) */\r
+\r
+/* --------------------------------- ADC_REPEAT --------------------------------- */\r
+#define ADC_REPEAT_CH0_Pos (0UL) /*!< ADC REPEAT: CH0 (Bit 0) */\r
+#define ADC_REPEAT_CH0_Msk (0x1UL) /*!< ADC REPEAT: CH0 (Bitfield-Mask: 0x01) */\r
+#define ADC_REPEAT_CH1_Pos (1UL) /*!< ADC REPEAT: CH1 (Bit 1) */\r
+#define ADC_REPEAT_CH1_Msk (0x2UL) /*!< ADC REPEAT: CH1 (Bitfield-Mask: 0x01) */\r
+#define ADC_REPEAT_CH2_Pos (2UL) /*!< ADC REPEAT: CH2 (Bit 2) */\r
+#define ADC_REPEAT_CH2_Msk (0x4UL) /*!< ADC REPEAT: CH2 (Bitfield-Mask: 0x01) */\r
+#define ADC_REPEAT_CH3_Pos (3UL) /*!< ADC REPEAT: CH3 (Bit 3) */\r
+#define ADC_REPEAT_CH3_Msk (0x8UL) /*!< ADC REPEAT: CH3 (Bitfield-Mask: 0x01) */\r
+#define ADC_REPEAT_CH4_Pos (4UL) /*!< ADC REPEAT: CH4 (Bit 4) */\r
+#define ADC_REPEAT_CH4_Msk (0x10UL) /*!< ADC REPEAT: CH4 (Bitfield-Mask: 0x01) */\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Peripheral memory map ================ */\r
+/* ================================================================================ */\r
+\r
+#define PCR_BASE 0x40080100UL\r
+#define VBAT_BASE 0x4000A400UL\r
+#define LPC_BASE 0x400F3000UL\r
+#define LPC_CONFIG_BASE 0x400F3300UL\r
+#define GCR_BASE 0x400FFF00UL\r
+#define EMI_BASE 0x400F0000UL\r
+#define ACPI_EC0_BASE 0x400F0C00UL\r
+#define ACPI_EC1_BASE 0x400F1000UL\r
+#define KBC_BASE 0x400F0400UL\r
+#define PORT92_BASE 0x400F1800UL\r
+#define MBX_BASE 0x400F2400UL\r
+#define PM1_BASE 0x400F1400UL\r
+#define UART_BASE 0x400F1C00UL\r
+#define INTR_BASE 0x4000C000UL\r
+#define WDT_BASE 0x40000400UL\r
+#define TIMER_16_0_BASE 0x40000C00UL\r
+#define TIMER_16_1_BASE 0x40000C20UL\r
+#define TIMER_16_2_BASE 0x40000C40UL\r
+#define TIMER_16_3_BASE 0x40000C60UL\r
+#define TIMER_32_0_BASE 0x40000C80UL\r
+#define TIMER_32_1_BASE 0x40000CA0UL\r
+#define HTM_BASE 0x40009800UL\r
+#define RTC_BASE 0x400F2C00UL\r
+#define GPIO_BASE 0x40081000UL\r
+#define DMA_BASE 0x40002400UL\r
+#define SMB0_BASE 0x40001800UL\r
+#define SMB1_BASE 0x4000AC00UL\r
+#define SMB2_BASE 0x4000B000UL\r
+#define SMB3_BASE 0x4000B400UL\r
+#define PECI_BASE 0x40006400UL\r
+#define TACH_0_BASE 0x40006000UL\r
+#define TACH_1_BASE 0x40006100UL\r
+#define PWM_0_BASE 0x40005800UL\r
+#define PWM_1_BASE 0x40005810UL\r
+#define PWM_2_BASE 0x40005820UL\r
+#define PWM_3_BASE 0x40005830UL\r
+#define RPM_FAN_BASE 0x4000A000UL\r
+#define SPI_0_BASE 0x40009400UL\r
+#define SPI_1_BASE 0x40009480UL\r
+#define LED_0_BASE 0x4000B800UL\r
+#define LED_1_BASE 0x4000B900UL\r
+#define LED_2_BASE 0x4000BA00UL\r
+#define LED_3_BASE 0x4000BB00UL\r
+#define PS2_0_BASE 0x40009000UL\r
+#define PS2_1_BASE 0x40009040UL\r
+#define PS2_2_BASE 0x40009080UL\r
+#define PS2_3_BASE 0x400090C0UL\r
+#define KEYSCAN_BASE 0x40009C00UL\r
+#define BC_LINK_BASE 0x4000BC00UL\r
+#define TFDP_BASE 0x40008C00UL\r
+#define ADC_BASE 0x40007C00UL\r
+#define EC_REG_BANK_BASE 0x4000FC00UL\r
+#define JTAG_BASE 0x40080000UL\r
+#define PKE_BASE 0x4000BD00UL\r
+#define TRNG_BASE 0x4000BE00UL\r
+#define HASH_BASE 0x4000D000UL\r
+#define AES_BASE 0x4000D200UL\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Peripheral declaration ================ */\r
+/* ================================================================================ */\r
+\r
+#define CEC1302_PCR ((PCR_Type *) PCR_BASE)\r
+#define CEC1302_VBAT ((VBAT_Type *) VBAT_BASE)\r
+#define CEC1302_LPC ((LPC_Type *) LPC_BASE)\r
+#define CEC1302_LPC_CONFIG ((LPC_CONFIG_Type *) LPC_CONFIG_BASE)\r
+#define CEC1302_GCR ((GCR_Type *) GCR_BASE)\r
+#define CEC1302_EMI ((EMI_Type *) EMI_BASE)\r
+#define CEC1302_ACPI_EC0 ((ACPI_EC0_Type *) ACPI_EC0_BASE)\r
+#define CEC1302_ACPI_EC1 ((ACPI_EC0_Type *) ACPI_EC1_BASE)\r
+#define CEC1302_KBC ((KBC_Type *) KBC_BASE)\r
+#define CEC1302_PORT92 ((PORT92_Type *) PORT92_BASE)\r
+#define CEC1302_MBX ((MBX_Type *) MBX_BASE)\r
+#define CEC1302_PM1 ((PM1_Type *) PM1_BASE)\r
+#define CEC1302_UART ((UART_Type *) UART_BASE)\r
+#define CEC1302_INTR ((INTR_Type *) INTR_BASE)\r
+#define CEC1302_WDT ((WDT_Type *) WDT_BASE)\r
+#define CEC1302_TIMER_16_0 ((TIMER_16_0_Type *) TIMER_16_0_BASE)\r
+#define CEC1302_TIMER_16_1 ((TIMER_16_0_Type *) TIMER_16_1_BASE)\r
+#define CEC1302_TIMER_16_2 ((TIMER_16_0_Type *) TIMER_16_2_BASE)\r
+#define CEC1302_TIMER_16_3 ((TIMER_16_0_Type *) TIMER_16_3_BASE)\r
+#define CEC1302_TIMER_32_0 ((TIMER_16_0_Type *) TIMER_32_0_BASE)\r
+#define CEC1302_TIMER_32_1 ((TIMER_16_0_Type *) TIMER_32_1_BASE)\r
+#define CEC1302_HTM ((HTM_Type *) HTM_BASE)\r
+#define CEC1302_RTC ((RTC_Type *) RTC_BASE)\r
+#define CEC1302_GPIO ((GPIO_Type *) GPIO_BASE)\r
+#define CEC1302_DMA ((DMA_Type *) DMA_BASE)\r
+#define CEC1302_SMB0 ((SMB0_Type *) SMB0_BASE)\r
+#define CEC1302_SMB1 ((SMB0_Type *) SMB1_BASE)\r
+#define CEC1302_SMB2 ((SMB0_Type *) SMB2_BASE)\r
+#define CEC1302_SMB3 ((SMB0_Type *) SMB3_BASE)\r
+#define CEC1302_PECI ((PECI_Type *) PECI_BASE)\r
+#define CEC1302_TACH_0 ((TACH_0_Type *) TACH_0_BASE)\r
+#define CEC1302_TACH_1 ((TACH_0_Type *) TACH_1_BASE)\r
+#define CEC1302_PWM_0 ((PWM_0_Type *) PWM_0_BASE)\r
+#define CEC1302_PWM_1 ((PWM_0_Type *) PWM_1_BASE)\r
+#define CEC1302_PWM_2 ((PWM_0_Type *) PWM_2_BASE)\r
+#define CEC1302_PWM_3 ((PWM_0_Type *) PWM_3_BASE)\r
+#define CEC1302_RPM_FAN ((RPM_FAN_Type *) RPM_FAN_BASE)\r
+#define CEC1302_SPI_0 ((SPI_0_Type *) SPI_0_BASE)\r
+#define CEC1302_SPI_1 ((SPI_0_Type *) SPI_1_BASE)\r
+#define CEC1302_LED_0 ((LED_0_Type *) LED_0_BASE)\r
+#define CEC1302_LED_1 ((LED_0_Type *) LED_1_BASE)\r
+#define CEC1302_LED_2 ((LED_0_Type *) LED_2_BASE)\r
+#define CEC1302_LED_3 ((LED_0_Type *) LED_3_BASE)\r
+#define CEC1302_PS2_0 ((PS2_0_Type *) PS2_0_BASE)\r
+#define CEC1302_PS2_1 ((PS2_0_Type *) PS2_1_BASE)\r
+#define CEC1302_PS2_2 ((PS2_0_Type *) PS2_2_BASE)\r
+#define CEC1302_PS2_3 ((PS2_0_Type *) PS2_3_BASE)\r
+#define CEC1302_KEYSCAN ((KEYSCAN_Type *) KEYSCAN_BASE)\r
+#define CEC1302_BC_LINK ((BC_LINK_Type *) BC_LINK_BASE)\r
+#define CEC1302_TFDP ((TFDP_Type *) TFDP_BASE)\r
+#define CEC1302_ADC ((ADC_Type *) ADC_BASE)\r
+#define CEC1302_EC_REG_BANK ((EC_REG_BANK_Type *) EC_REG_BANK_BASE)\r
+#define CEC1302_JTAG ((JTAG_Type *) JTAG_BASE)\r
+#define CEC1302_PKE ((PKE_TypeDef *) PKE_BASE)\r
+#define CEC1302_TRNG ((TRNG_TypeDef *) TRNG_BASE)\r
+#define CEC1302_HASH ((HASH_TypeDef *) HASH_BASE)\r
+#define CEC1302_AES ((AES_TypeDef *) AES_BASE)\r
+\r
+ \r
+/** @} */ /* End of group Device_Peripheral_Registers */\r
+/** @} */ /* End of group MCHP_CEC1302 */\r
+/** @} */ /* End of group Microchip Technology Inc. */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* MCHP_CEC1302_H */\r
+\r
+\r
--- /dev/null
+/*******************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+********************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+$File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/MEC1322.h $\r
+********************************************************************************\r
+$Revision: #1 $\r
+$DateTime: 2015/12/23 15:37:58 $\r
+$Author: akrishnan $\r
+ Change Description: Initial revision for MEC1322\r
+******************************************************************************/\r
+/** @file smscmmcr.h\r
+* brief the mmcr definitions\r
+* \r
+******************************************************************************/\r
+#ifndef SMSCMMCR_H_\r
+#define SMSCMMCR_H_\r
+\r
+//NOTE: Please Don't edit this File, this is extrated from the Spread sheet \r
+// : //depotAE/projects/MEC1322/docs/MMCRs/MEC1322_FPGA1_Query_All_Addressing_ResultSet.csv\r
+typedef volatile unsigned char VUINT8;\r
+typedef volatile unsigned short int VUINT16;\r
+typedef volatile unsigned long int VUINT32;\r
+\r
+/***************************************************************\r
+* PWM\r
+***************************************************************/\r
+#define ADDR_PWM_0_COUNTER_ON_TIME 0x40005800\r
+#define MMCR_PWM_0_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_ON_TIME))\r
+\r
+#define ADDR_PWM_0_COUNTER_OFF_TIME 0x40005804\r
+#define MMCR_PWM_0_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_OFF_TIME))\r
+\r
+#define ADDR_PWM_0_CONFIGURATION 0x40005808\r
+#define MMCR_PWM_0_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_0_CONFIGURATION))\r
+\r
+#define ADDR_PWM_1_COUNTER_ON_TIME 0x40005810\r
+#define MMCR_PWM_1_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_ON_TIME))\r
+\r
+#define ADDR_PWM_1_COUNTER_OFF_TIME 0x40005814\r
+#define MMCR_PWM_1_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_OFF_TIME))\r
+\r
+#define ADDR_PWM_1_CONFIGURATION 0x40005818\r
+#define MMCR_PWM_1_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_1_CONFIGURATION))\r
+\r
+#define ADDR_PWM_2_COUNTER_ON_TIME 0x40005820\r
+#define MMCR_PWM_2_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_ON_TIME))\r
+\r
+#define ADDR_PWM_2_COUNTER_OFF_TIME 0x40005824\r
+#define MMCR_PWM_2_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_OFF_TIME))\r
+\r
+#define ADDR_PWM_2_CONFIGURATION 0x40005828\r
+#define MMCR_PWM_2_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_2_CONFIGURATION))\r
+\r
+#define ADDR_PWM_3_COUNTER_ON_TIME 0x40005830\r
+#define MMCR_PWM_3_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_ON_TIME))\r
+\r
+#define ADDR_PWM_3_COUNTER_OFF_TIME 0x40005834\r
+#define MMCR_PWM_3_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_OFF_TIME))\r
+\r
+#define ADDR_PWM_3_CONFIGURATION 0x40005838\r
+#define MMCR_PWM_3_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_3_CONFIGURATION))\r
+\r
+/***************************************************************\r
+* PECI\r
+***************************************************************/\r
+#define ADDR_PECI_WRITE_DATA 0x40006400\r
+#define MMCR_PECI_WRITE_DATA (*(VUINT32 *)(ADDR_PECI_WRITE_DATA))\r
+\r
+#define ADDR_PECI_READ_DATA 0x40006404\r
+#define MMCR_PECI_READ_DATA (*(VUINT32 *)(ADDR_PECI_READ_DATA))\r
+\r
+#define ADDR_PECI_CONTROL 0x40006408\r
+#define MMCR_PECI_CONTROL (*(VUINT32 *)(ADDR_PECI_CONTROL))\r
+\r
+#define ADDR_PECI_STATUS_1 0x4000640C\r
+#define MMCR_PECI_STATUS_1 (*(VUINT32 *)(ADDR_PECI_STATUS_1))\r
+\r
+#define ADDR_PECI_STATUS_2 0x40006410\r
+#define MMCR_PECI_STATUS_2 (*(VUINT32 *)(ADDR_PECI_STATUS_2))\r
+\r
+#define ADDR_PECI_ERROR 0x40006414\r
+#define MMCR_PECI_ERROR (*(VUINT32 *)(ADDR_PECI_ERROR))\r
+\r
+#define ADDR_PECI_INTERRUPT_ENABLE_1 0x40006418\r
+#define MMCR_PECI_INTERRUPT_ENABLE_1 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_1))\r
+\r
+#define ADDR_PECI_INTERRUPT_ENABLE_2 0x4000641C\r
+#define MMCR_PECI_INTERRUPT_ENABLE_2 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_2))\r
+\r
+#define ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE 0x40006420\r
+#define MMCR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE))\r
+\r
+#define ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE 0x40006424\r
+#define MMCR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE))\r
+\r
+#define ADDR_PECI_REQUEST_TIMER_LOW_BYTE 0x40006428\r
+#define MMCR_PECI_REQUEST_TIMER_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_LOW_BYTE))\r
+\r
+#define ADDR_PECI_REQUEST_TIMER_HIGH_BYTE 0x4000642C\r
+#define MMCR_PECI_REQUEST_TIMER_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_HIGH_BYTE))\r
+\r
+#define ADDR_PECI_BLOCK_ID 0x40006440\r
+#define MMCR_PECI_BLOCK_ID (*(VUINT32 *)(ADDR_PECI_BLOCK_ID))\r
+\r
+#define ADDR_PECI_BLOCK_REVISION 0x40006444\r
+#define MMCR_PECI_BLOCK_REVISION (*(VUINT32 *)(ADDR_PECI_BLOCK_REVISION))\r
+\r
+/***************************************************************\r
+* ACPI EC Interface \r
+***************************************************************/\r
+#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0 0x400F0D00\r
+#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0))\r
+\r
+#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1 0x400F0D01\r
+#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1))\r
+\r
+#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2 0x400F0D02\r
+#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2))\r
+\r
+#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3 0x400F0D03\r
+#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3))\r
+\r
+#define ADDR_ACPI_0_STATUS_EC 0x400F0D04\r
+#define MMCR_ACPI_0_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_0_STATUS_EC))\r
+\r
+#define ADDR_ACPI_0_BYTE_CONTROL_EC 0x400F0D05\r
+#define MMCR_ACPI_0_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_0_BYTE_CONTROL_EC))\r
+\r
+#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08\r
+#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))\r
+\r
+#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08\r
+#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))\r
+\r
+#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1 0x400F0D09\r
+#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1))\r
+\r
+#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2 0x400F0D0A\r
+#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2))\r
+\r
+#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3 0x400F0D0B\r
+#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3))\r
+\r
+#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0 0x400F1100\r
+#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0))\r
+\r
+#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1 0x400F1101\r
+#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1))\r
+\r
+#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2 0x400F1102\r
+#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2))\r
+\r
+#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3 0x400F1103\r
+#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3))\r
+\r
+#define ADDR_ACPI_1_STATUS_EC 0x400F1104\r
+#define MMCR_ACPI_1_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_1_STATUS_EC))\r
+\r
+#define ADDR_ACPI_1_BYTE_CONTROL_EC 0x400F1105\r
+#define MMCR_ACPI_1_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_1_BYTE_CONTROL_EC))\r
+\r
+#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108\r
+#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))\r
+\r
+#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108\r
+#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))\r
+\r
+#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1 0x400F1109\r
+#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1))\r
+\r
+#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2 0x400F110A\r
+#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2))\r
+\r
+#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3 0x400F110B\r
+#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3))\r
+\r
+/***************************************************************\r
+* Keyboard Matrix Scan Support\r
+***************************************************************/\r
+#define ADDR_KEYBOARD_KSO_SELECT 0x40009C04\r
+#define MMCR_KEYBOARD_KSO_SELECT (*(VUINT32 *)(ADDR_KEYBOARD_KSO_SELECT))\r
+\r
+#define ADDR_KEYBOARD_KSI_INPUT 0x40009C08\r
+#define MMCR_KEYBOARD_KSI_INPUT (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INPUT))\r
+\r
+#define ADDR_KEYBOARD_KSI_STATUS 0x40009C0C\r
+#define MMCR_KEYBOARD_KSI_STATUS (*(VUINT32 *)(ADDR_KEYBOARD_KSI_STATUS))\r
+\r
+#define ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE 0x40009C10\r
+#define MMCR_KEYBOARD_KSI_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL 0x40009C14\r
+#define MMCR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL (*(VUINT32 *)(ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL))\r
+\r
+/***************************************************************\r
+* PS/2 Device Interface\r
+***************************************************************/\r
+#define ADDR_PS2_3_STATUS 0x400090C8\r
+#define MMCR_PS2_3_STATUS (*(VUINT8 *)(ADDR_PS2_3_STATUS))\r
+\r
+#define ADDR_PS2_3_CONTROL 0x400090C4\r
+#define MMCR_PS2_3_CONTROL (*(VUINT8 *)(ADDR_PS2_3_CONTROL))\r
+\r
+#define ADDR_PS2_3_RECEIVE_BUFFER 0x400090C0\r
+#define MMCR_PS2_3_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_3_RECEIVE_BUFFER))\r
+\r
+#define ADDR_PS2_3_TRANSMIT_BUFFER 0x400090C0\r
+#define MMCR_PS2_3_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_3_TRANSMIT_BUFFER))\r
+\r
+#define ADDR_PS2_0_TRANSMIT_BUFFER 0x40009000\r
+#define MMCR_PS2_0_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_0_TRANSMIT_BUFFER))\r
+\r
+#define ADDR_PS2_0_RECEIVE_BUFFER 0x40009000\r
+#define MMCR_PS2_0_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_0_RECEIVE_BUFFER))\r
+\r
+#define ADDR_PS2_0_CONTROL 0x40009004\r
+#define MMCR_PS2_0_CONTROL (*(VUINT8 *)(ADDR_PS2_0_CONTROL))\r
+\r
+#define ADDR_PS2_0_STATUS 0x40009008\r
+#define MMCR_PS2_0_STATUS (*(VUINT8 *)(ADDR_PS2_0_STATUS))\r
+\r
+#define ADDR_PS2_1_TRANSMIT_BUFFER 0x40009040\r
+#define MMCR_PS2_1_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_1_TRANSMIT_BUFFER))\r
+\r
+#define ADDR_PS2_1_RECEIVE_BUFFER 0x40009040\r
+#define MMCR_PS2_1_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_1_RECEIVE_BUFFER))\r
+\r
+#define ADDR_PS2_1_CONTROL 0x40009044\r
+#define MMCR_PS2_1_CONTROL (*(VUINT8 *)(ADDR_PS2_1_CONTROL))\r
+\r
+#define ADDR_PS2_1_STATUS 0x40009048\r
+#define MMCR_PS2_1_STATUS (*(VUINT8 *)(ADDR_PS2_1_STATUS))\r
+\r
+#define ADDR_PS2_2_RECEIVE_BUFFER 0x40009080\r
+#define MMCR_PS2_2_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_2_RECEIVE_BUFFER))\r
+\r
+#define ADDR_PS2_2_TRANSMIT_BUFFER 0x40009080\r
+#define MMCR_PS2_2_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_2_TRANSMIT_BUFFER))\r
+\r
+#define ADDR_PS2_2_CONTROL 0x40009084\r
+#define MMCR_PS2_2_CONTROL (*(VUINT8 *)(ADDR_PS2_2_CONTROL))\r
+\r
+#define ADDR_PS2_2_STATUS 0x40009088\r
+#define MMCR_PS2_2_STATUS (*(VUINT8 *)(ADDR_PS2_2_STATUS))\r
+\r
+/***************************************************************\r
+* 8042 Host Interface\r
+***************************************************************/\r
+#define ADDR_8042_ACTIVATE 0x400F0730\r
+#define MMCR_8042_ACTIVATE (*(VUINT8 *)(ADDR_8042_ACTIVATE))\r
+\r
+#define ADDR_8042_HOST_EC_DATACMD 0x400F0500\r
+#define MMCR_8042_HOST_EC_DATACMD (*(VUINT8 *)(ADDR_8042_HOST_EC_DATACMD))\r
+\r
+#define ADDR_8042_EC_HOST_DATA 0x400F0500\r
+#define MMCR_8042_EC_HOST_DATA (*(VUINT8 *)(ADDR_8042_EC_HOST_DATA))\r
+\r
+#define ADDR_8042_KEYBOARD_STATUS_READ 0x400F0504\r
+#define MMCR_8042_KEYBOARD_STATUS_READ (*(VUINT8 *)(ADDR_8042_KEYBOARD_STATUS_READ))\r
+\r
+#define ADDR_8042_KEYBOARD_CONTROL 0x400F0508\r
+#define MMCR_8042_KEYBOARD_CONTROL (*(VUINT8 *)(ADDR_8042_KEYBOARD_CONTROL))\r
+\r
+#define ADDR_8042_EC_HOST_AUX 0x400F050C\r
+#define MMCR_8042_EC_HOST_AUX (*(VUINT8 *)(ADDR_8042_EC_HOST_AUX))\r
+\r
+#define ADDR_8042_PCOBF 0x400F0514\r
+#define MMCR_8042_PCOBF (*(VUINT8 *)(ADDR_8042_PCOBF))\r
+\r
+#define ADDR_8042_PORT92_ENABLE 0x400F1B30\r
+#define MMCR_8042_PORT92_ENABLE (*(VUINT8 *)(ADDR_8042_PORT92_ENABLE))\r
+\r
+#define ADDR_8042_GATEA20_CONTROL 0x400F1900\r
+#define MMCR_8042_GATEA20_CONTROL (*(VUINT8 *)(ADDR_8042_GATEA20_CONTROL))\r
+\r
+#define ADDR_8042_SETGA20L 0x400F1908\r
+#define MMCR_8042_SETGA20L (*(VUINT8 *)(ADDR_8042_SETGA20L))\r
+\r
+#define ADDR_8042_RSTGA20L 0x400F190C\r
+#define MMCR_8042_RSTGA20L (*(VUINT8 *)(ADDR_8042_RSTGA20L))\r
+\r
+/***************************************************************\r
+* SMBus\r
+***************************************************************/\r
+#define ADDR_SMB_3_DEBUG_FSM_SMB 0x4000B45C\r
+#define MMCR_SMB_3_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_SMB))\r
+\r
+#define ADDR_SMB_3_DEBUG_FSM_I2C 0x4000B458\r
+#define MMCR_SMB_3_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_I2C))\r
+\r
+#define ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER 0x4000B454\r
+#define MMCR_SMBUS_3_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER))\r
+\r
+#define ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER 0x4000B450\r
+#define MMCR_SMBUS_3_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER))\r
+\r
+#define ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER 0x4000B44C\r
+#define MMCR_SMBUS_3_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER))\r
+\r
+#define ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER 0x4000B448\r
+#define MMCR_SMBUS_3_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER))\r
+\r
+#define ADDR_SMB_3_TIME_OUT_SCALING 0x4000B444\r
+#define MMCR_SMB_3_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_3_TIME_OUT_SCALING))\r
+\r
+#define ADDR_SMB_3_DATA_TIMING 0x4000B440\r
+#define MMCR_SMB_3_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_3_DATA_TIMING))\r
+\r
+#define ADDR_SMB_3_CLOCK_SYNC 0x4000B43C\r
+#define MMCR_SMB_3_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_3_CLOCK_SYNC))\r
+\r
+#define ADDR_SMB_3_BIT_BANG_CONTROL 0x4000B438\r
+#define MMCR_SMB_3_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_3_BIT_BANG_CONTROL))\r
+\r
+#define ADDR_SMB_3_REVISION 0x4000B434\r
+#define MMCR_SMB_3_REVISION (*(VUINT8 *)(ADDR_SMB_3_REVISION))\r
+\r
+#define ADDR_SMB_3_BLOCK_ID 0x4000B430\r
+#define MMCR_SMB_3_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_3_BLOCK_ID))\r
+\r
+#define ADDR_SMB_3_BUS_CLOCK 0x4000B42C\r
+#define MMCR_SMB_3_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_3_BUS_CLOCK))\r
+\r
+#define ADDR_SMB_3_CONFIGURATION 0x4000B428\r
+#define MMCR_SMB_3_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_3_CONFIGURATION))\r
+\r
+#define ADDR_SMB_3_IDLE_SCALING 0x4000B424\r
+#define MMCR_SMB_3_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_3_IDLE_SCALING))\r
+\r
+#define ADDR_SMB_3_COMPLETION 0x4000B420\r
+#define MMCR_SMB_3_COMPLETION (*(VUINT32 *)(ADDR_SMB_3_COMPLETION))\r
+\r
+#define ADDR_SMB_3_DATA_TIMING2 0x4000B418\r
+#define MMCR_SMB_3_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_3_DATA_TIMING2))\r
+\r
+#define ADDR_SMB_3_PEC 0x4000B414\r
+#define MMCR_SMB_3_PEC (*(VUINT8 *)(ADDR_SMB_3_PEC))\r
+\r
+#define ADDR_SMBUS_3_SLAVE_COMMAND 0x4000B410\r
+#define MMCR_SMBUS_3_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_SLAVE_COMMAND))\r
+\r
+#define ADDR_SMBUS_3_MASTER_COMMAND 0x4000B40C\r
+#define MMCR_SMBUS_3_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_MASTER_COMMAND))\r
+\r
+#define ADDR_SMB_3_DATA 0x4000B408\r
+#define MMCR_SMB_3_DATA (*(VUINT8 *)(ADDR_SMB_3_DATA))\r
+\r
+#define ADDR_SMB_3_OWN_ADDRESS 0x4000B404\r
+#define MMCR_SMB_3_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_3_OWN_ADDRESS))\r
+\r
+#define ADDR_SMB_3_STATUS 0x4000B400\r
+#define MMCR_SMB_3_STATUS (*(VUINT8 *)(ADDR_SMB_3_STATUS))\r
+\r
+#define ADDR_SMB_3_CONTROL 0x4000B400\r
+#define MMCR_SMB_3_CONTROL (*(VUINT8 *)(ADDR_SMB_3_CONTROL))\r
+\r
+#define ADDR_SMB_2_CONTROL 0x4000B000\r
+#define MMCR_SMB_2_CONTROL (*(VUINT8 *)(ADDR_SMB_2_CONTROL))\r
+\r
+#define ADDR_SMB_2_STATUS 0x4000B000\r
+#define MMCR_SMB_2_STATUS (*(VUINT8 *)(ADDR_SMB_2_STATUS))\r
+\r
+#define ADDR_SMB_2_OWN_ADDRESS 0x4000B004\r
+#define MMCR_SMB_2_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_2_OWN_ADDRESS))\r
+\r
+#define ADDR_SMB_2_DATA 0x4000B008\r
+#define MMCR_SMB_2_DATA (*(VUINT8 *)(ADDR_SMB_2_DATA))\r
+\r
+#define ADDR_SMBUS_2_MASTER_COMMAND 0x4000B00C\r
+#define MMCR_SMBUS_2_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_MASTER_COMMAND))\r
+\r
+#define ADDR_SMBUS_2_SLAVE_COMMAND 0x4000B010\r
+#define MMCR_SMBUS_2_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_SLAVE_COMMAND))\r
+\r
+#define ADDR_SMB_2_PEC 0x4000B014\r
+#define MMCR_SMB_2_PEC (*(VUINT8 *)(ADDR_SMB_2_PEC))\r
+\r
+#define ADDR_SMB_2_DATA_TIMING2 0x4000B018\r
+#define MMCR_SMB_2_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_2_DATA_TIMING2))\r
+\r
+#define ADDR_SMB_2_COMPLETION 0x4000B020\r
+#define MMCR_SMB_2_COMPLETION (*(VUINT32 *)(ADDR_SMB_2_COMPLETION))\r
+\r
+#define ADDR_SMB_2_IDLE_SCALING 0x4000B024\r
+#define MMCR_SMB_2_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_2_IDLE_SCALING))\r
+\r
+#define ADDR_SMB_2_CONFIGURATION 0x4000B028\r
+#define MMCR_SMB_2_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_2_CONFIGURATION))\r
+\r
+#define ADDR_SMB_2_BUS_CLOCK 0x4000B02C\r
+#define MMCR_SMB_2_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_2_BUS_CLOCK))\r
+\r
+#define ADDR_SMB_2_BLOCK_ID 0x4000B030\r
+#define MMCR_SMB_2_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_2_BLOCK_ID))\r
+\r
+#define ADDR_SMB_2_REVISION 0x4000B034\r
+#define MMCR_SMB_2_REVISION (*(VUINT8 *)(ADDR_SMB_2_REVISION))\r
+\r
+#define ADDR_SMB_2_BIT_BANG_CONTROL 0x4000B038\r
+#define MMCR_SMB_2_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_2_BIT_BANG_CONTROL))\r
+\r
+#define ADDR_SMB_2_CLOCK_SYNC 0x4000B03C\r
+#define MMCR_SMB_2_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_2_CLOCK_SYNC))\r
+\r
+#define ADDR_SMB_2_DATA_TIMING 0x4000B040\r
+#define MMCR_SMB_2_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_2_DATA_TIMING))\r
+\r
+#define ADDR_SMB_2_TIME_OUT_SCALING 0x4000B044\r
+#define MMCR_SMB_2_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_2_TIME_OUT_SCALING))\r
+\r
+#define ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER 0x4000B048\r
+#define MMCR_SMBUS_2_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER))\r
+\r
+#define ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER 0x4000B04C\r
+#define MMCR_SMBUS_2_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER))\r
+\r
+#define ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER 0x4000B050\r
+#define MMCR_SMBUS_2_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER))\r
+\r
+#define ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER 0x4000B054\r
+#define MMCR_SMBUS_2_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER))\r
+\r
+#define ADDR_SMB_2_DEBUG_FSM_I2C 0x4000B058\r
+#define MMCR_SMB_2_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_I2C))\r
+\r
+#define ADDR_SMB_2_DEBUG_FSM_SMB 0x4000B05C\r
+#define MMCR_SMB_2_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_SMB))\r
+\r
+#define ADDR_SMB_1_CONTROL 0x4000AC00\r
+#define MMCR_SMB_1_CONTROL (*(VUINT8 *)(ADDR_SMB_1_CONTROL))\r
+\r
+#define ADDR_SMB_1_STATUS 0x4000AC00\r
+#define MMCR_SMB_1_STATUS (*(VUINT8 *)(ADDR_SMB_1_STATUS))\r
+\r
+#define ADDR_SMB_1_OWN_ADDRESS 0x4000AC04\r
+#define MMCR_SMB_1_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_1_OWN_ADDRESS))\r
+\r
+#define ADDR_SMB_1_DATA 0x4000AC08\r
+#define MMCR_SMB_1_DATA (*(VUINT8 *)(ADDR_SMB_1_DATA))\r
+\r
+#define ADDR_SMBUS_1_MASTER_COMMAND 0x4000AC0C\r
+#define MMCR_SMBUS_1_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_MASTER_COMMAND))\r
+\r
+#define ADDR_SMBUS_1_SLAVE_COMMAND 0x4000AC10\r
+#define MMCR_SMBUS_1_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_SLAVE_COMMAND))\r
+\r
+#define ADDR_SMB_1_PEC 0x4000AC14\r
+#define MMCR_SMB_1_PEC (*(VUINT8 *)(ADDR_SMB_1_PEC))\r
+\r
+#define ADDR_SMB_1_DATA_TIMING2 0x4000AC18\r
+#define MMCR_SMB_1_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_1_DATA_TIMING2))\r
+\r
+#define ADDR_SMB_1_COMPLETION 0x4000AC20\r
+#define MMCR_SMB_1_COMPLETION (*(VUINT32 *)(ADDR_SMB_1_COMPLETION))\r
+\r
+#define ADDR_SMB_1_IDLE_SCALING 0x4000AC24\r
+#define MMCR_SMB_1_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_1_IDLE_SCALING))\r
+\r
+#define ADDR_SMB_1_CONFIGURATION 0x4000AC28\r
+#define MMCR_SMB_1_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_1_CONFIGURATION))\r
+\r
+#define ADDR_SMB_1_BUS_CLOCK 0x4000AC2C\r
+#define MMCR_SMB_1_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_1_BUS_CLOCK))\r
+\r
+#define ADDR_SMB_1_BLOCK_ID 0x4000AC30\r
+#define MMCR_SMB_1_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_1_BLOCK_ID))\r
+\r
+#define ADDR_SMB_1_REVISION 0x4000AC34\r
+#define MMCR_SMB_1_REVISION (*(VUINT8 *)(ADDR_SMB_1_REVISION))\r
+\r
+#define ADDR_SMB_1_BIT_BANG_CONTROL 0x4000AC38\r
+#define MMCR_SMB_1_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_1_BIT_BANG_CONTROL))\r
+\r
+#define ADDR_SMB_1_CLOCK_SYNC 0x4000AC3C\r
+#define MMCR_SMB_1_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_1_CLOCK_SYNC))\r
+\r
+#define ADDR_SMB_1_DATA_TIMING 0x4000AC40\r
+#define MMCR_SMB_1_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_1_DATA_TIMING))\r
+\r
+#define ADDR_SMB_1_TIME_OUT_SCALING 0x4000AC44\r
+#define MMCR_SMB_1_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_1_TIME_OUT_SCALING))\r
+\r
+#define ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER 0x4000AC48\r
+#define MMCR_SMBUS_1_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER))\r
+\r
+#define ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER 0x4000AC4C\r
+#define MMCR_SMBUS_1_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER))\r
+\r
+#define ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER 0x4000AC50\r
+#define MMCR_SMBUS_1_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER))\r
+\r
+#define ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER 0x4000AC54\r
+#define MMCR_SMBUS_1_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER))\r
+\r
+#define ADDR_SMB_1_DEBUG_FSM_I2C 0x4000AC58\r
+#define MMCR_SMB_1_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_I2C))\r
+\r
+#define ADDR_SMB_1_DEBUG_FSM_SMB 0x4000AC5C\r
+#define MMCR_SMB_1_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_SMB))\r
+\r
+#define ADDR_SMB_0_STATUS 0x40001800\r
+#define MMCR_SMB_0_STATUS (*(VUINT8 *)(ADDR_SMB_0_STATUS))\r
+\r
+#define ADDR_SMB_0_CONTROL 0x40001800\r
+#define MMCR_SMB_0_CONTROL (*(VUINT8 *)(ADDR_SMB_0_CONTROL))\r
+\r
+#define ADDR_SMB_0_OWN_ADDRESS 0x40001804\r
+#define MMCR_SMB_0_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_0_OWN_ADDRESS))\r
+\r
+#define ADDR_SMB_0_DATA 0x40001808\r
+#define MMCR_SMB_0_DATA (*(VUINT8 *)(ADDR_SMB_0_DATA))\r
+\r
+#define ADDR_SMBUS_0_MASTER_COMMAND 0x4000180C\r
+#define MMCR_SMBUS_0_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_MASTER_COMMAND))\r
+\r
+#define ADDR_SMBUS_0_SLAVE_COMMAND 0x40001810\r
+#define MMCR_SMBUS_0_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_SLAVE_COMMAND))\r
+\r
+#define ADDR_SMB_0_PEC 0x40001814\r
+#define MMCR_SMB_0_PEC (*(VUINT8 *)(ADDR_SMB_0_PEC))\r
+\r
+#define ADDR_SMB_0_DATA_TIMING2 0x40001818\r
+#define MMCR_SMB_0_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_0_DATA_TIMING2))\r
+\r
+#define ADDR_SMB_0_COMPLETION 0x40001820\r
+#define MMCR_SMB_0_COMPLETION (*(VUINT32 *)(ADDR_SMB_0_COMPLETION))\r
+\r
+#define ADDR_SMB_0_IDLE_SCALING 0x40001824\r
+#define MMCR_SMB_0_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_0_IDLE_SCALING))\r
+\r
+#define ADDR_SMB_0_CONFIGURATION 0x40001828\r
+#define MMCR_SMB_0_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_0_CONFIGURATION))\r
+\r
+#define ADDR_SMB_0_BUS_CLOCK 0x4000182C\r
+#define MMCR_SMB_0_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_0_BUS_CLOCK))\r
+\r
+#define ADDR_SMB_0_BLOCK_ID 0x40001830\r
+#define MMCR_SMB_0_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_0_BLOCK_ID))\r
+\r
+#define ADDR_SMB_0_REVISION 0x40001834\r
+#define MMCR_SMB_0_REVISION (*(VUINT8 *)(ADDR_SMB_0_REVISION))\r
+\r
+#define ADDR_SMB_0_BIT_BANG_CONTROL 0x40001838\r
+#define MMCR_SMB_0_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_0_BIT_BANG_CONTROL))\r
+\r
+#define ADDR_SMB_0_CLOCK_SYNC 0x4000183C\r
+#define MMCR_SMB_0_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_0_CLOCK_SYNC))\r
+\r
+#define ADDR_SMB_0_DATA_TIMING 0x40001840\r
+#define MMCR_SMB_0_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_0_DATA_TIMING))\r
+\r
+#define ADDR_SMB_0_TIME_OUT_SCALING 0x40001844\r
+#define MMCR_SMB_0_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_0_TIME_OUT_SCALING))\r
+\r
+#define ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER 0x40001848\r
+#define MMCR_SMBUS_0_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER))\r
+\r
+#define ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER 0x4000184C\r
+#define MMCR_SMBUS_0_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER))\r
+\r
+#define ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER 0x40001850\r
+#define MMCR_SMBUS_0_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER))\r
+\r
+#define ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER 0x40001854\r
+#define MMCR_SMBUS_0_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER))\r
+\r
+#define ADDR_SMB_0_DEBUG_FSM_I2C 0x40001858\r
+#define MMCR_SMB_0_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_I2C))\r
+\r
+#define ADDR_SMB_0_DEBUG_FSM_SMB 0x4000185C\r
+#define MMCR_SMB_0_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_SMB))\r
+\r
+/***************************************************************\r
+* Watchdog Timer Interface\r
+***************************************************************/\r
+#define ADDR_WATCHDOG_WDT_LOAD 0x40000400\r
+#define MMCR_WATCHDOG_WDT_LOAD (*(VUINT16 *)(ADDR_WATCHDOG_WDT_LOAD))\r
+\r
+#define ADDR_WATCHDOG_WDT_CONTROL 0x40000404\r
+#define MMCR_WATCHDOG_WDT_CONTROL (*(VUINT8 *)(ADDR_WATCHDOG_WDT_CONTROL))\r
+\r
+#define ADDR_WATCHDOG_WDT_KICK 0x40000408\r
+#define MMCR_WATCHDOG_WDT_KICK (*(VUINT8 *)(ADDR_WATCHDOG_WDT_KICK))\r
+\r
+#define ADDR_WATCHDOG_WDT_COUNT 0x4000040C\r
+#define MMCR_WATCHDOG_WDT_COUNT (*(VUINT16 *)(ADDR_WATCHDOG_WDT_COUNT))\r
+\r
+/***************************************************************\r
+* ACPI PM1\r
+***************************************************************/\r
+#define ADDR_ACPI_0_PM1_STATUS_1 0x400F1500\r
+#define MMCR_ACPI_0_PM1_STATUS_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_1))\r
+\r
+#define ADDR_ACPI_0_PM1_STATUS_2 0x400F1501\r
+#define MMCR_ACPI_0_PM1_STATUS_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_2))\r
+\r
+#define ADDR_ACPI_0_PM1_ENABLE_1 0x400F1502\r
+#define MMCR_ACPI_0_PM1_ENABLE_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_1))\r
+\r
+#define ADDR_ACPI_0_PM1_ENABLE_2 0x400F1503\r
+#define MMCR_ACPI_0_PM1_ENABLE_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_2))\r
+\r
+#define ADDR_ACPI_0_PM1_CONTROL_1 0x400F1504\r
+#define MMCR_ACPI_0_PM1_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_1))\r
+\r
+#define ADDR_ACPI_0_PM1_CONTROL_2 0x400F1505\r
+#define MMCR_ACPI_0_PM1_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_2))\r
+\r
+#define ADDR_ACPI_0_PM2_CONTROL_1 0x400F1506\r
+#define MMCR_ACPI_0_PM2_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_1))\r
+\r
+#define ADDR_ACPI_0_PM2_CONTROL_2 0x400F1507\r
+#define MMCR_ACPI_0_PM2_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_2))\r
+\r
+#define ADDR_ACPI_0_PM1_EC_PM_STATUS 0x400F1510\r
+#define MMCR_ACPI_0_PM1_EC_PM_STATUS (*(VUINT8 *)(ADDR_ACPI_0_PM1_EC_PM_STATUS))\r
+\r
+/***************************************************************\r
+* EC GP-SPI\r
+***************************************************************/\r
+#define ADDR_EC_1_SPI_CLOCK_GENERATOR 0x40009498\r
+#define MMCR_EC_1_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_GENERATOR))\r
+\r
+#define ADDR_EC_1_SPI_CLOCK_CONTROL 0x40009494\r
+#define MMCR_EC_1_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_CONTROL))\r
+\r
+#define ADDR_EC_1_SPI_RX_DATA 0x40009490\r
+#define MMCR_EC_1_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_RX_DATA))\r
+\r
+#define ADDR_EC_1_SPI_TX_DATA 0x4000948C\r
+#define MMCR_EC_1_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_TX_DATA))\r
+\r
+#define ADDR_EC_1_SPI_STATUS 0x40009488\r
+#define MMCR_EC_1_SPI_STATUS (*(VUINT32 *)(ADDR_EC_1_SPI_STATUS))\r
+\r
+#define ADDR_EC_1_SPI_CONTROL 0x40009484\r
+#define MMCR_EC_1_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CONTROL))\r
+\r
+#define ADDR_EC_1_SPI_ENABLE 0x40009480\r
+#define MMCR_EC_1_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_1_SPI_ENABLE))\r
+\r
+#define ADDR_EC_0_SPI_ENABLE 0x40009400\r
+#define MMCR_EC_0_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_0_SPI_ENABLE))\r
+\r
+#define ADDR_EC_0_SPI_CONTROL 0x40009404\r
+#define MMCR_EC_0_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CONTROL))\r
+\r
+#define ADDR_EC_0_SPI_STATUS 0x40009408\r
+#define MMCR_EC_0_SPI_STATUS (*(VUINT32 *)(ADDR_EC_0_SPI_STATUS))\r
+\r
+#define ADDR_EC_0_SPI_TX_DATA 0x4000940C\r
+#define MMCR_EC_0_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_TX_DATA))\r
+\r
+#define ADDR_EC_0_SPI_RX_DATA 0x40009410\r
+#define MMCR_EC_0_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_RX_DATA))\r
+\r
+#define ADDR_EC_0_SPI_CLOCK_CONTROL 0x40009414\r
+#define MMCR_EC_0_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_CONTROL))\r
+\r
+#define ADDR_EC_0_SPI_CLOCK_GENERATOR 0x40009418\r
+#define MMCR_EC_0_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_GENERATOR))\r
+\r
+/***************************************************************\r
+* Mailbox Registers Interface\r
+***************************************************************/\r
+#define ADDR_MAILBOX_HOST_TO_EC_MAILBOX 0x400F2500\r
+#define MMCR_MAILBOX_HOST_TO_EC_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_HOST_TO_EC_MAILBOX))\r
+\r
+#define ADDR_MAILBOX_EC_TO_HOST_MAILBOX 0x400F2504\r
+#define MMCR_MAILBOX_EC_TO_HOST_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_EC_TO_HOST_MAILBOX))\r
+\r
+#define ADDR_MAILBOX_SMI_INTERRUPT_SOURCE 0x400F2508\r
+#define MMCR_MAILBOX_SMI_INTERRUPT_SOURCE (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_SOURCE))\r
+\r
+#define ADDR_MAILBOX_SMI_INTERRUPT_MASK 0x400F250C\r
+#define MMCR_MAILBOX_SMI_INTERRUPT_MASK (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_MASK))\r
+\r
+#define ADDR_MAILBOX_3_0 0x400F2510\r
+#define MMCR_MAILBOX_3_0 (*(VUINT32 *)(ADDR_MAILBOX_3_0))\r
+\r
+#define ADDR_MAILBOX_7_4 0x400F2514\r
+#define MMCR_MAILBOX_7_4 (*(VUINT32 *)(ADDR_MAILBOX_7_4))\r
+\r
+#define ADDR_MAILBOX_BH_8 0x400F2518\r
+#define MMCR_MAILBOX_BH_8 (*(VUINT32 *)(ADDR_MAILBOX_BH_8))\r
+\r
+#define ADDR_MAILBOX_FH_CH 0x400F251C\r
+#define MMCR_MAILBOX_FH_CH (*(VUINT32 *)(ADDR_MAILBOX_FH_CH))\r
+\r
+#define ADDR_MAILBOX_13H_10H 0x400F2520\r
+#define MMCR_MAILBOX_13H_10H (*(VUINT32 *)(ADDR_MAILBOX_13H_10H))\r
+\r
+#define ADDR_MAILBOX_17H_14H 0x400F2524\r
+#define MMCR_MAILBOX_17H_14H (*(VUINT32 *)(ADDR_MAILBOX_17H_14H))\r
+\r
+#define ADDR_MAILBOX_1BH_18H 0x400F2528\r
+#define MMCR_MAILBOX_1BH_18H (*(VUINT32 *)(ADDR_MAILBOX_1BH_18H))\r
+\r
+#define ADDR_MAILBOX_1FH_1CH 0x400F252C\r
+#define MMCR_MAILBOX_1FH_1CH (*(VUINT32 *)(ADDR_MAILBOX_1FH_1CH))\r
+\r
+/***************************************************************\r
+* Hibernation Timer\r
+***************************************************************/\r
+#define ADDR_HIBERNATION_0_HTIMER_X_PRELOAD 0x40009800\r
+#define MMCR_HIBERNATION_0_HTIMER_X_PRELOAD (*(VUINT16 *)(ADDR_HIBERNATION_0_HTIMER_X_PRELOAD))\r
+\r
+#define ADDR_HIBERNATION_0_TIMER_X_CONTROL 0x40009804\r
+#define MMCR_HIBERNATION_0_TIMER_X_CONTROL (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_CONTROL))\r
+\r
+#define ADDR_HIBERNATION_0_TIMER_X_COUNT 0x40009808\r
+#define MMCR_HIBERNATION_0_TIMER_X_COUNT (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_COUNT))\r
+\r
+/***************************************************************\r
+* UART\r
+***************************************************************/\r
+#define ADDR_M16C550A_UART_ACTIVATE 0x400F1F30\r
+#define MMCR_M16C550A_UART_ACTIVATE (*(VUINT8 *)(ADDR_M16C550A_UART_ACTIVATE))\r
+\r
+#define ADDR_M16C550A_UART_CONFIG_SELECT 0x400F1FF0\r
+#define MMCR_M16C550A_UART_CONFIG_SELECT (*(VUINT8 *)(ADDR_M16C550A_UART_CONFIG_SELECT))\r
+\r
+#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB 0x400F1D00\r
+#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB))\r
+\r
+#define ADDR_M16C550A_UART_RECEIVE_BUFFER 0x400F1D00\r
+#define MMCR_M16C550A_UART_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_RECEIVE_BUFFER))\r
+\r
+#define ADDR_M16C550A_UART_TRANSMIT_BUFFER 0x400F1D00\r
+#define MMCR_M16C550A_UART_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_TRANSMIT_BUFFER))\r
+\r
+#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB 0x400F1D01\r
+#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB))\r
+\r
+#define ADDR_M16C550A_UART_INTERRUPT_ENABLE 0x400F1D01\r
+#define MMCR_M16C550A_UART_INTERRUPT_ENABLE (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_M16C550A_UART_FIFO_CONTROL 0x400F1D02\r
+#define MMCR_M16C550A_UART_FIFO_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_FIFO_CONTROL))\r
+\r
+#define ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION 0x400F1D02\r
+#define MMCR_M16C550A_UART_INTERRUPT_IDENTIFICATION (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION))\r
+\r
+#define ADDR_M16C550A_UART_LINE_CONTROL 0x400F1D03\r
+#define MMCR_M16C550A_UART_LINE_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_CONTROL))\r
+\r
+#define ADDR_M16C550A_UART_MODEM_CONTROL 0x400F1D04\r
+#define MMCR_M16C550A_UART_MODEM_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_CONTROL))\r
+\r
+#define ADDR_M16C550A_UART_LINE_STATUS 0x400F1D05\r
+#define MMCR_M16C550A_UART_LINE_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_STATUS))\r
+\r
+#define ADDR_M16C550A_UART_MODEM_STATUS 0x400F1D06\r
+#define MMCR_M16C550A_UART_MODEM_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_STATUS))\r
+\r
+#define ADDR_M16C550A_UART_SCRATCHPAD 0x400F1D07\r
+#define MMCR_M16C550A_UART_SCRATCHPAD (*(VUINT8 *)(ADDR_M16C550A_UART_SCRATCHPAD))\r
+\r
+/***************************************************************\r
+* TACH\r
+***************************************************************/\r
+#define ADDR_TACH_0_CONTROL 0x40006000\r
+#define MMCR_TACH_0_CONTROL (*(VUINT32 *)(ADDR_TACH_0_CONTROL))\r
+\r
+#define ADDR_TACH_0_STATUS 0x40006004\r
+#define MMCR_TACH_0_STATUS (*(VUINT32 *)(ADDR_TACH_0_STATUS))\r
+\r
+#define ADDR_TACH_0_HIGH_LIMIT 0x40006008\r
+#define MMCR_TACH_0_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_0_HIGH_LIMIT))\r
+\r
+#define ADDR_TACH_0_LOW_LIMIT 0x4000600C\r
+#define MMCR_TACH_0_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_0_LOW_LIMIT))\r
+\r
+#define ADDR_TACH_1_CONTROL 0x40006010\r
+#define MMCR_TACH_1_CONTROL (*(VUINT32 *)(ADDR_TACH_1_CONTROL))\r
+\r
+#define ADDR_TACH_1_STATUS 0x40006014\r
+#define MMCR_TACH_1_STATUS (*(VUINT32 *)(ADDR_TACH_1_STATUS))\r
+\r
+#define ADDR_TACH_1_HIGH_LIMIT 0x40006018\r
+#define MMCR_TACH_1_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_1_HIGH_LIMIT))\r
+\r
+#define ADDR_TACH_1_LOW_LIMIT 0x4000601C\r
+#define MMCR_TACH_1_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_1_LOW_LIMIT))\r
+\r
+/***************************************************************\r
+* Global Config Regs Basic\r
+***************************************************************/\r
+#define ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER 0x400FFF07\r
+#define MMCR_GLOBAL_LOGICAL_DEVICE_NUMBER (*(VUINT8 *)(ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER))\r
+\r
+#define ADDR_GLOBAL_DEVICE_ID 0x400FFF20\r
+#define MMCR_GLOBAL_DEVICE_ID (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_ID))\r
+\r
+#define ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED 0x400FFF21\r
+#define MMCR_GLOBAL_DEVICE_REVISION_HARD_WIRED (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED))\r
+\r
+#define ADDR_GLOBAL_GCR_BUILD 0x400FFF28\r
+#define MMCR_GLOBAL_GCR_BUILD (*(VUINT16 *)(ADDR_GLOBAL_GCR_BUILD))\r
+\r
+#define ADDR_GLOBAL_GCR_SCRATCH 0x400FFF2C\r
+#define MMCR_GLOBAL_GCR_SCRATCH (*(VUINT32 *)(ADDR_GLOBAL_GCR_SCRATCH))\r
+\r
+/***************************************************************\r
+* Trace FIFO Debug Port\r
+***************************************************************/\r
+#define ADDR_TRACE_DATA 0x40008C00\r
+#define MMCR_TRACE_DATA (*(VUINT32 *)(ADDR_TRACE_DATA))\r
+\r
+#define ADDR_TRACE_CONTROL 0x40008C04\r
+#define MMCR_TRACE_CONTROL (*(VUINT32 *)(ADDR_TRACE_CONTROL))\r
+\r
+/***************************************************************\r
+* STAP\r
+***************************************************************/\r
+#define ADDR_STAP_MESSAGE_OBF 0x40080000\r
+#define MMCR_STAP_MESSAGE_OBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_OBF))\r
+\r
+#define ADDR_STAP_MESSAGE_IBF 0x40080004\r
+#define MMCR_STAP_MESSAGE_IBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_IBF))\r
+\r
+#define ADDR_STAP_OBF_STATUS 0x40080008\r
+#define MMCR_STAP_OBF_STATUS (*(VUINT8 *)(ADDR_STAP_OBF_STATUS))\r
+\r
+#define ADDR_STAP_IBF_STATUS 0x40080009\r
+#define MMCR_STAP_IBF_STATUS (*(VUINT8 *)(ADDR_STAP_IBF_STATUS))\r
+\r
+#define ADDR_STAP_DBG_CTRL 0x4008000C\r
+#define MMCR_STAP_DBG_CTRL (*(VUINT8 *)(ADDR_STAP_DBG_CTRL))\r
+\r
+/***************************************************************\r
+* EMI\r
+***************************************************************/\r
+#define ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX 0x400F0100\r
+#define MMCR_IMAP_EMI_HOST_TO_EC_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX))\r
+\r
+#define ADDR_IMAP_EC_TO_HOST_MAILBOX 0x400F0101\r
+#define MMCR_IMAP_EC_TO_HOST_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EC_TO_HOST_MAILBOX))\r
+\r
+#define ADDR_IMAP_MEMORY_BASE_ADDRESS_0 0x400F0104\r
+#define MMCR_IMAP_MEMORY_BASE_ADDRESS_0 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_0))\r
+\r
+#define ADDR_IMAP_MEMORY_READ_LIMIT_0 0x400F0108\r
+#define MMCR_IMAP_MEMORY_READ_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_0))\r
+\r
+#define ADDR_IMAP_MEMORY_WRITE_LIMIT_0 0x400F010A\r
+#define MMCR_IMAP_MEMORY_WRITE_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_0))\r
+\r
+#define ADDR_IMAP_MEMORY_BASE_ADDRESS_1 0x400F010C\r
+#define MMCR_IMAP_MEMORY_BASE_ADDRESS_1 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_1))\r
+\r
+#define ADDR_IMAP_MEMORY_READ_LIMIT_1 0x400F0110\r
+#define MMCR_IMAP_MEMORY_READ_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_1))\r
+\r
+#define ADDR_IMAP_MEMORY_WRITE_LIMIT_1 0x400F0112\r
+#define MMCR_IMAP_MEMORY_WRITE_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_1))\r
+\r
+#define ADDR_IMAP_INTERRUPT_SET 0x400F0114\r
+#define MMCR_IMAP_INTERRUPT_SET (*(VUINT16 *)(ADDR_IMAP_INTERRUPT_SET))\r
+\r
+#define ADDR_IMAP_HOST_CLEAR_ENABLE 0x400F0116\r
+#define MMCR_IMAP_HOST_CLEAR_ENABLE (*(VUINT16 *)(ADDR_IMAP_HOST_CLEAR_ENABLE))\r
+\r
+/***************************************************************\r
+* Blinking/Breathing PWM\r
+***************************************************************/\r
+#define ADDR_LED_3_UPDATE_INTERVAL 0x4000BB10\r
+#define MMCR_LED_3_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_3_UPDATE_INTERVAL))\r
+\r
+#define ADDR_LED_3_UPDATE_STEPSIZE 0x4000BB0C\r
+#define MMCR_LED_3_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_3_UPDATE_STEPSIZE))\r
+\r
+#define ADDR_LED_3_DELAY 0x4000BB08\r
+#define MMCR_LED_3_DELAY (*(VUINT32 *)(ADDR_LED_3_DELAY))\r
+\r
+#define ADDR_LED_3_LIMITS 0x4000BB04\r
+#define MMCR_LED_3_LIMITS (*(VUINT32 *)(ADDR_LED_3_LIMITS))\r
+\r
+#define ADDR_LED_3_CONFIGURATION 0x4000BB00\r
+#define MMCR_LED_3_CONFIGURATION (*(VUINT32 *)(ADDR_LED_3_CONFIGURATION))\r
+\r
+#define ADDR_LED_2_UPDATE_INTERVAL 0x4000BA10\r
+#define MMCR_LED_2_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_2_UPDATE_INTERVAL))\r
+\r
+#define ADDR_LED_2_UPDATE_STEPSIZE 0x4000BA0C\r
+#define MMCR_LED_2_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_2_UPDATE_STEPSIZE))\r
+\r
+#define ADDR_LED_2_DELAY 0x4000BA08\r
+#define MMCR_LED_2_DELAY (*(VUINT32 *)(ADDR_LED_2_DELAY))\r
+\r
+#define ADDR_LED_2_LIMITS 0x4000BA04\r
+#define MMCR_LED_2_LIMITS (*(VUINT32 *)(ADDR_LED_2_LIMITS))\r
+\r
+#define ADDR_LED_2_CONFIGURATION 0x4000BA00\r
+#define MMCR_LED_2_CONFIGURATION (*(VUINT32 *)(ADDR_LED_2_CONFIGURATION))\r
+\r
+#define ADDR_LED_1_CONFIGURATION 0x4000B900\r
+#define MMCR_LED_1_CONFIGURATION (*(VUINT32 *)(ADDR_LED_1_CONFIGURATION))\r
+\r
+#define ADDR_LED_1_LIMITS 0x4000B904\r
+#define MMCR_LED_1_LIMITS (*(VUINT32 *)(ADDR_LED_1_LIMITS))\r
+\r
+#define ADDR_LED_1_DELAY 0x4000B908\r
+#define MMCR_LED_1_DELAY (*(VUINT32 *)(ADDR_LED_1_DELAY))\r
+\r
+#define ADDR_LED_1_UPDATE_STEPSIZE 0x4000B90C\r
+#define MMCR_LED_1_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_1_UPDATE_STEPSIZE))\r
+\r
+#define ADDR_LED_1_UPDATE_INTERVAL 0x4000B910\r
+#define MMCR_LED_1_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_1_UPDATE_INTERVAL))\r
+\r
+#define ADDR_LED_0_CONFIGURATION 0x4000B800\r
+#define MMCR_LED_0_CONFIGURATION (*(VUINT32 *)(ADDR_LED_0_CONFIGURATION))\r
+\r
+#define ADDR_LED_0_LIMITS 0x4000B804\r
+#define MMCR_LED_0_LIMITS (*(VUINT32 *)(ADDR_LED_0_LIMITS))\r
+\r
+#define ADDR_LED_0_DELAY 0x4000B808\r
+#define MMCR_LED_0_DELAY (*(VUINT32 *)(ADDR_LED_0_DELAY))\r
+\r
+#define ADDR_LED_0_UPDATE_STEPSIZE 0x4000B80C\r
+#define MMCR_LED_0_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_0_UPDATE_STEPSIZE))\r
+\r
+#define ADDR_LED_0_UPDATE_INTERVAL 0x4000B810\r
+#define MMCR_LED_0_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_0_UPDATE_INTERVAL))\r
+\r
+/***************************************************************\r
+* SMSC BC-Link Master\r
+***************************************************************/\r
+#define ADDR_BC_LINK_STATUS 0x4000BC00\r
+#define MMCR_BC_LINK_STATUS (*(VUINT8 *)(ADDR_BC_LINK_STATUS))\r
+\r
+#define ADDR_BC_LINK_ADDRESS 0x4000BC04\r
+#define MMCR_BC_LINK_ADDRESS (*(VUINT8 *)(ADDR_BC_LINK_ADDRESS))\r
+\r
+#define ADDR_BC_LINK_DATA 0x4000BC08\r
+#define MMCR_BC_LINK_DATA (*(VUINT8 *)(ADDR_BC_LINK_DATA))\r
+\r
+#define ADDR_BC_LINK_CLOCK_SELECT 0x4000BC0C\r
+#define MMCR_BC_LINK_CLOCK_SELECT (*(VUINT8 *)(ADDR_BC_LINK_CLOCK_SELECT))\r
+\r
+/***************************************************************\r
+* Basic Timer\r
+***************************************************************/\r
+#define ADDR_BASIC_0_TIMER_COUNT 0x40000C00\r
+#define MMCR_BASIC_0_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_0_TIMER_COUNT))\r
+\r
+#define ADDR_BASIC_0_TIMER_PRELOAD 0x40000C04\r
+#define MMCR_BASIC_0_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_0_TIMER_PRELOAD))\r
+\r
+#define ADDR_BASIC_0_TIMER_STATUS 0x40000C08\r
+#define MMCR_BASIC_0_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_0_TIMER_STATUS))\r
+\r
+#define ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE 0x40000C0C\r
+#define MMCR_BASIC_0_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_BASIC_0_TIMER_CONTROL 0x40000C10\r
+#define MMCR_BASIC_0_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_0_TIMER_CONTROL))\r
+\r
+#define ADDR_BASIC_1_TIMER_COUNT 0x40000C20\r
+#define MMCR_BASIC_1_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_1_TIMER_COUNT))\r
+\r
+#define ADDR_BASIC_1_TIMER_PRELOAD 0x40000C24\r
+#define MMCR_BASIC_1_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_1_TIMER_PRELOAD))\r
+\r
+#define ADDR_BASIC_1_TIMER_STATUS 0x40000C28\r
+#define MMCR_BASIC_1_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_1_TIMER_STATUS))\r
+\r
+#define ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE 0x40000C2C\r
+#define MMCR_BASIC_1_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_BASIC_1_TIMER_CONTROL 0x40000C30\r
+#define MMCR_BASIC_1_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_1_TIMER_CONTROL))\r
+\r
+#define ADDR_BASIC_2_TIMER_COUNT 0x40000C40\r
+#define MMCR_BASIC_2_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_2_TIMER_COUNT))\r
+\r
+#define ADDR_BASIC_2_TIMER_PRELOAD 0x40000C44\r
+#define MMCR_BASIC_2_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_2_TIMER_PRELOAD))\r
+\r
+#define ADDR_BASIC_2_TIMER_STATUS 0x40000C48\r
+#define MMCR_BASIC_2_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_2_TIMER_STATUS))\r
+\r
+#define ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE 0x40000C4C\r
+#define MMCR_BASIC_2_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_BASIC_2_TIMER_CONTROL 0x40000C50\r
+#define MMCR_BASIC_2_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_2_TIMER_CONTROL))\r
+\r
+#define ADDR_BASIC_3_TIMER_COUNT 0x40000C60\r
+#define MMCR_BASIC_3_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_3_TIMER_COUNT))\r
+\r
+#define ADDR_BASIC_3_TIMER_PRELOAD 0x40000C64\r
+#define MMCR_BASIC_3_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_3_TIMER_PRELOAD))\r
+\r
+#define ADDR_BASIC_3_TIMER_STATUS 0x40000C68\r
+#define MMCR_BASIC_3_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_3_TIMER_STATUS))\r
+\r
+#define ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE 0x40000C6C\r
+#define MMCR_BASIC_3_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_BASIC_3_TIMER_CONTROL 0x40000C70\r
+#define MMCR_BASIC_3_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_3_TIMER_CONTROL))\r
+\r
+#define ADDR_BASIC_4_TIMER_COUNT 0x40000C80\r
+#define MMCR_BASIC_4_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_4_TIMER_COUNT))\r
+\r
+#define ADDR_BASIC_4_TIMER_PRELOAD 0x40000C84\r
+#define MMCR_BASIC_4_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_4_TIMER_PRELOAD))\r
+\r
+#define ADDR_BASIC_4_TIMER_STATUS 0x40000C88\r
+#define MMCR_BASIC_4_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_4_TIMER_STATUS))\r
+\r
+#define ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE 0x40000C8C\r
+#define MMCR_BASIC_4_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_BASIC_4_TIMER_CONTROL 0x40000C90\r
+#define MMCR_BASIC_4_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_4_TIMER_CONTROL))\r
+\r
+#define ADDR_BASIC_5_TIMER_COUNT 0x40000CA0\r
+#define MMCR_BASIC_5_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_5_TIMER_COUNT))\r
+\r
+#define ADDR_BASIC_5_TIMER_PRELOAD 0x40000CA4\r
+#define MMCR_BASIC_5_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_5_TIMER_PRELOAD))\r
+\r
+#define ADDR_BASIC_5_TIMER_STATUS 0x40000CA8\r
+#define MMCR_BASIC_5_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_5_TIMER_STATUS))\r
+\r
+#define ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE 0x40000CAC\r
+#define MMCR_BASIC_5_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_BASIC_5_TIMER_CONTROL 0x40000CB0\r
+#define MMCR_BASIC_5_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_5_TIMER_CONTROL))\r
+\r
+/***************************************************************\r
+* INTS\r
+***************************************************************/\r
+#define ADDR_EC_GIRQ8_SOURCE 0x4000C000\r
+#define MMCR_EC_GIRQ8_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ8_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ8_ENABLE_SET 0x4000C004\r
+#define MMCR_EC_GIRQ8_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ8_RESULT 0x4000C008\r
+#define MMCR_EC_GIRQ8_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ8_RESULT))\r
+\r
+#define ADDR_EC_GIRQ8_ENABLE_CLEAR 0x4000C00C\r
+#define MMCR_EC_GIRQ8_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ9_SOURCE 0x4000C014\r
+#define MMCR_EC_GIRQ9_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ9_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ9_ENABLE_SET 0x4000C018\r
+#define MMCR_EC_GIRQ9_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ9_RESULT 0x4000C01C\r
+#define MMCR_EC_GIRQ9_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ9_RESULT))\r
+\r
+#define ADDR_EC_GIRQ9_ENABLE_CLEAR 0x4000C020\r
+#define MMCR_EC_GIRQ9_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ10_SOURCE 0x4000C028\r
+#define MMCR_EC_GIRQ10_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ10_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ10_ENABLE_SET 0x4000C02C\r
+#define MMCR_EC_GIRQ10_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ10_RESULT 0x4000C030\r
+#define MMCR_EC_GIRQ10_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ10_RESULT))\r
+\r
+#define ADDR_EC_GIRQ10_ENABLE_CLEAR 0x4000C034\r
+#define MMCR_EC_GIRQ10_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ11_SOURCE 0x4000C03C\r
+#define MMCR_EC_GIRQ11_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ11_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ11_ENABLE_SET 0x4000C040\r
+#define MMCR_EC_GIRQ11_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ11_RESULT 0x4000C044\r
+#define MMCR_EC_GIRQ11_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ11_RESULT))\r
+\r
+#define ADDR_EC_GIRQ11_ENABLE_CLEAR 0x4000C048\r
+#define MMCR_EC_GIRQ11_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ12_SOURCE 0x4000C050\r
+#define MMCR_EC_GIRQ12_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ12_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ12_ENABLE_SET 0x4000C054\r
+#define MMCR_EC_GIRQ12_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ12_RESULT 0x4000C058\r
+#define MMCR_EC_GIRQ12_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ12_RESULT))\r
+\r
+#define ADDR_EC_GIRQ12_ENABLE_CLEAR 0x4000C05C\r
+#define MMCR_EC_GIRQ12_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ13_SOURCE 0x4000C064\r
+#define MMCR_EC_GIRQ13_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ13_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ13_ENABLE_SET 0x4000C068\r
+#define MMCR_EC_GIRQ13_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ13_RESULT 0x4000C06C\r
+#define MMCR_EC_GIRQ13_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ13_RESULT))\r
+\r
+#define ADDR_EC_GIRQ13_ENABLE_CLEAR 0x4000C070\r
+#define MMCR_EC_GIRQ13_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ14_SOURCE 0x4000C078\r
+#define MMCR_EC_GIRQ14_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ14_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ14_ENABLE_SET 0x4000C07C\r
+#define MMCR_EC_GIRQ14_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ14_RESULT 0x4000C080\r
+#define MMCR_EC_GIRQ14_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ14_RESULT))\r
+\r
+#define ADDR_EC_GIRQ14_ENABLE_CLEAR 0x4000C084\r
+#define MMCR_EC_GIRQ14_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ15_SOURCE 0x4000C08C\r
+#define MMCR_EC_GIRQ15_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ15_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ15_ENABLE_SET 0x4000C090\r
+#define MMCR_EC_GIRQ15_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ15_RESULT 0x4000C094\r
+#define MMCR_EC_GIRQ15_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ15_RESULT))\r
+\r
+#define ADDR_EC_GIRQ15_ENABLE_CLEAR 0x4000C098\r
+#define MMCR_EC_GIRQ15_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ16_SOURCE 0x4000C0A0\r
+#define MMCR_EC_GIRQ16_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ16_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ16_ENABLE_SET 0x4000C0A4\r
+#define MMCR_EC_GIRQ16_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ16_RESULT 0x4000C0A8\r
+#define MMCR_EC_GIRQ16_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ16_RESULT))\r
+\r
+#define ADDR_EC_GIRQ16_ENABLE_CLEAR 0x4000C0AC\r
+#define MMCR_EC_GIRQ16_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ17_SOURCE 0x4000C0B4\r
+#define MMCR_EC_GIRQ17_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ17_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ17_ENABLE_SET 0x4000C0B8\r
+#define MMCR_EC_GIRQ17_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ17_RESULT 0x4000C0BC\r
+#define MMCR_EC_GIRQ17_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ17_RESULT))\r
+\r
+#define ADDR_EC_GIRQ17_ENABLE_CLEAR 0x4000C0C0\r
+#define MMCR_EC_GIRQ17_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ18_SOURCE 0x4000C0C8\r
+#define MMCR_EC_GIRQ18_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ18_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ18_ENABLE_SET 0x4000C0CC\r
+#define MMCR_EC_GIRQ18_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ18_RESULT 0x4000C0D0\r
+#define MMCR_EC_GIRQ18_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ18_RESULT))\r
+\r
+#define ADDR_EC_GIRQ18_ENABLE_CLEAR 0x4000C0D4\r
+#define MMCR_EC_GIRQ18_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ19_SOURCE 0x4000C0DC\r
+#define MMCR_EC_GIRQ19_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ19_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ19_ENABLE_SET 0x4000C0E0\r
+#define MMCR_EC_GIRQ19_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ19_RESULT 0x4000C0E4\r
+#define MMCR_EC_GIRQ19_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ19_RESULT))\r
+\r
+#define ADDR_EC_GIRQ19_ENABLE_CLEAR 0x4000C0E8\r
+#define MMCR_EC_GIRQ19_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ20_SOURCE 0x4000C0F0\r
+#define MMCR_EC_GIRQ20_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ20_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ20_ENABLE_SET 0x4000C0F4\r
+#define MMCR_EC_GIRQ20_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ20_RESULT 0x4000C0F8\r
+#define MMCR_EC_GIRQ20_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ20_RESULT))\r
+\r
+#define ADDR_EC_GIRQ20_ENABLE_CLEAR 0x4000C0FC\r
+#define MMCR_EC_GIRQ20_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ21_SOURCE 0x4000C104\r
+#define MMCR_EC_GIRQ21_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ21_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ21_ENABLE_SET 0x4000C108\r
+#define MMCR_EC_GIRQ21_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ21_RESULT 0x4000C10C\r
+#define MMCR_EC_GIRQ21_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ21_RESULT))\r
+\r
+#define ADDR_EC_GIRQ21_ENABLE_CLEAR 0x4000C110\r
+#define MMCR_EC_GIRQ21_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ22_SOURCE 0x4000C118\r
+#define MMCR_EC_GIRQ22_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ22_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ22_ENABLE_SET 0x4000C11C\r
+#define MMCR_EC_GIRQ22_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ22_RESULT 0x4000C120\r
+#define MMCR_EC_GIRQ22_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ22_RESULT))\r
+\r
+#define ADDR_EC_GIRQ22_ENABLE_CLEAR 0x4000C124\r
+#define MMCR_EC_GIRQ22_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_GIRQ23_SOURCE 0x4000C12C\r
+#define MMCR_EC_GIRQ23_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ23_SOURCE))\r
+\r
+#define ADDR_EC_GIRQ23_ENABLE_SET 0x4000C130\r
+#define MMCR_EC_GIRQ23_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_SET))\r
+\r
+#define ADDR_EC_GIRQ23_RESULT 0x4000C134\r
+#define MMCR_EC_GIRQ23_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ23_RESULT))\r
+\r
+#define ADDR_EC_GIRQ23_ENABLE_CLEAR 0x4000C138\r
+#define MMCR_EC_GIRQ23_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_BLOCK_ENABLE_SET 0x4000C200\r
+#define MMCR_EC_BLOCK_ENABLE_SET (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_SET))\r
+\r
+#define ADDR_EC_BLOCK_ENABLE_CLEAR 0x4000C204\r
+#define MMCR_EC_BLOCK_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_CLEAR))\r
+\r
+#define ADDR_EC_BLOCK_IRQ_VECTOR 0x4000C208\r
+#define MMCR_EC_BLOCK_IRQ_VECTOR (*(VUINT32 *)(ADDR_EC_BLOCK_IRQ_VECTOR))\r
+\r
+/***************************************************************\r
+* RPM Fan Control\r
+***************************************************************/\r
+#define ADDR_RPM_FAN_SETTING 0x4000A000\r
+#define MMCR_RPM_FAN_SETTING (*(VUINT8 *)(ADDR_RPM_FAN_SETTING))\r
+\r
+#define ADDR_RPM_PWM_DIVIDE 0x4000A001\r
+#define MMCR_RPM_PWM_DIVIDE (*(VUINT8 *)(ADDR_RPM_PWM_DIVIDE))\r
+\r
+#define ADDR_RPM_FAN_CONFIGURATION_1 0x4000A002\r
+#define MMCR_RPM_FAN_CONFIGURATION_1 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_1))\r
+\r
+#define ADDR_RPM_FAN_CONFIGURATION_2 0x4000A003\r
+#define MMCR_RPM_FAN_CONFIGURATION_2 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_2))\r
+\r
+#define ADDR_RPM_GAIN 0x4000A005\r
+#define MMCR_RPM_GAIN (*(VUINT8 *)(ADDR_RPM_GAIN))\r
+\r
+#define ADDR_RPM_FAN_SPIN_UP_CONFIGURATION 0x4000A006\r
+#define MMCR_RPM_FAN_SPIN_UP_CONFIGURATION (*(VUINT8 *)(ADDR_RPM_FAN_SPIN_UP_CONFIGURATION))\r
+\r
+#define ADDR_RPM_FAN_STEP 0x4000A007\r
+#define MMCR_RPM_FAN_STEP (*(VUINT8 *)(ADDR_RPM_FAN_STEP))\r
+\r
+#define ADDR_RPM_FAN_MINIMUM_DRIVE 0x4000A008\r
+#define MMCR_RPM_FAN_MINIMUM_DRIVE (*(VUINT8 *)(ADDR_RPM_FAN_MINIMUM_DRIVE))\r
+\r
+#define ADDR_RPM_VALID_TACH_COUNT 0x4000A009\r
+#define MMCR_RPM_VALID_TACH_COUNT (*(VUINT8 *)(ADDR_RPM_VALID_TACH_COUNT))\r
+\r
+#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE 0x4000A00A\r
+#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE))\r
+\r
+#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE 0x4000A00B\r
+#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE))\r
+\r
+#define ADDR_RPM_TACH_TARGET_LOW_BYTE 0x4000A00C\r
+#define MMCR_RPM_TACH_TARGET_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_LOW_BYTE))\r
+\r
+#define ADDR_RPM_TACH_TARGET_HIGH_BYTE 0x4000A00D\r
+#define MMCR_RPM_TACH_TARGET_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_HIGH_BYTE))\r
+\r
+#define ADDR_RPM_TACH_READING_LOW_BYTE 0x4000A00E\r
+#define MMCR_RPM_TACH_READING_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_LOW_BYTE))\r
+\r
+#define ADDR_RPM_TACH_READING_HIGH_BYTE 0x4000A00F\r
+#define MMCR_RPM_TACH_READING_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_HIGH_BYTE))\r
+\r
+#define ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY 0x4000A010\r
+#define MMCR_RPM_PWM_DRIVER_BASE_FREQUENCY (*(VUINT8 *)(ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY))\r
+\r
+#define ADDR_RPM_FAN_STATUS 0x4000A011\r
+#define MMCR_RPM_FAN_STATUS (*(VUINT8 *)(ADDR_RPM_FAN_STATUS))\r
+\r
+#define ADDR_RPM_FAN_TEST 0x4000A014\r
+#define MMCR_RPM_FAN_TEST (*(VUINT8 *)(ADDR_RPM_FAN_TEST))\r
+\r
+#define ADDR_RPM_FAN_TEST1 0x4000A015\r
+#define MMCR_RPM_FAN_TEST1 (*(VUINT8 *)(ADDR_RPM_FAN_TEST1))\r
+\r
+#define ADDR_RPM_FAN_TEST2 0x4000A016\r
+#define MMCR_RPM_FAN_TEST2 (*(VUINT8 *)(ADDR_RPM_FAN_TEST2))\r
+\r
+#define ADDR_RPM_FAN_TEST3 0x4000A017\r
+#define MMCR_RPM_FAN_TEST3 (*(VUINT8 *)(ADDR_RPM_FAN_TEST3))\r
+\r
+/***************************************************************\r
+* V2P (HP ckt#1) 32bit_aligned\r
+***************************************************************/\r
+#define ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY 0x40007C80\r
+#define MMCR_V2P_ADC2PWM_OUTPUT_FREQUENCY (*(VUINT32 *)(ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY))\r
+\r
+#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW 0x40007C84\r
+#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW))\r
+\r
+#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH 0x40007C88\r
+#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH))\r
+\r
+#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA 0x40007C8C\r
+#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA))\r
+\r
+#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS 0x40007C90\r
+#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_STATUS (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS))\r
+\r
+#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 0x40007C94\r
+#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1))\r
+\r
+#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 0x40007C98\r
+#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2))\r
+\r
+#define ADDR_V2P_ADC2PWM_CONTROL 0x40007C9C\r
+#define MMCR_V2P_ADC2PWM_CONTROL (*(VUINT32 *)(ADDR_V2P_ADC2PWM_CONTROL))\r
+\r
+#define ADDR_V2P_LPF_CUT_OFF_FREQUENCY 0x40007CA0\r
+#define MMCR_V2P_LPF_CUT_OFF_FREQUENCY (*(VUINT32 *)(ADDR_V2P_LPF_CUT_OFF_FREQUENCY))\r
+\r
+#define ADDR_V2P_TEST 0x40007CA4\r
+#define MMCR_V2P_TEST (*(VUINT32 *)(ADDR_V2P_TEST))\r
+\r
+#define ADDR_V2P_NOTICE_DATA 0x40007CA8\r
+#define MMCR_V2P_NOTICE_DATA (*(VUINT32 *)(ADDR_V2P_NOTICE_DATA))\r
+\r
+#define ADDR_V2P_TEST_DATA 0x40007CAC\r
+#define MMCR_V2P_TEST_DATA (*(VUINT32 *)(ADDR_V2P_TEST_DATA))\r
+\r
+#define ADDR_V2P_COUNTER_START 0x40007CB0\r
+#define MMCR_V2P_COUNTER_START (*(VUINT32 *)(ADDR_V2P_COUNTER_START))\r
+\r
+#define ADDR_V2P_HYSTERESIS 0x40007CB4\r
+#define MMCR_V2P_HYSTERESIS (*(VUINT32 *)(ADDR_V2P_HYSTERESIS))\r
+\r
+#define ADDR_V2P_BIAS 0x40007CB8\r
+#define MMCR_V2P_BIAS (*(VUINT32 *)(ADDR_V2P_BIAS))\r
+\r
+#define ADDR_V2P_INTERRUPT_CONTROL 0x40007CBC\r
+#define MMCR_V2P_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_V2P_INTERRUPT_CONTROL))\r
+\r
+/***************************************************************\r
+* VBAT_REGS (1322)\r
+***************************************************************/\r
+#define ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS 0x4000A400\r
+#define MMCR_VBAT_POWER_FAIL_AND_RESET_STATUS (*(VUINT8 *)(ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS))\r
+\r
+#define ADDR_VBAT_CONTROL 0x4000A404\r
+#define MMCR_VBAT_CONTROL (*(VUINT8 *)(ADDR_VBAT_CONTROL))\r
+\r
+#define ADDR_VBAT_CLOCK_ENABLE 0x4000A408\r
+#define MMCR_VBAT_CLOCK_ENABLE (*(VUINT8 *)(ADDR_VBAT_CLOCK_ENABLE))\r
+\r
+/***************************************************************\r
+* EC_REG_BANK (1322)\r
+***************************************************************/\r
+#define ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS 0x4000FC04\r
+#define MMCR_EC_REG_BANK_AHB_ERROR_ADDRESS (*(VUINT32 *)(ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS))\r
+\r
+#define ADDR_EC_REG_BANK_INPUT_MUX0 0x4000FC08\r
+#define MMCR_EC_REG_BANK_INPUT_MUX0 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX0))\r
+\r
+#define ADDR_EC_REG_BANK_INPUT_MUX1 0x4000FC0C\r
+#define MMCR_EC_REG_BANK_INPUT_MUX1 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX1))\r
+\r
+#define ADDR_EC_REG_BANK_ID 0x4000FC10\r
+#define MMCR_EC_REG_BANK_ID (*(VUINT8 *)(ADDR_EC_REG_BANK_ID))\r
+\r
+#define ADDR_EC_REG_BANK_AHB_ERROR_CONTROL 0x4000FC14\r
+#define MMCR_EC_REG_BANK_AHB_ERROR_CONTROL (*(VUINT8 *)(ADDR_EC_REG_BANK_AHB_ERROR_CONTROL))\r
+\r
+#define ADDR_EC_REG_BANK_INTERRUPT_CONTROL 0x4000FC18\r
+#define MMCR_EC_REG_BANK_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_INTERRUPT_CONTROL))\r
+\r
+#define ADDR_EC_REG_BANK_ETM_TRACE 0x4000FC1C\r
+#define MMCR_EC_REG_BANK_ETM_TRACE (*(VUINT32 *)(ADDR_EC_REG_BANK_ETM_TRACE))\r
+\r
+#define ADDR_EC_REG_BANK_JTAG_ENABLE 0x4000FC20\r
+#define MMCR_EC_REG_BANK_JTAG_ENABLE (*(VUINT32 *)(ADDR_EC_REG_BANK_JTAG_ENABLE))\r
+\r
+#define ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK 0x4000FC24\r
+#define MMCR_EC_REG_BANK_PRIVATE_KEY_LOCK (*(VUINT32 *)(ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK))\r
+\r
+#define ADDR_EC_REG_BANK_WDT_COUNT 0x4000FC28\r
+#define MMCR_EC_REG_BANK_WDT_COUNT (*(VUINT32 *)(ADDR_EC_REG_BANK_WDT_COUNT))\r
+\r
+#define ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL 0x4000FC2C\r
+#define MMCR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL))\r
+\r
+#define ADDR_EC_REG_BANK_ADC_VREF_TRIM 0x4000FC30\r
+#define MMCR_EC_REG_BANK_ADC_VREF_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_TRIM))\r
+\r
+#define ADDR_EC_REG_BANK_REGULATOR_TRIM 0x4000FC34\r
+#define MMCR_EC_REG_BANK_REGULATOR_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_REGULATOR_TRIM))\r
+\r
+#define ADDR_EC_REG_BANK_ADC_VREF_PD 0x4000FC38\r
+#define MMCR_EC_REG_BANK_ADC_VREF_PD (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_PD))\r
+\r
+#define ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST 0x4000FC3C\r
+#define MMCR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST))\r
+\r
+#define ADDR_EC_REG_BANK_MISC_TRIM 0x4000FC40\r
+#define MMCR_EC_REG_BANK_MISC_TRIM (*(VUINT8 *)(ADDR_EC_REG_BANK_MISC_TRIM))\r
+\r
+/***************************************************************\r
+* PCR\r
+***************************************************************/\r
+#define ADDR_PCR_CHIP_SLEEP_ENABLE 0x40080100\r
+#define MMCR_PCR_CHIP_SLEEP_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_SLEEP_ENABLE))\r
+\r
+#define ADDR_PCR_CHIP_CLOCK_REQUIRED 0x40080104\r
+#define MMCR_PCR_CHIP_CLOCK_REQUIRED (*(VUINT32 *)(ADDR_PCR_CHIP_CLOCK_REQUIRED))\r
+\r
+#define ADDR_PCR_EC_SLEEP_ENABLES 0x40080108\r
+#define MMCR_PCR_EC_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLES))\r
+\r
+#define ADDR_PCR_EC_CLOCK_REQUIRED_STATUS 0x4008010C\r
+#define MMCR_PCR_EC_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_STATUS))\r
+\r
+#define ADDR_PCR_HOST_SLEEP_ENABLES 0x40080110\r
+#define MMCR_PCR_HOST_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_HOST_SLEEP_ENABLES))\r
+\r
+#define ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS 0x40080114\r
+#define MMCR_PCR_HOST_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS))\r
+\r
+#define ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 0x40080118\r
+#define MMCR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 (*(VUINT32 *)(ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0))\r
+\r
+#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120\r
+#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))\r
+\r
+#define ADDR_PCR_EC_SLEEP_ENABLE_2 0x40080124\r
+#define MMCR_PCR_EC_SLEEP_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLE_2))\r
+\r
+#define ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS 0x40080128\r
+#define MMCR_PCR_EC_CLOCK_REQUIRED_2_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS))\r
+\r
+#define ADDR_PCR_SLOW_CLOCK_CONTROL 0x4008012C\r
+#define MMCR_PCR_SLOW_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_SLOW_CLOCK_CONTROL))\r
+\r
+#define ADDR_PCR_OSCILLATOR_ID 0x40080130\r
+#define MMCR_PCR_OSCILLATOR_ID (*(VUINT32 *)(ADDR_PCR_OSCILLATOR_ID))\r
+\r
+#define ADDR_PCR_CHIP_RESET_ENABLE 0x40080138\r
+#define MMCR_PCR_CHIP_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_RESET_ENABLE))\r
+\r
+#define ADDR_PCR_HOST_RESET_ENABLE 0x4008013C\r
+#define MMCR_PCR_HOST_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_HOST_RESET_ENABLE))\r
+\r
+#define ADDR_PCR_EC_RESET_ENABLE 0x40080140\r
+#define MMCR_PCR_EC_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE))\r
+\r
+#define ADDR_PCR_EC_RESET_ENABLE_2 0x40080144\r
+#define MMCR_PCR_EC_RESET_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE_2))\r
+\r
+#define ADDR_PCR_CLOCK_RESET_CONTROL 0x40080148\r
+#define MMCR_PCR_CLOCK_RESET_CONTROL (*(VUINT32 *)(ADDR_PCR_CLOCK_RESET_CONTROL))\r
+\r
+/***************************************************************\r
+* Public Key Crypto Engine\r
+***************************************************************/\r
+#define ADDR_PUBLIC_PK_CONFIGREG 0x4000BD00\r
+#define MMCR_PUBLIC_PK_CONFIGREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONFIGREG))\r
+\r
+#define ADDR_PUBLIC_PK_COMMANDREG 0x4000BD04\r
+#define MMCR_PUBLIC_PK_COMMANDREG (*(VUINT32 *)(ADDR_PUBLIC_PK_COMMANDREG))\r
+\r
+#define ADDR_PUBLIC_PK_CONTROLREG 0x4000BD08\r
+#define MMCR_PUBLIC_PK_CONTROLREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONTROLREG))\r
+\r
+#define ADDR_PUBLIC_PK_STATUSREG 0x4000BD0C\r
+#define MMCR_PUBLIC_PK_STATUSREG (*(VUINT32 *)(ADDR_PUBLIC_PK_STATUSREG))\r
+\r
+#define ADDR_PUBLIC_PK_VERSIONREG 0x4000BD10\r
+#define MMCR_PUBLIC_PK_VERSIONREG (*(VUINT32 *)(ADDR_PUBLIC_PK_VERSIONREG))\r
+\r
+#define ADDR_PUBLIC_PK_LOADMICROCODEREG 0x4000BD14\r
+#define MMCR_PUBLIC_PK_LOADMICROCODEREG (*(VUINT32 *)(ADDR_PUBLIC_PK_LOADMICROCODEREG))\r
+\r
+/***************************************************************\r
+* Non Deterministic Random Number Generator\r
+***************************************************************/\r
+#define ADDR_NON_CONTROLREG 0x4000BE00\r
+#define MMCR_NON_CONTROLREG (*(VUINT32 *)(ADDR_NON_CONTROLREG))\r
+\r
+#define ADDR_NON_FIFOLEVELREG 0x4000BE04\r
+#define MMCR_NON_FIFOLEVELREG (*(VUINT32 *)(ADDR_NON_FIFOLEVELREG))\r
+\r
+#define ADDR_NON_VERSIONREG 0x4000BE08\r
+#define MMCR_NON_VERSIONREG (*(VUINT32 *)(ADDR_NON_VERSIONREG))\r
+\r
+/***************************************************************\r
+* RTC\r
+***************************************************************/\r
+#define ADDR_RTC_SECONDS 0x400F2800\r
+#define MMCR_RTC_SECONDS (*(VUINT8 *)(ADDR_RTC_SECONDS))\r
+\r
+#define ADDR_RTC_SECONDS_ALARM 0x400F2801\r
+#define MMCR_RTC_SECONDS_ALARM (*(VUINT8 *)(ADDR_RTC_SECONDS_ALARM))\r
+\r
+#define ADDR_RTC_MINUTES 0x400F2802\r
+#define MMCR_RTC_MINUTES (*(VUINT8 *)(ADDR_RTC_MINUTES))\r
+\r
+#define ADDR_RTC_MINUTES_ALARM 0x400F2803\r
+#define MMCR_RTC_MINUTES_ALARM (*(VUINT8 *)(ADDR_RTC_MINUTES_ALARM))\r
+\r
+#define ADDR_RTC_HOURS 0x400F2804\r
+#define MMCR_RTC_HOURS (*(VUINT8 *)(ADDR_RTC_HOURS))\r
+\r
+#define ADDR_RTC_HOURS_ALARM 0x400F2805\r
+#define MMCR_RTC_HOURS_ALARM (*(VUINT8 *)(ADDR_RTC_HOURS_ALARM))\r
+\r
+#define ADDR_RTC_DAY_OF_WEEK 0x400F2806\r
+#define MMCR_RTC_DAY_OF_WEEK (*(VUINT8 *)(ADDR_RTC_DAY_OF_WEEK))\r
+\r
+#define ADDR_RTC_DAY_OF_MONTH 0x400F2807\r
+#define MMCR_RTC_DAY_OF_MONTH (*(VUINT8 *)(ADDR_RTC_DAY_OF_MONTH))\r
+\r
+#define ADDR_RTC_MONTH 0x400F2808\r
+#define MMCR_RTC_MONTH (*(VUINT8 *)(ADDR_RTC_MONTH))\r
+\r
+#define ADDR_RTC_YEAR 0x400F2809\r
+#define MMCR_RTC_YEAR (*(VUINT8 *)(ADDR_RTC_YEAR))\r
+\r
+#define ADDR_RTC_A 0x400F280A\r
+#define MMCR_RTC_A (*(VUINT8 *)(ADDR_RTC_A))\r
+\r
+#define ADDR_RTC_B 0x400F280B\r
+#define MMCR_RTC_B (*(VUINT8 *)(ADDR_RTC_B))\r
+\r
+#define ADDR_RTC_C 0x400F280C\r
+#define MMCR_RTC_C (*(VUINT8 *)(ADDR_RTC_C))\r
+\r
+#define ADDR_RTC_D 0x400F280D\r
+#define MMCR_RTC_D (*(VUINT8 *)(ADDR_RTC_D))\r
+\r
+#define ADDR_RTC_CONTROL 0x400F2810\r
+#define MMCR_RTC_CONTROL (*(VUINT8 *)(ADDR_RTC_CONTROL))\r
+\r
+#define ADDR_RTC_WEEK_ALARM 0x400F2814\r
+#define MMCR_RTC_WEEK_ALARM (*(VUINT8 *)(ADDR_RTC_WEEK_ALARM))\r
+\r
+#define ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD 0x400F2818\r
+#define MMCR_RTC_DAYLIGHT_SAVINGS_FORWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD))\r
+\r
+#define ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD 0x400F281C\r
+#define MMCR_RTC_DAYLIGHT_SAVINGS_BACKWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD))\r
+\r
+#define ADDR_RTC_TEST_MODE 0x400F2820\r
+#define MMCR_RTC_TEST_MODE (*(VUINT8 *)(ADDR_RTC_TEST_MODE))\r
+\r
+/***************************************************************\r
+* Analog to Digital Converter (ADC)\r
+***************************************************************/\r
+#define ADDR_ADC_CONTROL 0x40007C00\r
+#define MMCR_ADC_CONTROL (*(VUINT32 *)(ADDR_ADC_CONTROL))\r
+\r
+#define ADDR_ADC_DELAY 0x40007C04\r
+#define MMCR_ADC_DELAY (*(VUINT32 *)(ADDR_ADC_DELAY))\r
+\r
+#define ADDR_ADC_STATUS 0x40007C08\r
+#define MMCR_ADC_STATUS (*(VUINT32 *)(ADDR_ADC_STATUS))\r
+\r
+#define ADDR_ADC_SINGLE 0x40007C0C\r
+#define MMCR_ADC_SINGLE (*(VUINT32 *)(ADDR_ADC_SINGLE))\r
+\r
+#define ADDR_ADC_REPEAT 0x40007C10\r
+#define MMCR_ADC_REPEAT (*(VUINT32 *)(ADDR_ADC_REPEAT))\r
+\r
+#define ADDR_ADC_CHANNEL_0_READINGS 0x40007C14\r
+#define MMCR_ADC_CHANNEL_0_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_0_READINGS))\r
+\r
+#define ADDR_ADC_CHANNEL_1_READINGS 0x40007C18\r
+#define MMCR_ADC_CHANNEL_1_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_1_READINGS))\r
+\r
+#define ADDR_ADC_CHANNEL_2_READINGS 0x40007C1C\r
+#define MMCR_ADC_CHANNEL_2_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_2_READINGS))\r
+\r
+#define ADDR_ADC_CHANNEL_3_READINGS 0x40007C20\r
+#define MMCR_ADC_CHANNEL_3_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_3_READINGS))\r
+\r
+#define ADDR_ADC_CHANNEL_4_READINGS 0x40007C24\r
+#define MMCR_ADC_CHANNEL_4_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_4_READINGS))\r
+\r
+#define ADDR_ADC_DEBUG_FPGA_TEST_MODE 0x40007C54\r
+#define MMCR_ADC_DEBUG_FPGA_TEST_MODE (*(VUINT32 *)(ADDR_ADC_DEBUG_FPGA_TEST_MODE))\r
+\r
+#define ADDR_ADC_TEST 0x40007C78\r
+#define MMCR_ADC_TEST (*(VUINT32 *)(ADDR_ADC_TEST))\r
+\r
+#define ADDR_ADC_CONFIGURATION 0x40007C7C\r
+#define MMCR_ADC_CONFIGURATION (*(VUINT32 *)(ADDR_ADC_CONFIGURATION))\r
+\r
+/***************************************************************\r
+* eFUSE\r
+***************************************************************/\r
+#define ADDR_EFUSE_CONTROL 0x40082000\r
+#define MMCR_EFUSE_CONTROL (*(VUINT8 *)(ADDR_EFUSE_CONTROL))\r
+\r
+#define ADDR_EFUSE_MANUAL_CONTROL 0x40082004\r
+#define MMCR_EFUSE_MANUAL_CONTROL (*(VUINT8 *)(ADDR_EFUSE_MANUAL_CONTROL))\r
+\r
+#define ADDR_EFUSE_MANUAL_MODE_ADDRESS 0x40082006\r
+#define MMCR_EFUSE_MANUAL_MODE_ADDRESS (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_ADDRESS))\r
+\r
+#define ADDR_EFUSE_MANUAL_MODE_DATA 0x4008200C\r
+#define MMCR_EFUSE_MANUAL_MODE_DATA (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_DATA))\r
+\r
+/***************************************************************\r
+* AES Crypto Engine & Hash Function\r
+***************************************************************/\r
+#define ADDR_AES_CONFIGREG 0x4000D200\r
+#define MMCR_AES_CONFIGREG (*(VUINT32 *)(ADDR_AES_CONFIGREG))\r
+\r
+#define ADDR_AES_COMMANDREG 0x4000D204\r
+#define MMCR_AES_COMMANDREG (*(VUINT32 *)(ADDR_AES_COMMANDREG))\r
+\r
+#define ADDR_AES_CONTROLREG 0x4000D208\r
+#define MMCR_AES_CONTROLREG (*(VUINT32 *)(ADDR_AES_CONTROLREG))\r
+\r
+#define ADDR_AES_STATUSREG 0x4000D20C\r
+#define MMCR_AES_STATUSREG (*(VUINT32 *)(ADDR_AES_STATUSREG))\r
+\r
+#define ADDR_AES_VERSIONREG 0x4000D210\r
+#define MMCR_AES_VERSIONREG (*(VUINT32 *)(ADDR_AES_VERSIONREG))\r
+\r
+#define ADDR_AES_NBHEADERREG 0x4000D214\r
+#define MMCR_AES_NBHEADERREG (*(VUINT32 *)(ADDR_AES_NBHEADERREG))\r
+\r
+#define ADDR_AES_LASTHEADERREG 0x4000D218\r
+#define MMCR_AES_LASTHEADERREG (*(VUINT32 *)(ADDR_AES_LASTHEADERREG))\r
+\r
+#define ADDR_AES_NBBLOCKREG 0x4000D21C\r
+#define MMCR_AES_NBBLOCKREG (*(VUINT32 *)(ADDR_AES_NBBLOCKREG))\r
+\r
+#define ADDR_AES_LASTBLOCKREG 0x4000D220\r
+#define MMCR_AES_LASTBLOCKREG (*(VUINT32 *)(ADDR_AES_LASTBLOCKREG))\r
+\r
+#define ADDR_AES_DMAINREG 0x4000D224\r
+#define MMCR_AES_DMAINREG (*(VUINT32 *)(ADDR_AES_DMAINREG))\r
+\r
+#define ADDR_AES_DMAOUTREG 0x4000D228\r
+#define MMCR_AES_DMAOUTREG (*(VUINT32 *)(ADDR_AES_DMAOUTREG))\r
+\r
+#define ADDR_AES_SHAMODE_REGISTER 0x4000D000\r
+#define MMCR_AES_SHAMODE_REGISTER (*(VUINT32 *)(ADDR_AES_SHAMODE_REGISTER))\r
+\r
+#define ADDR_AES_NBBLOCK_REGISTER 0x4000D004\r
+#define MMCR_AES_NBBLOCK_REGISTER (*(VUINT32 *)(ADDR_AES_NBBLOCK_REGISTER))\r
+\r
+#define ADDR_AES_CONTROL 0x4000D008\r
+#define MMCR_AES_CONTROL (*(VUINT32 *)(ADDR_AES_CONTROL))\r
+\r
+#define ADDR_AES_STATUS 0x4000D00C\r
+#define MMCR_AES_STATUS (*(VUINT32 *)(ADDR_AES_STATUS))\r
+\r
+#define ADDR_AES_VERSION 0x4000D010\r
+#define MMCR_AES_VERSION (*(VUINT32 *)(ADDR_AES_VERSION))\r
+\r
+#define ADDR_AES_GENERICVALUE_REGISTER 0x4000D014\r
+#define MMCR_AES_GENERICVALUE_REGISTER (*(VUINT32 *)(ADDR_AES_GENERICVALUE_REGISTER))\r
+\r
+#define ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS 0x4000D018\r
+#define MMCR_AES_INITIAL_HASH_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS))\r
+\r
+#define ADDR_AES_DATA_SOURCE_ADDRESS 0x4000D01C\r
+#define MMCR_AES_DATA_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_DATA_SOURCE_ADDRESS))\r
+\r
+#define ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS 0x4000D020\r
+#define MMCR_AES_HASH_RESULT_DESTINATION_ADDRESS (*(VUINT32 *)(ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS))\r
+\r
+/***************************************************************\r
+* LPC\r
+***************************************************************/\r
+#define ADDR_LPC_ACTIVATE 0x400F3330\r
+#define MMCR_LPC_ACTIVATE (*(VUINT8 *)(ADDR_LPC_ACTIVATE))\r
+\r
+#define ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION 0x400F3340\r
+#define MMCR_LPC_SIRQ0_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION 0x400F3341\r
+#define MMCR_LPC_SIRQ1_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION 0x400F3342\r
+#define MMCR_LPC_SIRQ2_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION 0x400F3343\r
+#define MMCR_LPC_SIRQ3_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION 0x400F3344\r
+#define MMCR_LPC_SIRQ4_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION 0x400F3345\r
+#define MMCR_LPC_SIRQ5_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION 0x400F3346\r
+#define MMCR_LPC_SIRQ6_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION 0x400F3347\r
+#define MMCR_LPC_SIRQ7_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION 0x400F3348\r
+#define MMCR_LPC_SIRQ8_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION 0x400F3349\r
+#define MMCR_LPC_SIRQ9_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION 0x400F334A\r
+#define MMCR_LPC_SIRQ10_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION 0x400F334B\r
+#define MMCR_LPC_SIRQ11_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION 0x400F334C\r
+#define MMCR_LPC_SIRQ12_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION 0x400F334D\r
+#define MMCR_LPC_SIRQ13_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION 0x400F334E\r
+#define MMCR_LPC_SIRQ14_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION 0x400F334F\r
+#define MMCR_LPC_SIRQ15_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION))\r
+\r
+#define ADDR_LPC_INTERFACE_BAR 0x400F3360\r
+#define MMCR_LPC_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_INTERFACE_BAR))\r
+\r
+#define ADDR_LPC_EM_INTERFACE_0_BAR 0x400F3364\r
+#define MMCR_LPC_EM_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_EM_INTERFACE_0_BAR))\r
+\r
+#define ADDR_LPC_UART_0_BAR 0x400F3368\r
+#define MMCR_LPC_UART_0_BAR (*(VUINT32 *)(ADDR_LPC_UART_0_BAR))\r
+\r
+#define ADDR_LPC_KEYBOARD_CONTROLLER_BAR 0x400F3378\r
+#define MMCR_LPC_KEYBOARD_CONTROLLER_BAR (*(VUINT32 *)(ADDR_LPC_KEYBOARD_CONTROLLER_BAR))\r
+\r
+#define ADDR_LPC_ACPI_EC_INTERFACE_0_BAR 0x400F3388\r
+#define MMCR_LPC_ACPI_EC_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_0_BAR))\r
+\r
+#define ADDR_LPC_ACPI_EC_INTERFACE_1_BAR 0x400F338C\r
+#define MMCR_LPC_ACPI_EC_INTERFACE_1_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_1_BAR))\r
+\r
+#define ADDR_LPC_ACPI_PM1_INTERFACE_BAR 0x400F3390\r
+#define MMCR_LPC_ACPI_PM1_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_PM1_INTERFACE_BAR))\r
+\r
+#define ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR 0x400F3394\r
+#define MMCR_LPC_LEGACY_GATEA20_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR))\r
+\r
+#define ADDR_LPC_MAILBOXS_INTERFACE_BAR 0x400F3398\r
+#define MMCR_LPC_MAILBOXS_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_MAILBOXS_INTERFACE_BAR))\r
+\r
+#define ADDR_LPC_BUS_MONITOR 0x400F3104\r
+#define MMCR_LPC_BUS_MONITOR (*(VUINT32 *)(ADDR_LPC_BUS_MONITOR))\r
+\r
+#define ADDR_LPC_HOST_BUS_ERROR 0x400F3108\r
+#define MMCR_LPC_HOST_BUS_ERROR (*(VUINT32 *)(ADDR_LPC_HOST_BUS_ERROR))\r
+\r
+#define ADDR_LPC_EC_SERIRQ 0x400F310C\r
+#define MMCR_LPC_EC_SERIRQ (*(VUINT32 *)(ADDR_LPC_EC_SERIRQ))\r
+\r
+#define ADDR_LPC_EC_CLOCK_CONTROL 0x400F3110\r
+#define MMCR_LPC_EC_CLOCK_CONTROL (*(VUINT32 *)(ADDR_LPC_EC_CLOCK_CONTROL))\r
+\r
+#define ADDR_LPC_BAR_INHIBIT 0x400F3120\r
+#define MMCR_LPC_BAR_INHIBIT (*(VUINT32 *)(ADDR_LPC_BAR_INHIBIT))\r
+\r
+#define ADDR_LPC_BAR_INIT 0x400F3130\r
+#define MMCR_LPC_BAR_INIT (*(VUINT16 *)(ADDR_LPC_BAR_INIT))\r
+\r
+#define ADDR_LPC_MEMORY_HOST_CONFIGURATION 0x400F31FC\r
+#define MMCR_LPC_MEMORY_HOST_CONFIGURATION (*(VUINT32 *)(ADDR_LPC_MEMORY_HOST_CONFIGURATION))\r
+\r
+/***************************************************************\r
+* GPIO\r
+***************************************************************/\r
+#define ADDR_GPIO000_PIN_CONTROL 0x40081000\r
+#define MMCR_GPIO000_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO001_PIN_CONTROL 0x40081004\r
+#define MMCR_GPIO001_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO002_PIN_CONTROL 0x40081008\r
+#define MMCR_GPIO002_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO003_PIN_CONTROL 0x4008100C\r
+#define MMCR_GPIO003_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO004_PIN_CONTROL 0x40081010\r
+#define MMCR_GPIO004_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO005_PIN_CONTROL 0x40081014\r
+#define MMCR_GPIO005_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO006_PIN_CONTROL 0x40081018\r
+#define MMCR_GPIO006_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO007_PIN_CONTROL 0x4008101C\r
+#define MMCR_GPIO007_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO010_PIN_CONTROL 0x40081020\r
+#define MMCR_GPIO010_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO011_PIN_CONTROL 0x40081024\r
+#define MMCR_GPIO011_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO012_PIN_CONTROL 0x40081028\r
+#define MMCR_GPIO012_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO013_PIN_CONTROL 0x4008102C\r
+#define MMCR_GPIO013_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO014_PIN_CONTROL 0x40081030\r
+#define MMCR_GPIO014_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO015_PIN_CONTROL 0x40081034\r
+#define MMCR_GPIO015_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO016_PIN_CONTROL 0x40081038\r
+#define MMCR_GPIO016_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO017_PIN_CONTROL 0x4008103C\r
+#define MMCR_GPIO017_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO020_PIN_CONTROL 0x40081040\r
+#define MMCR_GPIO020_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO021_PIN_CONTROL 0x40081044\r
+#define MMCR_GPIO021_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO022_PIN_CONTROL 0x40081048\r
+#define MMCR_GPIO022_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO023_PIN_CONTROL 0x4008104C\r
+#define MMCR_GPIO023_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO024_PIN_CONTROL 0x40081050\r
+#define MMCR_GPIO024_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO025_PIN_CONTROL 0x40081054\r
+#define MMCR_GPIO025_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO026_PIN_CONTROL 0x40081058\r
+#define MMCR_GPIO026_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO027_PIN_CONTROL 0x4008105C\r
+#define MMCR_GPIO027_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO030_PIN_CONTROL 0x40081060\r
+#define MMCR_GPIO030_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO031_PIN_CONTROL 0x40081064\r
+#define MMCR_GPIO031_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO032_PIN_CONTROL 0x40081068\r
+#define MMCR_GPIO032_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO033_PIN_CONTROL 0x4008106C\r
+#define MMCR_GPIO033_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO034_PIN_CONTROL 0x40081070\r
+#define MMCR_GPIO034_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO035_PIN_CONTROL 0x40081074\r
+#define MMCR_GPIO035_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO036_PIN_CONTROL 0x40081078\r
+#define MMCR_GPIO036_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO040_PIN_CONTROL 0x40081080\r
+#define MMCR_GPIO040_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO041_PIN_CONTROL 0x40081084\r
+#define MMCR_GPIO041_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO042_PIN_CONTROL 0x40081088\r
+#define MMCR_GPIO042_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO043_PIN_CONTROL 0x4008108C\r
+#define MMCR_GPIO043_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO044_PIN_CONTROL 0x40081090\r
+#define MMCR_GPIO044_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO045_PIN_CONTROL 0x40081094\r
+#define MMCR_GPIO045_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO046_PIN_CONTROL 0x40081098\r
+#define MMCR_GPIO046_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO047_PIN_CONTROL 0x4008109C\r
+#define MMCR_GPIO047_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO050_PIN_CONTROL 0x400810A0\r
+#define MMCR_GPIO050_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO051_PIN_CONTROL 0x400810A4\r
+#define MMCR_GPIO051_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO052_PIN_CONTROL 0x400810A8\r
+#define MMCR_GPIO052_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO053_PIN_CONTROL 0x400810AC\r
+#define MMCR_GPIO053_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO054_PIN_CONTROL 0x400810B0\r
+#define MMCR_GPIO054_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO055_PIN_CONTROL 0x400810B4\r
+#define MMCR_GPIO055_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO056_PIN_CONTROL 0x400810B8\r
+#define MMCR_GPIO056_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO057_PIN_CONTROL 0x400810BC\r
+#define MMCR_GPIO057_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO060_PIN_CONTROL 0x400810C0\r
+#define MMCR_GPIO060_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO061_PIN_CONTROL 0x400810C4\r
+#define MMCR_GPIO061_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO062_PIN_CONTROL 0x400810C8\r
+#define MMCR_GPIO062_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO063_PIN_CONTROL 0x400810CC\r
+#define MMCR_GPIO063_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO064_PIN_CONTROL 0x400810D0\r
+#define MMCR_GPIO064_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO065_PIN_CONTROL 0x400810D4\r
+#define MMCR_GPIO065_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO066_PIN_CONTROL 0x400810D8\r
+#define MMCR_GPIO066_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO067_PIN_CONTROL 0x400810DC\r
+#define MMCR_GPIO067_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO100_PIN_CONTROL 0x40081100\r
+#define MMCR_GPIO100_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO101_PIN_CONTROL 0x40081104\r
+#define MMCR_GPIO101_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO102_PIN_CONTROL 0x40081108\r
+#define MMCR_GPIO102_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO103_PIN_CONTROL 0x4008110C\r
+#define MMCR_GPIO103_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO104_PIN_CONTROL 0x40081110\r
+#define MMCR_GPIO104_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO105_PIN_CONTROL 0x40081114\r
+#define MMCR_GPIO105_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO106_PIN_CONTROL 0x40081118\r
+#define MMCR_GPIO106_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO107_PIN_CONTROL 0x4008111C\r
+#define MMCR_GPIO107_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO110_PIN_CONTROL 0x40081120\r
+#define MMCR_GPIO110_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO111_PIN_CONTROL 0x40081124\r
+#define MMCR_GPIO111_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO112_PIN_CONTROL 0x40081128\r
+#define MMCR_GPIO112_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO113_PIN_CONTROL 0x4008112C\r
+#define MMCR_GPIO113_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO114_PIN_CONTROL 0x40081130\r
+#define MMCR_GPIO114_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO115_PIN_CONTROL 0x40081134\r
+#define MMCR_GPIO115_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO116_PIN_CONTROL 0x40081138\r
+#define MMCR_GPIO116_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO117_PIN_CONTROL 0x4008113C\r
+#define MMCR_GPIO117_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO120_PIN_CONTROL 0x40081140\r
+#define MMCR_GPIO120_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO121_PIN_CONTROL 0x40081144\r
+#define MMCR_GPIO121_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO122_PIN_CONTROL 0x40081148\r
+#define MMCR_GPIO122_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO123_PIN_CONTROL 0x4008114C\r
+#define MMCR_GPIO123_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO124_PIN_CONTROL 0x40081150\r
+#define MMCR_GPIO124_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO125_PIN_CONTROL 0x40081154\r
+#define MMCR_GPIO125_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO126_PIN_CONTROL 0x40081158\r
+#define MMCR_GPIO126_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO127_PIN_CONTROL 0x4008115C\r
+#define MMCR_GPIO127_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO130_PIN_CONTROL 0x40081160\r
+#define MMCR_GPIO130_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO131_PIN_CONTROL 0x40081164\r
+#define MMCR_GPIO131_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO132_PIN_CONTROL 0x40081168\r
+#define MMCR_GPIO132_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO133_PIN_CONTROL 0x4008116C\r
+#define MMCR_GPIO133_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO134_PIN_CONTROL 0x40081170\r
+#define MMCR_GPIO134_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO135_PIN_CONTROL 0x40081174\r
+#define MMCR_GPIO135_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO136_PIN_CONTROL 0x40081178\r
+#define MMCR_GPIO136_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO140_PIN_CONTROL 0x40081180\r
+#define MMCR_GPIO140_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO141_PIN_CONTROL 0x40081184\r
+#define MMCR_GPIO141_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO142_PIN_CONTROL 0x40081188\r
+#define MMCR_GPIO142_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO143_PIN_CONTROL 0x4008118C\r
+#define MMCR_GPIO143_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO144_PIN_CONTROL 0x40081190\r
+#define MMCR_GPIO144_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO145_PIN_CONTROL 0x40081194\r
+#define MMCR_GPIO145_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO146_PIN_CONTROL 0x40081198\r
+#define MMCR_GPIO146_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO147_PIN_CONTROL 0x4008119C\r
+#define MMCR_GPIO147_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO150_PIN_CONTROL 0x400811A0\r
+#define MMCR_GPIO150_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO151_PIN_CONTROL 0x400811A4\r
+#define MMCR_GPIO151_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO152_PIN_CONTROL 0x400811A8\r
+#define MMCR_GPIO152_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO153_PIN_CONTROL 0x400811AC\r
+#define MMCR_GPIO153_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO154_PIN_CONTROL 0x400811B0\r
+#define MMCR_GPIO154_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO155_PIN_CONTROL 0x400811B4\r
+#define MMCR_GPIO155_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO156_PIN_CONTROL 0x400811B8\r
+#define MMCR_GPIO156_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO157_PIN_CONTROL 0x400811BC\r
+#define MMCR_GPIO157_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO160_PIN_CONTROL 0x400811C0\r
+#define MMCR_GPIO160_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO161_PIN_CONTROL 0x400811C4\r
+#define MMCR_GPIO161_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO162_PIN_CONTROL 0x400811C8\r
+#define MMCR_GPIO162_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO163_PIN_CONTROL 0x400811CC\r
+#define MMCR_GPIO163_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO164_PIN_CONTROL 0x400811D0\r
+#define MMCR_GPIO164_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO165_PIN_CONTROL 0x400811D4\r
+#define MMCR_GPIO165_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO200_PIN_CONTROL 0x40081200\r
+#define MMCR_GPIO200_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO201_PIN_CONTROL 0x40081204\r
+#define MMCR_GPIO201_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO202_PIN_CONTROL 0x40081208\r
+#define MMCR_GPIO202_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO203_PIN_CONTROL 0x4008120C\r
+#define MMCR_GPIO203_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO204_PIN_CONTROL 0x40081210\r
+#define MMCR_GPIO204_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO206_PIN_CONTROL 0x40081218\r
+#define MMCR_GPIO206_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO210_PIN_CONTROL 0x40081220\r
+#define MMCR_GPIO210_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO211_PIN_CONTROL 0x40081224\r
+#define MMCR_GPIO211_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO212_PIN_CONTROL 0x40081228\r
+#define MMCR_GPIO212_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO213_PIN_CONTROL 0x4008122C\r
+#define MMCR_GPIO213_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL))\r
+\r
+#define ADDR_GPIO_OUTPUT_GPIO_000_036 0x40081280\r
+#define MMCR_GPIO_OUTPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_000_036))\r
+\r
+#define ADDR_GPIO_OUTPUT_GPIO_040_076 0x40081284\r
+#define MMCR_GPIO_OUTPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_040_076))\r
+\r
+#define ADDR_GPIO_OUTPUT_GPIO_100_136 0x40081288\r
+#define MMCR_GPIO_OUTPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_100_136))\r
+\r
+#define ADDR_GPIO_OUTPUT_GPIO_140_176 0x4008128C\r
+#define MMCR_GPIO_OUTPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_140_176))\r
+\r
+#define ADDR_GPIO_OUTPUT_GPIO_200_236 0x40081290\r
+#define MMCR_GPIO_OUTPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_200_236))\r
+\r
+#define ADDR_GPIO_INPUT_GPIO_000_036 0x40081300\r
+#define MMCR_GPIO_INPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_000_036))\r
+\r
+#define ADDR_GPIO_INPUT_GPIO_040_076 0x40081304\r
+#define MMCR_GPIO_INPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_040_076))\r
+\r
+#define ADDR_GPIO_INPUT_GPIO_100_136 0x40081308\r
+#define MMCR_GPIO_INPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_100_136))\r
+\r
+#define ADDR_GPIO_INPUT_GPIO_140_176 0x4008130C\r
+#define MMCR_GPIO_INPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_140_176))\r
+\r
+#define ADDR_GPIO_INPUT_GPIO_200_236 0x40081310\r
+#define MMCR_GPIO_INPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_200_236))\r
+\r
+#define ADDR_GPIO_LOCK_4 0x400813EC\r
+#define MMCR_GPIO_LOCK_4 (*(VUINT32 *)(ADDR_GPIO_LOCK_4))\r
+\r
+#define ADDR_GPIO_LOCK_3 0x400813F0\r
+#define MMCR_GPIO_LOCK_3 (*(VUINT32 *)(ADDR_GPIO_LOCK_3))\r
+\r
+#define ADDR_GPIO_LOCK_2 0x400813F4\r
+#define MMCR_GPIO_LOCK_2 (*(VUINT32 *)(ADDR_GPIO_LOCK_2))\r
+\r
+#define ADDR_GPIO_LOCK_1 0x400813F8\r
+#define MMCR_GPIO_LOCK_1 (*(VUINT32 *)(ADDR_GPIO_LOCK_1))\r
+\r
+#define ADDR_GPIO_LOCK_0 0x400813FC\r
+#define MMCR_GPIO_LOCK_0 (*(VUINT32 *)(ADDR_GPIO_LOCK_0))\r
+\r
+#define ADDR_GPIO000_PIN_CONTROL_2 0x40081500\r
+#define MMCR_GPIO000_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO001_PIN_CONTROL_2 0x40081504\r
+#define MMCR_GPIO001_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO002_PIN_CONTROL_2 0x40081508\r
+#define MMCR_GPIO002_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO003_PIN_CONTROL_2 0x4008150C\r
+#define MMCR_GPIO003_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO004_PIN_CONTROL_2 0x40081510\r
+#define MMCR_GPIO004_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO005_PIN_CONTROL_2 0x40081514\r
+#define MMCR_GPIO005_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO006_PIN_CONTROL_2 0x40081518\r
+#define MMCR_GPIO006_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO007_PIN_CONTROL_2 0x4008151C\r
+#define MMCR_GPIO007_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO010_PIN_CONTROL_2 0x40081520\r
+#define MMCR_GPIO010_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO011_PIN_CONTROL_2 0x40081524\r
+#define MMCR_GPIO011_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO012_PIN_CONTROL_2 0x40081528\r
+#define MMCR_GPIO012_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO013_PIN_CONTROL_2 0x4008152C\r
+#define MMCR_GPIO013_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO014_PIN_CONTROL_2 0x40081530\r
+#define MMCR_GPIO014_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO015_PIN_CONTROL_2 0x40081534\r
+#define MMCR_GPIO015_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO016_PIN_CONTROL_2 0x40081538\r
+#define MMCR_GPIO016_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO017_PIN_CONTROL_2 0x4008153C\r
+#define MMCR_GPIO017_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO020_PIN_CONTROL_2 0x40081540\r
+#define MMCR_GPIO020_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO021_PIN_CONTROL_2 0x40081544\r
+#define MMCR_GPIO021_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO022_PIN_CONTROL_2 0x40081548\r
+#define MMCR_GPIO022_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO023_PIN_CONTROL_2 0x4008154C\r
+#define MMCR_GPIO023_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO024_PIN_CONTROL_2 0x40081550\r
+#define MMCR_GPIO024_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO025_PIN_CONTROL_2 0x40081554\r
+#define MMCR_GPIO025_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO026_PIN_CONTROL_2 0x40081558\r
+#define MMCR_GPIO026_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO027_PIN_CONTROL_2 0x4008155C\r
+#define MMCR_GPIO027_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO030_PIN_CONTROL_2 0x40081560\r
+#define MMCR_GPIO030_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO031_PIN_CONTROL_2 0x40081564\r
+#define MMCR_GPIO031_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO032_PIN_CONTROL_2 0x40081568\r
+#define MMCR_GPIO032_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO033_PIN_CONTROL_2 0x4008156C\r
+#define MMCR_GPIO033_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO034_PIN_CONTROL_2 0x40081570\r
+#define MMCR_GPIO034_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO035_PIN_CONTROL_2 0x40081574\r
+#define MMCR_GPIO035_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO036_PIN_CONTROL_2 0x40081578\r
+#define MMCR_GPIO036_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO040_PIN_CONTROL_2 0x40081580\r
+#define MMCR_GPIO040_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO041_PIN_CONTROL_2 0x40081584\r
+#define MMCR_GPIO041_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO042_PIN_CONTROL_2 0x40081588\r
+#define MMCR_GPIO042_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO043_PIN_CONTROL_2 0x4008158C\r
+#define MMCR_GPIO043_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO044_PIN_CONTROL_2 0x40081590\r
+#define MMCR_GPIO044_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO045_PIN_CONTROL_2 0x40081594\r
+#define MMCR_GPIO045_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO046_PIN_CONTROL_2 0x40081598\r
+#define MMCR_GPIO046_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO047_PIN_CONTROL_2 0x4008159C\r
+#define MMCR_GPIO047_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO050_PIN_CONTROL_2 0x400815A0\r
+#define MMCR_GPIO050_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO051_PIN_CONTROL_2 0x400815A4\r
+#define MMCR_GPIO051_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO052_PIN_CONTROL_2 0x400815A8\r
+#define MMCR_GPIO052_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO053_PIN_CONTROL_2 0x400815AC\r
+#define MMCR_GPIO053_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO054_PIN_CONTROL_2 0x400815B0\r
+#define MMCR_GPIO054_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO055_PIN_CONTROL_2 0x400815B4\r
+#define MMCR_GPIO055_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO056_PIN_CONTROL_2 0x400815B8\r
+#define MMCR_GPIO056_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO057_PIN_CONTROL_2 0x400815BC\r
+#define MMCR_GPIO057_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO060_PIN_CONTROL_2 0x400815C0\r
+#define MMCR_GPIO060_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO061_PIN_CONTROL_2 0x400815C4\r
+#define MMCR_GPIO061_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO062_PIN_CONTROL_2 0x400815C8\r
+#define MMCR_GPIO062_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO063_PIN_CONTROL_2 0x400815CC\r
+#define MMCR_GPIO063_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO064_PIN_CONTROL_2 0x400815D0\r
+#define MMCR_GPIO064_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO065_PIN_CONTROL_2 0x400815D4\r
+#define MMCR_GPIO065_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO066_PIN_CONTROL_2 0x400815D8\r
+#define MMCR_GPIO066_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO067_PIN_CONTROL_2 0x400815DC\r
+#define MMCR_GPIO067_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO100_PIN_CONTROL_2 0x400815E0\r
+#define MMCR_GPIO100_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO101_PIN_CONTROL_2 0x400815E4\r
+#define MMCR_GPIO101_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO102_PIN_CONTROL_2 0x400815E8\r
+#define MMCR_GPIO102_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO103_PIN_CONTROL_2 0x400815EC\r
+#define MMCR_GPIO103_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO104_PIN_CONTROL_2 0x400815F0\r
+#define MMCR_GPIO104_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO105_PIN_CONTROL_2 0x400815F4\r
+#define MMCR_GPIO105_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO106_PIN_CONTROL_2 0x400815F8\r
+#define MMCR_GPIO106_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO107_PIN_CONTROL_2 0x400815FC\r
+#define MMCR_GPIO107_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO110_PIN_CONTROL_2 0x40081600\r
+#define MMCR_GPIO110_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO111_PIN_CONTROL_2 0x40081604\r
+#define MMCR_GPIO111_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO112_PIN_CONTROL_2 0x40081608\r
+#define MMCR_GPIO112_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO113_PIN_CONTROL_2 0x4008160C\r
+#define MMCR_GPIO113_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO114_PIN_CONTROL_2 0x40081610\r
+#define MMCR_GPIO114_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO115_PIN_CONTROL_2 0x40081614\r
+#define MMCR_GPIO115_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO116_PIN_CONTROL_2 0x40081618\r
+#define MMCR_GPIO116_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO117_PIN_CONTROL_2 0x4008161C\r
+#define MMCR_GPIO117_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO120_PIN_CONTROL_2 0x40081620\r
+#define MMCR_GPIO120_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO121_PIN_CONTROL_2 0x40081624\r
+#define MMCR_GPIO121_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO122_PIN_CONTROL_2 0x40081628\r
+#define MMCR_GPIO122_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO123_PIN_CONTROL_2 0x4008162C\r
+#define MMCR_GPIO123_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO124_PIN_CONTROL_2 0x40081630\r
+#define MMCR_GPIO124_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO125_PIN_CONTROL_2 0x40081634\r
+#define MMCR_GPIO125_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO126_PIN_CONTROL_2 0x40081638\r
+#define MMCR_GPIO126_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO127_PIN_CONTROL_2 0x4008163C\r
+#define MMCR_GPIO127_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO130_PIN_CONTROL_2 0x40081640\r
+#define MMCR_GPIO130_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO131_PIN_CONTROL_2 0x40081644\r
+#define MMCR_GPIO131_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO132_PIN_CONTROL_2 0x40081648\r
+#define MMCR_GPIO132_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO133_PIN_CONTROL_2 0x4008164C\r
+#define MMCR_GPIO133_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO134_PIN_CONTROL_2 0x40081650\r
+#define MMCR_GPIO134_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO135_PIN_CONTROL_2 0x40081654\r
+#define MMCR_GPIO135_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO136_PIN_CONTROL_2 0x40081658\r
+#define MMCR_GPIO136_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO140_PIN_CONTROL_2 0x40081660\r
+#define MMCR_GPIO140_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO141_PIN_CONTROL_2 0x40081664\r
+#define MMCR_GPIO141_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO142_PIN_CONTROL_2 0x40081668\r
+#define MMCR_GPIO142_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO143_PIN_CONTROL_2 0x4008166C\r
+#define MMCR_GPIO143_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO144_PIN_CONTROL_2 0x40081670\r
+#define MMCR_GPIO144_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO145_PIN_CONTROL_2 0x40081674\r
+#define MMCR_GPIO145_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO146_PIN_CONTROL_2 0x40081678\r
+#define MMCR_GPIO146_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO147_PIN_CONTROL_2 0x4008167C\r
+#define MMCR_GPIO147_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO150_PIN_CONTROL_2 0x40081680\r
+#define MMCR_GPIO150_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO151_PIN_CONTROL_2 0x40081684\r
+#define MMCR_GPIO151_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO152_PIN_CONTROL_2 0x40081688\r
+#define MMCR_GPIO152_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO153_PIN_CONTROL_2 0x4008168C\r
+#define MMCR_GPIO153_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO154_PIN_CONTROL_2 0x40081690\r
+#define MMCR_GPIO154_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO155_PIN_CONTROL_2 0x40081694\r
+#define MMCR_GPIO155_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO156_PIN_CONTROL_2 0x40081698\r
+#define MMCR_GPIO156_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO157_PIN_CONTROL_2 0x4008169C\r
+#define MMCR_GPIO157_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO160_PIN_CONTROL_2 0x400816A0\r
+#define MMCR_GPIO160_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO161_PIN_CONTROL_2 0x400816A4\r
+#define MMCR_GPIO161_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO162_PIN_CONTROL_2 0x400816A8\r
+#define MMCR_GPIO162_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO163_PIN_CONTROL_2 0x400816AC\r
+#define MMCR_GPIO163_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO164_PIN_CONTROL_2 0x400816B0\r
+#define MMCR_GPIO164_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO165_PIN_CONTROL_2 0x400816B4\r
+#define MMCR_GPIO165_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO200_PIN_CONTROL_2 0x40081720\r
+#define MMCR_GPIO200_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO201_PIN_CONTROL_2 0x40081724\r
+#define MMCR_GPIO201_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO202_PIN_CONTROL_2 0x40081728\r
+#define MMCR_GPIO202_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO203_PIN_CONTROL_2 0x4008172C\r
+#define MMCR_GPIO203_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO204_PIN_CONTROL_2 0x40081730\r
+#define MMCR_GPIO204_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO206_PIN_CONTROL_2 0x40081738\r
+#define MMCR_GPIO206_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO210_PIN_CONTROL_2 0x40081740\r
+#define MMCR_GPIO210_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO211_PIN_CONTROL_2 0x40081744\r
+#define MMCR_GPIO211_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO212_PIN_CONTROL_2 0x40081748\r
+#define MMCR_GPIO212_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL_2))\r
+\r
+#define ADDR_GPIO213_PIN_CONTROL_2 0x4008174C\r
+#define MMCR_GPIO213_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL_2))\r
+\r
+/***************************************************************\r
+* DMA\r
+***************************************************************/\r
+#define ADDR_DMA_MAIN_CONTROL 0x40002400\r
+#define MMCR_DMA_MAIN_CONTROL (*(VUINT8 *)(ADDR_DMA_MAIN_CONTROL))\r
+\r
+#define ADDR_DMA_AFIFO_DATA 0x40002404\r
+#define MMCR_DMA_AFIFO_DATA (*(VUINT32 *)(ADDR_DMA_AFIFO_DATA))\r
+\r
+#define ADDR_DMA_MAIN_DEBUG 0x40002408\r
+#define MMCR_DMA_MAIN_DEBUG (*(VUINT8 *)(ADDR_DMA_MAIN_DEBUG))\r
+\r
+#define ADDR_DMA_CH0_ACTIVATE 0x40002410\r
+#define MMCR_DMA_CH0_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH0_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH0_MEMORY_START_ADDRESS 0x40002414\r
+#define MMCR_DMA_CH0_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH0_MEMORY_END_ADDRESS 0x40002418\r
+#define MMCR_DMA_CH0_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH0_AHB_ADDRESS 0x4000241C\r
+#define MMCR_DMA_CH0_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH0_CONTROL 0x40002420\r
+#define MMCR_DMA_CH0_CONTROL (*(VUINT32 *)(ADDR_DMA_CH0_CONTROL))\r
+\r
+#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS 0x40002424\r
+#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE 0x40002428\r
+#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH0_TEST 0x4000242C\r
+#define MMCR_DMA_CH0_TEST (*(VUINT32 *)(ADDR_DMA_CH0_TEST))\r
+\r
+#define ADDR_DMA_CH1_ACTIVATE 0x40002430\r
+#define MMCR_DMA_CH1_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH1_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH1_MEMORY_START_ADDRESS 0x40002434\r
+#define MMCR_DMA_CH1_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH1_MEMORY_END_ADDRESS 0x40002438\r
+#define MMCR_DMA_CH1_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH1_AHB_ADDRESS 0x4000243C\r
+#define MMCR_DMA_CH1_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH1_CONTROL 0x40002440\r
+#define MMCR_DMA_CH1_CONTROL (*(VUINT32 *)(ADDR_DMA_CH1_CONTROL))\r
+\r
+#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS 0x40002444\r
+#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE 0x40002448\r
+#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH1_TEST 0x4000244C\r
+#define MMCR_DMA_CH1_TEST (*(VUINT32 *)(ADDR_DMA_CH1_TEST))\r
+\r
+#define ADDR_DMA_CH10_ACTIVATE 0x40002550\r
+#define MMCR_DMA_CH10_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH10_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH10_MEMORY_START_ADDRESS 0x40002554\r
+#define MMCR_DMA_CH10_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH10_MEMORY_END_ADDRESS 0x40002558\r
+#define MMCR_DMA_CH10_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH10_AHB_ADDRESS 0x4000255C\r
+#define MMCR_DMA_CH10_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH10_CONTROL 0x40002560\r
+#define MMCR_DMA_CH10_CONTROL (*(VUINT32 *)(ADDR_DMA_CH10_CONTROL))\r
+\r
+#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS 0x40002564\r
+#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE 0x40002568\r
+#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH10_TEST 0x4000256C\r
+#define MMCR_DMA_CH10_TEST (*(VUINT32 *)(ADDR_DMA_CH10_TEST))\r
+\r
+#define ADDR_DMA_CH11_ACTIVATE 0x40002570\r
+#define MMCR_DMA_CH11_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH11_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH11_MEMORY_START_ADDRESS 0x40002574\r
+#define MMCR_DMA_CH11_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH11_MEMORY_END_ADDRESS 0x40002578\r
+#define MMCR_DMA_CH11_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH11_AHB_ADDRESS 0x4000257C\r
+#define MMCR_DMA_CH11_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH11_CONTROL 0x40002580\r
+#define MMCR_DMA_CH11_CONTROL (*(VUINT32 *)(ADDR_DMA_CH11_CONTROL))\r
+\r
+#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS 0x40002584\r
+#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE 0x40002588\r
+#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH11_TEST 0x4000258C\r
+#define MMCR_DMA_CH11_TEST (*(VUINT32 *)(ADDR_DMA_CH11_TEST))\r
+\r
+#define ADDR_DMA_CH2_ACTIVATE 0x40002450\r
+#define MMCR_DMA_CH2_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH2_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH2_MEMORY_START_ADDRESS 0x40002454\r
+#define MMCR_DMA_CH2_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH2_MEMORY_END_ADDRESS 0x40002458\r
+#define MMCR_DMA_CH2_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH2_AHB_ADDRESS 0x4000245C\r
+#define MMCR_DMA_CH2_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH2_CONTROL 0x40002460\r
+#define MMCR_DMA_CH2_CONTROL (*(VUINT32 *)(ADDR_DMA_CH2_CONTROL))\r
+\r
+#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS 0x40002464\r
+#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE 0x40002468\r
+#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH2_TEST 0x4000246C\r
+#define MMCR_DMA_CH2_TEST (*(VUINT32 *)(ADDR_DMA_CH2_TEST))\r
+\r
+#define ADDR_DMA_CH3_ACTIVATE 0x40002470\r
+#define MMCR_DMA_CH3_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH3_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH3_MEMORY_START_ADDRESS 0x40002474\r
+#define MMCR_DMA_CH3_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH3_MEMORY_END_ADDRESS 0x40002478\r
+#define MMCR_DMA_CH3_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH3_AHB_ADDRESS 0x4000247C\r
+#define MMCR_DMA_CH3_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH3_CONTROL 0x40002480\r
+#define MMCR_DMA_CH3_CONTROL (*(VUINT32 *)(ADDR_DMA_CH3_CONTROL))\r
+\r
+#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS 0x40002484\r
+#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE 0x40002488\r
+#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH3_TEST 0x4000248C\r
+#define MMCR_DMA_CH3_TEST (*(VUINT32 *)(ADDR_DMA_CH3_TEST))\r
+\r
+#define ADDR_DMA_CH4_ACTIVATE 0x40002490\r
+#define MMCR_DMA_CH4_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH4_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH4_MEMORY_START_ADDRESS 0x40002494\r
+#define MMCR_DMA_CH4_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH4_MEMORY_END_ADDRESS 0x40002498\r
+#define MMCR_DMA_CH4_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH4_AHB_ADDRESS 0x4000249C\r
+#define MMCR_DMA_CH4_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH4_CONTROL 0x400024A0\r
+#define MMCR_DMA_CH4_CONTROL (*(VUINT32 *)(ADDR_DMA_CH4_CONTROL))\r
+\r
+#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS 0x400024A4\r
+#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE 0x400024A8\r
+#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH4_TEST 0x400024AC\r
+#define MMCR_DMA_CH4_TEST (*(VUINT32 *)(ADDR_DMA_CH4_TEST))\r
+\r
+#define ADDR_DMA_CH5_ACTIVATE 0x400024B0\r
+#define MMCR_DMA_CH5_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH5_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH5_MEMORY_START_ADDRESS 0x400024B4\r
+#define MMCR_DMA_CH5_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH5_MEMORY_END_ADDRESS 0x400024B8\r
+#define MMCR_DMA_CH5_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH5_AHB_ADDRESS 0x400024BC\r
+#define MMCR_DMA_CH5_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH5_CONTROL 0x400024C0\r
+#define MMCR_DMA_CH5_CONTROL (*(VUINT32 *)(ADDR_DMA_CH5_CONTROL))\r
+\r
+#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS 0x400024C4\r
+#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE 0x400024C8\r
+#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH5_TEST 0x400024CC\r
+#define MMCR_DMA_CH5_TEST (*(VUINT32 *)(ADDR_DMA_CH5_TEST))\r
+\r
+#define ADDR_DMA_CH6_ACTIVATE 0x400024D0\r
+#define MMCR_DMA_CH6_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH6_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH6_MEMORY_START_ADDRESS 0x400024D4\r
+#define MMCR_DMA_CH6_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH6_MEMORY_END_ADDRESS 0x400024D8\r
+#define MMCR_DMA_CH6_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH6_AHB_ADDRESS 0x400024DC\r
+#define MMCR_DMA_CH6_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH6_CONTROL 0x4.00E+05\r
+#define MMCR_DMA_CH6_CONTROL (*(VUINT32 *)(ADDR_DMA_CH6_CONTROL))\r
+\r
+#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS 0x4.00E+09\r
+#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE 0x4.00E+13\r
+#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH6_TEST 0x400024EC\r
+#define MMCR_DMA_CH6_TEST (*(VUINT32 *)(ADDR_DMA_CH6_TEST))\r
+\r
+#define ADDR_DMA_CH7_ACTIVATE 0x400024F0\r
+#define MMCR_DMA_CH7_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH7_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH7_MEMORY_START_ADDRESS 0x400024F4\r
+#define MMCR_DMA_CH7_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH7_MEMORY_END_ADDRESS 0x400024F8\r
+#define MMCR_DMA_CH7_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH7_AHB_ADDRESS 0x400024FC\r
+#define MMCR_DMA_CH7_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH7_CONTROL 0x40002500\r
+#define MMCR_DMA_CH7_CONTROL (*(VUINT32 *)(ADDR_DMA_CH7_CONTROL))\r
+\r
+#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS 0x40002504\r
+#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE 0x40002508\r
+#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH7_TEST 0x4000250C\r
+#define MMCR_DMA_CH7_TEST (*(VUINT32 *)(ADDR_DMA_CH7_TEST))\r
+\r
+#define ADDR_DMA_CH8_ACTIVATE 0x40002510\r
+#define MMCR_DMA_CH8_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH8_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH8_MEMORY_START_ADDRESS 0x40002514\r
+#define MMCR_DMA_CH8_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH8_MEMORY_END_ADDRESS 0x40002518\r
+#define MMCR_DMA_CH8_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH8_AHB_ADDRESS 0x4000251C\r
+#define MMCR_DMA_CH8_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH8_CONTROL 0x40002520\r
+#define MMCR_DMA_CH8_CONTROL (*(VUINT32 *)(ADDR_DMA_CH8_CONTROL))\r
+\r
+#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS 0x40002524\r
+#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE 0x40002528\r
+#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH8_TEST 0x4000252C\r
+#define MMCR_DMA_CH8_TEST (*(VUINT32 *)(ADDR_DMA_CH8_TEST))\r
+\r
+#define ADDR_DMA_CH9_ACTIVATE 0x40002530\r
+#define MMCR_DMA_CH9_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH9_ACTIVATE))\r
+\r
+#define ADDR_DMA_CH9_MEMORY_START_ADDRESS 0x40002534\r
+#define MMCR_DMA_CH9_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_START_ADDRESS))\r
+\r
+#define ADDR_DMA_CH9_MEMORY_END_ADDRESS 0x40002538\r
+#define MMCR_DMA_CH9_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_END_ADDRESS))\r
+\r
+#define ADDR_DMA_CH9_AHB_ADDRESS 0x4000253C\r
+#define MMCR_DMA_CH9_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_AHB_ADDRESS))\r
+\r
+#define ADDR_DMA_CH9_CONTROL 0x40002540\r
+#define MMCR_DMA_CH9_CONTROL (*(VUINT32 *)(ADDR_DMA_CH9_CONTROL))\r
+\r
+#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS 0x40002544\r
+#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS))\r
+\r
+#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE 0x40002548\r
+#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE))\r
+\r
+#define ADDR_DMA_CH9_TEST 0x4000254C\r
+#define MMCR_DMA_CH9_TEST (*(VUINT32 *)(ADDR_DMA_CH9_TEST))\r
+\r
+#endif /*SMSCMMCR_H_*/\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2015/11/22 06:01:28 $ \r
+$Author: amohandas $\r
+Last Change: Updated with unit testing feedbacks\r
+******************************************************************************/\r
+/** @file btimer.h\r
+* \brief Basic Timer Peripheral Header file\r
+* \author jvasanth\r
+* \r
+* This file is the header file for Basic Timer Peripheral \r
+******************************************************************************/\r
+\r
+/** @defgroup Basic_Timer\r
+ * @{\r
+ */\r
+\r
+#ifndef _BTIMER_H\r
+#define _BTIMER_H\r
+\r
+/******************************************************************************/\r
+/** Logical Timer ID for APIs.\r
+ * This is the timer IDs passed to Basic Timer API function calls \r
+ *******************************************************************************/\r
+enum _PID_BTIMER_\r
+{\r
+ PID_BTIMER_0,\r
+ PID_BTIMER_1,\r
+ PID_BTIMER_2,\r
+ PID_BTIMER_3,\r
+ PID_BTIMER_4,\r
+ PID_BTIMER_5,\r
+ PID_BTIMER_MAX \r
+};\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Logical flags for Timer Control */\r
+/* ---------------------------------------------------------------------- */\r
+//This is for tmr_cntl parameter in btimer_init function\r
+#define BTIMER_AUTO_RESTART (0x08u)\r
+#define BTIMER_ONE_SHOT (0u)\r
+#define BTIMER_COUNT_UP (0x04u)\r
+#define BTIMER_COUNT_DOWN (0u)\r
+#define BTIMER_INT_EN (0x01u)\r
+#define BTIMER_NO_INT (0u)\r
+/* ---------------------------------------------------------------------- */\r
+\r
+\r
+//Timer Block Hardware Bits and Masks\r
+#define BTIMER_CNTL_HALT (0x80UL)\r
+#define BTIMER_CNTL_RELOAD (0x40UL)\r
+#define BTIMER_CNTL_START (0x20UL)\r
+#define BTIMER_CNTL_SOFT_RESET (0x10UL)\r
+#define BTIMER_CNTL_AUTO_RESTART (0x08UL)\r
+#define BTIMER_CNTL_COUNT_UP (0x04UL)\r
+#define BTIMER_CNTL_ENABLE (0x01UL)\r
+\r
+#define BTIMER_CNTL_HALT_BIT (7U)\r
+#define BTIMER_CNTL_RELOAD_BIT (6U)\r
+#define BTIMER_CNTL_START_BIT (5U)\r
+#define BTIMER_CNTRL_SOFT_RESET_BIT (4U)\r
+#define BTIMER_CNTL_AUTO_RESTART_BIT (3U)\r
+#define BTIMER_CNTL_COUNT_DIR_BIT (2U)\r
+#define BTIMER_CNTL_ENABLE_BIT (0U)\r
+\r
+#define BTIMER_GIRQ MEC_GIRQ23_ID\r
+#define BTIMER_MAX_INSTANCE PID_BTIMER_MAX\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Basic Timer Intitialization function */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Initialize specified timer\r
+ * @param btimer_id Basic Timer ID\r
+ * @param tmr_cntl Logical flags for Timer Control\r
+ * @param initial_count Initial Count\r
+ * @param preload_count Preload Count\r
+ * @note Performs a soft reset of the timer before configuration \r
+ */\r
+void btimer_init(uint8_t btimer_id, \r
+ uint16_t tmr_cntl,\r
+ uint16_t prescaler,\r
+ uint32_t initial_count,\r
+ uint32_t preload_count);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions to program and read the Basic Timer Counter */\r
+/* ---------------------------------------------------------------------- */\r
+/** Program timer's counter register.\r
+ * @param btimer_id Basic Timer ID\r
+ * @param count new counter value \r
+ * @note Timer hardware may implement a 16-bit or 32-bit \r
+ * hardware counter. If the timer is 16-bit only the lower\r
+ * 16-bits of the count paramter are used.\r
+ */\r
+void btimer_count_set(uint8_t btimer_id, uint32_t count);\r
+\r
+/** Return current value of timer's count register.\r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint32_t timer count may be 32 or 16 bits depending \r
+ * upon the hardware. Timers 0-3 are 16-bit\r
+ * and Timers 4-5 are 32-bit.\r
+ */\r
+uint32_t btimer_count_get(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Function to reload counter from Preload Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Force timer to reload counter from preload \r
+ * register. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note Hardware will only reload counter if timer is running. \r
+ */\r
+void btimer_reload(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions for stopping and starting the basic Timer */\r
+/* ---------------------------------------------------------------------- */\r
+/** Start timer counting.\r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_start(uint8_t btimer_id);\r
+\r
+/** Stop timer. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note When a stopped timer is started again it will reload \r
+ * the count register from preload value.\r
+ */\r
+void btimer_stop(uint8_t btimer_id);\r
+\r
+/** Return state of timer's START bit. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint8_t 0(timer not started), 1 (timer started)\r
+ */\r
+uint8_t btimer_is_started(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Function to perform basic timer soft reset */\r
+/* ---------------------------------------------------------------------- */\r
+/** Peform soft reset of specified timer. \r
+ * @param btimer_id Basic Timer ID \r
+ * @note Soft reset set all registers to POR values.\r
+ * Spins 256 times waiting on hardware to clear reset bit. \r
+ */\r
+void btimer_reset(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions to halt/unhalt the timer counting */\r
+/* ---------------------------------------------------------------------- */\r
+/** Halt timer counting with no reload on unhalt. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note A halted timer will not reload the count register when \r
+ * unhalted, it will continue counting from the current\r
+ * count value.\r
+ */\r
+void btimer_halt(uint8_t btimer_id);\r
+\r
+/** Unhalt timer counting. \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_unhalt(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions for Basic Timer interrupt */\r
+/* ---------------------------------------------------------------------- */\r
+/** Enable specified timer's interrupt from the block. \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param ien Non-zero enable interrupt in timer block, 0 \r
+ * disable.\r
+ */\r
+void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien);\r
+\r
+/** Read Timer interrupt status and clear if set \r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint8_t 1 (Timer interrupt status set) else 0. \r
+ * @note If timer interrupt status is set then clear it before \r
+ * returning.\r
+ */\r
+uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions for Basic Timer GIRQ */\r
+/* ---------------------------------------------------------------------- */\r
+/** Enables GIRQ enable bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_enable_set(uint8_t btimer_id);\r
+\r
+/** Clears GIRQ enable bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_enable_clr(uint8_t btimer_id);\r
+\r
+/** Returns GIRQ source bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @return uint8_t 0(src bit not set), Non-zero (src bit set)\r
+ */\r
+uint8_t btimer_girq_src_get(uint8_t btimer_id);\r
+\r
+/** Clears GIRQ source bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_src_clr(uint8_t btimer_id);\r
+\r
+/** Returns GIRQ result bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @return uint8_t 0(result bit not set), Non-zero (result bit set)\r
+ */\r
+uint8_t btimer_girq_result_get(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions for Basic Timer Sleep */\r
+/* ---------------------------------------------------------------------- */\r
+/** Enable/Disable clock gating on idle of a timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param sleep_en 1 = Sleep enable, 0 = Sleep disable\r
+ */\r
+void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en);\r
+\r
+/** Returns clk required status for the timer block\r
+ * @param btimer_id Basic Timer ID.\r
+ * @return Non-zero if clk required, else 0\r
+ */\r
+uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id);\r
+\r
+/** Enable/Disable reset on sleep for the timer block \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param reset_en 1 to enable, 0 to disable\r
+ */\r
+void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions to set and read Timer Counter Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Sets timer counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @param count - 32-bit counter \r
+ */\r
+void p_btimer_count_set(uint8_t btimer_id, uint32_t count);\r
+\r
+/** Read the timer counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @return count - 32-bit counter \r
+ */\r
+uint32_t p_btimer_count_get(uint8_t btimer_id);\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Function to program the Preload */\r
+/* ---------------------------------------------------------------------- */\r
+/** Sets preload for the counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @param preload_count - 32-bit pre-load value \r
+ */\r
+void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Functions - Functions for basic timer interrupts */\r
+/* ---------------------------------------------------------------------- */\r
+/** Reads the interrupt status bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ * @return status - 1 if interrupt status set, else 0\r
+ */\r
+uint8_t p_btimer_int_status_get(uint8_t btimer_id);\r
+\r
+/** Clears interrupt status bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_status_clr(uint8_t btimer_id);\r
+\r
+/** Sets interrupt enable bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_enable_set(uint8_t btimer_id);\r
+\r
+/** Clears interrupt enable bit for the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_enable_clr(uint8_t btimer_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Functions - Functions for Control Register */\r
+/* ---------------------------------------------------------------------- */\r
+/** Writes the control register 32-bits\r
+ * @param btimer_id Basic Timer ID\r
+ * @param value - 32-bit value to program\r
+ */\r
+void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value);\r
+\r
+/** Reads the control register \r
+ * @param btimer_id Basic Timer ID\r
+ * @return uint32_t - 32-bit value\r
+ */\r
+uint32_t p_btimer_ctrl_read(uint8_t btimer_id);\r
+\r
+/** Clears enable bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_enable_set(uint8_t btimer_id);\r
+\r
+/** Clears enable bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_enable_clr(uint8_t btimer_id);\r
+\r
+/** Sets counter direction bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id);\r
+\r
+/** Clears counter direction bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id);\r
+\r
+/** Sets auto restart bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id);\r
+\r
+/** Clears auto resetart bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id);\r
+\r
+/** Sets soft reset bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id);\r
+\r
+/** Read Soft Reset bit \r
+ * @param btimer_id Basic Timer ID\r
+ * @return 0 if soft reset status bit cleared; else non-zero value\r
+ */\r
+uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id);\r
+\r
+/** Sets start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_start_set(uint8_t btimer_id);\r
+\r
+/** Read start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ * @return 0 if start bit not set; else non-zero value\r
+ */\r
+uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id);\r
+\r
+/** Clears start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_start_clr(uint8_t btimer_id);\r
+\r
+/** Sets reload bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_reload_set(uint8_t btimer_id);\r
+\r
+/** Clears reload bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_reload_clr(uint8_t btimer_id);\r
+\r
+/** Sets halt bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_halt_set(uint8_t btimer_id);\r
+\r
+/** Clears halt bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+\r
+void p_btimer_ctrl_halt_clr(uint8_t btimer_id);\r
+\r
+/** Sets prescale value\r
+ * @param btimer_id Basic Timer ID\r
+ * @param prescaler - 16-bit pre-scale value \r
+ */\r
+void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler);\r
+\r
+\r
+#endif // #ifndef _BTIMER_H\r
+\r
+/* end btimer_perphl.c */\r
+\r
+/** @} //Peripherals Basic_Timer\r
+ */\r
+\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #2 $ \r
+$DateTime: 2015/11/24 06:27:00 $ \r
+$Author: amohandas $\r
+Last Change: Updated for tabs\r
+******************************************************************************/\r
+/** @file btimer_api.c\r
+* \brief Basic Timer APIs Source file\r
+* \author jvasanth\r
+* \r
+* This file implements the Basic Timer API functions \r
+******************************************************************************/\r
+\r
+/** @defgroup Basic_Timer\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "btimer.h"\r
+#include "..\pcr\pcr.h"\r
+\r
+/** Basic Timer Sleep Registers & Bit Positions */\r
+static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = {\r
+ PCR_BTIMER0,\r
+ PCR_BTIMER1,\r
+ PCR_BTIMER2,\r
+ PCR_BTIMER3,\r
+ PCR_BTIMER4,\r
+ PCR_BTIMER5\r
+};\r
+\r
+#ifdef PLIB_BTIMER_CHECK_ID\r
+\r
+/** Local helper that checks if logical Timer ID is valid. \r
+ * @param btimer_id Basic Timer ID \r
+ * @return uint8_t Non-zero(VALID), 0(Invalid)\r
+ */\r
+static uint8_t btmr_valid(uint8_t btimer_id)\r
+{\r
+ if ( btimer_id < (PID_BTIMER_MAX ) ) {\r
+ return true;\r
+ }\r
+ return false;\r
+}\r
+\r
+#else\r
+\r
+\r
+/** This version of tmr_valid skips checking always returning 1. \r
+ * Compiler may optimize it out.\r
+ * @param btimer_id Basic Timer ID \r
+ * @return uint8_t 1(VALID) \r
+ */\r
+static uint8_t btmr_valid(uint8_t btimer_id) { return 1; }\r
+\r
+#endif\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Basic Timer Intitialization function */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Initialize specified timer\r
+ * @param btimer_id Basic Timer ID\r
+ * @param tmr_cntl Logical flags for Timer Control\r
+ * @param initial_count Initial Count\r
+ * @param preload_count Preload Count\r
+ * @note Performs a soft reset of the timer before configuration \r
+ */\r
+void btimer_init(uint8_t btimer_id, \r
+ uint16_t tmr_cntl,\r
+ uint16_t prescaler,\r
+ uint32_t initial_count,\r
+ uint32_t preload_count)\r
+{ \r
+ uint32_t value; \r
+\r
+ if (btmr_valid(btimer_id)) {\r
+ \r
+ btimer_reset(btimer_id); \r
+ \r
+ // Ungate timer clocks and program prescale\r
+ value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE); \r
+ p_btimer_ctrl_write(btimer_id, value);\r
+ \r
+ // Program Preload & initial counter value\r
+ p_btimer_preload_set(btimer_id, preload_count);\r
+ p_btimer_count_set(btimer_id, initial_count); \r
+ \r
+ // Program control register, interrupt enable, and clear status\r
+ if (tmr_cntl & BTIMER_COUNT_UP) { \r
+ p_btimer_ctrl_counter_dir_set(btimer_id); \r
+ }\r
+ if (tmr_cntl & BTIMER_AUTO_RESTART) {\r
+ p_btimer_ctrl_auto_restart_set(btimer_id); \r
+ } \r
+ if (tmr_cntl & BTIMER_INT_EN) { \r
+ p_btimer_int_enable_set(btimer_id); // enable first\r
+ p_btimer_int_status_clr(btimer_id); // clear status \r
+ }\r
+ }\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to program and read the Basic Timer Counter */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Program timer's counter register.\r
+ * @param btimer_id Basic Timer ID\r
+ * @param count new counter value \r
+ * @note Timer hardware may implement a 16-bit or 32-bit \r
+ * hardware counter. If the timer is 16-bit only the lower\r
+ * 16-bits of the count paramter are used.\r
+ */\r
+void btimer_count_set(uint8_t btimer_id, uint32_t count)\r
+{\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ p_btimer_count_set(btimer_id, count); \r
+ }\r
+}\r
+\r
+/** Return current value of timer's count register.\r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint32_t timer count may be 32 or 16 bits depending \r
+ * upon the hardware. Timers 0-3 are 16-bit\r
+ * and Timers 4-5 are 32-bit.\r
+ */\r
+uint32_t btimer_count_get(uint8_t btimer_id)\r
+{ \r
+ uint32_t cnt;\r
+ \r
+ cnt = 0ul;\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ cnt = p_btimer_count_get(btimer_id); \r
+ }\r
+ \r
+ return cnt;\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to reload counter from Preload Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Force timer to reload counter from preload \r
+ * register. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note Hardware will only reload counter if timer is running. \r
+ */\r
+void btimer_reload(uint8_t btimer_id)\r
+{\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running\r
+ {\r
+ p_btimer_ctrl_reload_set(btimer_id);\r
+ }\r
+ }\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for stopping and starting the basic Timer */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Start timer counting.\r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_start(uint8_t btimer_id)\r
+{\r
+ if ( btmr_valid(btimer_id) ) {\r
+ \r
+ p_btimer_ctrl_start_set(btimer_id);\r
+ }\r
+}\r
+\r
+/** Stop timer. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note When a stopped timer is started again it will reload \r
+ * the count register from preload value.\r
+ */\r
+void btimer_stop(uint8_t btimer_id)\r
+{\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ p_btimer_ctrl_start_clr(btimer_id); \r
+ \r
+ }\r
+}\r
+\r
+/** Return state of timer's START bit. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint8_t 0(timer not started), 1 (timer started)\r
+ */\r
+uint8_t btimer_is_started(uint8_t btimer_id)\r
+{ \r
+ uint8_t sts;\r
+ \r
+ sts = 0;\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ if (p_btimer_ctrl_start_get(btimer_id)) \r
+ {\r
+ sts = 1;\r
+ } \r
+ }\r
+ return sts;\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to perform basic timer soft reset */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Peform soft reset of specified timer. \r
+ * @param btimer_id Basic Timer ID \r
+ * @note Soft reset set all registers to POR values.\r
+ * Spins 256 times waiting on hardware to clear reset bit. \r
+ */\r
+void btimer_reset(uint8_t btimer_id)\r
+{ \r
+ uint32_t wait_cnt;\r
+ uint8_t soft_reset_sts;\r
+\r
+ if (btmr_valid(btimer_id)) { \r
+ \r
+ p_btimer_ctrl_soft_reset_set(btimer_id); \r
+\r
+ wait_cnt = 256ul;\r
+ do {\r
+ soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id);\r
+ \r
+ if (0 == soft_reset_sts){ \r
+ break;\r
+ }\r
+ } \r
+ while ( wait_cnt-- ); \r
+ } \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to halt/unhalt the timer counting */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Halt timer counting with no reload on unhalt. \r
+ * @param btimer_id Basic Timer ID. \r
+ * @note A halted timer will not reload the count register when \r
+ * unhalted, it will continue counting from the current\r
+ * count value.\r
+ */\r
+void btimer_halt(uint8_t btimer_id)\r
+{\r
+ if ( btmr_valid(btimer_id) ) {\r
+ \r
+ p_btimer_ctrl_halt_set(btimer_id); \r
+ }\r
+}\r
+\r
+/** Unhalt timer counting. \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_unhalt(uint8_t btimer_id)\r
+{\r
+ if ( btmr_valid(btimer_id) ) { \r
+ \r
+ p_btimer_ctrl_halt_clr(btimer_id);\r
+ }\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Basic Timer interrupt */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Enable specified timer's interrupt from the block. \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param ien Non-zero enable interrupt in timer block, 0 \r
+ * disable.\r
+ */\r
+void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien)\r
+{ \r
+ if (btmr_valid(btimer_id)) { \r
+ \r
+ p_btimer_int_enable_set(btimer_id);\r
+\r
+ if (ien) {\r
+ p_btimer_int_enable_set(btimer_id);\r
+ } else {\r
+ p_btimer_int_enable_clr(btimer_id);\r
+ }\r
+ }\r
+}\r
+\r
+/** Read Timer interrupt status and clear if set \r
+ * @param btimer_id Basic Timer ID. \r
+ * @return uint8_t 1 (Timer interrupt status set) else 0. \r
+ * @note If timer interrupt status is set then clear it before \r
+ * returning.\r
+ */\r
+uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id)\r
+{ \r
+ uint8_t sts;\r
+\r
+ sts = 0;\r
+ if (btmr_valid(btimer_id)) { \r
+ \r
+ sts = p_btimer_int_status_get(btimer_id);\r
+ if (sts) {\r
+ p_btimer_int_status_clr(btimer_id); \r
+ }\r
+ }\r
+ return sts;\r
+}\r
+\r
+#if 0 //Temporary disable until interrupt module\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Basic Timer GIRQ */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Enables GIRQ enable bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_enable_set(uint8_t btimer_id)\r
+{\r
+ if (btmr_valid(btimer_id))\r
+ {\r
+ //Note: Bit Position is same as Timer ID \r
+ p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id);\r
+ } \r
+}\r
+\r
+/** Clears GIRQ enable bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_enable_clr(uint8_t btimer_id)\r
+{ \r
+ if (btmr_valid(btimer_id))\r
+ { \r
+ //Note: Bit Position is same as Timer ID \r
+ p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id);\r
+ } \r
+ \r
+}\r
+\r
+/** Returns GIRQ source bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @return uint8_t 0(src bit not set), Non-zero (src bit set)\r
+ */\r
+uint8_t btimer_girq_src_get(uint8_t btimer_id)\r
+{\r
+ uint8_t retVal;\r
+\r
+ retVal = 0;\r
+ if (btmr_valid(btimer_id))\r
+ {\r
+ //Note: Bit Position is same as Timer ID \r
+ retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id); \r
+ }\r
+\r
+ return retVal;\r
+}\r
+\r
+/** Clears GIRQ source bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ */\r
+void btimer_girq_src_clr(uint8_t btimer_id)\r
+{\r
+ if (btmr_valid(btimer_id))\r
+ {\r
+ //Note: Bit Position is same as Timer ID \r
+ p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id); \r
+ } \r
+}\r
+\r
+/** Returns GIRQ result bit for the timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @return uint8_t 0(result bit not set), Non-zero (result bit set)\r
+ */\r
+uint8_t btimer_girq_result_get(uint8_t btimer_id)\r
+{\r
+ uint8_t retVal;\r
+\r
+ retVal = 0;\r
+ if (btmr_valid(btimer_id))\r
+ {\r
+ //Note: Bit Position is same as Timer ID \r
+ retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id); \r
+ }\r
+\r
+ return retVal; \r
+}\r
+#endif\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Basic Timer Sleep */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Enable/Disable clock gating on idle of a timer \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param sleep_en 1 = Sleep enable, 0 = Sleep disable\r
+ */\r
+void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en)\r
+{\r
+ uint32_t pcr_blk_id;\r
+ \r
+ if ( btmr_valid(btimer_id) ) \r
+ { \r
+ pcr_blk_id = btmr_pcr_id[btimer_id]; \r
+ \r
+ pcr_sleep_enable(pcr_blk_id, sleep_en); \r
+ }\r
+}\r
+\r
+/** Returns clk required status for the timer block\r
+ * @param btimer_id Basic Timer ID.\r
+ * @return Non-zero if clk required, else 0\r
+ */\r
+uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id)\r
+{\r
+ uint32_t retVal;\r
+ uint32_t pcr_blk_id;\r
+ \r
+ retVal = 0ul; \r
+ if ( btmr_valid(btimer_id) ) \r
+ { \r
+ pcr_blk_id = btmr_pcr_id[btimer_id];\r
+ \r
+ retVal = pcr_clock_reqd_status_get(pcr_blk_id); \r
+ }\r
+ \r
+ return retVal;\r
+}\r
+\r
+/** Enable/Disable reset on sleep for the timer block \r
+ * @param btimer_id Basic Timer ID.\r
+ * @param reset_en 1 to enable, 0 to disable\r
+ */\r
+void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en)\r
+{\r
+ uint32_t pcr_blk_id; \r
+ \r
+ if ( btmr_valid(btimer_id) ) \r
+ { \r
+ pcr_blk_id = btmr_pcr_id[btimer_id];\r
+ \r
+ pcr_reset_enable(pcr_blk_id, reset_en); \r
+ }\r
+}\r
+\r
+/* end btimer_api.c */\r
+\r
+/** @} //Peripheral Basic_Timer\r
+ */\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #2 $ \r
+$DateTime: 2015/11/24 06:27:00 $ \r
+$Author: amohandas $\r
+Last Change: Updated for tabs\r
+******************************************************************************/\r
+/** @file btimer_perphl.c\r
+* \brief Basic Timer Peripheral Source file\r
+* \author jvasanth\r
+* \r
+* This file implements the Basic Timer Peripheral functions \r
+******************************************************************************/\r
+\r
+/** @defgroup Basic_Timer\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "btimer.h"\r
+\r
+/** Basic Timer Instance base addresses */\r
+static TIMER_16_0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = {\r
+ CEC1302_TIMER_16_0,\r
+ CEC1302_TIMER_16_1,\r
+ CEC1302_TIMER_16_2,\r
+ CEC1302_TIMER_16_3,\r
+ CEC1302_TIMER_32_0,\r
+ CEC1302_TIMER_32_1\r
+};\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to set and read Timer Counter Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Sets timer counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @param count - 32-bit counter \r
+ */\r
+void p_btimer_count_set(uint8_t btimer_id, uint32_t count)\r
+{\r
+ btmr_inst[btimer_id]->COUNT = count; \r
+}\r
+\r
+/** Read the timer counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @return count - 32-bit counter \r
+ */\r
+uint32_t p_btimer_count_get(uint8_t btimer_id)\r
+{ \r
+ return btmr_inst[btimer_id]->COUNT; \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to program the Preload */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Sets preload for the counter\r
+ * @param btimer_id Basic Timer ID\r
+ * @param preload_count - 32-bit pre-load value \r
+ */\r
+void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count)\r
+{\r
+ btmr_inst[btimer_id]->PRE_LOAD = preload_count; \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for basic timer interrupts */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the interrupt status bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ * @return status - 1 if interrupt status set, else 0\r
+ */\r
+uint8_t p_btimer_int_status_get(uint8_t btimer_id)\r
+{\r
+ return (uint8_t)(btmr_inst[btimer_id]->INTERRUPT_STATUS);\r
+}\r
+\r
+/** Clears interrupt status bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_status_clr(uint8_t btimer_id)\r
+{\r
+ // Write 1 to clear\r
+ btmr_inst[btimer_id]->INTERRUPT_STATUS = 1;\r
+}\r
+\r
+/** Sets interrupt enable bit in the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_enable_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->INTERRUPT_ENABLE = 1;\r
+}\r
+\r
+/** Clears interrupt enable bit for the timer block\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_int_enable_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->INTERRUPT_ENABLE = 0;\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Control Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Writes the control register 32-bits\r
+ * @param btimer_id Basic Timer ID\r
+ * @param value - 32-bit value to program\r
+ */\r
+void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.w = value;\r
+}\r
+\r
+/** Reads the control register \r
+ * @param btimer_id Basic Timer ID\r
+ * @return uint32_t - 32-bit value\r
+ */\r
+uint32_t p_btimer_ctrl_read(uint8_t btimer_id)\r
+{ \r
+ uint32_t retVal;\r
+\r
+ retVal = btmr_inst[btimer_id]->CONTROL.w;\r
+\r
+ return retVal;\r
+}\r
+\r
+/** Sets enable bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_enable_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE;\r
+}\r
+\r
+/** Clears enable bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_enable_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE;\r
+}\r
+\r
+/** Sets counter direction bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP;\r
+}\r
+\r
+/** Clears counter direction bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP;\r
+}\r
+\r
+/** Sets auto restart bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART;\r
+}\r
+\r
+/** Clears auto resetart bit in the control register\r
+ * @param btimer_id Basic Timer ID\r
+ */\r
+void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART;\r
+}\r
+\r
+/** Sets soft reset bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET;\r
+}\r
+\r
+/** Read Soft Reset bit \r
+ * @param btimer_id Basic Timer ID\r
+ * @return 0 if soft reset status bit cleared; else non-zero value\r
+ */\r
+uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id)\r
+{ \r
+ return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET);\r
+}\r
+\r
+/** Sets start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_start_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START;\r
+}\r
+\r
+/** Read start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ * @return 0 if start bit not set; else non-zero value\r
+ */\r
+uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id)\r
+{ \r
+ return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START);\r
+}\r
+\r
+/** Clears start bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_start_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START;\r
+}\r
+\r
+/** Sets reload bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_reload_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD;\r
+}\r
+\r
+/** Clears reload bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_reload_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD;\r
+}\r
+\r
+/** Sets halt bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_halt_set(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT;\r
+}\r
+\r
+/** Clears halt bit in the control register\r
+ * @param btimer_id Basic Timer ID \r
+ */\r
+void p_btimer_ctrl_halt_clr(uint8_t btimer_id)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT;\r
+}\r
+\r
+/** Sets prescale value\r
+ * @param btimer_id Basic Timer ID\r
+ * @param prescaler - 16-bit pre-scale value \r
+ */\r
+void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler)\r
+{ \r
+ btmr_inst[btimer_id]->CONTROL.h[1] = prescaler;\r
+}\r
+\r
+\r
+/* end btimer_perphl.c */\r
+\r
+/** @} //Peripheral Basic_Timer\r
+ */\r
+\r
--- /dev/null
+/*\r
+ **********************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+ **********************************************************************************\r
+ * common.h\r
+ * This is the header file including common headers from various modules\r
+ **********************************************************************************\r
+ * $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $\r
+ * Description: added ict module\r
+ **********************************************************************************\r
+ * #xx\r
+ **********************************************************************************\r
+ * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common.h $\r
+ */\r
+\r
+/*********************************************************************************/\r
+/** @defgroup common common\r
+ * @{\r
+ */\r
+\r
+/** @file common.h\r
+* \brief header file including common headers from various modules\r
+* \author App Firmware Team\r
+* \r
+**********************************************************************************/\r
+#ifndef _COMMON_H_\r
+#define _COMMON_H_\r
+\r
+// Include common headers from various modules\r
+// !!! The include order is important !!!\r
+#include "cfg.h"\r
+#include "platform.h"\r
+#include "MCHP_CEC1302.h"\r
+#include "ARM_REG.h"\r
+/* Cortex-M4 processor and core peripherals */\r
+#include "core_cm4.h" \r
+#include "MEC1322.h"\r
+\r
+#include "defs.h"\r
+#include "string.h"\r
+\r
+#include "kernel.h"\r
+#include "..\system\system.h"\r
+#include "..\debug\trace.h"\r
+#include "..\interrupt\interrupt.h"\r
+#include "..\timer\timer_app.h"\r
+\r
+#include "cec1302_crypto_api.h"\r
+\r
+#endif /*_COMMON_H_*/\r
+\r
+/** @}\r
+ */\r
+\r
+\r
--- /dev/null
+/*\r
+ **********************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+ **********************************************************************************\r
+ * common.h\r
+ * This is the header file including common headers from various modules\r
+ **********************************************************************************\r
+ * $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $\r
+ * Description: added ict module\r
+ **********************************************************************************\r
+ * #xx\r
+ **********************************************************************************\r
+ * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common_lib.h $\r
+ */\r
+\r
+/*********************************************************************************/\r
+/** @defgroup common common\r
+ * @{\r
+ */\r
+\r
+/** @file common.h\r
+* \brief header file including common headers from various modules\r
+* \author App Firmware Team\r
+* \r
+**********************************************************************************/\r
+#ifndef _COMMON_LIB_H_\r
+#define _COMMON_LIB_H_\r
+\r
+// Include common headers from various modules\r
+// !!! The include order is important !!!\r
+#include "platform.h"\r
+#include "ARM_REG.h"\r
+#include "MCHP_CEC1302.h"\r
+/* Cortex-M4 processor and core peripherals */\r
+#include "core_cm4.h" \r
+#include "MEC1322.h"\r
+#include "defs.h"\r
+#include "string.h"\r
+//_RB_#include "build.h"\r
+//_RB_#include "..\system\system.h"\r
+//_RB_#include "..\debug\trace.h"\r
+#include <stdbool.h>\r
+#endif /*_COMMON_LIB_H_*/\r
+\r
+/** @}\r
+ */\r
+\r
+\r
--- /dev/null
+/*\r
+ **********************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+ **********************************************************************************\r
+ * defs.h\r
+ * This is the definition header file for generic usages\r
+ **********************************************************************************\r
+ * #xx\r
+ **********************************************************************************\r
+ * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/defs.h $\r
+ */\r
+\r
+\r
+/*********************************************************************************/\r
+/** @defgroup defs defs\r
+ * @{\r
+ */\r
+\r
+/** @file defs.h\r
+* \brief definition header file for generic usages\r
+* \author App Firmware Team\r
+* \r
+**********************************************************************************/\r
+#ifndef _DEFS_H_\r
+#define _DEFS_H_\r
+\r
+/* bit operation MACRO, xvar could be byte, word or dword */\r
+#define mSET_BIT(x, xvar) ( xvar |= x )\r
+#define mCLR_BIT(x, xvar) ( xvar &= ~x )\r
+#define mGET_BIT(x, xvar) ( xvar & x )\r
+#define mCLR_SRC_BIT(x, xvar) ( xvar = x )\r
+#define mTOGGLE_BIT(x, xvar) {if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}}\r
+\r
+#endif /*_DEFS_H_*/\r
+\r
+/** @}\r
+ */\r
+\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2015/12/17 01:09:00 $ \r
+$Author: snakka $\r
+Last Change: Updated for peripheral functions prefix p_\r
+******************************************************************************/\r
+/** @file btimer.h\r
+* \brief Hibernation Timer Peripheral Header file\r
+* \author jvasanth\r
+* \r
+* This file is the header file for Hibernation Timer Peripheral \r
+******************************************************************************/\r
+\r
+/** @defgroup Hibernation_Timer\r
+ * @{\r
+ */\r
+\r
+#ifndef _HTIMER_H\r
+#define _HTIMER_H\r
+\r
+/******************************************************************************/\r
+/** Logical Timer ID for APIs.\r
+ * This is the timer IDs passed to Hibernation Timer function calls \r
+ *******************************************************************************/\r
+enum _PID_HTIMER_\r
+{\r
+ PID_HTIMER_0, \r
+ PID_HTIMER_MAX \r
+};\r
+\r
+#define HTIMER_MAX_INSTANCE PID_HTIMER_MAX\r
+\r
+/* -------------------------------------------------------------------- */\r
+/* Hibernation Timer APIs */\r
+/* -------------------------------------------------------------------- */\r
+/** Enables hibernation timer\r
+ * @param htimer_id Hibernation Timer ID\r
+ * @param preload_value - 16-bit preload value \r
+ * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
+ * 1 - resolution of 0.125s per LSB\r
+ */\r
+void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode);\r
+\r
+/** Disables the hibernation timer by programming the prelaod value as 0\r
+ * @param htimer_id Hibernation Timer ID \r
+ */\r
+void htimer_disable(uint8_t htimer_id);\r
+\r
+\r
+/** Reloads new preload value for the hibernation timer\r
+ * @param htimer_id Hibernation Timer ID\r
+ * @param reload_value - 16-bit preload value \r
+ */\r
+void htimer_reload(uint8_t htimer_id, uint16_t reload_value);\r
+\r
+\r
+/* -------------------------------------------------------------------- */\r
+/* Hibernation Timer Peripheral Functions */\r
+/* -------------------------------------------------------------------- */\r
+/** Sets hibernation timer preload value\r
+ * @param htimer_id Hibernation Timer ID\r
+ * @param preload_value - 16-bit preload value \r
+ */\r
+void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value);\r
+\r
+/*_RB_ Added by RB. */\r
+uint16_t p_htimer_preload_get(uint8_t htimer_id);\r
+\r
+/** Sets hibernation timer resolution\r
+ * @param htimer_id Hibernation Timer ID\r
+ * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
+ * 1 - resolution of 0.125s per LSB\r
+ */\r
+void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode);\r
+\r
+\r
+/** Returns the Hibernation Timer current count value\r
+ * @param htimer_id Hibernation Timer ID\r
+ * @return 16-bit count value \r
+ */\r
+uint16_t p_htimer_count_get(uint8_t htimer_id);\r
+\r
+\r
+#endif // #ifndef _HTIMER_H\r
+\r
+/* end htimer.h */\r
+\r
+/** @} //Peripherals Hibernation_Timer\r
+ */\r
+\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2015/12/17 01:09:00 $ \r
+$Author: snakka $\r
+Last Change: Updated for peripheral functions prefix p_\r
+******************************************************************************/\r
+/** @file btimer_perphl.c\r
+* \brief Hibernation Timer API Source file\r
+* \author jvasanth\r
+* \r
+* This file implements Hibernation Timer APIs \r
+******************************************************************************/\r
+\r
+/** @defgroup Hibernation_Timer\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "htimer.h"\r
+\r
+#ifdef PLIB_HTIMER_CHECK_ID\r
+\r
+/** Local helper that checks if logical Timer ID is valid. \r
+ * @param htimer_id Hibernation Timer ID \r
+ * @return uint8_t Non-zero(VALID), 0(Invalid)\r
+ */\r
+static uint8_t htmr_valid(uint8_t htimer_id)\r
+{\r
+ if ( htimer_id < (PID_HTIMER_MAX ) ) {\r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+#else\r
+\r
+\r
+/** This version of tmr_valid skips checking always returning 1. \r
+ * Compiler may optimize it out.\r
+ * @param htimer_id Hibernation Timer ID\r
+ * @return uint8_t 1(VALID) \r
+ */\r
+static uint8_t htmr_valid(uint8_t htimer_id) { return 1; }\r
+\r
+#endif\r
+\r
+\r
+/** Enables hibernation timer\r
+ * @param htimer_id Hibernation Timer ID\r
+ * @param preload_value - 16-bit preload value \r
+ * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
+ * 1 - resolution of 0.125s per LSB\r
+ */\r
+void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode)\r
+{\r
+ if (htmr_valid(htimer_id)) \r
+ {\r
+ p_htimer_preload_set(htimer_id, preload_value);\r
+ \r
+ p_htimer_resolution_set(htimer_id, resolution_mode);\r
+ } \r
+}\r
+\r
+/** Disables the hibernation timer by programming the prelaod value as 0\r
+ * @param htimer_id Hibernation Timer ID \r
+ */\r
+void htimer_disable(uint8_t htimer_id)\r
+{ \r
+ if (htmr_valid(htimer_id)) \r
+ {\r
+ p_htimer_preload_set(htimer_id, 0);\r
+ } \r
+}\r
+\r
+/** Reloads new preload value for the hibernation timer\r
+ * @param htimer_id Hibernation Timer ID\r
+ * @param reload_value - 16-bit preload value \r
+ */\r
+void htimer_reload(uint8_t htimer_id, uint16_t reload_value)\r
+{ \r
+ if ( htmr_valid(htimer_id)) \r
+ {\r
+ p_htimer_preload_set(htimer_id, reload_value);\r
+ } \r
+}\r
+\r
+/* end htimer_api.c */\r
+\r
+/** @} //APIs Hibernation_Timer\r
+ */\r
+\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2015/12/17 01:09:00 $ \r
+$Author: snakka $\r
+Last Change: Updated for peripheral functions prefix p_\r
+******************************************************************************/\r
+/** @file btimer_perphl.c\r
+* \brief Hibernation Timer Peripheral Source file\r
+* \author jvasanth\r
+* \r
+* This file implements Hibernation Timer Peripheral functions \r
+******************************************************************************/\r
+\r
+/** @defgroup Hibernation_Timer\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "htimer.h"\r
+\r
+/** Hibernation Timer Instance base addresses */\r
+static HTM_Type * const htmr_inst[HTIMER_MAX_INSTANCE] = {\r
+ CEC1302_HTM \r
+};\r
+\r
+/** Sets hibernation timer preload value\r
+ * @param htimer_id Hibernation Timer ID\r
+ * @param preload_value - 16-bit preload value \r
+ * @note Setting the preload with a non-zero value starts \r
+ * the hibernation timer to down count. Setting the preload \r
+ * to 0 disables the hibernation counter\r
+ */\r
+void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value)\r
+{\r
+ htmr_inst[htimer_id]->PRELOAD = preload_value; \r
+}\r
+\r
+/** Sets hibernation timer resolution\r
+ * @param htimer_id Hibernation Timer ID\r
+ * @param resolution_mode 0 - resolution of 30.5us per LSB, \r
+ * 1 - resolution of 0.125s per LSB\r
+ */\r
+void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode)\r
+{\r
+ htmr_inst[htimer_id]->CONTROL = resolution_mode; \r
+}\r
+\r
+/** Returns the Hibernation Timer current count value\r
+ * @param htimer_id Hibernation Timer ID\r
+ * @return 16-bit count value \r
+ */\r
+uint16_t p_htimer_count_get(uint8_t htimer_id)\r
+{\r
+ uint16_t htimer_count;\r
+ \r
+ htimer_count = htmr_inst[htimer_id]->COUNT;\r
+ \r
+ return htimer_count;\r
+}\r
+\r
+/*_RB_ Added by RB. */\r
+uint16_t p_htimer_preload_get(uint8_t htimer_id)\r
+{\r
+ return htmr_inst[htimer_id]->PRELOAD;\r
+}\r
+\r
+\r
+/* end htimer_perphl.c */\r
+\r
+/** @} //Peripheral Hibernation_Timer\r
+ */\r
+\r
--- /dev/null
+/****************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+*/\r
+\r
+/** @defgroup interrupt interrupt\r
+ * @{\r
+ */\r
+/** @file interrupt.h\r
+ \brief This is the header file for interrupt.c\r
+ This program is designed to allow the other C programs to be able to use this component\r
+\r
+ There are entry points for all C wrapper API implementation\r
+\r
+<b>Platform:</b> This is ARC-based component \r
+\r
+<b>Toolset:</b> Metaware IDE(8.5.1)\r
+<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
+\r
+/*******************************************************************************\r
+ * SMSC version control information (Perforce):\r
+ *\r
+ * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/kernel/skern/source/interrupt/interrupt.h $\r
+ * REVISION: $Revision: #1 $\r
+ * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
+ * AUTHOR: $Author: akrishnan $\r
+ *\r
+ * Revision history (latest first):\r
+ * #xx\r
+ ***********************************************************************************\r
+ */\r
+\r
+#ifndef _INTERRUPT_H_\r
+#define _INTERRUPT_H_\r
+\r
+\r
+/* public function prototypes */\r
+void interrupt_block_init(void);\r
+void null_handler(void);\r
+\r
+/* macro for interrupt control */\r
+/* 16-bit timers interrupt control */\r
+#define sbit_TIMER0 ( 1UL << 0UL )\r
+#define sbit_TIMER1 ( 1UL << 1UL )\r
+#define sbit_TIMER2 ( 1UL << 2UL )\r
+#define sbit_TIMER3 ( 1UL << 3Ul )\r
+\r
+#define disable_timer0_irq() mCLR_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define enable_timer0_irq() mSET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define clear_timer0_source() mCLR_SRC_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE)\r
+#define get_timer0_source() mGET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE)\r
+\r
+#define disable_timer1_irq() mCLR_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define enable_timer1_irq() mSET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define clear_timer1_source() mCLR_SRC_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE)\r
+#define get_timer1_source() mGET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE)\r
+\r
+#define disable_timer2_irq() mCLR_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define enable_timer2_irq() mSET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define clear_timer2_source() mCLR_SRC_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE)\r
+#define get_timer2_source() mGET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE)\r
+\r
+#define disable_timer3_irq() mCLR_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define enable_timer3_irq() mSET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define clear_timer3_source() mCLR_SRC_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE)\r
+#define get_timer3_source() mGET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE)\r
+\r
+\r
+/* hibernation timers interrupt control */\r
+#define sbit_HTIMER0 ( 1UL << 20 )\r
+#define sbit_HTIMER1 b_bit14\r
+\r
+#define disable_htimer0_irq() mCLR_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET)\r
+#define enable_htimer0_irq() mSET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET)\r
+#define clear_htimer0_source() mCLR_SRC_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE)\r
+#define get_htimer0_source() mGET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE)\r
+\r
+#define disable_htimer1_irq() mCLR_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define enable_htimer1_irq() mSET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define clear_htimer1_source() mCLR_SRC_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE)\r
+#define get_htimer1_source() mGET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE)\r
+\r
+/* RTC interrupt control */\r
+#define b_bit18 (1 << 18)\r
+#define b_bit19 (1 << 19)\r
+#define sbit_RTC_INT b_bit18\r
+#define disable_rtc_irq() mCLR_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
+#define enable_rtc_irq() mSET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
+#define clear_rtc_irq_source() mCLR_SRC_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
+#define get_rtc_irq_source() mGET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
+/* RTC alarm interrupt control */\r
+#define sbit_RTC_ALM_INT b_bit19\r
+#define disable_rtc_alm_irq() mCLR_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
+#define enable_rtc_alm_irq() mSET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
+#define clear_rtc_irq_alm_source() mCLR_SRC_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
+#define get_rtc_irq_alm_source() mGET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET)\r
+\r
+/* week timer interrupt control */\r
+#define sbit_WKTIMER b_bit7\r
+\r
+#define disable_wktimer_irq() mCLR_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define enable_wktimer_irq() mSET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define clear_wktimer_source() mCLR_SRC_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE)\r
+#define get_wktimer_source() mGET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE)\r
+\r
+\r
+/* scan matrix interrupt control */\r
+#define sbit_SCANNER b_bit16\r
+#define disable_scanner_irq() mCLR_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET)\r
+#define enable_scanner_irq() mSET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET)\r
+#define clear_scanner_source() mCLR_SRC_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE)\r
+#define get_scanner_source() mGET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE)\r
+\r
+\r
+/* PS2 interrupt control */\r
+/* PS2 activity interrupt */\r
+#define sbit_PS2_ACT_0 b_bit13\r
+#define sbit_PS2_ACT_1 b_bit14\r
+#define sbit_PS2_ACT_2 b_bit15\r
+/* PS2 wakeup interrupt: detect start bit */\r
+#define sbit_PS2_WK_0A b_bit17\r
+#define sbit_PS2_WK_1B b_bit20\r
+#define sbit_PS2_WK_2 b_bit21\r
+\r
+/* PS2 activity interrupt control */\r
+#define disable_ps2_act_0_irq() mCLR_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define enable_ps2_act_0_irq() mSET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define clear_ps2_act_0_source() mCLR_SRC_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE)\r
+#define get_ps2_act_0_source() mGET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE)\r
+\r
+#define disable_ps2_act_1_irq() mCLR_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define enable_ps2_act_1_irq() mSET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define clear_ps2_act_1_source() mCLR_SRC_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE)\r
+#define get_ps2_act_1_source() mGET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE)\r
+\r
+#define disable_ps2_act_2_irq() mCLR_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define enable_ps2_act_2_irq() mSET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define clear_ps2_act_2_source() mCLR_SRC_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE)\r
+#define get_ps2_act_2_source() mGET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE)\r
+\r
+/* PS2 wakeup interrupt control */\r
+#define disable_ps2_wk_0_irq() mCLR_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define enable_ps2_wk_0_irq() mSET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define clear_ps2_wk_0_source() mCLR_SRC_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE)\r
+#define get_ps2_wk_0_source() mGET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE)\r
+\r
+#define disable_ps2_wk_1_irq() mCLR_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define enable_ps2_wk_1_irq() mSET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define clear_ps2_wk_1_source() mCLR_SRC_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE)\r
+#define get_ps2_wk_1_source() mGET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE)\r
+\r
+#define disable_ps2_wk_2_irq() mCLR_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define enable_ps2_wk_2_irq() mSET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET)\r
+#define clear_ps2_wk_2_source() mCLR_SRC_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE)\r
+#define get_ps2_wk_2_source() mGET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE)\r
+\r
+\r
+/* ICT interrupt control */\r
+/* capture 0~5 interrupt */\r
+#define sbit_ICT_CAPTURE0 b_bit17\r
+#define sbit_ICT_CAPTURE1 b_bit18\r
+#define sbit_ICT_CAPTURE2 b_bit19\r
+#define sbit_ICT_CAPTURE3 b_bit20\r
+#define sbit_ICT_CAPTURE4 b_bit21\r
+#define sbit_ICT_CAPTURE5 b_bit22\r
+\r
+/* capture 0 interrupt control */\r
+#define disable_capture0_irq() mCLR_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define enable_capture0_irq() mSET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET)\r
+#define clear_capture0_source() mCLR_SRC_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE)\r
+#define get_capture0_source() mGET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE)\r
+\r
+\r
+/* SMBus interrupt control */\r
+\r
+\r
+/* GPIO interrupt control */\r
+\r
+\r
+/* BC link interrupt control */\r
+/* bclink A~D interrupt */\r
+#define sbit_BCLINK_A_BUSY b_bit0\r
+#define sbit_BCLINK_A_ERR b_bit1\r
+#define sbit_BCLINK_A_INT b_bit2\r
+#define sbit_BCLINK_B_BUSY b_bit3\r
+#define sbit_BCLINK_B_ERR b_bit4\r
+#define sbit_BCLINK_B_INT b_bit5\r
+#define sbit_BCLINK_C_BUSY b_bit6\r
+#define sbit_BCLINK_C_ERR b_bit7\r
+#define sbit_BCLINK_C_INT b_bit8\r
+#define sbit_BCLINK_D_BUSY b_bit9\r
+#define sbit_BCLINK_D_ERR b_bit10\r
+#define sbit_BCLINK_D_INT b_bit11\r
+\r
+/* bclink B interrupt control */\r
+#define disable_bclink_b_busy_irq() mCLR_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET)\r
+#define enable_bclink_b_busy_irq() mSET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET)\r
+#define clear_bclink_b_busy_source() mCLR_SRC_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE)\r
+#define get_bclink_b_busy_source() mGET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE)\r
+\r
+#define disable_bclink_b_err_irq() mCLR_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET)\r
+#define enable_bclink_b_err_irq() mSET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET)\r
+#define clear_bclink_b_err_source() mCLR_SRC_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE)\r
+#define get_bclink_b_err_source() mGET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE)\r
+\r
+#define disable_bclink_b_int_irq() mCLR_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET)\r
+#define enable_bclink_b_int_irq() mSET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET)\r
+#define clear_bclink_b_int_source() mCLR_SRC_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE)\r
+#define get_bclink_b_int_source() mGET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE)\r
+\r
+/* UART interrupt control */\r
+#define sbit_UART_INT b_bit0\r
+\r
+#define disable_uart_irq() mCLR_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET)\r
+#define enable_uart_irq() mSET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET)\r
+#define clear_uart_irq_source() mCLR_SRC_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE)\r
+#define get_uart_irq_source() mGET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE)\r
+\r
+// GIRQ IDs for EC Interrupt Aggregator\r
+enum MEC_GIRQ_IDS\r
+{\r
+ MEC_GIRQ08_ID = 0,\r
+ MEC_GIRQ09_ID, \r
+ MEC_GIRQ10_ID, \r
+ MEC_GIRQ11_ID, \r
+ MEC_GIRQ12_ID, \r
+ MEC_GIRQ13_ID, \r
+ MEC_GIRQ14_ID, \r
+ MEC_GIRQ15_ID, \r
+ MEC_GIRQ16_ID, \r
+ MEC_GIRQ17_ID, \r
+ MEC_GIRQ18_ID, \r
+ MEC_GIRQ19_ID, \r
+ MEC_GIRQ20_ID, \r
+ MEC_GIRQ21_ID, \r
+ MEC_GIRQ22_ID, \r
+ MEC_GIRQ23_ID, \r
+ MEC_GIRQ_ID_MAX\r
+};\r
+\r
+//Bitmask of GIRQ in ECIA Block Registers\r
+#define MEC_GIRQ08_BITMASK (1UL << (MEC_GIRQ08_ID + 8))\r
+#define MEC_GIRQ09_BITMASK (1UL << (MEC_GIRQ09_ID + 8)) \r
+#define MEC_GIRQ10_BITMASK (1UL << (MEC_GIRQ10_ID + 8)) \r
+#define MEC_GIRQ11_BITMASK (1UL << (MEC_GIRQ11_ID + 8)) \r
+#define MEC_GIRQ12_BITMASK (1UL << (MEC_GIRQ12_ID + 8)) \r
+#define MEC_GIRQ13_BITMASK (1UL << (MEC_GIRQ13_ID + 8)) \r
+#define MEC_GIRQ14_BITMASK (1UL << (MEC_GIRQ14_ID + 8)) \r
+#define MEC_GIRQ15_BITMASK (1UL << (MEC_GIRQ15_ID + 8)) \r
+#define MEC_GIRQ16_BITMASK (1UL << (MEC_GIRQ16_ID + 8)) \r
+#define MEC_GIRQ17_BITMASK (1UL << (MEC_GIRQ17_ID + 8)) \r
+#define MEC_GIRQ18_BITMASK (1UL << (MEC_GIRQ18_ID + 8)) \r
+#define MEC_GIRQ19_BITMASK (1UL << (MEC_GIRQ19_ID + 8)) \r
+#define MEC_GIRQ20_BITMASK (1UL << (MEC_GIRQ20_ID + 8)) \r
+#define MEC_GIRQ21_BITMASK (1UL << (MEC_GIRQ21_ID + 8)) \r
+#define MEC_GIRQ22_BITMASK (1UL << (MEC_GIRQ22_ID + 8)) \r
+#define MEC_GIRQ23_BITMASK (1UL << (MEC_GIRQ23_ID + 8)) \r
+\r
+#define INTERRUPT_MODE_ALL_AGGREGATED (0u)\r
+#define INTERRUPT_MODE_DIRECT (1u)\r
+\r
+// Bit map of GIRQs whose sources can be directly connected to the NVIC\r
+// GIRQs 12 - 18, 23\r
+#define ECIA_GIRQ_DIRECT_BITMAP (0x0087F000ul)\r
+\r
+/*\r
+ * n = b[7:0] = zero-based direct mapped NVIC ID\r
+ * m = b[15:8] = zero-based aggregated NVIC ID\r
+ * a = b[23:16] = block Aggregator register block ID\r
+ * b = b[31:24] = block bit position in Aggregator registers\r
+*/\r
+#define IROUTE(b,a,m,n) (((uint32_t)(n)&0xFFul) + \\r
+ (((uint32_t)(m)&0xFFul)<<8u) + \\r
+ ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \\r
+ (((uint32_t)(b)&0x1Ful)<<24))\r
+\r
+#define ECIA_NVIC_ID_BITPOS (0u)\r
+#define ECIA_IA_NVIC_ID_BITPOS (8u)\r
+#define ECIA_GIRQ_ID_BITPOS (16u)\r
+#define ECIA_GIRQ_BIT_BITPOS (24u)\r
+\r
+//\r
+// GIRQ08\r
+//\r
+#define GPIO_0140_IROUTE IROUTE(0,8,57,57)\r
+#define GPIO_0141_IROUTE IROUTE(1,8,57,57)\r
+#define GPIO_0142_IROUTE IROUTE(2,8,57,57)\r
+#define GPIO_0143_IROUTE IROUTE(3,8,57,57)\r
+#define GPIO_0144_IROUTE IROUTE(4,8,57,57)\r
+#define GPIO_0145_IROUTE IROUTE(5,8,57,57)\r
+#define GPIO_0147_IROUTE IROUTE(7,8,57,57)\r
+//\r
+#define GPIO_0150_IROUTE IROUTE(8,8,57,57)\r
+#define GPIO_0151_IROUTE IROUTE(9,8,57,57)\r
+#define GPIO_0152_IROUTE IROUTE(10,8,57,57)\r
+#define GPIO_0153_IROUTE IROUTE(11,8,57,57)\r
+#define GPIO_0154_IROUTE IROUTE(12,8,57,57)\r
+#define GPIO_0155_IROUTE IROUTE(13,8,57,57)\r
+#define GPIO_0156_IROUTE IROUTE(14,8,57,57)\r
+#define GPIO_0157_IROUTE IROUTE(15,8,57,57)\r
+//\r
+#define GPIO_0160_IROUTE IROUTE(16,8,57,57)\r
+#define GPIO_0161_IROUTE IROUTE(17,8,57,57)\r
+#define GPIO_0162_IROUTE IROUTE(18,8,57,57)\r
+#define GPIO_0163_IROUTE IROUTE(19,8,57,57)\r
+#define GPIO_0164_IROUTE IROUTE(20,8,57,57)\r
+#define GPIO_0165_IROUTE IROUTE(21,8,57,57)\r
+#define GPIO_0166_IROUTE IROUTE(22,8,57,57)\r
+#define GPIO_0167_IROUTE IROUTE(23,8,57,57)\r
+\r
+//\r
+// GIRQ09\r
+//\r
+#define GPIO_0100_IROUTE IROUTE(0,9,58,58)\r
+#define GPIO_0101_IROUTE IROUTE(1,9,58,58)\r
+#define GPIO_0102_IROUTE IROUTE(2,9,58,58)\r
+#define GPIO_0103_IROUTE IROUTE(3,9,58,58)\r
+#define GPIO_0104_IROUTE IROUTE(4,9,58,58)\r
+#define GPIO_0105_IROUTE IROUTE(5,9,58,58)\r
+#define GPIO_0105_IROUTE IROUTE(5,9,58,58)\r
+#define GPIO_0107_IROUTE IROUTE(7,9,58,58)\r
+//\r
+#define GPIO_0110_IROUTE IROUTE(8,9,58,58)\r
+#define GPIO_0111_IROUTE IROUTE(9,9,58,58)\r
+#define GPIO_0112_IROUTE IROUTE(10,9,58,58)\r
+#define GPIO_0113_IROUTE IROUTE(11,9,58,58)\r
+#define GPIO_0114_IROUTE IROUTE(12,9,58,58)\r
+#define GPIO_0115_IROUTE IROUTE(13,9,58,58)\r
+#define GPIO_0116_IROUTE IROUTE(14,9,58,58)\r
+#define GPIO_0117_IROUTE IROUTE(15,9,58,58)\r
+//\r
+#define GPIO_0120_IROUTE IROUTE(16,9,58,58)\r
+#define GPIO_0121_IROUTE IROUTE(17,9,58,58)\r
+#define GPIO_0122_IROUTE IROUTE(18,9,58,58)\r
+#define GPIO_0124_IROUTE IROUTE(20,9,58,58)\r
+#define GPIO_0125_IROUTE IROUTE(21,9,58,58)\r
+#define GPIO_0126_IROUTE IROUTE(22,9,58,58)\r
+#define GPIO_0127_IROUTE IROUTE(23,9,58,58)\r
+//\r
+#define GPIO_0130_IROUTE IROUTE(24,9,58,58)\r
+#define GPIO_0131_IROUTE IROUTE(25,9,58,58)\r
+#define GPIO_0132_IROUTE IROUTE(26,9,58,58)\r
+#define GPIO_0133_IROUTE IROUTE(27,9,58,58)\r
+#define GPIO_0134_IROUTE IROUTE(28,9,58,58)\r
+#define GPIO_0135_IROUTE IROUTE(29,9,58,58)\r
+#define GPIO_0136_IROUTE IROUTE(30,9,58,58)\r
+\r
+//\r
+// GIRQ10\r
+//\r
+#define GPIO_0040_IROUTE IROUTE(0,10,59,59)\r
+#define GPIO_0041_IROUTE IROUTE(1,10,59,59)\r
+#define GPIO_0042_IROUTE IROUTE(2,10,59,59)\r
+#define GPIO_0043_IROUTE IROUTE(3,10,59,59)\r
+#define GPIO_0044_IROUTE IROUTE(4,10,59,59)\r
+#define GPIO_0045_IROUTE IROUTE(5,10,59,59)\r
+#define GPIO_0045_IROUTE IROUTE(5,10,59,59)\r
+#define GPIO_0047_IROUTE IROUTE(7,10,59,59)\r
+//\r
+#define GPIO_0050_IROUTE IROUTE(8,10,59,59)\r
+#define GPIO_0051_IROUTE IROUTE(9,10,59,59)\r
+#define GPIO_0052_IROUTE IROUTE(10,10,59,59)\r
+#define GPIO_0053_IROUTE IROUTE(11,10,59,59)\r
+#define GPIO_0054_IROUTE IROUTE(12,10,59,59)\r
+#define GPIO_0055_IROUTE IROUTE(13,10,59,59)\r
+#define GPIO_0056_IROUTE IROUTE(14,10,59,59)\r
+#define GPIO_0057_IROUTE IROUTE(15,10,59,59)\r
+//\r
+#define GPIO_0060_IROUTE IROUTE(16,10,59,59)\r
+#define GPIO_0061_IROUTE IROUTE(17,10,59,59)\r
+#define GPIO_0062_IROUTE IROUTE(18,10,59,59)\r
+#define GPIO_0063_IROUTE IROUTE(19,10,59,59)\r
+#define GPIO_0064_IROUTE IROUTE(20,10,59,59)\r
+#define GPIO_0065_IROUTE IROUTE(21,10,59,59)\r
+#define GPIO_0066_IROUTE IROUTE(22,10,59,59)\r
+#define GPIO_0067_IROUTE IROUTE(23,10,59,59)\r
+//\r
+#define GPIO_0070_IROUTE IROUTE(24,10,59,59)\r
+#define GPIO_0071_IROUTE IROUTE(25,10,59,59)\r
+#define GPIO_0072_IROUTE IROUTE(26,10,59,59)\r
+#define GPIO_0073_IROUTE IROUTE(27,10,59,59)\r
+#define GPIO_0074_IROUTE IROUTE(28,10,59,59)\r
+#define GPIO_0075_IROUTE IROUTE(29,10,59,59)\r
+#define GPIO_0076_IROUTE IROUTE(30,10,59,59)\r
+\r
+//\r
+// GIRQ11\r
+//\r
+#define GPIO_0000_IROUTE IROUTE(0,11,60,60)\r
+#define GPIO_0001_IROUTE IROUTE(1,11,60,60)\r
+#define GPIO_0002_IROUTE IROUTE(2,11,60,60)\r
+#define GPIO_0003_IROUTE IROUTE(3,11,60,60)\r
+#define GPIO_0004_IROUTE IROUTE(4,11,60,60)\r
+#define GPIO_0005_IROUTE IROUTE(5,11,60,60)\r
+#define GPIO_0006_IROUTE IROUTE(6,11,60,60)\r
+#define GPIO_0007_IROUTE IROUTE(7,11,60,60)\r
+//\r
+#define GPIO_0010_IROUTE IROUTE(8,11,60,60)\r
+#define GPIO_0011_IROUTE IROUTE(9,11,60,60)\r
+#define GPIO_0012_IROUTE IROUTE(10,11,60,60)\r
+#define GPIO_0013_IROUTE IROUTE(11,11,60,60)\r
+#define GPIO_0014_IROUTE IROUTE(12,11,60,60)\r
+#define GPIO_0015_IROUTE IROUTE(13,11,60,60)\r
+#define GPIO_0016_IROUTE IROUTE(14,11,60,60)\r
+#define GPIO_0017_IROUTE IROUTE(15,11,60,60)\r
+//\r
+#define GPIO_0020_IROUTE IROUTE(16,11,60,60)\r
+#define GPIO_0021_IROUTE IROUTE(17,11,60,60)\r
+#define GPIO_0022_IROUTE IROUTE(18,11,60,60)\r
+#define GPIO_0023_IROUTE IROUTE(19,11,60,60)\r
+#define GPIO_0024_IROUTE IROUTE(20,11,60,60)\r
+#define GPIO_0025_IROUTE IROUTE(21,11,60,60)\r
+#define GPIO_0026_IROUTE IROUTE(22,11,60,60)\r
+#define GPIO_0027_IROUTE IROUTE(23,11,60,60)\r
+//\r
+#define GPIO_0030_IROUTE IROUTE(24,11,60,60)\r
+#define GPIO_0031_IROUTE IROUTE(25,11,60,60)\r
+#define GPIO_0032_IROUTE IROUTE(26,11,60,60)\r
+#define GPIO_0033_IROUTE IROUTE(27,11,60,60)\r
+#define GPIO_0034_IROUTE IROUTE(28,11,60,60)\r
+#define GPIO_0035_IROUTE IROUTE(29,11,60,60)\r
+#define GPIO_0036_IROUTE IROUTE(30,11,60,60)\r
+\r
+//\r
+// GIRQ12\r
+//\r
+#define SMB0_IROUTE IROUTE(0,12,61,0)\r
+#define SMB1_IROUTE IROUTE(1,12,61,1)\r
+#define SMB2_IROUTE IROUTE(2,12,61,2)\r
+#define SMB3_IROUTE IROUTE(3,12,61,3)\r
+// SMB wakes have no direct connection to NVIC, always aggregated\r
+#define SMB0_WAKE_IROUTE IROUTE(4,12,61,61)\r
+#define SMB1_WAKE_IROUTE IROUTE(5,12,61,61)\r
+#define SMB2_WAKE_IROUTE IROUTE(6,12,61,61)\r
+#define SMB3_WAKE_IROUTE IROUTE(7,12,61,61)\r
+#define SMB4_WAKE_IROUTE IROUTE(8,12,61,61)\r
+\r
+//\r
+// GIRQ13\r
+//\r
+#define DMA0_IROUTE IROUTE(16,13,62,4)\r
+#define DMA1_IROUTE IROUTE(17,13,62,5)\r
+#define DMA2_IROUTE IROUTE(18,13,62,6)\r
+#define DMA3_IROUTE IROUTE(19,13,62,7)\r
+#define DMA4_IROUTE IROUTE(20,13,62,8)\r
+#define DMA5_IROUTE IROUTE(21,13,62,9)\r
+#define DMA6_IROUTE IROUTE(22,13,62,10)\r
+#define DMA7_IROUTE IROUTE(23,13,62,11)\r
+#define DMA8_IROUTE IROUTE(24,13,62,81)\r
+#define DMA9_IROUTE IROUTE(25,13,62,82)\r
+#define DMA10_IROUTE IROUTE(26,13,62,83)\r
+#define DMA11_IROUTE IROUTE(27,13,62,84)\r
+\r
+//\r
+// GIRQ14\r
+//\r
+#define LPC_BERR_IROUTE IROUTE(2,14,63,12)\r
+\r
+//\r
+// GIRQ15\r
+//\r
+#define UART0_IROUTE IROUTE(0,15,64,13)\r
+#define EMI0_IROUTE IROUTE(2,15,64,14)\r
+#define ACPI_EC0_IBF_IROUTE IROUTE(6,15,64,15)\r
+#define ACPI_EC0_OBF_IROUTE IROUTE(7,15,64,16)\r
+#define ACPI_EC1_IBF_IROUTE IROUTE(8,15,64,17)\r
+#define ACPI_EC1_OBF_IROUTE IROUTE(9,15,64,18)\r
+#define ACPI_PM1_CTL_IROUTE IROUTE(10,15,64,19)\r
+#define ACPI_PM1_EN_IROUTE IROUTE(11,15,64,20)\r
+#define ACPI_PM1_STS_IROUTE IROUTE(12,15,64,21)\r
+#define EM8042_OBF_IROUTE IROUTE(13,15,64,22)\r
+#define EM8042_IBF_IROUTE IROUTE(14,15,64,23)\r
+#define MBOX_IROUTE IROUTE(15,15,64,24)\r
+#define MBOX_DATA_IROUTE IROUTE(16,15,64,40) \r
+\r
+//\r
+// GIRQ16\r
+//\r
+#define PECI_IROUTE IROUTE(3,16,65,25)\r
+\r
+//\r
+// GIRQ17\r
+//\r
+#define TACH0_IROUTE IROUTE(0,17,66,26)\r
+#define TACH1_IROUTE IROUTE(1,17,66,27)\r
+#define PS2_0_WAKE_IROUTE IROUTE(2,17,66,66)\r
+#define PS2_1_WAKE_IROUTE IROUTE(3,17,66,66)\r
+#define PS2_2_WAKE_IROUTE IROUTE(4,17,66,66)\r
+#define PS2_3_WAKE_IROUTE IROUTE(5,17,66,66)\r
+#define BC_WAKE_IROUTE IROUTE(6,17,66,66)\r
+#define ADC_SNGL_IROUTE IROUTE(10,17,66,28)\r
+#define ADC_RPT_IROUTE IROUTE(11,17,66,29)\r
+#define ADC2PWM1_IROUTE IROUTE(12,17,66,30)\r
+#define ADC2PWM2_IROUTE IROUTE(13,17,66,31)\r
+#define PS2_0_IROUTE IROUTE(14,17,66,32)\r
+#define PS2_1_IROUTE IROUTE(15,17,66,33)\r
+#define PS2_2_IROUTE IROUTE(16,17,66,34)\r
+#define PS2_3_IROUTE IROUTE(17,17,66,35)\r
+#define RTC_IROUTE IROUTE(18,17,66,91)\r
+#define RTC_ALARM_IROUTE IROUTE(19,17,66,92)\r
+#define HTIMER_IROUTE IROUTE(20,17,66,38)\r
+#define KSC_IROUTE IROUTE(21,17,66,39)\r
+#define KSC_WAKE_IROUTE IROUTE(22,17,66,66)\r
+#define RPM_STALL_IROUTE IROUTE(23,17,66,41)\r
+#define RPM_SPIN_IROUTE IROUTE(24,17,66,42)\r
+#define PFR_IROUTE IROUTE(25,17,66,43)\r
+#define LED0_IROUTE IROUTE(26,17,66,44)\r
+#define LED1_IROUTE IROUTE(27,17,66,45)\r
+#define LED2_IROUTE IROUTE(28,17,66,46)\r
+#define BCM_ERR_IROUTE IROUTE(29,17,66,47)\r
+#define BCM_BUSY_IROUTE IROUTE(30,17,66,48)\r
+\r
+//\r
+// GIRQ18\r
+//\r
+#define SPI0_TX_IROUTE IROUTE(0,18,67,36)\r
+#define SPI0_RX_IROUTE IROUTE(1,18,67,37)\r
+#define SPI1_TX_IROUTE IROUTE(2,18,67,55)\r
+#define SPI1_RX_IROUTE IROUTE(3,18,67,56)\r
+#define LED3_IROUTE IROUTE(4,18,67,85)\r
+#define PKE_ERR_IROUTE IROUTE(5,18,67,86)\r
+#define PKE_END_IROUTE IROUTE(6,18,67,87)\r
+#define NDRNG_IROUTE IROUTE(7,18,67,88)\r
+#define AES_IROUTE IROUTE(8,18,67,89)\r
+#define HASH_IROUTE IROUTE(9,18,67,90)\r
+\r
+//\r
+// GIRQ19, Aggregated only\r
+//\r
+#define LRESET_IROUTE IROUTE(0,19,68,68)\r
+#define VCC_PWRGD_IROUTE IROUTE(1,19,68,68)\r
+\r
+//\r
+// GIRQ20, Aggregated only\r
+//\r
+#define GPIO_0200_IROUTE IROUTE(0,20,69,69)\r
+#define GPIO_0201_IROUTE IROUTE(1,20,69,69)\r
+#define GPIO_0202_IROUTE IROUTE(2,20,69,69)\r
+#define GPIO_0203_IROUTE IROUTE(3,20,69,69)\r
+#define GPIO_0204_IROUTE IROUTE(4,20,69,69)\r
+#define GPIO_0206_IROUTE IROUTE(6,20,69,69)\r
+//\r
+#define GPIO_0210_IROUTE IROUTE(8,20,69,69)\r
+#define GPIO_0211_IROUTE IROUTE(9,20,69,69)\r
+#define GPIO_0212_IROUTE IROUTE(10,20,69,69)\r
+#define GPIO_0213_IROUTE IROUTE(11,20,69,69)\r
+\r
+//\r
+// GIRQ21\r
+//\r
+// No sources\r
+\r
+//\r
+// GIRQ22\r
+//\r
+// No sources\r
+\r
+//\r
+// GIRQ23\r
+//\r
+#define BTMR0_IROUTE IROUTE(0,23,72,49)\r
+#define BTMR1_IROUTE IROUTE(1,23,72,50)\r
+#define BTMR2_IROUTE IROUTE(2,23,72,51)\r
+#define BTMR3_IROUTE IROUTE(3,23,72,52)\r
+#define BTMR4_IROUTE IROUTE(4,23,72,53)\r
+#define BTMR5_IROUTE IROUTE(5,23,72,54)\r
+\r
+// GIRQ08 Bit Positions \r
+#define GIRQ08_GPIO_0140_BITPOS (0)\r
+#define GIRQ08_GPIO_0141_BITPOS (1)\r
+#define GIRQ08_GPIO_0142_BITPOS (2)\r
+#define GIRQ08_GPIO_0143_BITPOS (3)\r
+#define GIRQ08_GPIO_0144_BITPOS (4)\r
+#define GIRQ08_GPIO_0145_BITPOS (5)\r
+//#define GIRQ08_GPIO_0146_BITPOS (6) RESERVED\r
+#define GIRQ08_GPIO_0147_BITPOS (7)\r
+//\r
+#define GIRQ08_GPIO_0150_BITPOS (8)\r
+#define GIRQ08_GPIO_0151_BITPOS (9)\r
+#define GIRQ08_GPIO_0152_BITPOS (10)\r
+#define GIRQ08_GPIO_0153_BITPOS (11)\r
+#define GIRQ08_GPIO_0154_BITPOS (12)\r
+#define GIRQ08_GPIO_0155_BITPOS (13)\r
+#define GIRQ08_GPIO_0156_BITPOS (14) \r
+#define GIRQ08_GPIO_0157_BITPOS (15)\r
+//\r
+#define GIRQ08_GPIO_0160_BITPOS (16)\r
+#define GIRQ08_GPIO_0161_BITPOS (17)\r
+#define GIRQ08_GPIO_0162_BITPOS (18)\r
+#define GIRQ08_GPIO_0163_BITPOS (19)\r
+#define GIRQ08_GPIO_0164_BITPOS (20)\r
+#define GIRQ08_GPIO_0165_BITPOS (21)\r
+#define GIRQ08_GPIO_0166_BITPOS (22) \r
+#define GIRQ08_GPIO_0167_BITPOS (23)\r
+//\r
+#define GIRQ08_MASK (0x00FFFFBFul)\r
+#define GIRQ08_WAKE_CAPABLE_MASK (0x00FFFFBFul)\r
+//\r
+\r
+// GIRQ09 Bit Positions \r
+#define GIRQ09_GPIO_0100_BITPOS (0)\r
+#define GIRQ09_GPIO_0101_BITPOS (1)\r
+#define GIRQ09_GPIO_0102_BITPOS (2)\r
+#define GIRQ09_GPIO_0103_BITPOS (3)\r
+#define GIRQ09_GPIO_0104_BITPOS (4)\r
+#define GIRQ09_GPIO_0105_BITPOS (5)\r
+#define GIRQ09_GPIO_0106_BITPOS (6) \r
+#define GIRQ09_GPIO_0107_BITPOS (7)\r
+//\r
+#define GIRQ09_GPIO_0110_BITPOS (8)\r
+#define GIRQ09_GPIO_0111_BITPOS (9)\r
+#define GIRQ09_GPIO_0112_BITPOS (10)\r
+#define GIRQ09_GPIO_0113_BITPOS (11)\r
+#define GIRQ09_GPIO_0114_BITPOS (12)\r
+#define GIRQ09_GPIO_0115_BITPOS (13)\r
+#define GIRQ09_GPIO_0116_BITPOS (14) \r
+#define GIRQ09_GPIO_0117_BITPOS (15)\r
+//\r
+#define GIRQ09_GPIO_0120_BITPOS (16)\r
+#define GIRQ09_GPIO_0121_BITPOS (17)\r
+#define GIRQ09_GPIO_0122_BITPOS (18)\r
+//#define GIRQ09_GPIO_0123_BITPOS (19) RESERVED\r
+#define GIRQ09_GPIO_0124_BITPOS (20)\r
+#define GIRQ09_GPIO_0125_BITPOS (21)\r
+#define GIRQ09_GPIO_0126_BITPOS (22) \r
+#define GIRQ09_GPIO_0127_BITPOS (23)\r
+//\r
+#define GIRQ09_GPIO_0130_BITPOS (24)\r
+#define GIRQ09_GPIO_0131_BITPOS (25)\r
+#define GIRQ09_GPIO_0132_BITPOS (26)\r
+#define GIRQ09_GPIO_0133_BITPOS (27)\r
+#define GIRQ09_GPIO_0134_BITPOS (28)\r
+#define GIRQ09_GPIO_0135_BITPOS (29)\r
+#define GIRQ09_GPIO_0136_BITPOS (30) \r
+//#define GIRQ09_GPIO_0137_BITPOS (31) RESERVED\r
+//\r
+#define GIRQ09_MASK (0x7FF7FFFFul)\r
+#define GIRQ09_WAKE_CAPABLE_MASK (0x7FF7FFFFul)\r
+//\r
+\r
+// GIRQ10 Bit Positions \r
+#define GIRQ10_GPIO_0040_BITPOS (0)\r
+#define GIRQ10_GPIO_0041_BITPOS (1)\r
+#define GIRQ10_GPIO_0042_BITPOS (2)\r
+#define GIRQ10_GPIO_0043_BITPOS (3)\r
+#define GIRQ10_GPIO_0044_BITPOS (4)\r
+#define GIRQ10_GPIO_0045_BITPOS (5)\r
+#define GIRQ10_GPIO_0046_BITPOS (6) \r
+#define GIRQ10_GPIO_0047_BITPOS (7)\r
+//\r
+#define GIRQ10_GPIO_0050_BITPOS (8)\r
+#define GIRQ10_GPIO_0051_BITPOS (9)\r
+#define GIRQ10_GPIO_0052_BITPOS (10)\r
+#define GIRQ10_GPIO_0053_BITPOS (11)\r
+#define GIRQ10_GPIO_0054_BITPOS (12)\r
+#define GIRQ10_GPIO_0055_BITPOS (13)\r
+#define GIRQ10_GPIO_0056_BITPOS (14) \r
+#define GIRQ10_GPIO_0057_BITPOS (15)\r
+//\r
+#define GIRQ10_GPIO_0060_BITPOS (16)\r
+#define GIRQ10_GPIO_0061_BITPOS (17)\r
+#define GIRQ10_GPIO_0062_BITPOS (18)\r
+#define GIRQ10_GPIO_0063_BITPOS (19)\r
+#define GIRQ10_GPIO_0064_BITPOS (20)\r
+#define GIRQ10_GPIO_0065_BITPOS (21)\r
+#define GIRQ10_GPIO_0066_BITPOS (22) \r
+#define GIRQ10_GPIO_0067_BITPOS (23)\r
+//\r
+#define GIRQ10_GPIO_0070_BITPOS (24)\r
+#define GIRQ10_GPIO_0071_BITPOS (25)\r
+#define GIRQ10_GPIO_0072_BITPOS (26)\r
+#define GIRQ10_GPIO_0073_BITPOS (27)\r
+#define GIRQ10_GPIO_0074_BITPOS (28)\r
+#define GIRQ10_GPIO_0075_BITPOS (29)\r
+#define GIRQ10_GPIO_0076_BITPOS (30) \r
+//#define GIRQ10_GPIO_0077_BITPOS (31) RESERVED\r
+//\r
+#define GIRQ10_MASK (0x7FFFFFFFul)\r
+#define GIRQ10_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+//\r
+\r
+// GIRQ11 Bit Positions \r
+#define GIRQ11_GPIO_0000_BITPOS (0)\r
+#define GIRQ11_GPIO_0001_BITPOS (1)\r
+#define GIRQ11_GPIO_0002_BITPOS (2)\r
+#define GIRQ11_GPIO_0003_BITPOS (3)\r
+#define GIRQ11_GPIO_0004_BITPOS (4)\r
+#define GIRQ11_GPIO_0005_BITPOS (5)\r
+#define GIRQ11_GPIO_0006_BITPOS (6) \r
+#define GIRQ11_GPIO_0007_BITPOS (7)\r
+//\r
+#define GIRQ11_GPIO_0010_BITPOS (8)\r
+#define GIRQ11_GPIO_0011_BITPOS (9)\r
+#define GIRQ11_GPIO_0012_BITPOS (10)\r
+#define GIRQ11_GPIO_0013_BITPOS (11)\r
+#define GIRQ11_GPIO_0014_BITPOS (12)\r
+#define GIRQ11_GPIO_0015_BITPOS (13)\r
+#define GIRQ11_GPIO_0016_BITPOS (14) \r
+#define GIRQ11_GPIO_0017_BITPOS (15)\r
+//\r
+#define GIRQ11_GPIO_0020_BITPOS (16)\r
+#define GIRQ11_GPIO_0021_BITPOS (17)\r
+#define GIRQ11_GPIO_0022_BITPOS (18)\r
+#define GIRQ11_GPIO_0023_BITPOS (19)\r
+#define GIRQ11_GPIO_0024_BITPOS (20)\r
+#define GIRQ11_GPIO_0025_BITPOS (21)\r
+#define GIRQ11_GPIO_0026_BITPOS (22) \r
+#define GIRQ11_GPIO_0027_BITPOS (23)\r
+//\r
+#define GIRQ11_GPIO_0030_BITPOS (24)\r
+#define GIRQ11_GPIO_0031_BITPOS (25)\r
+#define GIRQ11_GPIO_0032_BITPOS (26)\r
+#define GIRQ11_GPIO_0033_BITPOS (27)\r
+#define GIRQ11_GPIO_0034_BITPOS (28)\r
+#define GIRQ11_GPIO_0035_BITPOS (29)\r
+#define GIRQ11_GPIO_0036_BITPOS (30) \r
+//#define GIRQ11_GPIO_0037_BITPOS (31) RESERVED\r
+//\r
+#define GIRQ11_MASK (0x7FFFFFFFul)\r
+#define GIRQ11_WAKE_CAPABLE_MASK (0x7FFFFFFFul)\r
+//\r
+\r
+// GIRQ12 Bit Positions \r
+#define GIRQ12_SMBUS0_BITPOS (0)\r
+#define GIRQ12_SMBUS1_BITPOS (1)\r
+#define GIRQ12_SMBUS2_BITPOS (2)\r
+#define GIRQ12_SMBUS3_BITPOS (3)\r
+#define GIRQ12_SMBUS0_WAKE_BITPOS (4)\r
+#define GIRQ12_SMBUS1_WAKE_BITPOS (5)\r
+#define GIRQ12_SMBUS2_WAKE_BITPOS (6)\r
+#define GIRQ12_SMBUS3_WAKE_BITPOS (7)\r
+#define GIRQ12_SMBUS4_WAKE_BITPOS (8)\r
+// RESERVED bits[31:9]\r
+#define GIRQ12_MASK (0x01FFul)\r
+#define GIRQ12_WAKE_CAPABLE_MASK (0x01F0ul)\r
+//\r
+\r
+// GIRQ13 Bit Positions \r
+#define GIRQ13_DMA0_BITPOS (16)\r
+#define GIRQ13_DMA1_BITPOS (17)\r
+#define GIRQ13_DMA2_BITPOS (18)\r
+#define GIRQ13_DMA3_BITPOS (19)\r
+#define GIRQ13_DMA4_BITPOS (20)\r
+#define GIRQ13_DMA5_BITPOS (21)\r
+#define GIRQ13_DMA6_BITPOS (22)\r
+#define GIRQ13_DMA7_BITPOS (23)\r
+#define GIRQ13_DMA8_BITPOS (24)\r
+#define GIRQ13_DMA9_BITPOS (25)\r
+#define GIRQ13_DMA10_BITPOS (26)\r
+#define GIRQ13_DMA11_BITPOS (27)\r
+//\r
+#define GIRQ13_MASK (0x0FFF0000ul)\r
+#define GIRQ13_WAKE_CAPABLE_MASK (0x00000000ul)\r
+//\r
+\r
+// GIRQ14 Bit Positions \r
+#define GIRQ14_LPC_BITPOS (2)\r
+//\r
+#define GIRQ14_MASK (0x04ul)\r
+#define GIRQ14_WAKE_CAPABLE_MASK (0x00ul)\r
+//\r
+\r
+// GIRQ15 Bit Positions \r
+#define GIRQ15_UART0_BITPOS (0)\r
+#define GIRQ15_IMAP_BITPOS (2)\r
+#define GIRQ15_KBD_K_BITPOS (3)\r
+#define GIRQ15_KBD_M_BITPOS (4)\r
+#define GIRQ15_ACPI0_IBF_BITPOS (6)\r
+#define GIRQ15_ACPI0_OBF_BITPOS (7)\r
+#define GIRQ15_ACPI1_IBF_BITPOS (8)\r
+#define GIRQ15_ACPI1_OBF_BITPOS (9)\r
+#define GIRQ15_ACPI_PM1CTL_BITPOS (10)\r
+#define GIRQ15_ACPI_PM1EN_BITPOS (11)\r
+#define GIRQ15_ACPI_PM1STS_BITPOS (12)\r
+#define GIRQ15_MF8042_OBF_BITPOS (13)\r
+#define GIRQ15_MF8042_IBF_BITPOS (14)\r
+#define GIRQ15_MAILBOX_BITPOS (15)\r
+#define GIRQ15_MAILBOX_DATA_BITPOS (16)\r
+//\r
+#define GIRQ15_MASK (0x01FFDDul)\r
+#define GIRQ15_WAKE_CAPABLE_MASK (0x000000ul)\r
+//\r
+\r
+// GIRQ16 Bit Positions \r
+#define GIRQ16_PECI_BITPOS (3)\r
+//\r
+#define GIRQ16_MASK (0x08ul)\r
+#define GIRQ16_WAKE_CAPABLE_MASK (0x00ul)\r
+//\r
+\r
+// GIRQ17 Bit Positions \r
+#define GIRQ17_TACH0_BITPOS (0)\r
+#define GIRQ17_TACH1_BITPOS (1)\r
+#define GIRQ17_PS2_0_WAKE_BITPOS (2)\r
+#define GIRQ17_PS2_1_WAKE_BITPOS (3)\r
+#define GIRQ17_PS2_2_WAKE_BITPOS (4)\r
+#define GIRQ17_PS2_3_WAKE_BITPOS (5)\r
+#define GIRQ17_BC_WAKE_BITPOS (6)\r
+// RESERVED b[9:7]\r
+#define GIRQ17_ADC_INT0_BITPOS (10)\r
+#define GIRQ17_ADC_INT1_BITPOS (11)\r
+#define GIRQ17_V2P_INT0_BITPOS (12)\r
+#define GIRQ17_V2P_INT1_BITPOS (13)\r
+#define GIRQ17_PS2_0_BITPOS (14)\r
+#define GIRQ17_PS2_1_BITPOS (15)\r
+#define GIRQ17_PS2_2_BITPOS (16)\r
+#define GIRQ17_PS2_3_BITPOS (17)\r
+// RESERVED b[19:18]\r
+#define GIRQ17_HIBTMR_BITPOS (20)\r
+#define GIRQ17_KEY_INT_BITPOS (21)\r
+#define GIRQ17_KEY_INT_WAKE_BITPOS (22)\r
+#define GIRQ17_RPM_STALL_BITPOS (23)\r
+#define GIRQ17_RPM_SPIN_BITPOS (24)\r
+#define GIRQ17_VBAT_BITPOS (25)\r
+#define GIRQ17_LED0_BITPOS (26)\r
+#define GIRQ17_LED1_BITPOS (27)\r
+#define GIRQ17_LED2_BITPOS (28)\r
+#define GIRQ17_MBC_ERR_BITPOS (29)\r
+#define GIRQ17_MBC_BUSY_BITPOS (30)\r
+//\r
+#define GIRQ17_MASK (0x7FF3FC7Ful)\r
+#define GIRQ17_WAKE_CAPABLE_MASK (0x0230007Cul)\r
+//\r
+\r
+// GIRQ18 Bit Positions \r
+#define GIRQ18_SPI0_TX_BITPOS (0)\r
+#define GIRQ18_SPI0_RX_BITPOS (1)\r
+#define GIRQ18_SPI1_TX_BITPOS (2)\r
+#define GIRQ18_SPI1_RX_BITPOS (3)\r
+#define GIRQ18_LED3_BITPOS (4) // NVIC 85\r
+#define GIRQ18_PKE_ERR_BITPOS (5) // NVIC 86\r
+#define GIRQ18_PKE_END_BITPOS (6) // NVIC 87\r
+#define GIRQ18_TRNG_BITPOS (7) // NVIC 88\r
+#define GIRQ18_AES_BITPOS (8) // NVIC 89\r
+#define GIRQ18_HASH_BITPOS (9) // NVIC 90\r
+//\r
+#define GIRQ18_MASK (0x0FFul)\r
+#define GIRQ18_WAKE_CAPABLE_MASK (0x000ul)\r
+//\r
+\r
+// GIRQ19 Bit Positions \r
+#define GIRQ19_LRESET_BITPOS (0)\r
+#define GIRQ19_VCC_PWRGD_BITPOS (1)\r
+//\r
+#define GIRQ19_MASK (0x03ul)\r
+#define GIRQ19_WAKE_CAPABLE_MASK (0x03ul)\r
+//\r
+\r
+// GIRQ20 Bit Positions \r
+#define GIRQ20_GPIO_0200_BITPOS (0)\r
+#define GIRQ20_GPIO_0201_BITPOS (1)\r
+#define GIRQ20_GPIO_0202_BITPOS (2)\r
+#define GIRQ20_GPIO_0203_BITPOS (3)\r
+#define GIRQ20_GPIO_0204_BITPOS (4)\r
+//#define GIRQ20_GPIO_0205_BITPOS (5)\r
+#define GIRQ20_GPIO_0206_BITPOS (6)\r
+//#define GIRQ20_GPIO_0207_BITPOS (7)\r
+//\r
+#define GIRQ20_GPIO_0210_BITPOS (8)\r
+#define GIRQ20_GPIO_0211_BITPOS (9)\r
+#define GIRQ20_GPIO_0212_BITPOS (10)\r
+#define GIRQ20_GPIO_0213_BITPOS (11)\r
+// \r
+#define GIRQ20_MASK (0x0F5Ful)\r
+#define GIRQ20_WAKE_CAPABLE_MASK (0x0F5Ful)\r
+//\r
+\r
+// GIRQ21 Bit Positions \r
+#define GIRQ21_MASK (0x00ul)\r
+#define GIRQ21_WAKE_CAPABLE_MASK (0x00ul)\r
+\r
+// GIRQ22 Bit Positions \r
+#define GIRQ22_MASK (0x00ul)\r
+#define GIRQ22_WAKE_CAPABLE_MASK (0x00ul)\r
+\r
+// GIRQ23 Bit Positions \r
+#define GIRQ23_TMR0_BITPOS (0)\r
+#define GIRQ23_TMR1_BITPOS (1)\r
+#define GIRQ23_TMR2_BITPOS (2)\r
+#define GIRQ23_TMR3_BITPOS (3)\r
+#define GIRQ23_TMR4_BITPOS (4)\r
+#define GIRQ23_TMR5_BITPOS (5)\r
+//\r
+#define GIRQ23_MASK (0x03Ful)\r
+#define GIRQ23_WAKE_CAPABLE_MASK (0x000ul)\r
+//\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* NVIC,ECIA Routing Policy for Direct Mode */\r
+/* ------------------------------------------------------------------------------- */\r
+/* In Direct Mode, some interrupts could be configured to be used as aggregated.\r
+ * Configuration:\r
+ * 1. Always set ECS Interrupt Direct enable bit. \r
+ * 2. If GIRQn aggregated set Block Enable bit.\r
+ * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs.\r
+ * Switching issues:\r
+ * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers.\r
+ * Also requires set/clear of individual NVIC Enables.\r
+ * \r
+ * Note: interrupt_is_girq_direct() internal function uses this policy to detect \r
+ * if any interrupt is configured as direct or aggregated\r
+*/\r
+\r
+/** Initialize EC Interrupt Aggregator\r
+ * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode \r
+ * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated \r
+ * This parameter is only applicable in direct mode.\r
+ * @note All GPIO's and wake capable sources are always \r
+ * aggregated! GPIO's interrupts will still work in direct mode.\r
+ * Block wakes are not be routed to the processor in direct \r
+ * mode. \r
+ * Note2: This function disables and enables global interrupt \r
+ */\r
+void interrupt_init(uint8_t mode, uint32_t girq_bitmask);\r
+\r
+/** Set interrupt routing mode to aggregated or direct. \r
+ * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated \r
+ * @note In direct mode, one could enable certain GIRQs as aggregated using \r
+ * p_interrupt_ecia_block_enable_set function\r
+ */\r
+void interrupt_mode_set(uint8_t mode);\r
+\r
+/** Clears all individual interrupts Enables and Source in ECIA,\r
+ * and Clears all NVIC external enables and pending bits \r
+ */\r
+void interrupt_reset(void);\r
+\r
+/** Enables interrupt for a device \r
+ * @param dev_iroute - source IROUTING information \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_enable(uint32_t dev_iroute);\r
+\r
+/** Disables interrupt for a device\r
+ * @param dev_iroute - source IROUTING information \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_disable(uint32_t dev_iroute);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* ECIA APIs using device IROUTE() as input */ \r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Clear Source in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ */\r
+void interrupt_device_ecia_source_clear(const uint32_t dev_iroute);\r
+\r
+/** Get the Source bit in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ * @return 0 if source bit not set; else non-zero value\r
+ */\r
+uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute);\r
+\r
+/** Get the Result bit in the ECIA for the device \r
+ * @param devi - device IROUTING value \r
+ * @return 0 if result bit not set; else non-zero value\r
+ */\r
+uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* NVIC APIs using device IROUTE() as input */ \r
+/* ------------------------------------------------------------------------------- */\r
+/* Note that if the device interrupt is aggregated, then these APIs would affect the \r
+ * NVIC corresponding to the aggregated GIRQ \r
+ */\r
+\r
+/** Enable/Disable the NVIC (in the NVIC controller) for the device\r
+ * @param dev_iroute : source IROUTING information (encoded in a uint32_t)\r
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ \r
+ * @note Recommended to use interrupt_device_enable, interrupt_device_disable\r
+ * to enable/disable interrupts for the device, since those APIs configure ECIA as well\r
+ */\r
+void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag);\r
+\r
+/** Set NVIC priority for specified peripheral interrupt source\r
+ * @param dev_iroute - source IROUTING information (encoded in a uint32_t)\r
+ * @param nvic_pri - NVIC Priority\r
+ * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt \r
+ * sources in the GIRQ. \r
+ * 2. This function disables and enables global interrupt \r
+ */\r
+void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri);\r
+\r
+/** Return NVIC priority for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint32_t NVIC priority \r
+ */\r
+uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute);\r
+\r
+/** Return NVIC pending for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint8_t 0(not pending), 1 (pending in NVIC) \r
+ * \r
+ */\r
+uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute);\r
+\r
+/** Set NVIC pending for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ */\r
+void interrupt_device_nvic_pending_set(const uint32_t dev_iroute);\r
+\r
+/** Clears NVIC pending for interrupt source\r
+ * @param dev_iroute - source IROUTING information \r
+ * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear \r
+ * @note This function disables and enables global interrupt \r
+ */\r
+uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute);\r
+ \r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear *\r
+ * and Status Register */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Enable specified GIRQ in ECIA block\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ */\r
+ void p_interrupt_ecia_block_enable_set(uint8_t girq_id);\r
+ \r
+ /** Enable GIRQs in ECIA Block \r
+ * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block \r
+ */\r
+void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask);\r
+\r
+/** Check if specified GIRQ block enabled or not\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ * @return retVal - 1 if the particular GIRQ block enabled, else 0\r
+ */\r
+uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id);\r
+\r
+/** Set all GIRQ block enables */\r
+void p_interrupt_ecia_block_enable_all_set(void);\r
+\r
+/** Clear specified GIRQ in ECIA Block \r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ */\r
+void p_interrupt_ecia_block_enable_clr(uint8_t girq_id);\r
+\r
+/** Clear GIRQs in ECIA Block \r
+ * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block \r
+ */\r
+void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask);\r
+\r
+/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */\r
+void p_interrupt_ecia_block_enable_all_clr(void);\r
+ \r
+ /** Get status of GIRQ in ECIA Block\r
+ * @param girq_id - enum MEC_GIRQ_IDS \r
+ * @return 0 if status bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id);\r
+\r
+/** Reads the Block IRQ Vector Register\r
+ * @return 32-bit value\r
+ */\r
+uint32_t p_interrupt_ecia_block_irq_all_status_get(void);\r
+\r
+/* ---------------------------------------------------------------------------- */\r
+/* Peripheral Functions - Operations on GIRQx Source, Enable, Result *\r
+ * and Enable Registers */\r
+/* ---------------------------------------------------------------------------- */\r
+\r
+/** Clear specified interrupt source bit in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum);\r
+\r
+/** Read the specified interrupt source bit in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ * @return 0 if source bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum);\r
+\r
+/** Enable the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum);\r
+\r
+/** Disable the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ */\r
+void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum);\r
+\r
+/** Read the status of the specified interrupt in GIRQx\r
+ * girq_id - enum MEC_GIRQ_IDS\r
+ * bitnum = [0, 31]\r
+ * @return 0 if enable bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum);\r
+\r
+/** Read the result bit of the interrupt in GIRQx\r
+ * @param girq_id - enum MEC_GIRQ_IDS\r
+ * @param bitnum -[0, 31]\r
+ * @return 0 if enable bit not set; else non-zero value\r
+ */\r
+uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Function - Operations on all GIRQs */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Clear all aggregator GIRQn status registers */\r
+void p_interrupt_ecia_girqs_source_reset(void);\r
+\r
+/** Clear all aggregator GIRQn enables */\r
+ void p_interrupt_ecia_girqs_enable_reset(void);\r
+ \r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Function - Function to set interrupt control */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Set interrupt control \r
+ * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
+ */\r
+ void p_interrupt_control_set(uint8_t nvic_en_flag);\r
+ \r
+ /** Read interrupt control \r
+ * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled\r
+ */\r
+uint8_t p_interrupt_control_get(void);\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Peripheral Functions - NVIC */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller\r
+ * @param nvic_num : NVIC number (see enum IRQn_Type)\r
+ * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ\r
+ * @note Application should perform this operation\r
+ */\r
+ void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag);\r
+ \r
+ /** ecia_nvic_clr_en - Clear all NVIC external enables */ \r
+void p_interrupt_nvic_extEnables_clr(void);\r
+\r
+/** Clear all NVIC external enables and pending bits */\r
+void p_interrupt_nvic_enpend_clr(void);\r
+\r
+/** Set NVIC external priorities to POR value */\r
+void p_interrupt_nvic_priorities_default_set(void);\r
+\r
+/** Set NVIC external priorities to specified priority (0 - 7)\r
+ * @param zero-based 3-bit priority value: 0=highest, 7=lowest.\r
+ * @note NVIC highest priority is the value 0, lowest is all 1's.\r
+ * Each external interrupt has an 8-bit register and the priority \r
+ * is left justified in the registers. MECxxx implements 8 priority \r
+ * levels or bits [7:5] in the register. Lowest priority = 0xE0\r
+ */\r
+void p_interrupt_nvic_priorities_set(uint8_t new_pri);\r
+\r
+#endif /*_INTERRUPT_H_*/\r
+\r
+/** @}\r
+ */\r
+\r
+\r
+\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2015/11/24 06:28:28 $ \r
+$Author: amohandas $\r
+Last Change: Updated for tabs\r
+******************************************************************************/\r
+/** @file pcr.h\r
+* \brief Power, Clocks, and Resets Header file\r
+* \author jvasanth\r
+* \r
+* This file is the PCR header file \r
+******************************************************************************/\r
+\r
+/** @defgroup PCR\r
+ * @{\r
+ */\r
+\r
+#ifndef _PCR_H\r
+#define _PCR_H\r
+\r
+\r
+/******************************************************************************/\r
+/** PCR Register IDS \r
+ *******************************************************************************/\r
+enum _PCR_REGSET_ID_\r
+{\r
+ PCR_REG_CHIP_SLEEP_ENABLE =0,\r
+ PCR_REG_CHIP_CLK_REQD_STS,\r
+ PCR_REG_EC_SLEEP_ENABLE,\r
+ PCR_REG_EC_CLK_REQD_STS,\r
+ PCR_REG_HOST_SLEEP_ENABLE,\r
+ PCR_REG_HOST_CLK_REQD_STS,\r
+ PCR_REG_SYSTEM_SLEEP_CTRL, \r
+ PCR_REG_PROCESSOR_CLK_CTRL = 8,\r
+ PCR_REG_EC_SLEEP_ENABLE_2,\r
+ PCR_REG_EC_CLK_REQD_STS_2,\r
+ PCR_REG_SLOW_CLK_CTRL,\r
+ PCR_REG_OSCILLATOR_ID,\r
+ PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS,\r
+ PCR_REG_CHIP_RESET_ENABLE,\r
+ PCR_REG_HOST_RESET_ENABLE,\r
+ PCR_REG_EC_RESET_ENABLE,\r
+ PCR_REG_EC_RESET_ENABLE_2,\r
+ PCR_REG_PWR_RESET_CTRL\r
+};\r
+/* ---------------------------------------------------------------------- */\r
+\r
+// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable\r
+//PCR register group 0 - CHIP\r
+#define PCR0_REGS_CHIP (((uint32_t)(PCR_REG_CHIP_SLEEP_ENABLE) & 0xFF) + \\r
+ (((uint32_t)(PCR_REG_CHIP_CLK_REQD_STS) & 0xFF)<<8u) + \\r
+ (((uint32_t)(PCR_REG_CHIP_RESET_ENABLE) & 0xFF)<<16u))\r
+\r
+//PCR register group 1 - EC\r
+#define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \\r
+ (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \\r
+ (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))\r
+\r
+//PCR register group 2 - HOST\r
+#define PCR2_REGS_HOST (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \\r
+ (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \\r
+ (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))\r
+\r
+//PCR register group 3 - EC 2\r
+#define PCR3_REGS_EC2 (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \\r
+ (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \\r
+ (((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u))\r
+ \r
+ \r
+//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
+#define PCR1_EC_INT_BITPOS (0u)\r
+#define PCR1_EC_PECI_BITPOS (1u)\r
+#define PCR1_EC_TACH0_BITPOS (2u)\r
+#define PCR1_EC_PWM0_BITPOS (4u)\r
+#define PCR1_EC_PMC_BITPOS (5u)\r
+#define PCR1_EC_DMA_BITPOS (6u)\r
+#define PCR1_EC_TFDP_BITPOS (7u)\r
+#define PCR1_EC_CPU_BITPOS (8u)\r
+#define PCR1_EC_WDT_BITPOS (9u)\r
+#define PCR1_EC_SMB0_BITPOS (10u)\r
+#define PCR1_EC_TACH1_BITPOS (11u)\r
+#define PCR1_EC_PWM1_BITPOS (20u)\r
+#define PCR1_EC_PWM2_BITPOS (21u)\r
+#define PCR1_EC_PWM3_BITPOS (22u)\r
+#define PCR1_EC_REG_BITPOS (29u)\r
+#define PCR1_EC_BTIMER0_BITPOS (30u)\r
+#define PCR1_EC_BTIMER1_BITPOS (31u)\r
+\r
+//PCR2_HOST -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
+#define PCR2_HOST_LPC_BITPOS (0u)\r
+#define PCR2_HOST_UART0_BITPOS (1u)\r
+#define PCR2_HOST_GLBL_CFG_BITPOS (12u)\r
+#define PCR2_HOST_ACPI_EC0_BITPOS (13u)\r
+#define PCR2_HOST_ACPI_EC1_BITPOS (14u)\r
+#define PCR2_HOST_ACPI_PM1_BITPOS (15u)\r
+#define PCR2_HOST_8042EM_BITPOS (16u)\r
+#define PCR2_HOST_RTC_BITPOS (18u)\r
+\r
+//PCR3_EC2 -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions\r
+#define PCR3_EC2_ADC_BITPOS (3u)\r
+#define PCR3_EC2_PS2_0_BITPOS (5u)\r
+#define PCR3_EC2_PS2_1_BITPOS (6u)\r
+#define PCR3_EC2_PS2_2_BITPOS (7u)\r
+#define PCR3_EC2_PS2_3_BITPOS (8u)\r
+#define PCR3_EC2_SPI0_BITPOS (9u)\r
+#define PCR3_EC2_HTIMER_BITPOS (10u)\r
+#define PCR3_EC2_KEYSCAN_BITPOS (11u)\r
+#define PCR3_EC2_RPM_PWM_BITPOS (12u)\r
+#define PCR3_EC2_SMB1_BITPOS (13u)\r
+#define PCR3_EC2_SMB2_BITPOS (14u)\r
+#define PCR3_EC2_SMB3_BITPOS (15u)\r
+#define PCR3_EC2_LED0_BITPOS (16u)\r
+#define PCR3_EC2_LED1_BITPOS (17u)\r
+#define PCR3_EC2_LED2_BITPOS (18u)\r
+#define PCR3_EC2_BCM_BITPOS (19u)\r
+#define PCR3_EC2_SPI1_BITPOS (20u)\r
+#define PCR3_EC2_BTIMER2_BITPOS (21u)\r
+#define PCR3_EC2_BTIMER3_BITPOS (22u)\r
+#define PCR3_EC2_BTIMER4_BITPOS (23u)\r
+#define PCR3_EC2_BTIMER5_BITPOS (24u)\r
+#define PCR3_EC2_LED3_BITPOS (25u)\r
+\r
+/*\r
+ * n = b[7:0] = PCR Reg Bit Position\r
+ * m = b[31:8] = PCRx Regs IDs\r
+ */\r
+//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul)) \r
+\r
+//PCRx_REGS_BIT positions \r
+#define PCRx_REGS_POS_SLEEP_ENABLE (8u)\r
+#define PCRx_REGS_POS_CLK_REQD_STS (16u)\r
+#define PCRx_REGS_POS_RESET_ENABLE (24u) \r
+\r
+\r
+/******************************************************************************/\r
+/** PCR Block IDS. \r
+ * These IDs are used to directly refer to a block \r
+ *******************************************************************************/\r
+typedef enum {\r
+ PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)), \r
+ PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)), \r
+ PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)), \r
+ PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)), \r
+ PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)), \r
+ PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)), \r
+ PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)), \r
+ PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)), \r
+ PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)), \r
+ PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)), \r
+ PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)), \r
+ PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)), \r
+ PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)), \r
+ PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)), \r
+ PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)), \r
+ PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)), \r
+ PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)), \r
+ PCR_LPC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_LPC_BITPOS & 0xFFu)),\r
+ PCR_UART0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_UART0_BITPOS & 0xFFu)),\r
+ PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_GLBL_CFG_BITPOS & 0xFFu)),\r
+ PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC0_BITPOS & 0xFFu)),\r
+ PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC1_BITPOS & 0xFFu)),\r
+ PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_PM1_BITPOS & 0xFFu)),\r
+ PCR_8042EM = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_8042EM_BITPOS & 0xFFu)),\r
+ PCR_RTC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_RTC_BITPOS & 0xFFu)),\r
+ PCR_ADC = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_ADC_BITPOS & 0xFFu)),\r
+ PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_0_BITPOS & 0xFFu)), \r
+ PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_1_BITPOS & 0xFFu)), \r
+ PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_2_BITPOS & 0xFFu)), \r
+ PCR_PS2_3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_3_BITPOS & 0xFFu)), \r
+ PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI0_BITPOS & 0xFFu)), \r
+ PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_HTIMER_BITPOS & 0xFFu)), \r
+ PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_KEYSCAN_BITPOS & 0xFFu)), \r
+ PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_RPM_PWM_BITPOS & 0xFFu)), \r
+ PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB1_BITPOS & 0xFFu)), \r
+ PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB2_BITPOS & 0xFFu)), \r
+ PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB3_BITPOS & 0xFFu)), \r
+ PCR_LED0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED0_BITPOS & 0xFFu)), \r
+ PCR_LED1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED1_BITPOS & 0xFFu)), \r
+ PCR_LED2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED2_BITPOS & 0xFFu)), \r
+ PCR_BCM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BCM_BITPOS & 0xFFu)), \r
+ PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI1_BITPOS & 0xFFu)), \r
+ PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER2_BITPOS & 0xFFu)), \r
+ PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER3_BITPOS & 0xFFu)), \r
+ PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER4_BITPOS & 0xFFu)), \r
+ PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER5_BITPOS & 0xFFu)), \r
+ PCR_LED3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED3_BITPOS & 0xFFu)), \r
+} PCR_BLK_ID;\r
+\r
+\r
+/******************************************************************************/\r
+/** PCR Processor ClK Divide Values \r
+ *******************************************************************************/\r
+enum PROCESSOR_CLK_DIVIDE_VALUE\r
+{\r
+ PCR_CPU_CLK_DIVIDE_1 = 1,\r
+ PCR_CPU_CLK_DIVIDE_4 = 4,\r
+ PCR_CPU_CLK_DIVIDE_16 = 16,\r
+ PCR_CPU_CLK_DIVIDE_48 = 48 \r
+};\r
+\r
+/******************************************************************************/\r
+/** System Sleep Modes \r
+ *******************************************************************************/\r
+enum SYSTEM_SLEEP_MODES\r
+{\r
+ SYSTEM_HEAVY_SLEEP_1 = 0, \r
+ SYSTEM_HEAVY_SLEEP_3 = 1,\r
+ SYSTEM_HEAVY_SLEEP_2 = 2,\r
+ SYSTEM_DEEPEST_SLEEP = 5 \r
+};\r
+\r
+/* Bitmask for System Sleep Control Register */\r
+#define PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK (1UL<<0)\r
+#define PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK (1UL<<1)\r
+#define PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK (1UL<<2)\r
+\r
+/* Bitmask for Chip Sub-system Power Reset Status Register */\r
+#define PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK (1UL<<2)\r
+#define PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK (1UL<<3)\r
+#define PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK (1UL<<5)\r
+#define PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK (1UL<<6)\r
+#define PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK (1UL<<10)\r
+#define PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK (1UL<<11)\r
+\r
+/* Bitmask for Processor Clock Control Register */\r
+#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8)\r
+\r
+/* Bitmask for Power Reset Control Register */\r
+#define PCR_iRESET_OUT_BITMASK (1UL<<0)\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions to program Sleep Enable, CLK Reqd Status, *\r
+ * Reset Enable for a block *\r
+ * ---------------------------------------------------------------------- */\r
+ /** Sets or Clears block specific bit in PCR Sleep Enable Register\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register\r
+ */\r
+void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);\r
+\r
+/** Get Clock Required Status for the block\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @return uint8_t - 1 if Clock Required Status set, else 0\r
+ */\r
+uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id);\r
+\r
+/** Sets or Clears Reset Enable register bit for the block\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register\r
+ */\r
+void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* API - Functions for entering low power modes */\r
+/* ---------------------------------------------------------------------- */\r
+/** Instructs all blocks to sleep by setting the Sleep Enable bits */\r
+void pcr_all_blocks_sleep(void);\r
+\r
+/** Clears the Sleep Enable bits for all blocks */\r
+void pcr_all_blocks_wake(void);\r
+\r
+/** Programs required sleep mode in System Sleep Control Register\r
+ * @param sleep_mode - see enum SYSTEM_SLEEP_MODES\r
+ */\r
+void pcr_system_sleep(uint8_t sleep_mode);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions to program and read 32-bit values *\r
+ * from PCR Registers *\r
+ * ---------------------------------------------------------------------- */\r
+ /** Write 32-bit value in the PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param value - 32-bit value\r
+ */\r
+void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value);\r
+\r
+/** Reads 32-bit value from the PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @return value - 32-bit value\r
+ */\r
+uint32_t p_pcr_reg_read(uint8_t pcr_reg_id);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions to set, clr and get bits in *\r
+ * PCR Registers * \r
+ * ---------------------------------------------------------------------- */\r
+ /** Sets bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to set \r
+ */\r
+void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask);\r
+\r
+/** Clears bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to clear \r
+ */\r
+void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask);\r
+\r
+/** Read bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to read \r
+ * @return value - 32-bit value\r
+ */\r
+uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask);\r
+\r
+/** Sets or Clears bits in a PCR Register - Helper Function\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to set or clear\r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register\r
+ */\r
+void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag);\r
+ \r
+//Functions to operate on System Sleep Control Register \r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions to operate on System Sleep Control *\r
+ * Register * \r
+ * ---------------------------------------------------------------------- */\r
+/** Sets/Clears the Ring oscillator power down bit \r
+ * in System Sleep Control Register\r
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
+ */\r
+void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag);\r
+\r
+/** Sets/Clears the Ring oscillator output gate bit \r
+ * in System Sleep Control Register\r
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
+ */\r
+void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag);\r
+\r
+/** Sets/Clears the Core regulator standby bit \r
+ * in System Sleep Control Register\r
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
+ */\r
+void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag);\r
+\r
+/** Writes required sleep mode in System Sleep Control Register\r
+ * @param sleep_value - System Sleep control value - [D2, D1, D0]\r
+ */\r
+void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value);\r
+\r
+/** Reads the System Sleep Control PCR Register\r
+ * @return value - byte 0 of the system sleep control PCR register\r
+ */\r
+uint8_t p_pcr_system_sleep_ctrl_read(void);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Function to program to CLK Divide Value * \r
+ * ---------------------------------------------------------------------- */\r
+ /** Writes the clock divide value in the Processor Clock Control Register\r
+ * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
+ */\r
+void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Function to program the Slow Clock Control *\r
+ * Register *\r
+ * ---------------------------------------------------------------------- */\r
+ /** Write the slow clock divide value in the Slow Clock Control Register\r
+ * @param slow_clk_divide_value - slow clk divide value\r
+ */\r
+void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Function to read the Oscillator Lock Status */ \r
+/* ---------------------------------------------------------------------- */\r
+/** Reads the Oscillator Lock status bit in the Oscillator ID Register\r
+ * @return 1 if Oscillator Lock Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_oscillator_lock_sts_get(void);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions to read various power status in *\r
+ * Chip Sub-System register *\r
+ * ---------------------------------------------------------------------- */\r
+ /** Reads the VCC Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if VCC Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void);\r
+\r
+/** Reads the SIO Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if SIO Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void);\r
+\r
+/** Reads the VBAT Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if VBAT Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void);\r
+\r
+/** Clears the VBAT Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register \r
+ */\r
+void p_pcr_chip_subsystem_vbat_reset_sts_clr(void);\r
+\r
+/** Reads the VCC1 Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if VCC1 Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void);\r
+\r
+/** Clears the VCC1 Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register \r
+ */\r
+void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void);\r
+\r
+/** Reads the 32K_ACTIVE status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if 32_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void);\r
+\r
+/** Reads the PCICLK_ACTIVE status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if CICLK_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void);\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Peripheral Function - Functions for Power Reset Control Register */ \r
+/* ---------------------------------------------------------------------- */\r
+/** Reads the iRESET_OUT bit in the Power Reset Control Register\r
+ * @return 1 if iRESET_OUT bit is set, else 0\r
+ */\r
+uint8_t p_pcr_iReset_Out_get(void);\r
+\r
+/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register\r
+ * @param 1 Set iRESET_OUT bit; 0 - Clear the bit\r
+ */\r
+void p_pcr_iReset_Out(uint8_t set_clr_flag);\r
+\r
+#endif // #ifndef _PCR_H\r
+/* end pcr.h */\r
+/** @}\r
+ */\r
+\r
+\r
+\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2015/11/24 06:28:28 $ \r
+$Author: amohandas $\r
+Last Change: Updated for tabs\r
+******************************************************************************/\r
+/** @file pcr_api.c\r
+* \brief Power, Clocks, and Resets API Source file\r
+* \author jvasanth\r
+* \r
+* This file implements the PCR APIs \r
+******************************************************************************/\r
+\r
+/** @defgroup PCR\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "pcr.h"\r
+\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Sets or Clears block specific bit in PCR Sleep Enable Register\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register\r
+ */\r
+void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)\r
+{\r
+ uint32_t bit_mask;\r
+ uint8_t pcr_reg_id; \r
+ \r
+ bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
+ pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu);\r
+\r
+ p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); \r
+}\r
+\r
+\r
+/** Get Clock Required Status for the block\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @return uint8_t - 1 if Clock Required Status set, else 0\r
+ */\r
+uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id)\r
+{\r
+ uint32_t bit_mask;\r
+ uint8_t pcr_reg_id, retVal; \r
+ \r
+ bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
+ pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu);\r
+\r
+ retVal = 0;\r
+ if (p_pcr_reg_get(pcr_reg_id, bit_mask))\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal;\r
+}\r
+\r
+/** Sets or Clears Reset Enable register bit for the block\r
+ * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT \r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register\r
+ */\r
+void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)\r
+{\r
+ uint32_t bit_mask;\r
+ uint8_t pcr_reg_id; \r
+ \r
+ bit_mask = 1UL<<(pcr_block_id & 0xFFu);\r
+ pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu);\r
+\r
+ p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); \r
+}\r
+\r
+\r
+/* ------------------------------------------------------------------------------- */\r
+/* Functions for entering low power modes */\r
+/* ------------------------------------------------------------------------------- */\r
+\r
+/** Instructs all blocks to sleep by setting the Sleep Enable bits */\r
+void pcr_all_blocks_sleep(void)\r
+{\r
+ p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0xFFFFFFFF);\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0xFFFFFFFF);\r
+ p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0xFFFFFFFF);\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF); \r
+}\r
+\r
+/** Clears the Sleep Enable bits for all blocks */\r
+ void pcr_all_blocks_wake(void)\r
+{\r
+ p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0);\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0);\r
+ p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0);\r
+ p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0); \r
+}\r
+\r
+/** Programs required sleep mode in System Sleep Control Register\r
+ * @param sleep_mode - see enum SYSTEM_SLEEP_MODES\r
+ */\r
+void pcr_system_sleep(uint8_t sleep_mode)\r
+{\r
+ p_pcr_system_sleep_ctrl_write(sleep_mode);\r
+}\r
+\r
+\r
+/* end pcr_api.c */\r
+/** @}\r
+ */\r
--- /dev/null
+/*****************************************************************************\r
+* © 2015 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+******************************************************************************\r
+\r
+Version Control Information (Perforce)\r
+******************************************************************************\r
+$Revision: #1 $ \r
+$DateTime: 2015/11/24 06:28:28 $ \r
+$Author: amohandas $\r
+Last Change: Updated for tabs\r
+******************************************************************************/\r
+/** @file pcr_perphl.c\r
+* \brief Power, Clocks, and Resets Peripheral Source file\r
+* \author jvasanth\r
+* \r
+* This file implements the PCR Peripheral functions \r
+******************************************************************************/\r
+\r
+/** @defgroup PCR\r
+ * @{\r
+ */\r
+\r
+#include "common_lib.h"\r
+#include "pcr.h"\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Generic functions to program and read 32-bit values from PCR Registers */\r
+/* ---------------------------------------------------------------------- */\r
+/** Writes 32-bit value in the PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param value - 32-bit value\r
+ */\r
+void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id;\r
+\r
+ *pPCR_Reg = value; \r
+}\r
+\r
+/** Reads 32-bit value from the PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @return value - 32-bit value\r
+ */\r
+uint32_t p_pcr_reg_read(uint8_t pcr_reg_id)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint32_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id; \r
+\r
+ retVal = *pPCR_Reg;\r
+\r
+ return retVal;\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to set, clr and get bits in PCR Registers */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Sets bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to set \r
+ */\r
+void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id;\r
+\r
+ *pPCR_Reg |= bit_mask; \r
+}\r
+\r
+/** Clears bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to clear \r
+ */\r
+void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id;\r
+\r
+ *pPCR_Reg &= ~bit_mask; \r
+}\r
+\r
+/** Read bits in a PCR Register\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to read \r
+ * @return value - 32-bit value\r
+ */\r
+uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint32_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE); \r
+\r
+ pPCR_Reg += pcr_reg_id; \r
+\r
+ retVal = (*pPCR_Reg) & bit_mask;\r
+\r
+ return retVal;\r
+}\r
+\r
+/** Sets or Clears bits in a PCR Register - Helper Function\r
+ * @param pcr_reg_id - pcr register id \r
+ * @param bit_mask - Bit mask of bits to set or clear\r
+ * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register\r
+ */\r
+void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag)\r
+{\r
+ if (set_clr_flag)\r
+ {\r
+ p_pcr_reg_set(pcr_reg_id, bit_mask);\r
+ }\r
+ else\r
+ {\r
+ p_pcr_reg_clr(pcr_reg_id, bit_mask);\r
+ } \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to operate on System Sleep Control Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/**\r
+ * Sets/Clears the Ring oscillator power down bit \r
+ * in System Sleep Control Register\r
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
+ */\r
+void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+ \r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;\r
+\r
+ if (set_clr_flag)\r
+ {\r
+ *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK; \r
+ }\r
+ else\r
+ {\r
+ *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK; \r
+ }\r
+}\r
+\r
+/** Sets/Clears the Ring oscillator output gate bit \r
+ * in System Sleep Control Register\r
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
+ */\r
+void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+ \r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;\r
+\r
+ if (set_clr_flag)\r
+ {\r
+ *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK; \r
+ }\r
+ else\r
+ {\r
+ *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK; \r
+ }\r
+}\r
+\r
+/** Sets/Clears the Core regulator standby bit \r
+ * in System Sleep Control Register\r
+ * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit\r
+ */\r
+void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+ \r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;\r
+\r
+ if (set_clr_flag)\r
+ {\r
+ *pPCR_Reg |= PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK; \r
+ }\r
+ else\r
+ {\r
+ *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK; \r
+ }\r
+}\r
+\r
+/** Writes required sleep mode in System Sleep Control Register\r
+ * @param sleep_value - System Sleep control value - [D2, D1, D0]\r
+ */\r
+void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+ \r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; \r
+\r
+ *pPCR_Reg = (sleep_value & 0x7); \r
+}\r
+\r
+/** Reads the System Sleep Control PCR Register\r
+ * @return value - byte 0 of the system sleep control PCR register\r
+ */\r
+uint8_t p_pcr_system_sleep_ctrl_read(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+ \r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; \r
+\r
+ retVal = (uint8_t)((*pPCR_Reg) & 0xFF);\r
+\r
+ return retVal;\r
+}\r
+\r
+\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to program to CLK Divide Value */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Writes the clock divide value in the Processor Clock Control Register\r
+ * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE\r
+ */\r
+void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL; \r
+\r
+ *pPCR_Reg = (clk_divide_value & 0xFF); \r
+ \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to program the slow clock divide value */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Write the slow clock divide value in the Slow Clock Control Register\r
+ * @param slow_clk_divide_value - slow clk divide value\r
+ */\r
+void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL; \r
+\r
+ *pPCR_Reg = (slow_clk_divide_value & 0x3FF); \r
+\r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Function to read the Oscillator Lock Status */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the Oscillator Lock status bit in the Oscillator ID Register\r
+ * @return 1 if Oscillator Lock Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_oscillator_lock_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal;\r
+ \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions to read various power status in Chip Sub-System register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the VCC Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if VCC Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Reads the SIO Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if SIO Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Reads the VBAT Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if VBAT Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Clears the VBAT Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register \r
+ */\r
+void p_pcr_chip_subsystem_vbat_reset_sts_clr(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;\r
+\r
+ // Write to clear\r
+ *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK;\r
+ \r
+}\r
+\r
+/** Reads the VCC1 Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if VCC1 Reset Status bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Clears the VCC1 Reset Status bit \r
+ * in the Chip Subsystem Power Reset Status Register \r
+ */\r
+void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;\r
+\r
+ // Write to clear\r
+ *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK;\r
+ \r
+}\r
+\r
+/** Reads the 32K_ACTIVE status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if 32_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal; \r
+}\r
+\r
+/** Reads the PCICLK_ACTIVE status bit \r
+ * in the Chip Subsystem Power Reset Status Register\r
+ * @return 1 if CICLK_ACTIVE bit is set, else 0\r
+ */\r
+uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ } \r
+ return retVal; \r
+}\r
+\r
+/* ---------------------------------------------------------------------- */\r
+/* Functions for Power Reset Control Register */\r
+/* ---------------------------------------------------------------------- */\r
+\r
+/** Reads the iRESET_OUT bit in the Power Reset Control Register\r
+ * @return 1 if iRESET_OUT bit is set, else 0\r
+ */\r
+uint8_t p_pcr_iReset_Out_get(void)\r
+{\r
+ __IO uint32_t *pPCR_Reg;\r
+ uint8_t retVal;\r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; \r
+\r
+ retVal = 0;\r
+ if (*pPCR_Reg & PCR_iRESET_OUT_BITMASK)\r
+ {\r
+ retVal = 1;\r
+ }\r
+ \r
+ return retVal;\r
+ \r
+}\r
+\r
+/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register\r
+ * @param 1 Set iRESET_OUT bit; 0 - Clear the bit\r
+ */\r
+void p_pcr_iReset_Out(uint8_t set_clr_flag)\r
+{\r
+ __IO uint32_t *pPCR_Reg; \r
+\r
+ pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;\r
+\r
+ *pPCR_Reg = (set_clr_flag & 0x1); \r
+}\r
+\r
+\r
+/* end pcr_perphl.c */\r
+/** @}\r
+ */\r
--- /dev/null
+/****************************************************************************\r
+* © 2013 Microchip Technology Inc. and its subsidiaries.\r
+* You may use this software and any derivatives exclusively with\r
+* Microchip products.\r
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".\r
+* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,\r
+* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,\r
+* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP\r
+* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.\r
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,\r
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND\r
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS\r
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.\r
+* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL\r
+* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF\r
+* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.\r
+* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE\r
+* OF THESE TERMS.\r
+*/\r
+\r
+/** @defgroup pwm pwm_c_wrapper\r
+ * @{\r
+ */\r
+/** @file pwm_c_wrapper.cpp\r
+ \brief the pwm component C wrapper \r
+ This program is designed to allow the other C programs to be able to use this component\r
+\r
+ There are entry points for all C wrapper API implementation\r
+\r
+<b>Platform:</b> This is ARC-based component \r
+\r
+<b>Toolset:</b> Metaware IDE(8.5.1)\r
+<b>Reference:</b> smsc_reusable_fw_requirement.doc */\r
+\r
+/*******************************************************************************\r
+ * SMSC version control information (Perforce):\r
+ *\r
+ * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/platform.h $\r
+ * REVISION: $Revision: #1 $\r
+ * DATETIME: $DateTime: 2015/12/23 15:37:58 $\r
+ * AUTHOR: $Author: akrishnan $\r
+ *\r
+ * Revision history (latest first):\r
+ * #xx\r
+ ***********************************************************************************\r
+ */\r
+\r
+#ifndef _PLATFORM_H_\r
+#define _PLATFORM_H_\r
+#include <stdint.h>\r
+/* Platform Configuration PreProcessor Conditions */\r
+#define TOOLKEIL 1\r
+#define TOOLPC 2\r
+#define TOOLMW 3\r
+#define TOOLMDK 4\r
+\r
+#define PCLINT 9 //added to satisfy PC Lint's need for a value here\r
+\r
+#ifdef __CC_ARM // Keil ARM MDK\r
+#define TOOLSET TOOLMDK\r
+#endif\r
+\r
+#if 0\r
+#ifdef _WIN32 //always defined by visual c++\r
+#define TOOLSET TOOLPC\r
+#endif\r
+\r
+#ifdef __WIN32__ //always defined by borland\r
+#define TOOLSET TOOLPC\r
+#endif\r
+#endif\r
+\r
+\r
+#ifdef _ARC\r
+#define TOOLSET TOOLMW // ARC Metaware\r
+#endif\r
+\r
+#ifndef TOOLSET\r
+//#error "ERROR: cfg.h TOOLSET not defined!"\r
+#endif\r
+\r
+#if TOOLSET == TOOLMDK\r
+#define _KEIL_ARM_ 1 /* Make 1 for Keil MDK Compiler */\r
+#define _KEIL_ 0 /* Make 1 for Keil Compiler */\r
+#define _PC_ 0 \r
+#define _ARC_CORE_ 0\r
+#endif\r
+\r
+#if TOOLSET == TOOLKEIL\r
+#define _KEIL_ARM_ 0\r
+#define _KEIL_ 1 /* Make 1 for Keil Compiler */\r
+#define _PC_ 0 \r
+#define _ARC_CORE_ 0\r
+#endif\r
+\r
+#if TOOLSET == TOOLPC\r
+#define _KEIL_ARM_ 0\r
+#define _KEIL_ 0 \r
+#define _PC_ 1 /* Make 1 for PC Environment */\r
+#define _ARC_CORE_ 0\r
+#endif\r
+\r
+#if TOOLSET == TOOLMW\r
+#define _KEIL_ARM_ 0\r
+#define _KEIL_ 0\r
+#define _PC_ 0\r
+#define _ARC_CORE_ 1\r
+#endif\r
+\r
+/* Short form for Standard Data Types */\r
+typedef unsigned char UINT8;\r
+typedef unsigned short UINT16;\r
+typedef unsigned long UINT32;\r
+\r
+typedef volatile unsigned char REG8;\r
+\r
+typedef unsigned char BYTE;\r
+typedef unsigned short WORD;\r
+typedef unsigned long DWORD;\r
+\r
+typedef unsigned char UCHAR;\r
+typedef unsigned short USHORT;\r
+typedef unsigned long ULONG;\r
+\r
+typedef unsigned char BOOL;\r
+typedef unsigned int UINT;\r
+\r
+/* signed types */\r
+typedef signed char INT8;\r
+typedef signed short INT16;\r
+typedef signed long INT32;\r
+\r
+typedef void VOID;\r
+\r
+/* union types */\r
+typedef union _BITS_8\r
+{\r
+ UINT8 byte;\r
+ struct\r
+ {\r
+ UINT8 bit0: 1;\r
+ UINT8 bit1: 1;\r
+ UINT8 bit2: 1;\r
+ UINT8 bit3: 1;\r
+ UINT8 bit4: 1;\r
+ UINT8 bit5: 1;\r
+ UINT8 bit6: 1;\r
+ UINT8 bit7: 1;\r
+ }bit;\r
+}BITS_8;\r
+\r
+\r
+/* MACROS FOR Platform Portability */\r
+\r
+/* macro for defining MMCR register */\r
+/* add MMCRARRAY() & EXTERNMMCRARRAY() */\r
+#if _KEIL_\r
+#define MMCR(name,address) volatile unsigned char xdata name _at_ address\r
+#define MMCRARRAY(name,length,address) volatile unsigned char xdata name[length] _at_ address\r
+#define MMCRTYPE(name,dtype,address) volatile dtype xdata name _at_ address\r
+#define EXTERNMMCR(name) extern volatile unsigned char xdata name\r
+#define EXTERNMMCRARRAY(name) extern volatile unsigned char xdata name[]\r
+#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype xdata name\r
+#define SFR(name,address) sfr name = address\r
+#define SFRBIT(name,address) sbit name = address\r
+#define EXTERNSFR(name) \r
+#define BITADDRESSTYPE(name) bit name\r
+#define XDATA xdata\r
+#define CODE code\r
+#define DATA data\r
+#define IDATA idata\r
+#define INTERRUPT(x) interrupt x\r
+#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;)\r
+#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;)\r
+#define NULLPTR (char *)(0)\r
+#define PLATFORM_TRIM_OSC() // TODO\r
+#define PNOP() \r
+#define DISABLE_INTERRUPTS() sfrIE_EAbit=0\r
+#define ENABLE_INTERRUPTS() sfrIE_EAbit=1\r
+#define SAVE_DIS_INTERRUPTS(x) { x=sfrIE_EAbit; sfrIE_EAbit=0; }\r
+#define RESTORE_INTERRUPTS(x) { sfrIE_EAbit=x; }\r
+#define ATOMIC_CPU_SLEEP()\r
+#define NUM_IRQ_VECTORS 12 // DW-8051\r
+#define IRQ_VECTOR_SIZE 8 \r
+#define USE_INLINE_PATCHER 1\r
+#define IRQ_VECTABLE_IN_RAM 0\r
+#define PLAT_ROM_IRQ_VECTOR_BASE 0x03 // ROM start\r
+#define PLAT_IRQ_VECTOR_BASE 0x1003 // RAM start\r
+#define FUNC_NEVER_RETURNS\r
+#define BEGIN_SMALL_DATA_BLOCK(x)\r
+#define END_SMALL_DATA_BLOCK()\r
+UINT32 soft_norm(UINT32 val);\r
+#define NORM(x) soft_norm(x)\r
+//\r
+#define USE_FUNC_REPLACEMENT 0\r
+#endif\r
+\r
+#if _PC_\r
+#define MMCR(name,address) volatile unsigned char name\r
+#define MMCRARRAY(name,length,address) volatile unsigned char name[length]\r
+#define MMCRTYPE(name,dtype,address) volatile dtype name\r
+#define EXTERNMMCR(name) extern volatile unsigned char name\r
+#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]\r
+#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name\r
+#define SFR(name,address) volatile unsigned char name\r
+#define SFRBIT(name,address) volatile unsigned char name\r
+#define EXTERNSFR(name) extern volatile unsigned char name\r
+#define BITADDRESSTYPE(name) volatile unsigned char name\r
+#define XDATA\r
+#define CODE \r
+#define DATA\r
+#define IDATA\r
+#define INTERRUPT(x)\r
+#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;)\r
+#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;)\r
+#define NULLPTR (char *)(0)\r
+#define PLATFORM_TRIM_OSC() // TODO\r
+#define PNOP() \r
+#define DISABLE_INTERRUPTS() \r
+#define ENABLE_INTERRUPTS()\r
+#define SAVE_DIS_INTERRUPTS(x) \r
+#define RESTORE_INTERRUPTS(x) \r
+#define ATOMIC_CPU_SLEEP()\r
+#define NUM_IRQ_VECTORS 24\r
+#define IRQ_VECTOR_SIZE 8\r
+#define USE_INLINE_PATCHER 1\r
+#define IRQ_VECTABLE_IN_RAM 0\r
+#define FUNC_NEVER_RETURNS\r
+#define BEGIN_SMALL_DATA_BLOCK(x)\r
+#define END_SMALL_DATA_BLOCK()\r
+UINT32 soft_norm(UINT32 val);\r
+#define NORM(x) soft_norm(x)\r
+//\r
+#define USE_FUNC_REPLACEMENT 0\r
+#endif\r
+\r
+#if _ARC_CORE_\r
+// ARC C has no equivalent operator to specify address of a variable\r
+// ARC MMCR's are 32-bit registers\r
+#define MMCR(name,address) volatile unsigned char name\r
+#define MMCRARRAY(name,length,address) volatile unsigned char name[length]\r
+#define MMCRTYPE(name,dtype,address) volatile dtype name \r
+#define EXTERNMMCR(name) extern volatile unsigned char name\r
+#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]\r
+#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name\r
+#define SFR(name,address) volatile unsigned char name \r
+#define SFRBIT(name,address) volatile unsigned char name \r
+#define EXTERNSFR(name) extern volatile unsigned char name \r
+#define BITADDRESSTYPE(name) \r
+#define XDATA\r
+#define CODE \r
+#define DATA\r
+#define IDATA\r
+#define INTERRUPT(x)\r
+#define SET_GLOBAL_INTR_ENABLE() (_enable())\r
+#define CLR_GLOBAL_INTR_ENABLE() (_disable())\r
+#define NULLPTR (char *)(0)\r
+#define NULLVOIDPTR (void *)(0)\r
+#define NULLFPTR (void (*)(void))0\r
+#define PLATFORM_TRIM_OSC() // TODO\r
+#define PNOP() _nop()\r
+#define DISABLE_INTERRUPTS() _disable()\r
+#define ENABLE_INTERRUPTS() _enable()\r
+#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); }\r
+#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); }\r
+#define ATOMIC_CPU_SLEEP() _flag(6);_sleep();_nop();_nop();\r
+#define NUM_IRQ_VECTORS 24\r
+#define IRQ_VECTOR_SIZE 8\r
+#define USE_INLINE_PATCHER 0\r
+#define DCCM_CODE_ALIAS_ADDR 0x00060000\r
+#define PLAT_ROM_IRQ_VECTOR_BASE 0\r
+#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR)\r
+/// y #define IRQ_VECTABLE_IN_RAM 1\r
+#define IRQ_VECTABLE_IN_RAM 0\r
+#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS)\r
+#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x)\r
+#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data()\r
+#define NORM(x) _norm(x)\r
+\r
+#define INLINE_FUNCTION(x) #pragma On_inline(x)\r
+\r
+//\r
+#define USE_FUNC_REPLACEMENT 0\r
+#endif\r
+\r
+#if _KEIL_ARM_\r
+// For ARM MDK compiler\r
+// ARM MMCR's are 32-bit registers\r
+#define MMCR(name,address) volatile unsigned char name\r
+#define MMCRARRAY(name,length,address) volatile unsigned char name[length]\r
+#define MMCRTYPE(name,dtype,address) volatile dtype name \r
+#define EXTERNMMCR(name) extern volatile unsigned char name\r
+#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]\r
+#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name\r
+#define SFR(name,address) volatile unsigned char name \r
+#define SFRBIT(name,address) volatile unsigned char name \r
+#define EXTERNSFR(name) extern volatile unsigned char name \r
+#define BITADDRESSTYPE(name) \r
+#define XDATA\r
+#define CODE \r
+#define DATA\r
+#define IDATA\r
+#define INTERRUPT(x)\r
+#define SET_GLOBAL_INTR_ENABLE() (__enable_irq())\r
+#define CLR_GLOBAL_INTR_ENABLE() (__disable_irq())\r
+#define NULLPTR (char *)(0)\r
+#define NULLVOIDPTR (void *)(0)\r
+#define NULLFPTR (void (*)(void))0\r
+#define PLATFORM_TRIM_OSC() // TODO\r
+#define PNOP() __NOP()\r
+#define DISABLE_INTERRUPTS() __disable_irq()\r
+#define ENABLE_INTERRUPTS() __enable_irq()\r
+#define ATOMIC_CPU_SLEEP() __wfi();__nop();__nop();\r
+\r
+#if 0 /* need further efforts if needed */\r
+#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); }\r
+#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); }\r
+#define NUM_IRQ_VECTORS 24\r
+#define IRQ_VECTOR_SIZE 8\r
+#define USE_INLINE_PATCHER 0\r
+#define DCCM_CODE_ALIAS_ADDR 0x00060000\r
+#define PLAT_ROM_IRQ_VECTOR_BASE 0\r
+#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR)\r
+/// y #define IRQ_VECTABLE_IN_RAM 1\r
+#define IRQ_VECTABLE_IN_RAM 0\r
+#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x)\r
+#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data()\r
+#define INLINE_FUNCTION(x) #pragma On_inline(x)\r
+#define USE_FUNC_REPLACEMENT 0\r
+#endif\r
+\r
+#if 0\r
+#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS)\r
+#define NORM(x) _norm(x)\r
+#else\r
+/* for ARM MDK */\r
+#define FUNC_NEVER_RETURNS\r
+UINT32 soft_norm(UINT32 val);\r
+#define NORM(x) soft_norm(x)\r
+#endif\r
+#endif\r
+\r
+/* General Constants */\r
+#define FALSE 0x00\r
+#define TRUE !FALSE\r
+\r
+#define BIT_n_MASK(n) (1U << (n))\r
+#define BIT_0_MASK (1<<0)\r
+#define BIT_1_MASK (1<<1)\r
+#define BIT_2_MASK (1<<2)\r
+#define BIT_3_MASK (1<<3)\r
+#define BIT_4_MASK (1<<4)\r
+#define BIT_5_MASK (1<<5)\r
+#define BIT_6_MASK (1<<6)\r
+#define BIT_7_MASK (1<<7)\r
+#define BIT_8_MASK ((UINT16)1<<8)\r
+#define BIT_9_MASK ((UINT16)1<<9)\r
+#define BIT_10_MASK ((UINT16)1<<10)\r
+#define BIT_11_MASK ((UINT16)1<<11)\r
+#define BIT_12_MASK ((UINT16)1<<12)\r
+#define BIT_13_MASK ((UINT16)1<<13)\r
+#define BIT_14_MASK ((UINT16)1<<14)\r
+#define BIT_15_MASK ((UINT16)1<<15)\r
+#define BIT_16_MASK ((UINT32)1<<16)\r
+#define BIT_17_MASK ((UINT32)1<<17)\r
+#define BIT_18_MASK ((UINT32)1<<18)\r
+#define BIT_19_MASK ((UINT32)1<<19)\r
+#define BIT_20_MASK ((UINT32)1<<20)\r
+#define BIT_21_MASK ((UINT32)1<<21)\r
+#define BIT_22_MASK ((UINT32)1<<22)\r
+#define BIT_23_MASK ((UINT32)1<<23)\r
+#define BIT_24_MASK ((UINT32)1<<24)\r
+#define BIT_25_MASK ((UINT32)1<<25)\r
+#define BIT_26_MASK ((UINT32)1<<26)\r
+#define BIT_27_MASK ((UINT32)1<<27)\r
+#define BIT_28_MASK ((UINT32)1<<28)\r
+#define BIT_29_MASK ((UINT32)1<<29)\r
+#define BIT_30_MASK ((UINT32)1<<30)\r
+#define BIT_31_MASK ((UINT32)1<<31)\r
+\r
+\r
+/* For CEC application */\r
+#define ON 1\r
+#define OFF 0\r
+\r
+#endif /*_PLATFORM_H_*/\r
+\r
+/** @}\r
+ */\r
+\r
projects / freertos / commitdiff