Changes for U-Boot 1.1.3:
======================================================================
+* Prepare for SoC rework of ARM code:
+ - rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL
+ - rename memsetup into lowlevel_init (function name and source files)
+
* Fix problems with SNTP support;
enable SNTP support in some boards.
This only takes effect if the memory commands are activated
globally (CFG_CMD_MEM).
+- CONFIG_INIT_CRITICAL
+ [ARM only] If this variable is NOT defined, then
+ certain critical initializations (like setting up the
+ memory controller) are omitted. Normally this
+ variable MUST be defined for all boards. The only
+ exception is when U-Boot is loaded (to RAM) by some
+ other boot loader or by a debugger which performs
+ these intializations itself.
+
Building the Software:
======================
LEDS: .long NEPONSET_LEDS
- .globl memsetup
-memsetup:
+ .globl lowlevel_init
+lowlevel_init:
/* Setting up the memory and stuff */
LIB = lib$(BOARD).a
OBJS := cerf250.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Set up GPIO pins first ----------------------------------------- */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ ldr r0, =PSSR /* enable GPIO pins */
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2a: Initialize Asynchronous static memory controller */
+ /* ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* that data latches */
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2b: Initialize Card Interface */
+ /* ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+ ldr r2, [r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, [r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+ ldr r2, [r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, [r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, [r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, [r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, [r1, #MCIO1_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
+
+ /* Before accessing MDREFR we need a valid DRI field, so we set */
+ /* this to power on defaults + DRI field, set SDRAM clocks free running */
+
+ ldr r3, =CFG_MDREFR_VAL
+ ldr r2, =0xFFF
+ and r3, r3, r2
+
+ ldr r0, [r1, #MDREFR_OFFSET]
+ bic r0, r0, r2
+ bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
+ orr r0, r0, r3
+
+ str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+ /* ---------------------------------------------------------------- */
+
+ /* Initialize SXCNFG register. Assert the enable bits */
+
+ /* Write SXMRS to cause an MRS command to all enabled banks of */
+ /* synchronous static memory. Note that SXLCR need not be written */
+ /* at this time. */
+
+ /* FIXME: we use async mode for now */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
+
+ /* set MDREFR according to user define with exception of a few bits */
+
+ ldr r4, =CFG_MDREFR_VAL
+ ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
+ MDREFR_K2RUN |MDREFR_K2DB2)
+ and r4, r4, r2
+ bic r0, r0, r2
+ orr r0, r0, r4
+
+ str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r0, [r1, #MDREFR_OFFSET]
+
+ /* Step 4b: de-assert MDREFR:SLFRSH. */
+
+ bic r0, r0, #(MDREFR_SLFRSH)
+ str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r0, [r1, #MDREFR_OFFSET]
+
+
+ /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */
+
+ ldr r4, =CFG_MDREFR_VAL
+ ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
+ MDREFR_K1FREE | MDREFR_K2FREE)
+ and r4, r4, r2
+ orr r0, r0, r4
+ str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r0, [r1, #MDREFR_OFFSET]
+
+
+ /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
+ /* configure but not enable each SDRAM partition pair. */
+
+ ldr r4, =CFG_MDCNFG_VAL
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+ bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
+
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
+ /* 100..200 µsec. */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by */
+ /* attempting non-burst read or write accesses to disabled */
+ /* SDRAM, as commonly specified in the power up sequence */
+ /* documented in SDRAM data sheets. The address(es) used */
+ /* for this purpose must not be cacheable. */
+
+ ldr r3, =CFG_DRAM_BASE
+.rept 8
+ str r2, [r3]
+.endr
+
+ /* Step 4g: Write MDCNFG with enable bits asserted */
+ /* (MDCNFG:DEx set to 1). */
+
+ ldr r3, [r1, #MDCNFG_OFFSET]
+ orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
+ str r3, [r1, #MDCNFG_OFFSET]
+
+ /* Step 4h: Write MDMRS. */
+
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+
+ /* We are finished with Intel's memory controller initialisation */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Disable (mask) all interrupts at interrupt controller */
+ /* ---------------------------------------------------------------- */
+
+initirqs:
+
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
+
+
+ /* ---------------------------------------------------------------- */
+ /* Clock initialisation */
+ /* ---------------------------------------------------------------- */
+
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency */
+
+ /* Turn Off ALL on-chip peripheral clocks for re-configuration */
+ /* Note: See label 'ENABLECLKS' for the re-enabling */
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+
+ /* default value in case no valid rotary switch setting is found */
+ ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
+
+ /* ... and write the core clock config register */
+ ldr r1, =CCCR
+ str r2, [r1]
+
+#ifdef RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
+ /* has settled. */
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* */
+ /* ---------------------------------------------------------------- */
+
+ /* Save SDRAM size */
+ ldr r1, =DRAM_SIZE
+ str r8, [r1]
+
+ /* Interrupt init: Mask all interrupts */
+ ldr r0, =ICMR /* enable no sources */
+ mov r1, #0
+ str r1, [r0]
+
+ /* FIXME */
+
+#define NODEBUG
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+ mov pc, lr
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CFG_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-/*
- * Memory setup
- */
-
-.globl memsetup
-memsetup:
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CFG_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CFG_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CFG_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CFG_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CFG_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CFG_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CFG_PSSR_VAL
- str r1, [r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field, set SDRAM clocks free running */
-
- ldr r3, =CFG_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
-
- ldr r0, [r1, #MDREFR_OFFSET]
- bic r0, r0, r2
- bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
- orr r0, r0, r3
-
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* set MDREFR according to user define with exception of a few bits */
-
- ldr r4, =CFG_MDREFR_VAL
- ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
- MDREFR_K2RUN |MDREFR_K2DB2)
- and r4, r4, r2
- bic r0, r0, r2
- orr r0, r0, r4
-
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r0, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r0, r0, #(MDREFR_SLFRSH)
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r0, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */
-
- ldr r4, =CFG_MDREFR_VAL
- ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
- MDREFR_K1FREE | MDREFR_K2FREE)
- and r4, r4, r2
- orr r0, r0, r4
- str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r0, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CFG_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CFG_DRAM_BASE
-.rept 8
- str r2, [r3]
-.endr
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
-
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End memsetup */
- /* ---------------------------------------------------------------- */
-
-endmemsetup:
-
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := cradle.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+ .macro SET_LED val
+ ldr r6, =CRADLE_LED_CLR_REG
+ ldr r7, =0
+ str r7, [r6]
+ ldr r6, =CRADLE_LED_SET_REG
+ ldr r7, =\val
+ str r7, [r6]
+ .endm
+
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+ /* Set up GPIO pins first */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER0
+ ldr r1, =CFG_GRER0_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER1
+ ldr r1, =CFG_GRER1_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER2
+ ldr r1, =CFG_GRER2_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER0
+ ldr r1, =CFG_GFER0_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER1
+ ldr r1, =CFG_GFER1_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER2
+ ldr r1, =CFG_GFER2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ /* enable GPIO pins */
+ ldr r0, =PSSR
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+ SET_LED 1
+
+ ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */
+ ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */
+ str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */
+ ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */
+
+
+/*********************************************************************
+ Initlialize Memory Controller
+
+ See PXA250 Operating System Developer's Guide
+
+ pause for 200 uSecs- allow internal clocks to settle
+ *Note: only need this if hard reset... doing it anyway for now
+*/
+
+ @ Step 1
+ @ ---- Wait 200 usec
+ ldr r3, =OSCR @ reset the OS Timer Count to zero
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+ SET_LED 2
+
+mem_init:
+ @ get memory controller base address
+ ldr r1, =MEMC_BASE
+
+
+@****************************************************************************
+@ Step 2
+@
+
+ @ Step 2a
+ @ write msc0, read back to ensure data latches
+ @
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET]
+
+ @ write msc1
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ @ write msc2
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ @ Step 2b
+ @ write mecr
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+
+ @ write mcmem0
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+
+ @ write mcmem1
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+
+ @ write mcatt0
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+
+ @ write mcatt1
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+
+ @ write mcio0
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+
+ @ write mcio1
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+
+ /*SET_LED 3 */
+
+ @ Step 2c
+ @ fly-by-dma is defeatured on this part
+ @ write flycnfg
+ @ldr r2, =CFG_FLYCNFG_VAL
+ @str r2, [r1, #FLYCNFG_OFFSET]
+
+/* FIXME Does this sequence really make sense */
+#ifdef REDBOOT_WAY
+ @ Step 2d
+ @ get the mdrefr settings
+ ldr r3, =CFG_MDREFR_VAL
+
+ @ extract DRI field (we need a valid DRI field)
+ @
+ ldr r2, =0xFFF
+
+ @ valid DRI field in r3
+ @
+ and r3, r3, r2
+
+ @ get the reset state of MDREFR
+ @
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ clear the DRI field
+ @
+ bic r4, r4, r2
+
+ @ insert the valid DRI field loaded above
+ @
+ orr r4, r4, r3
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ *Note: preserve the mdrefr value in r4 *
+
+ /*SET_LED 4 */
+
+@****************************************************************************
+@ Step 3
+@
+@ NO SRAM
+
+ mov pc, r10
+
+
+@****************************************************************************
+@ Step 4
+@
+
+ @ Assumes previous mdrefr value in r4, if not then read current mdrefr
+
+ @ clear the free-running clock bits
+ @ (clear K0Free, K1Free, K2Free
+ @
+ bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
+
+ @ set K0RUN for CPLD clock
+ @
+ orr r4, r4, #0x00002000
+
+ @ set K1RUN if bank 0 installed
+ @
+ orr r4, r4, #0x00010000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ deassert SLFRSH
+ @
+ bic r4, r4, #0x00400000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ assert E1PIN
+ @
+ orr r4, r4, #0x00008000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+ nop
+ nop
+#else
+ @ Step 2d
+ @ get the mdrefr settings
+ ldr r3, =CFG_MDREFR_VAL
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ Step 4
+
+ @ set K0RUN for CPLD clock
+ @
+ orr r4, r4, #0x00002000
+
+ @ set K1RUN for bank 0
+ @
+ orr r4, r4, #0x00010000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ deassert SLFRSH
+ @
+ bic r4, r4, #0x00400000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ assert E1PIN
+ @
+ orr r4, r4, #0x00008000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+ nop
+ nop
+#endif
+
+ @ Step 4d
+ @ fetch platform value of mdcnfg
+ @
+ ldr r2, =CFG_MDCNFG_VAL
+
+ @ disable all sdram banks
+ @
+ bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
+ bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
+
+ @ program banks 0/1 for bus width
+ @
+ bic r2, r2, #MDCNFG_DWID0 @0=32-bit
+
+ @ write initial value of mdcnfg, w/o enabling sdram banks
+ @
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ @ Step 4e
+ @ pause for 200 uSecs
+ @
+ ldr r3, =OSCR @ reset the OS Timer Count to zero
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+ /*SET_LED 5 */
+
+ /* Why is this here??? */
+ mov r0, #0x78 @turn everything off
+ mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
+
+ @ Step 4f
+ @ Access memory *not yet enabled* for CBR refresh cycles (8)
+ @ - CBR is generated for all banks
+
+ ldr r2, =CFG_DRAM_BASE
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+
+ @ Step 4g
+ @get memory controller base address
+ @
+ ldr r1, =MEMC_BASE
+
+ @fetch current mdcnfg value
+ @
+ ldr r3, [r1, #MDCNFG_OFFSET]
+
+ @enable sdram bank 0 if installed (must do for any populated bank)
+ @
+ orr r3, r3, #MDCNFG_DE0
+
+ @write back mdcnfg, enabling the sdram bank(s)
+ @
+ str r3, [r1, #MDCNFG_OFFSET]
+
+ @ Step 4h
+ @ write mdmrs
+ @
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+ @ Done Memory Init
+
+ /*SET_LED 6 */
+
+ @********************************************************************
+ @ Disable (mask) all interrupts at the interrupt controller
+ @
+
+ @ clear the interrupt level register (use IRQ, not FIQ)
+ @
+ mov r1, #0
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ @ Set interrupt mask register
+ @
+ ldr r1, =CFG_ICMR_VAL
+ ldr r2, =ICMR
+ str r1, [r2]
+
+ @ ********************************************************************
+ @ Disable the peripheral clocks, and set the core clock
+ @
+
+ @ Turn Off ALL on-chip peripheral clocks for re-configuration
+ @
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+ @ set core clocks
+ @
+ ldr r2, =CFG_CCCR_VAL
+ ldr r1, =CCCR
+ str r2, [r1]
+
+#ifdef ENABLE32KHZ
+ @ enable the 32Khz oscillator for RTC and PowerManager
+ @
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ @ NOTE: spin here until OSCC.OOK get set,
+ @ meaning the PLL has settled.
+ @
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+#endif
+
+ @ Turn on needed clocks
+ @
+ ldr r1, =CKEN
+ ldr r2, =CFG_CKEN_VAL
+ str r2, [r1]
+
+ /*SET_LED 7 */
+
+/* Is this needed???? */
+#define NODEBUG
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
+#endif
+
+ /*SET_LED 8 */
+
+ mov pc, r10
+
+@ End lowlevel_init
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CFG_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
- .macro SET_LED val
- ldr r6, =CRADLE_LED_CLR_REG
- ldr r7, =0
- str r7, [r6]
- ldr r6, =CRADLE_LED_SET_REG
- ldr r7, =\val
- str r7, [r6]
- .endm
-
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
- /* Set up GPIO pins first */
-
- ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GRER0
- ldr r1, =CFG_GRER0_VAL
- str r1, [r0]
-
- ldr r0, =GRER1
- ldr r1, =CFG_GRER1_VAL
- str r1, [r0]
-
- ldr r0, =GRER2
- ldr r1, =CFG_GRER2_VAL
- str r1, [r0]
-
- ldr r0, =GFER0
- ldr r1, =CFG_GFER0_VAL
- str r1, [r0]
-
- ldr r0, =GFER1
- ldr r1, =CFG_GFER1_VAL
- str r1, [r0]
-
- ldr r0, =GFER2
- ldr r1, =CFG_GFER2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CFG_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CFG_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CFG_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CFG_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CFG_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CFG_GAFR2_U_VAL
- str r1, [r0]
-
- /* enable GPIO pins */
- ldr r0, =PSSR
- ldr r1, =CFG_PSSR_VAL
- str r1, [r0]
-
- SET_LED 1
-
- ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */
- ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */
- str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */
- ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */
-
-
-/*********************************************************************
- Initlialize Memory Controller
-
- See PXA250 Operating System Developer's Guide
-
- pause for 200 uSecs- allow internal clocks to settle
- *Note: only need this if hard reset... doing it anyway for now
-*/
-
- @ Step 1
- @ ---- Wait 200 usec
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- SET_LED 2
-
-mem_init:
- @ get memory controller base address
- ldr r1, =MEMC_BASE
-
-
-@****************************************************************************
-@ Step 2
-@
-
- @ Step 2a
- @ write msc0, read back to ensure data latches
- @
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
- @ write msc1
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- @ write msc2
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- @ Step 2b
- @ write mecr
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
-
- @ write mcmem0
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
-
- @ write mcmem1
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
-
- @ write mcatt0
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
-
- @ write mcatt1
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
-
- @ write mcio0
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
-
- @ write mcio1
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
-
- /*SET_LED 3 */
-
- @ Step 2c
- @ fly-by-dma is defeatured on this part
- @ write flycnfg
- @ldr r2, =CFG_FLYCNFG_VAL
- @str r2, [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CFG_MDREFR_VAL
-
- @ extract DRI field (we need a valid DRI field)
- @
- ldr r2, =0xFFF
-
- @ valid DRI field in r3
- @
- and r3, r3, r2
-
- @ get the reset state of MDREFR
- @
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ clear the DRI field
- @
- bic r4, r4, r2
-
- @ insert the valid DRI field loaded above
- @
- orr r4, r4, r3
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ *Note: preserve the mdrefr value in r4 *
-
- /*SET_LED 4 */
-
-@****************************************************************************
-@ Step 3
-@
-@ NO SRAM
-
- mov pc, r10
-
-
-@****************************************************************************
-@ Step 4
-@
-
- @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
- @ clear the free-running clock bits
- @ (clear K0Free, K1Free, K2Free
- @
- bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN if bank 0 installed
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#else
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CFG_MDREFR_VAL
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ Step 4
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN for bank 0
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#endif
-
- @ Step 4d
- @ fetch platform value of mdcnfg
- @
- ldr r2, =CFG_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- @ Step 4e
- @ pause for 200 uSecs
- @
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /*SET_LED 5 */
-
- /* Why is this here??? */
- mov r0, #0x78 @turn everything off
- mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
-
- @ Step 4f
- @ Access memory *not yet enabled* for CBR refresh cycles (8)
- @ - CBR is generated for all banks
-
- ldr r2, =CFG_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
- @ Step 4g
- @get memory controller base address
- @
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- @ Step 4h
- @ write mdmrs
- @
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- @ Done Memory Init
-
- /*SET_LED 6 */
-
- @********************************************************************
- @ Disable (mask) all interrupts at the interrupt controller
- @
-
- @ clear the interrupt level register (use IRQ, not FIQ)
- @
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
- @ Set interrupt mask register
- @
- ldr r1, =CFG_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
- @ ********************************************************************
- @ Disable the peripheral clocks, and set the core clock
- @
-
- @ Turn Off ALL on-chip peripheral clocks for re-configuration
- @
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
- @ set core clocks
- @
- ldr r2, =CFG_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef ENABLE32KHZ
- @ enable the 32Khz oscillator for RTC and PowerManager
- @
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- @ NOTE: spin here until OSCC.OOK get set,
- @ meaning the PLL has settled.
- @
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
- ldr r1, =CKEN
- ldr r2, =CFG_CKEN_VAL
- str r2, [r1]
-
- /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /*SET_LED 8 */
-
- mov pc, r10
-
-@ End memsetup
LIB = lib$(BOARD).a
OBJS := csb226.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+ /* Set up GPIO pins first ----------------------------------------- */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ ldr r0, =PSSR /* enable GPIO pins */
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
+/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
+/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
+/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
+/* */
+/* ldr r1, =LED_BLANK */
+/* mov r0, #0xFF */
+/* str r0, [r1] / turn on hex leds */
+/* */
+/*loop: */
+/* */
+/* ldr r0, =0xB0070001 */
+/* ldr r1, =_LED */
+/* str r0, [r1] / hex display */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2a: Initialize Asynchronous static memory controller */
+ /* ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* that data latches */
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2b: Initialize Card Interface */
+ /* ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+ ldr r2, [r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, [r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+ ldr r2, [r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, [r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, [r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, [r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, [r1, #MCIO1_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
+
+ /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
+ adr r3, mem_init /* r0 <- current position of code */
+ ldr r2, =mem_init
+ cmp r3, r2 /* skip init if in place */
+ beq initirqs
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
+
+ /* Before accessing MDREFR we need a valid DRI field, so we set */
+ /* this to power on defaults + DRI field. */
+
+ ldr r3, =CFG_MDREFR_VAL
+ ldr r2, =0xFFF
+ and r3, r3, r2
+ ldr r4, =0x03ca4000
+ orr r4, r4, r3
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+ /* ---------------------------------------------------------------- */
+
+ /* Initialize SXCNFG register. Assert the enable bits */
+
+ /* Write SXMRS to cause an MRS command to all enabled banks of */
+ /* synchronous static memory. Note that SXLCR need not be written */
+ /* at this time. */
+
+ /* FIXME: we use async mode for now */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
+
+ /* Step 4a: assert MDREFR:K?RUN and configure */
+ /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
+
+ ldr r4, =CFG_MDREFR_VAL
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Step 4b: de-assert MDREFR:SLFRSH. */
+
+ bic r4, r4, #(MDREFR_SLFRSH)
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* Step 4c: assert MDREFR:E1PIN and E0PIO */
+
+ orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
+ /* configure but not enable each SDRAM partition pair. */
+
+ ldr r4, =CFG_MDCNFG_VAL
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
+
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
+ /* 100..200 µsec. */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by */
+ /* attempting non-burst read or write accesses to disabled */
+ /* SDRAM, as commonly specified in the power up sequence */
+ /* documented in SDRAM data sheets. The address(es) used */
+ /* for this purpose must not be cacheable. */
+
+ /* There should 9 writes, since the first write doesn't */
+ /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
+ /* PXA210 Processors Specification Update, */
+ /* Jan 2003, Errata #116, page 30. */
+
+
+ ldr r3, =CFG_DRAM_BASE
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+ /* Step 4g: Write MDCNFG with enable bits asserted */
+ /* (MDCNFG:DEx set to 1). */
+
+ ldr r3, [r1, #MDCNFG_OFFSET]
+ orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
+ str r3, [r1, #MDCNFG_OFFSET]
+
+ /* Step 4h: Write MDMRS. */
+
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+
+ /* We are finished with Intel's memory controller initialisation */
+
+ /* ---------------------------------------------------------------- */
+ /* Disable (mask) all interrupts at interrupt controller */
+ /* ---------------------------------------------------------------- */
+
+initirqs:
+
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
+
+
+ /* ---------------------------------------------------------------- */
+ /* Clock initialisation */
+ /* ---------------------------------------------------------------- */
+
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency */
+ /* (hard-coding at 398.12MHz for now). */
+
+ /* Turn Off ALL on-chip peripheral clocks for re-configuration */
+ /* Note: See label 'ENABLECLKS' for the re-enabling */
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+
+ /* default value in case no valid rotary switch setting is found */
+ ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
+
+ /* ... and write the core clock config register */
+ ldr r1, =CCCR
+ str r2, [r1]
+
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+/*
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+*/
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
+ /* has settled. */
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+
+ /* ---------------------------------------------------------------- */
+ /* */
+ /* ---------------------------------------------------------------- */
+
+ /* Save SDRAM size */
+ ldr r1, =DRAM_SIZE
+ str r8, [r1]
+
+ /* Interrupt init: Mask all interrupts */
+ ldr r0, =ICMR /* enable no sources */
+ mov r1, #0
+ str r1, [r0]
+
+ /* FIXME */
+
+#ifndef DEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+ mov pc, lr
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CFG_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-
-/*
- * Memory setup
- */
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CFG_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CFG_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CFG_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CFG_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CFG_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CFG_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CFG_PSSR_VAL
- str r1, [r0]
-
-/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
-/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
-/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
-/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/* ldr r1, =LED_BLANK */
-/* mov r0, #0xFF */
-/* str r0, [r1] / turn on hex leds */
-/* */
-/*loop: */
-/* */
-/* ldr r0, =0xB0070001 */
-/* ldr r1, =_LED */
-/* str r0, [r1] / hex display */
-
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
- adr r3, mem_init /* r0 <- current position of code */
- ldr r2, =mem_init
- cmp r3, r2 /* skip init if in place */
- beq initirqs
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CFG_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* Step 4a: assert MDREFR:K?RUN and configure */
- /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
-
- ldr r4, =CFG_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO */
-
- orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CFG_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- /* There should 9 writes, since the first write doesn't */
- /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
- /* PXA210 Processors Specification Update, */
- /* Jan 2003, Errata #116, page 30. */
-
-
- ldr r3, =CFG_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
- /* enable the 32Khz oscillator for RTC and PowerManager */
-/*
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-*/
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#ifndef DEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End memsetup */
- /* ---------------------------------------------------------------- */
-
-endmemsetup:
-
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := B2.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures
+ * Modified By MATTO
+ *
+ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Documentation:
+ * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
+ * Advanced Developer's manual, December 1999
+ *
+ * Intel has a very hard to find SDRAM configurator on their web site:
+ * http://appzone.intel.com/hcd/sa1110/memory/index.asp
+ *
+ * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
+ * appears to be true, but it might be possible that somebody designs a
+ * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
+ *
+ * 04-10-2001: SELETZ
+ * - separated memory config for multiple platform support
+ * - perform SA1110 Hardware Reset Procedure
+ *
+ */
+
+.equ B0_Tacs, 0x0 /* 0clk */
+.equ B0_Tcos, 0x0 /* 0clk */
+.equ B0_Tacc, 0x4 /* 6clk */
+.equ B0_Tcoh, 0x0 /* 0clk */
+.equ B0_Tah, 0x0 /* 0clk */
+.equ B0_Tacp, 0x0 /* 0clk */
+.equ B0_PMC, 0x0 /* normal(1data) */
+/* Bank 1 parameter */
+.equ B1_Tacs, 0x3 /* 4clk */
+.equ B1_Tcos, 0x3 /* 4clk */
+.equ B1_Tacc, 0x7 /* 14clkv */
+.equ B1_Tcoh, 0x3 /* 4clk */
+.equ B1_Tah, 0x3 /* 4clk */
+.equ B1_Tacp, 0x3 /* 6clk */
+.equ B1_PMC, 0x0 /* normal(1data) */
+
+/* Bank 2 parameter - LAN91C96 */
+.equ B2_Tacs, 0x3 /* 4clk */
+.equ B2_Tcos, 0x3 /* 4clk */
+.equ B2_Tacc, 0x7 /* 14clk */
+.equ B2_Tcoh, 0x3 /* 4clk */
+.equ B2_Tah, 0x3 /* 4clk */
+.equ B2_Tacp, 0x3 /* 6clk */
+.equ B2_PMC, 0x0 /* normal(1data) */
+
+/* Bank 3 parameter */
+.equ B3_Tacs, 0x3 /* 4clk */
+.equ B3_Tcos, 0x3 /* 4clk */
+.equ B3_Tacc, 0x7 /* 14clk */
+.equ B3_Tcoh, 0x3 /* 4clk */
+.equ B3_Tah, 0x3 /* 4clk */
+.equ B3_Tacp, 0x3 /* 6clk */
+.equ B3_PMC, 0x0 /* normal(1data) */
+
+/* Bank 4 parameter */
+.equ B4_Tacs, 0x3 /* 4clk */
+.equ B4_Tcos, 0x3 /* 4clk */
+.equ B4_Tacc, 0x7 /* 14clk */
+.equ B4_Tcoh, 0x3 /* 4clk */
+.equ B4_Tah, 0x3 /* 4clk */
+.equ B4_Tacp, 0x3 /* 6clk */
+.equ B4_PMC, 0x0 /* normal(1data) */
+
+/* Bank 5 parameter */
+.equ B5_Tacs, 0x3 /* 4clk */
+.equ B5_Tcos, 0x3 /* 4clk */
+.equ B5_Tacc, 0x7 /* 14clk */
+.equ B5_Tcoh, 0x3 /* 4clk */
+.equ B5_Tah, 0x3 /* 4clk */
+.equ B5_Tacp, 0x3 /* 6clk */
+.equ B5_PMC, 0x0 /* normal(1data) */
+
+/* Bank 6(if SROM) parameter */
+.equ B6_Tacs, 0x3 /* 4clk */
+.equ B6_Tcos, 0x3 /* 4clk */
+.equ B6_Tacc, 0x7 /* 14clk */
+.equ B6_Tcoh, 0x3 /* 4clk */
+.equ B6_Tah, 0x3 /* 4clk */
+.equ B6_Tacp, 0x3 /* 6clk */
+.equ B6_PMC, 0x0 /* normal(1data) */
+
+/* Bank 7(if SROM) parameter */
+.equ B7_Tacs, 0x3 /* 4clk */
+.equ B7_Tcos, 0x3 /* 4clk */
+.equ B7_Tacc, 0x7 /* 14clk */
+.equ B7_Tcoh, 0x3 /* 4clk */
+.equ B7_Tah, 0x3 /* 4clk */
+.equ B7_Tacp, 0x3 /* 6clk */
+.equ B7_PMC, 0x0 /* normal(1data) */
+
+/* Bank 6 parameter */
+.equ B6_MT, 0x3 /* SDRAM */
+.equ B6_Trcd, 0x0 /* 2clk */
+.equ B6_SCAN, 0x0 /* 10bit */
+
+.equ B7_MT, 0x3 /* SDRAM */
+.equ B7_Trcd, 0x0 /* 2clk */
+.equ B7_SCAN, 0x0 /* 10bit */
+
+
+/* REFRESH parameter */
+.equ REFEN, 0x1 /* Refresh enable */
+.equ TREFMD, 0x0 /* CBR(CAS before RAS)/Auto refresh */
+.equ Trp, 0x0 /* 2clk */
+.equ Trc, 0x3 /* 0x1=5clk 0x3=11clk*/
+.equ Tchr, 0x0 /* 0x2=3clk 0x0=0clks */
+.equ REFCNT, 879
+
+MEMORY_CONFIG:
+ .long 0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/
+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/
+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/
+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/
+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/
+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/
+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /*GCS6*/
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /*GCS7*/
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/
+ .word 0x17 /*SCLK power down mode, BANKSIZE 16M/16M*/
+ .word 0x20 /*MRSR6 CL=2clk*/
+ .word 0x20 /*MRSR7*/
+
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /*
+ the next instruction fail due memory relocation...
+ we'll find the right MEMORY_CONFIG address with the next 3 lines...
+ */
+ /*ldr r0, =MEMORY_CONFIG*/
+ mov r0, pc
+ ldr r1, =(0x38+4)
+ sub r0, r0, r1
+
+ ldmia r0, {r1-r13}
+ ldr r0, =0x01c80000
+ stmia r0, {r1-r13}
+ mov pc, lr
+++ /dev/null
-/*
- * (C) Copyright 2004
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures
- * Modified By MATTO
- *
- * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-/*
- * Documentation:
- * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
- * Advanced Developer's manual, December 1999
- *
- * Intel has a very hard to find SDRAM configurator on their web site:
- * http://appzone.intel.com/hcd/sa1110/memory/index.asp
- *
- * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
- * appears to be true, but it might be possible that somebody designs a
- * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
- *
- * 04-10-2001: SELETZ
- * - separated memory config for multiple platform support
- * - perform SA1110 Hardware Reset Procedure
- *
- */
-
-.equ B0_Tacs, 0x0 /* 0clk */
-.equ B0_Tcos, 0x0 /* 0clk */
-.equ B0_Tacc, 0x4 /* 6clk */
-.equ B0_Tcoh, 0x0 /* 0clk */
-.equ B0_Tah, 0x0 /* 0clk */
-.equ B0_Tacp, 0x0 /* 0clk */
-.equ B0_PMC, 0x0 /* normal(1data) */
-/* Bank 1 parameter */
-.equ B1_Tacs, 0x3 /* 4clk */
-.equ B1_Tcos, 0x3 /* 4clk */
-.equ B1_Tacc, 0x7 /* 14clkv */
-.equ B1_Tcoh, 0x3 /* 4clk */
-.equ B1_Tah, 0x3 /* 4clk */
-.equ B1_Tacp, 0x3 /* 6clk */
-.equ B1_PMC, 0x0 /* normal(1data) */
-
-/* Bank 2 parameter - LAN91C96 */
-.equ B2_Tacs, 0x3 /* 4clk */
-.equ B2_Tcos, 0x3 /* 4clk */
-.equ B2_Tacc, 0x7 /* 14clk */
-.equ B2_Tcoh, 0x3 /* 4clk */
-.equ B2_Tah, 0x3 /* 4clk */
-.equ B2_Tacp, 0x3 /* 6clk */
-.equ B2_PMC, 0x0 /* normal(1data) */
-
-/* Bank 3 parameter */
-.equ B3_Tacs, 0x3 /* 4clk */
-.equ B3_Tcos, 0x3 /* 4clk */
-.equ B3_Tacc, 0x7 /* 14clk */
-.equ B3_Tcoh, 0x3 /* 4clk */
-.equ B3_Tah, 0x3 /* 4clk */
-.equ B3_Tacp, 0x3 /* 6clk */
-.equ B3_PMC, 0x0 /* normal(1data) */
-
-/* Bank 4 parameter */
-.equ B4_Tacs, 0x3 /* 4clk */
-.equ B4_Tcos, 0x3 /* 4clk */
-.equ B4_Tacc, 0x7 /* 14clk */
-.equ B4_Tcoh, 0x3 /* 4clk */
-.equ B4_Tah, 0x3 /* 4clk */
-.equ B4_Tacp, 0x3 /* 6clk */
-.equ B4_PMC, 0x0 /* normal(1data) */
-
-/* Bank 5 parameter */
-.equ B5_Tacs, 0x3 /* 4clk */
-.equ B5_Tcos, 0x3 /* 4clk */
-.equ B5_Tacc, 0x7 /* 14clk */
-.equ B5_Tcoh, 0x3 /* 4clk */
-.equ B5_Tah, 0x3 /* 4clk */
-.equ B5_Tacp, 0x3 /* 6clk */
-.equ B5_PMC, 0x0 /* normal(1data) */
-
-/* Bank 6(if SROM) parameter */
-.equ B6_Tacs, 0x3 /* 4clk */
-.equ B6_Tcos, 0x3 /* 4clk */
-.equ B6_Tacc, 0x7 /* 14clk */
-.equ B6_Tcoh, 0x3 /* 4clk */
-.equ B6_Tah, 0x3 /* 4clk */
-.equ B6_Tacp, 0x3 /* 6clk */
-.equ B6_PMC, 0x0 /* normal(1data) */
-
-/* Bank 7(if SROM) parameter */
-.equ B7_Tacs, 0x3 /* 4clk */
-.equ B7_Tcos, 0x3 /* 4clk */
-.equ B7_Tacc, 0x7 /* 14clk */
-.equ B7_Tcoh, 0x3 /* 4clk */
-.equ B7_Tah, 0x3 /* 4clk */
-.equ B7_Tacp, 0x3 /* 6clk */
-.equ B7_PMC, 0x0 /* normal(1data) */
-
-/* Bank 6 parameter */
-.equ B6_MT, 0x3 /* SDRAM */
-.equ B6_Trcd, 0x0 /* 2clk */
-.equ B6_SCAN, 0x0 /* 10bit */
-
-.equ B7_MT, 0x3 /* SDRAM */
-.equ B7_Trcd, 0x0 /* 2clk */
-.equ B7_SCAN, 0x0 /* 10bit */
-
-
-/* REFRESH parameter */
-.equ REFEN, 0x1 /* Refresh enable */
-.equ TREFMD, 0x0 /* CBR(CAS before RAS)/Auto refresh */
-.equ Trp, 0x0 /* 2clk */
-.equ Trc, 0x3 /* 0x1=5clk 0x3=11clk*/
-.equ Tchr, 0x0 /* 0x2=3clk 0x0=0clks */
-.equ REFCNT, 879
-
-MEMORY_CONFIG:
- .long 0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/
- .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/
- .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/
- .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/
- .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/
- .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/
- .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/
- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /*GCS6*/
- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /*GCS7*/
- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/
- .word 0x17 /*SCLK power down mode, BANKSIZE 16M/16M*/
- .word 0x20 /*MRSR6 CL=2clk*/
- .word 0x20 /*MRSR7*/
-
-
-.globl memsetup
-memsetup:
-
- /*
- the next instruction fail due memory relocation...
- we'll find the right MEMORY_CONFIG address with the next 3 lines...
- */
- /*ldr r0, =MEMORY_CONFIG*/
- mov r0, pc
- ldr r1, =(0x38+4)
- sub r0, r0, r1
-
- ldmia r0, {r1-r13}
- ldr r0, =0x01c80000
- stmia r0, {r1-r13}
- mov pc, lr
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
-SOBJS = memsetup.o
+SOBJS = lowlevel_init.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define AU1500_SYS_ADDR 0xB1900000
+#define sys_endian 0x0038
+#define CP0_Config0 $16
+#define CPU_SCALE ((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
+#define MEM_1MS ((CFG_MHZ) * 1000)
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl lowlevel_init
+lowlevel_init:
+ /*
+ * Step 1) Establish CPU endian mode.
+ * Db1500-specific:
+ * Switch S1.1 Off(bit7 reads 1) is Little Endian
+ * Switch S1.1 On (bit7 reads 0) is Big Endian
+ */
+#ifdef CONFIG_DBAU1550
+ li t0, MEM_STCFG2
+ li t1, 0x00000040
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME2
+ li t1, 0x22080a20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR2
+ li t1, 0x10c03f00
+ sw t1, 0(t0)
+#else
+ li t0, MEM_STCFG1
+ li t1, 0x00000080
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x22080a20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x10c03f00
+ sw t1, 0(t0)
+#endif
+
+ li t0, DB1XX0_BCSR_ADDR
+ lw t1,8(t0)
+ andi t1,t1,0x80
+ beq zero,t1,big_endian
+ nop
+little_endian:
+
+ /* Change Au1 core to little endian */
+ li t0, AU1500_SYS_ADDR
+ li t1, 1
+ sw t1, sys_endian(t0)
+ mfc0 t2, CP0_CONFIG
+ mtc0 t2, CP0_CONFIG
+ nop
+ nop
+
+ /* Big Endian is default so nothing to do but fall through */
+
+big_endian:
+
+ /*
+ * Step 2) Establish Status Register
+ * (set BEV, clear ERL, clear EXL, clear IE)
+ */
+ li t1, 0x00400000
+ mtc0 t1, CP0_STATUS
+
+ /*
+ * Step 3) Establish CP0 Config0
+ * (set OD, set K0=3)
+ */
+ li t1, 0x00080003
+ mtc0 t1, CP0_CONFIG
+
+ /*
+ * Step 4) Disable Watchpoint facilities
+ */
+ li t1, 0x00000000
+ mtc0 t1, CP0_WATCHLO
+ mtc0 t1, CP0_IWATCHLO
+ /*
+ * Step 5) Disable the performance counters
+ */
+ mtc0 zero, CP0_PERFORMANCE
+ nop
+
+ /*
+ * Step 6) Establish EJTAG Debug register
+ */
+ mtc0 zero, CP0_DEBUG
+ nop
+
+ /*
+ * Step 7) Establish Cause
+ * (set IV bit)
+ */
+ li t1, 0x00800000
+ mtc0 t1, CP0_CAUSE
+
+ /* Establish Wired (and Random) */
+ mtc0 zero, CP0_WIRED
+ nop
+
+#ifdef CONFIG_DBAU1550
+ /* No workaround if running from ram */
+ lui t0, 0xffc0
+ lui t3, 0xbfc0
+ and t1, ra, t0
+ bne t1, t3, noCacheJump
+ nop
+
+ /*** From AMD YAMON ***/
+ /*
+ * Step 8) Initialize the caches
+ */
+ li t0, (16*1024)
+ li t1, 32
+ li t2, 0x80000000
+ addu t3, t0, t2
+cacheloop:
+ cache 0, 0(t2)
+ cache 1, 0(t2)
+ addu t2, t1
+ bne t2, t3, cacheloop
+ nop
+
+ /* Save return address */
+ move t3, ra
+
+ /* Run from cacheable space now */
+ bal cachehere
+ nop
+cachehere:
+ li t1, ~0x20000000 /* convert to KSEG0 */
+ and t0, ra, t1
+ addi t0, 5*4 /* 5 insns beyond cachehere */
+ jr t0
+ nop
+
+ /* Restore return address */
+ move ra, t3
+
+ /*
+ * Step 9) Initialize the TLB
+ */
+ li t0, 0 # index value
+ li t1, 0x00000000 # entryhi value
+ li t2, 32 # 32 entries
+
+tlbloop:
+ /* Probe TLB for matching EntryHi */
+ mtc0 t1, CP0_ENTRYHI
+ tlbp
+ nop
+
+ /* Examine Index[P], 1=no matching entry */
+ mfc0 t3, CP0_INDEX
+ li t4, 0x80000000
+ and t3, t4, t3
+ addiu t1, t1, 1 # increment t1 (asid)
+ beq zero, t3, tlbloop
+ nop
+
+ /* Initialize the TLB entry */
+ mtc0 t0, CP0_INDEX
+ mtc0 zero, CP0_ENTRYLO0
+ mtc0 zero, CP0_ENTRYLO1
+ mtc0 zero, CP0_PAGEMASK
+ tlbwi
+
+ /* Do it again */
+ addiu t0, t0, 1
+ bne t0, t2, tlbloop
+ nop
+
+ /* First setup pll:s to make serial work ok */
+ /* We have a 12 MHz crystal */
+ li t0, SYS_CPUPLL
+ li t1, CPU_SCALE /* CPU clock */
+ sw t1, 0(t0)
+ sync
+ nop
+ nop
+
+ /* wait 1mS for clocks to settle */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+ /* Setup AUX PLL */
+ li t0, SYS_AUXPLL
+ li t1, 0x20 /* 96 MHz */
+ sw t1, 0(t0) /* aux pll */
+ sync
+
+ /* Static memory controller */
+ /* RCE0 - can not change while fetching, do so from icache */
+ move t2, ra /* Store return address */
+ bal getAddr
+ nop
+
+getAddr:
+ move t1, ra
+ move ra, t2 /* Move return addess back */
+
+ cache 0x14,0(t1)
+ cache 0x14,32(t1)
+ /*** /From YAMON ***/
+
+noCacheJump:
+#endif /* CONFIG_DBAU1550 */
+
+#ifdef CONFIG_DBAU1550
+ li t0, MEM_STTIME0
+ li t1, 0x040181D7
+ sw t1, 0(t0)
+
+ /* RCE0 AMD MirrorBit Flash (?) */
+ li t0, MEM_STCFG0
+ li t1, 0x00000003
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR0
+ li t1, 0x11803E00
+ sw t1, 0(t0)
+#else /* CONFIG_DBAU1550 */
+ li t0, MEM_STTIME0
+ li t1, 0x00014C0F
+ sw t1, 0(t0)
+
+ /* RCE0 AMD 29LV640M MirrorBit Flash */
+ li t0, MEM_STCFG0
+ li t1, 0x00000013
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR0
+ li t1, 0x11E03F80
+ sw t1, 0(t0)
+#endif /* CONFIG_DBAU1550 */
+
+ /* RCE1 CPLD Board Logic */
+ li t0, MEM_STCFG1
+ li t1, 0x00000080
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x22080a20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x10c03f00
+ sw t1, 0(t0)
+
+#ifdef CONFIG_DBAU1550
+ /* RCE2 CPLD Board Logic */
+ li t0, MEM_STCFG2
+ li t1, 0x00000040
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME2
+ li t1, 0x22080a20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR2
+ li t1, 0x10c03f00
+ sw t1, 0(t0)
+#else
+ li t0, MEM_STCFG2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+#endif
+
+ /* RCE3 PCMCIA 250ns */
+ li t0, MEM_STCFG3
+ li t1, 0x00000002
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME3
+ li t1, 0x280E3E07
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR3
+ li t1, 0x10000000
+ sw t1, 0(t0)
+
+ sync
+
+ /* Set peripherals to a known state */
+ li t0, IC0_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC0_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC0_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC0_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, IC1_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC1_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC1_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC1_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, SYS_FREQCTRL0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_FREQCTRL1
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_CLKSRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_PININPUTEN
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, 0xB1100100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, 0xB1400100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+
+ li t0, SYS_WAKEMSK
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_WAKESRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ /* wait 1mS before setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+#ifdef CONFIG_DBAU1550
+/* SDCS 0,1,2 DDR SDRAM */
+ li t0, MEM_SDMODE0
+ li t1, 0x04276221
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE1
+ li t1, 0x04276221
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE2
+ li t1, 0x04276221
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR0
+ li t1, 0xe21003f0
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR1
+ li t1, 0xe21043f0
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR2
+ li t1, 0xe21083f0
+ sw t1, 0(t0)
+
+ sync
+
+ li t0, MEM_SDCONFIGA
+ li t1, 0x9030060a /* Program refresh - disabled */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDCONFIGB
+ li t1, 0x00028000
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD /* Precharge all */
+ li t1, 0
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x40000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD1
+ li t1, 0x40000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD2
+ li t1, 0x40000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x00000063
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD1
+ li t1, 0x00000063
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD2
+ li t1, 0x00000063
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD /* Precharge all */
+ sw zero, 0(t0)
+ sync
+
+ /* Issue 2 autoref */
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+
+ /* Enable refresh */
+ li t0, MEM_SDCONFIGA
+ li t1, 0x9830060a /* Program refresh - enabled */
+ sw t1, 0(t0)
+ sync
+
+#else /* CONFIG_DBAU1550 */
+/* SDCS 0,1 SDRAM */
+ li t0, MEM_SDMODE0
+ li t1, 0x005522AA
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE1
+ li t1, 0x005522AA
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR0
+ li t1, 0x001003F8
+ sw t1, 0(t0)
+
+
+ li t0, MEM_SDADDR1
+ li t1, 0x001023F8
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x64000C24 /* Disable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x66000C24 /* Enable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x00000033
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD1
+ li t1, 0x00000033
+ sw t1, 0(t0)
+ sync
+
+#endif /* CONFIG_DBAU1550 */
+ /* wait 1mS after setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+ li t0, SYS_PINFUNC
+ li t1, 0x00008080
+ sw t1, 0(t0)
+
+ li t0, SYS_TRIOUTCLR
+ li t1, 0x00001FFF
+ sw t1, 0(t0)
+
+ li t0, SYS_OUTPUTCLR
+ li t1, 0x00008000
+ sw t1, 0(t0)
+ sync
+
+ j ra
+ nop
+++ /dev/null
-/* Memory sub-system initialization code */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-#include <asm/au1x00.h>
-#include <asm/mipsregs.h>
-
-#define AU1500_SYS_ADDR 0xB1900000
-#define sys_endian 0x0038
-#define CP0_Config0 $16
-#define CPU_SCALE ((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
-#define MEM_1MS ((CFG_MHZ) * 1000)
-
- .text
- .set noreorder
- .set mips32
-
- .globl memsetup
-memsetup:
- /*
- * Step 1) Establish CPU endian mode.
- * Db1500-specific:
- * Switch S1.1 Off(bit7 reads 1) is Little Endian
- * Switch S1.1 On (bit7 reads 0) is Big Endian
- */
-#ifdef CONFIG_DBAU1550
- li t0, MEM_STCFG2
- li t1, 0x00000040
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x22080a20
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x10c03f00
- sw t1, 0(t0)
-#else
- li t0, MEM_STCFG1
- li t1, 0x00000080
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x22080a20
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x10c03f00
- sw t1, 0(t0)
-#endif
-
- li t0, DB1XX0_BCSR_ADDR
- lw t1,8(t0)
- andi t1,t1,0x80
- beq zero,t1,big_endian
- nop
-little_endian:
-
- /* Change Au1 core to little endian */
- li t0, AU1500_SYS_ADDR
- li t1, 1
- sw t1, sys_endian(t0)
- mfc0 t2, CP0_CONFIG
- mtc0 t2, CP0_CONFIG
- nop
- nop
-
- /* Big Endian is default so nothing to do but fall through */
-
-big_endian:
-
- /*
- * Step 2) Establish Status Register
- * (set BEV, clear ERL, clear EXL, clear IE)
- */
- li t1, 0x00400000
- mtc0 t1, CP0_STATUS
-
- /*
- * Step 3) Establish CP0 Config0
- * (set OD, set K0=3)
- */
- li t1, 0x00080003
- mtc0 t1, CP0_CONFIG
-
- /*
- * Step 4) Disable Watchpoint facilities
- */
- li t1, 0x00000000
- mtc0 t1, CP0_WATCHLO
- mtc0 t1, CP0_IWATCHLO
- /*
- * Step 5) Disable the performance counters
- */
- mtc0 zero, CP0_PERFORMANCE
- nop
-
- /*
- * Step 6) Establish EJTAG Debug register
- */
- mtc0 zero, CP0_DEBUG
- nop
-
- /*
- * Step 7) Establish Cause
- * (set IV bit)
- */
- li t1, 0x00800000
- mtc0 t1, CP0_CAUSE
-
- /* Establish Wired (and Random) */
- mtc0 zero, CP0_WIRED
- nop
-
-#ifdef CONFIG_DBAU1550
- /* No workaround if running from ram */
- lui t0, 0xffc0
- lui t3, 0xbfc0
- and t1, ra, t0
- bne t1, t3, noCacheJump
- nop
-
- /*** From AMD YAMON ***/
- /*
- * Step 8) Initialize the caches
- */
- li t0, (16*1024)
- li t1, 32
- li t2, 0x80000000
- addu t3, t0, t2
-cacheloop:
- cache 0, 0(t2)
- cache 1, 0(t2)
- addu t2, t1
- bne t2, t3, cacheloop
- nop
-
- /* Save return address */
- move t3, ra
-
- /* Run from cacheable space now */
- bal cachehere
- nop
-cachehere:
- li t1, ~0x20000000 /* convert to KSEG0 */
- and t0, ra, t1
- addi t0, 5*4 /* 5 insns beyond cachehere */
- jr t0
- nop
-
- /* Restore return address */
- move ra, t3
-
- /*
- * Step 9) Initialize the TLB
- */
- li t0, 0 # index value
- li t1, 0x00000000 # entryhi value
- li t2, 32 # 32 entries
-
-tlbloop:
- /* Probe TLB for matching EntryHi */
- mtc0 t1, CP0_ENTRYHI
- tlbp
- nop
-
- /* Examine Index[P], 1=no matching entry */
- mfc0 t3, CP0_INDEX
- li t4, 0x80000000
- and t3, t4, t3
- addiu t1, t1, 1 # increment t1 (asid)
- beq zero, t3, tlbloop
- nop
-
- /* Initialize the TLB entry */
- mtc0 t0, CP0_INDEX
- mtc0 zero, CP0_ENTRYLO0
- mtc0 zero, CP0_ENTRYLO1
- mtc0 zero, CP0_PAGEMASK
- tlbwi
-
- /* Do it again */
- addiu t0, t0, 1
- bne t0, t2, tlbloop
- nop
-
- /* First setup pll:s to make serial work ok */
- /* We have a 12 MHz crystal */
- li t0, SYS_CPUPLL
- li t1, CPU_SCALE /* CPU clock */
- sw t1, 0(t0)
- sync
- nop
- nop
-
- /* wait 1mS for clocks to settle */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
- /* Setup AUX PLL */
- li t0, SYS_AUXPLL
- li t1, 0x20 /* 96 MHz */
- sw t1, 0(t0) /* aux pll */
- sync
-
- /* Static memory controller */
- /* RCE0 - can not change while fetching, do so from icache */
- move t2, ra /* Store return address */
- bal getAddr
- nop
-
-getAddr:
- move t1, ra
- move ra, t2 /* Move return addess back */
-
- cache 0x14,0(t1)
- cache 0x14,32(t1)
- /*** /From YAMON ***/
-
-noCacheJump:
-#endif /* CONFIG_DBAU1550 */
-
-#ifdef CONFIG_DBAU1550
- li t0, MEM_STTIME0
- li t1, 0x040181D7
- sw t1, 0(t0)
-
- /* RCE0 AMD MirrorBit Flash (?) */
- li t0, MEM_STCFG0
- li t1, 0x00000003
- sw t1, 0(t0)
-
- li t0, MEM_STADDR0
- li t1, 0x11803E00
- sw t1, 0(t0)
-#else /* CONFIG_DBAU1550 */
- li t0, MEM_STTIME0
- li t1, 0x00014C0F
- sw t1, 0(t0)
-
- /* RCE0 AMD 29LV640M MirrorBit Flash */
- li t0, MEM_STCFG0
- li t1, 0x00000013
- sw t1, 0(t0)
-
- li t0, MEM_STADDR0
- li t1, 0x11E03F80
- sw t1, 0(t0)
-#endif /* CONFIG_DBAU1550 */
-
- /* RCE1 CPLD Board Logic */
- li t0, MEM_STCFG1
- li t1, 0x00000080
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x22080a20
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x10c03f00
- sw t1, 0(t0)
-
-#ifdef CONFIG_DBAU1550
- /* RCE2 CPLD Board Logic */
- li t0, MEM_STCFG2
- li t1, 0x00000040
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x22080a20
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x10c03f00
- sw t1, 0(t0)
-#else
- li t0, MEM_STCFG2
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x00000000
- sw t1, 0(t0)
-#endif
-
- /* RCE3 PCMCIA 250ns */
- li t0, MEM_STCFG3
- li t1, 0x00000002
- sw t1, 0(t0)
-
- li t0, MEM_STTIME3
- li t1, 0x280E3E07
- sw t1, 0(t0)
-
- li t0, MEM_STADDR3
- li t1, 0x10000000
- sw t1, 0(t0)
-
- sync
-
- /* Set peripherals to a known state */
- li t0, IC0_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC0_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC0_SRCSET
- sw t1, 0(t0)
-
- li t0, IC0_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC0_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC0_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, IC1_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC1_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC1_SRCSET
- sw t1, 0(t0)
-
- li t0, IC1_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC1_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC1_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, SYS_FREQCTRL0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_FREQCTRL1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_CLKSRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_PININPUTEN
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, 0xB1100100
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, 0xB1400100
- li t1, 0x00000000
- sw t1, 0(t0)
-
-
- li t0, SYS_WAKEMSK
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_WAKESRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- /* wait 1mS before setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
-#ifdef CONFIG_DBAU1550
-/* SDCS 0,1,2 DDR SDRAM */
- li t0, MEM_SDMODE0
- li t1, 0x04276221
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE1
- li t1, 0x04276221
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE2
- li t1, 0x04276221
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR0
- li t1, 0xe21003f0
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR1
- li t1, 0xe21043f0
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR2
- li t1, 0xe21083f0
- sw t1, 0(t0)
-
- sync
-
- li t0, MEM_SDCONFIGA
- li t1, 0x9030060a /* Program refresh - disabled */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDCONFIGB
- li t1, 0x00028000
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD /* Precharge all */
- li t1, 0
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x40000000
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD1
- li t1, 0x40000000
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD2
- li t1, 0x40000000
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x00000063
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD1
- li t1, 0x00000063
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD2
- li t1, 0x00000063
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD /* Precharge all */
- sw zero, 0(t0)
- sync
-
- /* Issue 2 autoref */
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
-
- /* Enable refresh */
- li t0, MEM_SDCONFIGA
- li t1, 0x9830060a /* Program refresh - enabled */
- sw t1, 0(t0)
- sync
-
-#else /* CONFIG_DBAU1550 */
-/* SDCS 0,1 SDRAM */
- li t0, MEM_SDMODE0
- li t1, 0x005522AA
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE1
- li t1, 0x005522AA
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE2
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR0
- li t1, 0x001003F8
- sw t1, 0(t0)
-
-
- li t0, MEM_SDADDR1
- li t1, 0x001023F8
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR2
- li t1, 0x00000000
- sw t1, 0(t0)
-
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x64000C24 /* Disable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x66000C24 /* Enable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x00000033
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD1
- li t1, 0x00000033
- sw t1, 0(t0)
- sync
-
-#endif /* CONFIG_DBAU1550 */
- /* wait 1mS after setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
- li t0, SYS_PINFUNC
- li t1, 0x00008080
- sw t1, 0(t0)
-
- li t0, SYS_TRIOUTCLR
- li t1, 0x00001FFF
- sw t1, 0(t0)
-
- li t0, SYS_OUTPUTCLR
- li t1, 0x00008000
- sw t1, 0(t0)
- sync
-
- j ra
- nop
LIB = lib$(BOARD).a
OBJS := dnp1110.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/* some parameters for the board */
+
+MEM_BASE: .long 0xa0000000
+MEM_START: .long 0xc0000000
+
+#define MDCNFG 0x00
+#define MDCAS00 0x04 /* CAS waveform rotate reg 0 */
+#define MDCAS01 0x08 /* CAS waveform rotate reg 1 bank */
+#define MDCAS02 0x0C /* CAS waveform rotate reg 2 bank */
+#define MDREFR 0x1C /* DRAM refresh control reg */
+#define MDCAS20 0x20 /* CAS waveform rotate reg 0 bank */
+#define MDCAS21 0x24 /* CAS waveform rotate reg 1 bank */
+#define MDCAS22 0x28 /* CAS waveform rotate reg 2 bank */
+#define MECR 0x18 /* Expansion memory (PCMCIA) bus configuration register */
+#define MSC0 0x10 /* static memory control reg 0 */
+#define MSC1 0x14 /* static memory control reg 1 */
+#define MSC2 0x2C /* static memory control reg 2 */
+#define SMCNFG 0x30 /* SMROM configuration reg */
+
+mdcas00: .long 0x5555557F
+mdcas01: .long 0x55555555
+mdcas02: .long 0x55555555
+mdcas20: .long 0x5555557F
+mdcas21: .long 0x55555555
+mdcas22: .long 0x55555555
+mdcnfg: .long 0x0000B25C
+mdrefr: .long 0x007000C1
+mecr: .long 0x10841084
+msc0: .long 0x00004774
+msc1: .long 0x00000000
+msc2: .long 0x00000000
+smcnfg: .long 0x00000000
+
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ ldr r0, MEM_BASE
+
+ /* Set up the DRAM */
+
+ /* MDCAS00 */
+ ldr r1, mdcas00
+ str r1, [r0, #MDCAS00]
+
+ /* MDCAS01 */
+ ldr r1, mdcas01
+ str r1, [r0, #MDCAS01]
+
+ /* MDCAS02 */
+ ldr r1, mdcas02
+ str r1, [r0, #MDCAS02]
+
+ /* MDCAS20 */
+ ldr r1, mdcas20
+ str r1, [r0, #MDCAS20]
+
+ /* MDCAS21 */
+ ldr r1, mdcas21
+ str r1, [r0, #MDCAS21]
+
+ /* MDCAS22 */
+ ldr r1, mdcas22
+ str r1, [r0, #MDCAS22]
+
+ /* MDREFR */
+ ldr r1, mdrefr
+ str r1, [r0, #MDREFR]
+
+ /* Set up PCMCIA space */
+ ldr r1, mecr
+ str r1, [r0, #MECR]
+
+ /* Setup the flash memory and other */
+ ldr r1, msc0
+ str r1, [r0, #MSC0]
+
+ ldr r1, msc1
+ str r1, [r0, #MSC1]
+
+ ldr r1, msc2
+ str r1, [r0, #MSC2]
+
+ ldr r1, smcnfg
+ str r1, [r0, #SMCNFG]
+
+ /* MDCNFG */
+ ldr r1, mdcnfg
+ bic r1, r1, #0x00000001
+ str r1, [r0, #MDCNFG]
+
+ /* Load something to activate bank */
+ ldr r2, MEM_START
+.rept 8
+ ldr r1, [r2]
+.endr
+
+ /* MDCNFG */
+ ldr r1, mdcnfg
+ orr r1, r1, #0x00000001
+ str r1, [r0, #MDCNFG]
+
+ /* everything is fine now */
+ mov pc, lr
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include "config.h"
-#include "version.h"
-
-
-/* some parameters for the board */
-
-MEM_BASE: .long 0xa0000000
-MEM_START: .long 0xc0000000
-
-#define MDCNFG 0x00
-#define MDCAS00 0x04 /* CAS waveform rotate reg 0 */
-#define MDCAS01 0x08 /* CAS waveform rotate reg 1 bank */
-#define MDCAS02 0x0C /* CAS waveform rotate reg 2 bank */
-#define MDREFR 0x1C /* DRAM refresh control reg */
-#define MDCAS20 0x20 /* CAS waveform rotate reg 0 bank */
-#define MDCAS21 0x24 /* CAS waveform rotate reg 1 bank */
-#define MDCAS22 0x28 /* CAS waveform rotate reg 2 bank */
-#define MECR 0x18 /* Expansion memory (PCMCIA) bus configuration register */
-#define MSC0 0x10 /* static memory control reg 0 */
-#define MSC1 0x14 /* static memory control reg 1 */
-#define MSC2 0x2C /* static memory control reg 2 */
-#define SMCNFG 0x30 /* SMROM configuration reg */
-
-mdcas00: .long 0x5555557F
-mdcas01: .long 0x55555555
-mdcas02: .long 0x55555555
-mdcas20: .long 0x5555557F
-mdcas21: .long 0x55555555
-mdcas22: .long 0x55555555
-mdcnfg: .long 0x0000B25C
-mdrefr: .long 0x007000C1
-mecr: .long 0x10841084
-msc0: .long 0x00004774
-msc1: .long 0x00000000
-msc2: .long 0x00000000
-smcnfg: .long 0x00000000
-
-/* setting up the memory */
-
-.globl memsetup
-memsetup:
-
- ldr r0, MEM_BASE
-
- /* Set up the DRAM */
-
- /* MDCAS00 */
- ldr r1, mdcas00
- str r1, [r0, #MDCAS00]
-
- /* MDCAS01 */
- ldr r1, mdcas01
- str r1, [r0, #MDCAS01]
-
- /* MDCAS02 */
- ldr r1, mdcas02
- str r1, [r0, #MDCAS02]
-
- /* MDCAS20 */
- ldr r1, mdcas20
- str r1, [r0, #MDCAS20]
-
- /* MDCAS21 */
- ldr r1, mdcas21
- str r1, [r0, #MDCAS21]
-
- /* MDCAS22 */
- ldr r1, mdcas22
- str r1, [r0, #MDCAS22]
-
- /* MDREFR */
- ldr r1, mdrefr
- str r1, [r0, #MDREFR]
-
- /* Set up PCMCIA space */
- ldr r1, mecr
- str r1, [r0, #MECR]
-
- /* Setup the flash memory and other */
- ldr r1, msc0
- str r1, [r0, #MSC0]
-
- ldr r1, msc1
- str r1, [r0, #MSC1]
-
- ldr r1, msc2
- str r1, [r0, #MSC2]
-
- ldr r1, smcnfg
- str r1, [r0, #SMCNFG]
-
- /* MDCNFG */
- ldr r1, mdcnfg
- bic r1, r1, #0x00000001
- str r1, [r0, #MDCNFG]
-
- /* Load something to activate bank */
- ldr r2, MEM_START
-.rept 8
- ldr r1, [r2]
-.endr
-
- /* MDCNFG */
- ldr r1, mdcnfg
- orr r1, r1, #0x00000001
- str r1, [r0, #MDCNFG]
-
- /* everything is fine now */
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := ep7312.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory Setup stuff - taken from ???
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+SYSCON1: .long 0x80000100
+SYSCON2: .long 0x80001100
+SYSCON3: .long 0x80002200
+MEMCFG1: .long 0x80000180
+MEMCFG2: .long 0x800001C0
+SDCONF: .long 0x80002300
+SDRFPR: .long 0x80002340
+
+syscon1_val: .long 0x00040100
+syscon2_val: .long 0x00000102
+syscon3_val: .long 0x0000020E
+memcfg1_val: .long 0x1f101710
+memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits
+memcfg2_val: .long 0x00001f13 @ upper 16 bits are reserved for CS7 + CS6
+sdrfpr_val: .long 0x00000240
+sdconf_val: .long 0x00000522
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+ /*
+ * SYSCON1-3
+ */
+ ldr r0, SYSCON1
+ ldr r1, syscon1_val
+ str r1, [r0]
+
+ ldr r0, SYSCON2
+ ldr r1, syscon2_val
+ str r1, [r0]
+
+ ldr r0, SYSCON3
+ ldr r1, syscon3_val
+ str r1, [r0]
+
+ /*
+ * MEMCFG1
+ */
+ ldr r0, MEMCFG1
+ ldr r1, memcfg1_val
+ str r1, [r0]
+
+ /*
+ * MEMCFG2
+ */
+ ldr r0, MEMCFG2
+ ldr r2, [r0]
+ ldr r1, memcfg2_mask
+ bic r2, r2, r1
+ ldr r1, memcfg2_val
+ orr r2, r2, r1
+ str r2, [r0]
+
+ /*
+ * SDRFPR,SDCONF
+ */
+ ldr r0, SDCONF
+ ldr r1, sdconf_val
+ str r1, [r0]
+
+ ldr r0, SDRFPR
+ ldr r1, sdrfpr_val
+ str r1, [r0]
+
+ /* everything is fine now */
+ mov pc, lr
+++ /dev/null
-/*
- * Memory Setup stuff - taken from ???
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-
-/* some parameters for the board */
-
-SYSCON1: .long 0x80000100
-SYSCON2: .long 0x80001100
-SYSCON3: .long 0x80002200
-MEMCFG1: .long 0x80000180
-MEMCFG2: .long 0x800001C0
-SDCONF: .long 0x80002300
-SDRFPR: .long 0x80002340
-
-syscon1_val: .long 0x00040100
-syscon2_val: .long 0x00000102
-syscon3_val: .long 0x0000020E
-memcfg1_val: .long 0x1f101710
-memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits
-memcfg2_val: .long 0x00001f13 @ upper 16 bits are reserved for CS7 + CS6
-sdrfpr_val: .long 0x00000240
-sdconf_val: .long 0x00000522
-/* setting up the memory */
-
-.globl memsetup
-memsetup:
- /*
- * SYSCON1-3
- */
- ldr r0, SYSCON1
- ldr r1, syscon1_val
- str r1, [r0]
-
- ldr r0, SYSCON2
- ldr r1, syscon2_val
- str r1, [r0]
-
- ldr r0, SYSCON3
- ldr r1, syscon3_val
- str r1, [r0]
-
- /*
- * MEMCFG1
- */
- ldr r0, MEMCFG1
- ldr r1, memcfg1_val
- str r1, [r0]
-
- /*
- * MEMCFG2
- */
- ldr r0, MEMCFG2
- ldr r2, [r0]
- ldr r1, memcfg2_mask
- bic r2, r2, r1
- ldr r1, memcfg2_val
- orr r2, r2, r1
- str r2, [r0]
-
- /*
- * SDRFPR,SDCONF
- */
- ldr r0, SDCONF
- ldr r1, sdconf_val
- str r1, [r0]
-
- ldr r0, SDRFPR
- ldr r1, sdrfpr_val
- str r1, [r0]
-
- /* everything is fine now */
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := evb4510.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
--- /dev/null
+/*
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/hardware.h>
+
+/***********************************************************************
+ * Configure Memory Map
+ *
+ * This memory map allows us to relocate from FLASH to SRAM. After
+ * power-on reset the CPU only knows about the FLASH memory at address
+ * 0x00000000. After lowlevel_init completes the memory map will be:
+ *
+ * Memory Addr
+ * 0x00000000
+ * to 8MB SRAM (U5) -- 8MB Map
+ * 0x00800000
+ *
+ * 0x01000000
+ * to 2MB Flash @ 0x00000000 (U7) -- 2MB Map
+ * 0x01200000
+ *
+ * 0x02000000
+ * to 512KB Flash @ 0x02000000 (U9) -- 2MB Map
+ * 0x02080000
+ *
+ * Load all 12 memory registers with the STMIA instruction since
+ * memory access is disabled once these registers are written. The
+ * last register written re-enables memory access. For more info see
+ * the user's manual for the S3C4510B, available from Samsung's web
+ * site. Search for part number "S3C4510B".
+ *
+ ***********************************************************************/
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* preserve the temp register (r12 AKA ip) and remap it. */
+ ldr r1, =SRAM_BASE+0xC
+ add r0, r12, #0x01000000
+ str r0, [r1]
+
+ /* remap the link register for when we return */
+ add lr, lr, #0x01000000
+
+ /* store a short program in the on chip SRAM, which is
+ * unaffected when remapping memory. Note the cache must be
+ * disabled for the on chip SRAM to be available.
+ */
+ ldr r1, =SRAM_BASE
+ ldr r0, =0xe8801ffe /* stmia r0, {r1-r12} */
+ str r0, [r1]
+ add r1, r1, #4
+ ldr r0, =0xe59fc000 /* ldr r12, [pc, #0] */
+ str r0, [r1]
+ add r1, r1, #4
+ ldr r0, =0xe1a0f00e /* mov pc, lr */
+ str r0, [r1]
+
+ adr r0, memory_map_data
+ ldmia r0, {r1-r12}
+ ldr r0, =REG_EXTDBWTH
+
+ ldr pc, =SRAM_BASE
+
+.globl reset_cpu
+reset_cpu:
+ /*
+ * reset the cpu by re-mapping FLASH 0 to 0x0 and jumping to
+ * address 0x0. We accomplish this by storing a few
+ * instructions into the on chip SRAM (8KB) and run from
+ * there. Note the cache must be disabled for the on chip
+ * SRAM to be available.
+ *
+ * load r2 with REG_ROMCON0
+ * load r3 with 0x12040060 configure FLASH bank 0 @ 0x00000000
+ * load r4 with REG_DRAMCON0
+ * load r5 with 0x08000380 configure RAM bank 0 @ 0x01000000
+ * load r6 with REG_REFEXTCON
+ * load r7 with 0x9c218360
+ * load r8 with 0x0
+ * store str r3,[r2] @ SRAM_BASE
+ * store str r5,[r4] @ SRAM_BASE + 0x4
+ * store str r7,[r6] @ SRAM_BASE + 0x8
+ * store mov pc,r8 @ SRAM_BASE + 0xC
+ * mov pc, SRAM_BASE
+ *
+ */
+
+ /* disable cache */
+ ldr r0, =REG_SYSCFG
+ ldr r1, =0x83ffffa0 /* cache-disabled */
+ str r1, [r0]
+
+ ldr r2, =REG_ROMCON0
+ ldr r3, =0x02000060 /* Bank0 2MB FLASH @ 0x00000000 */
+ ldr r4, =REG_DRAMCON0
+ ldr r5, =0x18040380 /* DRAM0 8MB SRAM @ 0x01000000 */
+ ldr r6, =REG_REFEXTCON
+ ldr r7, =0xce278360
+ ldr r8, =0x00000000
+ ldr r1, =SRAM_BASE
+ ldr r0, =0xe5823000 /* str r3, [r2] */
+ str r0, [r1]
+ ldr r1, =SRAM_BASE+4
+ ldr r0, =0xe5845000 /* str r5, [r4] */
+ str r0, [r1]
+ ldr r1, =SRAM_BASE+8
+ ldr r0, =0xe5867000 /* str r7, [r6] */
+ str r0, [r1]
+ ldr r1, =SRAM_BASE+0xC
+ ldr r0, =0xe1a0f008 /* mov pc, r8 */
+ str r0, [r1]
+ ldr r1, =SRAM_BASE
+ mov pc, r1
+
+ /* never return */
+
+/************************************************************************
+ * Below are twelve 32-bit values for the twelve memory registers of
+ * the system manager, starting with register REG_EXTDBWTH.
+ ***********************************************************************/
+memory_map_data:
+ .long 0x00f03005 /* memory widths */
+ .long 0x12040060 /* Bank0 2MB FLASH @ 0x01000000 */
+ .long 0x22080060 /* Bank1 512KB FLASH @ 0x02000000 */
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x08000380 /* DRAM0 8MB SRAM @ 0x00000000 */
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x9c218360 /* enable memory */
+++ /dev/null
-/*
- * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-#include <asm/hardware.h>
-
-/***********************************************************************
- * Configure Memory Map
- *
- * This memory map allows us to relocate from FLASH to SRAM. After
- * power-on reset the CPU only knows about the FLASH memory at address
- * 0x00000000. After memsetup completes the memory map will be:
- *
- * Memory Addr
- * 0x00000000
- * to 8MB SRAM (U5) -- 8MB Map
- * 0x00800000
- *
- * 0x01000000
- * to 2MB Flash @ 0x00000000 (U7) -- 2MB Map
- * 0x01200000
- *
- * 0x02000000
- * to 512KB Flash @ 0x02000000 (U9) -- 2MB Map
- * 0x02080000
- *
- * Load all 12 memory registers with the STMIA instruction since
- * memory access is disabled once these registers are written. The
- * last register written re-enables memory access. For more info see
- * the user's manual for the S3C4510B, available from Samsung's web
- * site. Search for part number "S3C4510B".
- *
- ***********************************************************************/
-
-.globl memsetup
-memsetup:
-
- /* preserve the temp register (r12 AKA ip) and remap it. */
- ldr r1, =SRAM_BASE+0xC
- add r0, r12, #0x01000000
- str r0, [r1]
-
- /* remap the link register for when we return */
- add lr, lr, #0x01000000
-
- /* store a short program in the on chip SRAM, which is
- * unaffected when remapping memory. Note the cache must be
- * disabled for the on chip SRAM to be available.
- */
- ldr r1, =SRAM_BASE
- ldr r0, =0xe8801ffe /* stmia r0, {r1-r12} */
- str r0, [r1]
- add r1, r1, #4
- ldr r0, =0xe59fc000 /* ldr r12, [pc, #0] */
- str r0, [r1]
- add r1, r1, #4
- ldr r0, =0xe1a0f00e /* mov pc, lr */
- str r0, [r1]
-
- adr r0, memory_map_data
- ldmia r0, {r1-r12}
- ldr r0, =REG_EXTDBWTH
-
- ldr pc, =SRAM_BASE
-
-.globl reset_cpu
-reset_cpu:
- /*
- * reset the cpu by re-mapping FLASH 0 to 0x0 and jumping to
- * address 0x0. We accomplish this by storing a few
- * instructions into the on chip SRAM (8KB) and run from
- * there. Note the cache must be disabled for the on chip
- * SRAM to be available.
- *
- * load r2 with REG_ROMCON0
- * load r3 with 0x12040060 configure FLASH bank 0 @ 0x00000000
- * load r4 with REG_DRAMCON0
- * load r5 with 0x08000380 configure RAM bank 0 @ 0x01000000
- * load r6 with REG_REFEXTCON
- * load r7 with 0x9c218360
- * load r8 with 0x0
- * store str r3,[r2] @ SRAM_BASE
- * store str r5,[r4] @ SRAM_BASE + 0x4
- * store str r7,[r6] @ SRAM_BASE + 0x8
- * store mov pc,r8 @ SRAM_BASE + 0xC
- * mov pc, SRAM_BASE
- *
- */
-
- /* disable cache */
- ldr r0, =REG_SYSCFG
- ldr r1, =0x83ffffa0 /* cache-disabled */
- str r1, [r0]
-
- ldr r2, =REG_ROMCON0
- ldr r3, =0x02000060 /* Bank0 2MB FLASH @ 0x00000000 */
- ldr r4, =REG_DRAMCON0
- ldr r5, =0x18040380 /* DRAM0 8MB SRAM @ 0x01000000 */
- ldr r6, =REG_REFEXTCON
- ldr r7, =0xce278360
- ldr r8, =0x00000000
- ldr r1, =SRAM_BASE
- ldr r0, =0xe5823000 /* str r3, [r2] */
- str r0, [r1]
- ldr r1, =SRAM_BASE+4
- ldr r0, =0xe5845000 /* str r5, [r4] */
- str r0, [r1]
- ldr r1, =SRAM_BASE+8
- ldr r0, =0xe5867000 /* str r7, [r6] */
- str r0, [r1]
- ldr r1, =SRAM_BASE+0xC
- ldr r0, =0xe1a0f008 /* mov pc, r8 */
- str r0, [r1]
- ldr r1, =SRAM_BASE
- mov pc, r1
-
- /* never return */
-
-/************************************************************************
- * Below are twelve 32-bit values for the twelve memory registers of
- * the system manager, starting with register REG_EXTDBWTH.
- ***********************************************************************/
-memory_map_data:
- .long 0x00f03005 /* memory widths */
- .long 0x12040060 /* Bank0 2MB FLASH @ 0x01000000 */
- .long 0x22080060 /* Bank1 512KB FLASH @ 0x02000000 */
- .long 0x00000000
- .long 0x00000000
- .long 0x00000000
- .long 0x00000000
- .long 0x08000380 /* DRAM0 8MB SRAM @ 0x00000000 */
- .long 0x00000000
- .long 0x00000000
- .long 0x00000000
- .long 0x9c218360 /* enable memory */
LIB = lib$(BOARD).a
OBJS := gcplus.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2003-2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+ .globl lowlevel_init
+lowlevel_init:
+ /* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us.
+ * However the darn thing leaves the MMU enabled before handing control
+ * over to us. So we need to disable the MMU and we use lowlevel_init
+ * to do it.
+ */
+
+@ The following code segment was borrowed with gratitude from:
+@ linux-2.4.19-rmk7/arch/arm/boot/compressed/head-sa1100.S
+
+ @ Data cache might be active.
+ @ Be sure to flush kernel binary out of the cache,
+ @ whatever state it is, before it is turned off.
+ @ This is done by fetching through currently executed
+ @ memory to be sure we hit the same cache.
+ bic r2, pc, #0x1f
+ add r3, r2, #0x4000 @ 16 kb is quite enough...
+1: ldr r0, [r2], #32
+ teq r2, r3
+ bne 1b
+ mcr p15, 0, r0, c7, c10, 4 @ drain WB
+ mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
+
+ @ disabling MMU and caches
+ mrc p15, 0, r0, c1, c0, 0 @ read control reg
+ bic r0, r0, #0x0d @ clear WB, DC, MMU
+ bic r0, r0, #0x1000 @ clear Icache
+ mcr p15, 0, r0, c1, c0, 0
+
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ b 2f
+2:
+ nop
+ nop
+ nop
+ nop
+ nop
+
+
+ mov pc, lr
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- * 2003-2004 (c) MontaVista Software, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include "config.h"
-#include "version.h"
-
-
- .globl memsetup
-memsetup:
- /* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us.
- * However the darn thing leaves the MMU enabled before handing control
- * over to us. So we need to disable the MMU and we use memsetup
- * to do it.
- */
-
-@ The following code segment was borrowed with gratitude from:
-@ linux-2.4.19-rmk7/arch/arm/boot/compressed/head-sa1100.S
-
- @ Data cache might be active.
- @ Be sure to flush kernel binary out of the cache,
- @ whatever state it is, before it is turned off.
- @ This is done by fetching through currently executed
- @ memory to be sure we hit the same cache.
- bic r2, pc, #0x1f
- add r3, r2, #0x4000 @ 16 kb is quite enough...
-1: ldr r0, [r2], #32
- teq r2, r3
- bne 1b
- mcr p15, 0, r0, c7, c10, 4 @ drain WB
- mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
-
- @ disabling MMU and caches
- mrc p15, 0, r0, c1, c0, 0 @ read control reg
- bic r0, r0, #0x0d @ clear WB, DC, MMU
- bic r0, r0, #0x1000 @ clear Icache
- mcr p15, 0, r0, c1, c0, 0
-
- nop
- nop
- nop
- nop
- nop
-
- b 2f
-2:
- nop
- nop
- nop
- nop
- nop
-
-
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := impa7.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory Setup stuff - taken from ???
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+SYSCON2: .long 0x80001100
+MEMCFG1: .long 0x80000180
+MEMCFG2: .long 0x800001C0
+DRFPR: .long 0x80000200
+
+syscon2_mask: .long 0x00000004
+memcfg1_val: .long 0x160c1414
+memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits
+memcfg2_val: .long 0x00000000 @ upper 16 bits are reserved for CS7 + CS6
+drfpr_val: .long 0x00000081
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+ /*
+ * DRFPR
+ * 64kHz DRAM refresh
+ */
+ ldr r0, DRFPR
+ ldr r1, drfpr_val
+ str r1, [r0]
+
+ /*
+ * SYSCON2: clear bit 2, DRAM is 32 bits wide
+ */
+ ldr r0, SYSCON2
+ ldr r2, [r0]
+ ldr r1, syscon2_mask
+ bic r2, r2, r1
+ str r2, [r0]
+
+ /*
+ * MEMCFG1
+ * Setting up Keyboard at CS3, 8 Bit, 3 Waitstates
+ * Setting up CS8900 (Ethernet) at CS2, 32 Bit, 5 Waitstates
+ * Setting up flash at CS0 and CS1, 32 Bit, 3 Waitstates
+ */
+ ldr r0, MEMCFG1
+ ldr r1, memcfg1_val
+ str r1, [r0]
+
+ /*
+ * MEMCFG2
+ * Setting up ? with 0
+ *
+ */
+ ldr r0, MEMCFG2
+ ldr r2, [r0]
+ ldr r1, memcfg2_mask
+ bic r2, r2, r1
+ ldr r1, memcfg2_val
+ orr r2, r2, r1
+ str r2, [r0]
+
+ /* everything is fine now */
+ mov pc, lr
+++ /dev/null
-/*
- * Memory Setup stuff - taken from ???
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-
-/* some parameters for the board */
-
-SYSCON2: .long 0x80001100
-MEMCFG1: .long 0x80000180
-MEMCFG2: .long 0x800001C0
-DRFPR: .long 0x80000200
-
-syscon2_mask: .long 0x00000004
-memcfg1_val: .long 0x160c1414
-memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits
-memcfg2_val: .long 0x00000000 @ upper 16 bits are reserved for CS7 + CS6
-drfpr_val: .long 0x00000081
-/* setting up the memory */
-
-.globl memsetup
-memsetup:
- /*
- * DRFPR
- * 64kHz DRAM refresh
- */
- ldr r0, DRFPR
- ldr r1, drfpr_val
- str r1, [r0]
-
- /*
- * SYSCON2: clear bit 2, DRAM is 32 bits wide
- */
- ldr r0, SYSCON2
- ldr r2, [r0]
- ldr r1, syscon2_mask
- bic r2, r2, r1
- str r2, [r0]
-
- /*
- * MEMCFG1
- * Setting up Keyboard at CS3, 8 Bit, 3 Waitstates
- * Setting up CS8900 (Ethernet) at CS2, 32 Bit, 5 Waitstates
- * Setting up flash at CS0 and CS1, 32 Bit, 3 Waitstates
- */
- ldr r0, MEMCFG1
- ldr r1, memcfg1_val
- str r1, [r0]
-
- /*
- * MEMCFG2
- * Setting up ? with 0
- *
- */
- ldr r0, MEMCFG2
- ldr r2, [r0]
- ldr r1, memcfg2_mask
- bic r2, r2, r1
- ldr r1, memcfg2_val
- orr r2, r2, r1
- str r2, [r0]
-
- /* everything is fine now */
- mov pc, lr
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
-SOBJS = memsetup.o
+SOBJS = lowlevel_init.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory sub-system initialization code for INCA-IP development board.
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+
+#define EBU_MODUL_BASE 0xB8000200
+#define EBU_CLC(value) 0x0000(value)
+#define EBU_CON(value) 0x0010(value)
+#define EBU_ADDSEL0(value) 0x0020(value)
+#define EBU_ADDSEL1(value) 0x0024(value)
+#define EBU_ADDSEL2(value) 0x0028(value)
+#define EBU_BUSCON0(value) 0x0060(value)
+#define EBU_BUSCON1(value) 0x0064(value)
+#define EBU_BUSCON2(value) 0x0068(value)
+
+#define MC_MODUL_BASE 0xBF800000
+#define MC_ERRCAUSE(value) 0x0100(value)
+#define MC_ERRADDR(value) 0x0108(value)
+#define MC_IOGP(value) 0x0800(value)
+#define MC_SELFRFSH(value) 0x0A00(value)
+#define MC_CTRLENA(value) 0x1000(value)
+#define MC_MRSCODE(value) 0x1008(value)
+#define MC_CFGDW(value) 0x1010(value)
+#define MC_CFGPB0(value) 0x1018(value)
+#define MC_LATENCY(value) 0x1038(value)
+#define MC_TREFRESH(value) 0x1040(value)
+
+#define CGU_MODUL_BASE 0xBF107000
+#define CGU_PLL1CR(value) 0x0008(value)
+#define CGU_DIVCR(value) 0x0010(value)
+#define CGU_MUXCR(value) 0x0014(value)
+#define CGU_PLL1SR(value) 0x000C(value)
+
+ .set noreorder
+
+
+/*
+ * void ebu_init(long)
+ *
+ * a0 has the clock value we are going to run at
+ */
+ .globl ebu_init
+ .ent ebu_init
+ebu_init:
+
+ li t1, EBU_MODUL_BASE
+ li t2, 0xA0000041
+ sw t2, EBU_ADDSEL0(t1)
+ li t2, 0xA0800041
+ sw t2, EBU_ADDSEL2(t1)
+ li t2, 0xBE0000F1
+ sw t2, EBU_ADDSEL1(t1)
+
+ li t3, 100000000
+ beq a0, t3, 1f
+ nop
+ li t3, 133000000
+ beq a0, t3, 2f
+ nop
+ li t3, 150000000
+ beq a0, t3, 2f
+ nop
+ b 3f
+ nop
+
+ /* 100 MHz */
+1:
+ li t2, 0x8841417D
+ sw t2, EBU_BUSCON0(t1)
+ sw t2, EBU_BUSCON2(t1)
+ li t2, 0x684142BD
+ b 3f
+ sw t2, EBU_BUSCON1(t1) /* delay slot */
+
+ /* 133 or 150 MHz */
+2:
+ li t2, 0x8841417E
+ sw t2, EBU_BUSCON0(t1)
+ sw t2, EBU_BUSCON2(t1)
+ li t2, 0x684143FD
+ sw t2, EBU_BUSCON1(t1)
+3:
+ j ra
+ nop
+
+ .end ebu_init
+
+
+/*
+ * void cgu_init(long)
+ *
+ * a0 has the clock value
+ */
+ .globl cgu_init
+ .ent cgu_init
+cgu_init:
+
+ li t1, CGU_MODUL_BASE
+
+ li t3, 100000000
+ beq a0, t3, 1f
+ nop
+ li t3, 133000000
+ beq a0, t3, 2f
+ nop
+ li t3, 150000000
+ beq a0, t3, 3f
+ nop
+ b 5f
+ nop
+
+ /* 100 MHz clock */
+1:
+ li t2, 0x80000014
+ sw t2, CGU_DIVCR(t1)
+ li t2, 0x80000000
+ sw t2, CGU_MUXCR(t1)
+ li t2, 0x800B0001
+ b 5f
+ sw t2, CGU_PLL1CR(t1) /* delay slot */
+
+ /* 133 MHz clock */
+2:
+ li t2, 0x80000054
+ sw t2, CGU_DIVCR(t1)
+ li t2, 0x80000000
+ sw t2, CGU_MUXCR(t1)
+ li t2, 0x800B0001
+ b 5f
+ sw t2, CGU_PLL1CR(t1) /* delay slot */
+
+ /* 150 MHz clock */
+3:
+ li t2, 0x80000017
+ sw t2, CGU_DIVCR(t1)
+ li t2, 0xC00B0001
+ sw t2, CGU_PLL1CR(t1)
+ li t3, 0x80000000
+4:
+ lw t2, CGU_PLL1SR(t1)
+ and t2, t2, t3
+ beq t2, zero, 4b
+ nop
+ li t2, 0x80000001
+ sw t2, CGU_MUXCR(t1)
+5:
+ j ra
+ nop
+
+ .end cgu_init
+
+
+/*
+ * void sdram_init(long)
+ *
+ * a0 has the clock value
+ */
+ .globl sdram_init
+ .ent sdram_init
+sdram_init:
+
+ li t1, MC_MODUL_BASE
+
+#if 0
+ /* Disable memory controller before changing any of its registers */
+ sw zero, MC_CTRLENA(t1)
+#endif
+
+ li t2, 100000000
+ beq a0, t2, 1f
+ nop
+ li t2, 133000000
+ beq a0, t2, 2f
+ nop
+ li t2, 150000000
+ beq a0, t2, 3f
+ nop
+ b 5f
+ nop
+
+ /* 100 MHz clock */
+1:
+ /* Set clock ratio (clkrat=1:1, rddel=3) */
+ li t2, 0x00000003
+ sw t2, MC_IOGP(t1)
+
+ /* Set sdram refresh rate (4K/64ms @ 100MHz) */
+ li t2, 0x0000061A
+ b 4f
+ sw t2, MC_TREFRESH(t1)
+
+ /* 133 MHz clock */
+2:
+ /* Set clock ratio (clkrat=1:1, rddel=3) */
+ li t2, 0x00000003
+ sw t2, MC_IOGP(t1)
+
+ /* Set sdram refresh rate (4K/64ms @ 133MHz) */
+ li t2, 0x00000822
+ b 4f
+ sw t2, MC_TREFRESH(t1)
+
+ /* 150 MHz clock */
+3:
+ /* Set clock ratio (clkrat=3:2, rddel=4) */
+ li t2, 0x00000014
+ sw t2, MC_IOGP(t1)
+
+ /* Set sdram refresh rate (4K/64ms @ 150MHz) */
+ li t2, 0x00000927
+ sw t2, MC_TREFRESH(t1)
+
+4:
+ /* Clear Error log registers */
+ sw zero, MC_ERRCAUSE(t1)
+ sw zero, MC_ERRADDR(t1)
+
+ /* Clear Power-down registers */
+ sw zero, MC_SELFRFSH(t1)
+
+ /* Set CAS Latency */
+ li t2, 0x00000020 /* CL = 2 */
+ sw t2, MC_MRSCODE(t1)
+
+ /* Set word width to 16 bit */
+ li t2, 0x2
+ sw t2, MC_CFGDW(t1)
+
+ /* Set CS0 to SDRAM parameters */
+ li t2, 0x000014C9
+ sw t2, MC_CFGPB0(t1)
+
+ /* Set SDRAM latency parameters */
+ li t2, 0x00026325 /* BC PC100 */
+ sw t2, MC_LATENCY(t1)
+
+5:
+ /* Finally enable the controller */
+ li t2, 0x00000001
+ sw t2, MC_CTRLENA(t1)
+
+ j ra
+ nop
+
+ .end sdram_init
+
+
+ .globl lowlevel_init
+ .ent lowlevel_init
+lowlevel_init:
+
+ /* EBU, CGU and SDRAM Initialization.
+ */
+ li a0, CPU_CLOCK_RATE
+ move t0, ra
+
+ /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
+ * modify t0 and a0.
+ */
+ bal cgu_init
+ nop
+ bal ebu_init
+ nop
+ bal sdram_init
+ nop
+ move ra, t0
+
+ j ra
+ nop
+
+ .end lowlevel_init
+++ /dev/null
-/*
- * Memory sub-system initialization code for INCA-IP development board.
- *
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-
-#define EBU_MODUL_BASE 0xB8000200
-#define EBU_CLC(value) 0x0000(value)
-#define EBU_CON(value) 0x0010(value)
-#define EBU_ADDSEL0(value) 0x0020(value)
-#define EBU_ADDSEL1(value) 0x0024(value)
-#define EBU_ADDSEL2(value) 0x0028(value)
-#define EBU_BUSCON0(value) 0x0060(value)
-#define EBU_BUSCON1(value) 0x0064(value)
-#define EBU_BUSCON2(value) 0x0068(value)
-
-#define MC_MODUL_BASE 0xBF800000
-#define MC_ERRCAUSE(value) 0x0100(value)
-#define MC_ERRADDR(value) 0x0108(value)
-#define MC_IOGP(value) 0x0800(value)
-#define MC_SELFRFSH(value) 0x0A00(value)
-#define MC_CTRLENA(value) 0x1000(value)
-#define MC_MRSCODE(value) 0x1008(value)
-#define MC_CFGDW(value) 0x1010(value)
-#define MC_CFGPB0(value) 0x1018(value)
-#define MC_LATENCY(value) 0x1038(value)
-#define MC_TREFRESH(value) 0x1040(value)
-
-#define CGU_MODUL_BASE 0xBF107000
-#define CGU_PLL1CR(value) 0x0008(value)
-#define CGU_DIVCR(value) 0x0010(value)
-#define CGU_MUXCR(value) 0x0014(value)
-#define CGU_PLL1SR(value) 0x000C(value)
-
- .set noreorder
-
-
-/*
- * void ebu_init(long)
- *
- * a0 has the clock value we are going to run at
- */
- .globl ebu_init
- .ent ebu_init
-ebu_init:
-
- li t1, EBU_MODUL_BASE
- li t2, 0xA0000041
- sw t2, EBU_ADDSEL0(t1)
- li t2, 0xA0800041
- sw t2, EBU_ADDSEL2(t1)
- li t2, 0xBE0000F1
- sw t2, EBU_ADDSEL1(t1)
-
- li t3, 100000000
- beq a0, t3, 1f
- nop
- li t3, 133000000
- beq a0, t3, 2f
- nop
- li t3, 150000000
- beq a0, t3, 2f
- nop
- b 3f
- nop
-
- /* 100 MHz */
-1:
- li t2, 0x8841417D
- sw t2, EBU_BUSCON0(t1)
- sw t2, EBU_BUSCON2(t1)
- li t2, 0x684142BD
- b 3f
- sw t2, EBU_BUSCON1(t1) /* delay slot */
-
- /* 133 or 150 MHz */
-2:
- li t2, 0x8841417E
- sw t2, EBU_BUSCON0(t1)
- sw t2, EBU_BUSCON2(t1)
- li t2, 0x684143FD
- sw t2, EBU_BUSCON1(t1)
-3:
- j ra
- nop
-
- .end ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
- .globl cgu_init
- .ent cgu_init
-cgu_init:
-
- li t1, CGU_MODUL_BASE
-
- li t3, 100000000
- beq a0, t3, 1f
- nop
- li t3, 133000000
- beq a0, t3, 2f
- nop
- li t3, 150000000
- beq a0, t3, 3f
- nop
- b 5f
- nop
-
- /* 100 MHz clock */
-1:
- li t2, 0x80000014
- sw t2, CGU_DIVCR(t1)
- li t2, 0x80000000
- sw t2, CGU_MUXCR(t1)
- li t2, 0x800B0001
- b 5f
- sw t2, CGU_PLL1CR(t1) /* delay slot */
-
- /* 133 MHz clock */
-2:
- li t2, 0x80000054
- sw t2, CGU_DIVCR(t1)
- li t2, 0x80000000
- sw t2, CGU_MUXCR(t1)
- li t2, 0x800B0001
- b 5f
- sw t2, CGU_PLL1CR(t1) /* delay slot */
-
- /* 150 MHz clock */
-3:
- li t2, 0x80000017
- sw t2, CGU_DIVCR(t1)
- li t2, 0xC00B0001
- sw t2, CGU_PLL1CR(t1)
- li t3, 0x80000000
-4:
- lw t2, CGU_PLL1SR(t1)
- and t2, t2, t3
- beq t2, zero, 4b
- nop
- li t2, 0x80000001
- sw t2, CGU_MUXCR(t1)
-5:
- j ra
- nop
-
- .end cgu_init
-
-
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
- .globl sdram_init
- .ent sdram_init
-sdram_init:
-
- li t1, MC_MODUL_BASE
-
-#if 0
- /* Disable memory controller before changing any of its registers */
- sw zero, MC_CTRLENA(t1)
-#endif
-
- li t2, 100000000
- beq a0, t2, 1f
- nop
- li t2, 133000000
- beq a0, t2, 2f
- nop
- li t2, 150000000
- beq a0, t2, 3f
- nop
- b 5f
- nop
-
- /* 100 MHz clock */
-1:
- /* Set clock ratio (clkrat=1:1, rddel=3) */
- li t2, 0x00000003
- sw t2, MC_IOGP(t1)
-
- /* Set sdram refresh rate (4K/64ms @ 100MHz) */
- li t2, 0x0000061A
- b 4f
- sw t2, MC_TREFRESH(t1)
-
- /* 133 MHz clock */
-2:
- /* Set clock ratio (clkrat=1:1, rddel=3) */
- li t2, 0x00000003
- sw t2, MC_IOGP(t1)
-
- /* Set sdram refresh rate (4K/64ms @ 133MHz) */
- li t2, 0x00000822
- b 4f
- sw t2, MC_TREFRESH(t1)
-
- /* 150 MHz clock */
-3:
- /* Set clock ratio (clkrat=3:2, rddel=4) */
- li t2, 0x00000014
- sw t2, MC_IOGP(t1)
-
- /* Set sdram refresh rate (4K/64ms @ 150MHz) */
- li t2, 0x00000927
- sw t2, MC_TREFRESH(t1)
-
-4:
- /* Clear Error log registers */
- sw zero, MC_ERRCAUSE(t1)
- sw zero, MC_ERRADDR(t1)
-
- /* Clear Power-down registers */
- sw zero, MC_SELFRFSH(t1)
-
- /* Set CAS Latency */
- li t2, 0x00000020 /* CL = 2 */
- sw t2, MC_MRSCODE(t1)
-
- /* Set word width to 16 bit */
- li t2, 0x2
- sw t2, MC_CFGDW(t1)
-
- /* Set CS0 to SDRAM parameters */
- li t2, 0x000014C9
- sw t2, MC_CFGPB0(t1)
-
- /* Set SDRAM latency parameters */
- li t2, 0x00026325 /* BC PC100 */
- sw t2, MC_LATENCY(t1)
-
-5:
- /* Finally enable the controller */
- li t2, 0x00000001
- sw t2, MC_CTRLENA(t1)
-
- j ra
- nop
-
- .end sdram_init
-
-
- .globl memsetup
- .ent memsetup
-memsetup:
-
- /* EBU, CGU and SDRAM Initialization.
- */
- li a0, CPU_CLOCK_RATE
- move t0, ra
-
- /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
- * modify t0 and a0.
- */
- bal cgu_init
- nop
- bal ebu_init
- nop
- bal sdram_init
- nop
- move ra, t0
-
- j ra
- nop
-
- .end memsetup
LIB = lib$(BOARD).a
OBJS := innokom.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+ /* Set up GPIO pins first ----------------------------------------- */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ ldr r0, =PSSR /* enable GPIO pins */
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
+/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
+/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
+/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
+/* */
+/* ldr r1, =LED_BLANK */
+/* mov r0, #0xFF */
+/* str r0, [r1] / turn on hex leds */
+/* */
+/*loop: */
+/* */
+/* ldr r0, =0xB0070001 */
+/* ldr r1, =_LED */
+/* str r0, [r1] / hex display */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2a: Initialize Asynchronous static memory controller */
+ /* ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* that data latches */
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2b: Initialize Card Interface */
+ /* ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+ ldr r2, [r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, [r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+ ldr r2, [r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, [r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, [r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, [r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, [r1, #MCIO1_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
+
+ /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
+ adr r3, mem_init /* r0 <- current position of code */
+ ldr r2, =mem_init
+ cmp r3, r2 /* skip init if in place */
+ beq initirqs
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
+
+ /* Before accessing MDREFR we need a valid DRI field, so we set */
+ /* this to power on defaults + DRI field. */
+
+ ldr r3, =CFG_MDREFR_VAL
+ ldr r2, =0xFFF
+ and r3, r3, r2
+ ldr r4, =0x03ca4000
+ orr r4, r4, r3
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+ /* ---------------------------------------------------------------- */
+
+ /* Initialize SXCNFG register. Assert the enable bits */
+
+ /* Write SXMRS to cause an MRS command to all enabled banks of */
+ /* synchronous static memory. Note that SXLCR need not be written */
+ /* at this time. */
+
+ /* FIXME: we use async mode for now */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
+
+ /* Step 4a: assert MDREFR:K?RUN and configure */
+ /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
+
+ ldr r4, =CFG_MDREFR_VAL
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Step 4b: de-assert MDREFR:SLFRSH. */
+
+ bic r4, r4, #(MDREFR_SLFRSH)
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* Step 4c: assert MDREFR:E1PIN and E0PIO */
+
+ orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
+ /* configure but not enable each SDRAM partition pair. */
+
+ ldr r4, =CFG_MDCNFG_VAL
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
+
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
+ /* 100..200 µsec. */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by */
+ /* attempting non-burst read or write accesses to disabled */
+ /* SDRAM, as commonly specified in the power up sequence */
+ /* documented in SDRAM data sheets. The address(es) used */
+ /* for this purpose must not be cacheable. */
+
+ /* There should 9 writes, since the first write doesn't */
+ /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
+ /* PXA210 Processors Specification Update, */
+ /* Jan 2003, Errata #116, page 30. */
+
+
+ ldr r3, =CFG_DRAM_BASE
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+ /* Step 4g: Write MDCNFG with enable bits asserted */
+ /* (MDCNFG:DEx set to 1). */
+
+ ldr r3, [r1, #MDCNFG_OFFSET]
+ orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
+ str r3, [r1, #MDCNFG_OFFSET]
+
+ /* Step 4h: Write MDMRS. */
+
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+
+ /* We are finished with Intel's memory controller initialisation */
+
+ /* ---------------------------------------------------------------- */
+ /* Disable (mask) all interrupts at interrupt controller */
+ /* ---------------------------------------------------------------- */
+
+initirqs:
+
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
+
+
+ /* ---------------------------------------------------------------- */
+ /* Clock initialisation */
+ /* ---------------------------------------------------------------- */
+
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency */
+ /* (hard-coding at 398.12MHz for now). */
+
+ /* Turn Off ALL on-chip peripheral clocks for re-configuration */
+ /* Note: See label 'ENABLECLKS' for the re-enabling */
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+
+ /* default value in case no valid rotary switch setting is found */
+ ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
+
+ /* ... and write the core clock config register */
+ ldr r1, =CCCR
+ str r2, [r1]
+
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+/*
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+*/
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
+ /* has settled. */
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+
+ /* ---------------------------------------------------------------- */
+ /* */
+ /* ---------------------------------------------------------------- */
+
+ /* Save SDRAM size */
+ ldr r1, =DRAM_SIZE
+ str r8, [r1]
+
+ /* Interrupt init: Mask all interrupts */
+ ldr r0, =ICMR /* enable no sources */
+ mov r1, #0
+ str r1, [r0]
+
+ /* FIXME */
+
+#ifndef DEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+ mov pc, lr
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CFG_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-
-/*
- * Memory setup
- */
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CFG_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CFG_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CFG_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CFG_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CFG_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CFG_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CFG_PSSR_VAL
- str r1, [r0]
-
-/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
-/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
-/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
-/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/* ldr r1, =LED_BLANK */
-/* mov r0, #0xFF */
-/* str r0, [r1] / turn on hex leds */
-/* */
-/*loop: */
-/* */
-/* ldr r0, =0xB0070001 */
-/* ldr r1, =_LED */
-/* str r0, [r1] / hex display */
-
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
- adr r3, mem_init /* r0 <- current position of code */
- ldr r2, =mem_init
- cmp r3, r2 /* skip init if in place */
- beq initirqs
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CFG_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* Step 4a: assert MDREFR:K?RUN and configure */
- /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
-
- ldr r4, =CFG_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO */
-
- orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CFG_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- /* There should 9 writes, since the first write doesn't */
- /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
- /* PXA210 Processors Specification Update, */
- /* Jan 2003, Errata #116, page 30. */
-
-
- ldr r3, =CFG_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
- /* enable the 32Khz oscillator for RTC and PowerManager */
-/*
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-*/
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#ifndef DEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End memsetup */
- /* ---------------------------------------------------------------- */
-
-endmemsetup:
-
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := lart.o flash.o
-SOBJS := flashasm.o memsetup.o
+SOBJS := flashasm.o lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+MEM_BASE: .long 0xa0000000
+MEM_START: .long 0xc0000000
+
+#define MDCNFG 0x00
+#define MDCAS0 0x04
+#define MDCAS1 0x08
+#define MDCAS2 0x0c
+#define MSC0 0x10
+#define MSC1 0x14
+#define MECR 0x18
+
+mdcas0: .long 0xc71c703f
+mdcas1: .long 0xffc71c71
+mdcas2: .long 0xffffffff
+/* mdcnfg: .long 0x0bb2bcbf */
+mdcnfg: .long 0x0334b22f @ alt
+/* mcs0: .long 0xfff8fff8 */
+msc0: .long 0xad8c4888 @ alt
+mecr: .long 0x00060006
+/* mecr: .long 0x994a994a @ alt */
+
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr r0, MEM_BASE
+
+ /* Setup the flash memory */
+ ldr r1, msc0
+ str r1, [r0, #MSC0]
+
+ /* Set up the DRAM */
+
+ /* MDCAS0 */
+ ldr r1, mdcas0
+ str r1, [r0, #MDCAS0]
+
+ /* MDCAS1 */
+ ldr r1, mdcas1
+ str r1, [r0, #MDCAS1]
+
+ /* MDCAS2 */
+ ldr r1, mdcas2
+ str r1, [r0, #MDCAS2]
+
+ /* MDCNFG */
+ ldr r1, mdcnfg
+ str r1, [r0, #MDCNFG]
+
+ /* Set up PCMCIA space */
+ ldr r1, mecr
+ str r1, [r0, #MECR]
+
+ /* Load something to activate bank */
+ ldr r1, MEM_START
+
+.rept 8
+ ldr r0, [r1]
+.endr
+
+ /* everything is fine now */
+ mov pc, lr
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-
-/* some parameters for the board */
-
-MEM_BASE: .long 0xa0000000
-MEM_START: .long 0xc0000000
-
-#define MDCNFG 0x00
-#define MDCAS0 0x04
-#define MDCAS1 0x08
-#define MDCAS2 0x0c
-#define MSC0 0x10
-#define MSC1 0x14
-#define MECR 0x18
-
-mdcas0: .long 0xc71c703f
-mdcas1: .long 0xffc71c71
-mdcas2: .long 0xffffffff
-/* mdcnfg: .long 0x0bb2bcbf */
-mdcnfg: .long 0x0334b22f @ alt
-/* mcs0: .long 0xfff8fff8 */
-msc0: .long 0xad8c4888 @ alt
-mecr: .long 0x00060006
-/* mecr: .long 0x994a994a @ alt */
-
-/* setting up the memory */
-
-.globl memsetup
-memsetup:
- ldr r0, MEM_BASE
-
- /* Setup the flash memory */
- ldr r1, msc0
- str r1, [r0, #MSC0]
-
- /* Set up the DRAM */
-
- /* MDCAS0 */
- ldr r1, mdcas0
- str r1, [r0, #MDCAS0]
-
- /* MDCAS1 */
- ldr r1, mdcas1
- str r1, [r0, #MDCAS1]
-
- /* MDCAS2 */
- ldr r1, mdcas2
- str r1, [r0, #MDCAS2]
-
- /* MDCNFG */
- ldr r1, mdcnfg
- str r1, [r0, #MDCNFG]
-
- /* Set up PCMCIA space */
- ldr r1, mecr
- str r1, [r0, #MECR]
-
- /* Load something to activate bank */
- ldr r1, MEM_START
-
-.rept 8
- ldr r0, [r1]
-.endr
-
- /* everything is fine now */
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := logodl.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
--- /dev/null
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+ /* Set up GPIO pins first ----------------------------------------- */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ ldr r0, =PSSR /* enable GPIO pins */
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
+/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
+/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
+/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
+/* */
+/* ldr r1, =LED_BLANK */
+/* mov r0, #0xFF */
+/* str r0, [r1] / turn on hex leds */
+/* */
+/*loop: */
+/* */
+/* ldr r0, =0xB0070001 */
+/* ldr r1, =_LED */
+/* str r0, [r1] / hex display */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2a: Initialize Asynchronous static memory controller */
+ /* ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* that data latches */
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2b: Initialize Card Interface */
+ /* ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+ ldr r2, [r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, [r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+ ldr r2, [r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, [r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, [r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, [r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, [r1, #MCIO1_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
+
+ /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
+ adr r3, mem_init /* r0 <- current position of code */
+ ldr r2, =mem_init
+ cmp r3, r2 /* skip init if in place */
+ beq initirqs
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
+
+ /* Before accessing MDREFR we need a valid DRI field, so we set */
+ /* this to power on defaults + DRI field. */
+
+ ldr r3, =CFG_MDREFR_VAL
+ ldr r2, =0xFFF
+ and r3, r3, r2
+ ldr r4, =0x03ca4000
+ orr r4, r4, r3
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+ /* ---------------------------------------------------------------- */
+
+ /* Initialize SXCNFG register. Assert the enable bits */
+
+ /* Write SXMRS to cause an MRS command to all enabled banks of */
+ /* synchronous static memory. Note that SXLCR need not be written */
+ /* at this time. */
+
+ /* FIXME: we use async mode for now */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
+
+ /* Step 4a: assert MDREFR:K?RUN and configure */
+ /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
+
+ ldr r4, =CFG_MDREFR_VAL
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Step 4b: de-assert MDREFR:SLFRSH. */
+
+ bic r4, r4, #(MDREFR_SLFRSH)
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* Step 4c: assert MDREFR:E1PIN and E0PIO */
+
+ orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
+ /* configure but not enable each SDRAM partition pair. */
+
+ ldr r4, =CFG_MDCNFG_VAL
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
+
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
+ /* 100..200 µsec. */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by */
+ /* attempting non-burst read or write accesses to disabled */
+ /* SDRAM, as commonly specified in the power up sequence */
+ /* documented in SDRAM data sheets. The address(es) used */
+ /* for this purpose must not be cacheable. */
+
+ /* There should 9 writes, since the first write doesn't */
+ /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
+ /* PXA210 Processors Specification Update, */
+ /* Jan 2003, Errata #116, page 30. */
+
+
+ ldr r3, =CFG_DRAM_BASE
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+ /* Step 4g: Write MDCNFG with enable bits asserted */
+ /* (MDCNFG:DEx set to 1). */
+
+ ldr r3, [r1, #MDCNFG_OFFSET]
+ orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
+ str r3, [r1, #MDCNFG_OFFSET]
+
+ /* Step 4h: Write MDMRS. */
+
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+
+ /* We are finished with Intel's memory controller initialisation */
+
+ /* ---------------------------------------------------------------- */
+ /* Disable (mask) all interrupts at interrupt controller */
+ /* ---------------------------------------------------------------- */
+
+initirqs:
+
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
+
+
+ /* ---------------------------------------------------------------- */
+ /* Clock initialisation */
+ /* ---------------------------------------------------------------- */
+
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency */
+ /* (hard-coding at 398.12MHz for now). */
+
+ /* Turn Off ALL on-chip peripheral clocks for re-configuration */
+ /* Note: See label 'ENABLECLKS' for the re-enabling */
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+
+ /* default value in case no valid rotary switch setting is found */
+ ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
+
+ /* ... and write the core clock config register */
+ ldr r1, =CCCR
+ str r2, [r1]
+
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+/*
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+*/
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
+ /* has settled. */
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+
+ /* ---------------------------------------------------------------- */
+ /* */
+ /* ---------------------------------------------------------------- */
+
+ /* Save SDRAM size */
+ ldr r1, =DRAM_SIZE
+ str r8, [r1]
+
+ /* Interrupt init: Mask all interrupts */
+ ldr r0, =ICMR /* enable no sources */
+ mov r1, #0
+ str r1, [r0]
+
+ /* FIXME */
+
+#ifndef DEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+ mov pc, lr
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CFG_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-
-/*
- * Memory setup
- */
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CFG_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CFG_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CFG_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CFG_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CFG_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CFG_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CFG_PSSR_VAL
- str r1, [r0]
-
-/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
-/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
-/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
-/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/* ldr r1, =LED_BLANK */
-/* mov r0, #0xFF */
-/* str r0, [r1] / turn on hex leds */
-/* */
-/*loop: */
-/* */
-/* ldr r0, =0xB0070001 */
-/* ldr r1, =_LED */
-/* str r0, [r1] / hex display */
-
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
- adr r3, mem_init /* r0 <- current position of code */
- ldr r2, =mem_init
- cmp r3, r2 /* skip init if in place */
- beq initirqs
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CFG_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* Step 4a: assert MDREFR:K?RUN and configure */
- /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
-
- ldr r4, =CFG_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO */
-
- orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CFG_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- /* There should 9 writes, since the first write doesn't */
- /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
- /* PXA210 Processors Specification Update, */
- /* Jan 2003, Errata #116, page 30. */
-
-
- ldr r3, =CFG_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
- /* enable the 32Khz oscillator for RTC and PowerManager */
-/*
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-*/
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#ifndef DEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End memsetup */
- /* ---------------------------------------------------------------- */
-
-endmemsetup:
-
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := lpd7a40x.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory Setup - initialize memory controller(s) for devices required
+ * to boot and relocate
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* memory controller */
+#define BCRX_DEFAULT (0x0000fbe0)
+#define BCRX_MW_8 (0x00000000)
+#define BCRX_MW_16 (0x10000000)
+#define BCRX_MW_32 (0x20000000)
+#define BCRX_PME (0x08000000)
+#define BCRX_WP (0x04000000)
+#define BCRX_WST2_SHIFT (11)
+#define BCRX_WST1_SHIFT (5)
+#define BCRX_IDCY_SHIFT (0)
+
+/* Bank0 Async Flash */
+#define BCR0 (0x80002000)
+#define BCR0_FLASH (BCRX_MW_32 | (0x08<<BCRX_WST2_SHIFT) | (0x0E<<BCRX_WST1_SHIFT))
+
+/* Bank1 Open */
+#define BCR1 (0x80002004)
+
+/* Bank2 Not used (EEPROM?) */
+#define BCR2 (0x80002008)
+
+/* Bank3 Not used */
+#define BCR3 (0x8000200C)
+
+/* Bank4 PC Card1 */
+
+/* Bank5 PC Card2 */
+
+/* Bank6 CPLD IO Controller Peripherals (slow) */
+#define BCR6 (0x80002018)
+#define BCR6_CPLD_SLOW (BCRX_DEFAULT | BCRX_MW_16)
+
+/* Bank7 CPLD IO Controller Peripherals (fast) */
+#define BCR7 (0x8000201C)
+#define BCR7_CPLD_FAST (BCRX_MW_16 | (0x16<<BCRX_WST2_SHIFT) | (0x16<<BCRX_WST1_SHIFT) | (0x2<<BCRX_IDCY_SHIFT))
+
+/* SDRAM */
+#define GBLCNFG (0x80002404)
+#define GC_CKE (0x80000000)
+#define GC_CKSD (0x40000000)
+#define GC_LCR (0x00000040)
+#define GC_SMEMBURST (0x00000020)
+#define GC_MRS (0x00000002)
+#define GC_INIT (0x00000001)
+
+#define GC_CMD_NORMAL (GC_CKE)
+#define GC_CMD_MODE (GC_CKE | GC_MRS)
+#define GC_CMD_SYNCFLASH_LOAD (GC_CKE | GC_MRS | GC_LCR)
+#define GC_CMD_PRECHARGEALL (GC_CKE | GC_INIT)
+#define GC_CMD_NOP (GC_CKE | GC_INIT | GC_MRS)
+
+#define RFSHTMR (0x80002408)
+#define RFSHTMR_INIT (10) /* period=100 ns, HCLK=100Mhz, (2048+1-15.6*66) */
+#define RFSHTMR_NORMAL (1500) /* period=15.6 us, HCLK=100Mhz, (2048+1-15.6*66) */
+
+#define SDCSCX_BASE (0x80002410)
+#define SDCSCX_DEFAULT (0x01220008)
+#define SDCSCX_AUTOPC (0x01000000)
+#define SDCSCX_RAS2CAS_2 (0x00200000)
+#define SDCSCX_RAS2CAS_3 (0x00300000)
+#define SDCSCX_WBL (0x00080000)
+#define SDCSCX_CASLAT_8 (0x00070000)
+#define SDCSCX_CASLAT_7 (0x00060000)
+#define SDCSCX_CASLAT_6 (0x00050000)
+#define SDCSCX_CASLAT_5 (0x00040000)
+#define SDCSCX_CASLAT_4 (0x00030000)
+#define SDCSCX_CASLAT_3 (0x00020000)
+#define SDCSCX_CASLAT_2 (0x00010000)
+#define SDCSCX_2KPAGE (0x00000040)
+#define SDCSCX_SROMLL (0x00000020)
+#define SDCSCX_SROM512 (0x00000010)
+#define SDCSCX_4BNK (0x00000008)
+#define SDCSCX_2BNK (0x00000000)
+#define SDCSCX_EBW_16 (0x00000004)
+#define SDCSCX_EBW_32 (0x00000000)
+
+#define SDRAM_BASE (0xC0000000)
+#define SDCSC_BANK_OFFSET (0x10000000)
+
+/*
+ * The SDRAM DEVICE MODE PROGRAMMING VALUE
+ */
+#define BURST_LENGTH_4 (2 << 10)
+#define BURST_LENGTH_8 (3 << 10)
+#define WBURST_LENGTH_BL (0 << 19)
+#define WBURST_LENGTH_SINGLE (1 << 19)
+#define CAS_2 (2 << 14)
+#define CAS_3 (3 << 14)
+#define BAT_SEQUENTIAL (0 << 13)
+#define BAT_INTERLEAVED (1 << 13)
+#define OPM_NORMAL (0 << 17)
+#define SDRAM_DEVICE_MODE (WBURST_LENGTH_BL|OPM_NORMAL|CAS_3|BAT_SEQUENTIAL|BURST_LENGTH_4)
+
+
+#define TIMER1_BASE (0x80000C00)
+
+/*
+ * special lookup flags
+ */
+#define DO_MEM_DELAY 1
+#define DO_MEM_READ 2
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+ mov r9, lr @ save return address
+
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads INITMEM_DATA out of FLASH rather than memory ! */
+ /* r0 = current word pointer */
+ /* r1 = end word location, one word past last actual word */
+ /* r3 = address for writes, special lookup flags */
+ /* r4 = value for writes, delay constants, or read addresses */
+ /* r2 = location for mem reads */
+
+ ldr r0, =INITMEM_DATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ add r1, r0, #112
+
+mem_loop:
+ cmp r1, r0
+ moveq pc, r9 @ Done
+
+ ldr r3, [r0], #4 @ Fetch Destination Register Address, or 1 for delay
+ ldr r4, [r0], #4 @ value
+
+ cmp r3, #DO_MEM_DELAY
+ bleq mem_delay
+ beq mem_loop
+ cmp r3, #DO_MEM_READ
+ ldreq r2, [r4]
+ beq mem_loop
+ str r4, [r3] @ normal register/ram store
+ b mem_loop
+
+mem_delay:
+ ldr r5, =TIMER1_BASE
+ mov r6, r4, LSR #1 @ timer resolution is ~2us
+ str r6, [r5]
+ mov r6, #0x88 @ using 508.469KHz clock, enable
+ str r6, [r5, #8]
+0: ldr r6, [r5, #4] @ timer value
+ cmp r6, #0
+ bne 0b
+ mov r6, #0 @ disable timer
+ str r6, [r5, #8]
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+INITMEM_DATA:
+ .word BCR0
+ .word BCR0_FLASH
+ .word BCR6
+ .word BCR6_CPLD_SLOW
+ .word BCR7
+ .word BCR7_CPLD_FAST
+ .word SDCSCX_BASE
+ .word (SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
+ .word GBLCNFG
+ .word GC_CMD_NOP
+ .word DO_MEM_DELAY
+ .word 200
+ .word GBLCNFG
+ .word GC_CMD_PRECHARGEALL
+ .word RFSHTMR
+ .word RFSHTMR_INIT
+ .word DO_MEM_DELAY
+ .word 8
+ .word RFSHTMR
+ .word RFSHTMR_NORMAL
+ .word GBLCNFG
+ .word GC_CMD_MODE
+ .word DO_MEM_READ
+ .word (SDRAM_BASE | SDRAM_DEVICE_MODE)
+ .word GBLCNFG
+ .word GC_CMD_NORMAL
+ .word SDCSCX_BASE
+ .word (SDCSCX_AUTOPC | SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
+++ /dev/null
-/*
- * Memory Setup - initialize memory controller(s) for devices required
- * to boot and relocate
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-
-/* memory controller */
-#define BCRX_DEFAULT (0x0000fbe0)
-#define BCRX_MW_8 (0x00000000)
-#define BCRX_MW_16 (0x10000000)
-#define BCRX_MW_32 (0x20000000)
-#define BCRX_PME (0x08000000)
-#define BCRX_WP (0x04000000)
-#define BCRX_WST2_SHIFT (11)
-#define BCRX_WST1_SHIFT (5)
-#define BCRX_IDCY_SHIFT (0)
-
-/* Bank0 Async Flash */
-#define BCR0 (0x80002000)
-#define BCR0_FLASH (BCRX_MW_32 | (0x08<<BCRX_WST2_SHIFT) | (0x0E<<BCRX_WST1_SHIFT))
-
-/* Bank1 Open */
-#define BCR1 (0x80002004)
-
-/* Bank2 Not used (EEPROM?) */
-#define BCR2 (0x80002008)
-
-/* Bank3 Not used */
-#define BCR3 (0x8000200C)
-
-/* Bank4 PC Card1 */
-
-/* Bank5 PC Card2 */
-
-/* Bank6 CPLD IO Controller Peripherals (slow) */
-#define BCR6 (0x80002018)
-#define BCR6_CPLD_SLOW (BCRX_DEFAULT | BCRX_MW_16)
-
-/* Bank7 CPLD IO Controller Peripherals (fast) */
-#define BCR7 (0x8000201C)
-#define BCR7_CPLD_FAST (BCRX_MW_16 | (0x16<<BCRX_WST2_SHIFT) | (0x16<<BCRX_WST1_SHIFT) | (0x2<<BCRX_IDCY_SHIFT))
-
-/* SDRAM */
-#define GBLCNFG (0x80002404)
-#define GC_CKE (0x80000000)
-#define GC_CKSD (0x40000000)
-#define GC_LCR (0x00000040)
-#define GC_SMEMBURST (0x00000020)
-#define GC_MRS (0x00000002)
-#define GC_INIT (0x00000001)
-
-#define GC_CMD_NORMAL (GC_CKE)
-#define GC_CMD_MODE (GC_CKE | GC_MRS)
-#define GC_CMD_SYNCFLASH_LOAD (GC_CKE | GC_MRS | GC_LCR)
-#define GC_CMD_PRECHARGEALL (GC_CKE | GC_INIT)
-#define GC_CMD_NOP (GC_CKE | GC_INIT | GC_MRS)
-
-#define RFSHTMR (0x80002408)
-#define RFSHTMR_INIT (10) /* period=100 ns, HCLK=100Mhz, (2048+1-15.6*66) */
-#define RFSHTMR_NORMAL (1500) /* period=15.6 us, HCLK=100Mhz, (2048+1-15.6*66) */
-
-#define SDCSCX_BASE (0x80002410)
-#define SDCSCX_DEFAULT (0x01220008)
-#define SDCSCX_AUTOPC (0x01000000)
-#define SDCSCX_RAS2CAS_2 (0x00200000)
-#define SDCSCX_RAS2CAS_3 (0x00300000)
-#define SDCSCX_WBL (0x00080000)
-#define SDCSCX_CASLAT_8 (0x00070000)
-#define SDCSCX_CASLAT_7 (0x00060000)
-#define SDCSCX_CASLAT_6 (0x00050000)
-#define SDCSCX_CASLAT_5 (0x00040000)
-#define SDCSCX_CASLAT_4 (0x00030000)
-#define SDCSCX_CASLAT_3 (0x00020000)
-#define SDCSCX_CASLAT_2 (0x00010000)
-#define SDCSCX_2KPAGE (0x00000040)
-#define SDCSCX_SROMLL (0x00000020)
-#define SDCSCX_SROM512 (0x00000010)
-#define SDCSCX_4BNK (0x00000008)
-#define SDCSCX_2BNK (0x00000000)
-#define SDCSCX_EBW_16 (0x00000004)
-#define SDCSCX_EBW_32 (0x00000000)
-
-#define SDRAM_BASE (0xC0000000)
-#define SDCSC_BANK_OFFSET (0x10000000)
-
-/*
- * The SDRAM DEVICE MODE PROGRAMMING VALUE
- */
-#define BURST_LENGTH_4 (2 << 10)
-#define BURST_LENGTH_8 (3 << 10)
-#define WBURST_LENGTH_BL (0 << 19)
-#define WBURST_LENGTH_SINGLE (1 << 19)
-#define CAS_2 (2 << 14)
-#define CAS_3 (3 << 14)
-#define BAT_SEQUENTIAL (0 << 13)
-#define BAT_INTERLEAVED (1 << 13)
-#define OPM_NORMAL (0 << 17)
-#define SDRAM_DEVICE_MODE (WBURST_LENGTH_BL|OPM_NORMAL|CAS_3|BAT_SEQUENTIAL|BURST_LENGTH_4)
-
-
-#define TIMER1_BASE (0x80000C00)
-
-/*
- * special lookup flags
- */
-#define DO_MEM_DELAY 1
-#define DO_MEM_READ 2
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-.globl memsetup
-memsetup:
- mov r9, lr @ save return address
-
- /* memory control configuration */
- /* make r0 relative the current location so that it */
- /* reads INITMEM_DATA out of FLASH rather than memory ! */
- /* r0 = current word pointer */
- /* r1 = end word location, one word past last actual word */
- /* r3 = address for writes, special lookup flags */
- /* r4 = value for writes, delay constants, or read addresses */
- /* r2 = location for mem reads */
-
- ldr r0, =INITMEM_DATA
- ldr r1, _TEXT_BASE
- sub r0, r0, r1
- add r1, r0, #112
-
-mem_loop:
- cmp r1, r0
- moveq pc, r9 @ Done
-
- ldr r3, [r0], #4 @ Fetch Destination Register Address, or 1 for delay
- ldr r4, [r0], #4 @ value
-
- cmp r3, #DO_MEM_DELAY
- bleq mem_delay
- beq mem_loop
- cmp r3, #DO_MEM_READ
- ldreq r2, [r4]
- beq mem_loop
- str r4, [r3] @ normal register/ram store
- b mem_loop
-
-mem_delay:
- ldr r5, =TIMER1_BASE
- mov r6, r4, LSR #1 @ timer resolution is ~2us
- str r6, [r5]
- mov r6, #0x88 @ using 508.469KHz clock, enable
- str r6, [r5, #8]
-0: ldr r6, [r5, #4] @ timer value
- cmp r6, #0
- bne 0b
- mov r6, #0 @ disable timer
- str r6, [r5, #8]
- mov pc, lr
-
- .ltorg
-/* the literal pools origin */
-
-INITMEM_DATA:
- .word BCR0
- .word BCR0_FLASH
- .word BCR6
- .word BCR6_CPLD_SLOW
- .word BCR7
- .word BCR7_CPLD_FAST
- .word SDCSCX_BASE
- .word (SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
- .word GBLCNFG
- .word GC_CMD_NOP
- .word DO_MEM_DELAY
- .word 200
- .word GBLCNFG
- .word GC_CMD_PRECHARGEALL
- .word RFSHTMR
- .word RFSHTMR_INIT
- .word DO_MEM_DELAY
- .word 8
- .word RFSHTMR
- .word RFSHTMR_NORMAL
- .word GBLCNFG
- .word GC_CMD_MODE
- .word DO_MEM_READ
- .word (SDRAM_BASE | SDRAM_DEVICE_MODE)
- .word GBLCNFG
- .word GC_CMD_NORMAL
- .word SDCSCX_BASE
- .word (SDCSCX_AUTOPC | SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
LIB = lib$(BOARD).a
OBJS := lubbock.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+ /* Set up GPIO pins first ----------------------------------------- */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ ldr r0, =PSSR /* enable GPIO pins */
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2a: Initialize Asynchronous static memory controller */
+ /* ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* that data latches */
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2b: Initialize Card Interface */
+ /* ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+ ldr r2, [r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, [r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+ ldr r2, [r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, [r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, [r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, [r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, [r1, #MCIO1_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
+
+ /* Before accessing MDREFR we need a valid DRI field, so we set */
+ /* this to power on defaults + DRI field. */
+
+ ldr r3, =CFG_MDREFR_VAL
+ ldr r2, =0xFFF
+ and r3, r3, r2
+ ldr r4, =0x03ca4000
+ orr r4, r4, r3
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Note: preserve the mdrefr value in r4 */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+ /* ---------------------------------------------------------------- */
+
+ /* Initialize SXCNFG register. Assert the enable bits */
+
+ /* Write SXMRS to cause an MRS command to all enabled banks of */
+ /* synchronous static memory. Note that SXLCR need not be written */
+ /* at this time. */
+
+ /* FIXME: we use async mode for now */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
+
+ /* set MDREFR according to user define with exception of a few bits */
+
+ ldr r4, =CFG_MDREFR_VAL
+ orr r4, r4, #(MDREFR_SLFRSH)
+ bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Step 4b: de-assert MDREFR:SLFRSH. */
+
+ bic r4, r4, #(MDREFR_SLFRSH)
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
+
+ ldr r4, =CFG_MDREFR_VAL
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+
+ /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
+ /* configure but not enable each SDRAM partition pair. */
+
+ ldr r4, =CFG_MDCNFG_VAL
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
+
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
+ /* 100..200 µsec. */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by */
+ /* attempting non-burst read or write accesses to disabled */
+ /* SDRAM, as commonly specified in the power up sequence */
+ /* documented in SDRAM data sheets. The address(es) used */
+ /* for this purpose must not be cacheable. */
+
+ ldr r3, =CFG_DRAM_BASE
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+
+ /* Step 4g: Write MDCNFG with enable bits asserted */
+ /* (MDCNFG:DEx set to 1). */
+
+ ldr r3, [r1, #MDCNFG_OFFSET]
+ orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
+ str r3, [r1, #MDCNFG_OFFSET]
+
+ /* Step 4h: Write MDMRS. */
+
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+
+ /* We are finished with Intel's memory controller initialisation */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Disable (mask) all interrupts at interrupt controller */
+ /* ---------------------------------------------------------------- */
+
+initirqs:
+
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
+
+
+ /* ---------------------------------------------------------------- */
+ /* Clock initialisation */
+ /* ---------------------------------------------------------------- */
+
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency */
+ /* (hard-coding at 398.12MHz for now). */
+
+ /* Turn Off ALL on-chip peripheral clocks for re-configuration */
+ /* Note: See label 'ENABLECLKS' for the re-enabling */
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+
+ /* default value in case no valid rotary switch setting is found */
+ ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
+
+ /* ... and write the core clock config register */
+ ldr r1, =CCCR
+ str r2, [r1]
+
+#ifdef RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
+ /* has settled. */
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* */
+ /* ---------------------------------------------------------------- */
+
+ /* Save SDRAM size */
+ ldr r1, =DRAM_SIZE
+ str r8, [r1]
+
+ /* Interrupt init: Mask all interrupts */
+ ldr r0, =ICMR /* enable no sources */
+ mov r1, #0
+ str r1, [r0]
+
+ /* FIXME */
+
+#define NODEBUG
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+ mov pc, lr
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CFG_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-/*
- * Memory setup
- */
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CFG_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CFG_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CFG_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CFG_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CFG_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CFG_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CFG_PSSR_VAL
- str r1, [r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r3, =CFG_MDREFR_VAL
- ldr r2, =0xFFF
- and r3, r3, r2
- ldr r4, =0x03ca4000
- orr r4, r4, r3
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Note: preserve the mdrefr value in r4 */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- /* set MDREFR according to user define with exception of a few bits */
-
- ldr r4, =CFG_MDREFR_VAL
- orr r4, r4, #(MDREFR_SLFRSH)
- bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Step 4b: de-assert MDREFR:SLFRSH. */
-
- bic r4, r4, #(MDREFR_SLFRSH)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
-
- ldr r4, =CFG_MDREFR_VAL
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CFG_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CFG_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
-
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
-
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size */
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
-
- /* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End memsetup */
- /* ---------------------------------------------------------------- */
-
-endmemsetup:
-
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := modnet50.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
--- /dev/null
+/*
+ * Memory Setup stuff - taken from Linux
+ *
+ * Copyright (c) 2002 Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
+ * (c) 2004 IMMS gGmbH <www.imms.de>, Thomas Elste <info@elste.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/netarm_registers.h>
+
+
+/* some parameters for the board */
+#define FLASH_90ns_WAIT_STATES ((NETARM_PLL_COUNT_VAL + 2) / 3)
+#define FLASH_70ns_WAIT_STATES 4
+
+#define NETARM_MMAP_CS0_BASE (PHYS_FLASH_1)
+#if 1
+#define NETARM_MMAP_CS0_MASK (~(PHYS_FLASH_1_SIZE - 1))
+#else
+#define NETARM_MMAP_CS0_MASK (~(1000000 - 1))
+#endif
+#define NETARM_MMAP_CS1_BASE (PHYS_SDRAM_1)
+#define NETARM_MMAP_CS1_MASK (~(PHYS_SDRAM_1_SIZE - 1))
+#define NETARM_MMAP_CS2_BASE (PHYS_SDRAM_2)
+#define NETARM_MMAP_CS2_MASK (~(PHYS_SDRAM_2_SIZE - 1))
+#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
+#define NETARM_MMAP_CS3_BASE (PHYS_NVRAM_1)
+#define NETARM_MMAP_CS3_MASK (~(PHYS_NVRAM_SIZE - 1))
+#endif
+#define NETARM_MMAP_CS4_BASE (PHYS_EXT_1)
+#define NETARM_MMAP_CS4_MASK (~(PHYS_EXT_SIZE - 1))
+
+/* setting up the memory */
+.globl lowlevel_init
+lowlevel_init:
+
+#if defined(CONFIG_MODNET50)
+ ldr pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - TEXT_BASE)
+
+_jump_to_high:
+ /*
+ * MEM Config Reg
+ * ---------------------------------------------------
+ */
+ ldr r0, =NETARM_MEM_MODULE_BASE
+ ldr r1, =( NETARM_MEM_REFR_PERIOD_USEC(16) | \
+ NETARM_MEM_CFG_REFRESH_EN | \
+ NETARM_MEM_CFG_REFR_CYCLE_5CLKS )
+ str r1, [r0, #+NETARM_MEM_MODULE_CONFIG]
+
+
+memsetup_cs0:
+ /*
+ * Base Addr / Option Reg 0 (Flash)
+ * ---------------------------------------------------
+ */
+ ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS0_BASE) | \
+ NETARM_MEM_BAR_DRAM_FP | \
+ NETARM_MEM_BAR_DRAM_MUX_INT | \
+ NETARM_MEM_BAR_DRAM_MUX_BAL | \
+ NETARM_MEM_BAR_VALID )
+ str r1, [r0, #+NETARM_MEM_CS0_BASE_ADDR]
+
+ /* trust that the bus size for flash was strapped correctly */
+ /* this saves the bus width in r2 and then ORs it back in */
+ /* it's pretty safe assumption, otherwise it wouldn't boot */
+ ldr r2, [r0, #+NETARM_MEM_CS0_OPTIONS]
+ and r2, r2, #NETARM_MEM_OPT_BUS_SIZE_MASK
+
+/* just a test: assume 32 bit flash mem */
+/* mov r2, #NETARM_MEM_OPT_32BIT */
+
+ ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS0_MASK) | \
+ NETARM_MEM_OPT_WAIT_STATES(FLASH_70ns_WAIT_STATES) | \
+ NETARM_MEM_OPT_BCYC_4 | \
+ NETARM_MEM_OPT_BSIZE_16 | \
+ NETARM_MEM_OPT_16BIT | \
+ NETARM_MEM_OPT_READ_ASYNC | \
+ NETARM_MEM_OPT_WRITE_ASYNC )
+
+ orr r1, r1, r2
+ str r1, [r0, #+NETARM_MEM_CS0_OPTIONS]
+
+
+memsetup_cs1:
+ /*
+ * Base Addr / Option Reg 1 (DRAM #1)
+ * ---------------------------------------------------
+ */
+#ifdef CONFIG_NETARM_NET40_REV2
+ /* we have to config SDRAM in burst mode */
+ ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
+ NETARM_MEM_OPT_BCYC_2 | \
+ NETARM_MEM_OPT_BSIZE_16 | \
+ NETARM_MEM_OPT_WAIT_STATES(0) | \
+ NETARM_MEM_OPT_32BIT | \
+ NETARM_MEM_OPT_READ_ASYNC | \
+ NETARM_MEM_OPT_WRITE_ASYNC )
+ str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
+
+ ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
+ NETARM_MEM_BAR_DRAM_SYNC | \
+ NETARM_MEM_BAR_DRAM_MUX_INT | \
+ NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
+ NETARM_MEM_BAR_DRAM_SEL | \
+ NETARM_MEM_BAR_BURST_EN | \
+ NETARM_MEM_BAR_VALID )
+ str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
+#else
+ /* we have to config FPDRAM in burst mode with smaller burst access size */
+ ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
+ NETARM_MEM_OPT_BCYC_2 | \
+ NETARM_MEM_OPT_BSIZE_16 | \
+ NETARM_MEM_OPT_WAIT_STATES(0) | \
+ NETARM_MEM_OPT_32BIT | \
+ NETARM_MEM_OPT_READ_ASYNC | \
+ NETARM_MEM_OPT_WRITE_ASYNC )
+ str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
+
+ ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
+ NETARM_MEM_BAR_DRAM_SYNC | \
+ NETARM_MEM_BAR_DRAM_MUX_INT | \
+ NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
+ NETARM_MEM_BAR_DRAM_SEL | \
+ NETARM_MEM_BAR_BURST_EN | \
+ NETARM_MEM_BAR_VALID )
+ str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
+
+#endif /* CONFIG_NETARM_NET40_REV2 */
+
+
+memsetup_cs3:
+ /*
+ * Base Addr / Option Reg 3 (EEPROM, NVRAM)
+ * ---------------------------------------------------
+ */
+#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
+ ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS3_MASK) | \
+ NETARM_MEM_OPT_BCYC_3 | \
+ NETARM_MEM_OPT_BSIZE_2 | \
+ NETARM_MEM_OPT_WAIT_STATES(10) | \
+ NETARM_MEM_OPT_8BIT | \
+ NETARM_MEM_OPT_READ_ASYNC | \
+ NETARM_MEM_OPT_WRITE_ASYNC )
+ str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
+
+ ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS3_BASE) | \
+ NETARM_MEM_BAR_DRAM_FP | \
+ NETARM_MEM_BAR_DRAM_MUX_INT | \
+ NETARM_MEM_BAR_DRAM_MUX_BAL | \
+ NETARM_MEM_BAR_VALID )
+ str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
+#else
+ /* we don't need EEPROM --> no config */
+ ldr r1, =( 0 )
+ str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
+
+ ldr r1, =( 0 )
+ str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
+#endif
+
+
+#else
+/*
+#error "missing CONFIG_MODNET50 (see your config.h)"
+*/
+#endif /* CONFIG_MODNET50 */
+
+
+lowlevel_init_end:
+ /*
+ * manipulate address in lr and ip to match new
+ * address space
+ */
+ ldr r3, =(NETARM_MMAP_CS0_BASE)
+ mov r0, lr
+ add r0, r3, r0
+ mov lr, r0
+ mov r0, ip
+ add r0, r3, r0
+ mov ip, r0
+
+ /* everything is fine now */
+ mov pc, lr
+++ /dev/null
-/*
- * Memory Setup stuff - taken from Linux
- *
- * Copyright (c) 2002 Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
- * (c) 2004 IMMS gGmbH <www.imms.de>, Thomas Elste <info@elste.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/netarm_registers.h>
-
-
-/* some parameters for the board */
-#define FLASH_90ns_WAIT_STATES ((NETARM_PLL_COUNT_VAL + 2) / 3)
-#define FLASH_70ns_WAIT_STATES 4
-
-#define NETARM_MMAP_CS0_BASE (PHYS_FLASH_1)
-#if 1
-#define NETARM_MMAP_CS0_MASK (~(PHYS_FLASH_1_SIZE - 1))
-#else
-#define NETARM_MMAP_CS0_MASK (~(1000000 - 1))
-#endif
-#define NETARM_MMAP_CS1_BASE (PHYS_SDRAM_1)
-#define NETARM_MMAP_CS1_MASK (~(PHYS_SDRAM_1_SIZE - 1))
-#define NETARM_MMAP_CS2_BASE (PHYS_SDRAM_2)
-#define NETARM_MMAP_CS2_MASK (~(PHYS_SDRAM_2_SIZE - 1))
-#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
-#define NETARM_MMAP_CS3_BASE (PHYS_NVRAM_1)
-#define NETARM_MMAP_CS3_MASK (~(PHYS_NVRAM_SIZE - 1))
-#endif
-#define NETARM_MMAP_CS4_BASE (PHYS_EXT_1)
-#define NETARM_MMAP_CS4_MASK (~(PHYS_EXT_SIZE - 1))
-
-/* setting up the memory */
-.globl memsetup
-memsetup:
-
-#if defined(CONFIG_MODNET50)
- ldr pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - TEXT_BASE)
-
-_jump_to_high:
- /*
- * MEM Config Reg
- * ---------------------------------------------------
- */
- ldr r0, =NETARM_MEM_MODULE_BASE
- ldr r1, =( NETARM_MEM_REFR_PERIOD_USEC(16) | \
- NETARM_MEM_CFG_REFRESH_EN | \
- NETARM_MEM_CFG_REFR_CYCLE_5CLKS )
- str r1, [r0, #+NETARM_MEM_MODULE_CONFIG]
-
-
-memsetup_cs0:
- /*
- * Base Addr / Option Reg 0 (Flash)
- * ---------------------------------------------------
- */
- ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS0_BASE) | \
- NETARM_MEM_BAR_DRAM_FP | \
- NETARM_MEM_BAR_DRAM_MUX_INT | \
- NETARM_MEM_BAR_DRAM_MUX_BAL | \
- NETARM_MEM_BAR_VALID )
- str r1, [r0, #+NETARM_MEM_CS0_BASE_ADDR]
-
- /* trust that the bus size for flash was strapped correctly */
- /* this saves the bus width in r2 and then ORs it back in */
- /* it's pretty safe assumption, otherwise it wouldn't boot */
- ldr r2, [r0, #+NETARM_MEM_CS0_OPTIONS]
- and r2, r2, #NETARM_MEM_OPT_BUS_SIZE_MASK
-
-/* just a test: assume 32 bit flash mem */
-/* mov r2, #NETARM_MEM_OPT_32BIT */
-
- ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS0_MASK) | \
- NETARM_MEM_OPT_WAIT_STATES(FLASH_70ns_WAIT_STATES) | \
- NETARM_MEM_OPT_BCYC_4 | \
- NETARM_MEM_OPT_BSIZE_16 | \
- NETARM_MEM_OPT_16BIT | \
- NETARM_MEM_OPT_READ_ASYNC | \
- NETARM_MEM_OPT_WRITE_ASYNC )
-
- orr r1, r1, r2
- str r1, [r0, #+NETARM_MEM_CS0_OPTIONS]
-
-
-memsetup_cs1:
- /*
- * Base Addr / Option Reg 1 (DRAM #1)
- * ---------------------------------------------------
- */
-#ifdef CONFIG_NETARM_NET40_REV2
- /* we have to config SDRAM in burst mode */
- ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
- NETARM_MEM_OPT_BCYC_2 | \
- NETARM_MEM_OPT_BSIZE_16 | \
- NETARM_MEM_OPT_WAIT_STATES(0) | \
- NETARM_MEM_OPT_32BIT | \
- NETARM_MEM_OPT_READ_ASYNC | \
- NETARM_MEM_OPT_WRITE_ASYNC )
- str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
-
- ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
- NETARM_MEM_BAR_DRAM_SYNC | \
- NETARM_MEM_BAR_DRAM_MUX_INT | \
- NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
- NETARM_MEM_BAR_DRAM_SEL | \
- NETARM_MEM_BAR_BURST_EN | \
- NETARM_MEM_BAR_VALID )
- str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
-#else
- /* we have to config FPDRAM in burst mode with smaller burst access size */
- ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
- NETARM_MEM_OPT_BCYC_2 | \
- NETARM_MEM_OPT_BSIZE_16 | \
- NETARM_MEM_OPT_WAIT_STATES(0) | \
- NETARM_MEM_OPT_32BIT | \
- NETARM_MEM_OPT_READ_ASYNC | \
- NETARM_MEM_OPT_WRITE_ASYNC )
- str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
-
- ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
- NETARM_MEM_BAR_DRAM_SYNC | \
- NETARM_MEM_BAR_DRAM_MUX_INT | \
- NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
- NETARM_MEM_BAR_DRAM_SEL | \
- NETARM_MEM_BAR_BURST_EN | \
- NETARM_MEM_BAR_VALID )
- str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
-
-#endif /* CONFIG_NETARM_NET40_REV2 */
-
-
-memsetup_cs3:
- /*
- * Base Addr / Option Reg 3 (EEPROM, NVRAM)
- * ---------------------------------------------------
- */
-#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
- ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS3_MASK) | \
- NETARM_MEM_OPT_BCYC_3 | \
- NETARM_MEM_OPT_BSIZE_2 | \
- NETARM_MEM_OPT_WAIT_STATES(10) | \
- NETARM_MEM_OPT_8BIT | \
- NETARM_MEM_OPT_READ_ASYNC | \
- NETARM_MEM_OPT_WRITE_ASYNC )
- str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
-
- ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS3_BASE) | \
- NETARM_MEM_BAR_DRAM_FP | \
- NETARM_MEM_BAR_DRAM_MUX_INT | \
- NETARM_MEM_BAR_DRAM_MUX_BAL | \
- NETARM_MEM_BAR_VALID )
- str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
-#else
- /* we don't need EEPROM --> no config */
- ldr r1, =( 0 )
- str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
-
- ldr r1, =( 0 )
- str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
-#endif
-
-
-#else
-/*
-#error "missing CONFIG_MODNET50 (see your config.h)"
-*/
-#endif /* CONFIG_MODNET50 */
-
-
-memsetup_end:
- /*
- * manipulate address in lr and ip to match new
- * address space
- */
- ldr r3, =(NETARM_MMAP_CS0_BASE)
- mov r0, lr
- add r0, r3, r0
- mov lr, r0
- mov r0, ip
- add r0, r3, r0
- mov ip, r0
-
- /* everything is fine now */
- mov pc, lr
OBJS := vcma9.o flash.o cmd_vcma9.o
OBJS += ../common/common_util.o ../common/memtst.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+#define BWSCON 0x48000000
+#define PLD_BASE 0x2C000000
+#define SDRAM_REG 0x2C000106
+
+/* BWSCON */
+#define DW8 (0x0)
+#define DW16 (0x1)
+#define DW32 (0x2)
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+/* BANKSIZE */
+#define BURST_EN (0x1<<7)
+
+#define B1_BWSCON (DW16)
+#define B2_BWSCON (DW32)
+#define B3_BWSCON (DW32)
+#define B4_BWSCON (DW16 + WAIT + UBLB)
+#define B5_BWSCON (DW8 + UBLB)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/* BANK0CON */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x1 /* 1clk */
+/*#define B0_Tcos 0x0 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+/*#define B0_Tacc 0x5 8clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0 /* page mode is not used */
+#define B0_PMC 0x0 /* page mode disabled */
+
+/* BANK1CON */
+#define B1_Tacs 0x0 /* 0clk */
+#define B1_Tcos 0x1 /* 1clk */
+/*#define B1_Tcos 0x0 0clk */
+#define B1_Tacc 0x7 /* 14clk */
+/*#define B1_Tacc 0x5 8clk */
+#define B1_Tcoh 0x0 /* 0clk */
+#define B1_Tah 0x0 /* 0clk */
+#define B1_Tacp 0x0 /* page mode is not used */
+#define B1_PMC 0x0 /* page mode disabled */
+
+#define B2_Tacs 0x3 /* 4clk */
+#define B2_Tcos 0x3 /* 4clk */
+#define B2_Tacc 0x7 /* 14clk */
+#define B2_Tcoh 0x3 /* 4clk */
+#define B2_Tah 0x3 /* 4clk */
+#define B2_Tacp 0x0 /* page mode is not used */
+#define B2_PMC 0x0 /* page mode disabled */
+
+#define B3_Tacs 0x3 /* 4clk */
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7 /* 14clk */
+#define B3_Tcoh 0x3 /* 4clk */
+#define B3_Tah 0x3 /* 4clk */
+#define B3_Tacp 0x0 /* page mode is not used */
+#define B3_PMC 0x0 /* page mode disabled */
+
+#define B4_Tacs 0x3 /* 4clk */
+#define B4_Tcos 0x1 /* 1clk */
+#define B4_Tacc 0x7 /* 14clk */
+#define B4_Tcoh 0x1 /* 1clk */
+#define B4_Tah 0x0 /* 0clk */
+#define B4_Tacp 0x0 /* page mode is not used */
+#define B4_PMC 0x0 /* page mode disabled */
+
+#define B5_Tacs 0x0 /* 0clk */
+#define B5_Tcos 0x3 /* 4clk */
+#define B5_Tacc 0x5 /* 8clk */
+#define B5_Tcoh 0x2 /* 2clk */
+#define B5_Tah 0x1 /* 1clk */
+#define B5_Tacp 0x0 /* page mode is not used */
+#define B5_PMC 0x0 /* page mode disabled */
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1 /* 3clk */
+#define B6_SCAN 0x2 /* 10bit */
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 3clk */
+#define B7_SCAN 0x2 /* 10bit */
+
+/* REFRESH parameter */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x0 /* 2clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x2 /* 3clk */
+#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+ ldr r0, =CSDATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add r2, r0, #CSDATA_END-CSDATA
+0:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r2, r0
+ bne 0b
+
+ /* PLD access is now possible */
+ /* r0 == SDRAMDATA */
+ /* r1 == SDRAM controller regs */
+ ldr r2, =PLD_BASE
+ ldrb r3, [r2, #SDRAM_REG-PLD_BASE]
+ mov r4, #SDRAMDATA1_END-SDRAMDATA
+ /* calculate start and end point */
+ mla r0, r3, r4, r0
+ add r2, r0, r4
+0:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r2, r0
+ bne 0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+CSDATA:
+ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+CSDATA_END:
+
+SDRAMDATA:
+/* 4Mx8x4 */
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+SDRAMDATA1_END:
+
+/* 8Mx8x4 (not implemented yet) */
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+
+/* 2Mx8x4 (not implemented yet) */
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+
+/* 4Mx8x2 (not implemented yet) */
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the Samsung SMDK2410 by
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-
-/* some parameters for the board */
-
-#define BWSCON 0x48000000
-#define PLD_BASE 0x2C000000
-#define SDRAM_REG 0x2C000106
-
-/* BWSCON */
-#define DW8 (0x0)
-#define DW16 (0x1)
-#define DW32 (0x2)
-#define WAIT (0x1<<2)
-#define UBLB (0x1<<3)
-
-/* BANKSIZE */
-#define BURST_EN (0x1<<7)
-
-#define B1_BWSCON (DW16)
-#define B2_BWSCON (DW32)
-#define B3_BWSCON (DW32)
-#define B4_BWSCON (DW16 + WAIT + UBLB)
-#define B5_BWSCON (DW8 + UBLB)
-#define B6_BWSCON (DW32)
-#define B7_BWSCON (DW32)
-
-/* BANK0CON */
-#define B0_Tacs 0x0 /* 0clk */
-#define B0_Tcos 0x1 /* 1clk */
-/*#define B0_Tcos 0x0 0clk */
-#define B0_Tacc 0x7 /* 14clk */
-/*#define B0_Tacc 0x5 8clk */
-#define B0_Tcoh 0x0 /* 0clk */
-#define B0_Tah 0x0 /* 0clk */
-#define B0_Tacp 0x0 /* page mode is not used */
-#define B0_PMC 0x0 /* page mode disabled */
-
-/* BANK1CON */
-#define B1_Tacs 0x0 /* 0clk */
-#define B1_Tcos 0x1 /* 1clk */
-/*#define B1_Tcos 0x0 0clk */
-#define B1_Tacc 0x7 /* 14clk */
-/*#define B1_Tacc 0x5 8clk */
-#define B1_Tcoh 0x0 /* 0clk */
-#define B1_Tah 0x0 /* 0clk */
-#define B1_Tacp 0x0 /* page mode is not used */
-#define B1_PMC 0x0 /* page mode disabled */
-
-#define B2_Tacs 0x3 /* 4clk */
-#define B2_Tcos 0x3 /* 4clk */
-#define B2_Tacc 0x7 /* 14clk */
-#define B2_Tcoh 0x3 /* 4clk */
-#define B2_Tah 0x3 /* 4clk */
-#define B2_Tacp 0x0 /* page mode is not used */
-#define B2_PMC 0x0 /* page mode disabled */
-
-#define B3_Tacs 0x3 /* 4clk */
-#define B3_Tcos 0x3 /* 4clk */
-#define B3_Tacc 0x7 /* 14clk */
-#define B3_Tcoh 0x3 /* 4clk */
-#define B3_Tah 0x3 /* 4clk */
-#define B3_Tacp 0x0 /* page mode is not used */
-#define B3_PMC 0x0 /* page mode disabled */
-
-#define B4_Tacs 0x3 /* 4clk */
-#define B4_Tcos 0x1 /* 1clk */
-#define B4_Tacc 0x7 /* 14clk */
-#define B4_Tcoh 0x1 /* 1clk */
-#define B4_Tah 0x0 /* 0clk */
-#define B4_Tacp 0x0 /* page mode is not used */
-#define B4_PMC 0x0 /* page mode disabled */
-
-#define B5_Tacs 0x0 /* 0clk */
-#define B5_Tcos 0x3 /* 4clk */
-#define B5_Tacc 0x5 /* 8clk */
-#define B5_Tcoh 0x2 /* 2clk */
-#define B5_Tah 0x1 /* 1clk */
-#define B5_Tacp 0x0 /* page mode is not used */
-#define B5_PMC 0x0 /* page mode disabled */
-
-#define B6_MT 0x3 /* SDRAM */
-#define B6_Trcd 0x1 /* 3clk */
-#define B6_SCAN 0x2 /* 10bit */
-
-#define B7_MT 0x3 /* SDRAM */
-#define B7_Trcd 0x1 /* 3clk */
-#define B7_SCAN 0x2 /* 10bit */
-
-/* REFRESH parameter */
-#define REFEN 0x1 /* Refresh enable */
-#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
-#define Trp 0x0 /* 2clk */
-#define Trc 0x3 /* 7clk */
-#define Tchr 0x2 /* 3clk */
-#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
-/**************************************/
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-.globl memsetup
-memsetup:
- /* memory control configuration */
- /* make r0 relative the current location so that it */
- /* reads SMRDATA out of FLASH rather than memory ! */
- ldr r0, =CSDATA
- ldr r1, _TEXT_BASE
- sub r0, r0, r1
- ldr r1, =BWSCON /* Bus Width Status Controller */
- add r2, r0, #CSDATA_END-CSDATA
-0:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r2, r0
- bne 0b
-
- /* PLD access is now possible */
- /* r0 == SDRAMDATA */
- /* r1 == SDRAM controller regs */
- ldr r2, =PLD_BASE
- ldrb r3, [r2, #SDRAM_REG-PLD_BASE]
- mov r4, #SDRAMDATA1_END-SDRAMDATA
- /* calculate start and end point */
- mla r0, r3, r4, r0
- add r2, r0, r4
-0:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r2, r0
- bne 0b
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-/* the literal pools origin */
-
-CSDATA:
- .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
- .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
- .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
- .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
- .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
- .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
- .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
-CSDATA_END:
-
-SDRAMDATA:
-/* 4Mx8x4 */
- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-SDRAMDATA1_END:
-
-/* 8Mx8x4 (not implemented yet) */
- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
-/* 2Mx8x4 (not implemented yet) */
- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
-/* 4Mx8x2 (not implemented yet) */
- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
LIB = lib$(BOARD).a
OBJS := mx1ads.o syncflash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * board/mx1ads/lowlevel_init.S
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#define SDCTL0 0x221000
+#define SDCTL1 0x221004
+
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+/* memory controller init */
+
+ ldr r1, =SDCTL0
+
+/* Set Precharge Command */
+
+ ldr r3, =0x92120200
+/* ldr r3, =0x92120251
+*/
+ str r3, [r1]
+
+/* Issue Precharge All Commad */
+ ldr r3, =0x8200000
+ ldr r2, [r3]
+
+/* Set AutoRefresh Command */
+ ldr r3, =0xA2120200
+ str r3, [r1]
+
+/* Issue AutoRefresh Command */
+ ldr r3, =0x8000000
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+ ldr r2, [r3]
+
+/* Set Mode Register */
+ ldr r3, =0xB2120200
+ str r3, [r1]
+
+/* Issue Mode Register Command */
+ ldr r3, =0x08111800 /* Mode Register Value */
+ ldr r2, [r3]
+
+/* Set Normal Mode */
+ ldr r3, =0x82124200
+ str r3, [r1]
+
+/* everything is fine now */
+ mov pc, lr
+++ /dev/null
-/*
- * board/mx1ads/memsetup.S
- *
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * http://www.techware.com.tw/
- *
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#define SDCTL0 0x221000
-#define SDCTL1 0x221004
-
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-.globl memsetup
-memsetup:
-/* memory controller init */
-
- ldr r1, =SDCTL0
-
-/* Set Precharge Command */
-
- ldr r3, =0x92120200
-/* ldr r3, =0x92120251
-*/
- str r3, [r1]
-
-/* Issue Precharge All Commad */
- ldr r3, =0x8200000
- ldr r2, [r3]
-
-/* Set AutoRefresh Command */
- ldr r3, =0xA2120200
- str r3, [r1]
-
-/* Issue AutoRefresh Command */
- ldr r3, =0x8000000
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
- ldr r2, [r3]
-
-/* Set Mode Register */
- ldr r3, =0xB2120200
- str r3, [r1]
-
-/* Issue Mode Register Command */
- ldr r3, =0x08111800 /* Mode Register Value */
- ldr r2, [r3]
-
-/* Set Normal Mode */
- ldr r3, =0x82124200
- str r3, [r1]
-
-/* everything is fine now */
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := mx1fs2.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
--- /dev/null
+/*
+ * Copyright (C) 2004 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+/* Change PERCLK1DIV to 14 ie 14+1 */
+ ldr r0, =PCDR
+ ldr r1, =CFG_PCDR_VAL
+ str r1, [r0]
+
+/* set MCU PLL Control Register 0 */
+
+ ldr r0, =MPCTL0
+ ldr r1, =CFG_MPCTL0_VAL
+ str r1, [r0]
+
+/* set MCU PLL Control Register 1 */
+
+ ldr r0, =MPCTL1
+ ldr r1, =CFG_MPCTL1_VAL
+ str r1, [r0]
+
+/* set mpll restart bit */
+ ldr r0, =CSCR
+ ldr r1, [r0]
+ orr r1,r1,#(1<<21)
+ str r1, [r0]
+
+ mov r2,#0x10
+1:
+ mov r3,#0x2000
+2:
+ subs r3,r3,#1
+ bne 2b
+
+ subs r2,r2,#1
+ bne 1b
+
+/* set System PLL Control Register 0 */
+
+ ldr r0, =SPCTL0
+ ldr r1, =CFG_SPCTL0_VAL
+ str r1, [r0]
+
+/* set System PLL Control Register 1 */
+
+ ldr r0, =SPCTL1
+ ldr r1, =CFG_SPCTL1_VAL
+ str r1, [r0]
+
+/* set spll restart bit */
+ ldr r0, =CSCR
+ ldr r1, [r0]
+ orr r1,r1,#(1<<22)
+ str r1, [r0]
+
+ mov r2,#0x10
+1:
+ mov r3,#0x2000
+2:
+ subs r3,r3,#1
+ bne 2b
+
+ subs r2,r2,#1
+ bne 1b
+
+ ldr r0, =CSCR
+ ldr r1, =CFG_CSCR_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR
+ ldr r1, =CFG_GPCR_VAL
+ str r1, [r0]
+
+/*
+ * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
+ * this.....
+ *
+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
+ * register 1, this stops it using the output of the PLL and thus runs at the
+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
+ * use the value set in the CM_OSC registers...regardless of what you set it
+ * too! Thus, although i thought i was running at 140MHz, i'm actually running
+ * at 40!..
+ *
+ * Slapping this into my bootloader does the trick...
+ *
+ * MRC p15,0,r0,c1,c0,0 ; read core configuration register
+ * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
+ * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
+ * register
+ *
+ */
+ MRC p15,0,r0,c1,c0,0
+/* ORR r0,r0,#0xC0000000 async mode */
+/* ORR r0,r0,#0x40000000 sync mode */
+ ORR r0,r0,#0xC0000000
+ MCR p15,0,r0,c1,c0,0
+
+ ldr r0, =GIUS(0)
+ ldr r1, =CFG_GIUS_A_VAL
+ str r1, [r0]
+
+ ldr r0, =FMCR
+ ldr r1, =CFG_FMCR_VAL
+ str r1, [r0]
+
+ ldr r0, =CS0U
+ ldr r1, =CFG_CS0U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS0L
+ ldr r1, =CFG_CS0L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS1U
+ ldr r1, =CFG_CS1U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS1L
+ ldr r1, =CFG_CS1L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS4U
+ ldr r1, =CFG_CS4U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS4L
+ ldr r1, =CFG_CS4L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS5U
+ ldr r1, =CFG_CS5U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS5L
+ ldr r1, =CFG_CS5L_VAL
+ str r1, [r0]
+
+/* SDRAM Setup */
+
+ ldr r1,=0x00221000 /* adr of SDCTRL0 */
+ ldr r0,=0x92120200
+ str r0,[r1,#0] /* put in precharge command mode */
+ ldr r2,=0x08200000 /* adr for precharge cmd */
+ ldr r0,[r2,#0] /* precharge */
+ ldr r0,=0xA2120200
+ ldr r2,=0x08000000 /* start of SDRAM */
+ str r0,[r1,#0] /* put in auto-refresh mode */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,=0xB2120200
+ ldr r2,=0x08111800
+ str r0,[r1,#0] /* setup for mode register of SDRAM */
+ ldr r0,[r2,#0] /* program mode register */
+ ldr r0,=0x82124267
+ str r0,[r1,#0] /* back to normal operation */
+
+ mov pc,r10
+++ /dev/null
-/*
- * Copyright (C) 2004 Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- * 02111-1307, USA.
- *
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/imx-regs.h>
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
-/* Change PERCLK1DIV to 14 ie 14+1 */
- ldr r0, =PCDR
- ldr r1, =CFG_PCDR_VAL
- str r1, [r0]
-
-/* set MCU PLL Control Register 0 */
-
- ldr r0, =MPCTL0
- ldr r1, =CFG_MPCTL0_VAL
- str r1, [r0]
-
-/* set MCU PLL Control Register 1 */
-
- ldr r0, =MPCTL1
- ldr r1, =CFG_MPCTL1_VAL
- str r1, [r0]
-
-/* set mpll restart bit */
- ldr r0, =CSCR
- ldr r1, [r0]
- orr r1,r1,#(1<<21)
- str r1, [r0]
-
- mov r2,#0x10
-1:
- mov r3,#0x2000
-2:
- subs r3,r3,#1
- bne 2b
-
- subs r2,r2,#1
- bne 1b
-
-/* set System PLL Control Register 0 */
-
- ldr r0, =SPCTL0
- ldr r1, =CFG_SPCTL0_VAL
- str r1, [r0]
-
-/* set System PLL Control Register 1 */
-
- ldr r0, =SPCTL1
- ldr r1, =CFG_SPCTL1_VAL
- str r1, [r0]
-
-/* set spll restart bit */
- ldr r0, =CSCR
- ldr r1, [r0]
- orr r1,r1,#(1<<22)
- str r1, [r0]
-
- mov r2,#0x10
-1:
- mov r3,#0x2000
-2:
- subs r3,r3,#1
- bne 2b
-
- subs r2,r2,#1
- bne 1b
-
- ldr r0, =CSCR
- ldr r1, =CFG_CSCR_VAL
- str r1, [r0]
-
- ldr r0, =GPCR
- ldr r1, =CFG_GPCR_VAL
- str r1, [r0]
-
-/*
- * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
- * this.....
- *
- * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
- * register 1, this stops it using the output of the PLL and thus runs at the
- * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
- * use the value set in the CM_OSC registers...regardless of what you set it
- * too! Thus, although i thought i was running at 140MHz, i'm actually running
- * at 40!..
- *
- * Slapping this into my bootloader does the trick...
- *
- * MRC p15,0,r0,c1,c0,0 ; read core configuration register
- * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
- * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
- * register
- *
- */
- MRC p15,0,r0,c1,c0,0
-/* ORR r0,r0,#0xC0000000 async mode */
-/* ORR r0,r0,#0x40000000 sync mode */
- ORR r0,r0,#0xC0000000
- MCR p15,0,r0,c1,c0,0
-
- ldr r0, =GIUS(0)
- ldr r1, =CFG_GIUS_A_VAL
- str r1, [r0]
-
- ldr r0, =FMCR
- ldr r1, =CFG_FMCR_VAL
- str r1, [r0]
-
- ldr r0, =CS0U
- ldr r1, =CFG_CS0U_VAL
- str r1, [r0]
-
- ldr r0, =CS0L
- ldr r1, =CFG_CS0L_VAL
- str r1, [r0]
-
- ldr r0, =CS1U
- ldr r1, =CFG_CS1U_VAL
- str r1, [r0]
-
- ldr r0, =CS1L
- ldr r1, =CFG_CS1L_VAL
- str r1, [r0]
-
- ldr r0, =CS4U
- ldr r1, =CFG_CS4U_VAL
- str r1, [r0]
-
- ldr r0, =CS4L
- ldr r1, =CFG_CS4L_VAL
- str r1, [r0]
-
- ldr r0, =CS5U
- ldr r1, =CFG_CS5U_VAL
- str r1, [r0]
-
- ldr r0, =CS5L
- ldr r1, =CFG_CS5L_VAL
- str r1, [r0]
-
-/* SDRAM Setup */
-
- ldr r1,=0x00221000 /* adr of SDCTRL0 */
- ldr r0,=0x92120200
- str r0,[r1,#0] /* put in precharge command mode */
- ldr r2,=0x08200000 /* adr for precharge cmd */
- ldr r0,[r2,#0] /* precharge */
- ldr r0,=0xA2120200
- ldr r2,=0x08000000 /* start of SDRAM */
- str r0,[r1,#0] /* put in auto-refresh mode */
- ldr r0,[r2,#0] /* auto-refresh */
- ldr r0,[r2,#0] /* auto-refresh */
- ldr r0,[r2,#0] /* auto-refresh */
- ldr r0,[r2,#0] /* auto-refresh */
- ldr r0,[r2,#0] /* auto-refresh */
- ldr r0,[r2,#0] /* auto-refresh */
- ldr r0,[r2,#0] /* auto-refresh */
- ldr r0,=0xB2120200
- ldr r2,=0x08111800
- str r0,[r1,#0] /* setup for mode register of SDRAM */
- ldr r0,[r2,#0] /* program mode register */
- ldr r0,=0x82124267
- str r0,[r1,#0] /* back to normal operation */
-
- mov pc,r10
LIB = lib$(BOARD).a
OBJS := pleb2.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+ /* Set up GPIO pins first */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER0
+ ldr r1, =CFG_GRER0_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER1
+ ldr r1, =CFG_GRER1_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER2
+ ldr r1, =CFG_GRER2_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER0
+ ldr r1, =CFG_GFER0_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER1
+ ldr r1, =CFG_GFER1_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER2
+ ldr r1, =CFG_GFER2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ /* enable GPIO pins */
+ ldr r0, =PSSR
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+
+/*********************************************************************
+ Initlialize Memory Controller
+
+ See PXA250 Operating System Developer's Guide
+
+ pause for 200 uSecs- allow internal clocks to settle
+ *Note: only need this if hard reset... doing it anyway for now
+*/
+
+ @ Step 1
+ @ ---- Wait 200 usec
+ ldr r3, =OSCR @ reset the OS Timer Count to zero
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+ @ get memory controller base address
+ ldr r1, =MEMC_BASE
+
+@****************************************************************************
+@ Step 2
+@
+
+ @ Step 2a
+ @ write msc0, read back to ensure data latches
+ @
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET]
+
+ @ write msc1
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ @ write msc2
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+
+@ Step 2b
+ @ write mecr
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+
+ @ write mcmem0
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+
+ @ write mcmem1
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+
+ @ write mcatt0
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+
+ @ write mcatt1
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+
+ @ write mcio0
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+
+ @ write mcio1
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+
+@ Step 2c
+ @ fly-by-dma is defeatured on this part
+ @ write flycnfg
+ @ldr r2, =CFG_FLYCNFG_VAL
+ @str r2, [r1, #FLYCNFG_OFFSET]
+
+/* FIXME Does this sequence really make sense */
+#ifdef REDBOOT_WAY
+ @ Step 2d
+ @ get the mdrefr settings
+ ldr r3, =CFG_MDREFR_VAL
+
+ @ extract DRI field (we need a valid DRI field)
+ @
+ ldr r2, =0xFFF
+
+ @ valid DRI field in r3
+ @
+ and r3, r3, r2
+
+ @ get the reset state of MDREFR
+ @
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ clear the DRI field
+ @
+ bic r4, r4, r2
+
+ @ insert the valid DRI field loaded above
+ @
+ orr r4, r4, r3
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ *Note: preserve the mdrefr value in r4 *
+
+@****************************************************************************
+@ Step 3
+@
+@ NO SRAM
+
+ mov pc, r10
+
+
+@****************************************************************************
+@ Step 4
+@
+
+ @ Assumes previous mdrefr value in r4, if not then read current mdrefr
+
+ @ clear the free-running clock bits
+ @ (clear K0Free, K1Free, K2Free
+ @
+ bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
+
+ @ set K0RUN for CPLD clock
+ @
+ orr r4, r4, #0x00002000
+
+ @ set K1RUN if bank 0 installed
+ @
+ orr r4, r4, #0x00010000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ deassert SLFRSH
+ @
+ bic r4, r4, #0x00400000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ assert E1PIN
+ @
+ orr r4, r4, #0x00008000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+ nop
+ nop
+#else
+ @ Step 2d
+ @ get the mdrefr settings
+ ldr r3, =CFG_MDREFR_VAL
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ Step 4
+
+ @ set K0RUN for CPLD clock
+ @
+ orr r4, r4, #0x00002000
+
+ @ set K1RUN for bank 0
+ @
+ orr r4, r4, #0x00010000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ deassert SLFRSH
+ @
+ bic r4, r4, #0x00400000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ assert E1PIN
+ @
+ orr r4, r4, #0x00008000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+ nop
+ nop
+#endif
+
+ @ Step 4d
+ @ fetch platform value of mdcnfg
+ @
+ ldr r2, =CFG_MDCNFG_VAL
+
+ @ disable all sdram banks
+ @
+ bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
+ bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
+
+ @ program banks 0/1 for bus width
+ @
+ bic r2, r2, #MDCNFG_DWID0 @0=32-bit
+
+ @ write initial value of mdcnfg, w/o enabling sdram banks
+ @
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ @ Step 4e
+ @ pause for 200 uSecs
+ @
+ ldr r3, =OSCR @ reset the OS Timer Count to zero
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
+ 1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+ /* Why is this here??? */
+ mov r0, #0x78 @turn everything off
+ mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
+
+ @ Step 4f
+ @ Access memory *not yet enabled* for CBR refresh cycles (8)
+ @ - CBR is generated for all banks
+
+ ldr r2, =CFG_DRAM_BASE
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+
+ @ Step 4g
+ @get memory controller base address
+ @
+ ldr r1, =MEMC_BASE
+
+ @fetch current mdcnfg value
+ @
+ ldr r3, [r1, #MDCNFG_OFFSET]
+
+ @enable sdram bank 0 if installed (must do for any populated bank)
+ @
+ orr r3, r3, #MDCNFG_DE0
+
+ @write back mdcnfg, enabling the sdram bank(s)
+ @
+ str r3, [r1, #MDCNFG_OFFSET]
+
+ @ Step 4h
+ @ write mdmrs
+ @
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+ @ Done Memory Init
+
+ /*SET_LED 6 */
+
+ @********************************************************************
+ @ Disable (mask) all interrupts at the interrupt controller
+ @
+
+ @ clear the interrupt level register (use IRQ, not FIQ)
+ @
+ mov r1, #0
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ @ Set interrupt mask register
+ @
+ ldr r1, =CFG_ICMR_VAL
+ ldr r2, =ICMR
+ str r1, [r2]
+
+ @ ********************************************************************
+ @ Disable the peripheral clocks, and set the core clock
+ @
+
+ @ Turn Off ALL on-chip peripheral clocks for re-configuration
+ @
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+ @ set core clocks
+ @
+ ldr r2, =CFG_CCCR_VAL
+ ldr r1, =CCCR
+ str r2, [r1]
+
+ #ifdef ENABLE32KHZ
+ @ enable the 32Khz oscillator for RTC and PowerManager
+ @
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ @ NOTE: spin here until OSCC.OOK get set,
+ @ meaning the PLL has settled.
+ @
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+#endif
+
+ @ Turn on needed clocks
+ @
+ ldr r1, =CKEN
+ ldr r2, =CFG_CKEN_VAL
+ str r2, [r1]
+
+ /*SET_LED 7 */
+
+/* Is this needed???? */
+#define NODEBUG
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
+#endif
+
+ mov pc, r10
+
+@ End lowlevel_init
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CFG_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
- /* Set up GPIO pins first */
-
- ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GRER0
- ldr r1, =CFG_GRER0_VAL
- str r1, [r0]
-
- ldr r0, =GRER1
- ldr r1, =CFG_GRER1_VAL
- str r1, [r0]
-
- ldr r0, =GRER2
- ldr r1, =CFG_GRER2_VAL
- str r1, [r0]
-
- ldr r0, =GFER0
- ldr r1, =CFG_GFER0_VAL
- str r1, [r0]
-
- ldr r0, =GFER1
- ldr r1, =CFG_GFER1_VAL
- str r1, [r0]
-
- ldr r0, =GFER2
- ldr r1, =CFG_GFER2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CFG_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CFG_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CFG_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CFG_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CFG_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CFG_GAFR2_U_VAL
- str r1, [r0]
-
- /* enable GPIO pins */
- ldr r0, =PSSR
- ldr r1, =CFG_PSSR_VAL
- str r1, [r0]
-
-
-/*********************************************************************
- Initlialize Memory Controller
-
- See PXA250 Operating System Developer's Guide
-
- pause for 200 uSecs- allow internal clocks to settle
- *Note: only need this if hard reset... doing it anyway for now
-*/
-
- @ Step 1
- @ ---- Wait 200 usec
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
- @ get memory controller base address
- ldr r1, =MEMC_BASE
-
-@****************************************************************************
-@ Step 2
-@
-
- @ Step 2a
- @ write msc0, read back to ensure data latches
- @
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
- @ write msc1
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- @ write msc2
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
-
-@ Step 2b
- @ write mecr
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
-
- @ write mcmem0
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
-
- @ write mcmem1
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
-
- @ write mcatt0
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
-
- @ write mcatt1
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
-
- @ write mcio0
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
-
- @ write mcio1
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
-
-@ Step 2c
- @ fly-by-dma is defeatured on this part
- @ write flycnfg
- @ldr r2, =CFG_FLYCNFG_VAL
- @str r2, [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CFG_MDREFR_VAL
-
- @ extract DRI field (we need a valid DRI field)
- @
- ldr r2, =0xFFF
-
- @ valid DRI field in r3
- @
- and r3, r3, r2
-
- @ get the reset state of MDREFR
- @
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ clear the DRI field
- @
- bic r4, r4, r2
-
- @ insert the valid DRI field loaded above
- @
- orr r4, r4, r3
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ *Note: preserve the mdrefr value in r4 *
-
-@****************************************************************************
-@ Step 3
-@
-@ NO SRAM
-
- mov pc, r10
-
-
-@****************************************************************************
-@ Step 4
-@
-
- @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
- @ clear the free-running clock bits
- @ (clear K0Free, K1Free, K2Free
- @
- bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN if bank 0 installed
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#else
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CFG_MDREFR_VAL
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ Step 4
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN for bank 0
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#endif
-
- @ Step 4d
- @ fetch platform value of mdcnfg
- @
- ldr r2, =CFG_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- @ Step 4e
- @ pause for 200 uSecs
- @
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
- 1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /* Why is this here??? */
- mov r0, #0x78 @turn everything off
- mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
-
- @ Step 4f
- @ Access memory *not yet enabled* for CBR refresh cycles (8)
- @ - CBR is generated for all banks
-
- ldr r2, =CFG_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
- @ Step 4g
- @get memory controller base address
- @
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- @ Step 4h
- @ write mdmrs
- @
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- @ Done Memory Init
-
- /*SET_LED 6 */
-
- @********************************************************************
- @ Disable (mask) all interrupts at the interrupt controller
- @
-
- @ clear the interrupt level register (use IRQ, not FIQ)
- @
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
- @ Set interrupt mask register
- @
- ldr r1, =CFG_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
- @ ********************************************************************
- @ Disable the peripheral clocks, and set the core clock
- @
-
- @ Turn Off ALL on-chip peripheral clocks for re-configuration
- @
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
- @ set core clocks
- @
- ldr r2, =CFG_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
- #ifdef ENABLE32KHZ
- @ enable the 32Khz oscillator for RTC and PowerManager
- @
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- @ NOTE: spin here until OSCC.OOK get set,
- @ meaning the PLL has settled.
- @
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
- ldr r1, =CKEN
- ldr r2, =CFG_CKEN_VAL
- str r2, [r1]
-
- /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- mov pc, r10
-
-@ End memsetup
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o sconsole.o
-SOBJS = memsetup.o
+SOBJS = lowlevel_init.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
--- /dev/null
+/*
+ * Memory sub-system initialization code for PURPLE development board.
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+#define MC_IOGP 0xBF800800
+
+ .globl lowlevel_init
+lowlevel_init:
+ li t0, MC_IOGP
+ li t1, 0xf24
+ sw t1, 0(t0)
+ j ra
+ nop
+++ /dev/null
-/*
- * Memory sub-system initialization code for PURPLE development board.
- *
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-#define MC_IOGP 0xBF800800
-
- .globl memsetup
-memsetup:
- li t0, MC_IOGP
- li t1, 0xf24
- sw t1, 0(t0)
- j ra
- nop
.text :
{
cpu/mips/start.o (.text)
- board/purple/memsetup.o (.text)
+ board/purple/lowlevel_init.o (.text)
cpu/mips/cache.o (.text)
common/main.o (.text)
common/dlmalloc.o (.text)
LIB = lib$(BOARD).a
OBJS := scb9328.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
--- /dev/null
+/*
+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+/* Change PERCLK1DIV to 14 ie 14+1 */
+ ldr r0, =PCDR
+ ldr r1, =CFG_PCDR_VAL
+ str r1, [r0]
+
+/* set MCU PLL Control Register 0 */
+
+ ldr r0, =MPCTL0
+ ldr r1, =CFG_MPCTL0_VAL
+ str r1, [r0]
+
+/* set mpll restart bit */
+ ldr r0, =CSCR
+ ldr r1, [r0]
+ orr r1,r1,#(1<<21)
+ str r1, [r0]
+
+ mov r2,#0x10
+1:
+ mov r3,#0x2000
+2:
+ subs r3,r3,#1
+ bne 2b
+
+ subs r2,r2,#1
+ bne 1b
+
+/* set System PLL Control Register 0 */
+
+ ldr r0, =SPCTL0
+ ldr r1, =CFG_SPCTL0_VAL
+ str r1, [r0]
+
+/* set spll restart bit */
+ ldr r0, =CSCR
+ ldr r1, [r0]
+ orr r1,r1,#(1<<22)
+ str r1, [r0]
+
+ mov r2,#0x10
+1:
+ mov r3,#0x2000
+2:
+ subs r3,r3,#1
+ bne 2b
+
+ subs r2,r2,#1
+ bne 1b
+
+ ldr r0, =CSCR
+ ldr r1, =CFG_CSCR_VAL
+ str r1, [r0]
+
+/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
+ *this.....
+ *
+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
+ * register 1, this stops it using the output of the PLL and thus runs at the
+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
+ * use the value set in the CM_OSC registers...regardless of what you set it
+ * too! Thus, although i thought i was running at 140MHz, i'm actually running
+ * at 40!..
+
+ * Slapping this into my bootloader does the trick...
+
+ * MRC p15,0,r0,c1,c0,0 ; read core configuration register
+ * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
+ * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
+ * register
+ */
+ MRC p15,0,r0,c1,c0,0
+ ORR r0,r0,#0xC0000000
+ MCR p15,0,r0,c1,c0,0
+
+ ldr r0, =GPR(0)
+ ldr r1, =CFG_GPR_A_VAL
+ str r1, [r0]
+
+ ldr r0, =GIUS(0)
+ ldr r1, =CFG_GIUS_A_VAL
+ str r1, [r0]
+
+/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
+
+ ldr r0, =FMCR
+ ldr r1, =CFG_FMCR_VAL
+ str r1, [r0]
+
+ ldr r0, =CS0U
+ ldr r1, =CFG_CS0U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS0L
+ ldr r1, =CFG_CS0L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS1U
+ ldr r1, =CFG_CS1U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS1L
+ ldr r1, =CFG_CS1L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS2U
+ ldr r1, =CFG_CS2U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS2L
+ ldr r1, =CFG_CS2L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS3U
+ ldr r1, =CFG_CS3U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS3L
+ ldr r1, =CFG_CS3L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS4U
+ ldr r1, =CFG_CS4U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS4L
+ ldr r1, =CFG_CS4L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS5U
+ ldr r1, =CFG_CS5U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS5L
+ ldr r1, =CFG_CS5L_VAL
+ str r1, [r0]
+
+/* SDRAM Setup */
+
+ ldr r0, =SDCTL0
+ ldr r1, =PRECHARGE_CMD
+ str r1, [r0]
+
+ ldr r0, =0x08200000
+ ldr r1, =0x0 /* Issue Precharge all Command */
+ str r1, [r0]
+
+ ldr r0, =SDCTL0
+ ldr r1, =AUTOREFRESH_CMD
+ str r1, [r0]
+
+ ldr r0, =0x08000000
+ ldr r1, =0x0 /* Issue AutoRefresh Command */
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+
+ ldr r0, =SDCTL0
+ ldr r1, =0xb10a8300
+ str r1, [r0]
+
+ ldr r0, =0x08223000 /* CAS Latency 2 */
+ ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
+ str r1, [r0]
+
+ ldr r0, =SDCTL0
+ ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
+ str r1, [r0]
+
+ mov pc,r10
+++ /dev/null
-/*
- * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- * 02111-1307, USA.
- *
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/imx-regs.h>
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
-/* Change PERCLK1DIV to 14 ie 14+1 */
- ldr r0, =PCDR
- ldr r1, =CFG_PCDR_VAL
- str r1, [r0]
-
-/* set MCU PLL Control Register 0 */
-
- ldr r0, =MPCTL0
- ldr r1, =CFG_MPCTL0_VAL
- str r1, [r0]
-
-/* set mpll restart bit */
- ldr r0, =CSCR
- ldr r1, [r0]
- orr r1,r1,#(1<<21)
- str r1, [r0]
-
- mov r2,#0x10
-1:
- mov r3,#0x2000
-2:
- subs r3,r3,#1
- bne 2b
-
- subs r2,r2,#1
- bne 1b
-
-/* set System PLL Control Register 0 */
-
- ldr r0, =SPCTL0
- ldr r1, =CFG_SPCTL0_VAL
- str r1, [r0]
-
-/* set spll restart bit */
- ldr r0, =CSCR
- ldr r1, [r0]
- orr r1,r1,#(1<<22)
- str r1, [r0]
-
- mov r2,#0x10
-1:
- mov r3,#0x2000
-2:
- subs r3,r3,#1
- bne 2b
-
- subs r2,r2,#1
- bne 1b
-
- ldr r0, =CSCR
- ldr r1, =CFG_CSCR_VAL
- str r1, [r0]
-
-/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
- *this.....
- *
- * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
- * register 1, this stops it using the output of the PLL and thus runs at the
- * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
- * use the value set in the CM_OSC registers...regardless of what you set it
- * too! Thus, although i thought i was running at 140MHz, i'm actually running
- * at 40!..
-
- * Slapping this into my bootloader does the trick...
-
- * MRC p15,0,r0,c1,c0,0 ; read core configuration register
- * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
- * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
- * register
- */
- MRC p15,0,r0,c1,c0,0
- ORR r0,r0,#0xC0000000
- MCR p15,0,r0,c1,c0,0
-
- ldr r0, =GPR(0)
- ldr r1, =CFG_GPR_A_VAL
- str r1, [r0]
-
- ldr r0, =GIUS(0)
- ldr r1, =CFG_GIUS_A_VAL
- str r1, [r0]
-
-/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
-
- ldr r0, =FMCR
- ldr r1, =CFG_FMCR_VAL
- str r1, [r0]
-
- ldr r0, =CS0U
- ldr r1, =CFG_CS0U_VAL
- str r1, [r0]
-
- ldr r0, =CS0L
- ldr r1, =CFG_CS0L_VAL
- str r1, [r0]
-
- ldr r0, =CS1U
- ldr r1, =CFG_CS1U_VAL
- str r1, [r0]
-
- ldr r0, =CS1L
- ldr r1, =CFG_CS1L_VAL
- str r1, [r0]
-
- ldr r0, =CS2U
- ldr r1, =CFG_CS2U_VAL
- str r1, [r0]
-
- ldr r0, =CS2L
- ldr r1, =CFG_CS2L_VAL
- str r1, [r0]
-
- ldr r0, =CS3U
- ldr r1, =CFG_CS3U_VAL
- str r1, [r0]
-
- ldr r0, =CS3L
- ldr r1, =CFG_CS3L_VAL
- str r1, [r0]
-
- ldr r0, =CS4U
- ldr r1, =CFG_CS4U_VAL
- str r1, [r0]
-
- ldr r0, =CS4L
- ldr r1, =CFG_CS4L_VAL
- str r1, [r0]
-
- ldr r0, =CS5U
- ldr r1, =CFG_CS5U_VAL
- str r1, [r0]
-
- ldr r0, =CS5L
- ldr r1, =CFG_CS5L_VAL
- str r1, [r0]
-
-/* SDRAM Setup */
-
- ldr r0, =SDCTL0
- ldr r1, =PRECHARGE_CMD
- str r1, [r0]
-
- ldr r0, =0x08200000
- ldr r1, =0x0 /* Issue Precharge all Command */
- str r1, [r0]
-
- ldr r0, =SDCTL0
- ldr r1, =AUTOREFRESH_CMD
- str r1, [r0]
-
- ldr r0, =0x08000000
- ldr r1, =0x0 /* Issue AutoRefresh Command */
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
-
- ldr r0, =SDCTL0
- ldr r1, =0xb10a8300
- str r1, [r0]
-
- ldr r0, =0x08223000 /* CAS Latency 2 */
- ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
- str r1, [r0]
-
- ldr r0, =SDCTL0
- ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
- str r1, [r0]
-
- mov pc,r10
LIB = lib$(BOARD).a
OBJS := shannon.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+MEM_BASE: .long 0xa0000000
+MEM_START: .long 0xc0000000
+
+#define MDCNFG 0x00
+#define MDCAS0 0x04
+#define MDCAS1 0x08
+#define MDCAS2 0x0c
+#define MSC0 0x10
+#define MSC1 0x14
+#define MECR 0x18
+
+mdcas0: .long 0xc71c703f @ cccccccf
+mdcas1: .long 0xffc71c71 @ fffffffc
+mdcas2: .long 0xffffffff @ ffffffff
+mdcnfg: .long 0x0334b21f @ 9326991f
+msc0: .long 0xfff84458 @ 42304230
+msc1: .long 0xffffffff @ 20182018
+mecr: .long 0x7fff7fff @ 01000000
+
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr r0, MEM_BASE
+
+ /* Setup the flash memory */
+ ldr r1, msc0
+ str r1, [r0, #MSC0]
+
+ /* Set up the DRAM */
+
+ /* MDCAS0 */
+ ldr r1, mdcas0
+ str r1, [r0, #MDCAS0]
+
+ /* MDCAS1 */
+ ldr r1, mdcas1
+ str r1, [r0, #MDCAS1]
+
+ /* MDCAS2 */
+ ldr r1, mdcas2
+ str r1, [r0, #MDCAS2]
+
+ /* MDCNFG */
+ ldr r1, mdcnfg
+ str r1, [r0, #MDCNFG]
+
+ /* Set up PCMCIA space */
+ ldr r1, mecr
+ str r1, [r0, #MECR]
+
+ /* Load something to activate bank */
+ ldr r1, MEM_START
+
+.rept 8
+ ldr r0, [r1]
+.endr
+
+ /* everything is fine now */
+ mov pc, lr
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-
-/* some parameters for the board */
-
-MEM_BASE: .long 0xa0000000
-MEM_START: .long 0xc0000000
-
-#define MDCNFG 0x00
-#define MDCAS0 0x04
-#define MDCAS1 0x08
-#define MDCAS2 0x0c
-#define MSC0 0x10
-#define MSC1 0x14
-#define MECR 0x18
-
-mdcas0: .long 0xc71c703f @ cccccccf
-mdcas1: .long 0xffc71c71 @ fffffffc
-mdcas2: .long 0xffffffff @ ffffffff
-mdcnfg: .long 0x0334b21f @ 9326991f
-msc0: .long 0xfff84458 @ 42304230
-msc1: .long 0xffffffff @ 20182018
-mecr: .long 0x7fff7fff @ 01000000
-
-/* setting up the memory */
-
-.globl memsetup
-memsetup:
- ldr r0, MEM_BASE
-
- /* Setup the flash memory */
- ldr r1, msc0
- str r1, [r0, #MSC0]
-
- /* Set up the DRAM */
-
- /* MDCAS0 */
- ldr r1, mdcas0
- str r1, [r0, #MDCAS0]
-
- /* MDCAS1 */
- ldr r1, mdcas1
- str r1, [r0, #MDCAS1]
-
- /* MDCAS2 */
- ldr r1, mdcas2
- str r1, [r0, #MDCAS2]
-
- /* MDCNFG */
- ldr r1, mdcnfg
- str r1, [r0, #MDCNFG]
-
- /* Set up PCMCIA space */
- ldr r1, mecr
- str r1, [r0, #MECR]
-
- /* Load something to activate bank */
- ldr r1, MEM_START
-
-.rept 8
- ldr r0, [r1]
-.endr
-
- /* everything is fine now */
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := smdk2400.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung development board by
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2400.S
+ *
+ * Copyright (C) 2001 Samsung Electronics by chc, 010406
+ *
+ * S3C2400 specific tweaks.
+ *
+ */
+
+/* memory controller */
+#define BWSCON 0x14000000
+#define BANKCON3 0x14000010 /* for cs8900, ethernet */
+
+/* Bank0 */
+#define B0_Tacs 0x0 /* 0 clk */
+#define B0_Tcos 0x0 /* 0 clk */
+#define B0_Tacc 0x7 /* 14 clk */
+#define B0_Tcoh 0x0 /* 0 clk */
+#define B0_Tah 0x0 /* 0 clk */
+#define B0_Tacp 0x0
+#define B0_PMC 0x0 /* normal */
+
+/* Bank1 */
+#define B1_Tacs 0x0 /* 0 clk */
+#define B1_Tcos 0x0 /* 0 clk */
+#define B1_Tacc 0x7 /* 14 clk */
+#define B1_Tcoh 0x0 /* 0 clk */
+#define B1_Tah 0x0 /* 0 clk */
+#define B1_Tacp 0x0
+#define B1_PMC 0x0 /* normal */
+
+/* Bank2 */
+#define B2_Tacs 0x0 /* 0 clk */
+#define B2_Tcos 0x0 /* 0 clk */
+#define B2_Tacc 0x7 /* 14 clk */
+#define B2_Tcoh 0x0 /* 0 clk */
+#define B2_Tah 0x0 /* 0 clk */
+#define B2_Tacp 0x0
+#define B2_PMC 0x0 /* normal */
+
+/* Bank3 - setup for the cs8900 */
+#define B3_Tacs 0x0 /* 0 clk */
+#define B3_Tcos 0x3 /* 4 clk */
+#define B3_Tacc 0x7 /* 14 clk */
+#define B3_Tcoh 0x1 /* 1 clk */
+#define B3_Tah 0x0 /* 0 clk */
+#define B3_Tacp 0x3 /* 6 clk */
+#define B3_PMC 0x0 /* normal */
+
+/* Bank4 */
+#define B4_Tacs 0x0 /* 0 clk */
+#define B4_Tcos 0x0 /* 0 clk */
+#define B4_Tacc 0x7 /* 14 clk */
+#define B4_Tcoh 0x0 /* 0 clk */
+#define B4_Tah 0x0 /* 0 clk */
+#define B4_Tacp 0x0
+#define B4_PMC 0x0 /* normal */
+
+/* Bank5 */
+#define B5_Tacs 0x0 /* 0 clk */
+#define B5_Tcos 0x0 /* 0 clk */
+#define B5_Tacc 0x7 /* 14 clk */
+#define B5_Tcoh 0x0 /* 0 clk */
+#define B5_Tah 0x0 /* 0 clk */
+#define B5_Tacp 0x0
+#define B5_PMC 0x0 /* normal */
+
+/* Bank6 */
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1 /* 3clk */
+#define B6_SCAN 0x1 /* 9 bit */
+
+/* Bank7 */
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 3clk */
+#define B7_SCAN 0x1 /* 9 bit */
+
+/* refresh parameter */
+#define REFEN 0x1 /* enable refresh */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */
+#define Trp 0x0 /* 2 clk */
+#define Trc 0x3 /* 7 clk */
+#define Tchr 0x2 /* 3 clk */
+
+#define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */
+
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+ ldr r0, =SMRDATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add r2, r0, #52
+0:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r2, r0
+ bne 0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+SMRDATA:
+ .word 0x2211d114 /* d->Ethernet, BUSWIDTH=32 */
+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */
+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */
+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */
+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */
+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */
+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
+ .word 0x30 /* MRSR6, CL=3clk */
+ .word 0x30 /* MRSR7 */
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the Samsung development board by
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-
-/* some parameters for the board */
-
-/*
- *
- * Taken from linux/arch/arm/boot/compressed/head-s3c2400.S
- *
- * Copyright (C) 2001 Samsung Electronics by chc, 010406
- *
- * S3C2400 specific tweaks.
- *
- */
-
-/* memory controller */
-#define BWSCON 0x14000000
-#define BANKCON3 0x14000010 /* for cs8900, ethernet */
-
-/* Bank0 */
-#define B0_Tacs 0x0 /* 0 clk */
-#define B0_Tcos 0x0 /* 0 clk */
-#define B0_Tacc 0x7 /* 14 clk */
-#define B0_Tcoh 0x0 /* 0 clk */
-#define B0_Tah 0x0 /* 0 clk */
-#define B0_Tacp 0x0
-#define B0_PMC 0x0 /* normal */
-
-/* Bank1 */
-#define B1_Tacs 0x0 /* 0 clk */
-#define B1_Tcos 0x0 /* 0 clk */
-#define B1_Tacc 0x7 /* 14 clk */
-#define B1_Tcoh 0x0 /* 0 clk */
-#define B1_Tah 0x0 /* 0 clk */
-#define B1_Tacp 0x0
-#define B1_PMC 0x0 /* normal */
-
-/* Bank2 */
-#define B2_Tacs 0x0 /* 0 clk */
-#define B2_Tcos 0x0 /* 0 clk */
-#define B2_Tacc 0x7 /* 14 clk */
-#define B2_Tcoh 0x0 /* 0 clk */
-#define B2_Tah 0x0 /* 0 clk */
-#define B2_Tacp 0x0
-#define B2_PMC 0x0 /* normal */
-
-/* Bank3 - setup for the cs8900 */
-#define B3_Tacs 0x0 /* 0 clk */
-#define B3_Tcos 0x3 /* 4 clk */
-#define B3_Tacc 0x7 /* 14 clk */
-#define B3_Tcoh 0x1 /* 1 clk */
-#define B3_Tah 0x0 /* 0 clk */
-#define B3_Tacp 0x3 /* 6 clk */
-#define B3_PMC 0x0 /* normal */
-
-/* Bank4 */
-#define B4_Tacs 0x0 /* 0 clk */
-#define B4_Tcos 0x0 /* 0 clk */
-#define B4_Tacc 0x7 /* 14 clk */
-#define B4_Tcoh 0x0 /* 0 clk */
-#define B4_Tah 0x0 /* 0 clk */
-#define B4_Tacp 0x0
-#define B4_PMC 0x0 /* normal */
-
-/* Bank5 */
-#define B5_Tacs 0x0 /* 0 clk */
-#define B5_Tcos 0x0 /* 0 clk */
-#define B5_Tacc 0x7 /* 14 clk */
-#define B5_Tcoh 0x0 /* 0 clk */
-#define B5_Tah 0x0 /* 0 clk */
-#define B5_Tacp 0x0
-#define B5_PMC 0x0 /* normal */
-
-/* Bank6 */
-#define B6_MT 0x3 /* SDRAM */
-#define B6_Trcd 0x1 /* 3clk */
-#define B6_SCAN 0x1 /* 9 bit */
-
-/* Bank7 */
-#define B7_MT 0x3 /* SDRAM */
-#define B7_Trcd 0x1 /* 3clk */
-#define B7_SCAN 0x1 /* 9 bit */
-
-/* refresh parameter */
-#define REFEN 0x1 /* enable refresh */
-#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */
-#define Trp 0x0 /* 2 clk */
-#define Trc 0x3 /* 7 clk */
-#define Tchr 0x2 /* 3 clk */
-
-#define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */
-
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-.globl memsetup
-memsetup:
- /* memory control configuration */
- /* make r0 relative the current location so that it */
- /* reads SMRDATA out of FLASH rather than memory ! */
- ldr r0, =SMRDATA
- ldr r1, _TEXT_BASE
- sub r0, r0, r1
- ldr r1, =BWSCON /* Bus Width Status Controller */
- add r2, r0, #52
-0:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r2, r0
- bne 0b
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-/* the literal pools origin */
-
-SMRDATA:
- .word 0x2211d114 /* d->Ethernet, BUSWIDTH=32 */
- .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */
- .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */
- .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */
- .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */
- .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */
- .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */
- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
- .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
- .word 0x30 /* MRSR6, CL=3clk */
- .word 0x30 /* MRSR7 */
LIB = lib$(BOARD).a
OBJS := smdk2410.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
+ *
+ */
+
+#define BWSCON 0x48000000
+
+/* BWSCON */
+#define DW8 (0x0)
+#define DW16 (0x1)
+#define DW32 (0x2)
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/* BANK0CON */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0
+#define B0_PMC 0x0 /* normal */
+
+/* BANK1CON */
+#define B1_Tacs 0x0 /* 0clk */
+#define B1_Tcos 0x0 /* 0clk */
+#define B1_Tacc 0x7 /* 14clk */
+#define B1_Tcoh 0x0 /* 0clk */
+#define B1_Tah 0x0 /* 0clk */
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0 /* 0clk */
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7 /* 14clk */
+#define B3_Tcoh 0x1 /* 1clk */
+#define B3_Tah 0x0 /* 0clk */
+#define B3_Tacp 0x3 /* 6clk */
+#define B3_PMC 0x0 /* normal */
+
+#define B4_Tacs 0x0 /* 0clk */
+#define B4_Tcos 0x0 /* 0clk */
+#define B4_Tacc 0x7 /* 14clk */
+#define B4_Tcoh 0x0 /* 0clk */
+#define B4_Tah 0x0 /* 0clk */
+#define B4_Tacp 0x0
+#define B4_PMC 0x0 /* normal */
+
+#define B5_Tacs 0x0 /* 0clk */
+#define B5_Tcos 0x0 /* 0clk */
+#define B5_Tacc 0x7 /* 14clk */
+#define B5_Tcoh 0x0 /* 0clk */
+#define B5_Tah 0x0 /* 0clk */
+#define B5_Tacp 0x0
+#define B5_PMC 0x0 /* normal */
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1
+#define B6_SCAN 0x1 /* 9bit */
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 3clk */
+#define B7_SCAN 0x1 /* 9bit */
+
+/* REFRESH parameter */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x0 /* 2clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x2 /* 3clk */
+#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+ ldr r0, =SMRDATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add r2, r0, #13*4
+0:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r2, r0
+ bne 0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+SMRDATA:
+ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0x32
+ .word 0x30
+ .word 0x30
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the Samsung SMDK2410 by
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-
-/* some parameters for the board */
-
-/*
- *
- * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
- *
- * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
- *
- */
-
-#define BWSCON 0x48000000
-
-/* BWSCON */
-#define DW8 (0x0)
-#define DW16 (0x1)
-#define DW32 (0x2)
-#define WAIT (0x1<<2)
-#define UBLB (0x1<<3)
-
-#define B1_BWSCON (DW32)
-#define B2_BWSCON (DW16)
-#define B3_BWSCON (DW16 + WAIT + UBLB)
-#define B4_BWSCON (DW16)
-#define B5_BWSCON (DW16)
-#define B6_BWSCON (DW32)
-#define B7_BWSCON (DW32)
-
-/* BANK0CON */
-#define B0_Tacs 0x0 /* 0clk */
-#define B0_Tcos 0x0 /* 0clk */
-#define B0_Tacc 0x7 /* 14clk */
-#define B0_Tcoh 0x0 /* 0clk */
-#define B0_Tah 0x0 /* 0clk */
-#define B0_Tacp 0x0
-#define B0_PMC 0x0 /* normal */
-
-/* BANK1CON */
-#define B1_Tacs 0x0 /* 0clk */
-#define B1_Tcos 0x0 /* 0clk */
-#define B1_Tacc 0x7 /* 14clk */
-#define B1_Tcoh 0x0 /* 0clk */
-#define B1_Tah 0x0 /* 0clk */
-#define B1_Tacp 0x0
-#define B1_PMC 0x0
-
-#define B2_Tacs 0x0
-#define B2_Tcos 0x0
-#define B2_Tacc 0x7
-#define B2_Tcoh 0x0
-#define B2_Tah 0x0
-#define B2_Tacp 0x0
-#define B2_PMC 0x0
-
-#define B3_Tacs 0x0 /* 0clk */
-#define B3_Tcos 0x3 /* 4clk */
-#define B3_Tacc 0x7 /* 14clk */
-#define B3_Tcoh 0x1 /* 1clk */
-#define B3_Tah 0x0 /* 0clk */
-#define B3_Tacp 0x3 /* 6clk */
-#define B3_PMC 0x0 /* normal */
-
-#define B4_Tacs 0x0 /* 0clk */
-#define B4_Tcos 0x0 /* 0clk */
-#define B4_Tacc 0x7 /* 14clk */
-#define B4_Tcoh 0x0 /* 0clk */
-#define B4_Tah 0x0 /* 0clk */
-#define B4_Tacp 0x0
-#define B4_PMC 0x0 /* normal */
-
-#define B5_Tacs 0x0 /* 0clk */
-#define B5_Tcos 0x0 /* 0clk */
-#define B5_Tacc 0x7 /* 14clk */
-#define B5_Tcoh 0x0 /* 0clk */
-#define B5_Tah 0x0 /* 0clk */
-#define B5_Tacp 0x0
-#define B5_PMC 0x0 /* normal */
-
-#define B6_MT 0x3 /* SDRAM */
-#define B6_Trcd 0x1
-#define B6_SCAN 0x1 /* 9bit */
-
-#define B7_MT 0x3 /* SDRAM */
-#define B7_Trcd 0x1 /* 3clk */
-#define B7_SCAN 0x1 /* 9bit */
-
-/* REFRESH parameter */
-#define REFEN 0x1 /* Refresh enable */
-#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
-#define Trp 0x0 /* 2clk */
-#define Trc 0x3 /* 7clk */
-#define Tchr 0x2 /* 3clk */
-#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
-/**************************************/
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-.globl memsetup
-memsetup:
- /* memory control configuration */
- /* make r0 relative the current location so that it */
- /* reads SMRDATA out of FLASH rather than memory ! */
- ldr r0, =SMRDATA
- ldr r1, _TEXT_BASE
- sub r0, r0, r1
- ldr r1, =BWSCON /* Bus Width Status Controller */
- add r2, r0, #13*4
-0:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r2, r0
- bne 0b
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-/* the literal pools origin */
-
-SMRDATA:
- .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
- .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
- .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
- .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
- .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
- .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
- .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
- .word 0x32
- .word 0x30
- .word 0x30
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o vr4131-pci.o
-SOBJS = memsetup.o
+SOBJS = lowlevel_init.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Memory sub-system initialization code for TANBAC Evaluation board TB0229.
+ *
+ * Copyright (c) 2003 Masami Komiya <mkomiya@sonare.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+
+ .globl lowlevel_init
+lowlevel_init:
+
+ /* BCUCNTREG1 = 0x0040 */
+ la t0, 0xaf000000
+ li t1, 0x0040
+ sh t1, 0(t0)
+
+ /* ROMSIZEREG = 0x3333 */
+ la t0, 0xaf000004
+ li t1, 0x3333
+ sh t1, 0(t0)
+
+ /* ROMSPEEDREG = 0x3003 */
+ la t0, 0xaf000006
+ li t1, 0x3003
+ sh t1, 0(t0)
+
+ /* BCUCNTREG3 = 0 */
+ la t0, 0xaf000016
+ li t1, 0x0000
+ sh t1, 0(t0)
+
+ /* CMUCLKMSK */
+ la t0, 0xaf000060
+ li t1, 0x39a2
+ sh t1, 0(t0)
+
+ /* PMUCNTREG */
+ la t0, 0xaf0000c2
+ li t1, 0x0006
+ sh t1, 0(t0)
+
+ /* SDRAMMODEREG = 0x8029 */
+ la t0, 0xaf000400
+ li t1, 0x8029
+ sh t1, 0(t0)
+
+ /* SDRAMCNTREG = 0x2322 */
+ la t0, 0xaf000402
+ li t1, 0x2322
+ sh t1, 0(t0)
+
+ /* BCURFCNTREG = 0x0106 */
+ la t0, 0xaf000404
+ li t1, 0x0106
+ sh t1, 0(t0)
+
+ /* RAMSZEREG = 0x5555 (64MB Bank) */
+ la t0, 0xaf000408
+ li t1, 0x5555
+ sh t1, 0(t0)
+
+ j ra
+ nop
+++ /dev/null
-/*
- * Memory sub-system initialization code for TANBAC Evaluation board TB0229.
- *
- * Copyright (c) 2003 Masami Komiya <mkomiya@sonare.it>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2, or (at
- * your option) any later version.
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/regdef.h>
-
-
- .globl memsetup
-memsetup:
-
- /* BCUCNTREG1 = 0x0040 */
- la t0, 0xaf000000
- li t1, 0x0040
- sh t1, 0(t0)
-
- /* ROMSIZEREG = 0x3333 */
- la t0, 0xaf000004
- li t1, 0x3333
- sh t1, 0(t0)
-
- /* ROMSPEEDREG = 0x3003 */
- la t0, 0xaf000006
- li t1, 0x3003
- sh t1, 0(t0)
-
- /* BCUCNTREG3 = 0 */
- la t0, 0xaf000016
- li t1, 0x0000
- sh t1, 0(t0)
-
- /* CMUCLKMSK */
- la t0, 0xaf000060
- li t1, 0x39a2
- sh t1, 0(t0)
-
- /* PMUCNTREG */
- la t0, 0xaf0000c2
- li t1, 0x0006
- sh t1, 0(t0)
-
- /* SDRAMMODEREG = 0x8029 */
- la t0, 0xaf000400
- li t1, 0x8029
- sh t1, 0(t0)
-
- /* SDRAMCNTREG = 0x2322 */
- la t0, 0xaf000402
- li t1, 0x2322
- sh t1, 0(t0)
-
- /* BCURFCNTREG = 0x0106 */
- la t0, 0xaf000404
- li t1, 0x0106
- sh t1, 0(t0)
-
- /* RAMSZEREG = 0x5555 (64MB Bank) */
- la t0, 0xaf000408
- li t1, 0x5555
- sh t1, 0(t0)
-
- j ra
- nop
LIB = lib$(BOARD).a
OBJS := trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the TRAB board by
+ * (C) Copyright 2002-2003
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Copied from linux/arch/arm/boot/compressed/head-s3c2400.S
+ *
+ * Copyright (C) 2001 Samsung Electronics by chc, 010406
+ *
+ * TRAB specific tweaks.
+ *
+ */
+
+/* memory controller */
+#define BWSCON 0x14000000
+
+/* Bank0 */
+#define B0_Tacs 0x1 /* 1 clk */
+#define B0_Tcos 0x1 /* 1 clk */
+#define B0_Tacc 0x5 /* 8 clk */
+#define B0_Tcoh 0x1 /* 1 clk */
+#define B0_Tah 0x1 /* 1 clk */
+#define B0_Tacp 0x0
+#define B0_PMC 0x0 /* normal */
+
+/* Bank1 - SRAM */
+#define B1_Tacs 0x1 /* 1 clk */
+#define B1_Tcos 0x1 /* 1 clk */
+#define B1_Tacc 0x5 /* 8 clk */
+#define B1_Tcoh 0x1 /* 1 clk */
+#define B1_Tah 0x1 /* 1 clk */
+#define B1_Tacp 0x0
+#define B1_PMC 0x0 /* normal */
+
+/* Bank2 - CPLD */
+#define B2_Tacs 0x1 /* 1 clk */
+#define B2_Tcos 0x1 /* 1 clk */
+#define B2_Tacc 0x5 /* 8 clk */
+#define B2_Tcoh 0x1 /* 1 clk */
+#define B2_Tah 0x1 /* 1 clk */
+#define B2_Tacp 0x0
+#define B2_PMC 0x0 /* normal */
+
+/* Bank3 - setup for the cs8900 */
+#define B3_Tacs 0x3 /* 4 clk */
+#define B3_Tcos 0x3 /* 4 clk */
+#define B3_Tacc 0x7 /* 14 clk */
+#define B3_Tcoh 0x1 /* 1 clk */
+#define B3_Tah 0x0 /* 0 clk */
+#define B3_Tacp 0x3 /* 6 clk */
+#define B3_PMC 0x0 /* normal */
+
+/* Bank4 */
+#define B4_Tacs 0x0 /* 0 clk */
+#define B4_Tcos 0x0 /* 0 clk */
+#define B4_Tacc 0x7 /* 14 clk */
+#define B4_Tcoh 0x0 /* 0 clk */
+#define B4_Tah 0x0 /* 0 clk */
+#define B4_Tacp 0x0
+#define B4_PMC 0x0 /* normal */
+
+/* Bank5 */
+#define B5_Tacs 0x0 /* 0 clk */
+#define B5_Tcos 0x0 /* 0 clk */
+#define B5_Tacc 0x7 /* 14 clk */
+#define B5_Tcoh 0x0 /* 0 clk */
+#define B5_Tah 0x0 /* 0 clk */
+#define B5_Tacp 0x0
+#define B5_PMC 0x0 /* normal */
+
+#ifndef CONFIG_RAM_16MB /* 32 MB RAM */
+/* Bank6 */
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x0 /* 2clk */
+#define B6_SCAN 0x1 /* 9 bit */
+
+/* Bank7 */
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x0 /* 2clk */
+#define B7_SCAN 0x1 /* 9 bit */
+#else /* CONFIG_RAM_16MB = 16 MB RAM */
+/* Bank6 */
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1 /* 2clk */
+#define B6_SCAN 0x0 /* 8 bit */
+
+/* Bank7 */
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 2clk */
+#define B7_SCAN 0x0 /* 8 bit */
+#endif /* CONFIG_RAM_16MB */
+
+/* refresh parameter */
+#define REFEN 0x1 /* enable refresh */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */
+#define Trp 0x0 /* 2 clk */
+#define Trc 0x3 /* 7 clk */
+#define Tchr 0x2 /* 3 clk */
+
+#ifdef CONFIG_TRAB_50MHZ
+#define REFCNT 1269 /* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */
+#else
+#define REFCNT 1011 /* period=15.6 us, HCLK=66.5Mhz, (2048+1-15.6*66.5) */
+#endif
+
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+ ldr r0, =SMRDATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add r2, r0, #52
+0:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r2, r0
+ bne 0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+SMRDATA:
+ .word 0x2211d644 /* d->Ethernet, 6->CPLD, 4->SRAM, 4->FLASH */
+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */
+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */
+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */
+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */
+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */
+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+#ifndef CONFIG_RAM_16MB /* 32 MB RAM */
+ .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
+#else /* CONFIG_RAM_16MB = 16 MB RAM */
+ .word 0x17 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */
+#endif /* CONFIG_RAM_16MB */
+ .word 0x20 /* MRSR6, CL=2clk */
+ .word 0x20 /* MRSR7 */
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the TRAB board by
- * (C) Copyright 2002-2003
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-
-/* some parameters for the board */
-
-/*
- *
- * Copied from linux/arch/arm/boot/compressed/head-s3c2400.S
- *
- * Copyright (C) 2001 Samsung Electronics by chc, 010406
- *
- * TRAB specific tweaks.
- *
- */
-
-/* memory controller */
-#define BWSCON 0x14000000
-
-/* Bank0 */
-#define B0_Tacs 0x1 /* 1 clk */
-#define B0_Tcos 0x1 /* 1 clk */
-#define B0_Tacc 0x5 /* 8 clk */
-#define B0_Tcoh 0x1 /* 1 clk */
-#define B0_Tah 0x1 /* 1 clk */
-#define B0_Tacp 0x0
-#define B0_PMC 0x0 /* normal */
-
-/* Bank1 - SRAM */
-#define B1_Tacs 0x1 /* 1 clk */
-#define B1_Tcos 0x1 /* 1 clk */
-#define B1_Tacc 0x5 /* 8 clk */
-#define B1_Tcoh 0x1 /* 1 clk */
-#define B1_Tah 0x1 /* 1 clk */
-#define B1_Tacp 0x0
-#define B1_PMC 0x0 /* normal */
-
-/* Bank2 - CPLD */
-#define B2_Tacs 0x1 /* 1 clk */
-#define B2_Tcos 0x1 /* 1 clk */
-#define B2_Tacc 0x5 /* 8 clk */
-#define B2_Tcoh 0x1 /* 1 clk */
-#define B2_Tah 0x1 /* 1 clk */
-#define B2_Tacp 0x0
-#define B2_PMC 0x0 /* normal */
-
-/* Bank3 - setup for the cs8900 */
-#define B3_Tacs 0x3 /* 4 clk */
-#define B3_Tcos 0x3 /* 4 clk */
-#define B3_Tacc 0x7 /* 14 clk */
-#define B3_Tcoh 0x1 /* 1 clk */
-#define B3_Tah 0x0 /* 0 clk */
-#define B3_Tacp 0x3 /* 6 clk */
-#define B3_PMC 0x0 /* normal */
-
-/* Bank4 */
-#define B4_Tacs 0x0 /* 0 clk */
-#define B4_Tcos 0x0 /* 0 clk */
-#define B4_Tacc 0x7 /* 14 clk */
-#define B4_Tcoh 0x0 /* 0 clk */
-#define B4_Tah 0x0 /* 0 clk */
-#define B4_Tacp 0x0
-#define B4_PMC 0x0 /* normal */
-
-/* Bank5 */
-#define B5_Tacs 0x0 /* 0 clk */
-#define B5_Tcos 0x0 /* 0 clk */
-#define B5_Tacc 0x7 /* 14 clk */
-#define B5_Tcoh 0x0 /* 0 clk */
-#define B5_Tah 0x0 /* 0 clk */
-#define B5_Tacp 0x0
-#define B5_PMC 0x0 /* normal */
-
-#ifndef CONFIG_RAM_16MB /* 32 MB RAM */
-/* Bank6 */
-#define B6_MT 0x3 /* SDRAM */
-#define B6_Trcd 0x0 /* 2clk */
-#define B6_SCAN 0x1 /* 9 bit */
-
-/* Bank7 */
-#define B7_MT 0x3 /* SDRAM */
-#define B7_Trcd 0x0 /* 2clk */
-#define B7_SCAN 0x1 /* 9 bit */
-#else /* CONFIG_RAM_16MB = 16 MB RAM */
-/* Bank6 */
-#define B6_MT 0x3 /* SDRAM */
-#define B6_Trcd 0x1 /* 2clk */
-#define B6_SCAN 0x0 /* 8 bit */
-
-/* Bank7 */
-#define B7_MT 0x3 /* SDRAM */
-#define B7_Trcd 0x1 /* 2clk */
-#define B7_SCAN 0x0 /* 8 bit */
-#endif /* CONFIG_RAM_16MB */
-
-/* refresh parameter */
-#define REFEN 0x1 /* enable refresh */
-#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */
-#define Trp 0x0 /* 2 clk */
-#define Trc 0x3 /* 7 clk */
-#define Tchr 0x2 /* 3 clk */
-
-#ifdef CONFIG_TRAB_50MHZ
-#define REFCNT 1269 /* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */
-#else
-#define REFCNT 1011 /* period=15.6 us, HCLK=66.5Mhz, (2048+1-15.6*66.5) */
-#endif
-
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-.globl memsetup
-memsetup:
- /* memory control configuration */
- /* make r0 relative the current location so that it */
- /* reads SMRDATA out of FLASH rather than memory ! */
- ldr r0, =SMRDATA
- ldr r1, _TEXT_BASE
- sub r0, r0, r1
- ldr r1, =BWSCON /* Bus Width Status Controller */
- add r2, r0, #52
-0:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r2, r0
- bne 0b
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-/* the literal pools origin */
-
-SMRDATA:
- .word 0x2211d644 /* d->Ethernet, 6->CPLD, 4->SRAM, 4->FLASH */
- .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */
- .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */
- .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */
- .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */
- .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */
- .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */
- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
-#ifndef CONFIG_RAM_16MB /* 32 MB RAM */
- .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
-#else /* CONFIG_RAM_16MB = 16 MB RAM */
- .word 0x17 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */
-#endif /* CONFIG_RAM_16MB */
- .word 0x20 /* MRSR6, CL=2clk */
- .word 0x20 /* MRSR7 */
LIB = lib$(BOARD).a
OBJS := wepep250.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * Copyright (C) 2001, 2002 ETC s.r.o.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
+ * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ * Documentation:
+ * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
+ * Developer's Manual", February 2002, Order Number: 278522-001
+ * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
+ * Revision 1.0, February 2002
+ * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
+ * Revision 1.0, February 2002
+ *
+*/
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+/* setup memory - see 6.12 in [1]
+ * Step 1 - wait 200 us
+ */
+ mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */
+1: subs r0, r0, #1
+ bne 1b
+/* TODO: complete step 1 for Synchronous Static memory*/
+
+ ldr r0, =0x48000000 /* MC_BASE */
+
+
+/* step 1.a - setup MSCx
+ */
+ ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
+ str r1, [r0, #0x8] /* MSC0_OFFSET */
+
+/* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
+ * see AUTO REFRESH chapter in section D. in [2] and in [3]
+ * DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
+ * DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
+ * TODO: complete for Synchronous Static memory
+ */
+ ldr r1, [r0, #4] /* MDREFR_OFFSET */
+ ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */
+ bic r1, r1, r2
+#if defined( WEP_SDRAM_K4S281633 )
+ orr r1, r1, #48 /* MDREFR_DRI(48) */
+#elif defined( WEP_SDRAM_K4S561633 )
+ orr r1, r1, #24 /* MDREFR_DRI(24) */
+#else
+#error SDRAM chip is not defined
+#endif
+
+ str r1, [r0, #4] /* MDREFR_OFFSET */
+
+/* Step 2 - only for Synchronous Static memory (TODO)
+ *
+ * Step 3 - same as step 4
+ *
+ * Step 4
+ *
+ * Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
+ */
+ orr r1, r1, #0x00010000 /* MDREFR_K1RUN */
+ bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */
+ str r1, [r0, #4] /* MDREFR_OFFSET */
+
+/* Step 4.b - clear MDREFR:SLFRSH */
+ bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */
+ str r1, [r0, #4] /* MDREFR_OFFSET */
+
+/* Step 4.c - set MDREFR:E1PIN */
+ orr r1, r1, #0x00008000 /* MDREFR_E1PIN */
+ str r1, [r0, #4] /* MDREFR_OFFSET */
+
+/* Step 4.d - automatically done
+ *
+ * Steps 4.e and 4.f - configure SDRAM
+ */
+#if defined( WEP_SDRAM_K4S281633 )
+ ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
+#elif defined( WEP_SDRAM_K4S561633 )
+ ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
+#else
+#error SDRAM chip is not defined
+#endif
+ str r1, [r0, #0] /* MDCNFG_OFFSET */
+
+/* Step 5 - wait at least 200 us for SDRAM
+ * see section B. in [2]
+ */
+ mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */
+1: subs r2, r2, #1
+ bne 1b
+
+/* Step 6 - after reset dcache is disabled, so automatically done
+ *
+ * Step 7 - eight refresh cycles
+ */
+ mov r2, #0xA0000000
+ ldr r3, [r2]
+ ldr r3, [r2]
+ ldr r3, [r2]
+ ldr r3, [r2]
+ ldr r3, [r2]
+ ldr r3, [r2]
+ ldr r3, [r2]
+ ldr r3, [r2]
+
+/* Step 8 - we don't need dcache now
+ *
+ * Step 9 - enable SDRAM partition 0
+ */
+ orr r1, r1, #1 /* MDCNFG_DE0 */
+ str r1, [r0, #0] /* MDCNFG_OFFSET */
+
+/* Step 10 - write MDMRS */
+ mov r1, #0
+ str r1, [r0, #0x40] /* MDMRS_OFFSET */
+
+/* Step 11 - optional (TODO) */
+
+ mov pc,r10
+++ /dev/null
-/*
- * Copyright (C) 2001, 2002 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- * 02111-1307, USA.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
- * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- * Documentation:
- * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
- * Developer's Manual", February 2002, Order Number: 278522-001
- * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
- * Revision 1.0, February 2002
- * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
- * Revision 1.0, February 2002
- *
-*/
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
-/* setup memory - see 6.12 in [1]
- * Step 1 - wait 200 us
- */
- mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */
-1: subs r0, r0, #1
- bne 1b
-/* TODO: complete step 1 for Synchronous Static memory*/
-
- ldr r0, =0x48000000 /* MC_BASE */
-
-
-/* step 1.a - setup MSCx
- */
- ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
- str r1, [r0, #0x8] /* MSC0_OFFSET */
-
-/* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
- * see AUTO REFRESH chapter in section D. in [2] and in [3]
- * DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
- * DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
- * TODO: complete for Synchronous Static memory
- */
- ldr r1, [r0, #4] /* MDREFR_OFFSET */
- ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */
- bic r1, r1, r2
-#if defined( WEP_SDRAM_K4S281633 )
- orr r1, r1, #48 /* MDREFR_DRI(48) */
-#elif defined( WEP_SDRAM_K4S561633 )
- orr r1, r1, #24 /* MDREFR_DRI(24) */
-#else
-#error SDRAM chip is not defined
-#endif
-
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 2 - only for Synchronous Static memory (TODO)
- *
- * Step 3 - same as step 4
- *
- * Step 4
- *
- * Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
- */
- orr r1, r1, #0x00010000 /* MDREFR_K1RUN */
- bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 4.b - clear MDREFR:SLFRSH */
- bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 4.c - set MDREFR:E1PIN */
- orr r1, r1, #0x00008000 /* MDREFR_E1PIN */
- str r1, [r0, #4] /* MDREFR_OFFSET */
-
-/* Step 4.d - automatically done
- *
- * Steps 4.e and 4.f - configure SDRAM
- */
-#if defined( WEP_SDRAM_K4S281633 )
- ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
-#elif defined( WEP_SDRAM_K4S561633 )
- ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
-#else
-#error SDRAM chip is not defined
-#endif
- str r1, [r0, #0] /* MDCNFG_OFFSET */
-
-/* Step 5 - wait at least 200 us for SDRAM
- * see section B. in [2]
- */
- mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */
-1: subs r2, r2, #1
- bne 1b
-
-/* Step 6 - after reset dcache is disabled, so automatically done
- *
- * Step 7 - eight refresh cycles
- */
- mov r2, #0xA0000000
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
- ldr r3, [r2]
-
-/* Step 8 - we don't need dcache now
- *
- * Step 9 - enable SDRAM partition 0
- */
- orr r1, r1, #1 /* MDCNFG_DE0 */
- str r1, [r0, #0] /* MDCNFG_OFFSET */
-
-/* Step 10 - write MDMRS */
- mov r1, #0
- str r1, [r0, #0x40] /* MDMRS_OFFSET */
-
-/* Step 11 - optional (TODO) */
-
- mov pc,r10
LIB = lib$(BOARD).a
OBJS := xaeniax.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+ /*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+ /* Set up GPIO pins first ----------------------------------------- */
+
+ ldr r0,=GPSR0
+ ldr r1,=CFG_GPSR0_VAL
+ str r1,[r0]
+
+ ldr r0,=GPSR1
+ ldr r1,=CFG_GPSR1_VAL
+ str r1,[r0]
+
+ ldr r0,=GPSR2
+ ldr r1,=CFG_GPSR2_VAL
+ str r1,[r0]
+
+ ldr r0,=GPCR0
+ ldr r1,=CFG_GPCR0_VAL
+ str r1,[r0]
+
+ ldr r0,=GPCR1
+ ldr r1,=CFG_GPCR1_VAL
+ str r1,[r0]
+
+ ldr r0,=GPCR2
+ ldr r1,=CFG_GPCR2_VAL
+ str r1,[r0]
+
+ ldr r0,=GPDR0
+ ldr r1,=CFG_GPDR0_VAL
+ str r1,[r0]
+
+ ldr r0,=GPDR1
+ ldr r1,=CFG_GPDR1_VAL
+ str r1,[r0]
+
+ ldr r0,=GPDR2
+ ldr r1,=CFG_GPDR2_VAL
+ str r1,[r0]
+
+ ldr r0,=GAFR0_L
+ ldr r1,=CFG_GAFR0_L_VAL
+ str r1,[r0]
+
+ ldr r0,=GAFR0_U
+ ldr r1,=CFG_GAFR0_U_VAL
+ str r1,[r0]
+
+ ldr r0,=GAFR1_L
+ ldr r1,=CFG_GAFR1_L_VAL
+ str r1,[r0]
+
+ ldr r0,=GAFR1_U
+ ldr r1,=CFG_GAFR1_U_VAL
+ str r1,[r0]
+
+ ldr r0,=GAFR2_L
+ ldr r1,=CFG_GAFR2_L_VAL
+ str r1,[r0]
+
+ ldr r0,=GAFR2_U
+ ldr r1,=CFG_GAFR2_U_VAL
+ str r1,[r0]
+
+ ldr r0,=PSSR /* enable GPIO pins */
+ ldr r1,=CFG_PSSR_VAL
+ str r1,[r0]
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+
+ ldr r1,=MEMC_BASE /* get memory controller base addr. */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2a: Initialize Asynchronous static memory controller */
+ /* ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2,=CFG_MSC0_VAL
+ str r2,[r1, #MSC0_OFFSET]
+ ldr r2,[r1, #MSC0_OFFSET] /* read back to ensure data latches */
+
+ /* MSC1: nCS(2,3) */
+ ldr r2,=CFG_MSC1_VAL
+ str r2,[r1, #MSC1_OFFSET]
+ ldr r2,[r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2,=CFG_MSC2_VAL
+ str r2,[r1, #MSC2_OFFSET]
+ ldr r2,[r1, #MSC2_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2b: Initialize Card Interface */
+ /* ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2,=CFG_MECR_VAL
+ str r2,[r1, #MECR_OFFSET]
+ ldr r2,[r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2,=CFG_MCMEM0_VAL
+ str r2,[r1, #MCMEM0_OFFSET]
+ ldr r2,[r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2,=CFG_MCMEM1_VAL
+ str r2,[r1, #MCMEM1_OFFSET]
+ ldr r2,[r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2,=CFG_MCATT0_VAL
+ str r2,[r1, #MCATT0_OFFSET]
+ ldr r2,[r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2,=CFG_MCATT1_VAL
+ str r2,[r1, #MCATT1_OFFSET]
+ ldr r2,[r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2,=CFG_MCIO0_VAL
+ str r2,[r1, #MCIO0_OFFSET]
+ ldr r2,[r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2,=CFG_MCIO1_VAL
+ str r2,[r1, #MCIO1_OFFSET]
+ ldr r2,[r1, #MCIO1_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
+
+ @ get the mdrefr settings
+ ldr r4,=CFG_MDREFR_VAL
+
+ @ write back mdrefr
+ str r4,[r1, #MDREFR_OFFSET]
+ ldr r4,[r1, #MDREFR_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+ /* ---------------------------------------------------------------- */
+
+ /* Initialize SXCNFG register. Assert the enable bits */
+
+ /* Write SXMRS to cause an MRS command to all enabled banks of */
+ /* synchronous static memory. Note that SXLCR need not be written */
+ /* at this time. */
+
+ /* FIXME: we use async mode for now */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
+
+ @ set K1RUN for bank 0
+ @
+ orr r4, r4, #MDREFR_K1RUN
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ deassert SLFRSH
+ @
+ bic r4, r4, #MDREFR_SLFRSH
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ assert E1PIN
+ @ if E0PIN is also used: #(MDREFR_E1PIN|MDREFR_E0PIN)
+ orr r4, r4, #(MDREFR_E1PIN)
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+ nop
+ nop
+
+ /* Step 4d: */
+ /* fetch platform value of mdcnfg */
+ @
+ ldr r2, =CFG_MDCNFG_VAL
+
+ @ disable all sdram banks
+ @
+ bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
+ bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
+
+ @ program banks 0/1 for bus width
+ @
+ bic r2, r2, #MDCNFG_DWID0 @0=32-bit
+
+ @ write initial value of mdcnfg, w/o enabling sdram banks
+ @
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
+ /* 100..200 µsec. */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by */
+ /* attempting non-burst read or write accesses to disabled */
+ /* SDRAM, as commonly specified in the power up sequence */
+ /* documented in SDRAM data sheets. The address(es) used */
+ /* for this purpose must not be cacheable. */
+
+ ldr r3, =CFG_DRAM_BASE
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+
+ /* Step 4g: Write MDCNFG with enable bits asserted */
+ /* get memory controller base address */
+ ldr r1, =MEMC_BASE
+
+ @fetch current mdcnfg value
+ @
+ ldr r3, [r1, #MDCNFG_OFFSET]
+
+ @enable sdram bank 0 if installed (must do for any populated bank)
+ @
+ orr r3, r3, #MDCNFG_DE0
+
+ @write back mdcnfg, enabling the sdram bank(s)
+ @
+ str r3, [r1, #MDCNFG_OFFSET]
+
+ /* Step 4h: Write MDMRS. */
+
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+
+ /* We are finished with Intel's memory controller initialisation */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Disable (mask) all interrupts at interrupt controller */
+ /* ---------------------------------------------------------------- */
+
+initirqs:
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r1, =CFG_ICMR_VAL /* mask all interrupts at the controller */
+ ldr r2, =ICMR
+ str r1, [r2]
+
+
+ /* ---------------------------------------------------------------- */
+ /* Clock initialisation */
+ /* ---------------------------------------------------------------- */
+
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency */
+ /* (hard-coding at 398.12MHz for now). */
+ /* Turn Off ALL on-chip peripheral clocks for re-configuration */
+ /* Note: See label 'ENABLECLKS' for the re-enabling */
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+
+ /* default value */
+ ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
+
+ /* ... and write the core clock config register */
+ ldr r1, =CCCR
+ str r2, [r1]
+
+#ifdef RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
+ /* has settled. */
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+#endif
+
+ @ Turn on needed clocks
+ @
+test:
+ ldr r1, =CKEN
+ ldr r2, =CFG_CKEN_VAL
+ str r2, [r1]
+
+ /* ---------------------------------------------------------------- */
+ /* */
+ /* ---------------------------------------------------------------- */
+
+ /* Save SDRAM size ?*/
+ ldr r1, =DRAM_SIZE
+ str r8, [r1]
+
+ /* FIXME */
+
+#define NODEBUG
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+ mov pc, lr
+++ /dev/null
- /*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CFG_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0,=GPSR0
- ldr r1,=CFG_GPSR0_VAL
- str r1,[r0]
-
- ldr r0,=GPSR1
- ldr r1,=CFG_GPSR1_VAL
- str r1,[r0]
-
- ldr r0,=GPSR2
- ldr r1,=CFG_GPSR2_VAL
- str r1,[r0]
-
- ldr r0,=GPCR0
- ldr r1,=CFG_GPCR0_VAL
- str r1,[r0]
-
- ldr r0,=GPCR1
- ldr r1,=CFG_GPCR1_VAL
- str r1,[r0]
-
- ldr r0,=GPCR2
- ldr r1,=CFG_GPCR2_VAL
- str r1,[r0]
-
- ldr r0,=GPDR0
- ldr r1,=CFG_GPDR0_VAL
- str r1,[r0]
-
- ldr r0,=GPDR1
- ldr r1,=CFG_GPDR1_VAL
- str r1,[r0]
-
- ldr r0,=GPDR2
- ldr r1,=CFG_GPDR2_VAL
- str r1,[r0]
-
- ldr r0,=GAFR0_L
- ldr r1,=CFG_GAFR0_L_VAL
- str r1,[r0]
-
- ldr r0,=GAFR0_U
- ldr r1,=CFG_GAFR0_U_VAL
- str r1,[r0]
-
- ldr r0,=GAFR1_L
- ldr r1,=CFG_GAFR1_L_VAL
- str r1,[r0]
-
- ldr r0,=GAFR1_U
- ldr r1,=CFG_GAFR1_U_VAL
- str r1,[r0]
-
- ldr r0,=GAFR2_L
- ldr r1,=CFG_GAFR2_L_VAL
- str r1,[r0]
-
- ldr r0,=GAFR2_U
- ldr r1,=CFG_GAFR2_U_VAL
- str r1,[r0]
-
- ldr r0,=PSSR /* enable GPIO pins */
- ldr r1,=CFG_PSSR_VAL
- str r1,[r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1,=MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2,=CFG_MSC0_VAL
- str r2,[r1, #MSC0_OFFSET]
- ldr r2,[r1, #MSC0_OFFSET] /* read back to ensure data latches */
-
- /* MSC1: nCS(2,3) */
- ldr r2,=CFG_MSC1_VAL
- str r2,[r1, #MSC1_OFFSET]
- ldr r2,[r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2,=CFG_MSC2_VAL
- str r2,[r1, #MSC2_OFFSET]
- ldr r2,[r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2,=CFG_MECR_VAL
- str r2,[r1, #MECR_OFFSET]
- ldr r2,[r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2,=CFG_MCMEM0_VAL
- str r2,[r1, #MCMEM0_OFFSET]
- ldr r2,[r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2,=CFG_MCMEM1_VAL
- str r2,[r1, #MCMEM1_OFFSET]
- ldr r2,[r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2,=CFG_MCATT0_VAL
- str r2,[r1, #MCATT0_OFFSET]
- ldr r2,[r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2,=CFG_MCATT1_VAL
- str r2,[r1, #MCATT1_OFFSET]
- ldr r2,[r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2,=CFG_MCIO0_VAL
- str r2,[r1, #MCIO0_OFFSET]
- ldr r2,[r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2,=CFG_MCIO1_VAL
- str r2,[r1, #MCIO1_OFFSET]
- ldr r2,[r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- @ get the mdrefr settings
- ldr r4,=CFG_MDREFR_VAL
-
- @ write back mdrefr
- str r4,[r1, #MDREFR_OFFSET]
- ldr r4,[r1, #MDREFR_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- /* FIXME: we use async mode for now */
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- @ set K1RUN for bank 0
- @
- orr r4, r4, #MDREFR_K1RUN
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #MDREFR_SLFRSH
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @ if E0PIN is also used: #(MDREFR_E1PIN|MDREFR_E0PIN)
- orr r4, r4, #(MDREFR_E1PIN)
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-
- /* Step 4d: */
- /* fetch platform value of mdcnfg */
- @
- ldr r2, =CFG_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CFG_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* get memory controller base address */
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-
- /* We are finished with Intel's memory controller initialisation */
-
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r1, =CFG_ICMR_VAL /* mask all interrupts at the controller */
- ldr r2, =ICMR
- str r1, [r2]
-
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
- /* (hard-coding at 398.12MHz for now). */
- /* Turn Off ALL on-chip peripheral clocks for re-configuration */
- /* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-
- /* default value */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
-
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
-
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
-test:
- ldr r1, =CKEN
- ldr r2, =CFG_CKEN_VAL
- str r2, [r1]
-
- /* ---------------------------------------------------------------- */
- /* */
- /* ---------------------------------------------------------------- */
-
- /* Save SDRAM size ?*/
- ldr r1, =DRAM_SIZE
- str r8, [r1]
-
- /* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End memsetup */
- /* ---------------------------------------------------------------- */
-
-endmemsetup:
-
- mov pc, lr
LIB = lib$(BOARD).a
OBJS := xm250.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
--- /dev/null
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+/*
+ .macro SET_LED val
+ ldr r6, =CRADLE_LED_CLR_REG
+ ldr r7, =0
+ str r7, [r6]
+ ldr r6, =CRADLE_LED_SET_REG
+ ldr r7, =\val
+ str r7, [r6]
+ .endm
+*/
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+ /* Set up GPIO pins first */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER0
+ ldr r1, =CFG_GRER0_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER1
+ ldr r1, =CFG_GRER1_VAL
+ str r1, [r0]
+
+ ldr r0, =GRER2
+ ldr r1, =CFG_GRER2_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER0
+ ldr r1, =CFG_GFER0_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER1
+ ldr r1, =CFG_GFER1_VAL
+ str r1, [r0]
+
+ ldr r0, =GFER2
+ ldr r1, =CFG_GFER2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ /* enable GPIO pins */
+ ldr r0, =PSSR
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+ /* SET_LED 1 */
+
+ ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */
+ ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */
+ str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */
+ ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */
+
+
+/*********************************************************************
+ * Initlialize Memory Controller
+ *
+ * See PXA250 Operating System Developer's Guide
+ *
+ * pause for 200 uSecs- allow internal clocks to settle
+ * *Note: only need this if hard reset... doing it anyway for now
+ */
+
+ @ Step 1
+ @ ---- Wait 200 usec
+ ldr r3, =OSCR @ reset the OS Timer Count to zero
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+ /* SET_LED 2 */
+
+mem_init:
+ @ get memory controller base address
+ ldr r1, =MEMC_BASE
+
+
+@****************************************************************************
+@ Step 2
+@
+
+ @ Step 2a
+ @ write msc0, read back to ensure data latches
+ @
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET]
+
+ @ write msc1
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ @ write msc2
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ @ Step 2b
+ @ write mecr
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+
+ @ write mcmem0
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+
+ @ write mcmem1
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+
+ @ write mcatt0
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+
+ @ write mcatt1
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+
+ @ write mcio0
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+
+ @ write mcio1
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+
+ /*SET_LED 3 */
+
+ @ Step 2c
+ @ fly-by-dma is defeatured on this part
+ @ write flycnfg
+ @ldr r2, =CFG_FLYCNFG_VAL
+ @str r2, [r1, #FLYCNFG_OFFSET]
+
+/* FIXME Does this sequence really make sense */
+#ifdef REDBOOT_WAY
+ @ Step 2d
+ @ get the mdrefr settings
+ ldr r3, =CFG_MDREFR_VAL
+
+ @ extract DRI field (we need a valid DRI field)
+ @
+ ldr r2, =0xFFF
+
+ @ valid DRI field in r3
+ @
+ and r3, r3, r2
+
+ @ get the reset state of MDREFR
+ @
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ clear the DRI field
+ @
+ bic r4, r4, r2
+
+ @ insert the valid DRI field loaded above
+ @
+ orr r4, r4, r3
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ *Note: preserve the mdrefr value in r4 *
+
+ /*SET_LED 4 */
+
+@****************************************************************************
+@ Step 3
+@
+@ NO SRAM
+
+ mov pc, r10
+
+
+@****************************************************************************
+@ Step 4
+@
+
+ @ Assumes previous mdrefr value in r4, if not then read current mdrefr
+
+ @ clear the free-running clock bits
+ @ (clear K0Free, K1Free, K2Free
+ @
+ bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
+
+ @ set K0RUN for CPLD clock
+ @
+ orr r4, r4, #0x00002000
+
+ @ set K1RUN if bank 0 installed
+ @
+ orr r4, r4, #0x00010000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ deassert SLFRSH
+ @
+ bic r4, r4, #0x00400000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ assert E1PIN
+ @
+ orr r4, r4, #0x00008000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+ nop
+ nop
+#else
+ @ Step 2d
+ @ get the mdrefr settings
+ ldr r4, =CFG_MDREFR_VAL
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ Step 4
+
+ @ set K0RUN for FLASH clock
+ @
+ orr r4, r4, #0x00002000
+
+ @ set K1RUN for bank DRAM 0
+ @
+ orr r4, r4, #0x00010000
+
+ @ set K2RUN for bank PLD
+ @
+ orr r4, r4, #0x00040000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ deassert SLFRSH
+ @
+ bic r4, r4, #0x00400000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ assert E1PIN
+ @
+ orr r4, r4, #0x00008000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+ nop
+ nop
+#endif
+
+ @ Step 4d
+ @ fetch platform value of mdcnfg
+ @
+ ldr r2, =CFG_MDCNFG_VAL
+
+ @ disable all sdram banks
+ @
+ bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
+ bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
+
+ @ program banks 0/1 for bus width
+ @
+ bic r2, r2, #MDCNFG_DWID0 @0=32-bit
+
+ @ write initial value of mdcnfg, w/o enabling sdram banks
+ @
+ str r2, [r1, #MDCNFG_OFFSET]
+
+ @ Step 4e
+ @ pause for 200 uSecs
+ @
+ ldr r3, =OSCR @ reset the OS Timer Count to zero
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+ /*SET_LED 5 */
+
+ /* Why is this here??? */
+ mov r0, #0x78 @turn everything off
+ mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
+
+ @ Step 4f
+ @ Access memory *not yet enabled* for CBR refresh cycles (8)
+ @ - CBR is generated for all banks
+
+ ldr r2, =CFG_DRAM_BASE
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+
+ @ Step 4g
+ @get memory controller base address
+ @
+ ldr r1, =MEMC_BASE
+
+ @fetch current mdcnfg value
+ @
+ ldr r3, [r1, #MDCNFG_OFFSET]
+
+ @enable sdram bank 0 if installed (must do for any populated bank)
+ @
+ orr r3, r3, #MDCNFG_DE0
+
+ @write back mdcnfg, enabling the sdram bank(s)
+ @
+ str r3, [r1, #MDCNFG_OFFSET]
+
+ @ Step 4h
+ @ write mdmrs
+ @
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+ @ Done Memory Init
+
+ /*SET_LED 6 */
+
+ @********************************************************************
+ @ Disable (mask) all interrupts at the interrupt controller
+ @
+
+ @ clear the interrupt level register (use IRQ, not FIQ)
+ @
+ mov r1, #0
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ @ Set interrupt mask register
+ @
+ ldr r1, =CFG_ICMR_VAL
+ ldr r2, =ICMR
+ str r1, [r2]
+
+ @ ********************************************************************
+ @ Disable the peripheral clocks, and set the core clock
+ @
+
+ @ Turn Off ALL on-chip peripheral clocks for re-configuration
+ @
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+ @ set core clocks
+ @
+ ldr r2, =CFG_CCCR_VAL
+ ldr r1, =CCCR
+ str r2, [r1]
+
+#ifdef ENABLE32KHZ
+ @ enable the 32Khz oscillator for RTC and PowerManager
+ @
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ @ NOTE: spin here until OSCC.OOK get set,
+ @ meaning the PLL has settled.
+ @
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+#endif
+
+ @ Turn on needed clocks
+ @
+ ldr r1, =CKEN
+ ldr r2, =CFG_CKEN_VAL
+ str r2, [r1]
+
+ /*SET_LED 7 */
+
+/* Is this needed???? */
+#define NODEBUG
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
+#endif
+
+ /*SET_LED 8 */
+
+ mov pc, r10
+
+@ End lowlevel_init
+++ /dev/null
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CFG_DRAM_SIZE
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-/*
- .macro SET_LED val
- ldr r6, =CRADLE_LED_CLR_REG
- ldr r7, =0
- str r7, [r6]
- ldr r6, =CRADLE_LED_SET_REG
- ldr r7, =\val
- str r7, [r6]
- .endm
-*/
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
- /* Set up GPIO pins first */
-
- ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GRER0
- ldr r1, =CFG_GRER0_VAL
- str r1, [r0]
-
- ldr r0, =GRER1
- ldr r1, =CFG_GRER1_VAL
- str r1, [r0]
-
- ldr r0, =GRER2
- ldr r1, =CFG_GRER2_VAL
- str r1, [r0]
-
- ldr r0, =GFER0
- ldr r1, =CFG_GFER0_VAL
- str r1, [r0]
-
- ldr r0, =GFER1
- ldr r1, =CFG_GFER1_VAL
- str r1, [r0]
-
- ldr r0, =GFER2
- ldr r1, =CFG_GFER2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CFG_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CFG_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CFG_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CFG_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CFG_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CFG_GAFR2_U_VAL
- str r1, [r0]
-
- /* enable GPIO pins */
- ldr r0, =PSSR
- ldr r1, =CFG_PSSR_VAL
- str r1, [r0]
-
- /* SET_LED 1 */
-
- ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */
- ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */
- str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */
- ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */
-
-
-/*********************************************************************
- * Initlialize Memory Controller
- *
- * See PXA250 Operating System Developer's Guide
- *
- * pause for 200 uSecs- allow internal clocks to settle
- * *Note: only need this if hard reset... doing it anyway for now
- */
-
- @ Step 1
- @ ---- Wait 200 usec
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /* SET_LED 2 */
-
-mem_init:
- @ get memory controller base address
- ldr r1, =MEMC_BASE
-
-
-@****************************************************************************
-@ Step 2
-@
-
- @ Step 2a
- @ write msc0, read back to ensure data latches
- @
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
- @ write msc1
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- @ write msc2
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- @ Step 2b
- @ write mecr
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
-
- @ write mcmem0
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
-
- @ write mcmem1
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
-
- @ write mcatt0
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
-
- @ write mcatt1
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
-
- @ write mcio0
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
-
- @ write mcio1
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
-
- /*SET_LED 3 */
-
- @ Step 2c
- @ fly-by-dma is defeatured on this part
- @ write flycnfg
- @ldr r2, =CFG_FLYCNFG_VAL
- @str r2, [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
- @ Step 2d
- @ get the mdrefr settings
- ldr r3, =CFG_MDREFR_VAL
-
- @ extract DRI field (we need a valid DRI field)
- @
- ldr r2, =0xFFF
-
- @ valid DRI field in r3
- @
- and r3, r3, r2
-
- @ get the reset state of MDREFR
- @
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ clear the DRI field
- @
- bic r4, r4, r2
-
- @ insert the valid DRI field loaded above
- @
- orr r4, r4, r3
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ *Note: preserve the mdrefr value in r4 *
-
- /*SET_LED 4 */
-
-@****************************************************************************
-@ Step 3
-@
-@ NO SRAM
-
- mov pc, r10
-
-
-@****************************************************************************
-@ Step 4
-@
-
- @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
- @ clear the free-running clock bits
- @ (clear K0Free, K1Free, K2Free
- @
- bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
-
- @ set K0RUN for CPLD clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN if bank 0 installed
- @
- orr r4, r4, #0x00010000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#else
- @ Step 2d
- @ get the mdrefr settings
- ldr r4, =CFG_MDREFR_VAL
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ Step 4
-
- @ set K0RUN for FLASH clock
- @
- orr r4, r4, #0x00002000
-
- @ set K1RUN for bank DRAM 0
- @
- orr r4, r4, #0x00010000
-
- @ set K2RUN for bank PLD
- @
- orr r4, r4, #0x00040000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- @ deassert SLFRSH
- @
- bic r4, r4, #0x00400000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
-
- @ assert E1PIN
- @
- orr r4, r4, #0x00008000
-
- @ write back mdrefr
- @
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
- nop
- nop
-#endif
-
- @ Step 4d
- @ fetch platform value of mdcnfg
- @
- ldr r2, =CFG_MDCNFG_VAL
-
- @ disable all sdram banks
- @
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
- @ program banks 0/1 for bus width
- @
- bic r2, r2, #MDCNFG_DWID0 @0=32-bit
-
- @ write initial value of mdcnfg, w/o enabling sdram banks
- @
- str r2, [r1, #MDCNFG_OFFSET]
-
- @ Step 4e
- @ pause for 200 uSecs
- @
- ldr r3, =OSCR @ reset the OS Timer Count to zero
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
- /*SET_LED 5 */
-
- /* Why is this here??? */
- mov r0, #0x78 @turn everything off
- mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
-
- @ Step 4f
- @ Access memory *not yet enabled* for CBR refresh cycles (8)
- @ - CBR is generated for all banks
-
- ldr r2, =CFG_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
- @ Step 4g
- @get memory controller base address
- @
- ldr r1, =MEMC_BASE
-
- @fetch current mdcnfg value
- @
- ldr r3, [r1, #MDCNFG_OFFSET]
-
- @enable sdram bank 0 if installed (must do for any populated bank)
- @
- orr r3, r3, #MDCNFG_DE0
-
- @write back mdcnfg, enabling the sdram bank(s)
- @
- str r3, [r1, #MDCNFG_OFFSET]
-
- @ Step 4h
- @ write mdmrs
- @
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- @ Done Memory Init
-
- /*SET_LED 6 */
-
- @********************************************************************
- @ Disable (mask) all interrupts at the interrupt controller
- @
-
- @ clear the interrupt level register (use IRQ, not FIQ)
- @
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
- @ Set interrupt mask register
- @
- ldr r1, =CFG_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
- @ ********************************************************************
- @ Disable the peripheral clocks, and set the core clock
- @
-
- @ Turn Off ALL on-chip peripheral clocks for re-configuration
- @
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
- @ set core clocks
- @
- ldr r2, =CFG_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef ENABLE32KHZ
- @ enable the 32Khz oscillator for RTC and PowerManager
- @
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- @ NOTE: spin here until OSCC.OOK get set,
- @ meaning the PLL has settled.
- @
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
- @ Turn on needed clocks
- @
- ldr r1, =CKEN
- ldr r2, =CFG_CKEN_VAL
- str r2, [r1]
-
- /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /*SET_LED 8 */
-
- mov pc, r10
-
-@ End memsetup
LIB = lib$(BOARD).a
OBJS := xsengine.o flash.o
-SOBJS := memsetup.o
+SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+/* ---- GPIO INITIALISATION ---- */
+/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
+
+ /* General purpose set registers */
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ /* General purpose clear registers */
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ /* General rising edge registers */
+ ldr r0, =GRER0
+ ldr r1, =CFG_GRER0_VAL
+ str r1, [r0]
+ ldr r0, =GRER1
+ ldr r1, =CFG_GRER1_VAL
+ str r1, [r0]
+ ldr r0, =GRER2
+ ldr r1, =CFG_GRER2_VAL
+ str r1, [r0]
+
+ /* General falling edge registers */
+ ldr r0, =GFER0
+ ldr r1, =CFG_GFER0_VAL
+ str r1, [r0]
+ ldr r0, =GFER1
+ ldr r1, =CFG_GFER1_VAL
+ str r1, [r0]
+ ldr r0, =GFER2
+ ldr r1, =CFG_GFER2_VAL
+ str r1, [r0]
+
+ /* General edge detect registers */
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ /* General alternate function registers */
+ ldr r0, =GAFR0_L /* [0:15] */
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+ ldr r0, =GAFR0_U /* [31:16] */
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+ ldr r0, =GAFR1_L /* [47:32] */
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+ ldr r0, =GAFR1_U /* [63:48] */
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+ ldr r0, =GAFR2_L /* [79:64] */
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+ ldr r0, =GAFR2_U /* [80] */
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ /* General purpose direction registers */
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ /* Power manager sleep status */
+ ldr r0, =PSSR
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+/* ---- MEMORY INITIALISATION ---- */
+/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
+/* pause for 200 uSecs- allow internal clocks to settle */
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+/* get memory controller base address */
+ ldr r1, =MEMC_BASE
+
+/* ---- FLASH INITIALISATION ---- */
+/* Write MSC0 and read back to ensure data change is accepted by cpu */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET]
+
+/* ---- SDRAM INITIALISATION ---- */
+/* get the MDREFR settings */
+ ldr r2, =CFG_MDREFR_VAL
+ str r2, [r1, #MDREFR_OFFSET]
+
+/* fetch platform value of MDCNFG */
+ ldr r2, =CFG_MDCNFG_VAL
+
+/* disable all sdram banks */
+ bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
+ bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
+
+/* write initial value of MDCNFG, w/o enabling sdram banks */
+ str r2, [r1, #MDCNFG_OFFSET]
+
+/* pause for 200 uSecs */
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* about 200 usec */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+/* Access memory *not yet enabled* for CBR refresh cycles (8) */
+/* CBR is generated for all banks */
+
+ ldr r2, =CFG_DRAM_BASE
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+
+/* get memory controller base address */
+ ldr r2, =MEMC_BASE
+
+/* Enable SDRAM bank 0 in MDCNFG register */
+ ldr r2, [r1, #MDCNFG_OFFSET]
+ orr r2, r2, #MDCNFG_DE0
+ str r2, [r1, #MDCNFG_OFFSET]
+
+/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+/* ---- INTERRUPT INITIALISATION ---- */
+/* Disable (mask) all interrupts at the interrupt controller */
+/* clear the interrupt level register (use IRQ, not FIQ) */
+ mov r1, #0
+ ldr r2, =ICLR
+ str r1, [r2]
+
+/* Set interrupt mask register */
+ ldr r1, =CFG_ICMR_VAL
+ ldr r2, =ICMR
+ str r1, [r2]
+
+/* ---- CLOCK INITIALISATION ---- */
+/* Disable the peripheral clocks, and set the core clock */
+
+/* Turn Off ALL on-chip peripheral clocks for re-configuration */
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+/* set core clocks */
+ ldr r2, =CFG_CCCR_VAL
+ ldr r1, =CCCR
+ str r2, [r1]
+
+#ifdef ENABLE32KHZ
+/* enable the 32Khz oscillator for RTC and PowerManager */
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+/* NOTE: spin here until OSCC.OOK get set, meaning the PLL has settled. */
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+#endif
+
+/* Turn on needed clocks */
+ ldr r1, =CKEN
+ ldr r2, =CFG_CKEN_VAL
+ str r2, [r1]
+
+ mov pc, r10
+++ /dev/null
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE: .long CFG_DRAM_SIZE
-
-.globl memsetup
-memsetup:
-
- mov r10, lr
-
-/* ---- GPIO INITIALISATION ---- */
-/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
-
- /* General purpose set registers */
- ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
- str r1, [r0]
- ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
- str r1, [r0]
- ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
- str r1, [r0]
-
- /* General purpose clear registers */
- ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
- str r1, [r0]
- ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
- str r1, [r0]
- ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
- str r1, [r0]
-
- /* General rising edge registers */
- ldr r0, =GRER0
- ldr r1, =CFG_GRER0_VAL
- str r1, [r0]
- ldr r0, =GRER1
- ldr r1, =CFG_GRER1_VAL
- str r1, [r0]
- ldr r0, =GRER2
- ldr r1, =CFG_GRER2_VAL
- str r1, [r0]
-
- /* General falling edge registers */
- ldr r0, =GFER0
- ldr r1, =CFG_GFER0_VAL
- str r1, [r0]
- ldr r0, =GFER1
- ldr r1, =CFG_GFER1_VAL
- str r1, [r0]
- ldr r0, =GFER2
- ldr r1, =CFG_GFER2_VAL
- str r1, [r0]
-
- /* General edge detect registers */
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- /* General alternate function registers */
- ldr r0, =GAFR0_L /* [0:15] */
- ldr r1, =CFG_GAFR0_L_VAL
- str r1, [r0]
- ldr r0, =GAFR0_U /* [31:16] */
- ldr r1, =CFG_GAFR0_U_VAL
- str r1, [r0]
- ldr r0, =GAFR1_L /* [47:32] */
- ldr r1, =CFG_GAFR1_L_VAL
- str r1, [r0]
- ldr r0, =GAFR1_U /* [63:48] */
- ldr r1, =CFG_GAFR1_U_VAL
- str r1, [r0]
- ldr r0, =GAFR2_L /* [79:64] */
- ldr r1, =CFG_GAFR2_L_VAL
- str r1, [r0]
- ldr r0, =GAFR2_U /* [80] */
- ldr r1, =CFG_GAFR2_U_VAL
- str r1, [r0]
-
- /* General purpose direction registers */
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- /* Power manager sleep status */
- ldr r0, =PSSR
- ldr r1, =CFG_PSSR_VAL
- str r1, [r0]
-
-/* ---- MEMORY INITIALISATION ---- */
-/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
-/* pause for 200 uSecs- allow internal clocks to settle */
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-/* get memory controller base address */
- ldr r1, =MEMC_BASE
-
-/* ---- FLASH INITIALISATION ---- */
-/* Write MSC0 and read back to ensure data change is accepted by cpu */
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET]
-
-/* ---- SDRAM INITIALISATION ---- */
-/* get the MDREFR settings */
- ldr r2, =CFG_MDREFR_VAL
- str r2, [r1, #MDREFR_OFFSET]
-
-/* fetch platform value of MDCNFG */
- ldr r2, =CFG_MDCNFG_VAL
-
-/* disable all sdram banks */
- bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
- bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
-
-/* write initial value of MDCNFG, w/o enabling sdram banks */
- str r2, [r1, #MDCNFG_OFFSET]
-
-/* pause for 200 uSecs */
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* about 200 usec */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-/* Access memory *not yet enabled* for CBR refresh cycles (8) */
-/* CBR is generated for all banks */
-
- ldr r2, =CFG_DRAM_BASE
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
- str r2, [r2]
-
-/* get memory controller base address */
- ldr r2, =MEMC_BASE
-
-/* Enable SDRAM bank 0 in MDCNFG register */
- ldr r2, [r1, #MDCNFG_OFFSET]
- orr r2, r2, #MDCNFG_DE0
- str r2, [r1, #MDCNFG_OFFSET]
-
-/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
-/* ---- INTERRUPT INITIALISATION ---- */
-/* Disable (mask) all interrupts at the interrupt controller */
-/* clear the interrupt level register (use IRQ, not FIQ) */
- mov r1, #0
- ldr r2, =ICLR
- str r1, [r2]
-
-/* Set interrupt mask register */
- ldr r1, =CFG_ICMR_VAL
- ldr r2, =ICMR
- str r1, [r2]
-
-/* ---- CLOCK INITIALISATION ---- */
-/* Disable the peripheral clocks, and set the core clock */
-
-/* Turn Off ALL on-chip peripheral clocks for re-configuration */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
-
-/* set core clocks */
- ldr r2, =CFG_CCCR_VAL
- ldr r1, =CCCR
- str r2, [r1]
-
-#ifdef ENABLE32KHZ
-/* enable the 32Khz oscillator for RTC and PowerManager */
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
-/* NOTE: spin here until OSCC.OOK get set, meaning the PLL has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#endif
-
-/* Turn on needed clocks */
- ldr r1, =CKEN
- ldr r2, =CFG_CKEN_VAL
- str r2, [r1]
-
- mov pc, r10
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependent, you will
- * find a memsetup.S in your board directory.
+ * find a lowlevel_init.S in your board directory.
*/
mov ip, lr
- bl memsetup
+ bl lowlevel_init
mov lr, ip
mov pc, lr
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
- * find a memsetup.S in your board directory.
+ * find a lowlevel_init.S in your board directory.
*/
mov ip, lr
- bl memsetup
+ bl lowlevel_init
mov lr, ip
mov pc, lr
#include <config.h>
#include <version.h>
-#ifdef CONFIG_BOOTBINFUNC
+#ifdef CONFIG_INIT_CRITICAL
/*
* some parameters for the board
*
.word SDRAM
.word SDRAM_VAL
/* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_BOOTBINFUNC */
+#endif /* CONFIG_INIT_CRITICAL */
orr r0,r0,#0xd3 /* was 13 */
msr cpsr,r0
-#ifdef CONFIG_BOOTBINFUNC
+#ifdef CONFIG_INIT_CRITICAL
/* scratch stack */
ldr r1, =0x00204000
/* Insure word alignment */
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
orr r0, r0, #0xC0000000 @ set bits 31:30 (iA, nF)
mcr p15, 0, r0, c1, c0, 0 @ write r0 in cp15 control register (cp15 r1)
-#endif /* CONFIG_BOOTBINFUNC */
+#endif /* CONFIG_INIT_CRITICAL */
/*
* relocate exeception table
*/
*/
#ifdef CONFIG_INIT_CRITICAL
bl cpu_init_crit
-#endif
-#ifdef CONFIG_BOOTBINFUNC
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
-#endif /* CONFIG_BOOTBINFUNC */
+#endif /* CONFIG_INIT_CRITICAL */
/* Set up the stack */
stack_setup:
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
- * find a memsetup.S in your board directory.
+ * find a lowlevel_init.S in your board directory.
*/
mov ip, lr
- bl memsetup
+ bl lowlevel_init
mov lr, ip
mov pc, lr
/* Initialize any external memory.
*/
- bal memsetup
+ bal lowlevel_init
nop
/* Initialize caches...
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
- * find a memsetup.S in your board directory.
+ * find a lowlevel_init.S in your board directory.
*/
mov ip, lr
- bl memsetup
+ bl lowlevel_init
mov lr, ip
/* Memory interfaces are working. Disable MMU and enable I-cache. */
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
- * find a memsetup.S in your board directory.
+ * find a lowlevel_init.S in your board directory.
*/
- bl memsetup
+ bl lowlevel_init
#endif
relocate: /* relocate U-Boot to RAM */
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
- * find a memsetup.S in your board directory.
+ * find a lowlevel_init.S in your board directory.
*/
mov ip, lr
- bl memsetup
+ bl lowlevel_init
mov lr, ip
/*
cpu/arm720t/serial_netarm.c .. serial I/O for the cpu
-board/modnet50/memsetup.S .. memory setup for ModNET50
+board/modnet50/lowlevel_init.S .. memory setup for ModNET50
board/modnet50/flash.c .. flash routines
board/modnet50/modnet50.c .. some board init stuff
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
-/* define this to include the functionality of boot.bin in u-boot */
-#undef CONFIG_BOOTBINFUNC
-
-#ifdef CONFIG_BOOTBINFUNC
+#ifdef CONFIG_INIT_CRITICAL
#define CFG_USE_MAIN_OSCILLATOR 1
/* flash */
#define MC_PUIA_VAL 0x00000000
#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-#endif
+#endif /* CONFIG_INIT_CRITICAL */
/*
* Size of malloc() pool
*/
#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
#else
#define CFG_ENV_IS_IN_FLASH 1
-#ifdef CONFIG_BOOTBINFUNC
+#ifdef CONFIG_INIT_CRITICAL
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */
#else
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
-#endif
-#endif
+#endif /* CONFIG_INIT_CRITICAL */
+#endif /* CFG_ENV_IS_IN_DATAFLASH */
#define CFG_LOAD_ADDR 0x21000000 /* default load address */
-#ifdef CONFIG_BOOTBINFUNC
+#ifdef CONFIG_INIT_CRITICAL
#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
#define CFG_U_BOOT_BASE PHYS_FLASH_1
#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */
#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
-#endif
+#endif /* CONFIG_INIT_CRITICAL */
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 207360000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
-/* define this to include the functionality of boot.bin in u-boot */
-#define CONFIG_BOOTBINFUNC
-
-/* just to make sure */
-#ifndef CONFIG_BOOTBINFUNC
-#define CONFIG_BOOTBINFUNC
-#endif
-
-#ifdef CONFIG_BOOTBINFUNC
+#ifdef CONFIG_INIT_CRITICAL
#define CFG_USE_MAIN_OSCILLATOR 1
/* flash */
#define MC_PUIA_VAL 0x00000000
#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-#endif
+#endif /* CONFIG_INIT_CRITICAL */
/*
* Size of malloc() pool
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
#else
#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
#define CFG_MDMRS_VAL 0x00000000
-#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in memsetup.S */
+#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */
#endif
/*
* If we are developing, we might want to start U-Boot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
-#undef CONFIG_INIT_CRITICAL /* undef for developing */
+#undef CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* Also swap the flash1 and flash2 addresses during debug.
*
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* e.g. bootp/tftp download of the kernel is a far more convenient
* when testing new kernels on this target. However the ADS GCPlus Linux
* boot ROM leaves the MMU enabled when it passes control to U-Boot. So
- * we use memsetup (CONFIG_INIT_CRITICAL) to remedy that problem.
+ * we use lowlevel_init (CONFIG_INIT_CRITICAL) to remedy that problem.
*/
#define CONFIG_INIT_CRITICAL
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start U-Boot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start U-Boot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
#undef CONFIG_USE_IRQ
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
#undef CONFIG_USE_IRQ
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start u-boot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-
-#define CONFIG_INIT_CRITICAL /*undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
#define CFG_MDCNFG_VAL 0x00000aC9 /* Memory timings for the SDRAM.
tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */
-#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual
- bits set in memsetup.S */
+#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual */
+ /* bits set in lowlevel_init.S */
#define CFG_MDMRS_VAL 0x00000000
/*
* bring us to live
*/
#define CONFIG_INFERNO /* we are using the inferno bootldr */
-#undef CONFIG_INIT_CRITICAL /* undef for developing */
+#undef CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
#define CONFIG_PXA250 1 /* this is an PXA250 CPU */
#define CONFIG_WEPEP250 1 /* config for wepep250 board */
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
#undef CONFIG_INIT_CRITICAL
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/*
* High Level Configuration Options
#define CFG_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */
#define CFG_MDCNFG_VAL 0x000009c9
#define CFG_MDMRS_VAL 0x00220022
-#define CFG_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in memsetup.S */
+#define CFG_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */
/*
* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
-#define CONFIG_INIT_CRITICAL /* undef for developing */
+#define CONFIG_INIT_CRITICAL
/* High Level Configuration Options */
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
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